2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-timer.h"
33 #if defined(DEBUG_NVRAM)
34 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
36 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
40 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
41 * alarm and a watchdog timer and related control registers. In the
42 * PPC platform there is also a nvram lock function.
47 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
48 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
49 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
53 /* Model parameters */
54 uint32_t type
; // 2 = m48t02, 8 = m48t08, 59 = m48t59
55 /* Hardware parameters */
62 /* Alarm & watchdog */
64 struct QEMUTimer
*alrm_timer
;
65 struct QEMUTimer
*wd_timer
;
72 typedef struct M48t59ISAState
{
77 typedef struct M48t59SysBusState
{
82 /* Fake timer functions */
83 /* Generic helpers for BCD */
84 static inline uint8_t toBCD (uint8_t value
)
86 return (((value
/ 10) % 10) << 4) | (value
% 10);
89 static inline uint8_t fromBCD (uint8_t BCD
)
91 return ((BCD
>> 4) * 10) + (BCD
& 0x0F);
94 /* Alarm management */
95 static void alarm_cb (void *opaque
)
99 m48t59_t
*NVRAM
= opaque
;
101 qemu_set_irq(NVRAM
->IRQ
, 1);
102 if ((NVRAM
->buffer
[0x1FF5] & 0x80) == 0 &&
103 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
104 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
105 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
106 /* Repeat once a month */
107 qemu_get_timedate(&tm
, NVRAM
->time_offset
);
109 if (tm
.tm_mon
== 13) {
113 next_time
= qemu_timedate_diff(&tm
) - NVRAM
->time_offset
;
114 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
115 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
116 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
117 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
118 /* Repeat once a day */
119 next_time
= 24 * 60 * 60;
120 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
121 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
122 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
123 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
124 /* Repeat once an hour */
126 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
127 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
128 (NVRAM
->buffer
[0x1FF3] & 0x80) != 0 &&
129 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
130 /* Repeat once a minute */
133 /* Repeat once a second */
136 qemu_mod_timer(NVRAM
->alrm_timer
, qemu_get_clock(vm_clock
) +
138 qemu_set_irq(NVRAM
->IRQ
, 0);
141 static void set_alarm (m48t59_t
*NVRAM
)
144 if (NVRAM
->alrm_timer
!= NULL
) {
145 qemu_del_timer(NVRAM
->alrm_timer
);
146 diff
= qemu_timedate_diff(&NVRAM
->alarm
) - NVRAM
->time_offset
;
148 qemu_mod_timer(NVRAM
->alrm_timer
, diff
* 1000);
152 /* RTC management helpers */
153 static inline void get_time (m48t59_t
*NVRAM
, struct tm
*tm
)
155 qemu_get_timedate(tm
, NVRAM
->time_offset
);
158 static void set_time (m48t59_t
*NVRAM
, struct tm
*tm
)
160 NVRAM
->time_offset
= qemu_timedate_diff(tm
);
164 /* Watchdog management */
165 static void watchdog_cb (void *opaque
)
167 m48t59_t
*NVRAM
= opaque
;
169 NVRAM
->buffer
[0x1FF0] |= 0x80;
170 if (NVRAM
->buffer
[0x1FF7] & 0x80) {
171 NVRAM
->buffer
[0x1FF7] = 0x00;
172 NVRAM
->buffer
[0x1FFC] &= ~0x40;
173 /* May it be a hw CPU Reset instead ? */
174 qemu_system_reset_request();
176 qemu_set_irq(NVRAM
->IRQ
, 1);
177 qemu_set_irq(NVRAM
->IRQ
, 0);
181 static void set_up_watchdog (m48t59_t
*NVRAM
, uint8_t value
)
183 uint64_t interval
; /* in 1/16 seconds */
185 NVRAM
->buffer
[0x1FF0] &= ~0x80;
186 if (NVRAM
->wd_timer
!= NULL
) {
187 qemu_del_timer(NVRAM
->wd_timer
);
189 interval
= (1 << (2 * (value
& 0x03))) * ((value
>> 2) & 0x1F);
190 qemu_mod_timer(NVRAM
->wd_timer
, ((uint64_t)time(NULL
) * 1000) +
191 ((interval
* 1000) >> 4));
196 /* Direct access to NVRAM */
197 void m48t59_write (void *opaque
, uint32_t addr
, uint32_t val
)
199 m48t59_t
*NVRAM
= opaque
;
203 if (addr
> 0x1FF8 && addr
< 0x2000)
204 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, addr
, val
);
206 /* check for NVRAM access */
207 if ((NVRAM
->type
== 2 && addr
< 0x7f8) ||
208 (NVRAM
->type
== 8 && addr
< 0x1ff8) ||
209 (NVRAM
->type
== 59 && addr
< 0x1ff0))
215 /* flags register : read-only */
222 tmp
= fromBCD(val
& 0x7F);
223 if (tmp
>= 0 && tmp
<= 59) {
224 NVRAM
->alarm
.tm_sec
= tmp
;
225 NVRAM
->buffer
[0x1FF2] = val
;
231 tmp
= fromBCD(val
& 0x7F);
232 if (tmp
>= 0 && tmp
<= 59) {
233 NVRAM
->alarm
.tm_min
= tmp
;
234 NVRAM
->buffer
[0x1FF3] = val
;
240 tmp
= fromBCD(val
& 0x3F);
241 if (tmp
>= 0 && tmp
<= 23) {
242 NVRAM
->alarm
.tm_hour
= tmp
;
243 NVRAM
->buffer
[0x1FF4] = val
;
249 tmp
= fromBCD(val
& 0x1F);
251 NVRAM
->alarm
.tm_mday
= tmp
;
252 NVRAM
->buffer
[0x1FF5] = val
;
258 NVRAM
->buffer
[0x1FF6] = val
;
262 NVRAM
->buffer
[0x1FF7] = val
;
263 set_up_watchdog(NVRAM
, val
);
268 NVRAM
->buffer
[addr
] = (val
& ~0xA0) | 0x90;
273 tmp
= fromBCD(val
& 0x7F);
274 if (tmp
>= 0 && tmp
<= 59) {
275 get_time(NVRAM
, &tm
);
277 set_time(NVRAM
, &tm
);
279 if ((val
& 0x80) ^ (NVRAM
->buffer
[addr
] & 0x80)) {
281 NVRAM
->stop_time
= time(NULL
);
283 NVRAM
->time_offset
+= NVRAM
->stop_time
- time(NULL
);
284 NVRAM
->stop_time
= 0;
287 NVRAM
->buffer
[addr
] = val
& 0x80;
292 tmp
= fromBCD(val
& 0x7F);
293 if (tmp
>= 0 && tmp
<= 59) {
294 get_time(NVRAM
, &tm
);
296 set_time(NVRAM
, &tm
);
302 tmp
= fromBCD(val
& 0x3F);
303 if (tmp
>= 0 && tmp
<= 23) {
304 get_time(NVRAM
, &tm
);
306 set_time(NVRAM
, &tm
);
311 /* day of the week / century */
312 tmp
= fromBCD(val
& 0x07);
313 get_time(NVRAM
, &tm
);
315 set_time(NVRAM
, &tm
);
316 NVRAM
->buffer
[addr
] = val
& 0x40;
321 tmp
= fromBCD(val
& 0x1F);
323 get_time(NVRAM
, &tm
);
325 set_time(NVRAM
, &tm
);
331 tmp
= fromBCD(val
& 0x1F);
332 if (tmp
>= 1 && tmp
<= 12) {
333 get_time(NVRAM
, &tm
);
335 set_time(NVRAM
, &tm
);
342 if (tmp
>= 0 && tmp
<= 99) {
343 get_time(NVRAM
, &tm
);
344 if (NVRAM
->type
== 8)
345 tm
.tm_year
= fromBCD(val
) + 68; // Base year is 1968
347 tm
.tm_year
= fromBCD(val
);
348 set_time(NVRAM
, &tm
);
352 /* Check lock registers state */
353 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
355 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
358 if (addr
< NVRAM
->size
) {
359 NVRAM
->buffer
[addr
] = val
& 0xFF;
365 uint32_t m48t59_read (void *opaque
, uint32_t addr
)
367 m48t59_t
*NVRAM
= opaque
;
369 uint32_t retval
= 0xFF;
371 /* check for NVRAM access */
372 if ((NVRAM
->type
== 2 && addr
< 0x078f) ||
373 (NVRAM
->type
== 8 && addr
< 0x1ff8) ||
374 (NVRAM
->type
== 59 && addr
< 0x1ff0))
402 /* A read resets the watchdog */
403 set_up_watchdog(NVRAM
, NVRAM
->buffer
[0x1FF7]);
412 get_time(NVRAM
, &tm
);
413 retval
= (NVRAM
->buffer
[addr
] & 0x80) | toBCD(tm
.tm_sec
);
418 get_time(NVRAM
, &tm
);
419 retval
= toBCD(tm
.tm_min
);
424 get_time(NVRAM
, &tm
);
425 retval
= toBCD(tm
.tm_hour
);
429 /* day of the week / century */
430 get_time(NVRAM
, &tm
);
431 retval
= NVRAM
->buffer
[addr
] | tm
.tm_wday
;
436 get_time(NVRAM
, &tm
);
437 retval
= toBCD(tm
.tm_mday
);
442 get_time(NVRAM
, &tm
);
443 retval
= toBCD(tm
.tm_mon
+ 1);
448 get_time(NVRAM
, &tm
);
449 if (NVRAM
->type
== 8)
450 retval
= toBCD(tm
.tm_year
- 68); // Base year is 1968
452 retval
= toBCD(tm
.tm_year
);
455 /* Check lock registers state */
456 if (addr
>= 0x20 && addr
<= 0x2F && (NVRAM
->lock
& 1))
458 if (addr
>= 0x30 && addr
<= 0x3F && (NVRAM
->lock
& 2))
461 if (addr
< NVRAM
->size
) {
462 retval
= NVRAM
->buffer
[addr
];
466 if (addr
> 0x1FF9 && addr
< 0x2000)
467 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, retval
);
472 void m48t59_set_addr (void *opaque
, uint32_t addr
)
474 m48t59_t
*NVRAM
= opaque
;
479 void m48t59_toggle_lock (void *opaque
, int lock
)
481 m48t59_t
*NVRAM
= opaque
;
483 NVRAM
->lock
^= 1 << lock
;
486 /* IO access to NVRAM */
487 static void NVRAM_writeb (void *opaque
, uint32_t addr
, uint32_t val
)
489 m48t59_t
*NVRAM
= opaque
;
491 addr
-= NVRAM
->io_base
;
492 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, addr
, val
);
495 NVRAM
->addr
&= ~0x00FF;
499 NVRAM
->addr
&= ~0xFF00;
500 NVRAM
->addr
|= val
<< 8;
503 m48t59_write(NVRAM
, val
, NVRAM
->addr
);
504 NVRAM
->addr
= 0x0000;
511 static uint32_t NVRAM_readb (void *opaque
, uint32_t addr
)
513 m48t59_t
*NVRAM
= opaque
;
516 addr
-= NVRAM
->io_base
;
519 retval
= m48t59_read(NVRAM
, NVRAM
->addr
);
525 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, retval
);
530 static void nvram_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
532 m48t59_t
*NVRAM
= opaque
;
534 m48t59_write(NVRAM
, addr
, value
& 0xff);
537 static void nvram_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
539 m48t59_t
*NVRAM
= opaque
;
541 m48t59_write(NVRAM
, addr
, (value
>> 8) & 0xff);
542 m48t59_write(NVRAM
, addr
+ 1, value
& 0xff);
545 static void nvram_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
547 m48t59_t
*NVRAM
= opaque
;
549 m48t59_write(NVRAM
, addr
, (value
>> 24) & 0xff);
550 m48t59_write(NVRAM
, addr
+ 1, (value
>> 16) & 0xff);
551 m48t59_write(NVRAM
, addr
+ 2, (value
>> 8) & 0xff);
552 m48t59_write(NVRAM
, addr
+ 3, value
& 0xff);
555 static uint32_t nvram_readb (void *opaque
, target_phys_addr_t addr
)
557 m48t59_t
*NVRAM
= opaque
;
560 retval
= m48t59_read(NVRAM
, addr
);
564 static uint32_t nvram_readw (void *opaque
, target_phys_addr_t addr
)
566 m48t59_t
*NVRAM
= opaque
;
569 retval
= m48t59_read(NVRAM
, addr
) << 8;
570 retval
|= m48t59_read(NVRAM
, addr
+ 1);
574 static uint32_t nvram_readl (void *opaque
, target_phys_addr_t addr
)
576 m48t59_t
*NVRAM
= opaque
;
579 retval
= m48t59_read(NVRAM
, addr
) << 24;
580 retval
|= m48t59_read(NVRAM
, addr
+ 1) << 16;
581 retval
|= m48t59_read(NVRAM
, addr
+ 2) << 8;
582 retval
|= m48t59_read(NVRAM
, addr
+ 3);
586 static CPUWriteMemoryFunc
* const nvram_write
[] = {
592 static CPUReadMemoryFunc
* const nvram_read
[] = {
598 static void m48t59_save(QEMUFile
*f
, void *opaque
)
600 m48t59_t
*s
= opaque
;
602 qemu_put_8s(f
, &s
->lock
);
603 qemu_put_be16s(f
, &s
->addr
);
604 qemu_put_buffer(f
, s
->buffer
, s
->size
);
607 static int m48t59_load(QEMUFile
*f
, void *opaque
, int version_id
)
609 m48t59_t
*s
= opaque
;
614 qemu_get_8s(f
, &s
->lock
);
615 qemu_get_be16s(f
, &s
->addr
);
616 qemu_get_buffer(f
, s
->buffer
, s
->size
);
621 static void m48t59_reset_common(m48t59_t
*NVRAM
)
625 if (NVRAM
->alrm_timer
!= NULL
)
626 qemu_del_timer(NVRAM
->alrm_timer
);
628 if (NVRAM
->wd_timer
!= NULL
)
629 qemu_del_timer(NVRAM
->wd_timer
);
632 static void m48t59_reset_isa(DeviceState
*d
)
634 M48t59ISAState
*isa
= container_of(d
, M48t59ISAState
, busdev
.qdev
);
635 m48t59_t
*NVRAM
= &isa
->state
;
637 m48t59_reset_common(NVRAM
);
640 static void m48t59_reset_sysbus(DeviceState
*d
)
642 M48t59SysBusState
*sys
= container_of(d
, M48t59SysBusState
, busdev
.qdev
);
643 m48t59_t
*NVRAM
= &sys
->state
;
645 m48t59_reset_common(NVRAM
);
648 /* Initialisation routine */
649 m48t59_t
*m48t59_init (qemu_irq IRQ
, target_phys_addr_t mem_base
,
650 uint32_t io_base
, uint16_t size
,
655 M48t59SysBusState
*d
;
657 dev
= qdev_create(NULL
, "m48t59");
658 qdev_prop_set_uint32(dev
, "type", type
);
659 qdev_prop_set_uint32(dev
, "size", size
);
660 qdev_prop_set_uint32(dev
, "io_base", io_base
);
661 qdev_init_nofail(dev
);
662 s
= sysbus_from_qdev(dev
);
663 sysbus_connect_irq(s
, 0, IRQ
);
665 register_ioport_read(io_base
, 0x04, 1, NVRAM_readb
, s
);
666 register_ioport_write(io_base
, 0x04, 1, NVRAM_writeb
, s
);
669 sysbus_mmio_map(s
, 0, mem_base
);
672 d
= FROM_SYSBUS(M48t59SysBusState
, s
);
677 m48t59_t
*m48t59_init_isa(uint32_t io_base
, uint16_t size
, int type
)
683 dev
= isa_create("m48t59_isa");
684 qdev_prop_set_uint32(&dev
->qdev
, "type", type
);
685 qdev_prop_set_uint32(&dev
->qdev
, "size", size
);
686 qdev_prop_set_uint32(&dev
->qdev
, "io_base", io_base
);
687 qdev_init_nofail(&dev
->qdev
);
688 d
= DO_UPCAST(M48t59ISAState
, busdev
, dev
);
692 register_ioport_read(io_base
, 0x04, 1, NVRAM_readb
, s
);
693 register_ioport_write(io_base
, 0x04, 1, NVRAM_writeb
, s
);
699 static void m48t59_init_common(m48t59_t
*s
)
701 s
->buffer
= qemu_mallocz(s
->size
);
703 s
->alrm_timer
= qemu_new_timer(vm_clock
, &alarm_cb
, s
);
704 s
->wd_timer
= qemu_new_timer(vm_clock
, &watchdog_cb
, s
);
706 qemu_get_timedate(&s
->alarm
, 0);
708 register_savevm("m48t59", -1, 1, m48t59_save
, m48t59_load
, s
);
711 static int m48t59_init_isa1(ISADevice
*dev
)
713 M48t59ISAState
*d
= DO_UPCAST(M48t59ISAState
, busdev
, dev
);
714 m48t59_t
*s
= &d
->state
;
716 isa_init_irq(dev
, &s
->IRQ
, 8);
717 m48t59_init_common(s
);
722 static int m48t59_init1(SysBusDevice
*dev
)
724 M48t59SysBusState
*d
= FROM_SYSBUS(M48t59SysBusState
, dev
);
725 m48t59_t
*s
= &d
->state
;
728 sysbus_init_irq(dev
, &s
->IRQ
);
730 mem_index
= cpu_register_io_memory(nvram_read
, nvram_write
, s
);
731 sysbus_init_mmio(dev
, s
->size
, mem_index
);
732 m48t59_init_common(s
);
737 static ISADeviceInfo m48t59_isa_info
= {
738 .init
= m48t59_init_isa1
,
739 .qdev
.name
= "m48t59_isa",
740 .qdev
.size
= sizeof(M48t59ISAState
),
741 .qdev
.reset
= m48t59_reset_isa
,
743 .qdev
.props
= (Property
[]) {
744 DEFINE_PROP_UINT32("size", M48t59ISAState
, state
.size
, -1),
745 DEFINE_PROP_UINT32("type", M48t59ISAState
, state
.type
, -1),
746 DEFINE_PROP_HEX32( "io_base", M48t59ISAState
, state
.io_base
, 0),
747 DEFINE_PROP_END_OF_LIST(),
751 static SysBusDeviceInfo m48t59_info
= {
752 .init
= m48t59_init1
,
753 .qdev
.name
= "m48t59",
754 .qdev
.size
= sizeof(M48t59SysBusState
),
755 .qdev
.reset
= m48t59_reset_sysbus
,
756 .qdev
.props
= (Property
[]) {
757 DEFINE_PROP_UINT32("size", M48t59SysBusState
, state
.size
, -1),
758 DEFINE_PROP_UINT32("type", M48t59SysBusState
, state
.type
, -1),
759 DEFINE_PROP_HEX32( "io_base", M48t59SysBusState
, state
.io_base
, 0),
760 DEFINE_PROP_END_OF_LIST(),
764 static void m48t59_register_devices(void)
766 sysbus_register_withprop(&m48t59_info
);
767 isa_qdev_register(&m48t59_isa_info
);
770 device_init(m48t59_register_devices
)