hw/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "qemu-timer.h"
  27 #include "sysemu.h"
  28 #include "sysbus.h"
  29 #include "isa.h"
  30
  31 //#define DEBUG_NVRAM
  32
  33 #if defined(DEBUG_NVRAM)
  34 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  37 #endif
  38
  39 /*
  40  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  41  * alarm and a watchdog timer and related control registers. In the
  42  * PPC platform there is also a nvram lock function.
  43  */
  44
  45 /*
  46  * Chipset docs:
  47  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  48  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  49  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  50  */
  51
  52 struct m48t59_t {
  53     /* Model parameters */
  54     uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
  55     /* Hardware parameters */
  56     qemu_irq IRQ;
  57     uint32_t io_base;
  58     uint32_t size;
  59     /* RTC management */
  60     time_t   time_offset;
  61     time_t   stop_time;
  62     /* Alarm & watchdog */
  63     struct tm alarm;
  64     struct QEMUTimer *alrm_timer;
  65     struct QEMUTimer *wd_timer;
  66     /* NVRAM storage */
  67     uint8_t  lock;
  68     uint16_t addr;
  69     uint8_t *buffer;
  70 };
  71
  72 typedef struct M48t59ISAState {
  73     ISADevice busdev;
  74     m48t59_t state;
  75 } M48t59ISAState;
  76
  77 typedef struct M48t59SysBusState {
  78     SysBusDevice busdev;
  79     m48t59_t state;
  80 } M48t59SysBusState;
  81
  82 /* Fake timer functions */
  83 /* Generic helpers for BCD */
  84 static inline uint8_t toBCD (uint8_t value)
  85 {
  86     return (((value / 10) % 10) << 4) | (value % 10);
  87 }
  88
  89 static inline uint8_t fromBCD (uint8_t BCD)
  90 {
  91     return ((BCD >> 4) * 10) + (BCD & 0x0F);
  92 }
  93
  94 /* Alarm management */
  95 static void alarm_cb (void *opaque)
  96 {
  97     struct tm tm;
  98     uint64_t next_time;
  99     m48t59_t *NVRAM = opaque;
 100
 101     qemu_set_irq(NVRAM->IRQ, 1);
 102     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
 103         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 104         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 105         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 106         /* Repeat once a month */
 107         qemu_get_timedate(&tm, NVRAM->time_offset);
 108         tm.tm_mon++;
 109         if (tm.tm_mon == 13) {
 110             tm.tm_mon = 1;
 111             tm.tm_year++;
 112         }
 113         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 114     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 115                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 116                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 117                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 118         /* Repeat once a day */
 119         next_time = 24 * 60 * 60;
 120     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 121                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 122                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 123                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 124         /* Repeat once an hour */
 125         next_time = 60 * 60;
 126     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 127                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 128                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 129                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 130         /* Repeat once a minute */
 131         next_time = 60;
 132     } else {
 133         /* Repeat once a second */
 134         next_time = 1;
 135     }
 136     qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
 137                     next_time * 1000);
 138     qemu_set_irq(NVRAM->IRQ, 0);
 139 }
 140
 141 static void set_alarm (m48t59_t *NVRAM)
 142 {
 143     int diff;
 144     if (NVRAM->alrm_timer != NULL) {
 145         qemu_del_timer(NVRAM->alrm_timer);
 146         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 147         if (diff > 0)
 148             qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
 149     }
 150 }
 151
 152 /* RTC management helpers */
 153 static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
 154 {
 155     qemu_get_timedate(tm, NVRAM->time_offset);
 156 }
 157
 158 static void set_time (m48t59_t *NVRAM, struct tm *tm)
 159 {
 160     NVRAM->time_offset = qemu_timedate_diff(tm);
 161     set_alarm(NVRAM);
 162 }
 163
 164 /* Watchdog management */
 165 static void watchdog_cb (void *opaque)
 166 {
 167     m48t59_t *NVRAM = opaque;
 168
 169     NVRAM->buffer[0x1FF0] |= 0x80;
 170     if (NVRAM->buffer[0x1FF7] & 0x80) {
 171         NVRAM->buffer[0x1FF7] = 0x00;
 172         NVRAM->buffer[0x1FFC] &= ~0x40;
 173         /* May it be a hw CPU Reset instead ? */
 174         qemu_system_reset_request();
 175     } else {
 176         qemu_set_irq(NVRAM->IRQ, 1);
 177         qemu_set_irq(NVRAM->IRQ, 0);
 178     }
 179 }
 180
 181 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
 182 {
 183     uint64_t interval; /* in 1/16 seconds */
 184
 185     NVRAM->buffer[0x1FF0] &= ~0x80;
 186     if (NVRAM->wd_timer != NULL) {
 187         qemu_del_timer(NVRAM->wd_timer);
 188         if (value != 0) {
 189             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 190             qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 191                            ((interval * 1000) >> 4));
 192         }
 193     }
 194 }
 195
 196 /* Direct access to NVRAM */
 197 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
 198 {
 199     m48t59_t *NVRAM = opaque;
 200     struct tm tm;
 201     int tmp;
 202
 203     if (addr > 0x1FF8 && addr < 0x2000)
 204         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 205
 206     /* check for NVRAM access */
 207     if ((NVRAM->type == 2 && addr < 0x7f8) ||
 208         (NVRAM->type == 8 && addr < 0x1ff8) ||
 209         (NVRAM->type == 59 && addr < 0x1ff0))
 210         goto do_write;
 211
 212     /* TOD access */
 213     switch (addr) {
 214     case 0x1FF0:
 215         /* flags register : read-only */
 216         break;
 217     case 0x1FF1:
 218         /* unused */
 219         break;
 220     case 0x1FF2:
 221         /* alarm seconds */
 222         tmp = fromBCD(val & 0x7F);
 223         if (tmp >= 0 && tmp <= 59) {
 224             NVRAM->alarm.tm_sec = tmp;
 225             NVRAM->buffer[0x1FF2] = val;
 226             set_alarm(NVRAM);
 227         }
 228         break;
 229     case 0x1FF3:
 230         /* alarm minutes */
 231         tmp = fromBCD(val & 0x7F);
 232         if (tmp >= 0 && tmp <= 59) {
 233             NVRAM->alarm.tm_min = tmp;
 234             NVRAM->buffer[0x1FF3] = val;
 235             set_alarm(NVRAM);
 236         }
 237         break;
 238     case 0x1FF4:
 239         /* alarm hours */
 240         tmp = fromBCD(val & 0x3F);
 241         if (tmp >= 0 && tmp <= 23) {
 242             NVRAM->alarm.tm_hour = tmp;
 243             NVRAM->buffer[0x1FF4] = val;
 244             set_alarm(NVRAM);
 245         }
 246         break;
 247     case 0x1FF5:
 248         /* alarm date */
 249         tmp = fromBCD(val & 0x1F);
 250         if (tmp != 0) {
 251             NVRAM->alarm.tm_mday = tmp;
 252             NVRAM->buffer[0x1FF5] = val;
 253             set_alarm(NVRAM);
 254         }
 255         break;
 256     case 0x1FF6:
 257         /* interrupts */
 258         NVRAM->buffer[0x1FF6] = val;
 259         break;
 260     case 0x1FF7:
 261         /* watchdog */
 262         NVRAM->buffer[0x1FF7] = val;
 263         set_up_watchdog(NVRAM, val);
 264         break;
 265     case 0x1FF8:
 266     case 0x07F8:
 267         /* control */
 268        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 269         break;
 270     case 0x1FF9:
 271     case 0x07F9:
 272         /* seconds (BCD) */
 273         tmp = fromBCD(val & 0x7F);
 274         if (tmp >= 0 && tmp <= 59) {
 275             get_time(NVRAM, &tm);
 276             tm.tm_sec = tmp;
 277             set_time(NVRAM, &tm);
 278         }
 279         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 280             if (val & 0x80) {
 281                 NVRAM->stop_time = time(NULL);
 282             } else {
 283                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 284                 NVRAM->stop_time = 0;
 285             }
 286         }
 287         NVRAM->buffer[addr] = val & 0x80;
 288         break;
 289     case 0x1FFA:
 290     case 0x07FA:
 291         /* minutes (BCD) */
 292         tmp = fromBCD(val & 0x7F);
 293         if (tmp >= 0 && tmp <= 59) {
 294             get_time(NVRAM, &tm);
 295             tm.tm_min = tmp;
 296             set_time(NVRAM, &tm);
 297         }
 298         break;
 299     case 0x1FFB:
 300     case 0x07FB:
 301         /* hours (BCD) */
 302         tmp = fromBCD(val & 0x3F);
 303         if (tmp >= 0 && tmp <= 23) {
 304             get_time(NVRAM, &tm);
 305             tm.tm_hour = tmp;
 306             set_time(NVRAM, &tm);
 307         }
 308         break;
 309     case 0x1FFC:
 310     case 0x07FC:
 311         /* day of the week / century */
 312         tmp = fromBCD(val & 0x07);
 313         get_time(NVRAM, &tm);
 314         tm.tm_wday = tmp;
 315         set_time(NVRAM, &tm);
 316         NVRAM->buffer[addr] = val & 0x40;
 317         break;
 318     case 0x1FFD:
 319     case 0x07FD:
 320         /* date */
 321         tmp = fromBCD(val & 0x1F);
 322         if (tmp != 0) {
 323             get_time(NVRAM, &tm);
 324             tm.tm_mday = tmp;
 325             set_time(NVRAM, &tm);
 326         }
 327         break;
 328     case 0x1FFE:
 329     case 0x07FE:
 330         /* month */
 331         tmp = fromBCD(val & 0x1F);
 332         if (tmp >= 1 && tmp <= 12) {
 333             get_time(NVRAM, &tm);
 334             tm.tm_mon = tmp - 1;
 335             set_time(NVRAM, &tm);
 336         }
 337         break;
 338     case 0x1FFF:
 339     case 0x07FF:
 340         /* year */
 341         tmp = fromBCD(val);
 342         if (tmp >= 0 && tmp <= 99) {
 343             get_time(NVRAM, &tm);
 344             if (NVRAM->type == 8)
 345                 tm.tm_year = fromBCD(val) + 68; // Base year is 1968
 346             else
 347                 tm.tm_year = fromBCD(val);
 348             set_time(NVRAM, &tm);
 349         }
 350         break;
 351     default:
 352         /* Check lock registers state */
 353         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 354             break;
 355         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 356             break;
 357     do_write:
 358         if (addr < NVRAM->size) {
 359             NVRAM->buffer[addr] = val & 0xFF;
 360         }
 361         break;
 362     }
 363 }
 364
 365 uint32_t m48t59_read (void *opaque, uint32_t addr)
 366 {
 367     m48t59_t *NVRAM = opaque;
 368     struct tm tm;
 369     uint32_t retval = 0xFF;
 370
 371     /* check for NVRAM access */
 372     if ((NVRAM->type == 2 && addr < 0x078f) ||
 373         (NVRAM->type == 8 && addr < 0x1ff8) ||
 374         (NVRAM->type == 59 && addr < 0x1ff0))
 375         goto do_read;
 376
 377     /* TOD access */
 378     switch (addr) {
 379     case 0x1FF0:
 380         /* flags register */
 381         goto do_read;
 382     case 0x1FF1:
 383         /* unused */
 384         retval = 0;
 385         break;
 386     case 0x1FF2:
 387         /* alarm seconds */
 388         goto do_read;
 389     case 0x1FF3:
 390         /* alarm minutes */
 391         goto do_read;
 392     case 0x1FF4:
 393         /* alarm hours */
 394         goto do_read;
 395     case 0x1FF5:
 396         /* alarm date */
 397         goto do_read;
 398     case 0x1FF6:
 399         /* interrupts */
 400         goto do_read;
 401     case 0x1FF7:
 402         /* A read resets the watchdog */
 403         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 404         goto do_read;
 405     case 0x1FF8:
 406     case 0x07F8:
 407         /* control */
 408         goto do_read;
 409     case 0x1FF9:
 410     case 0x07F9:
 411         /* seconds (BCD) */
 412         get_time(NVRAM, &tm);
 413         retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
 414         break;
 415     case 0x1FFA:
 416     case 0x07FA:
 417         /* minutes (BCD) */
 418         get_time(NVRAM, &tm);
 419         retval = toBCD(tm.tm_min);
 420         break;
 421     case 0x1FFB:
 422     case 0x07FB:
 423         /* hours (BCD) */
 424         get_time(NVRAM, &tm);
 425         retval = toBCD(tm.tm_hour);
 426         break;
 427     case 0x1FFC:
 428     case 0x07FC:
 429         /* day of the week / century */
 430         get_time(NVRAM, &tm);
 431         retval = NVRAM->buffer[addr] | tm.tm_wday;
 432         break;
 433     case 0x1FFD:
 434     case 0x07FD:
 435         /* date */
 436         get_time(NVRAM, &tm);
 437         retval = toBCD(tm.tm_mday);
 438         break;
 439     case 0x1FFE:
 440     case 0x07FE:
 441         /* month */
 442         get_time(NVRAM, &tm);
 443         retval = toBCD(tm.tm_mon + 1);
 444         break;
 445     case 0x1FFF:
 446     case 0x07FF:
 447         /* year */
 448         get_time(NVRAM, &tm);
 449         if (NVRAM->type == 8)
 450             retval = toBCD(tm.tm_year - 68); // Base year is 1968
 451         else
 452             retval = toBCD(tm.tm_year);
 453         break;
 454     default:
 455         /* Check lock registers state */
 456         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 457             break;
 458         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 459             break;
 460     do_read:
 461         if (addr < NVRAM->size) {
 462             retval = NVRAM->buffer[addr];
 463         }
 464         break;
 465     }
 466     if (addr > 0x1FF9 && addr < 0x2000)
 467        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 468
 469     return retval;
 470 }
 471
 472 void m48t59_set_addr (void *opaque, uint32_t addr)
 473 {
 474     m48t59_t *NVRAM = opaque;
 475
 476     NVRAM->addr = addr;
 477 }
 478
 479 void m48t59_toggle_lock (void *opaque, int lock)
 480 {
 481     m48t59_t *NVRAM = opaque;
 482
 483     NVRAM->lock ^= 1 << lock;
 484 }
 485
 486 /* IO access to NVRAM */
 487 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
 488 {
 489     m48t59_t *NVRAM = opaque;
 490
 491     addr -= NVRAM->io_base;
 492     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 493     switch (addr) {
 494     case 0:
 495         NVRAM->addr &= ~0x00FF;
 496         NVRAM->addr |= val;
 497         break;
 498     case 1:
 499         NVRAM->addr &= ~0xFF00;
 500         NVRAM->addr |= val << 8;
 501         break;
 502     case 3:
 503         m48t59_write(NVRAM, val, NVRAM->addr);
 504         NVRAM->addr = 0x0000;
 505         break;
 506     default:
 507         break;
 508     }
 509 }
 510
 511 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
 512 {
 513     m48t59_t *NVRAM = opaque;
 514     uint32_t retval;
 515
 516     addr -= NVRAM->io_base;
 517     switch (addr) {
 518     case 3:
 519         retval = m48t59_read(NVRAM, NVRAM->addr);
 520         break;
 521     default:
 522         retval = -1;
 523         break;
 524     }
 525     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 526
 527     return retval;
 528 }
 529
 530 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 531 {
 532     m48t59_t *NVRAM = opaque;
 533
 534     m48t59_write(NVRAM, addr, value & 0xff);
 535 }
 536
 537 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 538 {
 539     m48t59_t *NVRAM = opaque;
 540
 541     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 542     m48t59_write(NVRAM, addr + 1, value & 0xff);
 543 }
 544
 545 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 546 {
 547     m48t59_t *NVRAM = opaque;
 548
 549     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 550     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 551     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 552     m48t59_write(NVRAM, addr + 3, value & 0xff);
 553 }
 554
 555 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
 556 {
 557     m48t59_t *NVRAM = opaque;
 558     uint32_t retval;
 559
 560     retval = m48t59_read(NVRAM, addr);
 561     return retval;
 562 }
 563
 564 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
 565 {
 566     m48t59_t *NVRAM = opaque;
 567     uint32_t retval;
 568
 569     retval = m48t59_read(NVRAM, addr) << 8;
 570     retval |= m48t59_read(NVRAM, addr + 1);
 571     return retval;
 572 }
 573
 574 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
 575 {
 576     m48t59_t *NVRAM = opaque;
 577     uint32_t retval;
 578
 579     retval = m48t59_read(NVRAM, addr) << 24;
 580     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 581     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 582     retval |= m48t59_read(NVRAM, addr + 3);
 583     return retval;
 584 }
 585
 586 static CPUWriteMemoryFunc * const nvram_write[] = {
 587     &nvram_writeb,
 588     &nvram_writew,
 589     &nvram_writel,
 590 };
 591
 592 static CPUReadMemoryFunc * const nvram_read[] = {
 593     &nvram_readb,
 594     &nvram_readw,
 595     &nvram_readl,
 596 };
 597
 598 static void m48t59_save(QEMUFile *f, void *opaque)
 599 {
 600     m48t59_t *s = opaque;
 601
 602     qemu_put_8s(f, &s->lock);
 603     qemu_put_be16s(f, &s->addr);
 604     qemu_put_buffer(f, s->buffer, s->size);
 605 }
 606
 607 static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
 608 {
 609     m48t59_t *s = opaque;
 610
 611     if (version_id != 1)
 612         return -EINVAL;
 613
 614     qemu_get_8s(f, &s->lock);
 615     qemu_get_be16s(f, &s->addr);
 616     qemu_get_buffer(f, s->buffer, s->size);
 617
 618     return 0;
 619 }
 620
 621 static void m48t59_reset_common(m48t59_t *NVRAM)
 622 {
 623     NVRAM->addr = 0;
 624     NVRAM->lock = 0;
 625     if (NVRAM->alrm_timer != NULL)
 626         qemu_del_timer(NVRAM->alrm_timer);
 627
 628     if (NVRAM->wd_timer != NULL)
 629         qemu_del_timer(NVRAM->wd_timer);
 630 }
 631
 632 static void m48t59_reset_isa(DeviceState *d)
 633 {
 634     M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
 635     m48t59_t *NVRAM = &isa->state;
 636
 637     m48t59_reset_common(NVRAM);
 638 }
 639
 640 static void m48t59_reset_sysbus(DeviceState *d)
 641 {
 642     M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
 643     m48t59_t *NVRAM = &sys->state;
 644
 645     m48t59_reset_common(NVRAM);
 646 }
 647
 648 /* Initialisation routine */
 649 m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
 650                        uint32_t io_base, uint16_t size,
 651                        int type)
 652 {
 653     DeviceState *dev;
 654     SysBusDevice *s;
 655     M48t59SysBusState *d;
 656
 657     dev = qdev_create(NULL, "m48t59");
 658     qdev_prop_set_uint32(dev, "type", type);
 659     qdev_prop_set_uint32(dev, "size", size);
 660     qdev_prop_set_uint32(dev, "io_base", io_base);
 661     qdev_init_nofail(dev);
 662     s = sysbus_from_qdev(dev);
 663     sysbus_connect_irq(s, 0, IRQ);
 664     if (io_base != 0) {
 665         register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
 666         register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
 667     }
 668     if (mem_base != 0) {
 669         sysbus_mmio_map(s, 0, mem_base);
 670     }
 671
 672     d = FROM_SYSBUS(M48t59SysBusState, s);
 673
 674     return &d->state;
 675 }
 676
 677 m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
 678 {
 679     M48t59ISAState *d;
 680     ISADevice *dev;
 681     m48t59_t *s;
 682
 683     dev = isa_create("m48t59_isa");
 684     qdev_prop_set_uint32(&dev->qdev, "type", type);
 685     qdev_prop_set_uint32(&dev->qdev, "size", size);
 686     qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
 687     qdev_init_nofail(&dev->qdev);
 688     d = DO_UPCAST(M48t59ISAState, busdev, dev);
 689     s = &d->state;
 690
 691     if (io_base != 0) {
 692         register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
 693         register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
 694     }
 695
 696     return s;
 697 }
 698
 699 static void m48t59_init_common(m48t59_t *s)
 700 {
 701     s->buffer = qemu_mallocz(s->size);
 702     if (s->type == 59) {
 703         s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
 704         s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
 705     }
 706     qemu_get_timedate(&s->alarm, 0);
 707
 708     register_savevm("m48t59", -1, 1, m48t59_save, m48t59_load, s);
 709 }
 710
 711 static int m48t59_init_isa1(ISADevice *dev)
 712 {
 713     M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
 714     m48t59_t *s = &d->state;
 715
 716     isa_init_irq(dev, &s->IRQ, 8);
 717     m48t59_init_common(s);
 718
 719     return 0;
 720 }
 721
 722 static int m48t59_init1(SysBusDevice *dev)
 723 {
 724     M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
 725     m48t59_t *s = &d->state;
 726     int mem_index;
 727
 728     sysbus_init_irq(dev, &s->IRQ);
 729
 730     mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
 731     sysbus_init_mmio(dev, s->size, mem_index);
 732     m48t59_init_common(s);
 733
 734     return 0;
 735 }
 736
 737 static ISADeviceInfo m48t59_isa_info = {
 738     .init = m48t59_init_isa1,
 739     .qdev.name = "m48t59_isa",
 740     .qdev.size = sizeof(M48t59ISAState),
 741     .qdev.reset = m48t59_reset_isa,
 742     .qdev.no_user = 1,
 743     .qdev.props = (Property[]) {
 744         DEFINE_PROP_UINT32("size",    M48t59ISAState, state.size,    -1),
 745         DEFINE_PROP_UINT32("type",    M48t59ISAState, state.type,    -1),
 746         DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base,  0),
 747         DEFINE_PROP_END_OF_LIST(),
 748     }
 749 };
 750
 751 static SysBusDeviceInfo m48t59_info = {
 752     .init = m48t59_init1,
 753     .qdev.name  = "m48t59",
 754     .qdev.size = sizeof(M48t59SysBusState),
 755     .qdev.reset = m48t59_reset_sysbus,
 756     .qdev.props = (Property[]) {
 757         DEFINE_PROP_UINT32("size",    M48t59SysBusState, state.size,    -1),
 758         DEFINE_PROP_UINT32("type",    M48t59SysBusState, state.type,    -1),
 759         DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base,  0),
 760         DEFINE_PROP_END_OF_LIST(),
 761     }
 762 };
 763
 764 static void m48t59_register_devices(void)
 765 {
 766     sysbus_register_withprop(&m48t59_info);
 767     isa_qdev_register(&m48t59_isa_info);
 768 }
 769
 770 device_init(m48t59_register_devices)