data/properties/vhdl.properties

   1 # Define SciTE settings for vhdl files.
   2
   3 # VHDL files
   4 file.patterns.vhdl=*.vhd;*.vhdl
   5 filter.vhdl=VHDL (vhd vhdl)|$(file.patterns.vhdl)|
   6
   7 lexer.$(file.patterns.vhdl)=vhdl
   8
   9 word.chars.vhdl=$(chars.alpha)$(chars.numeric)_
  10 word.characters.$(file.patterns.vhdl)=$(word.chars.vhdl)
  11
  12 #calltip.vhdl.word.characters=$(chars.alpha)$(chars.numeric)_
  13
  14 comment.block.vhdl=--
  15 #comment.block.at.line.start.vhdl=1
  16 #comment.stream.start.vhdl=/*
  17 #comment.stream.end.vhdl=*/
  18 #comment.box.start.vhdl=/*
  19 #comment.box.middle.vhdl= *
  20 #comment.box.end.vhdl= */
  21
  22 #~ fold.comment=1
  23 #~ fold.compact=1
  24 #~ fold.at.Begin=1
  25 #~ fold.at.Parenthese=1
  26
  27 #statement.lookback.$(file.patterns.vhdl)=20
  28 #block.start.$(file.patterns.vhdl)=5 begin
  29 #block.end.$(file.patterns.vhdl)=5 end
  30 #statement.indent.$(file.patterns.vhdl)=5 always case casex casez else for if while \
  31 #module function task
  32 #statement.end.$(file.patterns.vhdl)=10 ;
  33
  34 indent.maintain.$(file.patterns.vhdl)=1;
  35
  36
  37 keywords.$(file.patterns.vhdl)=access after alias all architecture array assert attribute begin block \
  38 body buffer bus case component configuration constant disconnect downto else elsif end entity exit file \
  39 for function generate generic group guarded if impure in inertial inout is label library linkage literal \
  40 loop map new next null of on open others out package port postponed procedure process pure range record \
  41 register reject report return select severity shared signal subtype then to transport type unaffected \
  42 units until use variable wait when while with
  43
  44 keywords2.$(file.patterns.vhdl)=                                                                            \
  45  abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
  46
  47 keywords3.$(file.patterns.vhdl)=                                                                            \
  48  left right low high ascending image value pos val succ pred leftof rightof base range reverse_range        \
  49  length delayed stable quiet transaction event active last_event last_active last_value driving             \
  50  driving_value simple_name path_name instance_name
  51
  52 keywords4.$(file.patterns.vhdl)=                                                                            \
  53  now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector      \
  54  to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left \
  55  rotate_right resize to_integer to_unsigned to_signed std_match to_01
  56
  57 keywords5.$(file.patterns.vhdl)=                                                                            \
  58  std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed               \
  59  std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives        \
  60  vital_timing
  61
  62 keywords6.$(file.patterns.vhdl)=                                                                            \
  63  boolean bit character severity_level integer real time delay_length natural positive string bit_vector     \
  64  file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic                \
  65  std_logic_vector X01 X01Z UX01 UX01Z unsigned signed
  66
  67 # vhdl styles
  68
  69 # Default
  70 style.vhdl.32=$(font.base)
  71 # White space
  72 style.vhdl.0=fore:#800080
  73 # Comment
  74 style.vhdl.1=$(colour.code.comment.line),$(font.code.comment.line)
  75 # Bang comment
  76 style.vhdl.2=fore:#3F7F3F,$(font.code.comment.line)
  77 # Number
  78 style.vhdl.3=$(colour.number)
  79 # Double quoted string
  80 style.vhdl.4=$(colour.string)
  81 # Operators
  82 #style.vhdl.5=$(colour.operator)
  83 # Identifiers
  84 style.vhdl.6=
  85 # End of line where string is not closed
  86 style.vhdl.7=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
  87 # Keyword
  88 style.vhdl.8=$(colour.keyword)
  89 # Std operator
  90 style.vhdl.9=fore:#007F7F
  91 # Attribute
  92 style.vhdl.10=fore:#804020
  93 # Std Function
  94 style.vhdl.11=fore:#808020
  95 # Std Package
  96 style.vhdl.12=fore:#208020
  97 # Std Type
  98 style.vhdl.13=fore:#208080
  99 # User defined identifiers and tasks
 100 style.vhdl.14=fore:#804020,$(font.code.comment.doc)
 101 # Braces are only matched in operator style
 102 braces.vhdl.style=10
 103