kernel/include/pci.h

   1 /*
   2  *  ZeX/OS
   3  *  Copyright (C) 2008  Tomas 'ZeXx86' Jedrzejek (zexx86@zexos.org)
   4  *
   5  *  This program is free software: you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation, either version 3 of the License, or
   8  *  (at your option) any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19
  20 #ifndef _PCI_H
  21 #define _PCI_H
  22
  23 /* ---
  24         offsets in PCI configuration space to the elements of the predefined
  25         header common to all header types
  26 --- */
  27
  28 #define PCI_vendor_id                           0x00            /* (2 byte) vendor id */
  29 #define PCI_device_id                           0x02            /* (2 byte) device id */
  30 #define PCI_command                             0x04            /* (2 byte) command */
  31 #define PCI_status                              0x06            /* (2 byte) status */
  32 #define PCI_revision                            0x08            /* (1 byte) revision id */
  33 #define PCI_class_api                           0x09            /* (1 byte) specific register interface type */
  34 #define PCI_class_sub                           0x0a            /* (1 byte) specific device function */
  35 #define PCI_class_base                          0x0b            /* (1 byte) device type (display vs network, etc) */
  36 #define PCI_line_size                           0x0c            /* (1 byte) cache line size in 32 bit words */
  37 #define PCI_latency                             0x0d            /* (1 byte) latency timer */
  38 #define PCI_header_type                         0x0e            /* (1 byte) header type */
  39 #define PCI_bist                                0x0f            /* (1 byte) built-in self-test */
  40
  41 /* ---
  42         pci commands
  43 --- */
  44 #define PCI_command_io                  0x1     /* Enable response in I/O space */
  45 #define PCI_command_mem                 0x2     /* Enable response in mem space */
  46 #define PCI_command_master              0x4     /* Enable bus mastering */
  47
  48 /* ---
  49         masks for header type register
  50 --- */
  51
  52 #define PCI_header_type_mask                    0x7F            /* header type field */
  53 #define PCI_multifunction                       0x80            /* multifunction device flag */
  54
  55 /* ---
  56         offsets in PCI configuration space to the elements of the predefined
  57         header common to header types 0x00 and 0x01
  58 --- */
  59 #define PCI_base_registers              0x10            /* base registers (size varies) */
  60 #define PCI_interrupt_line              0x3c            /* (1 byte) interrupt line */
  61 #define PCI_interrupt_pin               0x3d            /* (1 byte) interrupt pin */
  62
  63
  64 /* ---
  65         masks for flags in i/o space base address registers
  66 --- */
  67
  68 #define PCI_address_io_mask             0xFFFFFFFC      /* mask to get i/o space base address */
  69
  70
  71 /* ---
  72         masks for flags in expansion rom base address registers
  73 --- */
  74
  75 #define PCI_rom_enable                  0x00000001      /* 1 = expansion rom decode enabled */
  76 #define PCI_rom_address_mask    0xFFFFF800      /* mask to get expansion rom addr */
  77
  78 /** PCI interrupt pin values */
  79 #define PCI_pin_mask            0x07
  80 #define PCI_pin_none            0x00
  81 #define PCI_pin_a               0x01
  82 #define PCI_pin_b               0x02
  83 #define PCI_pin_c               0x03
  84 #define PCI_pin_d               0x04
  85 #define PCI_pin_max             0x04
  86
  87 /** PCI Capability Codes */
  88 #define PCI_cap_id_reserved     0x00
  89 #define PCI_cap_id_pm           0x01      /* Power management */
  90 #define PCI_cap_id_agp          0x02      /* AGP */
  91 #define PCI_cap_id_vpd          0x03      /* Vital product data */
  92 #define PCI_cap_id_slotid       0x04      /* Slot ID */
  93 #define PCI_cap_id_msi          0x05      /* Message signalled interrupt ??? */
  94 #define PCI_cap_id_chswp        0x06      /* Compact PCI HotSwap */
  95 #define PCI_cap_id_pcix         0x07
  96 #define PCI_cap_id_ldt          0x08
  97 #define PCI_cap_id_vendspec     0x09
  98 #define PCI_cap_id_debugport    0x0a
  99 #define PCI_cap_id_cpci_rsrcctl 0x0b
 100 #define PCI_cap_id_hotplug      0x0c
 101
 102 /** Power Management Control Status Register settings */
 103 #define PCI_pm_mask             0x03
 104 #define PCI_pm_ctrl             0x02
 105 #define PCI_pm_d1supp           0x0200
 106 #define PCI_pm_d2supp           0x0400
 107 #define PCI_pm_status           0x04
 108 #define PCI_pm_state_d0         0x00
 109 #define PCI_pm_state_d1         0x01
 110 #define PCI_pm_state_d2         0x02
 111 #define PCI_pm_state_d3         0x03
 112
 113
 114 enum {
 115         PCI_DEVICE = 0,
 116         PCI_HOST_BUS,
 117         PCI_BRIDGE,
 118         PCI_CARDBUS
 119 };
 120
 121 /* PCI device structure */
 122 typedef struct pcidev_context {
 123   struct pcidev_context *next, *prev;
 124         unsigned char bus, dev, fn;
 125         unsigned long id;
 126
 127         unsigned char   revision;                               /* revision id */
 128         unsigned char   class_api;                              /* specific register interface type */
 129         unsigned char   class_sub;                              /* specific device function */
 130         unsigned char   class_base;                             /* device type (display vs network, etc) */
 131         unsigned char   line_size;                              /* cache line size in 32 bit words */
 132         unsigned char   latency;                                /* latency timer */
 133         unsigned char   header_type;                            /* header type */
 134         unsigned char   bist;                                   /* built-in self-test */
 135         unsigned char   reserved;                               /* filler, for alignment */
 136         union {
 137                 struct {
 138                         unsigned long   cardbus_cis;                    /* CardBus CIS pointer */
 139                         unsigned short  subsystem_id;                   /* subsystem (add-in card) id */
 140                         unsigned short  subsystem_vendor_id;            /* subsystem (add-in card) vendor id */
 141                         unsigned long   rom_base;                       /* rom base address, viewed from host */
 142                         unsigned long   rom_base_pci;                   /* rom base addr, viewed from pci */
 143                         unsigned long   rom_size;                       /* rom size */
 144                         unsigned long   base_registers[6];              /* base registers, viewed from host */
 145                         unsigned long   base_registers_pci[6];          /* base registers, viewed from pci */
 146                         unsigned long   base_register_sizes[6];         /* size of what base regs point to */
 147                         unsigned char   base_register_flags[6];         /* flags from base address fields */
 148                         unsigned char   interrupt_line;                 /* interrupt line */
 149                         unsigned char   interrupt_pin;                  /* interrupt pin */
 150                         unsigned char   min_grant;                      /* burst period @ 33 Mhz */
 151                         unsigned char   max_latency;                    /* how often PCI access needed */
 152                 } h0;
 153                 struct {
 154                         unsigned long   base_registers[2];              /* base registers, viewed from host */
 155                         unsigned long   base_registers_pci[2];          /* base registers, viewed from pci */
 156                         unsigned long   base_register_sizes[2];         /* size of what base regs point to */
 157                         unsigned char   base_register_flags[2];         /* flags from base address fields */
 158                         unsigned char   primary_bus;
 159                         unsigned char   secondary_bus;
 160                         unsigned char   subordinate_bus;
 161                         unsigned char   secondary_latency;
 162                         unsigned char   io_base;
 163                         unsigned char   io_limit;
 164                         unsigned short  secondary_status;
 165                         unsigned short  memory_base;
 166                         unsigned short  memory_limit;
 167                         unsigned short  prefetchable_memory_base;
 168                         unsigned short  prefetchable_memory_limit;
 169                         unsigned long   prefetchable_memory_base_upper32;
 170                         unsigned long   prefetchable_memory_limit_upper32;
 171                         unsigned short  io_base_upper16;
 172                         unsigned short  io_limit_upper16;
 173                         unsigned long   rom_base;                       /* rom base address, viewed from host */
 174                         unsigned long   rom_base_pci;                   /* rom base addr, viewed from pci */
 175                         unsigned char   interrupt_line;                 /* interrupt line */
 176                         unsigned char   interrupt_pin;                  /* interrupt pin */
 177                         unsigned short  bridge_control;
 178                         unsigned short  subsystem_id;                   /* subsystem (add-in card) id */
 179                         unsigned short  subsystem_vendor_id;            /* subsystem (add-in card) vendor id */
 180                 } h1;
 181                 struct {
 182                         unsigned short  subsystem_id;                   /* subsystem (add-in card) id */
 183                         unsigned short  subsystem_vendor_id;            /* subsystem (add-in card) vendor id */
 184                 } h2;
 185         } u;
 186 } pcidev_t;
 187
 188 /* externs */
 189 extern void pcidev_display ();
 190 extern void pci_device_adjust (pcidev_t *pci);
 191 extern pcidev_t *pcidev_find (unsigned short vendor, unsigned short device);
 192 extern bool bus_pci_acthandler (unsigned act, char *block, unsigned block_len);
 193 extern int pci_read_config_dword (pcidev_t *pci, unsigned reg, unsigned long *val);
 194
 195 #endif