2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
4 // This program is free software; you can redistribute it and/or modify
5 // it under the terms of the GNU General Public License as published by
6 // the Free Software Foundation; either version 2 of the License, or
7 // (at your option) any later version.
9 // This program is distributed in the hope that it will be useful,
10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 // GNU General Public License for more details.
14 // You should have received a copy of the GNU General Public License
15 // along with this program; if not, write to the Free Software
16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 // TODO: interrupt input/outputs
20 module pia(rst_i
, clk_i
,
55 wire [7:0] pa_i
, pb_i
;
56 wire [7:0] pa_o
, pb_o
;
59 reg [7:0] pa_out_reg
, pb_out_reg
;
60 reg [7:0] pa_dir_reg
, pb_dir_reg
;
61 reg [1:0] ca1ctl
, cb1ctl
;
63 reg [2:0] ca2ctl
, cb2ctl
;
67 assign pa_o
= (pa_out_reg
& pa_dir_reg
) |
~pa_dir_reg
;
68 assign pb_o
= (pb_out_reg
& pb_dir_reg
) |
~pb_dir_reg
;
70 // Only manual CA2/CB2 output modes are supported.
71 assign ca2_o
= ca2ctl
[0];
72 assign cb2_o
= cb2ctl
[0];
75 always @ (adr_i
or pa_i
or pb_i
)
78 (pa_i
& ~pa_dir_reg
) |
(pa_out_reg
& pa_dir_reg
) :
81 (pb_i
& ~pb_dir_reg
) |
(pb_out_reg
& pb_dir_reg
) :
83 2: dat_o
= {2'b00, ca2ctl
, ddir_a
, ca1ctl
};
84 3: dat_o
= {2'b00, cb2ctl
, ddir_b
, cb1ctl
};
88 always @ (posedge clk_i
)
91 else if (stb_i
&& we_i
&& adr_i
== 0 && ddir_a
)
95 always @ (posedge clk_i
)
98 else if (stb_i
&& we_i
&& adr_i
== 0 && !ddir_a
)
102 always @ (posedge clk_i
)
105 else if (stb_i
&& we_i
&& adr_i
== 1 && ddir_b
)
109 always @ (posedge clk_i
)
112 else if (stb_i
&& we_i
&& adr_i
== 1 && !ddir_b
)
116 always @ (posedge clk_i
)
121 end else if (stb_i
&& we_i
&& adr_i
== 2) begin
122 ca2ctl
<= dat_i
[5:3];
124 ca1ctl
<= dat_i
[1:0];
128 always @ (posedge clk_i
)
133 end else if (stb_i
&& we_i
&& adr_i
== 3) begin
134 cb2ctl
<= dat_i
[5:3];
136 cb1ctl
<= dat_i
[1:0];