descriptionFPGA implementation of 8-bit Atari computers
last changeMon, 1 Sep 2008 21:47:58 +0000 (1 23:47 +0200)
content tags

The goal of the project is to create an FPGA implementation of Atari 8-bit computers.

2008-09-01 Tomek MalesinskiTop level Atosm chip and its initial firmwaremaster
2008-09-01 Tomek MalesinskiExternal Wishbone bus and serial input/output registers
2008-09-01 Tomek MalesinskiSerial input/output in Pokey
2008-09-01 Tomek MalesinskiAdd manual CA2/CB2 output
2008-08-23 Tomek MalesinskiDelete old TODO
2008-08-23 Tomek MalesinskiFix sensitivity list
2008-08-23 Tomek MalesinskiMemory refresh
2008-08-23 Tomek MalesinskiAntic mode 3
2008-08-23 Tomek Malesinskichactl[2] - reversing characters
2008-08-23 Tomek MalesinskiVertical scrolling
2008-08-22 Tomek MalesinskiAdditional delay for the lowest bit of hscrol
2008-08-22 Tomek MalesinskiLoad out_reg at the right time
2008-08-22 Tomek MalesinskiStart loading playfield later for bit modes
2008-08-22 Tomek MalesinskiTake hscroll into account when computing load_char_0
2008-08-22 Tomek MalesinskiMake load_out independent of dma_pf_width
2008-08-22 Tomek MalesinskiHave a full cycle to load playfield and char data
10 years ago master