atari.v

   1 // Atosm Chip
   2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
   3 //
   4 // This program is free software; you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation; either version 2 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // You should have received a copy of the GNU General Public License
  15 // along with this program; if not, write to the Free Software
  16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17
  18 `include "cpu6502.v"
  19 `include "memory.v"
  20 `include "antic.v"
  21
  22 // Clock:
  23 // clk2: 01010101
  24 // clk:  00110011
  25
  26 module atari(clk_i, clk2_i, rst_i);
  27    input clk_i;
  28    input clk2_i;
  29    input rst_i;
  30
  31    wire  clk_i;
  32    wire  clk2_i;
  33    wire  rst_i;
  34
  35    // Common interconnect signals.
  36    reg [15:0] adr;
  37    reg [7:0]  slavedat_o;
  38    reg [7:0]  masterdat_o;
  39    reg        stb;
  40    reg        we;
  41    wire       ack;
  42    wire       cyc;
  43
  44    // Masters outputs.
  45    wire [15:0] cpuadr_o, anticadr_o;
  46    wire [7:0]  cpudat_o;
  47    wire        cpustb_o, anticstb_o;
  48    wire        cpuwe_o;
  49    wire        cpucyc_o, anticcyc_o;
  50
  51    // Outputs from address decoder.
  52    reg         ramsel, romsel;
  53    reg         anticsel, gtiasel, pokeysel, piasel;
  54
  55    // Outputs from arbiter.
  56    wire        cpugnt, anticgnt;
  57
  58    // Slaves STB_I signals.
  59    wire        ramstb, romstb;
  60    wire        anticstb, gtiastb, pokeystb, piastb;
  61
  62    // Slaves DAT_O signals.
  63    wire [7:0]  ramdat_o, romdat_o;
  64    wire [7:0]  anticdat_o, gtiadat_o, pokeydat_o, piadat_o;
  65
  66    // Slaves ACK_O signals.
  67    wire        ramack_o, romack_o;
  68    wire        anticack_o, gtiaack_o, pokeyack_o, piaack_o;
  69
  70    // Arbiter.
  71    assign      cpugnt = 1;
  72    assign      anticgnt = 0;
  73    assign      cyc = cpucyc_o | anticcyc_o;
  74
  75    // Masters outputs multiplexer.
  76    always @ (cpuadr_o or cpudat_o or cpuwe_o or cpustb_o or
  77              anticadr_o or anticstb_o or
  78              cpugnt or anticgnt) begin
  79       if (anticgnt) begin
  80          adr = anticadr_o;
  81          masterdat_o = 0;
  82          we = 0;
  83          stb = anticstb_o;
  84       end else begin
  85          adr = cpuadr_o;
  86          masterdat_o = cpudat_o;
  87          we = cpuwe_o;
  88          stb = cpustb_o;
  89       end
  90    end
  91
  92    // Address decoder.
  93    always @ (adr) begin
  94       ramsel = 0;
  95       romsel = 0;
  96       anticsel = 0;
  97       gtiasel = 0;
  98       pokeysel = 0;
  99       anticsel = 0;
 100       if (adr < 'h4000)
 101         ramsel = 1;
 102       else if (adr[15:8] == 'hd0)
 103         gtiasel = 1;
 104       else if (adr[15:8] == 'hd2)
 105         pokeysel = 1;
 106       else if (adr[15:8] == 'hd3)
 107         piasel = 1;
 108       else if (adr[15:8] == 'hd4)
 109         anticsel = 1;
 110       else if (adr >= 'hc000)
 111         romsel = 1;
 112    end
 113
 114    // Slaves STB_I.
 115    assign ramstb = ramsel & cyc & stb;
 116    assign romstb = romsel & cyc & stb;
 117    assign anticstb = anticsel & cyc & stb;
 118    assign gtiastb = gtiasel & cyc & stb;
 119    assign pokeystb = pokeysel & cyc & stb;
 120    assign piastb = piasel & cyc & stb;
 121
 122    // Or'd slaves ACK_O.
 123    assign ack = ramack_o | romack_o | anticack_o | gtiaack_o |
 124                 pokeyack_o | piaack_o;
 125
 126    // Slaves DAT_O multiplexer.
 127    always @ (ramsel or ramdat_o or
 128              romsel or romdat_o or
 129              anticsel or anticdat_o or
 130              gtiasel or gtiadat_o or
 131              pokeysel or pokeydat_o or
 132              piasel or piadat_o)
 133      if (ramsel)
 134        slavedat_o = ramdat_o;
 135      else if (romsel)
 136        slavedat_o = romdat_o;
 137      else if (anticsel)
 138        slavedat_o = anticdat_o;
 139      else if (gtiasel)
 140        slavedat_o = gtiadat_o;
 141      else if (pokeysel)
 142        slavedat_o = pokeydat_o;
 143      else if (piasel)
 144        slavedat_o = piadat_o;
 145      else
 146        slavedat_o = 'hff;
 147
 148    defparam    u_ram.size = 'h4000;
 149    defparam    u_ram.adrbits = 14;
 150
 151    ram u_ram(.clk_i(clk_i),
 152              .adr_i(adr[13:0]),
 153              .dat_i(cpudat_o),
 154              .rst_i(rst_i),
 155              .stb_i(ramstb),
 156              .we_i(we),
 157              .ack_o(ramack_o),
 158              .dat_o(ramdat_o));
 159
 160    defparam    u_rom.size = 'h4000;
 161    defparam    u_rom.adrbits = 14;
 162
 163    rom u_rom(.clk_i(clk_i),
 164              .adr_i(adr[13:0]),
 165              .rst_i(rst_i),
 166              .stb_i(romstb),
 167              .ack_o(romack_o),
 168              .dat_o(romdat_o));
 169
 170    cpu6502 u_cpu(.clk_i(clk_i),
 171                  .adr_o(cpuadr_o),
 172                  .dat_i(slavedat_o),
 173                  .rst_i(rst_i),
 174                  .stb_o(cpustb),
 175                  .we_o(cpuwe_o),
 176                  .ack_i(ack),
 177                  .dat_o(cpudat_o));
 178
 179    antic u_antic(.clk_i(clk_i),
 180                  .adr_i(adr[3:0]),
 181                  .adr_o(anticadr_o),
 182                  .dat_i(cpudat_o),
 183                  .rst_i(rst_i),
 184                  .stb_i(anticstb),
 185                  .we_i(we),
 186                  .ack_o(anticack_o),
 187                  .dat_o(anticdat_o),
 188                  .clk2_i(clk2_i));
 189
 190 endmodule