antic.v

   1 // Atosm Chip
   2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
   3 //
   4 // This program is free software; you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation; either version 2 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // You should have received a copy of the GNU General Public License
  15 // along with this program; if not, write to the Free Software
  16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17
  18 module antic(rst_i, clk_i,
  19              adr_i, adr_o,
  20              dat_i, dat_o,
  21              we_i,
  22              stb_i, stb_o,
  23              ack_i, ack_o,
  24              clk2_i);
  25    input rst_i;
  26    input clk_i;
  27    input adr_i;
  28    input dat_i;
  29    input we_i;
  30    input stb_i;
  31    input ack_i;
  32    input clk2_i;
  33
  34    output adr_o;
  35    output dat_o;
  36    output stb_o;
  37    output ack_o;
  38
  39    wire       rst_i, clk_i;
  40    wire [3:0] adr_i;
  41    wire [7:0] dat_i;
  42    wire       we_i;
  43    wire       stb_i;
  44    wire       ack_i;
  45    wire       clk2_i;
  46
  47    reg [15:0] adr_o;
  48    reg [7:0]  dat_o;
  49    reg        stb_o;
  50    wire       ack_o;
  51
  52    reg [1:0]  dma_pf_width;
  53    reg        dma_mis_en;
  54    reg        dma_ply_en;
  55    reg        dma_pm_1res;
  56    reg        dma_instr_en;
  57
  58    reg [6:0]  chbase;
  59    reg [2:0]  chactl;
  60    reg [5:0]  pmbase;
  61    reg [3:0]  hscrol;
  62    reg [3:0]  vscrol;
  63
  64    reg [15:0] dlist_ctr;
  65    reg        dlist_inc;
  66
  67    reg [7:0]  hcount;
  68    reg [8:0]  vcount;
  69
  70    reg [1:0]  adro_sel;
  71
  72    parameter [1:0] ADRO_DLPTR   = 2'b00;
  73    parameter [1:0] ADRO_MEMSCAN = 2'b01;
  74    parameter [1:0] ADRO_CHAR    = 2'b10;
  75    parameter [1:0] ADRO_PM      = 2'b11;
  76
  77    assign ack_o = stb_i;
  78
  79    always @ (adr_i)
  80      case (adr_i)
  81        'hb:
  82          dat_o = vcount[8:1];
  83        default:
  84          dat_o = 'hff;
  85      endcase
  86
  87    // DMACTL
  88    always @ (posedge clk_i)
  89      if (we_i && adr_i == 'h0) begin
  90         dma_pf_width <= dat_i[1:0];
  91         dma_mis_en   <= dat_i[2];
  92         dma_ply_en   <= dat_i[3];
  93         dma_pm_1res  <= dat_i[4];
  94         dma_instr_en <= dat_i[5];
  95      end
  96
  97    // CHACTL
  98    always @ (posedge clk_i)
  99      if (we_i && adr_i == 'h1)
 100         chactl <= dat_i[2:0];
 101
 102    // DLISTL/H
 103    always @ (posedge clk_i)
 104      if (we_i && adr_i == 'h2)
 105        dlist_ctr[7:0] <= dat_i;
 106      else if (we_i && adr_i == 'h3)
 107        dlist_ctr[15:8] <= dat_i;
 108      else if (dlist_inc)
 109        dlist_ctr[9:0] <= dlist_ctr[9:0] + 1;
 110
 111    // HSCROL
 112    always @ (posedge clk_i)
 113      if (we_i && adr_i == 'h4)
 114        hscrol <= dat_i[3:0];
 115
 116    // VSCROL
 117    always @ (posedge clk_i)
 118      if (we_i && adr_i == 'h5)
 119        vscrol <= dat_i[3:0];
 120
 121    // PMBASE
 122    always @ (posedge clk_i)
 123      if (we_i && adr_i == 'h7)
 124        pmbase <= dat_i[7:2];
 125
 126    // CHBASE
 127    always @ (posedge clk_i)
 128      if (we_i && adr_i == 'h9)
 129        chbase <= dat_i[7:1];
 130
 131    // WSYNC
 132    always @ (posedge clk_i)
 133      if (we_i && adr_i == 'ha) begin
 134      end
 135
 136    // NMIEN
 137    always @ (posedge clk_i)
 138      if (we_i && adr_i == 'he) begin
 139      end
 140
 141    // NMIRES
 142    always @ (posedge clk_i)
 143      if (we_i && adr_i == 'hf) begin
 144      end
 145
 146    // HCOUNT
 147    always @ (posedge clk2_i)
 148      if (rst_i && !clk_i)
 149        hcount <= 0;
 150      else if (hcount == 227)
 151        hcount <= 0;
 152      else
 153        hcount <= hcount + 1;
 154
 155    // VCOUNT
 156    always @ (posedge clk2_i)
 157      if (rst_i && !clk_i)
 158        vcount <= 0;
 159      else if (hcount == 227)
 160        if (vcount == 311)
 161          vcount <= 0;
 162        else
 163          vcount <= vcount + 1;
 164
 165    always @ (adro_sel)
 166      case (adro_sel)
 167        ADRO_DLPTR:
 168          begin end
 169        ADRO_MEMSCAN:
 170          begin end
 171        ADRO_CHAR:
 172          begin end
 173        ADRO_PM:
 174          begin end
 175      endcase
 176
 177 endmodule