cpu/mpc8260/pci.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (c) 2005 MontaVista Software, Inc.
   6  * Vitaly Bordug <vbordug@ru.mvista.com>
   7  * Added support for PCI bridge on MPC8272ADS
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29
  30 #ifdef CONFIG_PCI
  31
  32 #include <pci.h>
  33 #include <mpc8260.h>
  34 #include <asm/m8260_pci.h>
  35 #include <asm/io.h>
  36
  37 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
  38 DECLARE_GLOBAL_DATA_PTR;
  39 #endif
  40
  41 /*
  42  *   Local->PCI map (from CPU)                             controlled by
  43  *   MPC826x master window
  44  *
  45  *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
  46  *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
  47  *
  48  *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
  49  *                              PCI Mem with prefetch
  50  *
  51  *   0xA0000000 - 0xBFFFFFFF    0xA0000000 - 0xBFFFFFFF   (Outbound ATU #2)
  52  *                              PCI Mem w/o  prefetch
  53  *
  54  *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
  55  *                              32-bit PCI IO
  56  *
  57  *   PCI->Local map (from PCI)
  58  *   MPC826x slave window                                  controlled by
  59  *
  60  *   0x00000000 - 0x1FFFFFFF    0x00000000 - 0x1FFFFFFF   (Inbound ATU #1)
  61  *                              MPC826x local memory
  62  */
  63
  64 /*
  65  * Slave window that allows PCI masters to access MPC826x local memory.
  66  * This window is set up using the first set of Inbound ATU registers
  67  */
  68
  69 #ifndef CFG_PCI_SLV_MEM_LOCAL
  70 #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE        /* Local base */
  71 #else
  72 #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
  73 #endif
  74
  75 #ifndef CFG_PCI_SLV_MEM_BUS
  76 #define PCI_SLV_MEM_BUS 0x00000000      /* PCI base */
  77 #else
  78 #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
  79 #endif
  80
  81 #ifndef CFG_PICMR0_MASK_ATTRIB
  82 #define PICMR0_MASK_ATTRIB      (PICMR_MASK_512MB | PICMR_ENABLE | \
  83                                  PICMR_PREFETCH_EN)
  84 #else
  85 #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
  86 #endif
  87
  88 /*
  89  * These are the windows that allow the CPU to access PCI address space.
  90  * All three PCI master windows, which allow the CPU to access PCI
  91  * prefetch, non prefetch, and IO space (see below), must all fit within
  92  * these windows.
  93  */
  94
  95 /* PCIBR0 */
  96 #ifndef CFG_PCI_MSTR0_LOCAL
  97 #define PCI_MSTR0_LOCAL         0x80000000      /* Local base */
  98 #else
  99 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
 100 #endif
 101
 102 #ifndef CFG_PCIMSK0_MASK
 103 #define PCIMSK0_MASK            PCIMSK_1GB      /* Size of window */
 104 #else
 105 #define PCIMSK0_MASK    CFG_PCIMSK0_MASK
 106 #endif
 107
 108 /* PCIBR1 */
 109 #ifndef CFG_PCI_MSTR1_LOCAL
 110 #define PCI_MSTR1_LOCAL         0xF4000000      /* Local base */
 111 #else
 112 #define PCI_MSTR1_LOCAL         CFG_PCI_MSTR1_LOCAL
 113 #endif
 114
 115 #ifndef CFG_PCIMSK1_MASK
 116 #define  PCIMSK1_MASK           PCIMSK_64MB     /* Size of window */
 117 #else
 118 #define  PCIMSK1_MASK           CFG_PCIMSK1_MASK
 119 #endif
 120
 121 /*
 122  * Master window that allows the CPU to access PCI Memory (prefetch).
 123  * This window will be setup with the first set of Outbound ATU registers
 124  * in the bridge.
 125  */
 126
 127 #ifndef CFG_PCI_MSTR_MEM_LOCAL
 128 #define PCI_MSTR_MEM_LOCAL 0x80000000   /* Local base */
 129 #else
 130 #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
 131 #endif
 132
 133 #ifndef CFG_PCI_MSTR_MEM_BUS
 134 #define PCI_MSTR_MEM_BUS 0x80000000     /* PCI base   */
 135 #else
 136 #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
 137 #endif
 138
 139 #ifndef CFG_CPU_PCI_MEM_START
 140 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
 141 #else
 142 #define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
 143 #endif
 144
 145 #ifndef CFG_PCI_MSTR_MEM_SIZE
 146 #define PCI_MSTR_MEM_SIZE 0x10000000    /* 256MB */
 147 #else
 148 #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
 149 #endif
 150
 151 #ifndef CFG_POCMR0_MASK_ATTRIB
 152 #define POCMR0_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 153 #else
 154 #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
 155 #endif
 156
 157 /*
 158  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 159  * This window will be setup with the second set of Outbound ATU registers
 160  * in the bridge.
 161  */
 162
 163 #ifndef CFG_PCI_MSTR_MEMIO_LOCAL
 164 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
 165 #else
 166 #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
 167 #endif
 168
 169 #ifndef CFG_PCI_MSTR_MEMIO_BUS
 170 #define PCI_MSTR_MEMIO_BUS 0x90000000   /* PCI base   */
 171 #else
 172 #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
 173 #endif
 174
 175 #ifndef CFG_CPU_PCI_MEMIO_START
 176 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
 177 #else
 178 #define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
 179 #endif
 180
 181 #ifndef CFG_PCI_MSTR_MEMIO_SIZE
 182 #define PCI_MSTR_MEMIO_SIZE 0x10000000  /* 256 MB */
 183 #else
 184 #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
 185 #endif
 186
 187 #ifndef CFG_POCMR1_MASK_ATTRIB
 188 #define POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 189 #else
 190 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
 191 #endif
 192
 193 /*
 194  * Master window that allows the CPU to access PCI IO space.
 195  * This window will be setup with the third set of Outbound ATU registers
 196  * in the bridge.
 197  */
 198
 199 #ifndef CFG_PCI_MSTR_IO_LOCAL
 200 #define PCI_MSTR_IO_LOCAL 0xA0000000    /* Local base */
 201 #else
 202 #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
 203 #endif
 204
 205 #ifndef CFG_PCI_MSTR_IO_BUS
 206 #define PCI_MSTR_IO_BUS 0xA0000000      /* PCI base   */
 207 #else
 208 #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
 209 #endif
 210
 211 #ifndef CFG_CPU_PCI_IO_START
 212 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
 213 #else
 214 #define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
 215 #endif
 216
 217 #ifndef CFG_PCI_MSTR_IO_SIZE
 218 #define PCI_MSTR_IO_SIZE 0x10000000     /* 256MB */
 219 #else
 220 #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
 221 #endif
 222
 223 #ifndef CFG_POCMR2_MASK_ATTRIB
 224 #define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
 225 #else
 226 #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
 227 #endif
 228
 229 /* PCI bus configuration registers.
 230  */
 231
 232 #define PCI_CLASS_BRIDGE_CTLR   0x06
 233
 234
 235 static inline void pci_outl (u32 addr, u32 data)
 236 {
 237         *(volatile u32 *) addr = cpu_to_le32 (data);
 238 }
 239
 240 void pci_mpc8250_init (struct pci_controller *hose)
 241 {
 242         u16 tempShort;
 243
 244         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 245         pci_dev_t host_devno = PCI_BDF (0, 0, 0);
 246
 247         pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
 248                             CFG_IMMR + PCI_CFG_DATA_REG);
 249
 250         /*
 251          * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
 252          */
 253 #ifdef CONFIG_MPC8266ADS
 254         immap->im_siu_conf.sc_siumcr =
 255                 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 256                 | SIUMCR_LBPC01;
 257 #elif defined CONFIG_MPC8272
 258         immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
 259                                   ~SIUMCR_BBD &
 260                                   ~SIUMCR_ESE &
 261                                   ~SIUMCR_PBSE &
 262                                   ~SIUMCR_CDIS &
 263                                   ~SIUMCR_DPPC11 &
 264                                   ~SIUMCR_L2CPC11 &
 265                                   ~SIUMCR_LBPC11 &
 266                                   ~SIUMCR_APPC11 &
 267                                   ~SIUMCR_CS10PC11 &
 268                                   ~SIUMCR_BCTLC11 &
 269                                   ~SIUMCR_MMR11)
 270                                   | SIUMCR_DPPC11
 271                                   | SIUMCR_L2CPC01
 272                                   | SIUMCR_LBPC00
 273                                   | SIUMCR_APPC10
 274                                   | SIUMCR_CS10PC00
 275                                   | SIUMCR_BCTLC00
 276                                   | SIUMCR_MMR11;
 277 #elif defined(CONFIG_TQM8272)
 278 /* nothing to do for this Board here */
 279 #else
 280         /*
 281          * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
 282          * and local bus for PCI (SIUMCR [LBPC]).
 283          */
 284         immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
 285                                                 ~SIUMCR_LBPC11 &
 286                                                 ~SIUMCR_CS10PC11 &
 287                                                 ~SIUMCR_LBPC11) |
 288                                         SIUMCR_LBPC01 |
 289                                         SIUMCR_CS10PC01 |
 290                                         SIUMCR_APPC10;
 291 #endif
 292
 293         /* Make PCI lowest priority */
 294         /* Each 4 bits is a device bus request  and the MS 4bits
 295            is highest priority */
 296         /* Bus               4bit value
 297            ---               ----------
 298            CPM high          0b0000
 299            CPM middle        0b0001
 300            CPM low           0b0010
 301            PCI reguest       0b0011
 302            Reserved          0b0100
 303            Reserved          0b0101
 304            Internal Core     0b0110
 305            External Master 1 0b0111
 306            External Master 2 0b1000
 307            External Master 3 0b1001
 308            The rest are reserved */
 309         immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
 310
 311         /* Park bus on core while modifying PCI Bus accesses */
 312         immap->im_siu_conf.sc_ppc_acr = 0x6;
 313
 314         /*
 315          * Set up master windows that allow the CPU to access PCI space. These
 316          * windows are set up using the two SIU PCIBR registers.
 317          */
 318         immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
 319         immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
 320
 321 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 322         immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
 323         immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
 324 #endif
 325
 326         /* Release PCI RST (by default the PCI RST signal is held low)  */
 327         immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
 328
 329         /* give it some time */
 330         {
 331 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 332                 /* Give the PCI cards more time to initialize before query
 333                    This might be good for other boards also
 334                  */
 335                 int i;
 336
 337                 for (i = 0; i < 1000; ++i)
 338 #endif
 339                         udelay (1000);
 340         }
 341
 342         /*
 343          * Set up master window that allows the CPU to access PCI Memory (prefetch)
 344          * space. This window is set up using the first set of Outbound ATU registers.
 345          */
 346         immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);        /* PCI base */
 347         immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);      /* Local base */
 348         immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);    /* Size & attribute */
 349
 350         /*
 351          * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
 352          * space. This window is set up using the second set of Outbound ATU registers.
 353          */
 354         immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);      /* PCI base */
 355         immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);    /* Local base */
 356         immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);    /* Size & attribute */
 357
 358         /*
 359          * Set up master window that allows the CPU to access PCI IO space. This window
 360          * is set up using the third set of Outbound ATU registers.
 361          */
 362         immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
 363         immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);       /* Local base */
 364         immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);    /* Size & attribute */
 365
 366         /*
 367          * Set up slave window that allows PCI masters to access MPC826x local memory.
 368          * This window is set up using the first set of Inbound ATU registers
 369          */
 370         immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);       /* PCI base */
 371         immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
 372         immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);    /* Size & attribute */
 373
 374         /* See above for description - puts PCI request as highest priority */
 375 #ifdef CONFIG_MPC8272
 376         immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
 377 #else
 378         immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
 379 #endif
 380
 381         /* Park the bus on the PCI */
 382         immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
 383
 384         /* Host mode - specify the bridge as a host-PCI bridge */
 385
 386         pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
 387                                     PCI_CLASS_BRIDGE_CTLR);
 388
 389         /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
 390         pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
 391         pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
 392                                     tempShort | PCI_COMMAND_MASTER |
 393                                     PCI_COMMAND_MEMORY);
 394
 395         /* do some bridge init, should be done on all 8260 based bridges */
 396         pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
 397                                     0x08);
 398         pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
 399                                     0xF8);
 400
 401         hose->first_busno = 0;
 402         hose->last_busno = 0xff;
 403
 404         /* System memory space */
 405 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
 406         pci_set_region (hose->regions + 0,
 407                         PCI_SLV_MEM_BUS,
 408                         PCI_SLV_MEM_LOCAL,
 409                         gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
 410 #else
 411         pci_set_region (hose->regions + 0,
 412                         CFG_SDRAM_BASE,
 413                         CFG_SDRAM_BASE,
 414                         0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
 415 #endif
 416
 417         /* PCI memory space */
 418 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
 419         pci_set_region (hose->regions + 1,
 420                         PCI_MSTR_MEMIO_BUS,
 421                         PCI_MSTR_MEMIO_LOCAL,
 422                         PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
 423 #else
 424         pci_set_region (hose->regions + 1,
 425                         PCI_MSTR_MEM_BUS,
 426                         PCI_MSTR_MEM_LOCAL,
 427                         PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
 428 #endif
 429
 430         /* PCI I/O space */
 431         pci_set_region (hose->regions + 2,
 432                         PCI_MSTR_IO_BUS,
 433                         PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
 434
 435         hose->region_count = 3;
 436
 437         pci_register_hose (hose);
 438         /* Mask off master abort machine checks */
 439         immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
 440         eieio ();
 441
 442         hose->last_busno = pci_hose_scan (hose);
 443
 444
 445         /* clear the error in the error status register */
 446         immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 447
 448         /* unmask master abort machine checks */
 449         immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 450 }
 451
 452 #endif /* CONFIG_PCI */