3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 MontaVista Software, Inc.
6 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/m8260_pci.h>
37 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
38 DECLARE_GLOBAL_DATA_PTR
;
42 * Local->PCI map (from CPU) controlled by
43 * MPC826x master window
45 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
46 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
48 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
49 * PCI Mem with prefetch
51 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
52 * PCI Mem w/o prefetch
54 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
57 * PCI->Local map (from PCI)
58 * MPC826x slave window controlled by
60 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
61 * MPC826x local memory
65 * Slave window that allows PCI masters to access MPC826x local memory.
66 * This window is set up using the first set of Inbound ATU registers
69 #ifndef CFG_PCI_SLV_MEM_LOCAL
70 #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
72 #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
75 #ifndef CFG_PCI_SLV_MEM_BUS
76 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
78 #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
81 #ifndef CFG_PICMR0_MASK_ATTRIB
82 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
85 #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
89 * These are the windows that allow the CPU to access PCI address space.
90 * All three PCI master windows, which allow the CPU to access PCI
91 * prefetch, non prefetch, and IO space (see below), must all fit within
96 #ifndef CFG_PCI_MSTR0_LOCAL
97 #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
99 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
102 #ifndef CFG_PCIMSK0_MASK
103 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
105 #define PCIMSK0_MASK CFG_PCIMSK0_MASK
109 #ifndef CFG_PCI_MSTR1_LOCAL
110 #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
112 #define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
115 #ifndef CFG_PCIMSK1_MASK
116 #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
118 #define PCIMSK1_MASK CFG_PCIMSK1_MASK
122 * Master window that allows the CPU to access PCI Memory (prefetch).
123 * This window will be setup with the first set of Outbound ATU registers
127 #ifndef CFG_PCI_MSTR_MEM_LOCAL
128 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
130 #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
133 #ifndef CFG_PCI_MSTR_MEM_BUS
134 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
136 #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
139 #ifndef CFG_CPU_PCI_MEM_START
140 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
142 #define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
145 #ifndef CFG_PCI_MSTR_MEM_SIZE
146 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
148 #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
151 #ifndef CFG_POCMR0_MASK_ATTRIB
152 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
154 #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
158 * Master window that allows the CPU to access PCI Memory (non-prefetch).
159 * This window will be setup with the second set of Outbound ATU registers
163 #ifndef CFG_PCI_MSTR_MEMIO_LOCAL
164 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
166 #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
169 #ifndef CFG_PCI_MSTR_MEMIO_BUS
170 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
172 #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
175 #ifndef CFG_CPU_PCI_MEMIO_START
176 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
178 #define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
181 #ifndef CFG_PCI_MSTR_MEMIO_SIZE
182 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
184 #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
187 #ifndef CFG_POCMR1_MASK_ATTRIB
188 #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
190 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
194 * Master window that allows the CPU to access PCI IO space.
195 * This window will be setup with the third set of Outbound ATU registers
199 #ifndef CFG_PCI_MSTR_IO_LOCAL
200 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
202 #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
205 #ifndef CFG_PCI_MSTR_IO_BUS
206 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
208 #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
211 #ifndef CFG_CPU_PCI_IO_START
212 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
214 #define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
217 #ifndef CFG_PCI_MSTR_IO_SIZE
218 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
220 #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
223 #ifndef CFG_POCMR2_MASK_ATTRIB
224 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
226 #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
229 /* PCI bus configuration registers.
232 #define PCI_CLASS_BRIDGE_CTLR 0x06
235 static inline void pci_outl (u32 addr
, u32 data
)
237 *(volatile u32
*) addr
= cpu_to_le32 (data
);
240 void pci_mpc8250_init (struct pci_controller
*hose
)
244 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
245 pci_dev_t host_devno
= PCI_BDF (0, 0, 0);
247 pci_setup_indirect (hose
, CFG_IMMR
+ PCI_CFG_ADDR_REG
,
248 CFG_IMMR
+ PCI_CFG_DATA_REG
);
251 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
253 #ifdef CONFIG_MPC8266ADS
254 immap
->im_siu_conf
.sc_siumcr
=
255 (immap
->im_siu_conf
.sc_siumcr
& ~SIUMCR_LBPC11
)
257 #elif defined CONFIG_MPC8272
258 immap
->im_siu_conf
.sc_siumcr
= (immap
->im_siu_conf
.sc_siumcr
&
277 #elif defined(CONFIG_TQM8272)
278 /* nothing to do for this Board here */
281 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
282 * and local bus for PCI (SIUMCR [LBPC]).
284 immap
->im_siu_conf
.sc_siumcr
= (immap
->im_siu_conf
.sc_siumcr
&
293 /* Make PCI lowest priority */
294 /* Each 4 bits is a device bus request and the MS 4bits
295 is highest priority */
305 External Master 1 0b0111
306 External Master 2 0b1000
307 External Master 3 0b1001
308 The rest are reserved */
309 immap
->im_siu_conf
.sc_ppc_alrh
= 0x61207893;
311 /* Park bus on core while modifying PCI Bus accesses */
312 immap
->im_siu_conf
.sc_ppc_acr
= 0x6;
315 * Set up master windows that allow the CPU to access PCI space. These
316 * windows are set up using the two SIU PCIBR registers.
318 immap
->im_memctl
.memc_pcimsk0
= PCIMSK0_MASK
;
319 immap
->im_memctl
.memc_pcibr0
= PCI_MSTR0_LOCAL
| PCIBR_ENABLE
;
321 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
322 immap
->im_memctl
.memc_pcimsk1
= PCIMSK1_MASK
;
323 immap
->im_memctl
.memc_pcibr1
= PCI_MSTR1_LOCAL
| PCIBR_ENABLE
;
326 /* Release PCI RST (by default the PCI RST signal is held low) */
327 immap
->im_pci
.pci_gcr
= cpu_to_le32 (PCIGCR_PCI_BUS_EN
);
329 /* give it some time */
331 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
332 /* Give the PCI cards more time to initialize before query
333 This might be good for other boards also
337 for (i
= 0; i
< 1000; ++i
)
343 * Set up master window that allows the CPU to access PCI Memory (prefetch)
344 * space. This window is set up using the first set of Outbound ATU registers.
346 immap
->im_pci
.pci_potar0
= cpu_to_le32 (PCI_MSTR_MEM_BUS
>> 12); /* PCI base */
347 immap
->im_pci
.pci_pobar0
= cpu_to_le32 (PCI_MSTR_MEM_LOCAL
>> 12); /* Local base */
348 immap
->im_pci
.pci_pocmr0
= cpu_to_le32 (POCMR0_MASK_ATTRIB
); /* Size & attribute */
351 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
352 * space. This window is set up using the second set of Outbound ATU registers.
354 immap
->im_pci
.pci_potar1
= cpu_to_le32 (PCI_MSTR_MEMIO_BUS
>> 12); /* PCI base */
355 immap
->im_pci
.pci_pobar1
= cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL
>> 12); /* Local base */
356 immap
->im_pci
.pci_pocmr1
= cpu_to_le32 (POCMR1_MASK_ATTRIB
); /* Size & attribute */
359 * Set up master window that allows the CPU to access PCI IO space. This window
360 * is set up using the third set of Outbound ATU registers.
362 immap
->im_pci
.pci_potar2
= cpu_to_le32 (PCI_MSTR_IO_BUS
>> 12); /* PCI base */
363 immap
->im_pci
.pci_pobar2
= cpu_to_le32 (PCI_MSTR_IO_LOCAL
>> 12); /* Local base */
364 immap
->im_pci
.pci_pocmr2
= cpu_to_le32 (POCMR2_MASK_ATTRIB
); /* Size & attribute */
367 * Set up slave window that allows PCI masters to access MPC826x local memory.
368 * This window is set up using the first set of Inbound ATU registers
370 immap
->im_pci
.pci_pitar0
= cpu_to_le32 (PCI_SLV_MEM_LOCAL
>> 12); /* PCI base */
371 immap
->im_pci
.pci_pibar0
= cpu_to_le32 (PCI_SLV_MEM_BUS
>> 12); /* Local base */
372 immap
->im_pci
.pci_picmr0
= cpu_to_le32 (PICMR0_MASK_ATTRIB
); /* Size & attribute */
374 /* See above for description - puts PCI request as highest priority */
375 #ifdef CONFIG_MPC8272
376 immap
->im_siu_conf
.sc_ppc_alrh
= 0x01236745;
378 immap
->im_siu_conf
.sc_ppc_alrh
= 0x03124567;
381 /* Park the bus on the PCI */
382 immap
->im_siu_conf
.sc_ppc_acr
= PPC_ACR_BUS_PARK_PCI
;
384 /* Host mode - specify the bridge as a host-PCI bridge */
386 pci_hose_write_config_byte (hose
, host_devno
, PCI_CLASS_CODE
,
387 PCI_CLASS_BRIDGE_CTLR
);
389 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
390 pci_hose_read_config_word (hose
, host_devno
, PCI_COMMAND
, &tempShort
);
391 pci_hose_write_config_word (hose
, host_devno
, PCI_COMMAND
,
392 tempShort
| PCI_COMMAND_MASTER
|
395 /* do some bridge init, should be done on all 8260 based bridges */
396 pci_hose_write_config_byte (hose
, host_devno
, PCI_CACHE_LINE_SIZE
,
398 pci_hose_write_config_byte (hose
, host_devno
, PCI_LATENCY_TIMER
,
401 hose
->first_busno
= 0;
402 hose
->last_busno
= 0xff;
404 /* System memory space */
405 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
406 pci_set_region (hose
->regions
+ 0,
409 gd
->ram_size
, PCI_REGION_MEM
| PCI_REGION_MEMORY
);
411 pci_set_region (hose
->regions
+ 0,
414 0x4000000, PCI_REGION_MEM
| PCI_REGION_MEMORY
);
417 /* PCI memory space */
418 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
419 pci_set_region (hose
->regions
+ 1,
421 PCI_MSTR_MEMIO_LOCAL
,
422 PCI_MSTR_MEMIO_SIZE
, PCI_REGION_MEM
);
424 pci_set_region (hose
->regions
+ 1,
427 PCI_MSTR_MEM_SIZE
, PCI_REGION_MEM
);
431 pci_set_region (hose
->regions
+ 2,
433 PCI_MSTR_IO_LOCAL
, PCI_MSTR_IO_SIZE
, PCI_REGION_IO
);
435 hose
->region_count
= 3;
437 pci_register_hose (hose
);
438 /* Mask off master abort machine checks */
439 immap
->im_pci
.pci_emr
&= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP
);
442 hose
->last_busno
= pci_hose_scan (hose
);
445 /* clear the error in the error status register */
446 immap
->im_pci
.pci_esr
= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP
);
448 /* unmask master abort machine checks */
449 immap
->im_pci
.pci_emr
|= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP
);
452 #endif /* CONFIG_PCI */