Merge branch 'master' into verilog-ams
[sverilog.git] / ivl_assert.h
blob32d05dd06cce92a89ac3e092276e4427db7b11a5
1 /*
2 * Copyright (c) 2007 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 #ifdef HAVE_CVS_IDENT
20 #ident "$Id: ivl_assert.h,v 1.1 2007/01/31 04:21:10 steve Exp $"
21 #endif
23 #ifndef __ivl_assert_h
24 #define __ivl_assert_h
26 # include <assert.h>
28 #define ivl_assert(tok, expression) \
29 do { \
30 if (! (expression)) \
31 __ivl_assert(#expression, tok, __FILE__, __LINE__); \
32 } while(0)
34 #define __ivl_assert(expression, tok, file, line) \
35 do { \
36 cerr << (tok).get_fileline() << ": assert: " \
37 << file << ":" << line \
38 << ": failed assertion " << (expression) << endl; \
39 abort(); \
40 } while(0)
43 #endif