Merge branch 'master' into verilog-ams
[sverilog.git] / functor.h
blobd3b9b5088a4826b93cabf698eb67eaa24b689e7e
1 #ifndef __functor_H
2 #define __functor_H
3 /*
4 * Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
23 * The functor is an object that can be applied to a design to
24 * transform it. This is different from the target_t, which can only
25 * scan the design but not transform it in any way.
27 * When a functor it scanning a process, signal or node, the functor
28 * is free to manipulate the list by deleting items, including the
29 * node being scanned. The Design class scanner knows how to handle
30 * the situation. However, if objects are added to the netlist, there
31 * is no guarantee that object will be scanned unless the functor is
32 * rerun.
35 class Design;
36 class NetNet;
37 class NetProcTop;
39 struct functor_t {
40 virtual ~functor_t();
42 /* Events are scanned here. */
43 virtual void event(class Design*des, class NetEvent*);
45 /* This is called once for each signal in the design. */
46 virtual void signal(class Design*des, class NetNet*);
48 /* This method is called for each process in the design. */
49 virtual void process(class Design*des, class NetProcTop*);
51 /* This method is called for each structural abs(). */
52 virtual void lpm_abs(class Design*des, class NetAbs*);
54 /* This method is called for each structural adder. */
55 virtual void lpm_add_sub(class Design*des, class NetAddSub*);
57 /* This method is called for each structural comparator. */
58 virtual void lpm_compare(class Design*des, class NetCompare*);
60 /* This method is called for each structural constant. */
61 virtual void lpm_const(class Design*des, class NetConst*);
63 /* This method is called for each structural constant. */
64 virtual void lpm_divide(class Design*des, class NetDivide*);
66 /* Constant literals. */
67 virtual void lpm_literal(class Design*des, class NetLiteral*);
69 /* This method is called for each structural constant. */
70 virtual void lpm_modulo(class Design*des, class NetModulo*);
72 /* This method is called for each FF in the design. */
73 virtual void lpm_ff(class Design*des, class NetFF*);
75 /* Handle LPM combinational logic devices. */
76 virtual void lpm_logic(class Design*des, class NetLogic*);
78 /* This method is called for each multiplier. */
79 virtual void lpm_mult(class Design*des, class NetMult*);
81 /* This method is called for each MUX. */
82 virtual void lpm_mux(class Design*des, class NetMux*);
84 /* This method is called for each power. */
85 virtual void lpm_pow(class Design*des, class NetPow*);
87 /* This method is called for each unary reduction gate. */
88 virtual void lpm_ureduce(class Design*des, class NetUReduce*);
90 virtual void sign_extend(class Design*des, class NetSignExtend*);
93 struct proc_match_t {
94 virtual ~proc_match_t();
96 virtual int assign(class NetAssign*);
97 virtual int assign_nb(class NetAssignNB*);
98 virtual int condit(class NetCondit*);
99 virtual int event_wait(class NetEvWait*);
100 virtual int block(class NetBlock*);
103 #endif