Merge branch 'master' into verilog-ams
[sverilog.git] / disciplines.vams
blob12ac0c74cdd792e3f9f353ccb175819145dabb77
2 // Standard definitions for Verilog-AMS
3 `ifdef DISCIPLINES_VAMS
4 `else
5 `define DISCIPLINES_VAMS 1
7 discipline \logic ;
8   domain discrete;
9 enddiscipline
11 discipline ddiscrete;
12   domain discrete;
13 enddiscipline
15 nature Current;
16   units      = "A";
17   access     = I;
18   idt_nature = Charge;
19 `ifdef CURRENT_ABSTOL
20   abstol     = `CURRENT_ABSTOL
21 `else
22   abstol     = 1e-12;
23 `endif
24 endnature
26 nature Charge;
27   units      = "coul";
28   access     = Q;
29   ddt_nature = Current;
30 `ifdef CHARGE_ABSTOL
31   abstol     = `CHARGE_ABSTOL;
32 `else
33   abstol     = 1e-14;
34 `endif
35 endnature
37 nature Voltage;
38   units      = "V";
39   access     = V;
40   idt_nature = Flux;
41 `ifdef VOLTAGE_ABSTOL
42   abstol     = `VOLTAGE_ABSTOL;
43 `else
44   abstol     = 1e-6;
45 `endif
46 endnature
48 nature Flux;
49   units      = "Wb";
50   access     = Phi;
51   ddt_nature = Voltage;
52 `ifdef FLUX_ABSTOL
53   abstol     = `flux_ABSTOL;
54 `else
55   abstol     = 1e-9;
56 `endif
57 endnature
59 discipline electrical;
60   potential Voltage;
61   flow Current;
62 enddiscipline
64 discipline voltage;
65   potential Voltage;
66 enddiscipline
68 discipline current;
69   flow Current;
70 enddiscipline
72 `endif // !`ifdef DISCIPLINES_VAMS