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Merge branch 'master' into verilog-ams
[sverilog.git] / check.conf
blob2f9b4f5717b817bac007eb89a5a7258fe63a8dd8
1 functor:cprop
2 functor:nodangle
3 -t:dll
4 flag:DLL=tgt-vvp/vvp.tgt
systemverilog compiler