Merge branch 'master' into verilog-ams
[sverilog.git] / Module.cc
blob9619401494aa9c559481d031041200787fa24890
1 /*
2 * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
20 # include "config.h"
22 # include "Module.h"
23 # include "PGate.h"
24 # include "PWire.h"
25 # include <assert.h>
27 /* n is a permallocated string. */
28 Module::Module(perm_string n)
29 : PScope(n, 0)
31 library_flag = false;
32 default_nettype = NetNet::NONE;
35 Module::~Module()
39 void Module::add_gate(PGate*gate)
41 gates_.push_back(gate);
44 void Module::add_task(perm_string name, PTask*task)
46 tasks_[name] = task;
49 void Module::add_function(perm_string name, PFunction *func)
51 funcs_[name] = func;
54 unsigned Module::port_count() const
56 return ports.count();
60 * Return the array of PEIdent object that are at this port of the
61 * module. If the port is internally unconnected, return an empty
62 * array.
64 const svector<PEIdent*>& Module::get_port(unsigned idx) const
66 assert(idx < ports.count());
67 static svector<PEIdent*> zero;
69 if (ports[idx])
70 return ports[idx]->expr;
71 else
72 return zero;
75 unsigned Module::find_port(const char*name) const
77 assert(name != 0);
78 for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
79 if (ports[idx] == 0) {
80 /* It is possible to have undeclared ports. These
81 are ports that are skipped in the declaration,
82 for example like so: module foo(x ,, y); The
83 port between x and y is unnamed and thus
84 inaccessible to binding by name. */
85 continue;
87 assert(ports[idx]);
88 if (ports[idx]->name == name)
89 return idx;
92 return ports.count();
96 PGate* Module::get_gate(perm_string name)
98 for (list<PGate*>::iterator cur = gates_.begin()
99 ; cur != gates_.end()
100 ; cur ++ ) {
102 if ((*cur)->get_name() == name)
103 return *cur;
106 return 0;
109 const list<PGate*>& Module::get_gates() const
111 return gates_;