2 * Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
22 # include "compiler.h"
24 # include "parse_misc.h"
25 # include "parse_api.h"
28 # include "PGenerate.h"
39 # include "ivl_assert.h"
42 map
<perm_string
,Module
*> pform_modules
;
43 map
<perm_string
,PUdp
*> pform_primitives
;
46 * The lexor accesses the vl_* variables.
52 /* This tracks the current module being processed. There can only be
53 exactly one module currently being parsed, since Verilog does not
54 allow nested module definitions. */
55 static Module
*pform_cur_module
= 0;
57 bool pform_library_flag
= false;
59 /* increment this for generate schemes within a module, and set it
60 to zero when a new module starts. */
61 static unsigned scope_generate_counter
= 1;
63 /* This tracks the current generate scheme being processed. This is
64 always within a module. */
65 static PGenerate
*pform_cur_generate
= 0;
67 static NetNet::Type pform_default_nettype
= NetNet::WIRE
;
70 * These variables track the current time scale, as well as where the
71 * timescale was set. This supports warnings about tangled timescales.
73 static int pform_time_unit
= 0;
74 static int pform_time_prec
= 0;
76 static char*pform_timescale_file
= 0;
77 static unsigned pform_timescale_line
= 0;
79 static inline void FILE_NAME(LineInfo
*obj
, const char*file
, unsigned lineno
)
81 obj
->set_lineno(lineno
);
82 obj
->set_file(filename_strings
.make(file
));
85 static inline void FILE_NAME(LineInfo
*tmp
, const struct vlltype
&where
)
87 tmp
->set_lineno(where
.first_line
);
88 tmp
->set_file(filename_strings
.make(where
.text
));
92 * The lexical_scope keeps track of the current lexical scope that is
93 * being parsed. The lexical scope may stack, so the current scope may
94 * have a parent, that is restored when the current scope ends.
96 * Items that have scoped names are put in the lexical_scope object.
98 static PScope
* lexical_scope
= 0;
100 void pform_pop_scope()
102 lexical_scope
= lexical_scope
->pscope_parent();
105 PTask
* pform_push_task_scope(char*name
)
107 perm_string task_name
= lex_strings
.make(name
);
108 PTask
*task
= new PTask(task_name
, pform_cur_module
);
110 // Add the task to the current module
111 pform_cur_module
->add_task(task
->pscope_name(), task
);
112 // Make this the current lexical scope
113 lexical_scope
= task
;
117 PFunction
* pform_push_function_scope(char*name
)
119 perm_string func_name
= lex_strings
.make(name
);
120 PFunction
*func
= new PFunction(func_name
, lexical_scope
);
122 // Add the task to the current module
123 pform_cur_module
->add_function(func
->pscope_name(), func
);
124 // Make this the current lexical scope
125 lexical_scope
= func
;
129 PBlock
* pform_push_block_scope(char*name
, PBlock::BL_TYPE bt
)
131 perm_string block_name
= lex_strings
.make(name
);
132 PBlock
*block
= new PBlock(block_name
, lexical_scope
, bt
);
134 // Make this the current lexical scope
135 lexical_scope
= block
;
140 static PWire
*get_wire_in_scope(perm_string name
)
142 /* Note that if we are processing a generate, then the
143 scope depth will be empty because generate schemes
144 cannot be within sub-scopes. Only directly in
146 if (pform_cur_generate
)
147 return pform_cur_generate
->get_wire(name
);
149 return lexical_scope
->wires_find(name
);
152 void pform_set_default_nettype(NetNet::Type type
,
153 const char*file
, unsigned lineno
)
155 pform_default_nettype
= type
;
157 if (pform_cur_module
) {
158 cerr
<< file
<<":"<<lineno
<< ": error: "
159 << "`default_nettype directives must appear" << endl
;
160 cerr
<< file
<<":"<<lineno
<< ": : "
161 << "outside module definitions. The containing" << endl
;
162 cerr
<< file
<<":"<<lineno
<< ": : "
163 << "module " << pform_cur_module
->mod_name()
164 << " starts on line "
165 << pform_cur_module
->get_fileline() << "." << endl
;
171 * The lexor calls this function to set the active timescale when it
172 * detects a `timescale directive. The function saves the directive
173 * values (for use by modules) and if warnings are enabled checks to
174 * see if some modules have no timescale.
176 void pform_set_timescale(int unit
, int prec
,
177 const char*file
, unsigned lineno
)
179 bool first_flag
= true;
181 assert(unit
>= prec
);
182 pform_time_unit
= unit
;
183 pform_time_prec
= prec
;
185 if (pform_timescale_file
) {
186 free(pform_timescale_file
);
190 pform_timescale_file
= strdup(file
);
191 pform_timescale_line
= lineno
;
193 if (warn_timescale
&& first_flag
&& (pform_modules
.size() > 0)) {
194 cerr
<< file
<< ":" << lineno
<< ": warning: "
195 << "Some modules have no timescale. This may cause"
197 cerr
<< file
<< ":" << lineno
<< ": : "
198 << "confusing timing results. Affected modules are:"
201 map
<perm_string
,Module
*>::iterator mod
;
202 for (mod
= pform_modules
.begin()
203 ; mod
!= pform_modules
.end() ; mod
++) {
204 const Module
*mp
= (*mod
).second
;
206 cerr
<< file
<< ":" << lineno
<< ": : "
207 << " -- module " << (*mod
).first
208 << " declared here: " << mp
->get_fileline() << endl
;
214 verinum
* pform_verinum_with_size(verinum
*siz
, verinum
*val
,
215 const char*file
, unsigned lineno
)
217 assert(siz
->is_defined());
218 unsigned long size
= siz
->as_ulong();
222 switch (val
->get(val
->len()-1)) {
234 verinum
*res
= new verinum(pad
, size
, true);
236 unsigned copy
= val
->len();
237 if (res
->len() < copy
)
240 for (unsigned idx
= 0 ; idx
< copy
; idx
+= 1) {
241 res
->set(idx
, val
->get(idx
));
244 res
->has_sign(val
->has_sign());
246 bool trunc_flag
= false;
247 for (unsigned idx
= copy
; idx
< val
->len() ; idx
+= 1) {
248 if (val
->get(idx
) != pad
) {
255 cerr
<< file
<< ":" << lineno
<< ": warning: Numeric constant "
256 << "truncated to " << copy
<< " bits." << endl
;
264 void pform_startmodule(const char*name
, const char*file
, unsigned lineno
,
265 svector
<named_pexpr_t
*>*attr
)
267 assert( pform_cur_module
== 0 );
269 perm_string lex_name
= lex_strings
.make(name
);
270 pform_cur_module
= new Module(lex_name
);
271 pform_cur_module
->time_unit
= pform_time_unit
;
272 pform_cur_module
->time_precision
= pform_time_prec
;
273 pform_cur_module
->default_nettype
= pform_default_nettype
;
275 FILE_NAME(pform_cur_module
, file
, lineno
);
276 pform_cur_module
->library_flag
= pform_library_flag
;
278 ivl_assert(*pform_cur_module
, lexical_scope
== 0);
279 lexical_scope
= pform_cur_module
;
281 /* The generate scheme numbering starts with *1*, not
282 zero. That's just the way it is, thanks to the standard. */
283 scope_generate_counter
= 1;
285 if (warn_timescale
&& pform_timescale_file
286 && (strcmp(pform_timescale_file
,file
) != 0)) {
288 cerr
<< pform_cur_module
->get_fileline() << ": warning: "
289 << "timescale for " << name
290 << " inherited from another file." << endl
;
291 cerr
<< pform_timescale_file
<< ":" << pform_timescale_line
292 << ": ...: The inherited timescale is here." << endl
;
295 for (unsigned idx
= 0 ; idx
< attr
->count() ; idx
+= 1) {
296 named_pexpr_t
*tmp
= (*attr
)[idx
];
297 pform_cur_module
->attributes
[tmp
->name
] = tmp
->parm
;
303 * This function is called by the parser to make a simple port
304 * reference. This is a name without a .X(...), so the internal name
305 * should be generated to be the same as the X.
307 Module::port_t
* pform_module_port_reference(perm_string name
,
311 Module::port_t
*ptmp
= new Module::port_t
;
312 PEIdent
*tmp
= new PEIdent(name
);
313 FILE_NAME(tmp
, file
, lineno
);
315 ptmp
->expr
= svector
<PEIdent
*>(1);
321 void pform_module_set_ports(svector
<Module::port_t
*>*ports
)
323 assert(pform_cur_module
);
325 /* The parser parses ``module foo()'' as having one
326 unconnected port, but it is really a module with no
327 ports. Fix it up here. */
328 if (ports
&& (ports
->count() == 1) && ((*ports
)[0] == 0)) {
334 pform_cur_module
->ports
= *ports
;
339 void pform_endmodule(const char*name
)
341 assert(pform_cur_module
);
342 perm_string mod_name
= pform_cur_module
->mod_name();
343 assert(strcmp(name
, mod_name
) == 0);
345 map
<perm_string
,Module
*>::const_iterator test
=
346 pform_modules
.find(mod_name
);
348 if (test
!= pform_modules
.end()) {
350 msg
<< "Module " << name
<< " was already declared here: "
351 << (*test
).second
->get_fileline() << endl
;
352 VLerror(msg
.str().c_str());
354 pform_modules
[mod_name
] = pform_cur_module
;
357 // The current lexical scope should be this module by now, and
358 // this module should not have a parent lexical scope.
359 ivl_assert(*pform_cur_module
, lexical_scope
== pform_cur_module
);
360 lexical_scope
= pform_cur_module
->pscope_parent();
361 ivl_assert(*pform_cur_module
, lexical_scope
== 0);
363 pform_cur_module
= 0;
366 void pform_genvars(const struct vlltype
&li
, list
<perm_string
>*names
)
368 list
<perm_string
>::const_iterator cur
;
369 for (cur
= names
->begin(); cur
!= names
->end() ; *cur
++) {
370 LineInfo
*lni
= new LineInfo();
372 pform_cur_module
->genvars
.push_back(
373 pair
<perm_string
,LineInfo
*>(*cur
, lni
));
379 void pform_start_generate_for(const struct vlltype
&li
,
380 char*ident1
, PExpr
*init
,
382 char*ident2
, PExpr
*next
)
384 PGenerate
*gen
= new PGenerate(scope_generate_counter
++);
388 // For now, assume that generates do not nest.
389 gen
->parent
= pform_cur_generate
;
390 pform_cur_generate
= gen
;
392 pform_cur_generate
->scheme_type
= PGenerate::GS_LOOP
;
394 pform_cur_generate
->loop_index
= lex_strings
.make(ident1
);
395 pform_cur_generate
->loop_init
= init
;
396 pform_cur_generate
->loop_test
= test
;
397 pform_cur_generate
->loop_step
= next
;
403 void pform_start_generate_if(const struct vlltype
&li
, PExpr
*test
)
405 PGenerate
*gen
= new PGenerate(scope_generate_counter
++);
409 // For now, assume that generates do not nest.
410 gen
->parent
= pform_cur_generate
;
411 pform_cur_generate
= gen
;
413 pform_cur_generate
->scheme_type
= PGenerate::GS_CONDIT
;
415 pform_cur_generate
->loop_init
= 0;
416 pform_cur_generate
->loop_test
= test
;
417 pform_cur_generate
->loop_step
= 0;
420 void pform_start_generate_else(const struct vlltype
&li
)
422 assert(pform_cur_generate
);
423 assert(pform_cur_generate
->scheme_type
== PGenerate::GS_CONDIT
);
425 PGenerate
*cur
= pform_cur_generate
;
428 PGenerate
*gen
= new PGenerate(scope_generate_counter
++);
432 // For now, assume that generates do not nest.
433 gen
->parent
= pform_cur_generate
;
434 pform_cur_generate
= gen
;
436 pform_cur_generate
->scheme_type
= PGenerate::GS_ELSE
;
438 pform_cur_generate
->loop_init
= 0;
439 pform_cur_generate
->loop_test
= cur
->loop_test
;
440 pform_cur_generate
->loop_step
= 0;
444 * The GS_CASE version of the PGenerate contains only case items. The
445 * items in turn contain the generated items themselves.
447 void pform_start_generate_case(const struct vlltype
&li
, PExpr
*expr
)
449 PGenerate
*gen
= new PGenerate(scope_generate_counter
++);
453 gen
->parent
= pform_cur_generate
;
454 pform_cur_generate
= gen
;
456 pform_cur_generate
->scheme_type
= PGenerate::GS_CASE
;
458 pform_cur_generate
->loop_init
= 0;
459 pform_cur_generate
->loop_test
= expr
;
460 pform_cur_generate
->loop_step
= 0;
464 * The generate case item is a special case schema that takes its id
465 * from the case schema that it is a part of. The idea is that the
466 * case schema can only instantiate exactly one item, so the items
467 * need not have a unique number.
469 void pform_generate_case_item(const struct vlltype
&li
, PExpr
*expr
)
471 assert(pform_cur_generate
);
472 assert(pform_cur_generate
->scheme_type
== PGenerate::GS_CASE
);
474 PGenerate
*gen
= new PGenerate(pform_cur_generate
->id_number
);
478 gen
->parent
= pform_cur_generate
;
479 pform_cur_generate
= gen
;
481 pform_cur_generate
->scheme_type
= PGenerate::GS_CASE_ITEM
;
483 pform_cur_generate
->loop_init
= 0;
484 pform_cur_generate
->loop_test
= expr
;
485 pform_cur_generate
->loop_step
= 0;
488 void pform_generate_block_name(char*name
)
490 assert(pform_cur_generate
!= 0);
491 assert(pform_cur_generate
->scope_name
== 0);
492 pform_cur_generate
->scope_name
= lex_strings
.make(name
);
496 void pform_endgenerate()
498 assert(pform_cur_generate
!= 0);
499 assert(pform_cur_module
);
501 // If there is no explicit block name then generate a temporary
502 // name. This will be replaced by the correct name later, once
503 // we know all the explicit names in the surrounding scope. If
504 // the naming scheme used here is changed, PGenerate::elaborate
505 // must be changed to match.
506 if (pform_cur_generate
->scope_name
== 0) {
508 snprintf(tmp
, sizeof tmp
, "$gen%d", pform_cur_generate
->id_number
);
509 pform_cur_generate
->scope_name
= lex_strings
.make(tmp
);
512 PGenerate
*cur
= pform_cur_generate
;
513 pform_cur_generate
= cur
->parent
;
515 if (pform_cur_generate
!= 0) {
516 assert(cur
->scheme_type
== PGenerate::GS_CASE_ITEM
517 || pform_cur_generate
->scheme_type
!= PGenerate::GS_CASE
);
518 pform_cur_generate
->generates
.push_back(cur
);
520 assert(cur
->scheme_type
!= PGenerate::GS_CASE_ITEM
);
521 pform_cur_module
->generate_schemes
.push_back(cur
);
525 bool pform_expression_is_constant(const PExpr
*ex
)
527 return ex
->is_constant(pform_cur_module
);
530 MIN_TYP_MAX min_typ_max_flag
= TYP
;
531 unsigned min_typ_max_warn
= 10;
533 PExpr
* pform_select_mtm_expr(PExpr
*min
, PExpr
*typ
, PExpr
*max
)
537 switch (min_typ_max_flag
) {
555 if (min_typ_max_warn
> 0) {
556 cerr
<< res
->get_fileline() << ": warning: choosing ";
557 switch (min_typ_max_flag
) {
569 cerr
<< " expression." << endl
;
570 min_typ_max_warn
-= 1;
576 template <> inline svector
<perm_string
>::svector(unsigned size
)
577 : nitems_(size
), items_(new perm_string
[size
])
581 static void process_udp_table(PUdp
*udp
, list
<string
>*table
,
582 const char*file
, unsigned lineno
)
584 const bool synchronous_flag
= udp
->sequential
;
586 /* Interpret and check the table entry strings, to make sure
587 they correspond to the inputs, output and output type. Make
588 up vectors for the fully interpreted result that can be
589 placed in the PUdp object.
591 The table strings are made up by the parser to be two or
592 three substrings separated by ';', i.e.:
594 0101:1:1 (synchronous device entry)
595 0101:0 (combinational device entry)
597 The parser doesn't check that we got the right kind here,
598 so this loop must watch out. */
599 svector
<string
> input (table
->size());
600 svector
<char> current (table
->size());
601 svector
<char> output (table
->size());
603 for (list
<string
>::iterator cur
= table
->begin()
604 ; cur
!= table
->end()
605 ; cur
++, idx
+= 1) {
608 /* Pull the input values from the string. */
609 assert(tmp
.find(':') == (udp
->ports
.count() - 1));
610 input
[idx
] = tmp
.substr(0, udp
->ports
.count()-1);
611 tmp
= tmp
.substr(udp
->ports
.count()-1);
613 assert(tmp
[0] == ':');
615 /* If this is a synchronous device, get the current
617 if (synchronous_flag
) {
618 if (tmp
.size() != 4) {
619 cerr
<< file
<<":"<<lineno
<< ": error: "
620 << "Invalid table format for"
621 << " sequential primitive." << endl
;
625 assert(tmp
.size() == 4);
626 current
[idx
] = tmp
[1];
629 } else if (tmp
.size() != 2) {
630 cerr
<< file
<<":"<<lineno
<< ": error: "
631 << "Invalid table format for"
632 << " combinational primitive." << endl
;
637 /* Finally, extract the desired output. */
638 assert(tmp
.size() == 2);
639 output
[idx
] = tmp
[1];
644 udp
->tcurrent
= current
;
645 udp
->toutput
= output
;
648 void pform_make_udp(perm_string name
, list
<perm_string
>*parms
,
649 svector
<PWire
*>*decl
, list
<string
>*table
,
651 const char*file
, unsigned lineno
)
653 unsigned local_errors
= 0;
654 assert(parms
->size() > 0);
656 /* Put the declarations into a map, so that I can check them
657 off with the parameters in the list. If the port is already
658 in the map, merge the port type. I will rebuild a list
659 of parameters for the PUdp object. */
660 map
<perm_string
,PWire
*> defs
;
661 for (unsigned idx
= 0 ; idx
< decl
->count() ; idx
+= 1) {
663 perm_string port_name
= (*decl
)[idx
]->basename();
665 if (PWire
*cur
= defs
[port_name
]) {
667 assert((*decl
)[idx
]);
668 if ((*decl
)[idx
]->get_port_type() != NetNet::PIMPLICIT
) {
669 rc
= cur
->set_port_type((*decl
)[idx
]->get_port_type());
672 if ((*decl
)[idx
]->get_wire_type() != NetNet::IMPLICIT
) {
673 rc
= cur
->set_wire_type((*decl
)[idx
]->get_wire_type());
678 defs
[port_name
] = (*decl
)[idx
];
683 /* Put the parameters into a vector of wire descriptions. Look
684 in the map for the definitions of the name. In this loop,
685 the parms list in the list of ports in the port list of the
686 UDP declaration, and the defs map maps that name to a
687 PWire* created by an input or output declaration. */
688 svector
<PWire
*> pins (parms
->size());
689 svector
<perm_string
> pin_names (parms
->size());
690 { list
<perm_string
>::iterator cur
;
692 for (cur
= parms
->begin(), idx
= 0
693 ; cur
!= parms
->end()
695 pins
[idx
] = defs
[*cur
];
696 pin_names
[idx
] = *cur
;
700 /* Check that the output is an output and the inputs are
701 inputs. I can also make sure that only the single output is
702 declared a register, if anything. The possible errors are:
704 -- an input port (not the first) is missing an input
707 -- An input port is declared output.
710 assert(pins
.count() > 0);
713 cerr
<< file
<<":"<<lineno
<< ": error: "
714 << "Output port of primitive " << name
715 << " missing output declaration." << endl
;
716 cerr
<< file
<<":"<<lineno
<< ": : "
717 << "Try: output " << pin_names
[0] << ";"
723 if (pins
[0]->get_port_type() != NetNet::POUTPUT
) {
724 cerr
<< file
<<":"<<lineno
<< ": error: "
725 << "The first port of a primitive"
726 << " must be an output." << endl
;
727 cerr
<< file
<<":"<<lineno
<< ": : "
728 << "Try: output " << pin_names
[0] << ";"
736 for (unsigned idx
= 1 ; idx
< pins
.count() ; idx
+= 1) {
737 if (pins
[idx
] == 0) {
738 cerr
<< file
<<":"<<lineno
<< ": error: "
739 << "Port " << (idx
+1)
740 << " of primitive " << name
<< " missing"
741 << " input declaration." << endl
;
742 cerr
<< file
<<":"<<lineno
<< ": : "
743 << "Try: input " << pin_names
[idx
] << ";"
749 if (pins
[idx
]->get_port_type() != NetNet::PINPUT
) {
750 cerr
<< file
<<":"<<lineno
<< ": error: "
751 << "Input port " << (idx
+1)
752 << " of primitive " << name
753 << " has an output (or missing) declaration." << endl
;
754 cerr
<< file
<<":"<<lineno
<< ": : "
755 << "Note that only the first port can be an output."
757 cerr
<< file
<<":"<<lineno
<< ": : "
758 << "Try \"input " << name
<< ";\""
765 if (pins
[idx
]->get_wire_type() == NetNet::REG
) {
766 cerr
<< file
<<":"<<lineno
<< ": error: "
767 << "Port " << (idx
+1)
768 << " of primitive " << name
<< " is an input port"
769 << " with a reg declaration." << endl
;
770 cerr
<< file
<<":"<<lineno
<< ": : "
771 << "primitive inputs cannot be reg."
779 if (local_errors
> 0) {
788 /* Verify the "initial" statement, if present, to be sure that
789 it only assigns to the output and the output is
790 registered. Then save the initial value that I get. */
791 verinum::V init
= verinum::Vx
;
794 assert(pins
[0]->get_wire_type() == NetNet::REG
);
796 PAssign
*pa
= dynamic_cast<PAssign
*>(init_expr
);
799 const PEIdent
*id
= dynamic_cast<const PEIdent
*>(pa
->lval());
803 //assert(id->name() == pins[0]->name());
805 const PENumber
*np
= dynamic_cast<const PENumber
*>(pa
->rval());
808 init
= np
->value()[0];
811 // Put the primitive into the primitives table
812 if (pform_primitives
[name
]) {
813 VLerror("UDP primitive already exists.");
816 PUdp
*udp
= new PUdp(name
, parms
->size());
818 // Detect sequential udp.
819 if (pins
[0]->get_wire_type() == NetNet::REG
)
820 udp
->sequential
= true;
822 // Make the port list for the UDP
823 for (unsigned idx
= 0 ; idx
< pins
.count() ; idx
+= 1)
824 udp
->ports
[idx
] = pins
[idx
]->basename();
826 process_udp_table(udp
, table
, file
, lineno
);
829 pform_primitives
[name
] = udp
;
833 /* Delete the excess tables and lists from the parser. */
840 void pform_make_udp(perm_string name
, bool synchronous_flag
,
841 perm_string out_name
, PExpr
*init_expr
,
842 list
<perm_string
>*parms
, list
<string
>*table
,
843 const char*file
, unsigned lineno
)
846 svector
<PWire
*> pins(parms
->size() + 1);
848 /* Make the PWire for the output port. */
849 pins
[0] = new PWire(out_name
,
850 synchronous_flag
? NetNet::REG
: NetNet::WIRE
,
851 NetNet::POUTPUT
, IVL_VT_LOGIC
);
852 FILE_NAME(pins
[0], file
, lineno
);
854 /* Make the PWire objects for the input ports. */
855 { list
<perm_string
>::iterator cur
;
857 for (cur
= parms
->begin(), idx
= 1
858 ; cur
!= parms
->end()
860 assert(idx
< pins
.count());
861 pins
[idx
] = new PWire(*cur
, NetNet::WIRE
,
862 NetNet::PINPUT
, IVL_VT_LOGIC
);
863 FILE_NAME(pins
[idx
], file
, lineno
);
865 assert(idx
== pins
.count());
868 /* Verify the initial expression, if present, to be sure that
869 it only assigns to the output and the output is
870 registered. Then save the initial value that I get. */
871 verinum::V init
= verinum::Vx
;
874 assert(pins
[0]->get_wire_type() == NetNet::REG
);
876 PAssign
*pa
= dynamic_cast<PAssign
*>(init_expr
);
879 const PEIdent
*id
= dynamic_cast<const PEIdent
*>(pa
->lval());
883 //assert(id->name() == pins[0]->name());
885 const PENumber
*np
= dynamic_cast<const PENumber
*>(pa
->rval());
888 init
= np
->value()[0];
891 // Put the primitive into the primitives table
892 if (pform_primitives
[name
]) {
893 VLerror("UDP primitive already exists.");
896 PUdp
*udp
= new PUdp(name
, pins
.count());
898 // Detect sequential udp.
899 udp
->sequential
= synchronous_flag
;
901 // Make the port list for the UDP
902 for (unsigned idx
= 0 ; idx
< pins
.count() ; idx
+= 1)
903 udp
->ports
[idx
] = pins
[idx
]->basename();
907 process_udp_table(udp
, table
, file
, lineno
);
910 pform_primitives
[name
] = udp
;
919 * This function attaches a range to a given name. The function is
920 * only called by the parser within the scope of the net declaration,
921 * and the name that I receive only has the tail component.
923 static void pform_set_net_range(perm_string name
,
924 const svector
<PExpr
*>*range
,
926 ivl_variable_type_t dt
,
929 PWire
*cur
= get_wire_in_scope(name
);
931 VLerror("error: name is not a valid net.");
936 /* This is the special case that we really mean a
937 scalar. Set a fake range. */
938 cur
->set_range(0, 0, rt
);
941 assert(range
->count() == 2);
944 cur
->set_range((*range
)[0], (*range
)[1], rt
);
946 cur
->set_signed(signed_flag
);
948 if (dt
!= IVL_VT_NO_TYPE
)
949 cur
->set_data_type(dt
);
952 void pform_set_net_range(list
<perm_string
>*names
,
953 svector
<PExpr
*>*range
,
955 ivl_variable_type_t dt
,
958 assert((range
== 0) || (range
->count() == 2));
960 for (list
<perm_string
>::iterator cur
= names
->begin()
961 ; cur
!= names
->end()
963 perm_string txt
= *cur
;
964 pform_set_net_range(txt
, range
, signed_flag
, dt
, rt
);
973 * This is invoked to make a named event. This is the declaration of
974 * the event, and not necessarily the use of it.
976 static void pform_make_event(perm_string name
, const char*fn
, unsigned ln
)
978 PEvent
*event
= new PEvent(name
);
979 FILE_NAME(event
, fn
, ln
);
980 pform_cur_module
->events
[name
] = event
;
983 void pform_make_events(list
<perm_string
>*names
, const char*fn
, unsigned ln
)
985 list
<perm_string
>::iterator cur
;
986 for (cur
= names
->begin() ; cur
!= names
->end() ; cur
++) {
987 perm_string txt
= *cur
;
988 pform_make_event(txt
, fn
, ln
);
995 * pform_makegates is called when a list of gates (with the same type)
996 * are ready to be instantiated. The function runs through the list of
997 * gates and calls the pform_makegate function to make the individual gate.
999 void pform_makegate(PGBuiltin::Type type
,
1000 struct str_pair_t str
,
1001 svector
<PExpr
*>* delay
,
1003 svector
<named_pexpr_t
*>*attr
)
1005 if (info
.parms_by_name
) {
1006 cerr
<< info
.file
<< ":" << info
.lineno
<< ": Gates do not "
1007 "have port names." << endl
;
1012 perm_string dev_name
= lex_strings
.make(info
.name
);
1013 PGBuiltin
*cur
= new PGBuiltin(type
, dev_name
, info
.parms
, delay
);
1015 cur
->set_range(info
.range
[0], info
.range
[1]);
1018 for (unsigned idx
= 0 ; idx
< attr
->count() ; idx
+= 1) {
1019 named_pexpr_t
*tmp
= (*attr
)[idx
];
1020 cur
->attributes
[tmp
->name
] = tmp
->parm
;
1024 cur
->strength0(str
.str0
);
1025 cur
->strength1(str
.str1
);
1026 FILE_NAME(cur
, info
.file
, info
.lineno
);
1028 if (pform_cur_generate
)
1029 pform_cur_generate
->add_gate(cur
);
1031 pform_cur_module
->add_gate(cur
);
1034 void pform_makegates(PGBuiltin::Type type
,
1035 struct str_pair_t str
,
1036 svector
<PExpr
*>*delay
,
1037 svector
<lgate
>*gates
,
1038 svector
<named_pexpr_t
*>*attr
)
1040 for (unsigned idx
= 0 ; idx
< gates
->count() ; idx
+= 1) {
1041 pform_makegate(type
, str
, delay
, (*gates
)[idx
], attr
);
1045 for (unsigned idx
= 0 ; idx
< attr
->count() ; idx
+= 1) {
1046 named_pexpr_t
*cur
= (*attr
)[idx
];
1056 * A module is different from a gate in that there are different
1057 * constraints, and sometimes different syntax. The X_modgate
1058 * functions handle the instantiations of modules (and UDP objects) by
1059 * making PGModule objects.
1061 * The first pform_make_modgate handles the case of a module
1062 * instantiated with ports passed by position. The "wires" is an
1063 * ordered array of port expressions.
1065 * The second pform_make_modgate handles the case of a module
1066 * instantiated with ports passed by name. The "bind" argument is the
1067 * ports matched with names.
1069 static void pform_make_modgate(perm_string type
,
1071 struct parmvalue_t
*overrides
,
1072 svector
<PExpr
*>*wires
,
1073 PExpr
*msb
, PExpr
*lsb
,
1074 const char*fn
, unsigned ln
)
1076 PGModule
*cur
= new PGModule(type
, name
, wires
);
1077 FILE_NAME(cur
, fn
, ln
);
1078 cur
->set_range(msb
,lsb
);
1080 if (overrides
&& overrides
->by_name
) {
1081 unsigned cnt
= overrides
->by_name
->count();
1082 named
<PExpr
*>*byname
= new named
<PExpr
*>[cnt
];
1084 for (unsigned idx
= 0 ; idx
< cnt
; idx
+= 1) {
1085 named_pexpr_t
*curp
= (*overrides
->by_name
)[idx
];
1086 byname
[idx
].name
= curp
->name
;
1087 byname
[idx
].parm
= curp
->parm
;
1090 cur
->set_parameters(byname
, cnt
);
1092 } else if (overrides
&& overrides
->by_order
) {
1093 cur
->set_parameters(overrides
->by_order
);
1096 if (pform_cur_generate
)
1097 pform_cur_generate
->add_gate(cur
);
1099 pform_cur_module
->add_gate(cur
);
1102 static void pform_make_modgate(perm_string type
,
1104 struct parmvalue_t
*overrides
,
1105 svector
<named_pexpr_t
*>*bind
,
1106 PExpr
*msb
, PExpr
*lsb
,
1107 const char*fn
, unsigned ln
)
1109 unsigned npins
= bind
->count();
1110 named
<PExpr
*>*pins
= new named
<PExpr
*>[npins
];
1111 for (unsigned idx
= 0 ; idx
< npins
; idx
+= 1) {
1112 named_pexpr_t
*curp
= (*bind
)[idx
];
1113 pins
[idx
].name
= curp
->name
;
1114 pins
[idx
].parm
= curp
->parm
;
1117 PGModule
*cur
= new PGModule(type
, name
, pins
, npins
);
1118 FILE_NAME(cur
, fn
, ln
);
1119 cur
->set_range(msb
,lsb
);
1121 if (overrides
&& overrides
->by_name
) {
1122 unsigned cnt
= overrides
->by_name
->count();
1123 named
<PExpr
*>*byname
= new named
<PExpr
*>[cnt
];
1125 for (unsigned idx
= 0 ; idx
< cnt
; idx
+= 1) {
1126 named_pexpr_t
*curp
= (*overrides
->by_name
)[idx
];
1127 byname
[idx
].name
= curp
->name
;
1128 byname
[idx
].parm
= curp
->parm
;
1131 cur
->set_parameters(byname
, cnt
);
1133 } else if (overrides
&& overrides
->by_order
) {
1135 cur
->set_parameters(overrides
->by_order
);
1139 if (pform_cur_generate
)
1140 pform_cur_generate
->add_gate(cur
);
1142 pform_cur_module
->add_gate(cur
);
1145 void pform_make_modgates(perm_string type
,
1146 struct parmvalue_t
*overrides
,
1147 svector
<lgate
>*gates
)
1150 for (unsigned idx
= 0 ; idx
< gates
->count() ; idx
+= 1) {
1151 lgate cur
= (*gates
)[idx
];
1152 perm_string cur_name
= lex_strings
.make(cur
.name
);
1154 if (cur
.parms_by_name
) {
1155 pform_make_modgate(type
, cur_name
, overrides
,
1157 cur
.range
[0], cur
.range
[1],
1158 cur
.file
, cur
.lineno
);
1160 } else if (cur
.parms
) {
1162 /* If there are no parameters, the parser will be
1163 tricked into thinking it is one empty
1164 parameter. This fixes that. */
1165 if ((cur
.parms
->count() == 1) && (cur
.parms
[0][0] == 0)) {
1167 cur
.parms
= new svector
<PExpr
*>(0);
1169 pform_make_modgate(type
, cur_name
, overrides
,
1171 cur
.range
[0], cur
.range
[1],
1172 cur
.file
, cur
.lineno
);
1175 svector
<PExpr
*>*wires
= new svector
<PExpr
*>(0);
1176 pform_make_modgate(type
, cur_name
, overrides
,
1178 cur
.range
[0], cur
.range
[1],
1179 cur
.file
, cur
.lineno
);
1186 static PGAssign
* pform_make_pgassign(PExpr
*lval
, PExpr
*rval
,
1187 svector
<PExpr
*>*del
,
1188 struct str_pair_t str
)
1190 svector
<PExpr
*>*wires
= new svector
<PExpr
*>(2);
1197 cur
= new PGAssign(wires
);
1199 cur
= new PGAssign(wires
, del
);
1201 cur
->strength0(str
.str0
);
1202 cur
->strength1(str
.str1
);
1204 if (pform_cur_generate
)
1205 pform_cur_generate
->add_gate(cur
);
1207 pform_cur_module
->add_gate(cur
);
1212 void pform_make_pgassign_list(svector
<PExpr
*>*alist
,
1213 svector
<PExpr
*>*del
,
1214 struct str_pair_t str
,
1219 for (unsigned idx
= 0 ; idx
< alist
->count()/2 ; idx
+= 1) {
1220 tmp
= pform_make_pgassign((*alist
)[2*idx
],
1223 FILE_NAME(tmp
, fn
, lineno
);
1228 * this function makes the initial assignment to a register as given
1229 * in the source. It handles the case where a reg variable is assigned
1230 * where it it declared:
1234 * This is equivalent to the combination of statements:
1237 * initial foo = <expr>;
1239 * and that is how it is parsed. This syntax is not part of the
1240 * IEEE1364-1995 standard, but is approved by OVI as enhancement
1243 void pform_make_reginit(const struct vlltype
&li
,
1244 perm_string name
, PExpr
*expr
)
1246 PWire
*cur
= lexical_scope
->wires_find(name
);
1248 VLerror(li
, "internal error: reginit to non-register?");
1253 PEIdent
*lval
= new PEIdent(name
);
1254 FILE_NAME(lval
, li
);
1255 PAssign
*ass
= new PAssign(lval
, expr
);
1257 PProcess
*top
= new PProcess(PProcess::PR_INITIAL
, ass
);
1260 lexical_scope
->behaviors
.push_back(top
);
1264 * This function is used by the parser when I have port definition of
1265 * the form like this:
1267 * input wire signed [7:0] nm;
1269 * The port_type, type, signed_flag and range are known all at once,
1270 * so we can create the PWire object all at once instead of piecemeal
1271 * as is done for the old method.
1273 void pform_module_define_port(const struct vlltype
&li
,
1275 NetNet::PortType port_type
,
1278 svector
<PExpr
*>*range
,
1279 svector
<named_pexpr_t
*>*attr
)
1281 PWire
*cur
= lexical_scope
->wires_find(name
);
1284 msg
<< name
<< " definition conflicts with "
1285 << "definition at " << cur
->get_fileline()
1287 VLerror(msg
.str().c_str());
1292 cur
= new PWire(name
, type
, port_type
, IVL_VT_LOGIC
);
1295 cur
->set_signed(signed_flag
);
1298 cur
->set_range(0, 0, (type
== NetNet::IMPLICIT
) ? SR_PORT
:
1302 assert(range
->count() == 2);
1303 assert((*range
)[0]);
1304 assert((*range
)[1]);
1305 cur
->set_range((*range
)[0], (*range
)[1],
1306 (type
== NetNet::IMPLICIT
) ? SR_PORT
: SR_BOTH
);
1310 for (unsigned idx
= 0 ; idx
< attr
->count() ; idx
+= 1) {
1311 named_pexpr_t
*tmp
= (*attr
)[idx
];
1312 cur
->attributes
[tmp
->name
] = tmp
->parm
;
1315 lexical_scope
->wires
[name
] = cur
;
1319 * This function makes a single signal (a wire, a reg, etc) as
1320 * requested by the parser. The name is unscoped, so I attach the
1321 * current scope to it (with the scoped_name function) and I try to
1322 * resolve it with an existing PWire in the scope.
1324 * The wire might already exist because of an implicit declaration in
1325 * a module port, i.e.:
1327 * module foo (bar...
1331 * The output (or other port direction indicator) may or may not have
1332 * been seen already, so I do not do any checking with it yet. But I
1333 * do check to see if the name has already been declared, as this
1334 * function is called for every declaration.
1338 * this is the basic form of pform_makewire. This takes a single simple
1339 * name, port type, net type, data type, and attributes, and creates
1340 * the variable/net. Other forms of pform_makewire ultimately call
1341 * this one to create the wire and stash it.
1343 void pform_makewire(const vlltype
&li
, perm_string name
,
1344 NetNet::Type type
, NetNet::PortType pt
,
1345 ivl_variable_type_t dt
,
1346 svector
<named_pexpr_t
*>*attr
)
1348 PWire
*cur
= get_wire_in_scope(name
);
1350 // If this is not implicit ("implicit" meaning we don't know
1351 // what the type is yet) then set the type now.
1352 if (cur
&& type
!= NetNet::IMPLICIT
) {
1353 bool rc
= cur
->set_wire_type(type
);
1356 msg
<< name
<< " definition conflicts with "
1357 << "definition at " << cur
->get_fileline()
1359 VLerror(msg
.str().c_str());
1360 cerr
<< "XXXX type=" << type
<<", curtype=" << cur
->get_wire_type() << endl
;
1365 bool new_wire_flag
= false;
1367 new_wire_flag
= true;
1368 cur
= new PWire(name
, type
, pt
, dt
);
1371 FILE_NAME(cur
, li
.text
, li
.first_line
);
1376 flag
= cur
->set_data_type(dt
);
1377 if (flag
== false) {
1378 cerr
<< cur
->get_fileline() << ": internal error: "
1379 << " wire data type handling mismatch. Cannot change "
1380 << cur
->get_data_type()
1381 << " to " << dt
<< "." << endl
;
1383 ivl_assert(*cur
, flag
);
1384 cur
->set_range(0, 0, SR_NET
);
1385 cur
->set_signed(true);
1392 for (unsigned idx
= 0 ; idx
< attr
->count() ; idx
+= 1) {
1393 named_pexpr_t
*tmp
= (*attr
)[idx
];
1394 cur
->attributes
[tmp
->name
] = tmp
->parm
;
1398 if (new_wire_flag
) {
1399 if (pform_cur_generate
)
1400 pform_cur_generate
->wires
[name
] = cur
;
1402 lexical_scope
->wires
[name
] = cur
;
1407 * This form takes a list of names and some type information, and
1408 * generates a bunch of variables/nets. We use the basic
1409 * pform_makewire above.
1411 void pform_makewire(const vlltype
&li
,
1412 svector
<PExpr
*>*range
,
1414 list
<perm_string
>*names
,
1416 NetNet::PortType pt
,
1417 ivl_variable_type_t dt
,
1418 svector
<named_pexpr_t
*>*attr
,
1421 for (list
<perm_string
>::iterator cur
= names
->begin()
1422 ; cur
!= names
->end()
1424 perm_string txt
= *cur
;
1425 pform_makewire(li
, txt
, type
, pt
, dt
, attr
);
1426 /* This has already been done for real variables. */
1427 if (dt
!= IVL_VT_REAL
) {
1428 pform_set_net_range(txt
, range
, signed_flag
, dt
, rt
);
1438 * This form makes nets with delays and continuous assignments.
1440 void pform_makewire(const vlltype
&li
,
1441 svector
<PExpr
*>*range
,
1443 svector
<PExpr
*>*delay
,
1445 net_decl_assign_t
*decls
,
1447 ivl_variable_type_t dt
)
1449 net_decl_assign_t
*first
= decls
->next
;
1453 net_decl_assign_t
*next
= first
->next
;
1455 pform_makewire(li
, first
->name
, type
, NetNet::NOT_A_PORT
, dt
, 0);
1456 /* This has already been done for real variables. */
1457 if (dt
!= IVL_VT_REAL
) {
1458 pform_set_net_range(first
->name
, range
, signed_flag
, dt
,
1462 PWire
*cur
= get_wire_in_scope(first
->name
);
1464 PEIdent
*lval
= new PEIdent(first
->name
);
1465 FILE_NAME(lval
, li
.text
, li
.first_line
);
1466 PGAssign
*ass
= pform_make_pgassign(lval
, first
->expr
,
1468 FILE_NAME(ass
, li
.text
, li
.first_line
);
1476 void pform_set_port_type(perm_string name
, NetNet::PortType pt
,
1477 const char*file
, unsigned lineno
)
1479 PWire
*cur
= lexical_scope
->wires_find(name
);
1481 cur
= new PWire(name
, NetNet::IMPLICIT
, NetNet::PIMPLICIT
, IVL_VT_NO_TYPE
);
1482 FILE_NAME(cur
, file
, lineno
);
1483 lexical_scope
->wires
[name
] = cur
;
1486 switch (cur
->get_port_type()) {
1487 case NetNet::PIMPLICIT
:
1488 if (! cur
->set_port_type(pt
))
1489 VLerror("error setting port direction.");
1492 case NetNet::NOT_A_PORT
:
1493 cerr
<< file
<< ":" << lineno
<< ": error: "
1494 << "port " << name
<< " is not in the port list."
1500 cerr
<< file
<< ":" << lineno
<< ": error: "
1501 << "port " << name
<< " already has a port declaration."
1510 * This function is called by the parser to create task ports. The
1511 * resulting wire (which should be a register) is put into a list to
1512 * be packed into the task parameter list.
1514 * It is possible that the wire (er, register) was already created,
1515 * but we know that if the name matches it is a part of the current
1516 * task, so in that case I just assign direction to it.
1518 * The following example demonstrates some of the issues:
1527 * This function is called when the parser matches the "input a" and
1528 * the "input b" statements. For ``a'', this function is called before
1529 * the wire is declared as a register, so I create the foo.a
1530 * wire. For ``b'', I will find that there is already a foo.b and I
1531 * just set the port direction. In either case, the ``reg a, b''
1532 * statement is caught by the block_item non-terminal and processed
1535 * Ports are implicitly type reg, because it must be possible for the
1536 * port to act as an l-value in a procedural assignment. It is obvious
1537 * for output and inout ports that the type is reg, because the task
1538 * only contains behavior (no structure) to a procedural assignment is
1539 * the *only* way to affect the output. It is less obvious for input
1540 * ports, but in practice an input port receives its value as if by a
1541 * procedural assignment from the calling behavior.
1543 * This function also handles the input ports of function
1544 * definitions. Input ports to function definitions have the same
1545 * constraints as those of tasks, so this works fine. Functions have
1546 * no output or inout ports.
1548 svector
<PWire
*>*pform_make_task_ports(NetNet::PortType pt
,
1549 ivl_variable_type_t vtype
,
1551 svector
<PExpr
*>*range
,
1552 list
<perm_string
>*names
,
1557 svector
<PWire
*>*res
= new svector
<PWire
*>(0);
1558 for (list
<perm_string
>::iterator cur
= names
->begin()
1559 ; cur
!= names
->end() ; cur
++ ) {
1561 perm_string name
= *cur
;
1563 /* Look for a preexisting wire. If it exists, set the
1564 port direction. If not, create it. */
1565 PWire
*curw
= lexical_scope
->wires_find(name
);
1567 curw
->set_port_type(pt
);
1569 curw
= new PWire(name
, NetNet::IMPLICIT_REG
, pt
, vtype
);
1570 FILE_NAME(curw
, file
, lineno
);
1571 lexical_scope
->wires
[name
] = curw
;
1574 curw
->set_signed(signed_flag
);
1576 /* If there is a range involved, it needs to be set. */
1578 curw
->set_range((*range
)[0], (*range
)[1], SR_PORT
);
1580 svector
<PWire
*>*tmp
= new svector
<PWire
*>(*res
, curw
);
1592 void pform_set_attrib(perm_string name
, perm_string key
, char*value
)
1594 if (PWire
*cur
= lexical_scope
->wires_find(name
)) {
1595 cur
->attributes
[key
] = new PEString(value
);
1597 } else if (PGate
*cur
= pform_cur_module
->get_gate(name
)) {
1598 cur
->attributes
[key
] = new PEString(value
);
1602 VLerror("Unable to match name for setting attribute.");
1608 * Set the attribute of a TYPE. This is different from an object in
1609 * that this applies to every instantiation of the given type.
1611 void pform_set_type_attrib(perm_string name
, const string
&key
,
1614 map
<perm_string
,PUdp
*>::const_iterator udp
= pform_primitives
.find(name
);
1615 if (udp
== pform_primitives
.end()) {
1616 VLerror("type name is not (yet) defined.");
1621 (*udp
).second
->attributes
[key
] = new PEString(value
);
1625 * This function attaches a memory index range to an existing
1626 * register. (The named wire must be a register.
1628 void pform_set_reg_idx(perm_string name
, PExpr
*l
, PExpr
*r
)
1631 if (pform_cur_generate
) {
1632 cur
= pform_cur_generate
->get_wire(name
);
1634 cur
= lexical_scope
->wires_find(name
);
1637 VLerror("internal error: name is not a valid memory for index.");
1641 cur
->set_memory_idx(l
, r
);
1644 void pform_set_parameter(perm_string name
, bool signed_flag
,
1645 svector
<PExpr
*>*range
, PExpr
*expr
,
1646 const char*file
, unsigned lineno
)
1649 pform_cur_module
->parameters
[name
].expr
= expr
;
1652 assert(range
->count() == 2);
1653 assert((*range
)[0]);
1654 assert((*range
)[1]);
1655 pform_cur_module
->parameters
[name
].msb
= (*range
)[0];
1656 pform_cur_module
->parameters
[name
].lsb
= (*range
)[1];
1658 pform_cur_module
->parameters
[name
].msb
= 0;
1659 pform_cur_module
->parameters
[name
].lsb
= 0;
1661 pform_cur_module
->parameters
[name
].signed_flag
= signed_flag
;
1662 pform_cur_module
->parameters
[name
].file
= filename_strings
.make(file
);
1663 pform_cur_module
->parameters
[name
].lineno
= lineno
;
1665 pform_cur_module
->param_names
.push_back(name
);
1668 void pform_set_localparam(perm_string name
, bool signed_flag
,
1669 svector
<PExpr
*>*range
, PExpr
*expr
,
1670 const char*file
, unsigned lineno
)
1673 pform_cur_module
->localparams
[name
].expr
= expr
;
1676 assert(range
->count() == 2);
1677 assert((*range
)[0]);
1678 assert((*range
)[1]);
1679 pform_cur_module
->localparams
[name
].msb
= (*range
)[0];
1680 pform_cur_module
->localparams
[name
].lsb
= (*range
)[1];
1682 pform_cur_module
->localparams
[name
].msb
= 0;
1683 pform_cur_module
->localparams
[name
].lsb
= 0;
1685 pform_cur_module
->localparams
[name
].signed_flag
= signed_flag
;
1686 pform_cur_module
->localparams
[name
].file
= filename_strings
.make(file
);
1687 pform_cur_module
->localparams
[name
].lineno
= lineno
;
1690 void pform_set_specparam(perm_string name
, PExpr
*expr
)
1693 pform_cur_module
->specparams
[name
] = expr
;
1696 void pform_set_defparam(const pform_name_t
&name
, PExpr
*expr
)
1699 pform_cur_module
->defparms
[name
] = expr
;
1705 extern PSpecPath
* pform_make_specify_path(const struct vlltype
&li
,
1706 list
<perm_string
>*src
, char pol
,
1707 bool full_flag
, list
<perm_string
>*dst
)
1709 PSpecPath
*path
= new PSpecPath(src
->size(), dst
->size());
1710 FILE_NAME(path
, li
.text
, li
.first_line
);
1713 list
<perm_string
>::const_iterator cur
;
1716 for (idx
= 0, cur
= src
->begin() ; cur
!= src
->end() ; idx
++, cur
++) {
1717 path
->src
[idx
] = *cur
;
1719 assert(idx
== path
->src
.size());
1722 for (idx
= 0, cur
= dst
->begin() ; cur
!= dst
->end() ; idx
++, cur
++) {
1723 path
->dst
[idx
] = *cur
;
1725 assert(idx
== path
->dst
.size());
1731 extern PSpecPath
*pform_make_specify_edge_path(const struct vlltype
&li
,
1732 int edge_flag
, /*posedge==true */
1733 list
<perm_string
>*src
, char pol
,
1734 bool full_flag
, list
<perm_string
>*dst
,
1735 PExpr
*data_source_expression
)
1737 PSpecPath
*tmp
= pform_make_specify_path(li
, src
, pol
, full_flag
, dst
);
1738 tmp
->edge
= edge_flag
;
1739 tmp
->data_source_expression
= data_source_expression
;
1743 extern PSpecPath
* pform_assign_path_delay(PSpecPath
*path
, svector
<PExpr
*>*del
)
1748 assert(path
->delays
.size() == 0);
1750 path
->delays
.resize(del
->count());
1751 for (unsigned idx
= 0 ; idx
< path
->delays
.size() ; idx
+= 1)
1752 path
->delays
[idx
] = (*del
)[idx
];
1760 extern void pform_module_specify_path(PSpecPath
*obj
)
1764 pform_cur_module
->specify_paths
.push_back(obj
);
1767 void pform_set_port_type(const struct vlltype
&li
,
1768 list
<perm_string
>*names
,
1769 svector
<PExpr
*>*range
,
1771 NetNet::PortType pt
)
1773 for (list
<perm_string
>::iterator cur
= names
->begin()
1774 ; cur
!= names
->end()
1776 perm_string txt
= *cur
;
1777 pform_set_port_type(txt
, pt
, li
.text
, li
.first_line
);
1778 pform_set_net_range(txt
, range
, signed_flag
, IVL_VT_NO_TYPE
,
1787 static void pform_set_reg_integer(perm_string name
)
1789 PWire
*cur
= lexical_scope
->wires_find(name
);
1791 cur
= new PWire(name
, NetNet::INTEGER
,
1794 cur
->set_signed(true);
1795 lexical_scope
->wires
[name
] = cur
;
1797 bool rc
= cur
->set_wire_type(NetNet::INTEGER
);
1799 cur
->set_data_type(IVL_VT_LOGIC
);
1800 cur
->set_signed(true);
1804 cur
->set_range(new PENumber(new verinum(integer_width
-1, integer_width
)),
1805 new PENumber(new verinum((uint64_t)0, integer_width
)),
1807 cur
->set_signed(true);
1810 void pform_set_reg_integer(list
<perm_string
>*names
)
1812 for (list
<perm_string
>::iterator cur
= names
->begin()
1813 ; cur
!= names
->end()
1815 perm_string txt
= *cur
;
1816 pform_set_reg_integer(txt
);
1821 static void pform_set_reg_time(perm_string name
)
1823 PWire
*cur
= lexical_scope
->wires_find(name
);
1825 cur
= new PWire(name
, NetNet::REG
, NetNet::NOT_A_PORT
, IVL_VT_LOGIC
);
1826 lexical_scope
->wires
[name
] = cur
;
1828 bool rc
= cur
->set_wire_type(NetNet::REG
);
1830 rc
= cur
->set_data_type(IVL_VT_LOGIC
);
1835 cur
->set_range(new PENumber(new verinum(TIME_WIDTH
-1, integer_width
)),
1836 new PENumber(new verinum((uint64_t)0, integer_width
)),
1840 void pform_set_reg_time(list
<perm_string
>*names
)
1842 for (list
<perm_string
>::iterator cur
= names
->begin()
1843 ; cur
!= names
->end()
1845 perm_string txt
= *cur
;
1846 pform_set_reg_time(txt
);
1851 svector
<PWire
*>* pform_make_udp_input_ports(list
<perm_string
>*names
)
1853 svector
<PWire
*>*out
= new svector
<PWire
*>(names
->size());
1856 for (list
<perm_string
>::iterator cur
= names
->begin()
1857 ; cur
!= names
->end()
1859 perm_string txt
= *cur
;
1860 PWire
*pp
= new PWire(txt
,
1872 PProcess
* pform_make_behavior(PProcess::Type type
, Statement
*st
,
1873 svector
<named_pexpr_t
*>*attr
)
1875 PProcess
*pp
= new PProcess(type
, st
);
1878 for (unsigned idx
= 0 ; idx
< attr
->count() ; idx
+= 1) {
1879 named_pexpr_t
*tmp
= (*attr
)[idx
];
1880 pp
->attributes
[tmp
->name
] = tmp
->parm
;
1885 if (pform_cur_generate
)
1886 pform_cur_generate
->add_behavior(pp
);
1888 pform_cur_module
->behaviors
.push_back(pp
);
1895 extern void reset_lexor();
1897 int pform_parse(const char*path
, FILE*file
)
1902 if (strcmp(path
, "-") == 0)
1905 vl_input
= fopen(path
, "r");
1906 if (vl_input
== 0) {
1907 cerr
<< "Unable to open " <<vl_file
<< "." << endl
;
1924 cerr
<< "I give up." << endl
;
1931 void pform_error_nested_modules()
1933 assert( pform_cur_module
!= 0 );
1934 cerr
<< pform_cur_module
->get_fileline() << ": error: original module "
1935 "(" << pform_cur_module
->mod_name() << ") defined here." << endl
;