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Fix correct reset value for ARM CP15 c1 auxiliary control register
[qemu/mini2440/sniper_sniper_test.git] / target-ppc / translate.c
blobe400cf2da15e8a4d422c9871960605cfede28316
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31 #include "host-utils.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define DO_SINGLE_STEP
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
45
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DISAS(...) do { } while (0)
50 #endif
51 /*****************************************************************************/
52 /* Code translation helpers */
53
54 /* global register indexes */
55 static TCGv_ptr cpu_env;
56 static char cpu_reg_names[10*3 + 22*4 /* GPR */
57 #if !defined(TARGET_PPC64)
58 + 10*4 + 22*5 /* SPE GPRh */
59 #endif
60 + 10*4 + 22*5 /* FPR */
61 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 + 8*5 /* CRF */];
63 static TCGv cpu_gpr[32];
64 #if !defined(TARGET_PPC64)
65 static TCGv cpu_gprh[32];
66 #endif
67 static TCGv_i64 cpu_fpr[32];
68 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
69 static TCGv_i32 cpu_crf[8];
70 static TCGv cpu_nip;
71 static TCGv cpu_msr;
72 static TCGv cpu_ctr;
73 static TCGv cpu_lr;
74 static TCGv cpu_xer;
75 static TCGv cpu_reserve;
76 static TCGv_i32 cpu_fpscr;
77 static TCGv_i32 cpu_access_type;
78
79 #include "gen-icount.h"
80
81 void ppc_translate_init(void)
82 {
83 int i;
84 char* p;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93
94 for (i = 0; i < 8; i++) {
95 sprintf(p, "crf%d", i);
96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
98 p += 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 sprintf(p, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 #if !defined(TARGET_PPC64)
107 sprintf(p, "r%dH", i);
108 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, gprh[i]), p);
110 p += (i < 10) ? 4 : 5;
111 #endif
112
113 sprintf(p, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117
118 sprintf(p, "avr%dH", i);
119 #ifdef WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127
128 sprintf(p, "avr%dL", i);
129 #ifdef WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132 #else
133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[0]), p);
135 #endif
136 p += (i < 10) ? 6 : 7;
137 }
138
139 cpu_nip = tcg_global_mem_new(TCG_AREG0,
140 offsetof(CPUState, nip), "nip");
141
142 cpu_msr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, msr), "msr");
144
145 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, ctr), "ctr");
147
148 cpu_lr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, lr), "lr");
150
151 cpu_xer = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, xer), "xer");
153
154 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, reserve), "reserve");
156
157 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, fpscr), "fpscr");
159
160 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, access_type), "access_type");
162
163 /* register helpers */
164 #define GEN_HELPER 2
165 #include "helper.h"
166
167 done_init = 1;
168 }
169
170 /* internal defines */
171 typedef struct DisasContext {
172 struct TranslationBlock *tb;
173 target_ulong nip;
174 uint32_t opcode;
175 uint32_t exception;
176 /* Routine used to access memory */
177 int mem_idx;
178 int access_type;
179 /* Translation flags */
180 int le_mode;
181 #if defined(TARGET_PPC64)
182 int sf_mode;
183 #endif
184 int fpu_enabled;
185 int altivec_enabled;
186 int spe_enabled;
187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
188 int singlestep_enabled;
189 } DisasContext;
190
191 struct opc_handler_t {
192 /* invalid bits */
193 uint32_t inval;
194 /* instruction type */
195 uint64_t type;
196 /* handler */
197 void (*handler)(DisasContext *ctx);
198 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
199 const char *oname;
200 #endif
201 #if defined(DO_PPC_STATISTICS)
202 uint64_t count;
203 #endif
204 };
205
206 static always_inline void gen_reset_fpstatus (void)
207 {
208 #ifdef CONFIG_SOFTFLOAT
209 gen_helper_reset_fpstatus();
210 #endif
211 }
212
213 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
214 {
215 TCGv_i32 t0 = tcg_temp_new_i32();
216
217 if (set_fprf != 0) {
218 /* This case might be optimized later */
219 tcg_gen_movi_i32(t0, 1);
220 gen_helper_compute_fprf(t0, arg, t0);
221 if (unlikely(set_rc)) {
222 tcg_gen_mov_i32(cpu_crf[1], t0);
223 }
224 gen_helper_float_check_status();
225 } else if (unlikely(set_rc)) {
226 /* We always need to compute fpcc */
227 tcg_gen_movi_i32(t0, 0);
228 gen_helper_compute_fprf(t0, arg, t0);
229 tcg_gen_mov_i32(cpu_crf[1], t0);
230 }
231
232 tcg_temp_free_i32(t0);
233 }
234
235 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
236 {
237 if (ctx->access_type != access_type) {
238 tcg_gen_movi_i32(cpu_access_type, access_type);
239 ctx->access_type = access_type;
240 }
241 }
242
243 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
244 {
245 #if defined(TARGET_PPC64)
246 if (ctx->sf_mode)
247 tcg_gen_movi_tl(cpu_nip, nip);
248 else
249 #endif
250 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
251 }
252
253 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
254 {
255 TCGv_i32 t0, t1;
256 if (ctx->exception == POWERPC_EXCP_NONE) {
257 gen_update_nip(ctx, ctx->nip);
258 }
259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
261 gen_helper_raise_exception_err(t0, t1);
262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
264 ctx->exception = (excp);
265 }
266
267 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
268 {
269 TCGv_i32 t0;
270 if (ctx->exception == POWERPC_EXCP_NONE) {
271 gen_update_nip(ctx, ctx->nip);
272 }
273 t0 = tcg_const_i32(excp);
274 gen_helper_raise_exception(t0);
275 tcg_temp_free_i32(t0);
276 ctx->exception = (excp);
277 }
278
279 static always_inline void gen_debug_exception (DisasContext *ctx)
280 {
281 TCGv_i32 t0;
282
283 if (ctx->exception != POWERPC_EXCP_BRANCH)
284 gen_update_nip(ctx, ctx->nip);
285 t0 = tcg_const_i32(EXCP_DEBUG);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288 }
289
290 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
291 {
292 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
293 }
294
295 /* Stop translation */
296 static always_inline void gen_stop_exception (DisasContext *ctx)
297 {
298 gen_update_nip(ctx, ctx->nip);
299 ctx->exception = POWERPC_EXCP_STOP;
300 }
301
302 /* No need to update nip here, as execution flow will change */
303 static always_inline void gen_sync_exception (DisasContext *ctx)
304 {
305 ctx->exception = POWERPC_EXCP_SYNC;
306 }
307
308 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
309 static void gen_##name (DisasContext *ctx); \
310 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
311 static void gen_##name (DisasContext *ctx)
312
313 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
314 static void gen_##name (DisasContext *ctx); \
315 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
316 static void gen_##name (DisasContext *ctx)
317
318 typedef struct opcode_t {
319 unsigned char opc1, opc2, opc3;
320 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
321 unsigned char pad[5];
322 #else
323 unsigned char pad[1];
324 #endif
325 opc_handler_t handler;
326 const char *oname;
327 } opcode_t;
328
329 /*****************************************************************************/
330 /*** Instruction decoding ***/
331 #define EXTRACT_HELPER(name, shift, nb) \
332 static always_inline uint32_t name (uint32_t opcode) \
333 { \
334 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
335 }
336
337 #define EXTRACT_SHELPER(name, shift, nb) \
338 static always_inline int32_t name (uint32_t opcode) \
339 { \
340 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
341 }
342
343 /* Opcode part 1 */
344 EXTRACT_HELPER(opc1, 26, 6);
345 /* Opcode part 2 */
346 EXTRACT_HELPER(opc2, 1, 5);
347 /* Opcode part 3 */
348 EXTRACT_HELPER(opc3, 6, 5);
349 /* Update Cr0 flags */
350 EXTRACT_HELPER(Rc, 0, 1);
351 /* Destination */
352 EXTRACT_HELPER(rD, 21, 5);
353 /* Source */
354 EXTRACT_HELPER(rS, 21, 5);
355 /* First operand */
356 EXTRACT_HELPER(rA, 16, 5);
357 /* Second operand */
358 EXTRACT_HELPER(rB, 11, 5);
359 /* Third operand */
360 EXTRACT_HELPER(rC, 6, 5);
361 /*** Get CRn ***/
362 EXTRACT_HELPER(crfD, 23, 3);
363 EXTRACT_HELPER(crfS, 18, 3);
364 EXTRACT_HELPER(crbD, 21, 5);
365 EXTRACT_HELPER(crbA, 16, 5);
366 EXTRACT_HELPER(crbB, 11, 5);
367 /* SPR / TBL */
368 EXTRACT_HELPER(_SPR, 11, 10);
369 static always_inline uint32_t SPR (uint32_t opcode)
370 {
371 uint32_t sprn = _SPR(opcode);
372
373 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
374 }
375 /*** Get constants ***/
376 EXTRACT_HELPER(IMM, 12, 8);
377 /* 16 bits signed immediate value */
378 EXTRACT_SHELPER(SIMM, 0, 16);
379 /* 16 bits unsigned immediate value */
380 EXTRACT_HELPER(UIMM, 0, 16);
381 /* 5 bits signed immediate value */
382 EXTRACT_HELPER(SIMM5, 16, 5);
383 /* 5 bits signed immediate value */
384 EXTRACT_HELPER(UIMM5, 16, 5);
385 /* Bit count */
386 EXTRACT_HELPER(NB, 11, 5);
387 /* Shift count */
388 EXTRACT_HELPER(SH, 11, 5);
389 /* Vector shift count */
390 EXTRACT_HELPER(VSH, 6, 4);
391 /* Mask start */
392 EXTRACT_HELPER(MB, 6, 5);
393 /* Mask end */
394 EXTRACT_HELPER(ME, 1, 5);
395 /* Trap operand */
396 EXTRACT_HELPER(TO, 21, 5);
397
398 EXTRACT_HELPER(CRM, 12, 8);
399 EXTRACT_HELPER(FM, 17, 8);
400 EXTRACT_HELPER(SR, 16, 4);
401 EXTRACT_HELPER(FPIMM, 12, 4);
402
403 /*** Jump target decoding ***/
404 /* Displacement */
405 EXTRACT_SHELPER(d, 0, 16);
406 /* Immediate address */
407 static always_inline target_ulong LI (uint32_t opcode)
408 {
409 return (opcode >> 0) & 0x03FFFFFC;
410 }
411
412 static always_inline uint32_t BD (uint32_t opcode)
413 {
414 return (opcode >> 0) & 0xFFFC;
415 }
416
417 EXTRACT_HELPER(BO, 21, 5);
418 EXTRACT_HELPER(BI, 16, 5);
419 /* Absolute/relative address */
420 EXTRACT_HELPER(AA, 1, 1);
421 /* Link */
422 EXTRACT_HELPER(LK, 0, 1);
423
424 /* Create a mask between <start> and <end> bits */
425 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
426 {
427 target_ulong ret;
428
429 #if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
431 ret = UINT64_MAX << (63 - end);
432 } else if (likely(end == 63)) {
433 ret = UINT64_MAX >> start;
434 }
435 #else
436 if (likely(start == 0)) {
437 ret = UINT32_MAX << (31 - end);
438 } else if (likely(end == 31)) {
439 ret = UINT32_MAX >> start;
440 }
441 #endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
448
449 return ret;
450 }
451
452 /*****************************************************************************/
453 /* PowerPC Instructions types definitions */
454 enum {
455 PPC_NONE = 0x0000000000000000ULL,
456 /* PowerPC base instructions set */
457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
459 #define PPC_INTEGER PPC_INSNS_BASE
460 /* flow control instructions */
461 #define PPC_FLOW PPC_INSNS_BASE
462 /* virtual memory instructions */
463 #define PPC_MEM PPC_INSNS_BASE
464 /* ld/st with reservation instructions */
465 #define PPC_RES PPC_INSNS_BASE
466 /* spr/msr access instructions */
467 #define PPC_MISC PPC_INSNS_BASE
468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
470 PPC_POWER = 0x0000000000000002ULL,
471 /* POWER2 instruction set extension */
472 PPC_POWER2 = 0x0000000000000004ULL,
473 /* Power RTC support */
474 PPC_POWER_RTC = 0x0000000000000008ULL,
475 /* Power-to-PowerPC bridge (601) */
476 PPC_POWER_BR = 0x0000000000000010ULL,
477 /* 64 bits PowerPC instruction set */
478 PPC_64B = 0x0000000000000020ULL,
479 /* New 64 bits extensions (PowerPC 2.0x) */
480 PPC_64BX = 0x0000000000000040ULL,
481 /* 64 bits hypervisor extensions */
482 PPC_64H = 0x0000000000000080ULL,
483 /* New wait instruction (PowerPC 2.0x) */
484 PPC_WAIT = 0x0000000000000100ULL,
485 /* Time base mftb instruction */
486 PPC_MFTB = 0x0000000000000200ULL,
487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
490 PPC_602_SPEC = 0x0000000000000400ULL,
491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
513 /* PowerPC 2.03 SPE extension */
514 PPC_SPE = 0x0000000002000000ULL,
515 /* PowerPC 2.03 SPE single-precision floating-point extension */
516 PPC_SPE_SINGLE = 0x0000000004000000ULL,
517 /* PowerPC 2.03 SPE double-precision floating-point extension */
518 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
519
520 /* Optional memory control instructions */
521 PPC_MEM_TLBIA = 0x0000000010000000ULL,
522 PPC_MEM_TLBIE = 0x0000000020000000ULL,
523 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
524 /* sync instruction */
525 PPC_MEM_SYNC = 0x0000000080000000ULL,
526 /* eieio instruction */
527 PPC_MEM_EIEIO = 0x0000000100000000ULL,
528
529 /* Cache control instructions */
530 PPC_CACHE = 0x0000000200000000ULL,
531 /* icbi instruction */
532 PPC_CACHE_ICBI = 0x0000000400000000ULL,
533 /* dcbz instruction with fixed cache line size */
534 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
535 /* dcbz instruction with tunable cache line size */
536 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
537 /* dcba instruction */
538 PPC_CACHE_DCBA = 0x0000002000000000ULL,
539 /* Freescale cache locking instructions */
540 PPC_CACHE_LOCK = 0x0000004000000000ULL,
541
542 /* MMU related extensions */
543 /* external control instructions */
544 PPC_EXTERN = 0x0000010000000000ULL,
545 /* segment register access instructions */
546 PPC_SEGMENT = 0x0000020000000000ULL,
547 /* PowerPC 6xx TLB management instructions */
548 PPC_6xx_TLB = 0x0000040000000000ULL,
549 /* PowerPC 74xx TLB management instructions */
550 PPC_74xx_TLB = 0x0000080000000000ULL,
551 /* PowerPC 40x TLB management instructions */
552 PPC_40x_TLB = 0x0000100000000000ULL,
553 /* segment register access instructions for PowerPC 64 "bridge" */
554 PPC_SEGMENT_64B = 0x0000200000000000ULL,
555 /* SLB management */
556 PPC_SLBI = 0x0000400000000000ULL,
557
558 /* Embedded PowerPC dedicated instructions */
559 PPC_WRTEE = 0x0001000000000000ULL,
560 /* PowerPC 40x exception model */
561 PPC_40x_EXCP = 0x0002000000000000ULL,
562 /* PowerPC 405 Mac instructions */
563 PPC_405_MAC = 0x0004000000000000ULL,
564 /* PowerPC 440 specific instructions */
565 PPC_440_SPEC = 0x0008000000000000ULL,
566 /* BookE (embedded) PowerPC specification */
567 PPC_BOOKE = 0x0010000000000000ULL,
568 /* mfapidi instruction */
569 PPC_MFAPIDI = 0x0020000000000000ULL,
570 /* tlbiva instruction */
571 PPC_TLBIVA = 0x0040000000000000ULL,
572 /* tlbivax instruction */
573 PPC_TLBIVAX = 0x0080000000000000ULL,
574 /* PowerPC 4xx dedicated instructions */
575 PPC_4xx_COMMON = 0x0100000000000000ULL,
576 /* PowerPC 40x ibct instructions */
577 PPC_40x_ICBT = 0x0200000000000000ULL,
578 /* rfmci is not implemented in all BookE PowerPC */
579 PPC_RFMCI = 0x0400000000000000ULL,
580 /* rfdi instruction */
581 PPC_RFDI = 0x0800000000000000ULL,
582 /* DCR accesses */
583 PPC_DCR = 0x1000000000000000ULL,
584 /* DCR extended accesse */
585 PPC_DCRX = 0x2000000000000000ULL,
586 /* user-mode DCR access, implemented in PowerPC 460 */
587 PPC_DCRUX = 0x4000000000000000ULL,
588 };
589
590 /*****************************************************************************/
591 /* PowerPC instructions table */
592 #if HOST_LONG_BITS == 64
593 #define OPC_ALIGN 8
594 #else
595 #define OPC_ALIGN 4
596 #endif
597 #if defined(__APPLE__)
598 #define OPCODES_SECTION \
599 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
600 #else
601 #define OPCODES_SECTION \
602 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
603 #endif
604
605 #if defined(DO_PPC_STATISTICS)
606 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
607 extern opcode_t opc_##name; \
608 OPCODES_SECTION opcode_t opc_##name = { \
609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
612 .pad = { 0, }, \
613 .handler = { \
614 .inval = invl, \
615 .type = _typ, \
616 .handler = &gen_##name, \
617 .oname = stringify(name), \
618 }, \
619 .oname = stringify(name), \
620 }
621 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
622 OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = invl, \
629 .type = _typ, \
630 .handler = &gen_##name, \
631 .oname = onam, \
632 }, \
633 .oname = onam, \
634 }
635 #else
636 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
637 extern opcode_t opc_##name; \
638 OPCODES_SECTION opcode_t opc_##name = { \
639 .opc1 = op1, \
640 .opc2 = op2, \
641 .opc3 = op3, \
642 .pad = { 0, }, \
643 .handler = { \
644 .inval = invl, \
645 .type = _typ, \
646 .handler = &gen_##name, \
647 }, \
648 .oname = stringify(name), \
649 }
650 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
651 extern opcode_t opc_##name; \
652 OPCODES_SECTION opcode_t opc_##name = { \
653 .opc1 = op1, \
654 .opc2 = op2, \
655 .opc3 = op3, \
656 .pad = { 0, }, \
657 .handler = { \
658 .inval = invl, \
659 .type = _typ, \
660 .handler = &gen_##name, \
661 }, \
662 .oname = onam, \
663 }
664 #endif
665
666 #define GEN_OPCODE_MARK(name) \
667 extern opcode_t opc_##name; \
668 OPCODES_SECTION opcode_t opc_##name = { \
669 .opc1 = 0xFF, \
670 .opc2 = 0xFF, \
671 .opc3 = 0xFF, \
672 .pad = { 0, }, \
673 .handler = { \
674 .inval = 0x00000000, \
675 .type = 0x00, \
676 .handler = NULL, \
677 }, \
678 .oname = stringify(name), \
679 }
680
681 /* SPR load/store helpers */
682 static always_inline void gen_load_spr(TCGv t, int reg)
683 {
684 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685 }
686
687 static always_inline void gen_store_spr(int reg, TCGv t)
688 {
689 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
690 }
691
692 /* Start opcode list */
693 GEN_OPCODE_MARK(start);
694
695 /* Invalid instruction */
696 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697 {
698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
699 }
700
701 static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
703 .type = PPC_NONE,
704 .handler = gen_invalid,
705 };
706
707 /*** Integer comparison ***/
708
709 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
710 {
711 int l1, l2, l3;
712
713 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
714 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
715 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
716
717 l1 = gen_new_label();
718 l2 = gen_new_label();
719 l3 = gen_new_label();
720 if (s) {
721 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
723 } else {
724 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
725 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
726 }
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
728 tcg_gen_br(l3);
729 gen_set_label(l1);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
731 tcg_gen_br(l3);
732 gen_set_label(l2);
733 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
734 gen_set_label(l3);
735 }
736
737 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
738 {
739 TCGv t0 = tcg_const_local_tl(arg1);
740 gen_op_cmp(arg0, t0, s, crf);
741 tcg_temp_free(t0);
742 }
743
744 #if defined(TARGET_PPC64)
745 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
746 {
747 TCGv t0, t1;
748 t0 = tcg_temp_local_new();
749 t1 = tcg_temp_local_new();
750 if (s) {
751 tcg_gen_ext32s_tl(t0, arg0);
752 tcg_gen_ext32s_tl(t1, arg1);
753 } else {
754 tcg_gen_ext32u_tl(t0, arg0);
755 tcg_gen_ext32u_tl(t1, arg1);
756 }
757 gen_op_cmp(t0, t1, s, crf);
758 tcg_temp_free(t1);
759 tcg_temp_free(t0);
760 }
761
762 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
763 {
764 TCGv t0 = tcg_const_local_tl(arg1);
765 gen_op_cmp32(arg0, t0, s, crf);
766 tcg_temp_free(t0);
767 }
768 #endif
769
770 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
771 {
772 #if defined(TARGET_PPC64)
773 if (!(ctx->sf_mode))
774 gen_op_cmpi32(reg, 0, 1, 0);
775 else
776 #endif
777 gen_op_cmpi(reg, 0, 1, 0);
778 }
779
780 /* cmp */
781 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
782 {
783 #if defined(TARGET_PPC64)
784 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
785 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 else
788 #endif
789 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
790 1, crfD(ctx->opcode));
791 }
792
793 /* cmpi */
794 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
795 {
796 #if defined(TARGET_PPC64)
797 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 else
801 #endif
802 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
803 1, crfD(ctx->opcode));
804 }
805
806 /* cmpl */
807 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
808 {
809 #if defined(TARGET_PPC64)
810 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
811 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 else
814 #endif
815 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
816 0, crfD(ctx->opcode));
817 }
818
819 /* cmpli */
820 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
821 {
822 #if defined(TARGET_PPC64)
823 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
824 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 else
827 #endif
828 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
829 0, crfD(ctx->opcode));
830 }
831
832 /* isel (PowerPC 2.03 specification) */
833 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
834 {
835 int l1, l2;
836 uint32_t bi = rC(ctx->opcode);
837 uint32_t mask;
838 TCGv_i32 t0;
839
840 l1 = gen_new_label();
841 l2 = gen_new_label();
842
843 mask = 1 << (3 - (bi & 0x03));
844 t0 = tcg_temp_new_i32();
845 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
847 if (rA(ctx->opcode) == 0)
848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
849 else
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_br(l2);
852 gen_set_label(l1);
853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
854 gen_set_label(l2);
855 tcg_temp_free_i32(t0);
856 }
857
858 /*** Integer arithmetic ***/
859
860 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
861 {
862 int l1;
863 TCGv t0;
864
865 l1 = gen_new_label();
866 /* Start with XER OV disabled, the most likely case */
867 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
868 t0 = tcg_temp_local_new();
869 tcg_gen_xor_tl(t0, arg0, arg1);
870 #if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873 #endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 tcg_gen_xor_tl(t0, arg1, arg2);
879 #if defined(TARGET_PPC64)
880 if (!ctx->sf_mode)
881 tcg_gen_ext32s_tl(t0, t0);
882 #endif
883 if (sub)
884 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
885 else
886 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
887 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
888 gen_set_label(l1);
889 tcg_temp_free(t0);
890 }
891
892 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
893 {
894 int l1 = gen_new_label();
895
896 #if defined(TARGET_PPC64)
897 if (!(ctx->sf_mode)) {
898 TCGv t0, t1;
899 t0 = tcg_temp_new();
900 t1 = tcg_temp_new();
901
902 tcg_gen_ext32u_tl(t0, arg1);
903 tcg_gen_ext32u_tl(t1, arg2);
904 if (sub) {
905 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
906 } else {
907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
908 }
909 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
910 gen_set_label(l1);
911 tcg_temp_free(t0);
912 tcg_temp_free(t1);
913 } else
914 #endif
915 {
916 if (sub) {
917 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
918 } else {
919 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
920 }
921 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
922 gen_set_label(l1);
923 }
924 }
925
926 /* Common add function */
927 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
928 int add_ca, int compute_ca, int compute_ov)
929 {
930 TCGv t0, t1;
931
932 if ((!compute_ca && !compute_ov) ||
933 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
934 t0 = ret;
935 } else {
936 t0 = tcg_temp_local_new();
937 }
938
939 if (add_ca) {
940 t1 = tcg_temp_local_new();
941 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
942 tcg_gen_shri_tl(t1, t1, XER_CA);
943 }
944
945 if (compute_ca && compute_ov) {
946 /* Start with XER CA and OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
948 } else if (compute_ca) {
949 /* Start with XER CA disabled, the most likely case */
950 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
951 } else if (compute_ov) {
952 /* Start with XER OV disabled, the most likely case */
953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
954 }
955
956 tcg_gen_add_tl(t0, arg1, arg2);
957
958 if (compute_ca) {
959 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
960 }
961 if (add_ca) {
962 tcg_gen_add_tl(t0, t0, t1);
963 gen_op_arith_compute_ca(ctx, t0, t1, 0);
964 tcg_temp_free(t1);
965 }
966 if (compute_ov) {
967 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
968 }
969
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, t0);
972
973 if (!TCGV_EQUAL(t0, ret)) {
974 tcg_gen_mov_tl(ret, t0);
975 tcg_temp_free(t0);
976 }
977 }
978 /* Add functions with two operands */
979 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
980 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
981 { \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 add_ca, compute_ca, compute_ov); \
985 }
986 /* Add functions with one operand and one immediate */
987 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
988 add_ca, compute_ca, compute_ov) \
989 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
990 { \
991 TCGv t0 = tcg_const_local_tl(const_val); \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], t0, \
994 add_ca, compute_ca, compute_ov); \
995 tcg_temp_free(t0); \
996 }
997
998 /* add add. addo addo. */
999 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1000 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1001 /* addc addc. addco addco. */
1002 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1003 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1004 /* adde adde. addeo addeo. */
1005 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1006 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1007 /* addme addme. addmeo addmeo. */
1008 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1009 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1010 /* addze addze. addzeo addzeo.*/
1011 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1012 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1013 /* addi */
1014 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1015 {
1016 target_long simm = SIMM(ctx->opcode);
1017
1018 if (rA(ctx->opcode) == 0) {
1019 /* li case */
1020 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1021 } else {
1022 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1023 }
1024 }
1025 /* addic addic.*/
1026 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1027 int compute_Rc0)
1028 {
1029 target_long simm = SIMM(ctx->opcode);
1030
1031 /* Start with XER CA and OV disabled, the most likely case */
1032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1033
1034 if (likely(simm != 0)) {
1035 TCGv t0 = tcg_temp_local_new();
1036 tcg_gen_addi_tl(t0, arg1, simm);
1037 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1038 tcg_gen_mov_tl(ret, t0);
1039 tcg_temp_free(t0);
1040 } else {
1041 tcg_gen_mov_tl(ret, arg1);
1042 }
1043 if (compute_Rc0) {
1044 gen_set_Rc0(ctx, ret);
1045 }
1046 }
1047 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1048 {
1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1050 }
1051 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1052 {
1053 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1054 }
1055 /* addis */
1056 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1057 {
1058 target_long simm = SIMM(ctx->opcode);
1059
1060 if (rA(ctx->opcode) == 0) {
1061 /* lis case */
1062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1063 } else {
1064 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1065 }
1066 }
1067
1068 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1069 int sign, int compute_ov)
1070 {
1071 int l1 = gen_new_label();
1072 int l2 = gen_new_label();
1073 TCGv_i32 t0 = tcg_temp_local_new_i32();
1074 TCGv_i32 t1 = tcg_temp_local_new_i32();
1075
1076 tcg_gen_trunc_tl_i32(t0, arg1);
1077 tcg_gen_trunc_tl_i32(t1, arg2);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1079 if (sign) {
1080 int l3 = gen_new_label();
1081 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1082 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1083 gen_set_label(l3);
1084 tcg_gen_div_i32(t0, t0, t1);
1085 } else {
1086 tcg_gen_divu_i32(t0, t0, t1);
1087 }
1088 if (compute_ov) {
1089 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1090 }
1091 tcg_gen_br(l2);
1092 gen_set_label(l1);
1093 if (sign) {
1094 tcg_gen_sari_i32(t0, t0, 31);
1095 } else {
1096 tcg_gen_movi_i32(t0, 0);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1100 }
1101 gen_set_label(l2);
1102 tcg_gen_extu_i32_tl(ret, t0);
1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, ret);
1107 }
1108 /* Div functions */
1109 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1110 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1111 { \
1112 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115 }
1116 /* divwu divwu. divwuo divwuo. */
1117 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1118 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1119 /* divw divw. divwo divwo. */
1120 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1121 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1122 #if defined(TARGET_PPC64)
1123 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1124 int sign, int compute_ov)
1125 {
1126 int l1 = gen_new_label();
1127 int l2 = gen_new_label();
1128
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1130 if (sign) {
1131 int l3 = gen_new_label();
1132 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1134 gen_set_label(l3);
1135 tcg_gen_div_i64(ret, arg1, arg2);
1136 } else {
1137 tcg_gen_divu_i64(ret, arg1, arg2);
1138 }
1139 if (compute_ov) {
1140 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1141 }
1142 tcg_gen_br(l2);
1143 gen_set_label(l1);
1144 if (sign) {
1145 tcg_gen_sari_i64(ret, arg1, 63);
1146 } else {
1147 tcg_gen_movi_i64(ret, 0);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1151 }
1152 gen_set_label(l2);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, ret);
1155 }
1156 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1157 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1158 { \
1159 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign, compute_ov); \
1162 }
1163 /* divwu divwu. divwuo divwuo. */
1164 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1165 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1166 /* divw divw. divwo divwo. */
1167 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1168 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1169 #endif
1170
1171 /* mulhw mulhw. */
1172 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1173 {
1174 TCGv_i64 t0, t1;
1175
1176 t0 = tcg_temp_new_i64();
1177 t1 = tcg_temp_new_i64();
1178 #if defined(TARGET_PPC64)
1179 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1183 #else
1184 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1185 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1186 tcg_gen_mul_i64(t0, t0, t1);
1187 tcg_gen_shri_i64(t0, t0, 32);
1188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1189 #endif
1190 tcg_temp_free_i64(t0);
1191 tcg_temp_free_i64(t1);
1192 if (unlikely(Rc(ctx->opcode) != 0))
1193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1194 }
1195 /* mulhwu mulhwu. */
1196 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1197 {
1198 TCGv_i64 t0, t1;
1199
1200 t0 = tcg_temp_new_i64();
1201 t1 = tcg_temp_new_i64();
1202 #if defined(TARGET_PPC64)
1203 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1207 #else
1208 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1209 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mul_i64(t0, t0, t1);
1211 tcg_gen_shri_i64(t0, t0, 32);
1212 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1213 #endif
1214 tcg_temp_free_i64(t0);
1215 tcg_temp_free_i64(t1);
1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1218 }
1219 /* mullw mullw. */
1220 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1221 {
1222 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1223 cpu_gpr[rB(ctx->opcode)]);
1224 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1227 }
1228 /* mullwo mullwo. */
1229 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1230 {
1231 int l1;
1232 TCGv_i64 t0, t1;
1233
1234 t0 = tcg_temp_new_i64();
1235 t1 = tcg_temp_new_i64();
1236 l1 = gen_new_label();
1237 /* Start with XER OV disabled, the most likely case */
1238 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1239 #if defined(TARGET_PPC64)
1240 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1242 #else
1243 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1245 #endif
1246 tcg_gen_mul_i64(t0, t0, t1);
1247 #if defined(TARGET_PPC64)
1248 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1250 #else
1251 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1252 tcg_gen_ext32s_i64(t1, t0);
1253 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1254 #endif
1255 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1256 gen_set_label(l1);
1257 tcg_temp_free_i64(t0);
1258 tcg_temp_free_i64(t1);
1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1261 }
1262 /* mulli */
1263 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1264 {
1265 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1266 SIMM(ctx->opcode));
1267 }
1268 #if defined(TARGET_PPC64)
1269 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1270 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1271 { \
1272 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1274 if (unlikely(Rc(ctx->opcode) != 0)) \
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1276 }
1277 /* mulhd mulhd. */
1278 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1279 /* mulhdu mulhdu. */
1280 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1281 /* mulld mulld. */
1282 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1283 {
1284 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1285 cpu_gpr[rB(ctx->opcode)]);
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1288 }
1289 /* mulldo mulldo. */
1290 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1291 #endif
1292
1293 /* neg neg. nego nego. */
1294 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1295 {
1296 int l1 = gen_new_label();
1297 int l2 = gen_new_label();
1298 TCGv t0 = tcg_temp_local_new();
1299 #if defined(TARGET_PPC64)
1300 if (ctx->sf_mode) {
1301 tcg_gen_mov_tl(t0, arg1);
1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1303 } else
1304 #endif
1305 {
1306 tcg_gen_ext32s_tl(t0, arg1);
1307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1308 }
1309 tcg_gen_neg_tl(ret, arg1);
1310 if (ov_check) {
1311 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1312 }
1313 tcg_gen_br(l2);
1314 gen_set_label(l1);
1315 tcg_gen_mov_tl(ret, t0);
1316 if (ov_check) {
1317 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1318 }
1319 gen_set_label(l2);
1320 tcg_temp_free(t0);
1321 if (unlikely(Rc(ctx->opcode) != 0))
1322 gen_set_Rc0(ctx, ret);
1323 }
1324 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1325 {
1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1327 }
1328 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1329 {
1330 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1331 }
1332
1333 /* Common subf function */
1334 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1335 int add_ca, int compute_ca, int compute_ov)
1336 {
1337 TCGv t0, t1;
1338
1339 if ((!compute_ca && !compute_ov) ||
1340 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1341 t0 = ret;
1342 } else {
1343 t0 = tcg_temp_local_new();
1344 }
1345
1346 if (add_ca) {
1347 t1 = tcg_temp_local_new();
1348 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1349 tcg_gen_shri_tl(t1, t1, XER_CA);
1350 }
1351
1352 if (compute_ca && compute_ov) {
1353 /* Start with XER CA and OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1355 } else if (compute_ca) {
1356 /* Start with XER CA disabled, the most likely case */
1357 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1358 } else if (compute_ov) {
1359 /* Start with XER OV disabled, the most likely case */
1360 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1361 }
1362
1363 if (add_ca) {
1364 tcg_gen_not_tl(t0, arg1);
1365 tcg_gen_add_tl(t0, t0, arg2);
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1367 tcg_gen_add_tl(t0, t0, t1);
1368 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1369 tcg_temp_free(t1);
1370 } else {
1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 if (compute_ca) {
1373 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1374 }
1375 }
1376 if (compute_ov) {
1377 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1378 }
1379
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, t0);
1382
1383 if (!TCGV_EQUAL(t0, ret)) {
1384 tcg_gen_mov_tl(ret, t0);
1385 tcg_temp_free(t0);
1386 }
1387 }
1388 /* Sub functions with Two operands functions */
1389 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1390 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1391 { \
1392 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1394 add_ca, compute_ca, compute_ov); \
1395 }
1396 /* Sub functions with one operand and one immediate */
1397 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1398 add_ca, compute_ca, compute_ov) \
1399 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1400 { \
1401 TCGv t0 = tcg_const_local_tl(const_val); \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], t0, \
1404 add_ca, compute_ca, compute_ov); \
1405 tcg_temp_free(t0); \
1406 }
1407 /* subf subf. subfo subfo. */
1408 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1409 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1410 /* subfc subfc. subfco subfco. */
1411 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1412 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1413 /* subfe subfe. subfeo subfo. */
1414 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1415 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1416 /* subfme subfme. subfmeo subfmeo. */
1417 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1418 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1419 /* subfze subfze. subfzeo subfzeo.*/
1420 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1421 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1422 /* subfic */
1423 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424 {
1425 /* Start with XER CA and OV disabled, the most likely case */
1426 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1427 TCGv t0 = tcg_temp_local_new();
1428 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1429 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1430 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1431 tcg_temp_free(t1);
1432 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1433 tcg_temp_free(t0);
1434 }
1435
1436 /*** Integer logical ***/
1437 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1438 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1439 { \
1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1441 cpu_gpr[rB(ctx->opcode)]); \
1442 if (unlikely(Rc(ctx->opcode) != 0)) \
1443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1444 }
1445
1446 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1447 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1448 { \
1449 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1450 if (unlikely(Rc(ctx->opcode) != 0)) \
1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1452 }
1453
1454 /* and & and. */
1455 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1456 /* andc & andc. */
1457 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1458 /* andi. */
1459 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1460 {
1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1463 }
1464 /* andis. */
1465 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1466 {
1467 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1469 }
1470 /* cntlzw */
1471 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1472 {
1473 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1474 if (unlikely(Rc(ctx->opcode) != 0))
1475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1476 }
1477 /* eqv & eqv. */
1478 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1479 /* extsb & extsb. */
1480 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1481 /* extsh & extsh. */
1482 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1483 /* nand & nand. */
1484 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1485 /* nor & nor. */
1486 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1487 /* or & or. */
1488 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1489 {
1490 int rs, ra, rb;
1491
1492 rs = rS(ctx->opcode);
1493 ra = rA(ctx->opcode);
1494 rb = rB(ctx->opcode);
1495 /* Optimisation for mr. ri case */
1496 if (rs != ra || rs != rb) {
1497 if (rs != rb)
1498 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1499 else
1500 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1501 if (unlikely(Rc(ctx->opcode) != 0))
1502 gen_set_Rc0(ctx, cpu_gpr[ra]);
1503 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1504 gen_set_Rc0(ctx, cpu_gpr[rs]);
1505 #if defined(TARGET_PPC64)
1506 } else {
1507 int prio = 0;
1508
1509 switch (rs) {
1510 case 1:
1511 /* Set process priority to low */
1512 prio = 2;
1513 break;
1514 case 6:
1515 /* Set process priority to medium-low */
1516 prio = 3;
1517 break;
1518 case 2:
1519 /* Set process priority to normal */
1520 prio = 4;
1521 break;
1522 #if !defined(CONFIG_USER_ONLY)
1523 case 31:
1524 if (ctx->mem_idx > 0) {
1525 /* Set process priority to very low */
1526 prio = 1;
1527 }
1528 break;
1529 case 5:
1530 if (ctx->mem_idx > 0) {
1531 /* Set process priority to medium-hight */
1532 prio = 5;
1533 }
1534 break;
1535 case 3:
1536 if (ctx->mem_idx > 0) {
1537 /* Set process priority to high */
1538 prio = 6;
1539 }
1540 break;
1541 case 7:
1542 if (ctx->mem_idx > 1) {
1543 /* Set process priority to very high */
1544 prio = 7;
1545 }
1546 break;
1547 #endif
1548 default:
1549 /* nop */
1550 break;
1551 }
1552 if (prio) {
1553 TCGv t0 = tcg_temp_new();
1554 gen_load_spr(t0, SPR_PPR);
1555 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1556 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1557 gen_store_spr(SPR_PPR, t0);
1558 tcg_temp_free(t0);
1559 }
1560 #endif
1561 }
1562 }
1563 /* orc & orc. */
1564 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1565 /* xor & xor. */
1566 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1567 {
1568 /* Optimisation for "set to zero" case */
1569 if (rS(ctx->opcode) != rB(ctx->opcode))
1570 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1571 else
1572 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1573 if (unlikely(Rc(ctx->opcode) != 0))
1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1575 }
1576 /* ori */
1577 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1578 {
1579 target_ulong uimm = UIMM(ctx->opcode);
1580
1581 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1582 /* NOP */
1583 /* XXX: should handle special NOPs for POWER series */
1584 return;
1585 }
1586 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1587 }
1588 /* oris */
1589 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1590 {
1591 target_ulong uimm = UIMM(ctx->opcode);
1592
1593 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1594 /* NOP */
1595 return;
1596 }
1597 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1598 }
1599 /* xori */
1600 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1601 {
1602 target_ulong uimm = UIMM(ctx->opcode);
1603
1604 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1605 /* NOP */
1606 return;
1607 }
1608 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1609 }
1610 /* xoris */
1611 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1612 {
1613 target_ulong uimm = UIMM(ctx->opcode);
1614
1615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1616 /* NOP */
1617 return;
1618 }
1619 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1620 }
1621 /* popcntb : PowerPC 2.03 specification */
1622 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1623 {
1624 #if defined(TARGET_PPC64)
1625 if (ctx->sf_mode)
1626 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1627 else
1628 #endif
1629 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 }
1631
1632 #if defined(TARGET_PPC64)
1633 /* extsw & extsw. */
1634 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1635 /* cntlzd */
1636 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1637 {
1638 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1639 if (unlikely(Rc(ctx->opcode) != 0))
1640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1641 }
1642 #endif
1643
1644 /*** Integer rotate ***/
1645 /* rlwimi & rlwimi. */
1646 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1647 {
1648 uint32_t mb, me, sh;
1649
1650 mb = MB(ctx->opcode);
1651 me = ME(ctx->opcode);
1652 sh = SH(ctx->opcode);
1653 if (likely(sh == 0 && mb == 0 && me == 31)) {
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 } else {
1656 target_ulong mask;
1657 TCGv t1;
1658 TCGv t0 = tcg_temp_new();
1659 #if defined(TARGET_PPC64)
1660 TCGv_i32 t2 = tcg_temp_new_i32();
1661 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_rotli_i32(t2, t2, sh);
1663 tcg_gen_extu_i32_i64(t0, t2);
1664 tcg_temp_free_i32(t2);
1665 #else
1666 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1667 #endif
1668 #if defined(TARGET_PPC64)
1669 mb += 32;
1670 me += 32;
1671 #endif
1672 mask = MASK(mb, me);
1673 t1 = tcg_temp_new();
1674 tcg_gen_andi_tl(t0, t0, mask);
1675 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1676 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1677 tcg_temp_free(t0);
1678 tcg_temp_free(t1);
1679 }
1680 if (unlikely(Rc(ctx->opcode) != 0))
1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1682 }
1683 /* rlwinm & rlwinm. */
1684 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1685 {
1686 uint32_t mb, me, sh;
1687
1688 sh = SH(ctx->opcode);
1689 mb = MB(ctx->opcode);
1690 me = ME(ctx->opcode);
1691
1692 if (likely(mb == 0 && me == (31 - sh))) {
1693 if (likely(sh == 0)) {
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1695 } else {
1696 TCGv t0 = tcg_temp_new();
1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shli_tl(t0, t0, sh);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
1701 }
1702 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1703 TCGv t0 = tcg_temp_new();
1704 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705 tcg_gen_shri_tl(t0, t0, mb);
1706 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 tcg_temp_free(t0);
1708 } else {
1709 TCGv t0 = tcg_temp_new();
1710 #if defined(TARGET_PPC64)
1711 TCGv_i32 t1 = tcg_temp_new_i32();
1712 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1713 tcg_gen_rotli_i32(t1, t1, sh);
1714 tcg_gen_extu_i32_i64(t0, t1);
1715 tcg_temp_free_i32(t1);
1716 #else
1717 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1718 #endif
1719 #if defined(TARGET_PPC64)
1720 mb += 32;
1721 me += 32;
1722 #endif
1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 tcg_temp_free(t0);
1725 }
1726 if (unlikely(Rc(ctx->opcode) != 0))
1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1728 }
1729 /* rlwnm & rlwnm. */
1730 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1731 {
1732 uint32_t mb, me;
1733 TCGv t0;
1734 #if defined(TARGET_PPC64)
1735 TCGv_i32 t1, t2;
1736 #endif
1737
1738 mb = MB(ctx->opcode);
1739 me = ME(ctx->opcode);
1740 t0 = tcg_temp_new();
1741 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1742 #if defined(TARGET_PPC64)
1743 t1 = tcg_temp_new_i32();
1744 t2 = tcg_temp_new_i32();
1745 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1746 tcg_gen_trunc_i64_i32(t2, t0);
1747 tcg_gen_rotl_i32(t1, t1, t2);
1748 tcg_gen_extu_i32_i64(t0, t1);
1749 tcg_temp_free_i32(t1);
1750 tcg_temp_free_i32(t2);
1751 #else
1752 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753 #endif
1754 if (unlikely(mb != 0 || me != 31)) {
1755 #if defined(TARGET_PPC64)
1756 mb += 32;
1757 me += 32;
1758 #endif
1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1760 } else {
1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1762 }
1763 tcg_temp_free(t0);
1764 if (unlikely(Rc(ctx->opcode) != 0))
1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1766 }
1767
1768 #if defined(TARGET_PPC64)
1769 #define GEN_PPC64_R2(name, opc1, opc2) \
1770 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1771 { \
1772 gen_##name(ctx, 0); \
1773 } \
1774 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1775 PPC_64B) \
1776 { \
1777 gen_##name(ctx, 1); \
1778 }
1779 #define GEN_PPC64_R4(name, opc1, opc2) \
1780 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1781 { \
1782 gen_##name(ctx, 0, 0); \
1783 } \
1784 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1785 PPC_64B) \
1786 { \
1787 gen_##name(ctx, 0, 1); \
1788 } \
1789 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1790 PPC_64B) \
1791 { \
1792 gen_##name(ctx, 1, 0); \
1793 } \
1794 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1795 PPC_64B) \
1796 { \
1797 gen_##name(ctx, 1, 1); \
1798 }
1799
1800 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1801 uint32_t me, uint32_t sh)
1802 {
1803 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1804 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1805 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1806 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1807 } else {
1808 TCGv t0 = tcg_temp_new();
1809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1810 if (likely(mb == 0 && me == 63)) {
1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1812 } else {
1813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1814 }
1815 tcg_temp_free(t0);
1816 }
1817 if (unlikely(Rc(ctx->opcode) != 0))
1818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1819 }
1820 /* rldicl - rldicl. */
1821 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1822 {
1823 uint32_t sh, mb;
1824
1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
1827 gen_rldinm(ctx, mb, 63, sh);
1828 }
1829 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1830 /* rldicr - rldicr. */
1831 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1832 {
1833 uint32_t sh, me;
1834
1835 sh = SH(ctx->opcode) | (shn << 5);
1836 me = MB(ctx->opcode) | (men << 5);
1837 gen_rldinm(ctx, 0, me, sh);
1838 }
1839 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1840 /* rldic - rldic. */
1841 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1842 {
1843 uint32_t sh, mb;
1844
1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848 }
1849 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
1851 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1852 uint32_t me)
1853 {
1854 TCGv t0;
1855
1856 mb = MB(ctx->opcode);
1857 me = ME(ctx->opcode);
1858 t0 = tcg_temp_new();
1859 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1860 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1861 if (unlikely(mb != 0 || me != 63)) {
1862 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1863 } else {
1864 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1865 }
1866 tcg_temp_free(t0);
1867 if (unlikely(Rc(ctx->opcode) != 0))
1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1869 }
1870
1871 /* rldcl - rldcl. */
1872 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1873 {
1874 uint32_t mb;
1875
1876 mb = MB(ctx->opcode) | (mbn << 5);
1877 gen_rldnm(ctx, mb, 63);
1878 }
1879 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1880 /* rldcr - rldcr. */
1881 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1882 {
1883 uint32_t me;
1884
1885 me = MB(ctx->opcode) | (men << 5);
1886 gen_rldnm(ctx, 0, me);
1887 }
1888 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1889 /* rldimi - rldimi. */
1890 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1891 {
1892 uint32_t sh, mb, me;
1893
1894 sh = SH(ctx->opcode) | (shn << 5);
1895 mb = MB(ctx->opcode) | (mbn << 5);
1896 me = 63 - sh;
1897 if (unlikely(sh == 0 && mb == 0)) {
1898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1899 } else {
1900 TCGv t0, t1;
1901 target_ulong mask;
1902
1903 t0 = tcg_temp_new();
1904 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1905 t1 = tcg_temp_new();
1906 mask = MASK(mb, me);
1907 tcg_gen_andi_tl(t0, t0, mask);
1908 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1910 tcg_temp_free(t0);
1911 tcg_temp_free(t1);
1912 }
1913 if (unlikely(Rc(ctx->opcode) != 0))
1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1915 }
1916 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1917 #endif
1918
1919 /*** Integer shift ***/
1920 /* slw & slw. */
1921 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1922 {
1923 TCGv t0;
1924 int l1, l2;
1925 l1 = gen_new_label();
1926 l2 = gen_new_label();
1927
1928 t0 = tcg_temp_local_new();
1929 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1931 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1932 tcg_gen_br(l2);
1933 gen_set_label(l1);
1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1935 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1936 gen_set_label(l2);
1937 tcg_temp_free(t0);
1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940 }
1941 /* sraw & sraw. */
1942 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1943 {
1944 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1945 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948 }
1949 /* srawi & srawi. */
1950 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1951 {
1952 int sh = SH(ctx->opcode);
1953 if (sh != 0) {
1954 int l1, l2;
1955 TCGv t0;
1956 l1 = gen_new_label();
1957 l2 = gen_new_label();
1958 t0 = tcg_temp_local_new();
1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1962 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1963 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1964 tcg_gen_br(l2);
1965 gen_set_label(l1);
1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1967 gen_set_label(l2);
1968 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1970 tcg_temp_free(t0);
1971 } else {
1972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1973 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1974 }
1975 if (unlikely(Rc(ctx->opcode) != 0))
1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1977 }
1978 /* srw & srw. */
1979 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1980 {
1981 TCGv t0, t1;
1982 int l1, l2;
1983 l1 = gen_new_label();
1984 l2 = gen_new_label();
1985
1986 t0 = tcg_temp_local_new();
1987 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1988 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1989 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1990 tcg_gen_br(l2);
1991 gen_set_label(l1);
1992 t1 = tcg_temp_new();
1993 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1995 tcg_temp_free(t1);
1996 gen_set_label(l2);
1997 tcg_temp_free(t0);
1998 if (unlikely(Rc(ctx->opcode) != 0))
1999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2000 }
2001 #if defined(TARGET_PPC64)
2002 /* sld & sld. */
2003 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2004 {
2005 TCGv t0;
2006 int l1, l2;
2007 l1 = gen_new_label();
2008 l2 = gen_new_label();
2009
2010 t0 = tcg_temp_local_new();
2011 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2012 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2013 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2014 tcg_gen_br(l2);
2015 gen_set_label(l1);
2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2017 gen_set_label(l2);
2018 tcg_temp_free(t0);
2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021 }
2022 /* srad & srad. */
2023 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2024 {
2025 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2026 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029 }
2030 /* sradi & sradi. */
2031 static always_inline void gen_sradi (DisasContext *ctx, int n)
2032 {
2033 int sh = SH(ctx->opcode) + (n << 5);
2034 if (sh != 0) {
2035 int l1, l2;
2036 TCGv t0;
2037 l1 = gen_new_label();
2038 l2 = gen_new_label();
2039 t0 = tcg_temp_local_new();
2040 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2041 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2042 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2043 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2044 tcg_gen_br(l2);
2045 gen_set_label(l1);
2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2047 gen_set_label(l2);
2048 tcg_temp_free(t0);
2049 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2050 } else {
2051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2052 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2053 }
2054 if (unlikely(Rc(ctx->opcode) != 0))
2055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2056 }
2057 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2058 {
2059 gen_sradi(ctx, 0);
2060 }
2061 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2062 {
2063 gen_sradi(ctx, 1);
2064 }
2065 /* srd & srd. */
2066 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2067 {
2068 TCGv t0;
2069 int l1, l2;
2070 l1 = gen_new_label();
2071 l2 = gen_new_label();
2072
2073 t0 = tcg_temp_local_new();
2074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2075 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2077 tcg_gen_br(l2);
2078 gen_set_label(l1);
2079 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2080 gen_set_label(l2);
2081 tcg_temp_free(t0);
2082 if (unlikely(Rc(ctx->opcode) != 0))
2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2084 }
2085 #endif
2086
2087 /*** Floating-Point arithmetic ***/
2088 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2089 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2090 { \
2091 if (unlikely(!ctx->fpu_enabled)) { \
2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
2093 return; \
2094 } \
2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
2097 gen_reset_fpstatus(); \
2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2100 if (isfloat) { \
2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2102 } \
2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
2105 }
2106
2107 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2110
2111 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2113 { \
2114 if (unlikely(!ctx->fpu_enabled)) { \
2115 gen_exception(ctx, POWERPC_EXCP_FPU); \
2116 return; \
2117 } \
2118 /* NIP cannot be restored if the memory exception comes from an helper */ \
2119 gen_update_nip(ctx, ctx->nip - 4); \
2120 gen_reset_fpstatus(); \
2121 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2122 cpu_fpr[rB(ctx->opcode)]); \
2123 if (isfloat) { \
2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2125 } \
2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
2128 }
2129 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2130 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2131 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2132
2133 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2134 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2135 { \
2136 if (unlikely(!ctx->fpu_enabled)) { \
2137 gen_exception(ctx, POWERPC_EXCP_FPU); \
2138 return; \
2139 } \
2140 /* NIP cannot be restored if the memory exception comes from an helper */ \
2141 gen_update_nip(ctx, ctx->nip - 4); \
2142 gen_reset_fpstatus(); \
2143 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2144 cpu_fpr[rC(ctx->opcode)]); \
2145 if (isfloat) { \
2146 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2147 } \
2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2149 set_fprf, Rc(ctx->opcode) != 0); \
2150 }
2151 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2152 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2153 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2154
2155 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2156 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2157 { \
2158 if (unlikely(!ctx->fpu_enabled)) { \
2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
2160 return; \
2161 } \
2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
2164 gen_reset_fpstatus(); \
2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
2168 }
2169
2170 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2171 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2172 { \
2173 if (unlikely(!ctx->fpu_enabled)) { \
2174 gen_exception(ctx, POWERPC_EXCP_FPU); \
2175 return; \
2176 } \
2177 /* NIP cannot be restored if the memory exception comes from an helper */ \
2178 gen_update_nip(ctx, ctx->nip - 4); \
2179 gen_reset_fpstatus(); \
2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
2183 }
2184
2185 /* fadd - fadds */
2186 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2187 /* fdiv - fdivs */
2188 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2189 /* fmul - fmuls */
2190 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2191
2192 /* fre */
2193 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2194
2195 /* fres */
2196 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2197
2198 /* frsqrte */
2199 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201 /* frsqrtes */
2202 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2203 {
2204 if (unlikely(!ctx->fpu_enabled)) {
2205 gen_exception(ctx, POWERPC_EXCP_FPU);
2206 return;
2207 }
2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx, ctx->nip - 4);
2210 gen_reset_fpstatus();
2211 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2212 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2214 }
2215
2216 /* fsel */
2217 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2218 /* fsub - fsubs */
2219 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2220 /* Optional: */
2221 /* fsqrt */
2222 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2223 {
2224 if (unlikely(!ctx->fpu_enabled)) {
2225 gen_exception(ctx, POWERPC_EXCP_FPU);
2226 return;
2227 }
2228 /* NIP cannot be restored if the memory exception comes from an helper */
2229 gen_update_nip(ctx, ctx->nip - 4);
2230 gen_reset_fpstatus();
2231 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2233 }
2234
2235 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
2243 gen_reset_fpstatus();
2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2245 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2247 }
2248
2249 /*** Floating-Point multiply-and-add ***/
2250 /* fmadd - fmadds */
2251 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2252 /* fmsub - fmsubs */
2253 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2254 /* fnmadd - fnmadds */
2255 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2256 /* fnmsub - fnmsubs */
2257 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2258
2259 /*** Floating-Point round & convert ***/
2260 /* fctiw */
2261 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2262 /* fctiwz */
2263 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2264 /* frsp */
2265 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2266 #if defined(TARGET_PPC64)
2267 /* fcfid */
2268 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2269 /* fctid */
2270 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2271 /* fctidz */
2272 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2273 #endif
2274
2275 /* frin */
2276 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2277 /* friz */
2278 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2279 /* frip */
2280 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2281 /* frim */
2282 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2283
2284 /*** Floating-Point compare ***/
2285 /* fcmpo */
2286 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2287 {
2288 TCGv_i32 crf;
2289 if (unlikely(!ctx->fpu_enabled)) {
2290 gen_exception(ctx, POWERPC_EXCP_FPU);
2291 return;
2292 }
2293 /* NIP cannot be restored if the memory exception comes from an helper */
2294 gen_update_nip(ctx, ctx->nip - 4);
2295 gen_reset_fpstatus();
2296 crf = tcg_const_i32(crfD(ctx->opcode));
2297 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2298 tcg_temp_free_i32(crf);
2299 gen_helper_float_check_status();
2300 }
2301
2302 /* fcmpu */
2303 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2304 {
2305 TCGv_i32 crf;
2306 if (unlikely(!ctx->fpu_enabled)) {
2307 gen_exception(ctx, POWERPC_EXCP_FPU);
2308 return;
2309 }
2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
2312 gen_reset_fpstatus();
2313 crf = tcg_const_i32(crfD(ctx->opcode));
2314 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2315 tcg_temp_free_i32(crf);
2316 gen_helper_float_check_status();
2317 }
2318
2319 /*** Floating-point move ***/
2320 /* fabs */
2321 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2322 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2323
2324 /* fmr - fmr. */
2325 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2326 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2327 {
2328 if (unlikely(!ctx->fpu_enabled)) {
2329 gen_exception(ctx, POWERPC_EXCP_FPU);
2330 return;
2331 }
2332 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2333 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2334 }
2335
2336 /* fnabs */
2337 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2338 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2339 /* fneg */
2340 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2342
2343 /*** Floating-Point status & ctrl register ***/
2344 /* mcrfs */
2345 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2346 {
2347 int bfa;
2348
2349 if (unlikely(!ctx->fpu_enabled)) {
2350 gen_exception(ctx, POWERPC_EXCP_FPU);
2351 return;
2352 }
2353 bfa = 4 * (7 - crfS(ctx->opcode));
2354 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2355 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2356 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2357 }
2358
2359 /* mffs */
2360 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2361 {
2362 if (unlikely(!ctx->fpu_enabled)) {
2363 gen_exception(ctx, POWERPC_EXCP_FPU);
2364 return;
2365 }
2366 gen_reset_fpstatus();
2367 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2368 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2369 }
2370
2371 /* mtfsb0 */
2372 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2373 {
2374 uint8_t crb;
2375
2376 if (unlikely(!ctx->fpu_enabled)) {
2377 gen_exception(ctx, POWERPC_EXCP_FPU);
2378 return;
2379 }
2380 crb = 31 - crbD(ctx->opcode);
2381 gen_reset_fpstatus();
2382 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2383 TCGv_i32 t0;
2384 /* NIP cannot be restored if the memory exception comes from an helper */
2385 gen_update_nip(ctx, ctx->nip - 4);
2386 t0 = tcg_const_i32(crb);
2387 gen_helper_fpscr_clrbit(t0);
2388 tcg_temp_free_i32(t0);
2389 }
2390 if (unlikely(Rc(ctx->opcode) != 0)) {
2391 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2392 }
2393 }
2394
2395 /* mtfsb1 */
2396 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2397 {
2398 uint8_t crb;
2399
2400 if (unlikely(!ctx->fpu_enabled)) {
2401 gen_exception(ctx, POWERPC_EXCP_FPU);
2402 return;
2403 }
2404 crb = 31 - crbD(ctx->opcode);
2405 gen_reset_fpstatus();
2406 /* XXX: we pretend we can only do IEEE floating-point computations */
2407 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2408 TCGv_i32 t0;
2409 /* NIP cannot be restored if the memory exception comes from an helper */
2410 gen_update_nip(ctx, ctx->nip - 4);
2411 t0 = tcg_const_i32(crb);
2412 gen_helper_fpscr_setbit(t0);
2413 tcg_temp_free_i32(t0);
2414 }
2415 if (unlikely(Rc(ctx->opcode) != 0)) {
2416 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2417 }
2418 /* We can raise a differed exception */
2419 gen_helper_float_check_status();
2420 }
2421
2422 /* mtfsf */
2423 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
2424 {
2425 TCGv_i32 t0;
2426 int L = ctx->opcode & 0x02000000;
2427
2428 if (unlikely(!ctx->fpu_enabled)) {
2429 gen_exception(ctx, POWERPC_EXCP_FPU);
2430 return;
2431 }
2432 /* NIP cannot be restored if the memory exception comes from an helper */
2433 gen_update_nip(ctx, ctx->nip - 4);
2434 gen_reset_fpstatus();
2435 if (L)
2436 t0 = tcg_const_i32(0xff);
2437 else
2438 t0 = tcg_const_i32(FM(ctx->opcode));
2439 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2440 tcg_temp_free_i32(t0);
2441 if (unlikely(Rc(ctx->opcode) != 0)) {
2442 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2443 }
2444 /* We can raise a differed exception */
2445 gen_helper_float_check_status();
2446 }
2447
2448 /* mtfsfi */
2449 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2450 {
2451 int bf, sh;
2452 TCGv_i64 t0;
2453 TCGv_i32 t1;
2454
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 bf = crbD(ctx->opcode) >> 2;
2460 sh = 7 - bf;
2461 /* NIP cannot be restored if the memory exception comes from an helper */
2462 gen_update_nip(ctx, ctx->nip - 4);
2463 gen_reset_fpstatus();
2464 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2465 t1 = tcg_const_i32(1 << sh);
2466 gen_helper_store_fpscr(t0, t1);
2467 tcg_temp_free_i64(t0);
2468 tcg_temp_free_i32(t1);
2469 if (unlikely(Rc(ctx->opcode) != 0)) {
2470 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2471 }
2472 /* We can raise a differed exception */
2473 gen_helper_float_check_status();
2474 }
2475
2476 /*** Addressing modes ***/
2477 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2478 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2479 {
2480 target_long simm = SIMM(ctx->opcode);
2481
2482 simm &= ~maskl;
2483 if (rA(ctx->opcode) == 0) {
2484 #if defined(TARGET_PPC64)
2485 if (!ctx->sf_mode) {
2486 tcg_gen_movi_tl(EA, (uint32_t)simm);
2487 } else
2488 #endif
2489 tcg_gen_movi_tl(EA, simm);
2490 } else if (likely(simm != 0)) {
2491 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2492 #if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, EA);
2495 }
2496 #endif
2497 } else {
2498 #if defined(TARGET_PPC64)
2499 if (!ctx->sf_mode) {
2500 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2501 } else
2502 #endif
2503 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2504 }
2505 }
2506
2507 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2508 {
2509 if (rA(ctx->opcode) == 0) {
2510 #if defined(TARGET_PPC64)
2511 if (!ctx->sf_mode) {
2512 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2513 } else
2514 #endif
2515 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2516 } else {
2517 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2518 #if defined(TARGET_PPC64)
2519 if (!ctx->sf_mode) {
2520 tcg_gen_ext32u_tl(EA, EA);
2521 }
2522 #endif
2523 }
2524 }
2525
2526 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2527 {
2528 if (rA(ctx->opcode) == 0) {
2529 tcg_gen_movi_tl(EA, 0);
2530 } else {
2531 #if defined(TARGET_PPC64)
2532 if (!ctx->sf_mode) {
2533 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2534 } else
2535 #endif
2536 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2537 }
2538 }
2539
2540 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2541 {
2542 tcg_gen_addi_tl(ret, arg1, val);
2543 #if defined(TARGET_PPC64)
2544 if (!ctx->sf_mode) {
2545 tcg_gen_ext32u_tl(ret, ret);
2546 }
2547 #endif
2548 }
2549
2550 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2551 {
2552 int l1 = gen_new_label();
2553 TCGv t0 = tcg_temp_new();
2554 TCGv_i32 t1, t2;
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx, ctx->nip - 4);
2557 tcg_gen_andi_tl(t0, EA, mask);
2558 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2559 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2560 t2 = tcg_const_i32(0);
2561 gen_helper_raise_exception_err(t1, t2);
2562 tcg_temp_free_i32(t1);
2563 tcg_temp_free_i32(t2);
2564 gen_set_label(l1);
2565 tcg_temp_free(t0);
2566 }
2567
2568 /*** Integer load ***/
2569 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2570 {
2571 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2572 }
2573
2574 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2575 {
2576 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2577 }
2578
2579 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2580 {
2581 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2582 if (unlikely(ctx->le_mode)) {
2583 #if defined(TARGET_PPC64)
2584 TCGv_i32 t0 = tcg_temp_new_i32();
2585 tcg_gen_trunc_tl_i32(t0, arg1);
2586 tcg_gen_bswap16_i32(t0, t0);
2587 tcg_gen_extu_i32_tl(arg1, t0);
2588 tcg_temp_free_i32(t0);
2589 #else
2590 tcg_gen_bswap16_i32(arg1, arg1);
2591 #endif
2592 }
2593 }
2594
2595 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2596 {
2597 if (unlikely(ctx->le_mode)) {
2598 #if defined(TARGET_PPC64)
2599 TCGv_i32 t0;
2600 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2601 t0 = tcg_temp_new_i32();
2602 tcg_gen_trunc_tl_i32(t0, arg1);
2603 tcg_gen_bswap16_i32(t0, t0);
2604 tcg_gen_extu_i32_tl(arg1, t0);
2605 tcg_gen_ext16s_tl(arg1, arg1);
2606 tcg_temp_free_i32(t0);
2607 #else
2608 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2609 tcg_gen_bswap16_i32(arg1, arg1);
2610 tcg_gen_ext16s_i32(arg1, arg1);
2611 #endif
2612 } else {
2613 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2614 }
2615 }
2616
2617 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2618 {
2619 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2620 if (unlikely(ctx->le_mode)) {
2621 #if defined(TARGET_PPC64)
2622 TCGv_i32 t0 = tcg_temp_new_i32();
2623 tcg_gen_trunc_tl_i32(t0, arg1);
2624 tcg_gen_bswap_i32(t0, t0);
2625 tcg_gen_extu_i32_tl(arg1, t0);
2626 tcg_temp_free_i32(t0);
2627 #else
2628 tcg_gen_bswap_i32(arg1, arg1);
2629 #endif
2630 }
2631 }
2632
2633 #if defined(TARGET_PPC64)
2634 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2635 {
2636 if (unlikely(ctx->le_mode)) {
2637 TCGv_i32 t0;
2638 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2639 t0 = tcg_temp_new_i32();
2640 tcg_gen_trunc_tl_i32(t0, arg1);
2641 tcg_gen_bswap_i32(t0, t0);
2642 tcg_gen_ext_i32_tl(arg1, t0);
2643 tcg_temp_free_i32(t0);
2644 } else
2645 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2646 }
2647 #endif
2648
2649 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2650 {
2651 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2652 if (unlikely(ctx->le_mode)) {
2653 tcg_gen_bswap_i64(arg1, arg1);
2654 }
2655 }
2656
2657 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2658 {
2659 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2660 }
2661
2662 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2663 {
2664 if (unlikely(ctx->le_mode)) {
2665 #if defined(TARGET_PPC64)
2666 TCGv_i32 t0;
2667 TCGv t1;
2668 t0 = tcg_temp_new_i32();
2669 tcg_gen_trunc_tl_i32(t0, arg1);
2670 tcg_gen_ext16u_i32(t0, t0);
2671 tcg_gen_bswap16_i32(t0, t0);
2672 t1 = tcg_temp_new();
2673 tcg_gen_extu_i32_tl(t1, t0);
2674 tcg_temp_free_i32(t0);
2675 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2676 tcg_temp_free(t1);
2677 #else
2678 TCGv t0 = tcg_temp_new();
2679 tcg_gen_ext16u_tl(t0, arg1);
2680 tcg_gen_bswap16_i32(t0, t0);
2681 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2682 tcg_temp_free(t0);
2683 #endif
2684 } else {
2685 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2686 }
2687 }
2688
2689 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2690 {
2691 if (unlikely(ctx->le_mode)) {
2692 #if defined(TARGET_PPC64)
2693 TCGv_i32 t0;
2694 TCGv t1;
2695 t0 = tcg_temp_new_i32();
2696 tcg_gen_trunc_tl_i32(t0, arg1);
2697 tcg_gen_bswap_i32(t0, t0);
2698 t1 = tcg_temp_new();
2699 tcg_gen_extu_i32_tl(t1, t0);
2700 tcg_temp_free_i32(t0);
2701 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2702 tcg_temp_free(t1);
2703 #else
2704 TCGv t0 = tcg_temp_new_i32();
2705 tcg_gen_bswap_i32(t0, arg1);
2706 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2707 tcg_temp_free(t0);
2708 #endif
2709 } else {
2710 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2711 }
2712 }
2713
2714 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2715 {
2716 if (unlikely(ctx->le_mode)) {
2717 TCGv_i64 t0 = tcg_temp_new_i64();
2718 tcg_gen_bswap_i64(t0, arg1);
2719 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2720 tcg_temp_free_i64(t0);
2721 } else
2722 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2723 }
2724
2725 #define GEN_LD(name, ldop, opc, type) \
2726 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2727 { \
2728 TCGv EA; \
2729 gen_set_access_type(ctx, ACCESS_INT); \
2730 EA = tcg_temp_new(); \
2731 gen_addr_imm_index(ctx, EA, 0); \
2732 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2733 tcg_temp_free(EA); \
2734 }
2735
2736 #define GEN_LDU(name, ldop, opc, type) \
2737 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2738 { \
2739 TCGv EA; \
2740 if (unlikely(rA(ctx->opcode) == 0 || \
2741 rA(ctx->opcode) == rD(ctx->opcode))) { \
2742 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2743 return; \
2744 } \
2745 gen_set_access_type(ctx, ACCESS_INT); \
2746 EA = tcg_temp_new(); \
2747 if (type == PPC_64B) \
2748 gen_addr_imm_index(ctx, EA, 0x03); \
2749 else \
2750 gen_addr_imm_index(ctx, EA, 0); \
2751 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2752 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2753 tcg_temp_free(EA); \
2754 }
2755
2756 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2757 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2758 { \
2759 TCGv EA; \
2760 if (unlikely(rA(ctx->opcode) == 0 || \
2761 rA(ctx->opcode) == rD(ctx->opcode))) { \
2762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2763 return; \
2764 } \
2765 gen_set_access_type(ctx, ACCESS_INT); \
2766 EA = tcg_temp_new(); \
2767 gen_addr_reg_index(ctx, EA); \
2768 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2774 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2775 { \
2776 TCGv EA; \
2777 gen_set_access_type(ctx, ACCESS_INT); \
2778 EA = tcg_temp_new(); \
2779 gen_addr_reg_index(ctx, EA); \
2780 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2781 tcg_temp_free(EA); \
2782 }
2783
2784 #define GEN_LDS(name, ldop, op, type) \
2785 GEN_LD(name, ldop, op | 0x20, type); \
2786 GEN_LDU(name, ldop, op | 0x21, type); \
2787 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2788 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2789
2790 /* lbz lbzu lbzux lbzx */
2791 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2792 /* lha lhau lhaux lhax */
2793 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2794 /* lhz lhzu lhzux lhzx */
2795 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2796 /* lwz lwzu lwzux lwzx */
2797 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2798 #if defined(TARGET_PPC64)
2799 /* lwaux */
2800 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2801 /* lwax */
2802 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2803 /* ldux */
2804 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2805 /* ldx */
2806 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2807 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2808 {
2809 TCGv EA;
2810 if (Rc(ctx->opcode)) {
2811 if (unlikely(rA(ctx->opcode) == 0 ||
2812 rA(ctx->opcode) == rD(ctx->opcode))) {
2813 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2814 return;
2815 }
2816 }
2817 gen_set_access_type(ctx, ACCESS_INT);
2818 EA = tcg_temp_new();
2819 gen_addr_imm_index(ctx, EA, 0x03);
2820 if (ctx->opcode & 0x02) {
2821 /* lwa (lwau is undefined) */
2822 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2823 } else {
2824 /* ld - ldu */
2825 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2826 }
2827 if (Rc(ctx->opcode))
2828 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2829 tcg_temp_free(EA);
2830 }
2831 /* lq */
2832 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2833 {
2834 #if defined(CONFIG_USER_ONLY)
2835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2836 #else
2837 int ra, rd;
2838 TCGv EA;
2839
2840 /* Restore CPU state */
2841 if (unlikely(ctx->mem_idx == 0)) {
2842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2843 return;
2844 }
2845 ra = rA(ctx->opcode);
2846 rd = rD(ctx->opcode);
2847 if (unlikely((rd & 1) || rd == ra)) {
2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2849 return;
2850 }
2851 if (unlikely(ctx->le_mode)) {
2852 /* Little-endian mode is not handled */
2853 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2854 return;
2855 }
2856 gen_set_access_type(ctx, ACCESS_INT);
2857 EA = tcg_temp_new();
2858 gen_addr_imm_index(ctx, EA, 0x0F);
2859 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2860 gen_addr_add(ctx, EA, EA, 8);
2861 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2862 tcg_temp_free(EA);
2863 #endif
2864 }
2865 #endif
2866
2867 /*** Integer store ***/
2868 #define GEN_ST(name, stop, opc, type) \
2869 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2870 { \
2871 TCGv EA; \
2872 gen_set_access_type(ctx, ACCESS_INT); \
2873 EA = tcg_temp_new(); \
2874 gen_addr_imm_index(ctx, EA, 0); \
2875 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2876 tcg_temp_free(EA); \
2877 }
2878
2879 #define GEN_STU(name, stop, opc, type) \
2880 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2881 { \
2882 TCGv EA; \
2883 if (unlikely(rA(ctx->opcode) == 0)) { \
2884 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2885 return; \
2886 } \
2887 gen_set_access_type(ctx, ACCESS_INT); \
2888 EA = tcg_temp_new(); \
2889 if (type == PPC_64B) \
2890 gen_addr_imm_index(ctx, EA, 0x03); \
2891 else \
2892 gen_addr_imm_index(ctx, EA, 0); \
2893 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2894 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2895 tcg_temp_free(EA); \
2896 }
2897
2898 #define GEN_STUX(name, stop, opc2, opc3, type) \
2899 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2900 { \
2901 TCGv EA; \
2902 if (unlikely(rA(ctx->opcode) == 0)) { \
2903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2904 return; \
2905 } \
2906 gen_set_access_type(ctx, ACCESS_INT); \
2907 EA = tcg_temp_new(); \
2908 gen_addr_reg_index(ctx, EA); \
2909 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2911 tcg_temp_free(EA); \
2912 }
2913
2914 #define GEN_STX(name, stop, opc2, opc3, type) \
2915 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2916 { \
2917 TCGv EA; \
2918 gen_set_access_type(ctx, ACCESS_INT); \
2919 EA = tcg_temp_new(); \
2920 gen_addr_reg_index(ctx, EA); \
2921 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2922 tcg_temp_free(EA); \
2923 }
2924
2925 #define GEN_STS(name, stop, op, type) \
2926 GEN_ST(name, stop, op | 0x20, type); \
2927 GEN_STU(name, stop, op | 0x21, type); \
2928 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2929 GEN_STX(name, stop, 0x17, op | 0x00, type)
2930
2931 /* stb stbu stbux stbx */
2932 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2933 /* sth sthu sthux sthx */
2934 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2935 /* stw stwu stwux stwx */
2936 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2937 #if defined(TARGET_PPC64)
2938 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2939 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2940 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2941 {
2942 int rs;
2943 TCGv EA;
2944
2945 rs = rS(ctx->opcode);
2946 if ((ctx->opcode & 0x3) == 0x2) {
2947 #if defined(CONFIG_USER_ONLY)
2948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2949 #else
2950 /* stq */
2951 if (unlikely(ctx->mem_idx == 0)) {
2952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2953 return;
2954 }
2955 if (unlikely(rs & 1)) {
2956 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2957 return;
2958 }
2959 if (unlikely(ctx->le_mode)) {
2960 /* Little-endian mode is not handled */
2961 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2962 return;
2963 }
2964 gen_set_access_type(ctx, ACCESS_INT);
2965 EA = tcg_temp_new();
2966 gen_addr_imm_index(ctx, EA, 0x03);
2967 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2968 gen_addr_add(ctx, EA, EA, 8);
2969 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2970 tcg_temp_free(EA);
2971 #endif
2972 } else {
2973 /* std / stdu */
2974 if (Rc(ctx->opcode)) {
2975 if (unlikely(rA(ctx->opcode) == 0)) {
2976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2977 return;
2978 }
2979 }
2980 gen_set_access_type(ctx, ACCESS_INT);
2981 EA = tcg_temp_new();
2982 gen_addr_imm_index(ctx, EA, 0x03);
2983 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2984 if (Rc(ctx->opcode))
2985 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2986 tcg_temp_free(EA);
2987 }
2988 }
2989 #endif
2990 /*** Integer load and store with byte reverse ***/
2991 /* lhbrx */
2992 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2993 {
2994 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2995 if (likely(!ctx->le_mode)) {
2996 #if defined(TARGET_PPC64)
2997 TCGv_i32 t0 = tcg_temp_new_i32();
2998 tcg_gen_trunc_tl_i32(t0, arg1);
2999 tcg_gen_bswap16_i32(t0, t0);
3000 tcg_gen_extu_i32_tl(arg1, t0);
3001 tcg_temp_free_i32(t0);
3002 #else
3003 tcg_gen_bswap16_i32(arg1, arg1);
3004 #endif
3005 }
3006 }
3007 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3008
3009 /* lwbrx */
3010 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3011 {
3012 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3013 if (likely(!ctx->le_mode)) {
3014 #if defined(TARGET_PPC64)
3015 TCGv_i32 t0 = tcg_temp_new_i32();
3016 tcg_gen_trunc_tl_i32(t0, arg1);
3017 tcg_gen_bswap_i32(t0, t0);
3018 tcg_gen_extu_i32_tl(arg1, t0);
3019 tcg_temp_free_i32(t0);
3020 #else
3021 tcg_gen_bswap_i32(arg1, arg1);
3022 #endif
3023 }
3024 }
3025 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3026
3027 /* sthbrx */
3028 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3029 {
3030 if (likely(!ctx->le_mode)) {
3031 #if defined(TARGET_PPC64)
3032 TCGv_i32 t0;
3033 TCGv t1;
3034 t0 = tcg_temp_new_i32();
3035 tcg_gen_trunc_tl_i32(t0, arg1);
3036 tcg_gen_ext16u_i32(t0, t0);
3037 tcg_gen_bswap16_i32(t0, t0);
3038 t1 = tcg_temp_new();
3039 tcg_gen_extu_i32_tl(t1, t0);
3040 tcg_temp_free_i32(t0);
3041 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3042 tcg_temp_free(t1);
3043 #else
3044 TCGv t0 = tcg_temp_new();
3045 tcg_gen_ext16u_tl(t0, arg1);
3046 tcg_gen_bswap16_i32(t0, t0);
3047 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3048 tcg_temp_free(t0);
3049 #endif
3050 } else {
3051 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3052 }
3053 }
3054 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3055
3056 /* stwbrx */
3057 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3058 {
3059 if (likely(!ctx->le_mode)) {
3060 #if defined(TARGET_PPC64)
3061 TCGv_i32 t0;
3062 TCGv t1;
3063 t0 = tcg_temp_new_i32();
3064 tcg_gen_trunc_tl_i32(t0, arg1);
3065 tcg_gen_bswap_i32(t0, t0);
3066 t1 = tcg_temp_new();
3067 tcg_gen_extu_i32_tl(t1, t0);
3068 tcg_temp_free_i32(t0);
3069 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3070 tcg_temp_free(t1);
3071 #else
3072 TCGv t0 = tcg_temp_new_i32();
3073 tcg_gen_bswap_i32(t0, arg1);
3074 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3075 tcg_temp_free(t0);
3076 #endif
3077 } else {
3078 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3079 }
3080 }
3081 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3082
3083 /*** Integer load and store multiple ***/
3084 /* lmw */
3085 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3086 {
3087 TCGv t0;
3088 TCGv_i32 t1;
3089 gen_set_access_type(ctx, ACCESS_INT);
3090 /* NIP cannot be restored if the memory exception comes from an helper */
3091 gen_update_nip(ctx, ctx->nip - 4);
3092 t0 = tcg_temp_new();
3093 t1 = tcg_const_i32(rD(ctx->opcode));
3094 gen_addr_imm_index(ctx, t0, 0);
3095 gen_helper_lmw(t0, t1);
3096 tcg_temp_free(t0);
3097 tcg_temp_free_i32(t1);
3098 }
3099
3100 /* stmw */
3101 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3102 {
3103 TCGv t0;
3104 TCGv_i32 t1;
3105 gen_set_access_type(ctx, ACCESS_INT);
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx, ctx->nip - 4);
3108 t0 = tcg_temp_new();
3109 t1 = tcg_const_i32(rS(ctx->opcode));
3110 gen_addr_imm_index(ctx, t0, 0);
3111 gen_helper_stmw(t0, t1);
3112 tcg_temp_free(t0);
3113 tcg_temp_free_i32(t1);
3114 }
3115
3116 /*** Integer load and store strings ***/
3117 /* lswi */
3118 /* PowerPC32 specification says we must generate an exception if
3119 * rA is in the range of registers to be loaded.
3120 * In an other hand, IBM says this is valid, but rA won't be loaded.
3121 * For now, I'll follow the spec...
3122 */
3123 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3124 {
3125 TCGv t0;
3126 TCGv_i32 t1, t2;
3127 int nb = NB(ctx->opcode);
3128 int start = rD(ctx->opcode);
3129 int ra = rA(ctx->opcode);
3130 int nr;
3131
3132 if (nb == 0)
3133 nb = 32;
3134 nr = nb / 4;
3135 if (unlikely(((start + nr) > 32 &&
3136 start <= ra && (start + nr - 32) > ra) ||
3137 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3138 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3139 return;
3140 }
3141 gen_set_access_type(ctx, ACCESS_INT);
3142 /* NIP cannot be restored if the memory exception comes from an helper */
3143 gen_update_nip(ctx, ctx->nip - 4);
3144 t0 = tcg_temp_new();
3145 gen_addr_register(ctx, t0);
3146 t1 = tcg_const_i32(nb);
3147 t2 = tcg_const_i32(start);
3148 gen_helper_lsw(t0, t1, t2);
3149 tcg_temp_free(t0);
3150 tcg_temp_free_i32(t1);
3151 tcg_temp_free_i32(t2);
3152 }
3153
3154 /* lswx */
3155 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3156 {
3157 TCGv t0;
3158 TCGv_i32 t1, t2, t3;
3159 gen_set_access_type(ctx, ACCESS_INT);
3160 /* NIP cannot be restored if the memory exception comes from an helper */
3161 gen_update_nip(ctx, ctx->nip - 4);
3162 t0 = tcg_temp_new();
3163 gen_addr_reg_index(ctx, t0);
3164 t1 = tcg_const_i32(rD(ctx->opcode));
3165 t2 = tcg_const_i32(rA(ctx->opcode));
3166 t3 = tcg_const_i32(rB(ctx->opcode));
3167 gen_helper_lswx(t0, t1, t2, t3);
3168 tcg_temp_free(t0);
3169 tcg_temp_free_i32(t1);
3170 tcg_temp_free_i32(t2);
3171 tcg_temp_free_i32(t3);
3172 }
3173
3174 /* stswi */
3175 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3176 {
3177 TCGv t0;
3178 TCGv_i32 t1, t2;
3179 int nb = NB(ctx->opcode);
3180 gen_set_access_type(ctx, ACCESS_INT);
3181 /* NIP cannot be restored if the memory exception comes from an helper */
3182 gen_update_nip(ctx, ctx->nip - 4);
3183 t0 = tcg_temp_new();
3184 gen_addr_register(ctx, t0);
3185 if (nb == 0)
3186 nb = 32;
3187 t1 = tcg_const_i32(nb);
3188 t2 = tcg_const_i32(rS(ctx->opcode));
3189 gen_helper_stsw(t0, t1, t2);
3190 tcg_temp_free(t0);
3191 tcg_temp_free_i32(t1);
3192 tcg_temp_free_i32(t2);
3193 }
3194
3195 /* stswx */
3196 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3197 {
3198 TCGv t0;
3199 TCGv_i32 t1, t2;
3200 gen_set_access_type(ctx, ACCESS_INT);
3201 /* NIP cannot be restored if the memory exception comes from an helper */
3202 gen_update_nip(ctx, ctx->nip - 4);
3203 t0 = tcg_temp_new();
3204 gen_addr_reg_index(ctx, t0);
3205 t1 = tcg_temp_new_i32();
3206 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3207 tcg_gen_andi_i32(t1, t1, 0x7F);
3208 t2 = tcg_const_i32(rS(ctx->opcode));
3209 gen_helper_stsw(t0, t1, t2);
3210 tcg_temp_free(t0);
3211 tcg_temp_free_i32(t1);
3212 tcg_temp_free_i32(t2);
3213 }
3214
3215 /*** Memory synchronisation ***/
3216 /* eieio */
3217 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3218 {
3219 }
3220
3221 /* isync */
3222 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3223 {
3224 gen_stop_exception(ctx);
3225 }
3226
3227 /* lwarx */
3228 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3229 {
3230 TCGv t0;
3231 gen_set_access_type(ctx, ACCESS_RES);
3232 t0 = tcg_temp_local_new();
3233 gen_addr_reg_index(ctx, t0);
3234 gen_check_align(ctx, t0, 0x03);
3235 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3236 tcg_gen_mov_tl(cpu_reserve, t0);
3237 tcg_temp_free(t0);
3238 }
3239
3240 /* stwcx. */
3241 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3242 {
3243 int l1;
3244 TCGv t0;
3245 gen_set_access_type(ctx, ACCESS_RES);
3246 t0 = tcg_temp_local_new();
3247 gen_addr_reg_index(ctx, t0);
3248 gen_check_align(ctx, t0, 0x03);
3249 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3250 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3251 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3252 l1 = gen_new_label();
3253 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3254 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3255 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3256 gen_set_label(l1);
3257 tcg_gen_movi_tl(cpu_reserve, -1);
3258 tcg_temp_free(t0);
3259 }
3260
3261 #if defined(TARGET_PPC64)
3262 /* ldarx */
3263 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3264 {
3265 TCGv t0;
3266 gen_set_access_type(ctx, ACCESS_RES);
3267 t0 = tcg_temp_local_new();
3268 gen_addr_reg_index(ctx, t0);
3269 gen_check_align(ctx, t0, 0x07);
3270 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3271 tcg_gen_mov_tl(cpu_reserve, t0);
3272 tcg_temp_free(t0);
3273 }
3274
3275 /* stdcx. */
3276 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3277 {
3278 int l1;
3279 TCGv t0;
3280 gen_set_access_type(ctx, ACCESS_RES);
3281 t0 = tcg_temp_local_new();
3282 gen_addr_reg_index(ctx, t0);
3283 gen_check_align(ctx, t0, 0x07);
3284 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3285 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3286 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3287 l1 = gen_new_label();
3288 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3289 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3290 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3291 gen_set_label(l1);
3292 tcg_gen_movi_tl(cpu_reserve, -1);
3293 tcg_temp_free(t0);
3294 }
3295 #endif /* defined(TARGET_PPC64) */
3296
3297 /* sync */
3298 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3299 {
3300 }
3301
3302 /* wait */
3303 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3304 {
3305 TCGv_i32 t0 = tcg_temp_new_i32();
3306 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3307 tcg_temp_free_i32(t0);
3308 /* Stop translation, as the CPU is supposed to sleep from now */
3309 gen_exception_err(ctx, EXCP_HLT, 1);
3310 }
3311
3312 /*** Floating-point load ***/
3313 #define GEN_LDF(name, ldop, opc, type) \
3314 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3315 { \
3316 TCGv EA; \
3317 if (unlikely(!ctx->fpu_enabled)) { \
3318 gen_exception(ctx, POWERPC_EXCP_FPU); \
3319 return; \
3320 } \
3321 gen_set_access_type(ctx, ACCESS_FLOAT); \
3322 EA = tcg_temp_new(); \
3323 gen_addr_imm_index(ctx, EA, 0); \
3324 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3325 tcg_temp_free(EA); \
3326 }
3327
3328 #define GEN_LDUF(name, ldop, opc, type) \
3329 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3330 { \
3331 TCGv EA; \
3332 if (unlikely(!ctx->fpu_enabled)) { \
3333 gen_exception(ctx, POWERPC_EXCP_FPU); \
3334 return; \
3335 } \
3336 if (unlikely(rA(ctx->opcode) == 0)) { \
3337 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3338 return; \
3339 } \
3340 gen_set_access_type(ctx, ACCESS_FLOAT); \
3341 EA = tcg_temp_new(); \
3342 gen_addr_imm_index(ctx, EA, 0); \
3343 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3344 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3345 tcg_temp_free(EA); \
3346 }
3347
3348 #define GEN_LDUXF(name, ldop, opc, type) \
3349 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3350 { \
3351 TCGv EA; \
3352 if (unlikely(!ctx->fpu_enabled)) { \
3353 gen_exception(ctx, POWERPC_EXCP_FPU); \
3354 return; \
3355 } \
3356 if (unlikely(rA(ctx->opcode) == 0)) { \
3357 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3358 return; \
3359 } \
3360 gen_set_access_type(ctx, ACCESS_FLOAT); \
3361 EA = tcg_temp_new(); \
3362 gen_addr_reg_index(ctx, EA); \
3363 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3364 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3365 tcg_temp_free(EA); \
3366 }
3367
3368 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3369 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3370 { \
3371 TCGv EA; \
3372 if (unlikely(!ctx->fpu_enabled)) { \
3373 gen_exception(ctx, POWERPC_EXCP_FPU); \
3374 return; \
3375 } \
3376 gen_set_access_type(ctx, ACCESS_FLOAT); \
3377 EA = tcg_temp_new(); \
3378 gen_addr_reg_index(ctx, EA); \
3379 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3380 tcg_temp_free(EA); \
3381 }
3382
3383 #define GEN_LDFS(name, ldop, op, type) \
3384 GEN_LDF(name, ldop, op | 0x20, type); \
3385 GEN_LDUF(name, ldop, op | 0x21, type); \
3386 GEN_LDUXF(name, ldop, op | 0x01, type); \
3387 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3388
3389 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3390 {
3391 TCGv t0 = tcg_temp_new();
3392 TCGv_i32 t1 = tcg_temp_new_i32();
3393 gen_qemu_ld32u(ctx, t0, arg2);
3394 tcg_gen_trunc_tl_i32(t1, t0);
3395 tcg_temp_free(t0);
3396 gen_helper_float32_to_float64(arg1, t1);
3397 tcg_temp_free_i32(t1);
3398 }
3399
3400 /* lfd lfdu lfdux lfdx */
3401 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3402 /* lfs lfsu lfsux lfsx */
3403 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3404
3405 /*** Floating-point store ***/
3406 #define GEN_STF(name, stop, opc, type) \
3407 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3408 { \
3409 TCGv EA; \
3410 if (unlikely(!ctx->fpu_enabled)) { \
3411 gen_exception(ctx, POWERPC_EXCP_FPU); \
3412 return; \
3413 } \
3414 gen_set_access_type(ctx, ACCESS_FLOAT); \
3415 EA = tcg_temp_new(); \
3416 gen_addr_imm_index(ctx, EA, 0); \
3417 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3418 tcg_temp_free(EA); \
3419 }
3420
3421 #define GEN_STUF(name, stop, opc, type) \
3422 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3423 { \
3424 TCGv EA; \
3425 if (unlikely(!ctx->fpu_enabled)) { \
3426 gen_exception(ctx, POWERPC_EXCP_FPU); \
3427 return; \
3428 } \
3429 if (unlikely(rA(ctx->opcode) == 0)) { \
3430 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3431 return; \
3432 } \
3433 gen_set_access_type(ctx, ACCESS_FLOAT); \
3434 EA = tcg_temp_new(); \
3435 gen_addr_imm_index(ctx, EA, 0); \
3436 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3437 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3438 tcg_temp_free(EA); \
3439 }
3440
3441 #define GEN_STUXF(name, stop, opc, type) \
3442 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3443 { \
3444 TCGv EA; \
3445 if (unlikely(!ctx->fpu_enabled)) { \
3446 gen_exception(ctx, POWERPC_EXCP_FPU); \
3447 return; \
3448 } \
3449 if (unlikely(rA(ctx->opcode) == 0)) { \
3450 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3451 return; \
3452 } \
3453 gen_set_access_type(ctx, ACCESS_FLOAT); \
3454 EA = tcg_temp_new(); \
3455 gen_addr_reg_index(ctx, EA); \
3456 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3457 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3458 tcg_temp_free(EA); \
3459 }
3460
3461 #define GEN_STXF(name, stop, opc2, opc3, type) \
3462 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3463 { \
3464 TCGv EA; \
3465 if (unlikely(!ctx->fpu_enabled)) { \
3466 gen_exception(ctx, POWERPC_EXCP_FPU); \
3467 return; \
3468 } \
3469 gen_set_access_type(ctx, ACCESS_FLOAT); \
3470 EA = tcg_temp_new(); \
3471 gen_addr_reg_index(ctx, EA); \
3472 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3473 tcg_temp_free(EA); \
3474 }
3475
3476 #define GEN_STFS(name, stop, op, type) \
3477 GEN_STF(name, stop, op | 0x20, type); \
3478 GEN_STUF(name, stop, op | 0x21, type); \
3479 GEN_STUXF(name, stop, op | 0x01, type); \
3480 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3481
3482 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3483 {
3484 TCGv_i32 t0 = tcg_temp_new_i32();
3485 TCGv t1 = tcg_temp_new();
3486 gen_helper_float64_to_float32(t0, arg1);
3487 tcg_gen_extu_i32_tl(t1, t0);
3488 tcg_temp_free_i32(t0);
3489 gen_qemu_st32(ctx, t1, arg2);
3490 tcg_temp_free(t1);
3491 }
3492
3493 /* stfd stfdu stfdux stfdx */
3494 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3495 /* stfs stfsu stfsux stfsx */
3496 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3497
3498 /* Optional: */
3499 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3500 {
3501 TCGv t0 = tcg_temp_new();
3502 tcg_gen_trunc_i64_tl(t0, arg1),
3503 gen_qemu_st32(ctx, t0, arg2);
3504 tcg_temp_free(t0);
3505 }
3506 /* stfiwx */
3507 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3508
3509 /*** Branch ***/
3510 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3511 target_ulong dest)
3512 {
3513 TranslationBlock *tb;
3514 tb = ctx->tb;
3515 #if defined(TARGET_PPC64)
3516 if (!ctx->sf_mode)
3517 dest = (uint32_t) dest;
3518 #endif
3519 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3520 likely(!ctx->singlestep_enabled)) {
3521 tcg_gen_goto_tb(n);
3522 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3523 tcg_gen_exit_tb((long)tb + n);
3524 } else {
3525 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3526 if (unlikely(ctx->singlestep_enabled)) {
3527 if ((ctx->singlestep_enabled &
3528 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3529 ctx->exception == POWERPC_EXCP_BRANCH) {
3530 target_ulong tmp = ctx->nip;
3531 ctx->nip = dest;
3532 gen_exception(ctx, POWERPC_EXCP_TRACE);
3533 ctx->nip = tmp;
3534 }
3535 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3536 gen_debug_exception(ctx);
3537 }
3538 }
3539 tcg_gen_exit_tb(0);
3540 }
3541 }
3542
3543 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3544 {
3545 #if defined(TARGET_PPC64)
3546 if (ctx->sf_mode == 0)
3547 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3548 else
3549 #endif
3550 tcg_gen_movi_tl(cpu_lr, nip);
3551 }
3552
3553 /* b ba bl bla */
3554 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3555 {
3556 target_ulong li, target;
3557
3558 ctx->exception = POWERPC_EXCP_BRANCH;
3559 /* sign extend LI */
3560 #if defined(TARGET_PPC64)
3561 if (ctx->sf_mode)
3562 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3563 else
3564 #endif
3565 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3566 if (likely(AA(ctx->opcode) == 0))
3567 target = ctx->nip + li - 4;
3568 else
3569 target = li;
3570 if (LK(ctx->opcode))
3571 gen_setlr(ctx, ctx->nip);
3572 gen_goto_tb(ctx, 0, target);
3573 }
3574
3575 #define BCOND_IM 0
3576 #define BCOND_LR 1
3577 #define BCOND_CTR 2
3578
3579 static always_inline void gen_bcond (DisasContext *ctx, int type)
3580 {
3581 uint32_t bo = BO(ctx->opcode);
3582 int l1 = gen_new_label();
3583 TCGv target;
3584
3585 ctx->exception = POWERPC_EXCP_BRANCH;
3586 if (type == BCOND_LR || type == BCOND_CTR) {
3587 target = tcg_temp_local_new();
3588 if (type == BCOND_CTR)
3589 tcg_gen_mov_tl(target, cpu_ctr);
3590 else
3591 tcg_gen_mov_tl(target, cpu_lr);
3592 }
3593 if (LK(ctx->opcode))
3594 gen_setlr(ctx, ctx->nip);
3595 l1 = gen_new_label();
3596 if ((bo & 0x4) == 0) {
3597 /* Decrement and test CTR */
3598 TCGv temp = tcg_temp_new();
3599 if (unlikely(type == BCOND_CTR)) {
3600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3601 return;
3602 }
3603 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3604 #if defined(TARGET_PPC64)
3605 if (!ctx->sf_mode)
3606 tcg_gen_ext32u_tl(temp, cpu_ctr);
3607 else
3608 #endif
3609 tcg_gen_mov_tl(temp, cpu_ctr);
3610 if (bo & 0x2) {
3611 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3612 } else {
3613 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3614 }
3615 tcg_temp_free(temp);
3616 }
3617 if ((bo & 0x10) == 0) {
3618 /* Test CR */
3619 uint32_t bi = BI(ctx->opcode);
3620 uint32_t mask = 1 << (3 - (bi & 0x03));
3621 TCGv_i32 temp = tcg_temp_new_i32();
3622
3623 if (bo & 0x8) {
3624 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3625 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3626 } else {
3627 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3628 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3629 }
3630 tcg_temp_free_i32(temp);
3631 }
3632 if (type == BCOND_IM) {
3633 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3634 if (likely(AA(ctx->opcode) == 0)) {
3635 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3636 } else {
3637 gen_goto_tb(ctx, 0, li);
3638 }
3639 gen_set_label(l1);
3640 gen_goto_tb(ctx, 1, ctx->nip);
3641 } else {
3642 #if defined(TARGET_PPC64)
3643 if (!(ctx->sf_mode))
3644 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3645 else
3646 #endif
3647 tcg_gen_andi_tl(cpu_nip, target, ~3);
3648 tcg_gen_exit_tb(0);
3649 gen_set_label(l1);
3650 #if defined(TARGET_PPC64)
3651 if (!(ctx->sf_mode))
3652 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3653 else
3654 #endif
3655 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3656 tcg_gen_exit_tb(0);
3657 }
3658 }
3659
3660 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3661 {
3662 gen_bcond(ctx, BCOND_IM);
3663 }
3664
3665 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3666 {
3667 gen_bcond(ctx, BCOND_CTR);
3668 }
3669
3670 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3671 {
3672 gen_bcond(ctx, BCOND_LR);
3673 }
3674
3675 /*** Condition register logical ***/
3676 #define GEN_CRLOGIC(name, tcg_op, opc) \
3677 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3678 { \
3679 uint8_t bitmask; \
3680 int sh; \
3681 TCGv_i32 t0, t1; \
3682 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3683 t0 = tcg_temp_new_i32(); \
3684 if (sh > 0) \
3685 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3686 else if (sh < 0) \
3687 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3688 else \
3689 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3690 t1 = tcg_temp_new_i32(); \
3691 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3692 if (sh > 0) \
3693 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3694 else if (sh < 0) \
3695 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3696 else \
3697 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3698 tcg_op(t0, t0, t1); \
3699 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3700 tcg_gen_andi_i32(t0, t0, bitmask); \
3701 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3702 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3703 tcg_temp_free_i32(t0); \
3704 tcg_temp_free_i32(t1); \
3705 }
3706
3707 /* crand */
3708 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3709 /* crandc */
3710 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3711 /* creqv */
3712 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3713 /* crnand */
3714 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3715 /* crnor */
3716 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3717 /* cror */
3718 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3719 /* crorc */
3720 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3721 /* crxor */
3722 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3723 /* mcrf */
3724 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3725 {
3726 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3727 }
3728
3729 /*** System linkage ***/
3730 /* rfi (mem_idx only) */
3731 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3732 {
3733 #if defined(CONFIG_USER_ONLY)
3734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3735 #else
3736 /* Restore CPU state */
3737 if (unlikely(!ctx->mem_idx)) {
3738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3739 return;
3740 }
3741 gen_helper_rfi();
3742 gen_sync_exception(ctx);
3743 #endif
3744 }
3745
3746 #if defined(TARGET_PPC64)
3747 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3748 {
3749 #if defined(CONFIG_USER_ONLY)
3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3751 #else
3752 /* Restore CPU state */
3753 if (unlikely(!ctx->mem_idx)) {
3754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3755 return;
3756 }
3757 gen_helper_rfid();
3758 gen_sync_exception(ctx);
3759 #endif
3760 }
3761
3762 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3763 {
3764 #if defined(CONFIG_USER_ONLY)
3765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3766 #else
3767 /* Restore CPU state */
3768 if (unlikely(ctx->mem_idx <= 1)) {
3769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3770 return;
3771 }
3772 gen_helper_hrfid();
3773 gen_sync_exception(ctx);
3774 #endif
3775 }
3776 #endif
3777
3778 /* sc */
3779 #if defined(CONFIG_USER_ONLY)
3780 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3781 #else
3782 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3783 #endif
3784 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3785 {
3786 uint32_t lev;
3787
3788 lev = (ctx->opcode >> 5) & 0x7F;
3789 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3790 }
3791
3792 /*** Trap ***/
3793 /* tw */
3794 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3795 {
3796 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3797 /* Update the nip since this might generate a trap exception */
3798 gen_update_nip(ctx, ctx->nip);
3799 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3800 tcg_temp_free_i32(t0);
3801 }
3802
3803 /* twi */
3804 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3805 {
3806 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3807 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3808 /* Update the nip since this might generate a trap exception */
3809 gen_update_nip(ctx, ctx->nip);
3810 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3811 tcg_temp_free(t0);
3812 tcg_temp_free_i32(t1);
3813 }
3814
3815 #if defined(TARGET_PPC64)
3816 /* td */
3817 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3818 {
3819 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3820 /* Update the nip since this might generate a trap exception */
3821 gen_update_nip(ctx, ctx->nip);
3822 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3823 tcg_temp_free_i32(t0);
3824 }
3825
3826 /* tdi */
3827 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3828 {
3829 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3830 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3831 /* Update the nip since this might generate a trap exception */
3832 gen_update_nip(ctx, ctx->nip);
3833 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3834 tcg_temp_free(t0);
3835 tcg_temp_free_i32(t1);
3836 }
3837 #endif
3838
3839 /*** Processor control ***/
3840 /* mcrxr */
3841 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3842 {
3843 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3844 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3845 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3846 }
3847
3848 /* mfcr mfocrf */
3849 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3850 {
3851 uint32_t crm, crn;
3852
3853 if (likely(ctx->opcode & 0x00100000)) {
3854 crm = CRM(ctx->opcode);
3855 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3856 crn = ctz32 (crm);
3857 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3858 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3859 cpu_gpr[rD(ctx->opcode)], crn * 4);
3860 }
3861 } else {
3862 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3863 }
3864 }
3865
3866 /* mfmsr */
3867 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3868 {
3869 #if defined(CONFIG_USER_ONLY)
3870 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3871 #else
3872 if (unlikely(!ctx->mem_idx)) {
3873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3874 return;
3875 }
3876 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3877 #endif
3878 }
3879
3880 #if 1
3881 #define SPR_NOACCESS ((void *)(-1UL))
3882 #else
3883 static void spr_noaccess (void *opaque, int sprn)
3884 {
3885 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3886 printf("ERROR: try to access SPR %d !\n", sprn);
3887 }
3888 #define SPR_NOACCESS (&spr_noaccess)
3889 #endif
3890
3891 /* mfspr */
3892 static always_inline void gen_op_mfspr (DisasContext *ctx)
3893 {
3894 void (*read_cb)(void *opaque, int gprn, int sprn);
3895 uint32_t sprn = SPR(ctx->opcode);
3896
3897 #if !defined(CONFIG_USER_ONLY)
3898 if (ctx->mem_idx == 2)
3899 read_cb = ctx->spr_cb[sprn].hea_read;
3900 else if (ctx->mem_idx)
3901 read_cb = ctx->spr_cb[sprn].oea_read;
3902 else
3903 #endif
3904 read_cb = ctx->spr_cb[sprn].uea_read;
3905 if (likely(read_cb != NULL)) {
3906 if (likely(read_cb != SPR_NOACCESS)) {
3907 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3908 } else {
3909 /* Privilege exception */
3910 /* This is a hack to avoid warnings when running Linux:
3911 * this OS breaks the PowerPC virtualisation model,
3912 * allowing userland application to read the PVR
3913 */
3914 if (sprn != SPR_PVR) {
3915 qemu_log("Trying to read privileged spr %d %03x at "
3916 ADDRX "\n", sprn, sprn, ctx->nip);
3917 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3918 sprn, sprn, ctx->nip);
3919 }
3920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3921 }
3922 } else {
3923 /* Not defined */
3924 qemu_log("Trying to read invalid spr %d %03x at "
3925 ADDRX "\n", sprn, sprn, ctx->nip);
3926 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3927 sprn, sprn, ctx->nip);
3928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3929 }
3930 }
3931
3932 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3933 {
3934 gen_op_mfspr(ctx);
3935 }
3936
3937 /* mftb */
3938 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3939 {
3940 gen_op_mfspr(ctx);
3941 }
3942
3943 /* mtcrf mtocrf*/
3944 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3945 {
3946 uint32_t crm, crn;
3947
3948 crm = CRM(ctx->opcode);
3949 if (likely((ctx->opcode & 0x00100000))) {
3950 if (crm && ((crm & (crm - 1)) == 0)) {
3951 TCGv_i32 temp = tcg_temp_new_i32();
3952 crn = ctz32 (crm);
3953 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3954 tcg_gen_shri_i32(temp, temp, crn * 4);
3955 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3956 tcg_temp_free_i32(temp);
3957 }
3958 } else {
3959 TCGv_i32 temp = tcg_const_i32(crm);
3960 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3961 tcg_temp_free_i32(temp);
3962 }
3963 }
3964
3965 /* mtmsr */
3966 #if defined(TARGET_PPC64)
3967 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3968 {
3969 #if defined(CONFIG_USER_ONLY)
3970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3971 #else
3972 if (unlikely(!ctx->mem_idx)) {
3973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3974 return;
3975 }
3976 if (ctx->opcode & 0x00010000) {
3977 /* Special form that does not need any synchronisation */
3978 TCGv t0 = tcg_temp_new();
3979 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3980 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3981 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3982 tcg_temp_free(t0);
3983 } else {
3984 /* XXX: we need to update nip before the store
3985 * if we enter power saving mode, we will exit the loop
3986 * directly from ppc_store_msr
3987 */
3988 gen_update_nip(ctx, ctx->nip);
3989 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3990 /* Must stop the translation as machine state (may have) changed */
3991 /* Note that mtmsr is not always defined as context-synchronizing */
3992 gen_stop_exception(ctx);
3993 }
3994 #endif
3995 }
3996 #endif
3997
3998 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3999 {
4000 #if defined(CONFIG_USER_ONLY)
4001 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4002 #else
4003 if (unlikely(!ctx->mem_idx)) {
4004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4005 return;
4006 }
4007 if (ctx->opcode & 0x00010000) {
4008 /* Special form that does not need any synchronisation */
4009 TCGv t0 = tcg_temp_new();
4010 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4011 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4012 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4013 tcg_temp_free(t0);
4014 } else {
4015 /* XXX: we need to update nip before the store
4016 * if we enter power saving mode, we will exit the loop
4017 * directly from ppc_store_msr
4018 */
4019 gen_update_nip(ctx, ctx->nip);
4020 #if defined(TARGET_PPC64)
4021 if (!ctx->sf_mode) {
4022 TCGv t0 = tcg_temp_new();
4023 TCGv t1 = tcg_temp_new();
4024 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4025 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4026 tcg_gen_or_tl(t0, t0, t1);
4027 tcg_temp_free(t1);
4028 gen_helper_store_msr(t0);
4029 tcg_temp_free(t0);
4030 } else
4031 #endif
4032 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4033 /* Must stop the translation as machine state (may have) changed */
4034 /* Note that mtmsr is not always defined as context-synchronizing */
4035 gen_stop_exception(ctx);
4036 }
4037 #endif
4038 }
4039
4040 /* mtspr */
4041 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4042 {
4043 void (*write_cb)(void *opaque, int sprn, int gprn);
4044 uint32_t sprn = SPR(ctx->opcode);
4045
4046 #if !defined(CONFIG_USER_ONLY)
4047 if (ctx->mem_idx == 2)
4048 write_cb = ctx->spr_cb[sprn].hea_write;
4049 else if (ctx->mem_idx)
4050 write_cb = ctx->spr_cb[sprn].oea_write;
4051 else
4052 #endif
4053 write_cb = ctx->spr_cb[sprn].uea_write;
4054 if (likely(write_cb != NULL)) {
4055 if (likely(write_cb != SPR_NOACCESS)) {
4056 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4057 } else {
4058 /* Privilege exception */
4059 qemu_log("Trying to write privileged spr %d %03x at "
4060 ADDRX "\n", sprn, sprn, ctx->nip);
4061 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4062 sprn, sprn, ctx->nip);
4063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4064 }
4065 } else {
4066 /* Not defined */
4067 qemu_log("Trying to write invalid spr %d %03x at "
4068 ADDRX "\n", sprn, sprn, ctx->nip);
4069 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4070 sprn, sprn, ctx->nip);
4071 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4072 }
4073 }
4074
4075 /*** Cache management ***/
4076 /* dcbf */
4077 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4078 {
4079 /* XXX: specification says this is treated as a load by the MMU */
4080 TCGv t0;
4081 gen_set_access_type(ctx, ACCESS_CACHE);
4082 t0 = tcg_temp_new();
4083 gen_addr_reg_index(ctx, t0);
4084 gen_qemu_ld8u(ctx, t0, t0);
4085 tcg_temp_free(t0);
4086 }
4087
4088 /* dcbi (Supervisor only) */
4089 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4090 {
4091 #if defined(CONFIG_USER_ONLY)
4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4093 #else
4094 TCGv EA, val;
4095 if (unlikely(!ctx->mem_idx)) {
4096 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4097 return;
4098 }
4099 EA = tcg_temp_new();
4100 gen_set_access_type(ctx, ACCESS_CACHE);
4101 gen_addr_reg_index(ctx, EA);
4102 val = tcg_temp_new();
4103 /* XXX: specification says this should be treated as a store by the MMU */
4104 gen_qemu_ld8u(ctx, val, EA);
4105 gen_qemu_st8(ctx, val, EA);
4106 tcg_temp_free(val);
4107 tcg_temp_free(EA);
4108 #endif
4109 }
4110
4111 /* dcdst */
4112 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4113 {
4114 /* XXX: specification say this is treated as a load by the MMU */
4115 TCGv t0;
4116 gen_set_access_type(ctx, ACCESS_CACHE);
4117 t0 = tcg_temp_new();
4118 gen_addr_reg_index(ctx, t0);
4119 gen_qemu_ld8u(ctx, t0, t0);
4120 tcg_temp_free(t0);
4121 }
4122
4123 /* dcbt */
4124 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4125 {
4126 /* interpreted as no-op */
4127 /* XXX: specification say this is treated as a load by the MMU
4128 * but does not generate any exception
4129 */
4130 }
4131
4132 /* dcbtst */
4133 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4134 {
4135 /* interpreted as no-op */
4136 /* XXX: specification say this is treated as a load by the MMU
4137 * but does not generate any exception
4138 */
4139 }
4140
4141 /* dcbz */
4142 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4143 {
4144 TCGv t0;
4145 gen_set_access_type(ctx, ACCESS_CACHE);
4146 /* NIP cannot be restored if the memory exception comes from an helper */
4147 gen_update_nip(ctx, ctx->nip - 4);
4148 t0 = tcg_temp_new();
4149 gen_addr_reg_index(ctx, t0);
4150 gen_helper_dcbz(t0);
4151 tcg_temp_free(t0);
4152 }
4153
4154 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4155 {
4156 TCGv t0;
4157 gen_set_access_type(ctx, ACCESS_CACHE);
4158 /* NIP cannot be restored if the memory exception comes from an helper */
4159 gen_update_nip(ctx, ctx->nip - 4);
4160 t0 = tcg_temp_new();
4161 gen_addr_reg_index(ctx, t0);
4162 if (ctx->opcode & 0x00200000)
4163 gen_helper_dcbz(t0);
4164 else
4165 gen_helper_dcbz_970(t0);
4166 tcg_temp_free(t0);
4167 }
4168
4169 /* dst / dstt */
4170 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4171 {
4172 if (rA(ctx->opcode) == 0) {
4173 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4174 } else {
4175 /* interpreted as no-op */
4176 }
4177 }
4178
4179 /* dstst /dststt */
4180 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4181 {
4182 if (rA(ctx->opcode) == 0) {
4183 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4184 } else {
4185 /* interpreted as no-op */
4186 }
4187
4188 }
4189
4190 /* dss / dssall */
4191 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4192 {
4193 /* interpreted as no-op */
4194 }
4195
4196 /* icbi */
4197 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4198 {
4199 TCGv t0;
4200 gen_set_access_type(ctx, ACCESS_CACHE);
4201 /* NIP cannot be restored if the memory exception comes from an helper */
4202 gen_update_nip(ctx, ctx->nip - 4);
4203 t0 = tcg_temp_new();
4204 gen_addr_reg_index(ctx, t0);
4205 gen_helper_icbi(t0);
4206 tcg_temp_free(t0);
4207 }
4208
4209 /* Optional: */
4210 /* dcba */
4211 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4212 {
4213 /* interpreted as no-op */
4214 /* XXX: specification say this is treated as a store by the MMU
4215 * but does not generate any exception
4216 */
4217 }
4218
4219 /*** Segment register manipulation ***/
4220 /* Supervisor only: */
4221 /* mfsr */
4222 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226 #else
4227 TCGv t0;
4228 if (unlikely(!ctx->mem_idx)) {
4229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4230 return;
4231 }
4232 t0 = tcg_const_tl(SR(ctx->opcode));
4233 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4234 tcg_temp_free(t0);
4235 #endif
4236 }
4237
4238 /* mfsrin */
4239 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4240 {
4241 #if defined(CONFIG_USER_ONLY)
4242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4243 #else
4244 TCGv t0;
4245 if (unlikely(!ctx->mem_idx)) {
4246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4247 return;
4248 }
4249 t0 = tcg_temp_new();
4250 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4251 tcg_gen_andi_tl(t0, t0, 0xF);
4252 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4253 tcg_temp_free(t0);
4254 #endif
4255 }
4256
4257 /* mtsr */
4258 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4259 {
4260 #if defined(CONFIG_USER_ONLY)
4261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4262 #else
4263 TCGv t0;
4264 if (unlikely(!ctx->mem_idx)) {
4265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4266 return;
4267 }
4268 t0 = tcg_const_tl(SR(ctx->opcode));
4269 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4270 tcg_temp_free(t0);
4271 #endif
4272 }
4273
4274 /* mtsrin */
4275 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4276 {
4277 #if defined(CONFIG_USER_ONLY)
4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4279 #else
4280 TCGv t0;
4281 if (unlikely(!ctx->mem_idx)) {
4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4283 return;
4284 }
4285 t0 = tcg_temp_new();
4286 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4287 tcg_gen_andi_tl(t0, t0, 0xF);
4288 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4289 tcg_temp_free(t0);
4290 #endif
4291 }
4292
4293 #if defined(TARGET_PPC64)
4294 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4295 /* mfsr */
4296 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4297 {
4298 #if defined(CONFIG_USER_ONLY)
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 #else
4301 TCGv t0;
4302 if (unlikely(!ctx->mem_idx)) {
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4304 return;
4305 }
4306 t0 = tcg_const_tl(SR(ctx->opcode));
4307 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4308 tcg_temp_free(t0);
4309 #endif
4310 }
4311
4312 /* mfsrin */
4313 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4314 PPC_SEGMENT_64B)
4315 {
4316 #if defined(CONFIG_USER_ONLY)
4317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4318 #else
4319 TCGv t0;
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 return;
4323 }
4324 t0 = tcg_temp_new();
4325 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4326 tcg_gen_andi_tl(t0, t0, 0xF);
4327 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4328 tcg_temp_free(t0);
4329 #endif
4330 }
4331
4332 /* mtsr */
4333 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4334 {
4335 #if defined(CONFIG_USER_ONLY)
4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4337 #else
4338 TCGv t0;
4339 if (unlikely(!ctx->mem_idx)) {
4340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4341 return;
4342 }
4343 t0 = tcg_const_tl(SR(ctx->opcode));
4344 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4345 tcg_temp_free(t0);
4346 #endif
4347 }
4348
4349 /* mtsrin */
4350 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4351 PPC_SEGMENT_64B)
4352 {
4353 #if defined(CONFIG_USER_ONLY)
4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4355 #else
4356 TCGv t0;
4357 if (unlikely(!ctx->mem_idx)) {
4358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4359 return;
4360 }
4361 t0 = tcg_temp_new();
4362 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4363 tcg_gen_andi_tl(t0, t0, 0xF);
4364 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4365 tcg_temp_free(t0);
4366 #endif
4367 }
4368
4369 /* slbmte */
4370 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4371 {
4372 #if defined(CONFIG_USER_ONLY)
4373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4374 #else
4375 if (unlikely(!ctx->mem_idx)) {
4376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4377 return;
4378 }
4379 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4380 #endif
4381 }
4382
4383 #endif /* defined(TARGET_PPC64) */
4384
4385 /*** Lookaside buffer management ***/
4386 /* Optional & mem_idx only: */
4387 /* tlbia */
4388 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4389 {
4390 #if defined(CONFIG_USER_ONLY)
4391 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4392 #else
4393 if (unlikely(!ctx->mem_idx)) {
4394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4395 return;
4396 }
4397 gen_helper_tlbia();
4398 #endif
4399 }
4400
4401 /* tlbiel */
4402 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE)
4403 {
4404 #if defined(CONFIG_USER_ONLY)
4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4406 #else
4407 if (unlikely(!ctx->mem_idx)) {
4408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4409 return;
4410 }
4411 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4412 #endif
4413 }
4414
4415 /* tlbie */
4416 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4417 {
4418 #if defined(CONFIG_USER_ONLY)
4419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4420 #else
4421 if (unlikely(!ctx->mem_idx)) {
4422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4423 return;
4424 }
4425 #if defined(TARGET_PPC64)
4426 if (!ctx->sf_mode) {
4427 TCGv t0 = tcg_temp_new();
4428 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4429 gen_helper_tlbie(t0);
4430 tcg_temp_free(t0);
4431 } else
4432 #endif
4433 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4434 #endif
4435 }
4436
4437 /* tlbsync */
4438 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4439 {
4440 #if defined(CONFIG_USER_ONLY)
4441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4442 #else
4443 if (unlikely(!ctx->mem_idx)) {
4444 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4445 return;
4446 }
4447 /* This has no effect: it should ensure that all previous
4448 * tlbie have completed
4449 */
4450 gen_stop_exception(ctx);
4451 #endif
4452 }
4453
4454 #if defined(TARGET_PPC64)
4455 /* slbia */
4456 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4457 {
4458 #if defined(CONFIG_USER_ONLY)
4459 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4460 #else
4461 if (unlikely(!ctx->mem_idx)) {
4462 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4463 return;
4464 }
4465 gen_helper_slbia();
4466 #endif
4467 }
4468
4469 /* slbie */
4470 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4471 {
4472 #if defined(CONFIG_USER_ONLY)
4473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4474 #else
4475 if (unlikely(!ctx->mem_idx)) {
4476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4477 return;
4478 }
4479 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4480 #endif
4481 }
4482 #endif
4483
4484 /*** External control ***/
4485 /* Optional: */
4486 /* eciwx */
4487 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4488 {
4489 TCGv t0;
4490 /* Should check EAR[E] ! */
4491 gen_set_access_type(ctx, ACCESS_EXT);
4492 t0 = tcg_temp_new();
4493 gen_addr_reg_index(ctx, t0);
4494 gen_check_align(ctx, t0, 0x03);
4495 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4496 tcg_temp_free(t0);
4497 }
4498
4499 /* ecowx */
4500 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4501 {
4502 TCGv t0;
4503 /* Should check EAR[E] ! */
4504 gen_set_access_type(ctx, ACCESS_EXT);
4505 t0 = tcg_temp_new();
4506 gen_addr_reg_index(ctx, t0);
4507 gen_check_align(ctx, t0, 0x03);
4508 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4509 tcg_temp_free(t0);
4510 }
4511
4512 /* PowerPC 601 specific instructions */
4513 /* abs - abs. */
4514 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4515 {
4516 int l1 = gen_new_label();
4517 int l2 = gen_new_label();
4518 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4519 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4520 tcg_gen_br(l2);
4521 gen_set_label(l1);
4522 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4523 gen_set_label(l2);
4524 if (unlikely(Rc(ctx->opcode) != 0))
4525 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4526 }
4527
4528 /* abso - abso. */
4529 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4530 {
4531 int l1 = gen_new_label();
4532 int l2 = gen_new_label();
4533 int l3 = gen_new_label();
4534 /* Start with XER OV disabled, the most likely case */
4535 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4536 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4537 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4538 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4539 tcg_gen_br(l2);
4540 gen_set_label(l1);
4541 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4542 tcg_gen_br(l3);
4543 gen_set_label(l2);
4544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4545 gen_set_label(l3);
4546 if (unlikely(Rc(ctx->opcode) != 0))
4547 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4548 }
4549
4550 /* clcs */
4551 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4552 {
4553 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4554 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4555 tcg_temp_free_i32(t0);
4556 /* Rc=1 sets CR0 to an undefined state */
4557 }
4558
4559 /* div - div. */
4560 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4561 {
4562 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4563 if (unlikely(Rc(ctx->opcode) != 0))
4564 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4565 }
4566
4567 /* divo - divo. */
4568 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4569 {
4570 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4571 if (unlikely(Rc(ctx->opcode) != 0))
4572 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4573 }
4574
4575 /* divs - divs. */
4576 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4577 {
4578 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4579 if (unlikely(Rc(ctx->opcode) != 0))
4580 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4581 }
4582
4583 /* divso - divso. */
4584 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4585 {
4586 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4587 if (unlikely(Rc(ctx->opcode) != 0))
4588 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4589 }
4590
4591 /* doz - doz. */
4592 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4593 {
4594 int l1 = gen_new_label();
4595 int l2 = gen_new_label();
4596 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4597 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4598 tcg_gen_br(l2);
4599 gen_set_label(l1);
4600 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4601 gen_set_label(l2);
4602 if (unlikely(Rc(ctx->opcode) != 0))
4603 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4604 }
4605
4606 /* dozo - dozo. */
4607 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4608 {
4609 int l1 = gen_new_label();
4610 int l2 = gen_new_label();
4611 TCGv t0 = tcg_temp_new();
4612 TCGv t1 = tcg_temp_new();
4613 TCGv t2 = tcg_temp_new();
4614 /* Start with XER OV disabled, the most likely case */
4615 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4616 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4617 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4618 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4619 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4620 tcg_gen_andc_tl(t1, t1, t2);
4621 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4622 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4623 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4624 tcg_gen_br(l2);
4625 gen_set_label(l1);
4626 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4627 gen_set_label(l2);
4628 tcg_temp_free(t0);
4629 tcg_temp_free(t1);
4630 tcg_temp_free(t2);
4631 if (unlikely(Rc(ctx->opcode) != 0))
4632 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4633 }
4634
4635 /* dozi */
4636 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4637 {
4638 target_long simm = SIMM(ctx->opcode);
4639 int l1 = gen_new_label();
4640 int l2 = gen_new_label();
4641 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4642 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4643 tcg_gen_br(l2);
4644 gen_set_label(l1);
4645 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4646 gen_set_label(l2);
4647 if (unlikely(Rc(ctx->opcode) != 0))
4648 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4649 }
4650
4651 /* lscbx - lscbx. */
4652 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4653 {
4654 TCGv t0 = tcg_temp_new();
4655 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4656 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4657 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4658
4659 gen_addr_reg_index(ctx, t0);
4660 /* NIP cannot be restored if the memory exception comes from an helper */
4661 gen_update_nip(ctx, ctx->nip - 4);
4662 gen_helper_lscbx(t0, t0, t1, t2, t3);
4663 tcg_temp_free_i32(t1);
4664 tcg_temp_free_i32(t2);
4665 tcg_temp_free_i32(t3);
4666 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4667 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4668 if (unlikely(Rc(ctx->opcode) != 0))
4669 gen_set_Rc0(ctx, t0);
4670 tcg_temp_free(t0);
4671 }
4672
4673 /* maskg - maskg. */
4674 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4675 {
4676 int l1 = gen_new_label();
4677 TCGv t0 = tcg_temp_new();
4678 TCGv t1 = tcg_temp_new();
4679 TCGv t2 = tcg_temp_new();
4680 TCGv t3 = tcg_temp_new();
4681 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4682 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4683 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4684 tcg_gen_addi_tl(t2, t0, 1);
4685 tcg_gen_shr_tl(t2, t3, t2);
4686 tcg_gen_shr_tl(t3, t3, t1);
4687 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4688 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4689 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4690 gen_set_label(l1);
4691 tcg_temp_free(t0);
4692 tcg_temp_free(t1);
4693 tcg_temp_free(t2);
4694 tcg_temp_free(t3);
4695 if (unlikely(Rc(ctx->opcode) != 0))
4696 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4697 }
4698
4699 /* maskir - maskir. */
4700 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4701 {
4702 TCGv t0 = tcg_temp_new();
4703 TCGv t1 = tcg_temp_new();
4704 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4705 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4706 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4707 tcg_temp_free(t0);
4708 tcg_temp_free(t1);
4709 if (unlikely(Rc(ctx->opcode) != 0))
4710 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4711 }
4712
4713 /* mul - mul. */
4714 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4715 {
4716 TCGv_i64 t0 = tcg_temp_new_i64();
4717 TCGv_i64 t1 = tcg_temp_new_i64();
4718 TCGv t2 = tcg_temp_new();
4719 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4720 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4721 tcg_gen_mul_i64(t0, t0, t1);
4722 tcg_gen_trunc_i64_tl(t2, t0);
4723 gen_store_spr(SPR_MQ, t2);
4724 tcg_gen_shri_i64(t1, t0, 32);
4725 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4726 tcg_temp_free_i64(t0);
4727 tcg_temp_free_i64(t1);
4728 tcg_temp_free(t2);
4729 if (unlikely(Rc(ctx->opcode) != 0))
4730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4731 }
4732
4733 /* mulo - mulo. */
4734 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4735 {
4736 int l1 = gen_new_label();
4737 TCGv_i64 t0 = tcg_temp_new_i64();
4738 TCGv_i64 t1 = tcg_temp_new_i64();
4739 TCGv t2 = tcg_temp_new();
4740 /* Start with XER OV disabled, the most likely case */
4741 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4742 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4743 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4744 tcg_gen_mul_i64(t0, t0, t1);
4745 tcg_gen_trunc_i64_tl(t2, t0);
4746 gen_store_spr(SPR_MQ, t2);
4747 tcg_gen_shri_i64(t1, t0, 32);
4748 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4749 tcg_gen_ext32s_i64(t1, t0);
4750 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4751 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4752 gen_set_label(l1);
4753 tcg_temp_free_i64(t0);
4754 tcg_temp_free_i64(t1);
4755 tcg_temp_free(t2);
4756 if (unlikely(Rc(ctx->opcode) != 0))
4757 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4758 }
4759
4760 /* nabs - nabs. */
4761 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4762 {
4763 int l1 = gen_new_label();
4764 int l2 = gen_new_label();
4765 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4766 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4767 tcg_gen_br(l2);
4768 gen_set_label(l1);
4769 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4770 gen_set_label(l2);
4771 if (unlikely(Rc(ctx->opcode) != 0))
4772 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4773 }
4774
4775 /* nabso - nabso. */
4776 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4777 {
4778 int l1 = gen_new_label();
4779 int l2 = gen_new_label();
4780 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4781 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4782 tcg_gen_br(l2);
4783 gen_set_label(l1);
4784 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4785 gen_set_label(l2);
4786 /* nabs never overflows */
4787 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4788 if (unlikely(Rc(ctx->opcode) != 0))
4789 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4790 }
4791
4792 /* rlmi - rlmi. */
4793 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4794 {
4795 uint32_t mb = MB(ctx->opcode);
4796 uint32_t me = ME(ctx->opcode);
4797 TCGv t0 = tcg_temp_new();
4798 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4799 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4800 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4801 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4802 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4803 tcg_temp_free(t0);
4804 if (unlikely(Rc(ctx->opcode) != 0))
4805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4806 }
4807
4808 /* rrib - rrib. */
4809 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4810 {
4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4814 tcg_gen_movi_tl(t1, 0x80000000);
4815 tcg_gen_shr_tl(t1, t1, t0);
4816 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4817 tcg_gen_and_tl(t0, t0, t1);
4818 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4819 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4820 tcg_temp_free(t0);
4821 tcg_temp_free(t1);
4822 if (unlikely(Rc(ctx->opcode) != 0))
4823 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4824 }
4825
4826 /* sle - sle. */
4827 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4828 {
4829 TCGv t0 = tcg_temp_new();
4830 TCGv t1 = tcg_temp_new();
4831 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4832 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4833 tcg_gen_subfi_tl(t1, 32, t1);
4834 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4835 tcg_gen_or_tl(t1, t0, t1);
4836 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4837 gen_store_spr(SPR_MQ, t1);
4838 tcg_temp_free(t0);
4839 tcg_temp_free(t1);
4840 if (unlikely(Rc(ctx->opcode) != 0))
4841 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4842 }
4843
4844 /* sleq - sleq. */
4845 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4846 {
4847 TCGv t0 = tcg_temp_new();
4848 TCGv t1 = tcg_temp_new();
4849 TCGv t2 = tcg_temp_new();
4850 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4851 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4852 tcg_gen_shl_tl(t2, t2, t0);
4853 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4854 gen_load_spr(t1, SPR_MQ);
4855 gen_store_spr(SPR_MQ, t0);
4856 tcg_gen_and_tl(t0, t0, t2);
4857 tcg_gen_andc_tl(t1, t1, t2);
4858 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4859 tcg_temp_free(t0);
4860 tcg_temp_free(t1);
4861 tcg_temp_free(t2);
4862 if (unlikely(Rc(ctx->opcode) != 0))
4863 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4864 }
4865
4866 /* sliq - sliq. */
4867 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4868 {
4869 int sh = SH(ctx->opcode);
4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4873 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4874 tcg_gen_or_tl(t1, t0, t1);
4875 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4876 gen_store_spr(SPR_MQ, t1);
4877 tcg_temp_free(t0);
4878 tcg_temp_free(t1);
4879 if (unlikely(Rc(ctx->opcode) != 0))
4880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4881 }
4882
4883 /* slliq - slliq. */
4884 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4885 {
4886 int sh = SH(ctx->opcode);
4887 TCGv t0 = tcg_temp_new();
4888 TCGv t1 = tcg_temp_new();
4889 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4890 gen_load_spr(t1, SPR_MQ);
4891 gen_store_spr(SPR_MQ, t0);
4892 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4893 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4894 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4895 tcg_temp_free(t0);
4896 tcg_temp_free(t1);
4897 if (unlikely(Rc(ctx->opcode) != 0))
4898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4899 }
4900
4901 /* sllq - sllq. */
4902 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4903 {
4904 int l1 = gen_new_label();
4905 int l2 = gen_new_label();
4906 TCGv t0 = tcg_temp_local_new();
4907 TCGv t1 = tcg_temp_local_new();
4908 TCGv t2 = tcg_temp_local_new();
4909 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4910 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4911 tcg_gen_shl_tl(t1, t1, t2);
4912 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4913 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4914 gen_load_spr(t0, SPR_MQ);
4915 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4916 tcg_gen_br(l2);
4917 gen_set_label(l1);
4918 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4919 gen_load_spr(t2, SPR_MQ);
4920 tcg_gen_andc_tl(t1, t2, t1);
4921 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4922 gen_set_label(l2);
4923 tcg_temp_free(t0);
4924 tcg_temp_free(t1);
4925 tcg_temp_free(t2);
4926 if (unlikely(Rc(ctx->opcode) != 0))
4927 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4928 }
4929
4930 /* slq - slq. */
4931 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4932 {
4933 int l1 = gen_new_label();
4934 TCGv t0 = tcg_temp_new();
4935 TCGv t1 = tcg_temp_new();
4936 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4937 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4938 tcg_gen_subfi_tl(t1, 32, t1);
4939 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4940 tcg_gen_or_tl(t1, t0, t1);
4941 gen_store_spr(SPR_MQ, t1);
4942 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4944 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4945 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4946 gen_set_label(l1);
4947 tcg_temp_free(t0);
4948 tcg_temp_free(t1);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4951 }
4952
4953 /* sraiq - sraiq. */
4954 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4955 {
4956 int sh = SH(ctx->opcode);
4957 int l1 = gen_new_label();
4958 TCGv t0 = tcg_temp_new();
4959 TCGv t1 = tcg_temp_new();
4960 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4961 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4962 tcg_gen_or_tl(t0, t0, t1);
4963 gen_store_spr(SPR_MQ, t0);
4964 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4965 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4966 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4967 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4968 gen_set_label(l1);
4969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974 }
4975
4976 /* sraq - sraq. */
4977 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4978 {
4979 int l1 = gen_new_label();
4980 int l2 = gen_new_label();
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_local_new();
4983 TCGv t2 = tcg_temp_local_new();
4984 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4985 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4986 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4987 tcg_gen_subfi_tl(t2, 32, t2);
4988 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4989 tcg_gen_or_tl(t0, t0, t2);
4990 gen_store_spr(SPR_MQ, t0);
4991 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4992 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4993 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4994 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4995 gen_set_label(l1);
4996 tcg_temp_free(t0);
4997 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4998 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4999 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5000 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5001 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
5002 gen_set_label(l2);
5003 tcg_temp_free(t1);
5004 tcg_temp_free(t2);
5005 if (unlikely(Rc(ctx->opcode) != 0))
5006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5007 }
5008
5009 /* sre - sre. */
5010 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
5011 {
5012 TCGv t0 = tcg_temp_new();
5013 TCGv t1 = tcg_temp_new();
5014 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5015 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5016 tcg_gen_subfi_tl(t1, 32, t1);
5017 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5018 tcg_gen_or_tl(t1, t0, t1);
5019 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5020 gen_store_spr(SPR_MQ, t1);
5021 tcg_temp_free(t0);
5022 tcg_temp_free(t1);
5023 if (unlikely(Rc(ctx->opcode) != 0))
5024 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5025 }
5026
5027 /* srea - srea. */
5028 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
5029 {
5030 TCGv t0 = tcg_temp_new();
5031 TCGv t1 = tcg_temp_new();
5032 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5033 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5034 gen_store_spr(SPR_MQ, t0);
5035 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5036 tcg_temp_free(t0);
5037 tcg_temp_free(t1);
5038 if (unlikely(Rc(ctx->opcode) != 0))
5039 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5040 }
5041
5042 /* sreq */
5043 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5044 {
5045 TCGv t0 = tcg_temp_new();
5046 TCGv t1 = tcg_temp_new();
5047 TCGv t2 = tcg_temp_new();
5048 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5049 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5050 tcg_gen_shr_tl(t1, t1, t0);
5051 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5052 gen_load_spr(t2, SPR_MQ);
5053 gen_store_spr(SPR_MQ, t0);
5054 tcg_gen_and_tl(t0, t0, t1);
5055 tcg_gen_andc_tl(t2, t2, t1);
5056 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5057 tcg_temp_free(t0);
5058 tcg_temp_free(t1);
5059 tcg_temp_free(t2);
5060 if (unlikely(Rc(ctx->opcode) != 0))
5061 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5062 }
5063
5064 /* sriq */
5065 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5066 {
5067 int sh = SH(ctx->opcode);
5068 TCGv t0 = tcg_temp_new();
5069 TCGv t1 = tcg_temp_new();
5070 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5071 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5072 tcg_gen_or_tl(t1, t0, t1);
5073 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5074 gen_store_spr(SPR_MQ, t1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
5077 if (unlikely(Rc(ctx->opcode) != 0))
5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5079 }
5080
5081 /* srliq */
5082 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5083 {
5084 int sh = SH(ctx->opcode);
5085 TCGv t0 = tcg_temp_new();
5086 TCGv t1 = tcg_temp_new();
5087 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5088 gen_load_spr(t1, SPR_MQ);
5089 gen_store_spr(SPR_MQ, t0);
5090 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5091 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5092 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5093 tcg_temp_free(t0);
5094 tcg_temp_free(t1);
5095 if (unlikely(Rc(ctx->opcode) != 0))
5096 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5097 }
5098
5099 /* srlq */
5100 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5101 {
5102 int l1 = gen_new_label();
5103 int l2 = gen_new_label();
5104 TCGv t0 = tcg_temp_local_new();
5105 TCGv t1 = tcg_temp_local_new();
5106 TCGv t2 = tcg_temp_local_new();
5107 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5108 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5109 tcg_gen_shr_tl(t2, t1, t2);
5110 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5111 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5112 gen_load_spr(t0, SPR_MQ);
5113 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5114 tcg_gen_br(l2);
5115 gen_set_label(l1);
5116 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5117 tcg_gen_and_tl(t0, t0, t2);
5118 gen_load_spr(t1, SPR_MQ);
5119 tcg_gen_andc_tl(t1, t1, t2);
5120 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5121 gen_set_label(l2);
5122 tcg_temp_free(t0);
5123 tcg_temp_free(t1);
5124 tcg_temp_free(t2);
5125 if (unlikely(Rc(ctx->opcode) != 0))
5126 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5127 }
5128
5129 /* srq */
5130 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5131 {
5132 int l1 = gen_new_label();
5133 TCGv t0 = tcg_temp_new();
5134 TCGv t1 = tcg_temp_new();
5135 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5136 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5137 tcg_gen_subfi_tl(t1, 32, t1);
5138 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5139 tcg_gen_or_tl(t1, t0, t1);
5140 gen_store_spr(SPR_MQ, t1);
5141 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5142 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5143 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5144 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5145 gen_set_label(l1);
5146 tcg_temp_free(t0);
5147 tcg_temp_free(t1);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5150 }
5151
5152 /* PowerPC 602 specific instructions */
5153 /* dsa */
5154 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5155 {
5156 /* XXX: TODO */
5157 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5158 }
5159
5160 /* esa */
5161 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5162 {
5163 /* XXX: TODO */
5164 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5165 }
5166
5167 /* mfrom */
5168 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5169 {
5170 #if defined(CONFIG_USER_ONLY)
5171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5172 #else
5173 if (unlikely(!ctx->mem_idx)) {
5174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5175 return;
5176 }
5177 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5178 #endif
5179 }
5180
5181 /* 602 - 603 - G2 TLB management */
5182 /* tlbld */
5183 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5184 {
5185 #if defined(CONFIG_USER_ONLY)
5186 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5187 #else
5188 if (unlikely(!ctx->mem_idx)) {
5189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5190 return;
5191 }
5192 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5193 #endif
5194 }
5195
5196 /* tlbli */
5197 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5198 {
5199 #if defined(CONFIG_USER_ONLY)
5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5201 #else
5202 if (unlikely(!ctx->mem_idx)) {
5203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5204 return;
5205 }
5206 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5207 #endif
5208 }
5209
5210 /* 74xx TLB management */
5211 /* tlbld */
5212 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5213 {
5214 #if defined(CONFIG_USER_ONLY)
5215 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5216 #else
5217 if (unlikely(!ctx->mem_idx)) {
5218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5219 return;
5220 }
5221 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5222 #endif
5223 }
5224
5225 /* tlbli */
5226 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5227 {
5228 #if defined(CONFIG_USER_ONLY)
5229 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5230 #else
5231 if (unlikely(!ctx->mem_idx)) {
5232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5233 return;
5234 }
5235 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5236 #endif
5237 }
5238
5239 /* POWER instructions not in PowerPC 601 */
5240 /* clf */
5241 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5242 {
5243 /* Cache line flush: implemented as no-op */
5244 }
5245
5246 /* cli */
5247 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5248 {
5249 /* Cache line invalidate: privileged and treated as no-op */
5250 #if defined(CONFIG_USER_ONLY)
5251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5252 #else
5253 if (unlikely(!ctx->mem_idx)) {
5254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5255 return;
5256 }
5257 #endif
5258 }
5259
5260 /* dclst */
5261 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5262 {
5263 /* Data cache line store: treated as no-op */
5264 }
5265
5266 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5267 {
5268 #if defined(CONFIG_USER_ONLY)
5269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5270 #else
5271 int ra = rA(ctx->opcode);
5272 int rd = rD(ctx->opcode);
5273 TCGv t0;
5274 if (unlikely(!ctx->mem_idx)) {
5275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5276 return;
5277 }
5278 t0 = tcg_temp_new();
5279 gen_addr_reg_index(ctx, t0);
5280 tcg_gen_shri_tl(t0, t0, 28);
5281 tcg_gen_andi_tl(t0, t0, 0xF);
5282 gen_helper_load_sr(cpu_gpr[rd], t0);
5283 tcg_temp_free(t0);
5284 if (ra != 0 && ra != rd)
5285 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5286 #endif
5287 }
5288
5289 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5290 {
5291 #if defined(CONFIG_USER_ONLY)
5292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5293 #else
5294 TCGv t0;
5295 if (unlikely(!ctx->mem_idx)) {
5296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5297 return;
5298 }
5299 t0 = tcg_temp_new();
5300 gen_addr_reg_index(ctx, t0);
5301 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5302 tcg_temp_free(t0);
5303 #endif
5304 }
5305
5306 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5307 {
5308 #if defined(CONFIG_USER_ONLY)
5309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5310 #else
5311 if (unlikely(!ctx->mem_idx)) {
5312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5313 return;
5314 }
5315 gen_helper_rfsvc();
5316 gen_sync_exception(ctx);
5317 #endif
5318 }
5319
5320 /* svc is not implemented for now */
5321
5322 /* POWER2 specific instructions */
5323 /* Quad manipulation (load/store two floats at a time) */
5324
5325 /* lfq */
5326 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5327 {
5328 int rd = rD(ctx->opcode);
5329 TCGv t0;
5330 gen_set_access_type(ctx, ACCESS_FLOAT);
5331 t0 = tcg_temp_new();
5332 gen_addr_imm_index(ctx, t0, 0);
5333 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5334 gen_addr_add(ctx, t0, t0, 8);
5335 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5336 tcg_temp_free(t0);
5337 }
5338
5339 /* lfqu */
5340 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5341 {
5342 int ra = rA(ctx->opcode);
5343 int rd = rD(ctx->opcode);
5344 TCGv t0, t1;
5345 gen_set_access_type(ctx, ACCESS_FLOAT);
5346 t0 = tcg_temp_new();
5347 t1 = tcg_temp_new();
5348 gen_addr_imm_index(ctx, t0, 0);
5349 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5350 gen_addr_add(ctx, t1, t0, 8);
5351 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5352 if (ra != 0)
5353 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5354 tcg_temp_free(t0);
5355 tcg_temp_free(t1);
5356 }
5357
5358 /* lfqux */
5359 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5360 {
5361 int ra = rA(ctx->opcode);
5362 int rd = rD(ctx->opcode);
5363 gen_set_access_type(ctx, ACCESS_FLOAT);
5364 TCGv t0, t1;
5365 t0 = tcg_temp_new();
5366 gen_addr_reg_index(ctx, t0);
5367 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5368 t1 = tcg_temp_new();
5369 gen_addr_add(ctx, t1, t0, 8);
5370 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5371 tcg_temp_free(t1);
5372 if (ra != 0)
5373 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5374 tcg_temp_free(t0);
5375 }
5376
5377 /* lfqx */
5378 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5379 {
5380 int rd = rD(ctx->opcode);
5381 TCGv t0;
5382 gen_set_access_type(ctx, ACCESS_FLOAT);
5383 t0 = tcg_temp_new();
5384 gen_addr_reg_index(ctx, t0);
5385 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5386 gen_addr_add(ctx, t0, t0, 8);
5387 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5388 tcg_temp_free(t0);
5389 }
5390
5391 /* stfq */
5392 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5393 {
5394 int rd = rD(ctx->opcode);
5395 TCGv t0;
5396 gen_set_access_type(ctx, ACCESS_FLOAT);
5397 t0 = tcg_temp_new();
5398 gen_addr_imm_index(ctx, t0, 0);
5399 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5400 gen_addr_add(ctx, t0, t0, 8);
5401 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5402 tcg_temp_free(t0);
5403 }
5404
5405 /* stfqu */
5406 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5407 {
5408 int ra = rA(ctx->opcode);
5409 int rd = rD(ctx->opcode);
5410 TCGv t0, t1;
5411 gen_set_access_type(ctx, ACCESS_FLOAT);
5412 t0 = tcg_temp_new();
5413 gen_addr_imm_index(ctx, t0, 0);
5414 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5415 t1 = tcg_temp_new();
5416 gen_addr_add(ctx, t1, t0, 8);
5417 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5418 tcg_temp_free(t1);
5419 if (ra != 0)
5420 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5421 tcg_temp_free(t0);
5422 }
5423
5424 /* stfqux */
5425 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5426 {
5427 int ra = rA(ctx->opcode);
5428 int rd = rD(ctx->opcode);
5429 TCGv t0, t1;
5430 gen_set_access_type(ctx, ACCESS_FLOAT);
5431 t0 = tcg_temp_new();
5432 gen_addr_reg_index(ctx, t0);
5433 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5434 t1 = tcg_temp_new();
5435 gen_addr_add(ctx, t1, t0, 8);
5436 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5437 tcg_temp_free(t1);
5438 if (ra != 0)
5439 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5440 tcg_temp_free(t0);
5441 }
5442
5443 /* stfqx */
5444 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5445 {
5446 int rd = rD(ctx->opcode);
5447 TCGv t0;
5448 gen_set_access_type(ctx, ACCESS_FLOAT);
5449 t0 = tcg_temp_new();
5450 gen_addr_reg_index(ctx, t0);
5451 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5452 gen_addr_add(ctx, t0, t0, 8);
5453 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5454 tcg_temp_free(t0);
5455 }
5456
5457 /* BookE specific instructions */
5458 /* XXX: not implemented on 440 ? */
5459 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5460 {
5461 /* XXX: TODO */
5462 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5463 }
5464
5465 /* XXX: not implemented on 440 ? */
5466 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5467 {
5468 #if defined(CONFIG_USER_ONLY)
5469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5470 #else
5471 TCGv t0;
5472 if (unlikely(!ctx->mem_idx)) {
5473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5474 return;
5475 }
5476 t0 = tcg_temp_new();
5477 gen_addr_reg_index(ctx, t0);
5478 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5479 tcg_temp_free(t0);
5480 #endif
5481 }
5482
5483 /* All 405 MAC instructions are translated here */
5484 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5485 int opc2, int opc3,
5486 int ra, int rb, int rt, int Rc)
5487 {
5488 TCGv t0, t1;
5489
5490 t0 = tcg_temp_local_new();
5491 t1 = tcg_temp_local_new();
5492
5493 switch (opc3 & 0x0D) {
5494 case 0x05:
5495 /* macchw - macchw. - macchwo - macchwo. */
5496 /* macchws - macchws. - macchwso - macchwso. */
5497 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5498 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5499 /* mulchw - mulchw. */
5500 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5501 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5502 tcg_gen_ext16s_tl(t1, t1);
5503 break;
5504 case 0x04:
5505 /* macchwu - macchwu. - macchwuo - macchwuo. */
5506 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5507 /* mulchwu - mulchwu. */
5508 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5509 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5510 tcg_gen_ext16u_tl(t1, t1);
5511 break;
5512 case 0x01:
5513 /* machhw - machhw. - machhwo - machhwo. */
5514 /* machhws - machhws. - machhwso - machhwso. */
5515 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5516 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5517 /* mulhhw - mulhhw. */
5518 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5519 tcg_gen_ext16s_tl(t0, t0);
5520 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5521 tcg_gen_ext16s_tl(t1, t1);
5522 break;
5523 case 0x00:
5524 /* machhwu - machhwu. - machhwuo - machhwuo. */
5525 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5526 /* mulhhwu - mulhhwu. */
5527 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5528 tcg_gen_ext16u_tl(t0, t0);
5529 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5530 tcg_gen_ext16u_tl(t1, t1);
5531 break;
5532 case 0x0D:
5533 /* maclhw - maclhw. - maclhwo - maclhwo. */
5534 /* maclhws - maclhws. - maclhwso - maclhwso. */
5535 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5536 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5537 /* mullhw - mullhw. */
5538 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5539 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5540 break;
5541 case 0x0C:
5542 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5543 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5544 /* mullhwu - mullhwu. */
5545 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5546 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5547 break;
5548 }
5549 if (opc2 & 0x04) {
5550 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5551 tcg_gen_mul_tl(t1, t0, t1);
5552 if (opc2 & 0x02) {
5553 /* nmultiply-and-accumulate (0x0E) */
5554 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5555 } else {
5556 /* multiply-and-accumulate (0x0C) */
5557 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5558 }
5559
5560 if (opc3 & 0x12) {
5561 /* Check overflow and/or saturate */
5562 int l1 = gen_new_label();
5563
5564 if (opc3 & 0x10) {
5565 /* Start with XER OV disabled, the most likely case */
5566 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5567 }
5568 if (opc3 & 0x01) {
5569 /* Signed */
5570 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5571 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5572 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5573 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5574 if (opc3 & 0x02) {
5575 /* Saturate */
5576 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5577 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5578 }
5579 } else {
5580 /* Unsigned */
5581 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5582 if (opc3 & 0x02) {
5583 /* Saturate */
5584 tcg_gen_movi_tl(t0, UINT32_MAX);
5585 }
5586 }
5587 if (opc3 & 0x10) {
5588 /* Check overflow */
5589 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5590 }
5591 gen_set_label(l1);
5592 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5593 }
5594 } else {
5595 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5596 }
5597 tcg_temp_free(t0);
5598 tcg_temp_free(t1);
5599 if (unlikely(Rc) != 0) {
5600 /* Update Rc0 */
5601 gen_set_Rc0(ctx, cpu_gpr[rt]);
5602 }
5603 }
5604
5605 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5606 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5607 { \
5608 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5609 rD(ctx->opcode), Rc(ctx->opcode)); \
5610 }
5611
5612 /* macchw - macchw. */
5613 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5614 /* macchwo - macchwo. */
5615 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5616 /* macchws - macchws. */
5617 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5618 /* macchwso - macchwso. */
5619 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5620 /* macchwsu - macchwsu. */
5621 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5622 /* macchwsuo - macchwsuo. */
5623 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5624 /* macchwu - macchwu. */
5625 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5626 /* macchwuo - macchwuo. */
5627 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5628 /* machhw - machhw. */
5629 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5630 /* machhwo - machhwo. */
5631 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5632 /* machhws - machhws. */
5633 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5634 /* machhwso - machhwso. */
5635 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5636 /* machhwsu - machhwsu. */
5637 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5638 /* machhwsuo - machhwsuo. */
5639 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5640 /* machhwu - machhwu. */
5641 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5642 /* machhwuo - machhwuo. */
5643 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5644 /* maclhw - maclhw. */
5645 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5646 /* maclhwo - maclhwo. */
5647 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5648 /* maclhws - maclhws. */
5649 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5650 /* maclhwso - maclhwso. */
5651 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5652 /* maclhwu - maclhwu. */
5653 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5654 /* maclhwuo - maclhwuo. */
5655 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5656 /* maclhwsu - maclhwsu. */
5657 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5658 /* maclhwsuo - maclhwsuo. */
5659 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5660 /* nmacchw - nmacchw. */
5661 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5662 /* nmacchwo - nmacchwo. */
5663 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5664 /* nmacchws - nmacchws. */
5665 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5666 /* nmacchwso - nmacchwso. */
5667 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5668 /* nmachhw - nmachhw. */
5669 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5670 /* nmachhwo - nmachhwo. */
5671 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5672 /* nmachhws - nmachhws. */
5673 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5674 /* nmachhwso - nmachhwso. */
5675 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5676 /* nmaclhw - nmaclhw. */
5677 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5678 /* nmaclhwo - nmaclhwo. */
5679 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5680 /* nmaclhws - nmaclhws. */
5681 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5682 /* nmaclhwso - nmaclhwso. */
5683 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5684
5685 /* mulchw - mulchw. */
5686 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5687 /* mulchwu - mulchwu. */
5688 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5689 /* mulhhw - mulhhw. */
5690 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5691 /* mulhhwu - mulhhwu. */
5692 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5693 /* mullhw - mullhw. */
5694 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5695 /* mullhwu - mullhwu. */
5696 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5697
5698 /* mfdcr */
5699 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5700 {
5701 #if defined(CONFIG_USER_ONLY)
5702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5703 #else
5704 TCGv dcrn;
5705 if (unlikely(!ctx->mem_idx)) {
5706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5707 return;
5708 }
5709 /* NIP cannot be restored if the memory exception comes from an helper */
5710 gen_update_nip(ctx, ctx->nip - 4);
5711 dcrn = tcg_const_tl(SPR(ctx->opcode));
5712 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5713 tcg_temp_free(dcrn);
5714 #endif
5715 }
5716
5717 /* mtdcr */
5718 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5719 {
5720 #if defined(CONFIG_USER_ONLY)
5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5722 #else
5723 TCGv dcrn;
5724 if (unlikely(!ctx->mem_idx)) {
5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5726 return;
5727 }
5728 /* NIP cannot be restored if the memory exception comes from an helper */
5729 gen_update_nip(ctx, ctx->nip - 4);
5730 dcrn = tcg_const_tl(SPR(ctx->opcode));
5731 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5732 tcg_temp_free(dcrn);
5733 #endif
5734 }
5735
5736 /* mfdcrx */
5737 /* XXX: not implemented on 440 ? */
5738 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5742 #else
5743 if (unlikely(!ctx->mem_idx)) {
5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5745 return;
5746 }
5747 /* NIP cannot be restored if the memory exception comes from an helper */
5748 gen_update_nip(ctx, ctx->nip - 4);
5749 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5750 /* Note: Rc update flag set leads to undefined state of Rc0 */
5751 #endif
5752 }
5753
5754 /* mtdcrx */
5755 /* XXX: not implemented on 440 ? */
5756 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5757 {
5758 #if defined(CONFIG_USER_ONLY)
5759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5760 #else
5761 if (unlikely(!ctx->mem_idx)) {
5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5763 return;
5764 }
5765 /* NIP cannot be restored if the memory exception comes from an helper */
5766 gen_update_nip(ctx, ctx->nip - 4);
5767 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5768 /* Note: Rc update flag set leads to undefined state of Rc0 */
5769 #endif
5770 }
5771
5772 /* mfdcrux (PPC 460) : user-mode access to DCR */
5773 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5774 {
5775 /* NIP cannot be restored if the memory exception comes from an helper */
5776 gen_update_nip(ctx, ctx->nip - 4);
5777 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5778 /* Note: Rc update flag set leads to undefined state of Rc0 */
5779 }
5780
5781 /* mtdcrux (PPC 460) : user-mode access to DCR */
5782 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5783 {
5784 /* NIP cannot be restored if the memory exception comes from an helper */
5785 gen_update_nip(ctx, ctx->nip - 4);
5786 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5787 /* Note: Rc update flag set leads to undefined state of Rc0 */
5788 }
5789
5790 /* dccci */
5791 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5792 {
5793 #if defined(CONFIG_USER_ONLY)
5794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5795 #else
5796 if (unlikely(!ctx->mem_idx)) {
5797 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5798 return;
5799 }
5800 /* interpreted as no-op */
5801 #endif
5802 }
5803
5804 /* dcread */
5805 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5806 {
5807 #if defined(CONFIG_USER_ONLY)
5808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5809 #else
5810 TCGv EA, val;
5811 if (unlikely(!ctx->mem_idx)) {
5812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5813 return;
5814 }
5815 gen_set_access_type(ctx, ACCESS_CACHE);
5816 EA = tcg_temp_new();
5817 gen_addr_reg_index(ctx, EA);
5818 val = tcg_temp_new();
5819 gen_qemu_ld32u(ctx, val, EA);
5820 tcg_temp_free(val);
5821 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5822 tcg_temp_free(EA);
5823 #endif
5824 }
5825
5826 /* icbt */
5827 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5828 {
5829 /* interpreted as no-op */
5830 /* XXX: specification say this is treated as a load by the MMU
5831 * but does not generate any exception
5832 */
5833 }
5834
5835 /* iccci */
5836 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5837 {
5838 #if defined(CONFIG_USER_ONLY)
5839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5840 #else
5841 if (unlikely(!ctx->mem_idx)) {
5842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5843 return;
5844 }
5845 /* interpreted as no-op */
5846 #endif
5847 }
5848
5849 /* icread */
5850 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5851 {
5852 #if defined(CONFIG_USER_ONLY)
5853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5854 #else
5855 if (unlikely(!ctx->mem_idx)) {
5856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5857 return;
5858 }
5859 /* interpreted as no-op */
5860 #endif
5861 }
5862
5863 /* rfci (mem_idx only) */
5864 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5865 {
5866 #if defined(CONFIG_USER_ONLY)
5867 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5868 #else
5869 if (unlikely(!ctx->mem_idx)) {
5870 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5871 return;
5872 }
5873 /* Restore CPU state */
5874 gen_helper_40x_rfci();
5875 gen_sync_exception(ctx);
5876 #endif
5877 }
5878
5879 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5880 {
5881 #if defined(CONFIG_USER_ONLY)
5882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5883 #else
5884 if (unlikely(!ctx->mem_idx)) {
5885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5886 return;
5887 }
5888 /* Restore CPU state */
5889 gen_helper_rfci();
5890 gen_sync_exception(ctx);
5891 #endif
5892 }
5893
5894 /* BookE specific */
5895 /* XXX: not implemented on 440 ? */
5896 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5897 {
5898 #if defined(CONFIG_USER_ONLY)
5899 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5900 #else
5901 if (unlikely(!ctx->mem_idx)) {
5902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5903 return;
5904 }
5905 /* Restore CPU state */
5906 gen_helper_rfdi();
5907 gen_sync_exception(ctx);
5908 #endif
5909 }
5910
5911 /* XXX: not implemented on 440 ? */
5912 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5913 {
5914 #if defined(CONFIG_USER_ONLY)
5915 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5916 #else
5917 if (unlikely(!ctx->mem_idx)) {
5918 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5919 return;
5920 }
5921 /* Restore CPU state */
5922 gen_helper_rfmci();
5923 gen_sync_exception(ctx);
5924 #endif
5925 }
5926
5927 /* TLB management - PowerPC 405 implementation */
5928 /* tlbre */
5929 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5930 {
5931 #if defined(CONFIG_USER_ONLY)
5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5933 #else
5934 if (unlikely(!ctx->mem_idx)) {
5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5936 return;
5937 }
5938 switch (rB(ctx->opcode)) {
5939 case 0:
5940 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5941 break;
5942 case 1:
5943 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5944 break;
5945 default:
5946 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5947 break;
5948 }
5949 #endif
5950 }
5951
5952 /* tlbsx - tlbsx. */
5953 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5954 {
5955 #if defined(CONFIG_USER_ONLY)
5956 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5957 #else
5958 TCGv t0;
5959 if (unlikely(!ctx->mem_idx)) {
5960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5961 return;
5962 }
5963 t0 = tcg_temp_new();
5964 gen_addr_reg_index(ctx, t0);
5965 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5966 tcg_temp_free(t0);
5967 if (Rc(ctx->opcode)) {
5968 int l1 = gen_new_label();
5969 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5970 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5971 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5972 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5973 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5974 gen_set_label(l1);
5975 }
5976 #endif
5977 }
5978
5979 /* tlbwe */
5980 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5981 {
5982 #if defined(CONFIG_USER_ONLY)
5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5984 #else
5985 if (unlikely(!ctx->mem_idx)) {
5986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5987 return;
5988 }
5989 switch (rB(ctx->opcode)) {
5990 case 0:
5991 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5992 break;
5993 case 1:
5994 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5995 break;
5996 default:
5997 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5998 break;
5999 }
6000 #endif
6001 }
6002
6003 /* TLB management - PowerPC 440 implementation */
6004 /* tlbre */
6005 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
6006 {
6007 #if defined(CONFIG_USER_ONLY)
6008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6009 #else
6010 if (unlikely(!ctx->mem_idx)) {
6011 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6012 return;
6013 }
6014 switch (rB(ctx->opcode)) {
6015 case 0:
6016 case 1:
6017 case 2:
6018 {
6019 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6020 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6021 tcg_temp_free_i32(t0);
6022 }
6023 break;
6024 default:
6025 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6026 break;
6027 }
6028 #endif
6029 }
6030
6031 /* tlbsx - tlbsx. */
6032 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
6033 {
6034 #if defined(CONFIG_USER_ONLY)
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036 #else
6037 TCGv t0;
6038 if (unlikely(!ctx->mem_idx)) {
6039 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6040 return;
6041 }
6042 t0 = tcg_temp_new();
6043 gen_addr_reg_index(ctx, t0);
6044 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6045 tcg_temp_free(t0);
6046 if (Rc(ctx->opcode)) {
6047 int l1 = gen_new_label();
6048 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6049 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6050 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6051 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6052 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6053 gen_set_label(l1);
6054 }
6055 #endif
6056 }
6057
6058 /* tlbwe */
6059 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
6060 {
6061 #if defined(CONFIG_USER_ONLY)
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6063 #else
6064 if (unlikely(!ctx->mem_idx)) {
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6066 return;
6067 }
6068 switch (rB(ctx->opcode)) {
6069 case 0:
6070 case 1:
6071 case 2:
6072 {
6073 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6074 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6075 tcg_temp_free_i32(t0);
6076 }
6077 break;
6078 default:
6079 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6080 break;
6081 }
6082 #endif
6083 }
6084
6085 /* wrtee */
6086 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6087 {
6088 #if defined(CONFIG_USER_ONLY)
6089 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6090 #else
6091 TCGv t0;
6092 if (unlikely(!ctx->mem_idx)) {
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6094 return;
6095 }
6096 t0 = tcg_temp_new();
6097 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6098 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6099 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6100 tcg_temp_free(t0);
6101 /* Stop translation to have a chance to raise an exception
6102 * if we just set msr_ee to 1
6103 */
6104 gen_stop_exception(ctx);
6105 #endif
6106 }
6107
6108 /* wrteei */
6109 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6110 {
6111 #if defined(CONFIG_USER_ONLY)
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6113 #else
6114 if (unlikely(!ctx->mem_idx)) {
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6116 return;
6117 }
6118 if (ctx->opcode & 0x00010000) {
6119 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6120 /* Stop translation to have a chance to raise an exception */
6121 gen_stop_exception(ctx);
6122 } else {
6123 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6124 }
6125 #endif
6126 }
6127
6128 /* PowerPC 440 specific instructions */
6129 /* dlmzb */
6130 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6131 {
6132 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6133 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6134 cpu_gpr[rB(ctx->opcode)], t0);
6135 tcg_temp_free_i32(t0);
6136 }
6137
6138 /* mbar replaces eieio on 440 */
6139 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6140 {
6141 /* interpreted as no-op */
6142 }
6143
6144 /* msync replaces sync on 440 */
6145 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6146 {
6147 /* interpreted as no-op */
6148 }
6149
6150 /* icbt */
6151 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6152 {
6153 /* interpreted as no-op */
6154 /* XXX: specification say this is treated as a load by the MMU
6155 * but does not generate any exception
6156 */
6157 }
6158
6159 /*** Altivec vector extension ***/
6160 /* Altivec registers moves */
6161
6162 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6163 {
6164 TCGv_ptr r = tcg_temp_new_ptr();
6165 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6166 return r;
6167 }
6168
6169 #define GEN_VR_LDX(name, opc2, opc3) \
6170 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6171 { \
6172 TCGv EA; \
6173 if (unlikely(!ctx->altivec_enabled)) { \
6174 gen_exception(ctx, POWERPC_EXCP_VPU); \
6175 return; \
6176 } \
6177 gen_set_access_type(ctx, ACCESS_INT); \
6178 EA = tcg_temp_new(); \
6179 gen_addr_reg_index(ctx, EA); \
6180 tcg_gen_andi_tl(EA, EA, ~0xf); \
6181 if (ctx->le_mode) { \
6182 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6183 tcg_gen_addi_tl(EA, EA, 8); \
6184 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6185 } else { \
6186 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6187 tcg_gen_addi_tl(EA, EA, 8); \
6188 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6189 } \
6190 tcg_temp_free(EA); \
6191 }
6192
6193 #define GEN_VR_STX(name, opc2, opc3) \
6194 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6195 { \
6196 TCGv EA; \
6197 if (unlikely(!ctx->altivec_enabled)) { \
6198 gen_exception(ctx, POWERPC_EXCP_VPU); \
6199 return; \
6200 } \
6201 gen_set_access_type(ctx, ACCESS_INT); \
6202 EA = tcg_temp_new(); \
6203 gen_addr_reg_index(ctx, EA); \
6204 tcg_gen_andi_tl(EA, EA, ~0xf); \
6205 if (ctx->le_mode) { \
6206 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6207 tcg_gen_addi_tl(EA, EA, 8); \
6208 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6209 } else { \
6210 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6211 tcg_gen_addi_tl(EA, EA, 8); \
6212 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6213 } \
6214 tcg_temp_free(EA); \
6215 }
6216
6217 #define GEN_VR_LVE(name, opc2, opc3) \
6218 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6219 { \
6220 TCGv EA; \
6221 TCGv_ptr rs; \
6222 if (unlikely(!ctx->altivec_enabled)) { \
6223 gen_exception(ctx, POWERPC_EXCP_VPU); \
6224 return; \
6225 } \
6226 gen_set_access_type(ctx, ACCESS_INT); \
6227 EA = tcg_temp_new(); \
6228 gen_addr_reg_index(ctx, EA); \
6229 rs = gen_avr_ptr(rS(ctx->opcode)); \
6230 gen_helper_lve##name (rs, EA); \
6231 tcg_temp_free(EA); \
6232 tcg_temp_free_ptr(rs); \
6233 }
6234
6235 #define GEN_VR_STVE(name, opc2, opc3) \
6236 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6237 { \
6238 TCGv EA; \
6239 TCGv_ptr rs; \
6240 if (unlikely(!ctx->altivec_enabled)) { \
6241 gen_exception(ctx, POWERPC_EXCP_VPU); \
6242 return; \
6243 } \
6244 gen_set_access_type(ctx, ACCESS_INT); \
6245 EA = tcg_temp_new(); \
6246 gen_addr_reg_index(ctx, EA); \
6247 rs = gen_avr_ptr(rS(ctx->opcode)); \
6248 gen_helper_stve##name (rs, EA); \
6249 tcg_temp_free(EA); \
6250 tcg_temp_free_ptr(rs); \
6251 }
6252
6253 GEN_VR_LDX(lvx, 0x07, 0x03);
6254 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6255 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6256
6257 GEN_VR_LVE(bx, 0x07, 0x00);
6258 GEN_VR_LVE(hx, 0x07, 0x01);
6259 GEN_VR_LVE(wx, 0x07, 0x02);
6260
6261 GEN_VR_STX(svx, 0x07, 0x07);
6262 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6263 GEN_VR_STX(svxl, 0x07, 0x0F);
6264
6265 GEN_VR_STVE(bx, 0x07, 0x04);
6266 GEN_VR_STVE(hx, 0x07, 0x05);
6267 GEN_VR_STVE(wx, 0x07, 0x06);
6268
6269 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6270 {
6271 TCGv_ptr rd;
6272 TCGv EA;
6273 if (unlikely(!ctx->altivec_enabled)) {
6274 gen_exception(ctx, POWERPC_EXCP_VPU);
6275 return;
6276 }
6277 EA = tcg_temp_new();
6278 gen_addr_reg_index(ctx, EA);
6279 rd = gen_avr_ptr(rD(ctx->opcode));
6280 gen_helper_lvsl(rd, EA);
6281 tcg_temp_free(EA);
6282 tcg_temp_free_ptr(rd);
6283 }
6284
6285 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6286 {
6287 TCGv_ptr rd;
6288 TCGv EA;
6289 if (unlikely(!ctx->altivec_enabled)) {
6290 gen_exception(ctx, POWERPC_EXCP_VPU);
6291 return;
6292 }
6293 EA = tcg_temp_new();
6294 gen_addr_reg_index(ctx, EA);
6295 rd = gen_avr_ptr(rD(ctx->opcode));
6296 gen_helper_lvsr(rd, EA);
6297 tcg_temp_free(EA);
6298 tcg_temp_free_ptr(rd);
6299 }
6300
6301 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6302 {
6303 TCGv_i32 t;
6304 if (unlikely(!ctx->altivec_enabled)) {
6305 gen_exception(ctx, POWERPC_EXCP_VPU);
6306 return;
6307 }
6308 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6309 t = tcg_temp_new_i32();
6310 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6311 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6312 tcg_temp_free_i32(t);
6313 }
6314
6315 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6316 {
6317 TCGv_ptr p;
6318 if (unlikely(!ctx->altivec_enabled)) {
6319 gen_exception(ctx, POWERPC_EXCP_VPU);
6320 return;
6321 }
6322 p = gen_avr_ptr(rD(ctx->opcode));
6323 gen_helper_mtvscr(p);
6324 tcg_temp_free_ptr(p);
6325 }
6326
6327 /* Logical operations */
6328 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6329 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6330 { \
6331 if (unlikely(!ctx->altivec_enabled)) { \
6332 gen_exception(ctx, POWERPC_EXCP_VPU); \
6333 return; \
6334 } \
6335 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6336 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6337 }
6338
6339 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6340 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6341 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6342 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6343 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6344
6345 #define GEN_VXFORM(name, opc2, opc3) \
6346 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6347 { \
6348 TCGv_ptr ra, rb, rd; \
6349 if (unlikely(!ctx->altivec_enabled)) { \
6350 gen_exception(ctx, POWERPC_EXCP_VPU); \
6351 return; \
6352 } \
6353 ra = gen_avr_ptr(rA(ctx->opcode)); \
6354 rb = gen_avr_ptr(rB(ctx->opcode)); \
6355 rd = gen_avr_ptr(rD(ctx->opcode)); \
6356 gen_helper_##name (rd, ra, rb); \
6357 tcg_temp_free_ptr(ra); \
6358 tcg_temp_free_ptr(rb); \
6359 tcg_temp_free_ptr(rd); \
6360 }
6361
6362 GEN_VXFORM(vaddubm, 0, 0);
6363 GEN_VXFORM(vadduhm, 0, 1);
6364 GEN_VXFORM(vadduwm, 0, 2);
6365 GEN_VXFORM(vsububm, 0, 16);
6366 GEN_VXFORM(vsubuhm, 0, 17);
6367 GEN_VXFORM(vsubuwm, 0, 18);
6368 GEN_VXFORM(vmaxub, 1, 0);
6369 GEN_VXFORM(vmaxuh, 1, 1);
6370 GEN_VXFORM(vmaxuw, 1, 2);
6371 GEN_VXFORM(vmaxsb, 1, 4);
6372 GEN_VXFORM(vmaxsh, 1, 5);
6373 GEN_VXFORM(vmaxsw, 1, 6);
6374 GEN_VXFORM(vminub, 1, 8);
6375 GEN_VXFORM(vminuh, 1, 9);
6376 GEN_VXFORM(vminuw, 1, 10);
6377 GEN_VXFORM(vminsb, 1, 12);
6378 GEN_VXFORM(vminsh, 1, 13);
6379 GEN_VXFORM(vminsw, 1, 14);
6380 GEN_VXFORM(vavgub, 1, 16);
6381 GEN_VXFORM(vavguh, 1, 17);
6382 GEN_VXFORM(vavguw, 1, 18);
6383 GEN_VXFORM(vavgsb, 1, 20);
6384 GEN_VXFORM(vavgsh, 1, 21);
6385 GEN_VXFORM(vavgsw, 1, 22);
6386 GEN_VXFORM(vmrghb, 6, 0);
6387 GEN_VXFORM(vmrghh, 6, 1);
6388 GEN_VXFORM(vmrghw, 6, 2);
6389 GEN_VXFORM(vmrglb, 6, 4);
6390 GEN_VXFORM(vmrglh, 6, 5);
6391 GEN_VXFORM(vmrglw, 6, 6);
6392 GEN_VXFORM(vmuloub, 4, 0);
6393 GEN_VXFORM(vmulouh, 4, 1);
6394 GEN_VXFORM(vmulosb, 4, 4);
6395 GEN_VXFORM(vmulosh, 4, 5);
6396 GEN_VXFORM(vmuleub, 4, 8);
6397 GEN_VXFORM(vmuleuh, 4, 9);
6398 GEN_VXFORM(vmulesb, 4, 12);
6399 GEN_VXFORM(vmulesh, 4, 13);
6400 GEN_VXFORM(vslb, 2, 4);
6401 GEN_VXFORM(vslh, 2, 5);
6402 GEN_VXFORM(vslw, 2, 6);
6403 GEN_VXFORM(vsrb, 2, 8);
6404 GEN_VXFORM(vsrh, 2, 9);
6405 GEN_VXFORM(vsrw, 2, 10);
6406 GEN_VXFORM(vsrab, 2, 12);
6407 GEN_VXFORM(vsrah, 2, 13);
6408 GEN_VXFORM(vsraw, 2, 14);
6409 GEN_VXFORM(vslo, 6, 16);
6410 GEN_VXFORM(vsro, 6, 17);
6411 GEN_VXFORM(vaddcuw, 0, 6);
6412 GEN_VXFORM(vsubcuw, 0, 22);
6413 GEN_VXFORM(vaddubs, 0, 8);
6414 GEN_VXFORM(vadduhs, 0, 9);
6415 GEN_VXFORM(vadduws, 0, 10);
6416 GEN_VXFORM(vaddsbs, 0, 12);
6417 GEN_VXFORM(vaddshs, 0, 13);
6418 GEN_VXFORM(vaddsws, 0, 14);
6419 GEN_VXFORM(vsububs, 0, 24);
6420 GEN_VXFORM(vsubuhs, 0, 25);
6421 GEN_VXFORM(vsubuws, 0, 26);
6422 GEN_VXFORM(vsubsbs, 0, 28);
6423 GEN_VXFORM(vsubshs, 0, 29);
6424 GEN_VXFORM(vsubsws, 0, 30);
6425 GEN_VXFORM(vrlb, 2, 0);
6426 GEN_VXFORM(vrlh, 2, 1);
6427 GEN_VXFORM(vrlw, 2, 2);
6428 GEN_VXFORM(vsl, 2, 7);
6429 GEN_VXFORM(vsr, 2, 11);
6430 GEN_VXFORM(vpkuhum, 7, 0);
6431 GEN_VXFORM(vpkuwum, 7, 1);
6432 GEN_VXFORM(vpkuhus, 7, 2);
6433 GEN_VXFORM(vpkuwus, 7, 3);
6434 GEN_VXFORM(vpkshus, 7, 4);
6435 GEN_VXFORM(vpkswus, 7, 5);
6436 GEN_VXFORM(vpkshss, 7, 6);
6437 GEN_VXFORM(vpkswss, 7, 7);
6438 GEN_VXFORM(vpkpx, 7, 12);
6439 GEN_VXFORM(vsum4ubs, 4, 24);
6440 GEN_VXFORM(vsum4sbs, 4, 28);
6441 GEN_VXFORM(vsum4shs, 4, 25);
6442 GEN_VXFORM(vsum2sws, 4, 26);
6443 GEN_VXFORM(vsumsws, 4, 30);
6444 GEN_VXFORM(vaddfp, 5, 0);
6445 GEN_VXFORM(vsubfp, 5, 1);
6446 GEN_VXFORM(vmaxfp, 5, 16);
6447 GEN_VXFORM(vminfp, 5, 17);
6448
6449 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6450 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6451 { \
6452 TCGv_ptr ra, rb, rd; \
6453 if (unlikely(!ctx->altivec_enabled)) { \
6454 gen_exception(ctx, POWERPC_EXCP_VPU); \
6455 return; \
6456 } \
6457 ra = gen_avr_ptr(rA(ctx->opcode)); \
6458 rb = gen_avr_ptr(rB(ctx->opcode)); \
6459 rd = gen_avr_ptr(rD(ctx->opcode)); \
6460 gen_helper_##opname (rd, ra, rb); \
6461 tcg_temp_free_ptr(ra); \
6462 tcg_temp_free_ptr(rb); \
6463 tcg_temp_free_ptr(rd); \
6464 }
6465
6466 #define GEN_VXRFORM(name, opc2, opc3) \
6467 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6468 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6469
6470 GEN_VXRFORM(vcmpequb, 3, 0)
6471 GEN_VXRFORM(vcmpequh, 3, 1)
6472 GEN_VXRFORM(vcmpequw, 3, 2)
6473 GEN_VXRFORM(vcmpgtsb, 3, 12)
6474 GEN_VXRFORM(vcmpgtsh, 3, 13)
6475 GEN_VXRFORM(vcmpgtsw, 3, 14)
6476 GEN_VXRFORM(vcmpgtub, 3, 8)
6477 GEN_VXRFORM(vcmpgtuh, 3, 9)
6478 GEN_VXRFORM(vcmpgtuw, 3, 10)
6479 GEN_VXRFORM(vcmpeqfp, 3, 3)
6480 GEN_VXRFORM(vcmpgefp, 3, 7)
6481 GEN_VXRFORM(vcmpgtfp, 3, 11)
6482 GEN_VXRFORM(vcmpbfp, 3, 15)
6483
6484 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6485 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6486 { \
6487 TCGv_ptr rd; \
6488 TCGv_i32 simm; \
6489 if (unlikely(!ctx->altivec_enabled)) { \
6490 gen_exception(ctx, POWERPC_EXCP_VPU); \
6491 return; \
6492 } \
6493 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6494 rd = gen_avr_ptr(rD(ctx->opcode)); \
6495 gen_helper_##name (rd, simm); \
6496 tcg_temp_free_i32(simm); \
6497 tcg_temp_free_ptr(rd); \
6498 }
6499
6500 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6501 GEN_VXFORM_SIMM(vspltish, 6, 13);
6502 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6503
6504 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6505 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6506 { \
6507 TCGv_ptr rb, rd; \
6508 if (unlikely(!ctx->altivec_enabled)) { \
6509 gen_exception(ctx, POWERPC_EXCP_VPU); \
6510 return; \
6511 } \
6512 rb = gen_avr_ptr(rB(ctx->opcode)); \
6513 rd = gen_avr_ptr(rD(ctx->opcode)); \
6514 gen_helper_##name (rd, rb); \
6515 tcg_temp_free_ptr(rb); \
6516 tcg_temp_free_ptr(rd); \
6517 }
6518
6519 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6520 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6521 GEN_VXFORM_NOA(vupklsb, 7, 10);
6522 GEN_VXFORM_NOA(vupklsh, 7, 11);
6523 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6524 GEN_VXFORM_NOA(vupklpx, 7, 15);
6525 GEN_VXFORM_NOA(vrefp, 5, 4);
6526 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6527 GEN_VXFORM_NOA(vlogefp, 5, 7);
6528 GEN_VXFORM_NOA(vrfim, 5, 8);
6529 GEN_VXFORM_NOA(vrfin, 5, 9);
6530 GEN_VXFORM_NOA(vrfip, 5, 10);
6531 GEN_VXFORM_NOA(vrfiz, 5, 11);
6532
6533 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6534 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6535 { \
6536 TCGv_ptr rd; \
6537 TCGv_i32 simm; \
6538 if (unlikely(!ctx->altivec_enabled)) { \
6539 gen_exception(ctx, POWERPC_EXCP_VPU); \
6540 return; \
6541 } \
6542 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6543 rd = gen_avr_ptr(rD(ctx->opcode)); \
6544 gen_helper_##name (rd, simm); \
6545 tcg_temp_free_i32(simm); \
6546 tcg_temp_free_ptr(rd); \
6547 }
6548
6549 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6550 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6551 { \
6552 TCGv_ptr rb, rd; \
6553 TCGv_i32 uimm; \
6554 if (unlikely(!ctx->altivec_enabled)) { \
6555 gen_exception(ctx, POWERPC_EXCP_VPU); \
6556 return; \
6557 } \
6558 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6559 rb = gen_avr_ptr(rB(ctx->opcode)); \
6560 rd = gen_avr_ptr(rD(ctx->opcode)); \
6561 gen_helper_##name (rd, rb, uimm); \
6562 tcg_temp_free_i32(uimm); \
6563 tcg_temp_free_ptr(rb); \
6564 tcg_temp_free_ptr(rd); \
6565 }
6566
6567 GEN_VXFORM_UIMM(vspltb, 6, 8);
6568 GEN_VXFORM_UIMM(vsplth, 6, 9);
6569 GEN_VXFORM_UIMM(vspltw, 6, 10);
6570 GEN_VXFORM_UIMM(vcfux, 5, 12);
6571 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6572 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6573 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6574
6575 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6576 {
6577 TCGv_ptr ra, rb, rd;
6578 TCGv_i32 sh;
6579 if (unlikely(!ctx->altivec_enabled)) {
6580 gen_exception(ctx, POWERPC_EXCP_VPU);
6581 return;
6582 }
6583 ra = gen_avr_ptr(rA(ctx->opcode));
6584 rb = gen_avr_ptr(rB(ctx->opcode));
6585 rd = gen_avr_ptr(rD(ctx->opcode));
6586 sh = tcg_const_i32(VSH(ctx->opcode));
6587 gen_helper_vsldoi (rd, ra, rb, sh);
6588 tcg_temp_free_ptr(ra);
6589 tcg_temp_free_ptr(rb);
6590 tcg_temp_free_ptr(rd);
6591 tcg_temp_free_i32(sh);
6592 }
6593
6594 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6595 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6596 { \
6597 TCGv_ptr ra, rb, rc, rd; \
6598 if (unlikely(!ctx->altivec_enabled)) { \
6599 gen_exception(ctx, POWERPC_EXCP_VPU); \
6600 return; \
6601 } \
6602 ra = gen_avr_ptr(rA(ctx->opcode)); \
6603 rb = gen_avr_ptr(rB(ctx->opcode)); \
6604 rc = gen_avr_ptr(rC(ctx->opcode)); \
6605 rd = gen_avr_ptr(rD(ctx->opcode)); \
6606 if (Rc(ctx->opcode)) { \
6607 gen_helper_##name1 (rd, ra, rb, rc); \
6608 } else { \
6609 gen_helper_##name0 (rd, ra, rb, rc); \
6610 } \
6611 tcg_temp_free_ptr(ra); \
6612 tcg_temp_free_ptr(rb); \
6613 tcg_temp_free_ptr(rc); \
6614 tcg_temp_free_ptr(rd); \
6615 }
6616
6617 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6618
6619 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6620 {
6621 TCGv_ptr ra, rb, rc, rd;
6622 if (unlikely(!ctx->altivec_enabled)) {
6623 gen_exception(ctx, POWERPC_EXCP_VPU);
6624 return;
6625 }
6626 ra = gen_avr_ptr(rA(ctx->opcode));
6627 rb = gen_avr_ptr(rB(ctx->opcode));
6628 rc = gen_avr_ptr(rC(ctx->opcode));
6629 rd = gen_avr_ptr(rD(ctx->opcode));
6630 gen_helper_vmladduhm(rd, ra, rb, rc);
6631 tcg_temp_free_ptr(ra);
6632 tcg_temp_free_ptr(rb);
6633 tcg_temp_free_ptr(rc);
6634 tcg_temp_free_ptr(rd);
6635 }
6636
6637 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6638 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6639 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6640 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6641 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6642
6643 /*** SPE extension ***/
6644 /* Register moves */
6645
6646 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6647 #if defined(TARGET_PPC64)
6648 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6649 #else
6650 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6651 #endif
6652 }
6653
6654 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6655 #if defined(TARGET_PPC64)
6656 tcg_gen_mov_i64(cpu_gpr[reg], t);
6657 #else
6658 TCGv_i64 tmp = tcg_temp_new_i64();
6659 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6660 tcg_gen_shri_i64(tmp, t, 32);
6661 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6662 tcg_temp_free_i64(tmp);
6663 #endif
6664 }
6665
6666 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6667 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6668 { \
6669 if (Rc(ctx->opcode)) \
6670 gen_##name1(ctx); \
6671 else \
6672 gen_##name0(ctx); \
6673 }
6674
6675 /* Handler for undefined SPE opcodes */
6676 static always_inline void gen_speundef (DisasContext *ctx)
6677 {
6678 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6679 }
6680
6681 /* SPE logic */
6682 #if defined(TARGET_PPC64)
6683 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6684 static always_inline void gen_##name (DisasContext *ctx) \
6685 { \
6686 if (unlikely(!ctx->spe_enabled)) { \
6687 gen_exception(ctx, POWERPC_EXCP_APU); \
6688 return; \
6689 } \
6690 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6691 cpu_gpr[rB(ctx->opcode)]); \
6692 }
6693 #else
6694 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6695 static always_inline void gen_##name (DisasContext *ctx) \
6696 { \
6697 if (unlikely(!ctx->spe_enabled)) { \
6698 gen_exception(ctx, POWERPC_EXCP_APU); \
6699 return; \
6700 } \
6701 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6702 cpu_gpr[rB(ctx->opcode)]); \
6703 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6704 cpu_gprh[rB(ctx->opcode)]); \
6705 }
6706 #endif
6707
6708 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6709 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6710 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6711 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6712 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6713 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6714 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6715 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6716
6717 /* SPE logic immediate */
6718 #if defined(TARGET_PPC64)
6719 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6720 static always_inline void gen_##name (DisasContext *ctx) \
6721 { \
6722 if (unlikely(!ctx->spe_enabled)) { \
6723 gen_exception(ctx, POWERPC_EXCP_APU); \
6724 return; \
6725 } \
6726 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6727 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6728 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6729 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6730 tcg_opi(t0, t0, rB(ctx->opcode)); \
6731 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6732 tcg_gen_trunc_i64_i32(t1, t2); \
6733 tcg_temp_free_i64(t2); \
6734 tcg_opi(t1, t1, rB(ctx->opcode)); \
6735 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6736 tcg_temp_free_i32(t0); \
6737 tcg_temp_free_i32(t1); \
6738 }
6739 #else
6740 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6741 static always_inline void gen_##name (DisasContext *ctx) \
6742 { \
6743 if (unlikely(!ctx->spe_enabled)) { \
6744 gen_exception(ctx, POWERPC_EXCP_APU); \
6745 return; \
6746 } \
6747 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6748 rB(ctx->opcode)); \
6749 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6750 rB(ctx->opcode)); \
6751 }
6752 #endif
6753 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6754 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6755 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6756 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6757
6758 /* SPE arithmetic */
6759 #if defined(TARGET_PPC64)
6760 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6761 static always_inline void gen_##name (DisasContext *ctx) \
6762 { \
6763 if (unlikely(!ctx->spe_enabled)) { \
6764 gen_exception(ctx, POWERPC_EXCP_APU); \
6765 return; \
6766 } \
6767 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6768 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6769 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6770 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6771 tcg_op(t0, t0); \
6772 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6773 tcg_gen_trunc_i64_i32(t1, t2); \
6774 tcg_temp_free_i64(t2); \
6775 tcg_op(t1, t1); \
6776 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6777 tcg_temp_free_i32(t0); \
6778 tcg_temp_free_i32(t1); \
6779 }
6780 #else
6781 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6782 static always_inline void gen_##name (DisasContext *ctx) \
6783 { \
6784 if (unlikely(!ctx->spe_enabled)) { \
6785 gen_exception(ctx, POWERPC_EXCP_APU); \
6786 return; \
6787 } \
6788 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6789 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6790 }
6791 #endif
6792
6793 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6794 {
6795 int l1 = gen_new_label();
6796 int l2 = gen_new_label();
6797
6798 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6799 tcg_gen_neg_i32(ret, arg1);
6800 tcg_gen_br(l2);
6801 gen_set_label(l1);
6802 tcg_gen_mov_i32(ret, arg1);
6803 gen_set_label(l2);
6804 }
6805 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6806 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6807 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6808 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6809 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6810 {
6811 tcg_gen_addi_i32(ret, arg1, 0x8000);
6812 tcg_gen_ext16u_i32(ret, ret);
6813 }
6814 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6815 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6816 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6817
6818 #if defined(TARGET_PPC64)
6819 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6820 static always_inline void gen_##name (DisasContext *ctx) \
6821 { \
6822 if (unlikely(!ctx->spe_enabled)) { \
6823 gen_exception(ctx, POWERPC_EXCP_APU); \
6824 return; \
6825 } \
6826 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6827 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6828 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6829 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6830 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6831 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6832 tcg_op(t0, t0, t2); \
6833 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6834 tcg_gen_trunc_i64_i32(t1, t3); \
6835 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6836 tcg_gen_trunc_i64_i32(t2, t3); \
6837 tcg_temp_free_i64(t3); \
6838 tcg_op(t1, t1, t2); \
6839 tcg_temp_free_i32(t2); \
6840 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6841 tcg_temp_free_i32(t0); \
6842 tcg_temp_free_i32(t1); \
6843 }
6844 #else
6845 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6846 static always_inline void gen_##name (DisasContext *ctx) \
6847 { \
6848 if (unlikely(!ctx->spe_enabled)) { \
6849 gen_exception(ctx, POWERPC_EXCP_APU); \
6850 return; \
6851 } \
6852 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6853 cpu_gpr[rB(ctx->opcode)]); \
6854 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6855 cpu_gprh[rB(ctx->opcode)]); \
6856 }
6857 #endif
6858
6859 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6860 {
6861 TCGv_i32 t0;
6862 int l1, l2;
6863
6864 l1 = gen_new_label();
6865 l2 = gen_new_label();
6866 t0 = tcg_temp_local_new_i32();
6867 /* No error here: 6 bits are used */
6868 tcg_gen_andi_i32(t0, arg2, 0x3F);
6869 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6870 tcg_gen_shr_i32(ret, arg1, t0);
6871 tcg_gen_br(l2);
6872 gen_set_label(l1);
6873 tcg_gen_movi_i32(ret, 0);
6874 tcg_gen_br(l2);
6875 tcg_temp_free_i32(t0);
6876 }
6877 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6878 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6879 {
6880 TCGv_i32 t0;
6881 int l1, l2;
6882
6883 l1 = gen_new_label();
6884 l2 = gen_new_label();
6885 t0 = tcg_temp_local_new_i32();
6886 /* No error here: 6 bits are used */
6887 tcg_gen_andi_i32(t0, arg2, 0x3F);
6888 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6889 tcg_gen_sar_i32(ret, arg1, t0);
6890 tcg_gen_br(l2);
6891 gen_set_label(l1);
6892 tcg_gen_movi_i32(ret, 0);
6893 tcg_gen_br(l2);
6894 tcg_temp_free_i32(t0);
6895 }
6896 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6897 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6898 {
6899 TCGv_i32 t0;
6900 int l1, l2;
6901
6902 l1 = gen_new_label();
6903 l2 = gen_new_label();
6904 t0 = tcg_temp_local_new_i32();
6905 /* No error here: 6 bits are used */
6906 tcg_gen_andi_i32(t0, arg2, 0x3F);
6907 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6908 tcg_gen_shl_i32(ret, arg1, t0);
6909 tcg_gen_br(l2);
6910 gen_set_label(l1);
6911 tcg_gen_movi_i32(ret, 0);
6912 tcg_gen_br(l2);
6913 tcg_temp_free_i32(t0);
6914 }
6915 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6916 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6917 {
6918 TCGv_i32 t0 = tcg_temp_new_i32();
6919 tcg_gen_andi_i32(t0, arg2, 0x1F);
6920 tcg_gen_rotl_i32(ret, arg1, t0);
6921 tcg_temp_free_i32(t0);
6922 }
6923 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6924 static always_inline void gen_evmergehi (DisasContext *ctx)
6925 {
6926 if (unlikely(!ctx->spe_enabled)) {
6927 gen_exception(ctx, POWERPC_EXCP_APU);
6928 return;
6929 }
6930 #if defined(TARGET_PPC64)
6931 TCGv t0 = tcg_temp_new();
6932 TCGv t1 = tcg_temp_new();
6933 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6934 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6935 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6936 tcg_temp_free(t0);
6937 tcg_temp_free(t1);
6938 #else
6939 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6940 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6941 #endif
6942 }
6943 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6944 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6945 {
6946 tcg_gen_sub_i32(ret, arg2, arg1);
6947 }
6948 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6949
6950 /* SPE arithmetic immediate */
6951 #if defined(TARGET_PPC64)
6952 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6953 static always_inline void gen_##name (DisasContext *ctx) \
6954 { \
6955 if (unlikely(!ctx->spe_enabled)) { \
6956 gen_exception(ctx, POWERPC_EXCP_APU); \
6957 return; \
6958 } \
6959 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6960 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6961 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6962 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6963 tcg_op(t0, t0, rA(ctx->opcode)); \
6964 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6965 tcg_gen_trunc_i64_i32(t1, t2); \
6966 tcg_temp_free_i64(t2); \
6967 tcg_op(t1, t1, rA(ctx->opcode)); \
6968 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6969 tcg_temp_free_i32(t0); \
6970 tcg_temp_free_i32(t1); \
6971 }
6972 #else
6973 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6974 static always_inline void gen_##name (DisasContext *ctx) \
6975 { \
6976 if (unlikely(!ctx->spe_enabled)) { \
6977 gen_exception(ctx, POWERPC_EXCP_APU); \
6978 return; \
6979 } \
6980 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6981 rA(ctx->opcode)); \
6982 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6983 rA(ctx->opcode)); \
6984 }
6985 #endif
6986 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6987 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6988
6989 /* SPE comparison */
6990 #if defined(TARGET_PPC64)
6991 #define GEN_SPEOP_COMP(name, tcg_cond) \
6992 static always_inline void gen_##name (DisasContext *ctx) \
6993 { \
6994 if (unlikely(!ctx->spe_enabled)) { \
6995 gen_exception(ctx, POWERPC_EXCP_APU); \
6996 return; \
6997 } \
6998 int l1 = gen_new_label(); \
6999 int l2 = gen_new_label(); \
7000 int l3 = gen_new_label(); \
7001 int l4 = gen_new_label(); \
7002 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7003 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7004 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7005 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7006 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7007 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7008 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7009 tcg_gen_br(l2); \
7010 gen_set_label(l1); \
7011 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7012 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7013 gen_set_label(l2); \
7014 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7015 tcg_gen_trunc_i64_i32(t0, t2); \
7016 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7017 tcg_gen_trunc_i64_i32(t1, t2); \
7018 tcg_temp_free_i64(t2); \
7019 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7020 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7021 ~(CRF_CH | CRF_CH_AND_CL)); \
7022 tcg_gen_br(l4); \
7023 gen_set_label(l3); \
7024 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7025 CRF_CH | CRF_CH_OR_CL); \
7026 gen_set_label(l4); \
7027 tcg_temp_free_i32(t0); \
7028 tcg_temp_free_i32(t1); \
7029 }
7030 #else
7031 #define GEN_SPEOP_COMP(name, tcg_cond) \
7032 static always_inline void gen_##name (DisasContext *ctx) \
7033 { \
7034 if (unlikely(!ctx->spe_enabled)) { \
7035 gen_exception(ctx, POWERPC_EXCP_APU); \
7036 return; \
7037 } \
7038 int l1 = gen_new_label(); \
7039 int l2 = gen_new_label(); \
7040 int l3 = gen_new_label(); \
7041 int l4 = gen_new_label(); \
7042 \
7043 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7044 cpu_gpr[rB(ctx->opcode)], l1); \
7045 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7046 tcg_gen_br(l2); \
7047 gen_set_label(l1); \
7048 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7049 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7050 gen_set_label(l2); \
7051 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7052 cpu_gprh[rB(ctx->opcode)], l3); \
7053 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7054 ~(CRF_CH | CRF_CH_AND_CL)); \
7055 tcg_gen_br(l4); \
7056 gen_set_label(l3); \
7057 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7058 CRF_CH | CRF_CH_OR_CL); \
7059 gen_set_label(l4); \
7060 }
7061 #endif
7062 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7063 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7064 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7065 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7066 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7067
7068 /* SPE misc */
7069 static always_inline void gen_brinc (DisasContext *ctx)
7070 {
7071 /* Note: brinc is usable even if SPE is disabled */
7072 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7073 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7074 }
7075 static always_inline void gen_evmergelo (DisasContext *ctx)
7076 {
7077 if (unlikely(!ctx->spe_enabled)) {
7078 gen_exception(ctx, POWERPC_EXCP_APU);
7079 return;
7080 }
7081 #if defined(TARGET_PPC64)
7082 TCGv t0 = tcg_temp_new();
7083 TCGv t1 = tcg_temp_new();
7084 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7085 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7086 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7087 tcg_temp_free(t0);
7088 tcg_temp_free(t1);
7089 #else
7090 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7091 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7092 #endif
7093 }
7094 static always_inline void gen_evmergehilo (DisasContext *ctx)
7095 {
7096 if (unlikely(!ctx->spe_enabled)) {
7097 gen_exception(ctx, POWERPC_EXCP_APU);
7098 return;
7099 }
7100 #if defined(TARGET_PPC64)
7101 TCGv t0 = tcg_temp_new();
7102 TCGv t1 = tcg_temp_new();
7103 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7104 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7105 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7106 tcg_temp_free(t0);
7107 tcg_temp_free(t1);
7108 #else
7109 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7110 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7111 #endif
7112 }
7113 static always_inline void gen_evmergelohi (DisasContext *ctx)
7114 {
7115 if (unlikely(!ctx->spe_enabled)) {
7116 gen_exception(ctx, POWERPC_EXCP_APU);
7117 return;
7118 }
7119 #if defined(TARGET_PPC64)
7120 TCGv t0 = tcg_temp_new();
7121 TCGv t1 = tcg_temp_new();
7122 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7123 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7124 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7125 tcg_temp_free(t0);
7126 tcg_temp_free(t1);
7127 #else
7128 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7129 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7130 #endif
7131 }
7132 static always_inline void gen_evsplati (DisasContext *ctx)
7133 {
7134 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7135
7136 #if defined(TARGET_PPC64)
7137 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7138 #else
7139 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7140 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7141 #endif
7142 }
7143 static always_inline void gen_evsplatfi (DisasContext *ctx)
7144 {
7145 uint64_t imm = rA(ctx->opcode) << 11;
7146
7147 #if defined(TARGET_PPC64)
7148 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7149 #else
7150 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7151 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7152 #endif
7153 }
7154
7155 static always_inline void gen_evsel (DisasContext *ctx)
7156 {
7157 int l1 = gen_new_label();
7158 int l2 = gen_new_label();
7159 int l3 = gen_new_label();
7160 int l4 = gen_new_label();
7161 TCGv_i32 t0 = tcg_temp_local_new_i32();
7162 #if defined(TARGET_PPC64)
7163 TCGv t1 = tcg_temp_local_new();
7164 TCGv t2 = tcg_temp_local_new();
7165 #endif
7166 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7167 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7168 #if defined(TARGET_PPC64)
7169 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7170 #else
7171 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7172 #endif
7173 tcg_gen_br(l2);
7174 gen_set_label(l1);
7175 #if defined(TARGET_PPC64)
7176 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7177 #else
7178 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7179 #endif
7180 gen_set_label(l2);
7181 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7182 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7183 #if defined(TARGET_PPC64)
7184 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7185 #else
7186 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7187 #endif
7188 tcg_gen_br(l4);
7189 gen_set_label(l3);
7190 #if defined(TARGET_PPC64)
7191 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7192 #else
7193 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7194 #endif
7195 gen_set_label(l4);
7196 tcg_temp_free_i32(t0);
7197 #if defined(TARGET_PPC64)
7198 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7199 tcg_temp_free(t1);
7200 tcg_temp_free(t2);
7201 #endif
7202 }
7203 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7204 {
7205 gen_evsel(ctx);
7206 }
7207 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7208 {
7209 gen_evsel(ctx);
7210 }
7211 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7212 {
7213 gen_evsel(ctx);
7214 }
7215 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7216 {
7217 gen_evsel(ctx);
7218 }
7219
7220 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7221 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7222 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7223 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7224 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7225 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7226 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7227 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7228 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7229 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7230 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7231 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7232 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7233 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7234 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7235 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7236 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7237 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7238 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7239 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7240 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7241 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7242 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7243 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7244 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7245
7246 /* SPE load and stores */
7247 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7248 {
7249 target_ulong uimm = rB(ctx->opcode);
7250
7251 if (rA(ctx->opcode) == 0) {
7252 tcg_gen_movi_tl(EA, uimm << sh);
7253 } else {
7254 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7255 #if defined(TARGET_PPC64)
7256 if (!ctx->sf_mode) {
7257 tcg_gen_ext32u_tl(EA, EA);
7258 }
7259 #endif
7260 }
7261 }
7262
7263 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7264 {
7265 #if defined(TARGET_PPC64)
7266 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7267 #else
7268 TCGv_i64 t0 = tcg_temp_new_i64();
7269 gen_qemu_ld64(ctx, t0, addr);
7270 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7271 tcg_gen_shri_i64(t0, t0, 32);
7272 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7273 tcg_temp_free_i64(t0);
7274 #endif
7275 }
7276
7277 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7278 {
7279 #if defined(TARGET_PPC64)
7280 TCGv t0 = tcg_temp_new();
7281 gen_qemu_ld32u(ctx, t0, addr);
7282 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7283 gen_addr_add(ctx, addr, addr, 4);
7284 gen_qemu_ld32u(ctx, t0, addr);
7285 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7286 tcg_temp_free(t0);
7287 #else
7288 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7289 gen_addr_add(ctx, addr, addr, 4);
7290 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7291 #endif
7292 }
7293
7294 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7295 {
7296 TCGv t0 = tcg_temp_new();
7297 #if defined(TARGET_PPC64)
7298 gen_qemu_ld16u(ctx, t0, addr);
7299 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7300 gen_addr_add(ctx, addr, addr, 2);
7301 gen_qemu_ld16u(ctx, t0, addr);
7302 tcg_gen_shli_tl(t0, t0, 32);
7303 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7304 gen_addr_add(ctx, addr, addr, 2);
7305 gen_qemu_ld16u(ctx, t0, addr);
7306 tcg_gen_shli_tl(t0, t0, 16);
7307 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7308 gen_addr_add(ctx, addr, addr, 2);
7309 gen_qemu_ld16u(ctx, t0, addr);
7310 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7311 #else
7312 gen_qemu_ld16u(ctx, t0, addr);
7313 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7314 gen_addr_add(ctx, addr, addr, 2);
7315 gen_qemu_ld16u(ctx, t0, addr);
7316 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7317 gen_addr_add(ctx, addr, addr, 2);
7318 gen_qemu_ld16u(ctx, t0, addr);
7319 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7320 gen_addr_add(ctx, addr, addr, 2);
7321 gen_qemu_ld16u(ctx, t0, addr);
7322 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7323 #endif
7324 tcg_temp_free(t0);
7325 }
7326
7327 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7328 {
7329 TCGv t0 = tcg_temp_new();
7330 gen_qemu_ld16u(ctx, t0, addr);
7331 #if defined(TARGET_PPC64)
7332 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7333 tcg_gen_shli_tl(t0, t0, 16);
7334 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7335 #else
7336 tcg_gen_shli_tl(t0, t0, 16);
7337 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7338 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7339 #endif
7340 tcg_temp_free(t0);
7341 }
7342
7343 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7344 {
7345 TCGv t0 = tcg_temp_new();
7346 gen_qemu_ld16u(ctx, t0, addr);
7347 #if defined(TARGET_PPC64)
7348 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7349 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7350 #else
7351 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7352 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7353 #endif
7354 tcg_temp_free(t0);
7355 }
7356
7357 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7358 {
7359 TCGv t0 = tcg_temp_new();
7360 gen_qemu_ld16s(ctx, t0, addr);
7361 #if defined(TARGET_PPC64)
7362 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7363 tcg_gen_ext32u_tl(t0, t0);
7364 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7365 #else
7366 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7367 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7368 #endif
7369 tcg_temp_free(t0);
7370 }
7371
7372 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7373 {
7374 TCGv t0 = tcg_temp_new();
7375 #if defined(TARGET_PPC64)
7376 gen_qemu_ld16u(ctx, t0, addr);
7377 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7378 gen_addr_add(ctx, addr, addr, 2);
7379 gen_qemu_ld16u(ctx, t0, addr);
7380 tcg_gen_shli_tl(t0, t0, 16);
7381 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7382 #else
7383 gen_qemu_ld16u(ctx, t0, addr);
7384 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7385 gen_addr_add(ctx, addr, addr, 2);
7386 gen_qemu_ld16u(ctx, t0, addr);
7387 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7388 #endif
7389 tcg_temp_free(t0);
7390 }
7391
7392 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7393 {
7394 #if defined(TARGET_PPC64)
7395 TCGv t0 = tcg_temp_new();
7396 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7397 gen_addr_add(ctx, addr, addr, 2);
7398 gen_qemu_ld16u(ctx, t0, addr);
7399 tcg_gen_shli_tl(t0, t0, 32);
7400 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7401 tcg_temp_free(t0);
7402 #else
7403 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7404 gen_addr_add(ctx, addr, addr, 2);
7405 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7406 #endif
7407 }
7408
7409 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7410 {
7411 #if defined(TARGET_PPC64)
7412 TCGv t0 = tcg_temp_new();
7413 gen_qemu_ld16s(ctx, t0, addr);
7414 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7415 gen_addr_add(ctx, addr, addr, 2);
7416 gen_qemu_ld16s(ctx, t0, addr);
7417 tcg_gen_shli_tl(t0, t0, 32);
7418 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7419 tcg_temp_free(t0);
7420 #else
7421 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7422 gen_addr_add(ctx, addr, addr, 2);
7423 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7424 #endif
7425 }
7426
7427 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7428 {
7429 TCGv t0 = tcg_temp_new();
7430 gen_qemu_ld32u(ctx, t0, addr);
7431 #if defined(TARGET_PPC64)
7432 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7433 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7434 #else
7435 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7436 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7437 #endif
7438 tcg_temp_free(t0);
7439 }
7440
7441 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7442 {
7443 TCGv t0 = tcg_temp_new();
7444 #if defined(TARGET_PPC64)
7445 gen_qemu_ld16u(ctx, t0, addr);
7446 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7447 tcg_gen_shli_tl(t0, t0, 32);
7448 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7449 gen_addr_add(ctx, addr, addr, 2);
7450 gen_qemu_ld16u(ctx, t0, addr);
7451 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7452 tcg_gen_shli_tl(t0, t0, 16);
7453 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7454 #else
7455 gen_qemu_ld16u(ctx, t0, addr);
7456 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7457 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7458 gen_addr_add(ctx, addr, addr, 2);
7459 gen_qemu_ld16u(ctx, t0, addr);
7460 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7461 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7462 #endif
7463 tcg_temp_free(t0);
7464 }
7465
7466 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7467 {
7468 #if defined(TARGET_PPC64)
7469 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7470 #else
7471 TCGv_i64 t0 = tcg_temp_new_i64();
7472 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7473 gen_qemu_st64(ctx, t0, addr);
7474 tcg_temp_free_i64(t0);
7475 #endif
7476 }
7477
7478 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7479 {
7480 #if defined(TARGET_PPC64)
7481 TCGv t0 = tcg_temp_new();
7482 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7483 gen_qemu_st32(ctx, t0, addr);
7484 tcg_temp_free(t0);
7485 #else
7486 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7487 #endif
7488 gen_addr_add(ctx, addr, addr, 4);
7489 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7490 }
7491
7492 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7493 {
7494 TCGv t0 = tcg_temp_new();
7495 #if defined(TARGET_PPC64)
7496 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7497 #else
7498 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7499 #endif
7500 gen_qemu_st16(ctx, t0, addr);
7501 gen_addr_add(ctx, addr, addr, 2);
7502 #if defined(TARGET_PPC64)
7503 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7504 gen_qemu_st16(ctx, t0, addr);
7505 #else
7506 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7507 #endif
7508 gen_addr_add(ctx, addr, addr, 2);
7509 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7510 gen_qemu_st16(ctx, t0, addr);
7511 tcg_temp_free(t0);
7512 gen_addr_add(ctx, addr, addr, 2);
7513 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7514 }
7515
7516 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7517 {
7518 TCGv t0 = tcg_temp_new();
7519 #if defined(TARGET_PPC64)
7520 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7521 #else
7522 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7523 #endif
7524 gen_qemu_st16(ctx, t0, addr);
7525 gen_addr_add(ctx, addr, addr, 2);
7526 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7527 gen_qemu_st16(ctx, t0, addr);
7528 tcg_temp_free(t0);
7529 }
7530
7531 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7532 {
7533 #if defined(TARGET_PPC64)
7534 TCGv t0 = tcg_temp_new();
7535 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7536 gen_qemu_st16(ctx, t0, addr);
7537 tcg_temp_free(t0);
7538 #else
7539 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7540 #endif
7541 gen_addr_add(ctx, addr, addr, 2);
7542 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7543 }
7544
7545 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7546 {
7547 #if defined(TARGET_PPC64)
7548 TCGv t0 = tcg_temp_new();
7549 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7550 gen_qemu_st32(ctx, t0, addr);
7551 tcg_temp_free(t0);
7552 #else
7553 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7554 #endif
7555 }
7556
7557 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7558 {
7559 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7560 }
7561
7562 #define GEN_SPEOP_LDST(name, opc2, sh) \
7563 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7564 { \
7565 TCGv t0; \
7566 if (unlikely(!ctx->spe_enabled)) { \
7567 gen_exception(ctx, POWERPC_EXCP_APU); \
7568 return; \
7569 } \
7570 gen_set_access_type(ctx, ACCESS_INT); \
7571 t0 = tcg_temp_new(); \
7572 if (Rc(ctx->opcode)) { \
7573 gen_addr_spe_imm_index(ctx, t0, sh); \
7574 } else { \
7575 gen_addr_reg_index(ctx, t0); \
7576 } \
7577 gen_op_##name(ctx, t0); \
7578 tcg_temp_free(t0); \
7579 }
7580
7581 GEN_SPEOP_LDST(evldd, 0x00, 3);
7582 GEN_SPEOP_LDST(evldw, 0x01, 3);
7583 GEN_SPEOP_LDST(evldh, 0x02, 3);
7584 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7585 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7586 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7587 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7588 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7589 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7590 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7591 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7592
7593 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7594 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7595 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7596 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7597 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7598 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7599 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7600
7601 /* Multiply and add - TODO */
7602 #if 0
7603 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7604 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7605 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7606 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7607 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7608 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7609 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7610 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7611 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7612 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7613 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7614 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7615
7616 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7617 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7618 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7619 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7620 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7621 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7622 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7623 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7624 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7625 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7626 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7627 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7628 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7629 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7630
7631 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7632 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7633 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7634 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7635 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7636 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7637
7638 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7639 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7640 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7641 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7642 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7643 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7644 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7645 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7646 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7647 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7648 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7649 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7650
7651 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7652 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7653 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7654 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7655 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7656
7657 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7658 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7659 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7660 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7661 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7662 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7663 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7664 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7665 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7666 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7667 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7668 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7669
7670 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7671 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7672 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7673 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7674 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7675 #endif
7676
7677 /*** SPE floating-point extension ***/
7678 #if defined(TARGET_PPC64)
7679 #define GEN_SPEFPUOP_CONV_32_32(name) \
7680 static always_inline void gen_##name (DisasContext *ctx) \
7681 { \
7682 TCGv_i32 t0; \
7683 TCGv t1; \
7684 t0 = tcg_temp_new_i32(); \
7685 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7686 gen_helper_##name(t0, t0); \
7687 t1 = tcg_temp_new(); \
7688 tcg_gen_extu_i32_tl(t1, t0); \
7689 tcg_temp_free_i32(t0); \
7690 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7691 0xFFFFFFFF00000000ULL); \
7692 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7693 tcg_temp_free(t1); \
7694 }
7695 #define GEN_SPEFPUOP_CONV_32_64(name) \
7696 static always_inline void gen_##name (DisasContext *ctx) \
7697 { \
7698 TCGv_i32 t0; \
7699 TCGv t1; \
7700 t0 = tcg_temp_new_i32(); \
7701 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7702 t1 = tcg_temp_new(); \
7703 tcg_gen_extu_i32_tl(t1, t0); \
7704 tcg_temp_free_i32(t0); \
7705 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7706 0xFFFFFFFF00000000ULL); \
7707 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7708 tcg_temp_free(t1); \
7709 }
7710 #define GEN_SPEFPUOP_CONV_64_32(name) \
7711 static always_inline void gen_##name (DisasContext *ctx) \
7712 { \
7713 TCGv_i32 t0 = tcg_temp_new_i32(); \
7714 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7715 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7716 tcg_temp_free_i32(t0); \
7717 }
7718 #define GEN_SPEFPUOP_CONV_64_64(name) \
7719 static always_inline void gen_##name (DisasContext *ctx) \
7720 { \
7721 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7722 }
7723 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7724 static always_inline void gen_##name (DisasContext *ctx) \
7725 { \
7726 TCGv_i32 t0, t1; \
7727 TCGv_i64 t2; \
7728 if (unlikely(!ctx->spe_enabled)) { \
7729 gen_exception(ctx, POWERPC_EXCP_APU); \
7730 return; \
7731 } \
7732 t0 = tcg_temp_new_i32(); \
7733 t1 = tcg_temp_new_i32(); \
7734 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7735 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7736 gen_helper_##name(t0, t0, t1); \
7737 tcg_temp_free_i32(t1); \
7738 t2 = tcg_temp_new(); \
7739 tcg_gen_extu_i32_tl(t2, t0); \
7740 tcg_temp_free_i32(t0); \
7741 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7742 0xFFFFFFFF00000000ULL); \
7743 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7744 tcg_temp_free(t2); \
7745 }
7746 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7747 static always_inline void gen_##name (DisasContext *ctx) \
7748 { \
7749 if (unlikely(!ctx->spe_enabled)) { \
7750 gen_exception(ctx, POWERPC_EXCP_APU); \
7751 return; \
7752 } \
7753 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7754 cpu_gpr[rB(ctx->opcode)]); \
7755 }
7756 #define GEN_SPEFPUOP_COMP_32(name) \
7757 static always_inline void gen_##name (DisasContext *ctx) \
7758 { \
7759 TCGv_i32 t0, t1; \
7760 if (unlikely(!ctx->spe_enabled)) { \
7761 gen_exception(ctx, POWERPC_EXCP_APU); \
7762 return; \
7763 } \
7764 t0 = tcg_temp_new_i32(); \
7765 t1 = tcg_temp_new_i32(); \
7766 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7767 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7768 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7769 tcg_temp_free_i32(t0); \
7770 tcg_temp_free_i32(t1); \
7771 }
7772 #define GEN_SPEFPUOP_COMP_64(name) \
7773 static always_inline void gen_##name (DisasContext *ctx) \
7774 { \
7775 if (unlikely(!ctx->spe_enabled)) { \
7776 gen_exception(ctx, POWERPC_EXCP_APU); \
7777 return; \
7778 } \
7779 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7780 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7781 }
7782 #else
7783 #define GEN_SPEFPUOP_CONV_32_32(name) \
7784 static always_inline void gen_##name (DisasContext *ctx) \
7785 { \
7786 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7787 }
7788 #define GEN_SPEFPUOP_CONV_32_64(name) \
7789 static always_inline void gen_##name (DisasContext *ctx) \
7790 { \
7791 TCGv_i64 t0 = tcg_temp_new_i64(); \
7792 gen_load_gpr64(t0, rB(ctx->opcode)); \
7793 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7794 tcg_temp_free_i64(t0); \
7795 }
7796 #define GEN_SPEFPUOP_CONV_64_32(name) \
7797 static always_inline void gen_##name (DisasContext *ctx) \
7798 { \
7799 TCGv_i64 t0 = tcg_temp_new_i64(); \
7800 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7801 gen_store_gpr64(rD(ctx->opcode), t0); \
7802 tcg_temp_free_i64(t0); \
7803 }
7804 #define GEN_SPEFPUOP_CONV_64_64(name) \
7805 static always_inline void gen_##name (DisasContext *ctx) \
7806 { \
7807 TCGv_i64 t0 = tcg_temp_new_i64(); \
7808 gen_load_gpr64(t0, rB(ctx->opcode)); \
7809 gen_helper_##name(t0, t0); \
7810 gen_store_gpr64(rD(ctx->opcode), t0); \
7811 tcg_temp_free_i64(t0); \
7812 }
7813 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7814 static always_inline void gen_##name (DisasContext *ctx) \
7815 { \
7816 if (unlikely(!ctx->spe_enabled)) { \
7817 gen_exception(ctx, POWERPC_EXCP_APU); \
7818 return; \
7819 } \
7820 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7821 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7822 }
7823 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7824 static always_inline void gen_##name (DisasContext *ctx) \
7825 { \
7826 TCGv_i64 t0, t1; \
7827 if (unlikely(!ctx->spe_enabled)) { \
7828 gen_exception(ctx, POWERPC_EXCP_APU); \
7829 return; \
7830 } \
7831 t0 = tcg_temp_new_i64(); \
7832 t1 = tcg_temp_new_i64(); \
7833 gen_load_gpr64(t0, rA(ctx->opcode)); \
7834 gen_load_gpr64(t1, rB(ctx->opcode)); \
7835 gen_helper_##name(t0, t0, t1); \
7836 gen_store_gpr64(rD(ctx->opcode), t0); \
7837 tcg_temp_free_i64(t0); \
7838 tcg_temp_free_i64(t1); \
7839 }
7840 #define GEN_SPEFPUOP_COMP_32(name) \
7841 static always_inline void gen_##name (DisasContext *ctx) \
7842 { \
7843 if (unlikely(!ctx->spe_enabled)) { \
7844 gen_exception(ctx, POWERPC_EXCP_APU); \
7845 return; \
7846 } \
7847 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7848 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7849 }
7850 #define GEN_SPEFPUOP_COMP_64(name) \
7851 static always_inline void gen_##name (DisasContext *ctx) \
7852 { \
7853 TCGv_i64 t0, t1; \
7854 if (unlikely(!ctx->spe_enabled)) { \
7855 gen_exception(ctx, POWERPC_EXCP_APU); \
7856 return; \
7857 } \
7858 t0 = tcg_temp_new_i64(); \
7859 t1 = tcg_temp_new_i64(); \
7860 gen_load_gpr64(t0, rA(ctx->opcode)); \
7861 gen_load_gpr64(t1, rB(ctx->opcode)); \
7862 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7863 tcg_temp_free_i64(t0); \
7864 tcg_temp_free_i64(t1); \
7865 }
7866 #endif
7867
7868 /* Single precision floating-point vectors operations */
7869 /* Arithmetic */
7870 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7871 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7872 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7873 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7874 static always_inline void gen_evfsabs (DisasContext *ctx)
7875 {
7876 if (unlikely(!ctx->spe_enabled)) {
7877 gen_exception(ctx, POWERPC_EXCP_APU);
7878 return;
7879 }
7880 #if defined(TARGET_PPC64)
7881 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7882 #else
7883 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7884 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7885 #endif
7886 }
7887 static always_inline void gen_evfsnabs (DisasContext *ctx)
7888 {
7889 if (unlikely(!ctx->spe_enabled)) {
7890 gen_exception(ctx, POWERPC_EXCP_APU);
7891 return;
7892 }
7893 #if defined(TARGET_PPC64)
7894 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7895 #else
7896 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7897 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7898 #endif
7899 }
7900 static always_inline void gen_evfsneg (DisasContext *ctx)
7901 {
7902 if (unlikely(!ctx->spe_enabled)) {
7903 gen_exception(ctx, POWERPC_EXCP_APU);
7904 return;
7905 }
7906 #if defined(TARGET_PPC64)
7907 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7908 #else
7909 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7910 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7911 #endif
7912 }
7913
7914 /* Conversion */
7915 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7916 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7917 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7918 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7919 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7920 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7921 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7922 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7923 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7924 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7925
7926 /* Comparison */
7927 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7928 GEN_SPEFPUOP_COMP_64(evfscmplt);
7929 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7930 GEN_SPEFPUOP_COMP_64(evfststgt);
7931 GEN_SPEFPUOP_COMP_64(evfststlt);
7932 GEN_SPEFPUOP_COMP_64(evfststeq);
7933
7934 /* Opcodes definitions */
7935 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7936 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7937 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7938 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7939 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7940 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7941 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7942 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7943 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7944 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7945 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7946 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7947 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7948 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7949
7950 /* Single precision floating-point operations */
7951 /* Arithmetic */
7952 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7953 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7954 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7955 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7956 static always_inline void gen_efsabs (DisasContext *ctx)
7957 {
7958 if (unlikely(!ctx->spe_enabled)) {
7959 gen_exception(ctx, POWERPC_EXCP_APU);
7960 return;
7961 }
7962 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7963 }
7964 static always_inline void gen_efsnabs (DisasContext *ctx)
7965 {
7966 if (unlikely(!ctx->spe_enabled)) {
7967 gen_exception(ctx, POWERPC_EXCP_APU);
7968 return;
7969 }
7970 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7971 }
7972 static always_inline void gen_efsneg (DisasContext *ctx)
7973 {
7974 if (unlikely(!ctx->spe_enabled)) {
7975 gen_exception(ctx, POWERPC_EXCP_APU);
7976 return;
7977 }
7978 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7979 }
7980
7981 /* Conversion */
7982 GEN_SPEFPUOP_CONV_32_32(efscfui);
7983 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7984 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7985 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7986 GEN_SPEFPUOP_CONV_32_32(efsctui);
7987 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7988 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7989 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7990 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7991 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7992 GEN_SPEFPUOP_CONV_32_64(efscfd);
7993
7994 /* Comparison */
7995 GEN_SPEFPUOP_COMP_32(efscmpgt);
7996 GEN_SPEFPUOP_COMP_32(efscmplt);
7997 GEN_SPEFPUOP_COMP_32(efscmpeq);
7998 GEN_SPEFPUOP_COMP_32(efststgt);
7999 GEN_SPEFPUOP_COMP_32(efststlt);
8000 GEN_SPEFPUOP_COMP_32(efststeq);
8001
8002 /* Opcodes definitions */
8003 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8004 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8005 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8006 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8007 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8008 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8009 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8010 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8011 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8012 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8013 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8014 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8015 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8016 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8017
8018 /* Double precision floating-point operations */
8019 /* Arithmetic */
8020 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8021 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8022 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8023 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8024 static always_inline void gen_efdabs (DisasContext *ctx)
8025 {
8026 if (unlikely(!ctx->spe_enabled)) {
8027 gen_exception(ctx, POWERPC_EXCP_APU);
8028 return;
8029 }
8030 #if defined(TARGET_PPC64)
8031 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8032 #else
8033 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8034 #endif
8035 }
8036 static always_inline void gen_efdnabs (DisasContext *ctx)
8037 {
8038 if (unlikely(!ctx->spe_enabled)) {
8039 gen_exception(ctx, POWERPC_EXCP_APU);
8040 return;
8041 }
8042 #if defined(TARGET_PPC64)
8043 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8044 #else
8045 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8046 #endif
8047 }
8048 static always_inline void gen_efdneg (DisasContext *ctx)
8049 {
8050 if (unlikely(!ctx->spe_enabled)) {
8051 gen_exception(ctx, POWERPC_EXCP_APU);
8052 return;
8053 }
8054 #if defined(TARGET_PPC64)
8055 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8056 #else
8057 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8058 #endif
8059 }
8060
8061 /* Conversion */
8062 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8063 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8064 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8065 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8066 GEN_SPEFPUOP_CONV_32_64(efdctui);
8067 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8068 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8069 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8070 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8071 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8072 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8073 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8074 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8075 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8076 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8077
8078 /* Comparison */
8079 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8080 GEN_SPEFPUOP_COMP_64(efdcmplt);
8081 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8082 GEN_SPEFPUOP_COMP_64(efdtstgt);
8083 GEN_SPEFPUOP_COMP_64(efdtstlt);
8084 GEN_SPEFPUOP_COMP_64(efdtsteq);
8085
8086 /* Opcodes definitions */
8087 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8088 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8089 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8090 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8091 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8092 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8093 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8094 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8095 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8096 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8097 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8098 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8099 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8100 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8101 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8102 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8103
8104 /* End opcode list */
8105 GEN_OPCODE_MARK(end);
8106
8107 #include "translate_init.c"
8108 #include "helper_regs.h"
8109
8110 /*****************************************************************************/
8111 /* Misc PowerPC helpers */
8112 void cpu_dump_state (CPUState *env, FILE *f,
8113 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8114 int flags)
8115 {
8116 #define RGPL 4
8117 #define RFPL 4
8118
8119 int i;
8120
8121 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8122 env->nip, env->lr, env->ctr, env->xer);
8123 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8124 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8125 #if !defined(NO_TIMER_DUMP)
8126 cpu_fprintf(f, "TB %08x %08x "
8127 #if !defined(CONFIG_USER_ONLY)
8128 "DECR %08x"
8129 #endif
8130 "\n",
8131 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8132 #if !defined(CONFIG_USER_ONLY)
8133 , cpu_ppc_load_decr(env)
8134 #endif
8135 );
8136 #endif
8137 for (i = 0; i < 32; i++) {
8138 if ((i & (RGPL - 1)) == 0)
8139 cpu_fprintf(f, "GPR%02d", i);
8140 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8141 if ((i & (RGPL - 1)) == (RGPL - 1))
8142 cpu_fprintf(f, "\n");
8143 }
8144 cpu_fprintf(f, "CR ");
8145 for (i = 0; i < 8; i++)
8146 cpu_fprintf(f, "%01x", env->crf[i]);
8147 cpu_fprintf(f, " [");
8148 for (i = 0; i < 8; i++) {
8149 char a = '-';
8150 if (env->crf[i] & 0x08)
8151 a = 'L';
8152 else if (env->crf[i] & 0x04)
8153 a = 'G';
8154 else if (env->crf[i] & 0x02)
8155 a = 'E';
8156 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8157 }
8158 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8159 for (i = 0; i < 32; i++) {
8160 if ((i & (RFPL - 1)) == 0)
8161 cpu_fprintf(f, "FPR%02d", i);
8162 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8163 if ((i & (RFPL - 1)) == (RFPL - 1))
8164 cpu_fprintf(f, "\n");
8165 }
8166 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8167 #if !defined(CONFIG_USER_ONLY)
8168 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8169 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8170 #endif
8171
8172 #undef RGPL
8173 #undef RFPL
8174 }
8175
8176 void cpu_dump_statistics (CPUState *env, FILE*f,
8177 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8178 int flags)
8179 {
8180 #if defined(DO_PPC_STATISTICS)
8181 opc_handler_t **t1, **t2, **t3, *handler;
8182 int op1, op2, op3;
8183
8184 t1 = env->opcodes;
8185 for (op1 = 0; op1 < 64; op1++) {
8186 handler = t1[op1];
8187 if (is_indirect_opcode(handler)) {
8188 t2 = ind_table(handler);
8189 for (op2 = 0; op2 < 32; op2++) {
8190 handler = t2[op2];
8191 if (is_indirect_opcode(handler)) {
8192 t3 = ind_table(handler);
8193 for (op3 = 0; op3 < 32; op3++) {
8194 handler = t3[op3];
8195 if (handler->count == 0)
8196 continue;
8197 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8198 "%016llx %lld\n",
8199 op1, op2, op3, op1, (op3 << 5) | op2,
8200 handler->oname,
8201 handler->count, handler->count);
8202 }
8203 } else {
8204 if (handler->count == 0)
8205 continue;
8206 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8207 "%016llx %lld\n",
8208 op1, op2, op1, op2, handler->oname,
8209 handler->count, handler->count);
8210 }
8211 }
8212 } else {
8213 if (handler->count == 0)
8214 continue;
8215 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8216 op1, op1, handler->oname,
8217 handler->count, handler->count);
8218 }
8219 }
8220 #endif
8221 }
8222
8223 /*****************************************************************************/
8224 static always_inline void gen_intermediate_code_internal (CPUState *env,
8225 TranslationBlock *tb,
8226 int search_pc)
8227 {
8228 DisasContext ctx, *ctxp = &ctx;
8229 opc_handler_t **table, *handler;
8230 target_ulong pc_start;
8231 uint16_t *gen_opc_end;
8232 CPUBreakpoint *bp;
8233 int j, lj = -1;
8234 int num_insns;
8235 int max_insns;
8236
8237 pc_start = tb->pc;
8238 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8239 ctx.nip = pc_start;
8240 ctx.tb = tb;
8241 ctx.exception = POWERPC_EXCP_NONE;
8242 ctx.spr_cb = env->spr_cb;
8243 ctx.mem_idx = env->mmu_idx;
8244 ctx.access_type = -1;
8245 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8246 #if defined(TARGET_PPC64)
8247 ctx.sf_mode = msr_sf;
8248 #endif
8249 ctx.fpu_enabled = msr_fp;
8250 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8251 ctx.spe_enabled = msr_spe;
8252 else
8253 ctx.spe_enabled = 0;
8254 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8255 ctx.altivec_enabled = msr_vr;
8256 else
8257 ctx.altivec_enabled = 0;
8258 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8259 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8260 else
8261 ctx.singlestep_enabled = 0;
8262 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8263 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8264 if (unlikely(env->singlestep_enabled))
8265 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8266 #if defined (DO_SINGLE_STEP) && 0
8267 /* Single step trace mode */
8268 msr_se = 1;
8269 #endif
8270 num_insns = 0;
8271 max_insns = tb->cflags & CF_COUNT_MASK;
8272 if (max_insns == 0)
8273 max_insns = CF_COUNT_MASK;
8274
8275 gen_icount_start();
8276 /* Set env in case of segfault during code fetch */
8277 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8278 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8279 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8280 if (bp->pc == ctx.nip) {
8281 gen_debug_exception(ctxp);
8282 break;
8283 }
8284 }
8285 }
8286 if (unlikely(search_pc)) {
8287 j = gen_opc_ptr - gen_opc_buf;
8288 if (lj < j) {
8289 lj++;
8290 while (lj < j)
8291 gen_opc_instr_start[lj++] = 0;
8292 gen_opc_pc[lj] = ctx.nip;
8293 gen_opc_instr_start[lj] = 1;
8294 gen_opc_icount[lj] = num_insns;
8295 }
8296 }
8297 LOG_DISAS("----------------\n");
8298 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8299 ctx.nip, ctx.mem_idx, (int)msr_ir);
8300 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8301 gen_io_start();
8302 if (unlikely(ctx.le_mode)) {
8303 ctx.opcode = bswap32(ldl_code(ctx.nip));
8304 } else {
8305 ctx.opcode = ldl_code(ctx.nip);
8306 }
8307 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8308 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8309 opc3(ctx.opcode), little_endian ? "little" : "big");
8310 ctx.nip += 4;
8311 table = env->opcodes;
8312 num_insns++;
8313 handler = table[opc1(ctx.opcode)];
8314 if (is_indirect_opcode(handler)) {
8315 table = ind_table(handler);
8316 handler = table[opc2(ctx.opcode)];
8317 if (is_indirect_opcode(handler)) {
8318 table = ind_table(handler);
8319 handler = table[opc3(ctx.opcode)];
8320 }
8321 }
8322 /* Is opcode *REALLY* valid ? */
8323 if (unlikely(handler->handler == &gen_invalid)) {
8324 if (qemu_log_enabled()) {
8325 qemu_log("invalid/unsupported opcode: "
8326 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8327 opc1(ctx.opcode), opc2(ctx.opcode),
8328 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8329 } else {
8330 printf("invalid/unsupported opcode: "
8331 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8332 opc1(ctx.opcode), opc2(ctx.opcode),
8333 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8334 }
8335 } else {
8336 if (unlikely((ctx.opcode & handler->inval) != 0)) {
8337 if (qemu_log_enabled()) {
8338 qemu_log("invalid bits: %08x for opcode: "
8339 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8340 ctx.opcode & handler->inval, opc1(ctx.opcode),
8341 opc2(ctx.opcode), opc3(ctx.opcode),
8342 ctx.opcode, ctx.nip - 4);
8343 } else {
8344 printf("invalid bits: %08x for opcode: "
8345 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8346 ctx.opcode & handler->inval, opc1(ctx.opcode),
8347 opc2(ctx.opcode), opc3(ctx.opcode),
8348 ctx.opcode, ctx.nip - 4);
8349 }
8350 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8351 break;
8352 }
8353 }
8354 (*(handler->handler))(&ctx);
8355 #if defined(DO_PPC_STATISTICS)
8356 handler->count++;
8357 #endif
8358 /* Check trace mode exceptions */
8359 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8360 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8361 ctx.exception != POWERPC_SYSCALL &&
8362 ctx.exception != POWERPC_EXCP_TRAP &&
8363 ctx.exception != POWERPC_EXCP_BRANCH)) {
8364 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8365 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8366 (env->singlestep_enabled) ||
8367 num_insns >= max_insns)) {
8368 /* if we reach a page boundary or are single stepping, stop
8369 * generation
8370 */
8371 break;
8372 }
8373 #if defined (DO_SINGLE_STEP)
8374 break;
8375 #endif
8376 }
8377 if (tb->cflags & CF_LAST_IO)
8378 gen_io_end();
8379 if (ctx.exception == POWERPC_EXCP_NONE) {
8380 gen_goto_tb(&ctx, 0, ctx.nip);
8381 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8382 if (unlikely(env->singlestep_enabled)) {
8383 gen_debug_exception(ctxp);
8384 }
8385 /* Generate the return instruction */
8386 tcg_gen_exit_tb(0);
8387 }
8388 gen_icount_end(tb, num_insns);
8389 *gen_opc_ptr = INDEX_op_end;
8390 if (unlikely(search_pc)) {
8391 j = gen_opc_ptr - gen_opc_buf;
8392 lj++;
8393 while (lj <= j)
8394 gen_opc_instr_start[lj++] = 0;
8395 } else {
8396 tb->size = ctx.nip - pc_start;
8397 tb->icount = num_insns;
8398 }
8399 #if defined(DEBUG_DISAS)
8400 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8401 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8402 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8403 int flags;
8404 flags = env->bfd_mach;
8405 flags |= ctx.le_mode << 16;
8406 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8407 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8408 qemu_log("\n");
8409 }
8410 #endif
8411 }
8412
8413 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8414 {
8415 gen_intermediate_code_internal(env, tb, 0);
8416 }
8417
8418 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8419 {
8420 gen_intermediate_code_internal(env, tb, 1);
8421 }
8422
8423 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8424 unsigned long searched_pc, int pc_pos, void *puc)
8425 {
8426 env->nip = gen_opc_pc[pc_pos];
8427 }