target-ppc/translate_init.c

   1 /*
   2  *  PowerPC CPU initialization for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20
  21 /* A lot of PowerPC definition have been included here.
  22  * Most of them are not usable for now but have been kept
  23  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
  24  */
  25
  26 #include "dis-asm.h"
  27 #include "host-utils.h"
  28 #include "gdbstub.h"
  29
  30 //#define PPC_DUMP_CPU
  31 //#define PPC_DEBUG_SPR
  32 //#define PPC_DUMP_SPR_ACCESSES
  33 #if defined(CONFIG_USER_ONLY)
  34 #define TODO_USER_ONLY 1
  35 #endif
  36
  37 struct ppc_def_t {
  38     const char *name;
  39     uint32_t pvr;
  40     uint32_t svr;
  41     uint64_t insns_flags;
  42     uint64_t msr_mask;
  43     powerpc_mmu_t   mmu_model;
  44     powerpc_excp_t  excp_model;
  45     powerpc_input_t bus_model;
  46     uint32_t flags;
  47     int bfd_mach;
  48     void (*init_proc)(CPUPPCState *env);
  49     int  (*check_pow)(CPUPPCState *env);
  50 };
  51
  52 /* For user-mode emulation, we don't emulate any IRQ controller */
  53 #if defined(CONFIG_USER_ONLY)
  54 #define PPC_IRQ_INIT_FN(name)                                                 \
  55 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  56 {                                                                             \
  57 }
  58 #else
  59 #define PPC_IRQ_INIT_FN(name)                                                 \
  60 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  61 #endif
  62
  63 PPC_IRQ_INIT_FN(40x);
  64 PPC_IRQ_INIT_FN(6xx);
  65 PPC_IRQ_INIT_FN(970);
  66
  67 /* Generic callbacks:
  68  * do nothing but store/retrieve spr value
  69  */
  70 static void spr_read_generic (void *opaque, int gprn, int sprn)
  71 {
  72     gen_load_spr(cpu_gpr[gprn], sprn);
  73 #ifdef PPC_DUMP_SPR_ACCESSES
  74     {
  75         TCGv t0 = tcg_const_i32(sprn);
  76         gen_helper_load_dump_spr(t0);
  77         tcg_temp_free_i32(t0);
  78     }
  79 #endif
  80 }
  81
  82 static void spr_write_generic (void *opaque, int sprn, int gprn)
  83 {
  84     gen_store_spr(sprn, cpu_gpr[gprn]);
  85 #ifdef PPC_DUMP_SPR_ACCESSES
  86     {
  87         TCGv t0 = tcg_const_i32(sprn);
  88         gen_helper_store_dump_spr(t0);
  89         tcg_temp_free_i32(t0);
  90     }
  91 #endif
  92 }
  93
  94 #if !defined(CONFIG_USER_ONLY)
  95 static void spr_write_clear (void *opaque, int sprn, int gprn)
  96 {
  97     TCGv t0 = tcg_temp_new();
  98     TCGv t1 = tcg_temp_new();
  99     gen_load_spr(t0, sprn);
 100     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 101     tcg_gen_and_tl(t0, t0, t1);
 102     gen_store_spr(sprn, t0);
 103     tcg_temp_free(t0);
 104     tcg_temp_free(t1);
 105 }
 106 #endif
 107
 108 /* SPR common to all PowerPC */
 109 /* XER */
 110 static void spr_read_xer (void *opaque, int gprn, int sprn)
 111 {
 112     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
 113 }
 114
 115 static void spr_write_xer (void *opaque, int sprn, int gprn)
 116 {
 117     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
 118 }
 119
 120 /* LR */
 121 static void spr_read_lr (void *opaque, int gprn, int sprn)
 122 {
 123     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 124 }
 125
 126 static void spr_write_lr (void *opaque, int sprn, int gprn)
 127 {
 128     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 129 }
 130
 131 /* CTR */
 132 static void spr_read_ctr (void *opaque, int gprn, int sprn)
 133 {
 134     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 135 }
 136
 137 static void spr_write_ctr (void *opaque, int sprn, int gprn)
 138 {
 139     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 140 }
 141
 142 /* User read access to SPR */
 143 /* USPRx */
 144 /* UMMCRx */
 145 /* UPMCx */
 146 /* USIA */
 147 /* UDECR */
 148 static void spr_read_ureg (void *opaque, int gprn, int sprn)
 149 {
 150     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 151 }
 152
 153 /* SPR common to all non-embedded PowerPC */
 154 /* DECR */
 155 #if !defined(CONFIG_USER_ONLY)
 156 static void spr_read_decr (void *opaque, int gprn, int sprn)
 157 {
 158     gen_helper_load_decr(cpu_gpr[gprn]);
 159 }
 160
 161 static void spr_write_decr (void *opaque, int sprn, int gprn)
 162 {
 163     gen_helper_store_decr(cpu_gpr[gprn]);
 164 }
 165 #endif
 166
 167 /* SPR common to all non-embedded PowerPC, except 601 */
 168 /* Time base */
 169 static void spr_read_tbl (void *opaque, int gprn, int sprn)
 170 {
 171     gen_helper_load_tbl(cpu_gpr[gprn]);
 172 }
 173
 174 static void spr_read_tbu (void *opaque, int gprn, int sprn)
 175 {
 176     gen_helper_load_tbu(cpu_gpr[gprn]);
 177 }
 178
 179 __attribute__ (( unused ))
 180 static void spr_read_atbl (void *opaque, int gprn, int sprn)
 181 {
 182     gen_helper_load_atbl(cpu_gpr[gprn]);
 183 }
 184
 185 __attribute__ (( unused ))
 186 static void spr_read_atbu (void *opaque, int gprn, int sprn)
 187 {
 188     gen_helper_load_atbu(cpu_gpr[gprn]);
 189 }
 190
 191 #if !defined(CONFIG_USER_ONLY)
 192 static void spr_write_tbl (void *opaque, int sprn, int gprn)
 193 {
 194     gen_helper_store_tbl(cpu_gpr[gprn]);
 195 }
 196
 197 static void spr_write_tbu (void *opaque, int sprn, int gprn)
 198 {
 199     gen_helper_store_tbu(cpu_gpr[gprn]);
 200 }
 201
 202 __attribute__ (( unused ))
 203 static void spr_write_atbl (void *opaque, int sprn, int gprn)
 204 {
 205     gen_helper_store_atbl(cpu_gpr[gprn]);
 206 }
 207
 208 __attribute__ (( unused ))
 209 static void spr_write_atbu (void *opaque, int sprn, int gprn)
 210 {
 211     gen_helper_store_atbu(cpu_gpr[gprn]);
 212 }
 213 #endif
 214
 215 #if !defined(CONFIG_USER_ONLY)
 216 /* IBAT0U...IBAT0U */
 217 /* IBAT0L...IBAT7L */
 218 static void spr_read_ibat (void *opaque, int gprn, int sprn)
 219 {
 220     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 221 }
 222
 223 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
 224 {
 225     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
 226 }
 227
 228 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
 229 {
 230     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 231     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 232     tcg_temp_free_i32(t0);
 233 }
 234
 235 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
 236 {
 237     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);
 238     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 239     tcg_temp_free_i32(t0);
 240 }
 241
 242 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
 243 {
 244     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 245     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 246     tcg_temp_free_i32(t0);
 247 }
 248
 249 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
 250 {
 251     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);
 252     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 253     tcg_temp_free_i32(t0);
 254 }
 255
 256 /* DBAT0U...DBAT7U */
 257 /* DBAT0L...DBAT7L */
 258 static void spr_read_dbat (void *opaque, int gprn, int sprn)
 259 {
 260     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 261 }
 262
 263 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
 264 {
 265     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 266 }
 267
 268 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
 269 {
 270     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 271     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 272     tcg_temp_free_i32(t0);
 273 }
 274
 275 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
 276 {
 277     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 278     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 279     tcg_temp_free_i32(t0);
 280 }
 281
 282 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
 283 {
 284     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 285     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 286     tcg_temp_free_i32(t0);
 287 }
 288
 289 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
 290 {
 291     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 292     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 293     tcg_temp_free_i32(t0);
 294 }
 295
 296 /* SDR1 */
 297 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
 298 {
 299     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
 300 }
 301
 302 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
 303 {
 304     gen_helper_store_sdr1(cpu_gpr[gprn]);
 305 }
 306
 307 /* 64 bits PowerPC specific SPRs */
 308 /* ASR */
 309 #if defined(TARGET_PPC64)
 310 static void spr_read_asr (void *opaque, int gprn, int sprn)
 311 {
 312     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
 313 }
 314
 315 static void spr_write_asr (void *opaque, int sprn, int gprn)
 316 {
 317     gen_helper_store_asr(cpu_gpr[gprn]);
 318 }
 319 #endif
 320 #endif
 321
 322 /* PowerPC 601 specific registers */
 323 /* RTC */
 324 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
 325 {
 326     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
 327 }
 328
 329 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
 330 {
 331     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
 332 }
 333
 334 #if !defined(CONFIG_USER_ONLY)
 335 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
 336 {
 337     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
 338 }
 339
 340 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
 341 {
 342     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
 343 }
 344
 345 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
 346 {
 347     DisasContext *ctx = opaque;
 348
 349     gen_helper_store_hid0_601(cpu_gpr[gprn]);
 350     /* Must stop the translation as endianness may have changed */
 351     gen_stop_exception(ctx);
 352 }
 353 #endif
 354
 355 /* Unified bats */
 356 #if !defined(CONFIG_USER_ONLY)
 357 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
 358 {
 359     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 360 }
 361
 362 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
 363 {
 364     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 365     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
 366     tcg_temp_free_i32(t0);
 367 }
 368
 369 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
 370 {
 371     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 372     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
 373     tcg_temp_free_i32(t0);
 374 }
 375 #endif
 376
 377 /* PowerPC 40x specific registers */
 378 #if !defined(CONFIG_USER_ONLY)
 379 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
 380 {
 381     gen_helper_load_40x_pit(cpu_gpr[gprn]);
 382 }
 383
 384 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
 385 {
 386     gen_helper_store_40x_pit(cpu_gpr[gprn]);
 387 }
 388
 389 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
 390 {
 391     DisasContext *ctx = opaque;
 392
 393     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
 394     /* We must stop translation as we may have rebooted */
 395     gen_stop_exception(ctx);
 396 }
 397
 398 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
 399 {
 400     gen_helper_store_40x_sler(cpu_gpr[gprn]);
 401 }
 402
 403 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
 404 {
 405     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
 406 }
 407
 408 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
 409 {
 410     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
 411 }
 412 #endif
 413
 414 /* PowerPC 403 specific registers */
 415 /* PBL1 / PBU1 / PBL2 / PBU2 */
 416 #if !defined(CONFIG_USER_ONLY)
 417 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
 418 {
 419     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
 420 }
 421
 422 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
 423 {
 424     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 425     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
 426     tcg_temp_free_i32(t0);
 427 }
 428
 429 static void spr_write_pir (void *opaque, int sprn, int gprn)
 430 {
 431     TCGv t0 = tcg_temp_new();
 432     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 433     gen_store_spr(SPR_PIR, t0);
 434     tcg_temp_free(t0);
 435 }
 436 #endif
 437
 438 #if !defined(CONFIG_USER_ONLY)
 439 /* Callback used to write the exception vector base */
 440 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
 441 {
 442     TCGv t0 = tcg_temp_new();
 443     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
 444     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 445     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 446     gen_store_spr(sprn, t0);
 447 }
 448
 449 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
 450 {
 451     DisasContext *ctx = opaque;
 452
 453     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 454         TCGv t0 = tcg_temp_new();
 455         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 456         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 457         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
 458         gen_store_spr(sprn, t0);
 459         tcg_temp_free(t0);
 460     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 461         TCGv t0 = tcg_temp_new();
 462         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 463         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 464         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
 465         gen_store_spr(sprn, t0);
 466         tcg_temp_free(t0);
 467     } else {
 468         printf("Trying to write an unknown exception vector %d %03x\n",
 469                sprn, sprn);
 470         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 471     }
 472 }
 473 #endif
 474
 475 static inline void vscr_init (CPUPPCState *env, uint32_t val)
 476 {
 477     env->vscr = val;
 478     /* Altivec always uses round-to-nearest */
 479     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 480     set_flush_to_zero(vscr_nj, &env->vec_status);
 481 }
 482
 483 #if defined(CONFIG_USER_ONLY)
 484 #define spr_register(env, num, name, uea_read, uea_write,                     \
 485                      oea_read, oea_write, initial_value)                      \
 486 do {                                                                          \
 487      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
 488 } while (0)
 489 static inline void _spr_register (CPUPPCState *env, int num,
 490                                   const char *name,
 491                                   void (*uea_read)(void *opaque, int gprn, int sprn),
 492                                   void (*uea_write)(void *opaque, int sprn, int gprn),
 493                                   target_ulong initial_value)
 494 #else
 495 static inline void spr_register (CPUPPCState *env, int num,
 496                                  const char *name,
 497                                  void (*uea_read)(void *opaque, int gprn, int sprn),
 498                                  void (*uea_write)(void *opaque, int sprn, int gprn),
 499                                  void (*oea_read)(void *opaque, int gprn, int sprn),
 500                                  void (*oea_write)(void *opaque, int sprn, int gprn),
 501                                  target_ulong initial_value)
 502 #endif
 503 {
 504     ppc_spr_t *spr;
 505
 506     spr = &env->spr_cb[num];
 507     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 508 #if !defined(CONFIG_USER_ONLY)
 509         spr->oea_read != NULL || spr->oea_write != NULL ||
 510 #endif
 511         spr->uea_read != NULL || spr->uea_write != NULL) {
 512         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 513         exit(1);
 514     }
 515 #if defined(PPC_DEBUG_SPR)
 516     printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
 517            initial_value);
 518 #endif
 519     spr->name = name;
 520     spr->uea_read = uea_read;
 521     spr->uea_write = uea_write;
 522 #if !defined(CONFIG_USER_ONLY)
 523     spr->oea_read = oea_read;
 524     spr->oea_write = oea_write;
 525 #endif
 526     env->spr[num] = initial_value;
 527 }
 528
 529 /* Generic PowerPC SPRs */
 530 static void gen_spr_generic (CPUPPCState *env)
 531 {
 532     /* Integer processing */
 533     spr_register(env, SPR_XER, "XER",
 534                  &spr_read_xer, &spr_write_xer,
 535                  &spr_read_xer, &spr_write_xer,
 536                  0x00000000);
 537     /* Branch contol */
 538     spr_register(env, SPR_LR, "LR",
 539                  &spr_read_lr, &spr_write_lr,
 540                  &spr_read_lr, &spr_write_lr,
 541                  0x00000000);
 542     spr_register(env, SPR_CTR, "CTR",
 543                  &spr_read_ctr, &spr_write_ctr,
 544                  &spr_read_ctr, &spr_write_ctr,
 545                  0x00000000);
 546     /* Interrupt processing */
 547     spr_register(env, SPR_SRR0, "SRR0",
 548                  SPR_NOACCESS, SPR_NOACCESS,
 549                  &spr_read_generic, &spr_write_generic,
 550                  0x00000000);
 551     spr_register(env, SPR_SRR1, "SRR1",
 552                  SPR_NOACCESS, SPR_NOACCESS,
 553                  &spr_read_generic, &spr_write_generic,
 554                  0x00000000);
 555     /* Processor control */
 556     spr_register(env, SPR_SPRG0, "SPRG0",
 557                  SPR_NOACCESS, SPR_NOACCESS,
 558                  &spr_read_generic, &spr_write_generic,
 559                  0x00000000);
 560     spr_register(env, SPR_SPRG1, "SPRG1",
 561                  SPR_NOACCESS, SPR_NOACCESS,
 562                  &spr_read_generic, &spr_write_generic,
 563                  0x00000000);
 564     spr_register(env, SPR_SPRG2, "SPRG2",
 565                  SPR_NOACCESS, SPR_NOACCESS,
 566                  &spr_read_generic, &spr_write_generic,
 567                  0x00000000);
 568     spr_register(env, SPR_SPRG3, "SPRG3",
 569                  SPR_NOACCESS, SPR_NOACCESS,
 570                  &spr_read_generic, &spr_write_generic,
 571                  0x00000000);
 572 }
 573
 574 /* SPR common to all non-embedded PowerPC, including 601 */
 575 static void gen_spr_ne_601 (CPUPPCState *env)
 576 {
 577     /* Exception processing */
 578     spr_register(env, SPR_DSISR, "DSISR",
 579                  SPR_NOACCESS, SPR_NOACCESS,
 580                  &spr_read_generic, &spr_write_generic,
 581                  0x00000000);
 582     spr_register(env, SPR_DAR, "DAR",
 583                  SPR_NOACCESS, SPR_NOACCESS,
 584                  &spr_read_generic, &spr_write_generic,
 585                  0x00000000);
 586     /* Timer */
 587     spr_register(env, SPR_DECR, "DECR",
 588                  SPR_NOACCESS, SPR_NOACCESS,
 589                  &spr_read_decr, &spr_write_decr,
 590                  0x00000000);
 591     /* Memory management */
 592     spr_register(env, SPR_SDR1, "SDR1",
 593                  SPR_NOACCESS, SPR_NOACCESS,
 594                  &spr_read_sdr1, &spr_write_sdr1,
 595                  0x00000000);
 596 }
 597
 598 /* BATs 0-3 */
 599 static void gen_low_BATs (CPUPPCState *env)
 600 {
 601 #if !defined(CONFIG_USER_ONLY)
 602     spr_register(env, SPR_IBAT0U, "IBAT0U",
 603                  SPR_NOACCESS, SPR_NOACCESS,
 604                  &spr_read_ibat, &spr_write_ibatu,
 605                  0x00000000);
 606     spr_register(env, SPR_IBAT0L, "IBAT0L",
 607                  SPR_NOACCESS, SPR_NOACCESS,
 608                  &spr_read_ibat, &spr_write_ibatl,
 609                  0x00000000);
 610     spr_register(env, SPR_IBAT1U, "IBAT1U",
 611                  SPR_NOACCESS, SPR_NOACCESS,
 612                  &spr_read_ibat, &spr_write_ibatu,
 613                  0x00000000);
 614     spr_register(env, SPR_IBAT1L, "IBAT1L",
 615                  SPR_NOACCESS, SPR_NOACCESS,
 616                  &spr_read_ibat, &spr_write_ibatl,
 617                  0x00000000);
 618     spr_register(env, SPR_IBAT2U, "IBAT2U",
 619                  SPR_NOACCESS, SPR_NOACCESS,
 620                  &spr_read_ibat, &spr_write_ibatu,
 621                  0x00000000);
 622     spr_register(env, SPR_IBAT2L, "IBAT2L",
 623                  SPR_NOACCESS, SPR_NOACCESS,
 624                  &spr_read_ibat, &spr_write_ibatl,
 625                  0x00000000);
 626     spr_register(env, SPR_IBAT3U, "IBAT3U",
 627                  SPR_NOACCESS, SPR_NOACCESS,
 628                  &spr_read_ibat, &spr_write_ibatu,
 629                  0x00000000);
 630     spr_register(env, SPR_IBAT3L, "IBAT3L",
 631                  SPR_NOACCESS, SPR_NOACCESS,
 632                  &spr_read_ibat, &spr_write_ibatl,
 633                  0x00000000);
 634     spr_register(env, SPR_DBAT0U, "DBAT0U",
 635                  SPR_NOACCESS, SPR_NOACCESS,
 636                  &spr_read_dbat, &spr_write_dbatu,
 637                  0x00000000);
 638     spr_register(env, SPR_DBAT0L, "DBAT0L",
 639                  SPR_NOACCESS, SPR_NOACCESS,
 640                  &spr_read_dbat, &spr_write_dbatl,
 641                  0x00000000);
 642     spr_register(env, SPR_DBAT1U, "DBAT1U",
 643                  SPR_NOACCESS, SPR_NOACCESS,
 644                  &spr_read_dbat, &spr_write_dbatu,
 645                  0x00000000);
 646     spr_register(env, SPR_DBAT1L, "DBAT1L",
 647                  SPR_NOACCESS, SPR_NOACCESS,
 648                  &spr_read_dbat, &spr_write_dbatl,
 649                  0x00000000);
 650     spr_register(env, SPR_DBAT2U, "DBAT2U",
 651                  SPR_NOACCESS, SPR_NOACCESS,
 652                  &spr_read_dbat, &spr_write_dbatu,
 653                  0x00000000);
 654     spr_register(env, SPR_DBAT2L, "DBAT2L",
 655                  SPR_NOACCESS, SPR_NOACCESS,
 656                  &spr_read_dbat, &spr_write_dbatl,
 657                  0x00000000);
 658     spr_register(env, SPR_DBAT3U, "DBAT3U",
 659                  SPR_NOACCESS, SPR_NOACCESS,
 660                  &spr_read_dbat, &spr_write_dbatu,
 661                  0x00000000);
 662     spr_register(env, SPR_DBAT3L, "DBAT3L",
 663                  SPR_NOACCESS, SPR_NOACCESS,
 664                  &spr_read_dbat, &spr_write_dbatl,
 665                  0x00000000);
 666     env->nb_BATs += 4;
 667 #endif
 668 }
 669
 670 /* BATs 4-7 */
 671 static void gen_high_BATs (CPUPPCState *env)
 672 {
 673 #if !defined(CONFIG_USER_ONLY)
 674     spr_register(env, SPR_IBAT4U, "IBAT4U",
 675                  SPR_NOACCESS, SPR_NOACCESS,
 676                  &spr_read_ibat_h, &spr_write_ibatu_h,
 677                  0x00000000);
 678     spr_register(env, SPR_IBAT4L, "IBAT4L",
 679                  SPR_NOACCESS, SPR_NOACCESS,
 680                  &spr_read_ibat_h, &spr_write_ibatl_h,
 681                  0x00000000);
 682     spr_register(env, SPR_IBAT5U, "IBAT5U",
 683                  SPR_NOACCESS, SPR_NOACCESS,
 684                  &spr_read_ibat_h, &spr_write_ibatu_h,
 685                  0x00000000);
 686     spr_register(env, SPR_IBAT5L, "IBAT5L",
 687                  SPR_NOACCESS, SPR_NOACCESS,
 688                  &spr_read_ibat_h, &spr_write_ibatl_h,
 689                  0x00000000);
 690     spr_register(env, SPR_IBAT6U, "IBAT6U",
 691                  SPR_NOACCESS, SPR_NOACCESS,
 692                  &spr_read_ibat_h, &spr_write_ibatu_h,
 693                  0x00000000);
 694     spr_register(env, SPR_IBAT6L, "IBAT6L",
 695                  SPR_NOACCESS, SPR_NOACCESS,
 696                  &spr_read_ibat_h, &spr_write_ibatl_h,
 697                  0x00000000);
 698     spr_register(env, SPR_IBAT7U, "IBAT7U",
 699                  SPR_NOACCESS, SPR_NOACCESS,
 700                  &spr_read_ibat_h, &spr_write_ibatu_h,
 701                  0x00000000);
 702     spr_register(env, SPR_IBAT7L, "IBAT7L",
 703                  SPR_NOACCESS, SPR_NOACCESS,
 704                  &spr_read_ibat_h, &spr_write_ibatl_h,
 705                  0x00000000);
 706     spr_register(env, SPR_DBAT4U, "DBAT4U",
 707                  SPR_NOACCESS, SPR_NOACCESS,
 708                  &spr_read_dbat_h, &spr_write_dbatu_h,
 709                  0x00000000);
 710     spr_register(env, SPR_DBAT4L, "DBAT4L",
 711                  SPR_NOACCESS, SPR_NOACCESS,
 712                  &spr_read_dbat_h, &spr_write_dbatl_h,
 713                  0x00000000);
 714     spr_register(env, SPR_DBAT5U, "DBAT5U",
 715                  SPR_NOACCESS, SPR_NOACCESS,
 716                  &spr_read_dbat_h, &spr_write_dbatu_h,
 717                  0x00000000);
 718     spr_register(env, SPR_DBAT5L, "DBAT5L",
 719                  SPR_NOACCESS, SPR_NOACCESS,
 720                  &spr_read_dbat_h, &spr_write_dbatl_h,
 721                  0x00000000);
 722     spr_register(env, SPR_DBAT6U, "DBAT6U",
 723                  SPR_NOACCESS, SPR_NOACCESS,
 724                  &spr_read_dbat_h, &spr_write_dbatu_h,
 725                  0x00000000);
 726     spr_register(env, SPR_DBAT6L, "DBAT6L",
 727                  SPR_NOACCESS, SPR_NOACCESS,
 728                  &spr_read_dbat_h, &spr_write_dbatl_h,
 729                  0x00000000);
 730     spr_register(env, SPR_DBAT7U, "DBAT7U",
 731                  SPR_NOACCESS, SPR_NOACCESS,
 732                  &spr_read_dbat_h, &spr_write_dbatu_h,
 733                  0x00000000);
 734     spr_register(env, SPR_DBAT7L, "DBAT7L",
 735                  SPR_NOACCESS, SPR_NOACCESS,
 736                  &spr_read_dbat_h, &spr_write_dbatl_h,
 737                  0x00000000);
 738     env->nb_BATs += 4;
 739 #endif
 740 }
 741
 742 /* Generic PowerPC time base */
 743 static void gen_tbl (CPUPPCState *env)
 744 {
 745     spr_register(env, SPR_VTBL,  "TBL",
 746                  &spr_read_tbl, SPR_NOACCESS,
 747                  &spr_read_tbl, SPR_NOACCESS,
 748                  0x00000000);
 749     spr_register(env, SPR_TBL,   "TBL",
 750                  SPR_NOACCESS, SPR_NOACCESS,
 751                  SPR_NOACCESS, &spr_write_tbl,
 752                  0x00000000);
 753     spr_register(env, SPR_VTBU,  "TBU",
 754                  &spr_read_tbu, SPR_NOACCESS,
 755                  &spr_read_tbu, SPR_NOACCESS,
 756                  0x00000000);
 757     spr_register(env, SPR_TBU,   "TBU",
 758                  SPR_NOACCESS, SPR_NOACCESS,
 759                  SPR_NOACCESS, &spr_write_tbu,
 760                  0x00000000);
 761 }
 762
 763 /* Softare table search registers */
 764 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 765 {
 766 #if !defined(CONFIG_USER_ONLY)
 767     env->nb_tlb = nb_tlbs;
 768     env->nb_ways = nb_ways;
 769     env->id_tlbs = 1;
 770     spr_register(env, SPR_DMISS, "DMISS",
 771                  SPR_NOACCESS, SPR_NOACCESS,
 772                  &spr_read_generic, SPR_NOACCESS,
 773                  0x00000000);
 774     spr_register(env, SPR_DCMP, "DCMP",
 775                  SPR_NOACCESS, SPR_NOACCESS,
 776                  &spr_read_generic, SPR_NOACCESS,
 777                  0x00000000);
 778     spr_register(env, SPR_HASH1, "HASH1",
 779                  SPR_NOACCESS, SPR_NOACCESS,
 780                  &spr_read_generic, SPR_NOACCESS,
 781                  0x00000000);
 782     spr_register(env, SPR_HASH2, "HASH2",
 783                  SPR_NOACCESS, SPR_NOACCESS,
 784                  &spr_read_generic, SPR_NOACCESS,
 785                  0x00000000);
 786     spr_register(env, SPR_IMISS, "IMISS",
 787                  SPR_NOACCESS, SPR_NOACCESS,
 788                  &spr_read_generic, SPR_NOACCESS,
 789                  0x00000000);
 790     spr_register(env, SPR_ICMP, "ICMP",
 791                  SPR_NOACCESS, SPR_NOACCESS,
 792                  &spr_read_generic, SPR_NOACCESS,
 793                  0x00000000);
 794     spr_register(env, SPR_RPA, "RPA",
 795                  SPR_NOACCESS, SPR_NOACCESS,
 796                  &spr_read_generic, &spr_write_generic,
 797                  0x00000000);
 798 #endif
 799 }
 800
 801 /* SPR common to MPC755 and G2 */
 802 static void gen_spr_G2_755 (CPUPPCState *env)
 803 {
 804     /* SGPRs */
 805     spr_register(env, SPR_SPRG4, "SPRG4",
 806                  SPR_NOACCESS, SPR_NOACCESS,
 807                  &spr_read_generic, &spr_write_generic,
 808                  0x00000000);
 809     spr_register(env, SPR_SPRG5, "SPRG5",
 810                  SPR_NOACCESS, SPR_NOACCESS,
 811                  &spr_read_generic, &spr_write_generic,
 812                  0x00000000);
 813     spr_register(env, SPR_SPRG6, "SPRG6",
 814                  SPR_NOACCESS, SPR_NOACCESS,
 815                  &spr_read_generic, &spr_write_generic,
 816                  0x00000000);
 817     spr_register(env, SPR_SPRG7, "SPRG7",
 818                  SPR_NOACCESS, SPR_NOACCESS,
 819                  &spr_read_generic, &spr_write_generic,
 820                  0x00000000);
 821 }
 822
 823 /* SPR common to all 7xx PowerPC implementations */
 824 static void gen_spr_7xx (CPUPPCState *env)
 825 {
 826     /* Breakpoints */
 827     /* XXX : not implemented */
 828     spr_register(env, SPR_DABR, "DABR",
 829                  SPR_NOACCESS, SPR_NOACCESS,
 830                  &spr_read_generic, &spr_write_generic,
 831                  0x00000000);
 832     /* XXX : not implemented */
 833     spr_register(env, SPR_IABR, "IABR",
 834                  SPR_NOACCESS, SPR_NOACCESS,
 835                  &spr_read_generic, &spr_write_generic,
 836                  0x00000000);
 837     /* Cache management */
 838     /* XXX : not implemented */
 839     spr_register(env, SPR_ICTC, "ICTC",
 840                  SPR_NOACCESS, SPR_NOACCESS,
 841                  &spr_read_generic, &spr_write_generic,
 842                  0x00000000);
 843     /* Performance monitors */
 844     /* XXX : not implemented */
 845     spr_register(env, SPR_MMCR0, "MMCR0",
 846                  SPR_NOACCESS, SPR_NOACCESS,
 847                  &spr_read_generic, &spr_write_generic,
 848                  0x00000000);
 849     /* XXX : not implemented */
 850     spr_register(env, SPR_MMCR1, "MMCR1",
 851                  SPR_NOACCESS, SPR_NOACCESS,
 852                  &spr_read_generic, &spr_write_generic,
 853                  0x00000000);
 854     /* XXX : not implemented */
 855     spr_register(env, SPR_PMC1, "PMC1",
 856                  SPR_NOACCESS, SPR_NOACCESS,
 857                  &spr_read_generic, &spr_write_generic,
 858                  0x00000000);
 859     /* XXX : not implemented */
 860     spr_register(env, SPR_PMC2, "PMC2",
 861                  SPR_NOACCESS, SPR_NOACCESS,
 862                  &spr_read_generic, &spr_write_generic,
 863                  0x00000000);
 864     /* XXX : not implemented */
 865     spr_register(env, SPR_PMC3, "PMC3",
 866                  SPR_NOACCESS, SPR_NOACCESS,
 867                  &spr_read_generic, &spr_write_generic,
 868                  0x00000000);
 869     /* XXX : not implemented */
 870     spr_register(env, SPR_PMC4, "PMC4",
 871                  SPR_NOACCESS, SPR_NOACCESS,
 872                  &spr_read_generic, &spr_write_generic,
 873                  0x00000000);
 874     /* XXX : not implemented */
 875     spr_register(env, SPR_SIAR, "SIAR",
 876                  SPR_NOACCESS, SPR_NOACCESS,
 877                  &spr_read_generic, SPR_NOACCESS,
 878                  0x00000000);
 879     /* XXX : not implemented */
 880     spr_register(env, SPR_UMMCR0, "UMMCR0",
 881                  &spr_read_ureg, SPR_NOACCESS,
 882                  &spr_read_ureg, SPR_NOACCESS,
 883                  0x00000000);
 884     /* XXX : not implemented */
 885     spr_register(env, SPR_UMMCR1, "UMMCR1",
 886                  &spr_read_ureg, SPR_NOACCESS,
 887                  &spr_read_ureg, SPR_NOACCESS,
 888                  0x00000000);
 889     /* XXX : not implemented */
 890     spr_register(env, SPR_UPMC1, "UPMC1",
 891                  &spr_read_ureg, SPR_NOACCESS,
 892                  &spr_read_ureg, SPR_NOACCESS,
 893                  0x00000000);
 894     /* XXX : not implemented */
 895     spr_register(env, SPR_UPMC2, "UPMC2",
 896                  &spr_read_ureg, SPR_NOACCESS,
 897                  &spr_read_ureg, SPR_NOACCESS,
 898                  0x00000000);
 899     /* XXX : not implemented */
 900     spr_register(env, SPR_UPMC3, "UPMC3",
 901                  &spr_read_ureg, SPR_NOACCESS,
 902                  &spr_read_ureg, SPR_NOACCESS,
 903                  0x00000000);
 904     /* XXX : not implemented */
 905     spr_register(env, SPR_UPMC4, "UPMC4",
 906                  &spr_read_ureg, SPR_NOACCESS,
 907                  &spr_read_ureg, SPR_NOACCESS,
 908                  0x00000000);
 909     /* XXX : not implemented */
 910     spr_register(env, SPR_USIAR, "USIAR",
 911                  &spr_read_ureg, SPR_NOACCESS,
 912                  &spr_read_ureg, SPR_NOACCESS,
 913                  0x00000000);
 914     /* External access control */
 915     /* XXX : not implemented */
 916     spr_register(env, SPR_EAR, "EAR",
 917                  SPR_NOACCESS, SPR_NOACCESS,
 918                  &spr_read_generic, &spr_write_generic,
 919                  0x00000000);
 920 }
 921
 922 static void gen_spr_thrm (CPUPPCState *env)
 923 {
 924     /* Thermal management */
 925     /* XXX : not implemented */
 926     spr_register(env, SPR_THRM1, "THRM1",
 927                  SPR_NOACCESS, SPR_NOACCESS,
 928                  &spr_read_generic, &spr_write_generic,
 929                  0x00000000);
 930     /* XXX : not implemented */
 931     spr_register(env, SPR_THRM2, "THRM2",
 932                  SPR_NOACCESS, SPR_NOACCESS,
 933                  &spr_read_generic, &spr_write_generic,
 934                  0x00000000);
 935     /* XXX : not implemented */
 936     spr_register(env, SPR_THRM3, "THRM3",
 937                  SPR_NOACCESS, SPR_NOACCESS,
 938                  &spr_read_generic, &spr_write_generic,
 939                  0x00000000);
 940 }
 941
 942 /* SPR specific to PowerPC 604 implementation */
 943 static void gen_spr_604 (CPUPPCState *env)
 944 {
 945     /* Processor identification */
 946     spr_register(env, SPR_PIR, "PIR",
 947                  SPR_NOACCESS, SPR_NOACCESS,
 948                  &spr_read_generic, &spr_write_pir,
 949                  0x00000000);
 950     /* Breakpoints */
 951     /* XXX : not implemented */
 952     spr_register(env, SPR_IABR, "IABR",
 953                  SPR_NOACCESS, SPR_NOACCESS,
 954                  &spr_read_generic, &spr_write_generic,
 955                  0x00000000);
 956     /* XXX : not implemented */
 957     spr_register(env, SPR_DABR, "DABR",
 958                  SPR_NOACCESS, SPR_NOACCESS,
 959                  &spr_read_generic, &spr_write_generic,
 960                  0x00000000);
 961     /* Performance counters */
 962     /* XXX : not implemented */
 963     spr_register(env, SPR_MMCR0, "MMCR0",
 964                  SPR_NOACCESS, SPR_NOACCESS,
 965                  &spr_read_generic, &spr_write_generic,
 966                  0x00000000);
 967     /* XXX : not implemented */
 968     spr_register(env, SPR_PMC1, "PMC1",
 969                  SPR_NOACCESS, SPR_NOACCESS,
 970                  &spr_read_generic, &spr_write_generic,
 971                  0x00000000);
 972     /* XXX : not implemented */
 973     spr_register(env, SPR_PMC2, "PMC2",
 974                  SPR_NOACCESS, SPR_NOACCESS,
 975                  &spr_read_generic, &spr_write_generic,
 976                  0x00000000);
 977     /* XXX : not implemented */
 978     spr_register(env, SPR_SIAR, "SIAR",
 979                  SPR_NOACCESS, SPR_NOACCESS,
 980                  &spr_read_generic, SPR_NOACCESS,
 981                  0x00000000);
 982     /* XXX : not implemented */
 983     spr_register(env, SPR_SDA, "SDA",
 984                  SPR_NOACCESS, SPR_NOACCESS,
 985                  &spr_read_generic, SPR_NOACCESS,
 986                  0x00000000);
 987     /* External access control */
 988     /* XXX : not implemented */
 989     spr_register(env, SPR_EAR, "EAR",
 990                  SPR_NOACCESS, SPR_NOACCESS,
 991                  &spr_read_generic, &spr_write_generic,
 992                  0x00000000);
 993 }
 994
 995 /* SPR specific to PowerPC 603 implementation */
 996 static void gen_spr_603 (CPUPPCState *env)
 997 {
 998     /* External access control */
 999     /* XXX : not implemented */
1000     spr_register(env, SPR_EAR, "EAR",
1001                  SPR_NOACCESS, SPR_NOACCESS,
1002                  &spr_read_generic, &spr_write_generic,
1003                  0x00000000);
1004 }
1005
1006 /* SPR specific to PowerPC G2 implementation */
1007 static void gen_spr_G2 (CPUPPCState *env)
1008 {
1009     /* Memory base address */
1010     /* MBAR */
1011     /* XXX : not implemented */
1012     spr_register(env, SPR_MBAR, "MBAR",
1013                  SPR_NOACCESS, SPR_NOACCESS,
1014                  &spr_read_generic, &spr_write_generic,
1015                  0x00000000);
1016     /* Exception processing */
1017     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1018                  SPR_NOACCESS, SPR_NOACCESS,
1019                  &spr_read_generic, &spr_write_generic,
1020                  0x00000000);
1021     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1022                  SPR_NOACCESS, SPR_NOACCESS,
1023                  &spr_read_generic, &spr_write_generic,
1024                  0x00000000);
1025     /* Breakpoints */
1026     /* XXX : not implemented */
1027     spr_register(env, SPR_DABR, "DABR",
1028                  SPR_NOACCESS, SPR_NOACCESS,
1029                  &spr_read_generic, &spr_write_generic,
1030                  0x00000000);
1031     /* XXX : not implemented */
1032     spr_register(env, SPR_DABR2, "DABR2",
1033                  SPR_NOACCESS, SPR_NOACCESS,
1034                  &spr_read_generic, &spr_write_generic,
1035                  0x00000000);
1036     /* XXX : not implemented */
1037     spr_register(env, SPR_IABR, "IABR",
1038                  SPR_NOACCESS, SPR_NOACCESS,
1039                  &spr_read_generic, &spr_write_generic,
1040                  0x00000000);
1041     /* XXX : not implemented */
1042     spr_register(env, SPR_IABR2, "IABR2",
1043                  SPR_NOACCESS, SPR_NOACCESS,
1044                  &spr_read_generic, &spr_write_generic,
1045                  0x00000000);
1046     /* XXX : not implemented */
1047     spr_register(env, SPR_IBCR, "IBCR",
1048                  SPR_NOACCESS, SPR_NOACCESS,
1049                  &spr_read_generic, &spr_write_generic,
1050                  0x00000000);
1051     /* XXX : not implemented */
1052     spr_register(env, SPR_DBCR, "DBCR",
1053                  SPR_NOACCESS, SPR_NOACCESS,
1054                  &spr_read_generic, &spr_write_generic,
1055                  0x00000000);
1056 }
1057
1058 /* SPR specific to PowerPC 602 implementation */
1059 static void gen_spr_602 (CPUPPCState *env)
1060 {
1061     /* ESA registers */
1062     /* XXX : not implemented */
1063     spr_register(env, SPR_SER, "SER",
1064                  SPR_NOACCESS, SPR_NOACCESS,
1065                  &spr_read_generic, &spr_write_generic,
1066                  0x00000000);
1067     /* XXX : not implemented */
1068     spr_register(env, SPR_SEBR, "SEBR",
1069                  SPR_NOACCESS, SPR_NOACCESS,
1070                  &spr_read_generic, &spr_write_generic,
1071                  0x00000000);
1072     /* XXX : not implemented */
1073     spr_register(env, SPR_ESASRR, "ESASRR",
1074                  SPR_NOACCESS, SPR_NOACCESS,
1075                  &spr_read_generic, &spr_write_generic,
1076                  0x00000000);
1077     /* Floating point status */
1078     /* XXX : not implemented */
1079     spr_register(env, SPR_SP, "SP",
1080                  SPR_NOACCESS, SPR_NOACCESS,
1081                  &spr_read_generic, &spr_write_generic,
1082                  0x00000000);
1083     /* XXX : not implemented */
1084     spr_register(env, SPR_LT, "LT",
1085                  SPR_NOACCESS, SPR_NOACCESS,
1086                  &spr_read_generic, &spr_write_generic,
1087                  0x00000000);
1088     /* Watchdog timer */
1089     /* XXX : not implemented */
1090     spr_register(env, SPR_TCR, "TCR",
1091                  SPR_NOACCESS, SPR_NOACCESS,
1092                  &spr_read_generic, &spr_write_generic,
1093                  0x00000000);
1094     /* Interrupt base */
1095     spr_register(env, SPR_IBR, "IBR",
1096                  SPR_NOACCESS, SPR_NOACCESS,
1097                  &spr_read_generic, &spr_write_generic,
1098                  0x00000000);
1099     /* XXX : not implemented */
1100     spr_register(env, SPR_IABR, "IABR",
1101                  SPR_NOACCESS, SPR_NOACCESS,
1102                  &spr_read_generic, &spr_write_generic,
1103                  0x00000000);
1104 }
1105
1106 /* SPR specific to PowerPC 601 implementation */
1107 static void gen_spr_601 (CPUPPCState *env)
1108 {
1109     /* Multiplication/division register */
1110     /* MQ */
1111     spr_register(env, SPR_MQ, "MQ",
1112                  &spr_read_generic, &spr_write_generic,
1113                  &spr_read_generic, &spr_write_generic,
1114                  0x00000000);
1115     /* RTC registers */
1116     spr_register(env, SPR_601_RTCU, "RTCU",
1117                  SPR_NOACCESS, SPR_NOACCESS,
1118                  SPR_NOACCESS, &spr_write_601_rtcu,
1119                  0x00000000);
1120     spr_register(env, SPR_601_VRTCU, "RTCU",
1121                  &spr_read_601_rtcu, SPR_NOACCESS,
1122                  &spr_read_601_rtcu, SPR_NOACCESS,
1123                  0x00000000);
1124     spr_register(env, SPR_601_RTCL, "RTCL",
1125                  SPR_NOACCESS, SPR_NOACCESS,
1126                  SPR_NOACCESS, &spr_write_601_rtcl,
1127                  0x00000000);
1128     spr_register(env, SPR_601_VRTCL, "RTCL",
1129                  &spr_read_601_rtcl, SPR_NOACCESS,
1130                  &spr_read_601_rtcl, SPR_NOACCESS,
1131                  0x00000000);
1132     /* Timer */
1133 #if 0 /* ? */
1134     spr_register(env, SPR_601_UDECR, "UDECR",
1135                  &spr_read_decr, SPR_NOACCESS,
1136                  &spr_read_decr, SPR_NOACCESS,
1137                  0x00000000);
1138 #endif
1139     /* External access control */
1140     /* XXX : not implemented */
1141     spr_register(env, SPR_EAR, "EAR",
1142                  SPR_NOACCESS, SPR_NOACCESS,
1143                  &spr_read_generic, &spr_write_generic,
1144                  0x00000000);
1145     /* Memory management */
1146 #if !defined(CONFIG_USER_ONLY)
1147     spr_register(env, SPR_IBAT0U, "IBAT0U",
1148                  SPR_NOACCESS, SPR_NOACCESS,
1149                  &spr_read_601_ubat, &spr_write_601_ubatu,
1150                  0x00000000);
1151     spr_register(env, SPR_IBAT0L, "IBAT0L",
1152                  SPR_NOACCESS, SPR_NOACCESS,
1153                  &spr_read_601_ubat, &spr_write_601_ubatl,
1154                  0x00000000);
1155     spr_register(env, SPR_IBAT1U, "IBAT1U",
1156                  SPR_NOACCESS, SPR_NOACCESS,
1157                  &spr_read_601_ubat, &spr_write_601_ubatu,
1158                  0x00000000);
1159     spr_register(env, SPR_IBAT1L, "IBAT1L",
1160                  SPR_NOACCESS, SPR_NOACCESS,
1161                  &spr_read_601_ubat, &spr_write_601_ubatl,
1162                  0x00000000);
1163     spr_register(env, SPR_IBAT2U, "IBAT2U",
1164                  SPR_NOACCESS, SPR_NOACCESS,
1165                  &spr_read_601_ubat, &spr_write_601_ubatu,
1166                  0x00000000);
1167     spr_register(env, SPR_IBAT2L, "IBAT2L",
1168                  SPR_NOACCESS, SPR_NOACCESS,
1169                  &spr_read_601_ubat, &spr_write_601_ubatl,
1170                  0x00000000);
1171     spr_register(env, SPR_IBAT3U, "IBAT3U",
1172                  SPR_NOACCESS, SPR_NOACCESS,
1173                  &spr_read_601_ubat, &spr_write_601_ubatu,
1174                  0x00000000);
1175     spr_register(env, SPR_IBAT3L, "IBAT3L",
1176                  SPR_NOACCESS, SPR_NOACCESS,
1177                  &spr_read_601_ubat, &spr_write_601_ubatl,
1178                  0x00000000);
1179     env->nb_BATs = 4;
1180 #endif
1181 }
1182
1183 static void gen_spr_74xx (CPUPPCState *env)
1184 {
1185     /* Processor identification */
1186     spr_register(env, SPR_PIR, "PIR",
1187                  SPR_NOACCESS, SPR_NOACCESS,
1188                  &spr_read_generic, &spr_write_pir,
1189                  0x00000000);
1190     /* XXX : not implemented */
1191     spr_register(env, SPR_MMCR2, "MMCR2",
1192                  SPR_NOACCESS, SPR_NOACCESS,
1193                  &spr_read_generic, &spr_write_generic,
1194                  0x00000000);
1195     /* XXX : not implemented */
1196     spr_register(env, SPR_UMMCR2, "UMMCR2",
1197                  &spr_read_ureg, SPR_NOACCESS,
1198                  &spr_read_ureg, SPR_NOACCESS,
1199                  0x00000000);
1200     /* XXX: not implemented */
1201     spr_register(env, SPR_BAMR, "BAMR",
1202                  SPR_NOACCESS, SPR_NOACCESS,
1203                  &spr_read_generic, &spr_write_generic,
1204                  0x00000000);
1205     /* XXX : not implemented */
1206     spr_register(env, SPR_MSSCR0, "MSSCR0",
1207                  SPR_NOACCESS, SPR_NOACCESS,
1208                  &spr_read_generic, &spr_write_generic,
1209                  0x00000000);
1210     /* Hardware implementation registers */
1211     /* XXX : not implemented */
1212     spr_register(env, SPR_HID0, "HID0",
1213                  SPR_NOACCESS, SPR_NOACCESS,
1214                  &spr_read_generic, &spr_write_generic,
1215                  0x00000000);
1216     /* XXX : not implemented */
1217     spr_register(env, SPR_HID1, "HID1",
1218                  SPR_NOACCESS, SPR_NOACCESS,
1219                  &spr_read_generic, &spr_write_generic,
1220                  0x00000000);
1221     /* Altivec */
1222     spr_register(env, SPR_VRSAVE, "VRSAVE",
1223                  &spr_read_generic, &spr_write_generic,
1224                  &spr_read_generic, &spr_write_generic,
1225                  0x00000000);
1226     /* XXX : not implemented */
1227     spr_register(env, SPR_L2CR, "L2CR",
1228                  SPR_NOACCESS, SPR_NOACCESS,
1229                  &spr_read_generic, &spr_write_generic,
1230                  0x00000000);
1231     /* Not strictly an SPR */
1232     vscr_init(env, 0x00010000);
1233 }
1234
1235 static void gen_l3_ctrl (CPUPPCState *env)
1236 {
1237     /* L3CR */
1238     /* XXX : not implemented */
1239     spr_register(env, SPR_L3CR, "L3CR",
1240                  SPR_NOACCESS, SPR_NOACCESS,
1241                  &spr_read_generic, &spr_write_generic,
1242                  0x00000000);
1243     /* L3ITCR0 */
1244     /* XXX : not implemented */
1245     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1246                  SPR_NOACCESS, SPR_NOACCESS,
1247                  &spr_read_generic, &spr_write_generic,
1248                  0x00000000);
1249     /* L3PM */
1250     /* XXX : not implemented */
1251     spr_register(env, SPR_L3PM, "L3PM",
1252                  SPR_NOACCESS, SPR_NOACCESS,
1253                  &spr_read_generic, &spr_write_generic,
1254                  0x00000000);
1255 }
1256
1257 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1258 {
1259 #if !defined(CONFIG_USER_ONLY)
1260     env->nb_tlb = nb_tlbs;
1261     env->nb_ways = nb_ways;
1262     env->id_tlbs = 1;
1263     /* XXX : not implemented */
1264     spr_register(env, SPR_PTEHI, "PTEHI",
1265                  SPR_NOACCESS, SPR_NOACCESS,
1266                  &spr_read_generic, &spr_write_generic,
1267                  0x00000000);
1268     /* XXX : not implemented */
1269     spr_register(env, SPR_PTELO, "PTELO",
1270                  SPR_NOACCESS, SPR_NOACCESS,
1271                  &spr_read_generic, &spr_write_generic,
1272                  0x00000000);
1273     /* XXX : not implemented */
1274     spr_register(env, SPR_TLBMISS, "TLBMISS",
1275                  SPR_NOACCESS, SPR_NOACCESS,
1276                  &spr_read_generic, &spr_write_generic,
1277                  0x00000000);
1278 #endif
1279 }
1280
1281 static void gen_spr_usprgh (CPUPPCState *env)
1282 {
1283     spr_register(env, SPR_USPRG4, "USPRG4",
1284                  &spr_read_ureg, SPR_NOACCESS,
1285                  &spr_read_ureg, SPR_NOACCESS,
1286                  0x00000000);
1287     spr_register(env, SPR_USPRG5, "USPRG5",
1288                  &spr_read_ureg, SPR_NOACCESS,
1289                  &spr_read_ureg, SPR_NOACCESS,
1290                  0x00000000);
1291     spr_register(env, SPR_USPRG6, "USPRG6",
1292                  &spr_read_ureg, SPR_NOACCESS,
1293                  &spr_read_ureg, SPR_NOACCESS,
1294                  0x00000000);
1295     spr_register(env, SPR_USPRG7, "USPRG7",
1296                  &spr_read_ureg, SPR_NOACCESS,
1297                  &spr_read_ureg, SPR_NOACCESS,
1298                  0x00000000);
1299 }
1300
1301 /* PowerPC BookE SPR */
1302 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1303 {
1304     const char *ivor_names[64] = {
1305         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1306         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1307         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1308         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1309         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1310         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1311         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1312         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1313         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1314         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1315         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1316         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1317         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1318         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1319         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1320         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1321     };
1322 #define SPR_BOOKE_IVORxx (-1)
1323     int ivor_sprn[64] = {
1324         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1325         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1326         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1327         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1328         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1329         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1330         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1331         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1332         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1333         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1334         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1335         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1336         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1337         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1338         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1339         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1340     };
1341     int i;
1342
1343     /* Interrupt processing */
1344     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1345                  SPR_NOACCESS, SPR_NOACCESS,
1346                  &spr_read_generic, &spr_write_generic,
1347                  0x00000000);
1348     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1349                  SPR_NOACCESS, SPR_NOACCESS,
1350                  &spr_read_generic, &spr_write_generic,
1351                  0x00000000);
1352     /* Debug */
1353     /* XXX : not implemented */
1354     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1355                  SPR_NOACCESS, SPR_NOACCESS,
1356                  &spr_read_generic, &spr_write_generic,
1357                  0x00000000);
1358     /* XXX : not implemented */
1359     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1360                  SPR_NOACCESS, SPR_NOACCESS,
1361                  &spr_read_generic, &spr_write_generic,
1362                  0x00000000);
1363     /* XXX : not implemented */
1364     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1365                  SPR_NOACCESS, SPR_NOACCESS,
1366                  &spr_read_generic, &spr_write_generic,
1367                  0x00000000);
1368     /* XXX : not implemented */
1369     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1370                  SPR_NOACCESS, SPR_NOACCESS,
1371                  &spr_read_generic, &spr_write_generic,
1372                  0x00000000);
1373     /* XXX : not implemented */
1374     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1375                  SPR_NOACCESS, SPR_NOACCESS,
1376                  &spr_read_generic, &spr_write_generic,
1377                  0x00000000);
1378     /* XXX : not implemented */
1379     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1380                  SPR_NOACCESS, SPR_NOACCESS,
1381                  &spr_read_generic, &spr_write_generic,
1382                  0x00000000);
1383     /* XXX : not implemented */
1384     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1385                  SPR_NOACCESS, SPR_NOACCESS,
1386                  &spr_read_generic, &spr_write_generic,
1387                  0x00000000);
1388     /* XXX : not implemented */
1389     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1390                  SPR_NOACCESS, SPR_NOACCESS,
1391                  &spr_read_generic, &spr_write_clear,
1392                  0x00000000);
1393     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1394                  SPR_NOACCESS, SPR_NOACCESS,
1395                  &spr_read_generic, &spr_write_generic,
1396                  0x00000000);
1397     spr_register(env, SPR_BOOKE_ESR, "ESR",
1398                  SPR_NOACCESS, SPR_NOACCESS,
1399                  &spr_read_generic, &spr_write_generic,
1400                  0x00000000);
1401     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1402                  SPR_NOACCESS, SPR_NOACCESS,
1403                  &spr_read_generic, &spr_write_excp_prefix,
1404                  0x00000000);
1405     /* Exception vectors */
1406     for (i = 0; i < 64; i++) {
1407         if (ivor_mask & (1ULL << i)) {
1408             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1409                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1410                 exit(1);
1411             }
1412             spr_register(env, ivor_sprn[i], ivor_names[i],
1413                          SPR_NOACCESS, SPR_NOACCESS,
1414                          &spr_read_generic, &spr_write_excp_vector,
1415                          0x00000000);
1416         }
1417     }
1418     spr_register(env, SPR_BOOKE_PID, "PID",
1419                  SPR_NOACCESS, SPR_NOACCESS,
1420                  &spr_read_generic, &spr_write_generic,
1421                  0x00000000);
1422     spr_register(env, SPR_BOOKE_TCR, "TCR",
1423                  SPR_NOACCESS, SPR_NOACCESS,
1424                  &spr_read_generic, &spr_write_booke_tcr,
1425                  0x00000000);
1426     spr_register(env, SPR_BOOKE_TSR, "TSR",
1427                  SPR_NOACCESS, SPR_NOACCESS,
1428                  &spr_read_generic, &spr_write_booke_tsr,
1429                  0x00000000);
1430     /* Timer */
1431     spr_register(env, SPR_DECR, "DECR",
1432                  SPR_NOACCESS, SPR_NOACCESS,
1433                  &spr_read_decr, &spr_write_decr,
1434                  0x00000000);
1435     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1436                  SPR_NOACCESS, SPR_NOACCESS,
1437                  SPR_NOACCESS, &spr_write_generic,
1438                  0x00000000);
1439     /* SPRGs */
1440     spr_register(env, SPR_USPRG0, "USPRG0",
1441                  &spr_read_generic, &spr_write_generic,
1442                  &spr_read_generic, &spr_write_generic,
1443                  0x00000000);
1444     spr_register(env, SPR_SPRG4, "SPRG4",
1445                  SPR_NOACCESS, SPR_NOACCESS,
1446                  &spr_read_generic, &spr_write_generic,
1447                  0x00000000);
1448     spr_register(env, SPR_SPRG5, "SPRG5",
1449                  SPR_NOACCESS, SPR_NOACCESS,
1450                  &spr_read_generic, &spr_write_generic,
1451                  0x00000000);
1452     spr_register(env, SPR_SPRG6, "SPRG6",
1453                  SPR_NOACCESS, SPR_NOACCESS,
1454                  &spr_read_generic, &spr_write_generic,
1455                  0x00000000);
1456     spr_register(env, SPR_SPRG7, "SPRG7",
1457                  SPR_NOACCESS, SPR_NOACCESS,
1458                  &spr_read_generic, &spr_write_generic,
1459                  0x00000000);
1460 }
1461
1462 /* FSL storage control registers */
1463 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1464 {
1465 #if !defined(CONFIG_USER_ONLY)
1466     const char *mas_names[8] = {
1467         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1468     };
1469     int mas_sprn[8] = {
1470         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1471         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1472     };
1473     int i;
1474
1475     /* TLB assist registers */
1476     /* XXX : not implemented */
1477     for (i = 0; i < 8; i++) {
1478         if (mas_mask & (1 << i)) {
1479             spr_register(env, mas_sprn[i], mas_names[i],
1480                          SPR_NOACCESS, SPR_NOACCESS,
1481                          &spr_read_generic, &spr_write_generic,
1482                          0x00000000);
1483         }
1484     }
1485     if (env->nb_pids > 1) {
1486         /* XXX : not implemented */
1487         spr_register(env, SPR_BOOKE_PID1, "PID1",
1488                      SPR_NOACCESS, SPR_NOACCESS,
1489                      &spr_read_generic, &spr_write_generic,
1490                      0x00000000);
1491     }
1492     if (env->nb_pids > 2) {
1493         /* XXX : not implemented */
1494         spr_register(env, SPR_BOOKE_PID2, "PID2",
1495                      SPR_NOACCESS, SPR_NOACCESS,
1496                      &spr_read_generic, &spr_write_generic,
1497                      0x00000000);
1498     }
1499     /* XXX : not implemented */
1500     spr_register(env, SPR_MMUCFG, "MMUCFG",
1501                  SPR_NOACCESS, SPR_NOACCESS,
1502                  &spr_read_generic, SPR_NOACCESS,
1503                  0x00000000); /* TOFIX */
1504     /* XXX : not implemented */
1505     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1506                  SPR_NOACCESS, SPR_NOACCESS,
1507                  &spr_read_generic, &spr_write_generic,
1508                  0x00000000); /* TOFIX */
1509     switch (env->nb_ways) {
1510     case 4:
1511         /* XXX : not implemented */
1512         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1513                      SPR_NOACCESS, SPR_NOACCESS,
1514                      &spr_read_generic, SPR_NOACCESS,
1515                      0x00000000); /* TOFIX */
1516         /* Fallthru */
1517     case 3:
1518         /* XXX : not implemented */
1519         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1520                      SPR_NOACCESS, SPR_NOACCESS,
1521                      &spr_read_generic, SPR_NOACCESS,
1522                      0x00000000); /* TOFIX */
1523         /* Fallthru */
1524     case 2:
1525         /* XXX : not implemented */
1526         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1527                      SPR_NOACCESS, SPR_NOACCESS,
1528                      &spr_read_generic, SPR_NOACCESS,
1529                      0x00000000); /* TOFIX */
1530         /* Fallthru */
1531     case 1:
1532         /* XXX : not implemented */
1533         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1534                      SPR_NOACCESS, SPR_NOACCESS,
1535                      &spr_read_generic, SPR_NOACCESS,
1536                      0x00000000); /* TOFIX */
1537         /* Fallthru */
1538     case 0:
1539     default:
1540         break;
1541     }
1542 #endif
1543 }
1544
1545 /* SPR specific to PowerPC 440 implementation */
1546 static void gen_spr_440 (CPUPPCState *env)
1547 {
1548     /* Cache control */
1549     /* XXX : not implemented */
1550     spr_register(env, SPR_440_DNV0, "DNV0",
1551                  SPR_NOACCESS, SPR_NOACCESS,
1552                  &spr_read_generic, &spr_write_generic,
1553                  0x00000000);
1554     /* XXX : not implemented */
1555     spr_register(env, SPR_440_DNV1, "DNV1",
1556                  SPR_NOACCESS, SPR_NOACCESS,
1557                  &spr_read_generic, &spr_write_generic,
1558                  0x00000000);
1559     /* XXX : not implemented */
1560     spr_register(env, SPR_440_DNV2, "DNV2",
1561                  SPR_NOACCESS, SPR_NOACCESS,
1562                  &spr_read_generic, &spr_write_generic,
1563                  0x00000000);
1564     /* XXX : not implemented */
1565     spr_register(env, SPR_440_DNV3, "DNV3",
1566                  SPR_NOACCESS, SPR_NOACCESS,
1567                  &spr_read_generic, &spr_write_generic,
1568                  0x00000000);
1569     /* XXX : not implemented */
1570     spr_register(env, SPR_440_DTV0, "DTV0",
1571                  SPR_NOACCESS, SPR_NOACCESS,
1572                  &spr_read_generic, &spr_write_generic,
1573                  0x00000000);
1574     /* XXX : not implemented */
1575     spr_register(env, SPR_440_DTV1, "DTV1",
1576                  SPR_NOACCESS, SPR_NOACCESS,
1577                  &spr_read_generic, &spr_write_generic,
1578                  0x00000000);
1579     /* XXX : not implemented */
1580     spr_register(env, SPR_440_DTV2, "DTV2",
1581                  SPR_NOACCESS, SPR_NOACCESS,
1582                  &spr_read_generic, &spr_write_generic,
1583                  0x00000000);
1584     /* XXX : not implemented */
1585     spr_register(env, SPR_440_DTV3, "DTV3",
1586                  SPR_NOACCESS, SPR_NOACCESS,
1587                  &spr_read_generic, &spr_write_generic,
1588                  0x00000000);
1589     /* XXX : not implemented */
1590     spr_register(env, SPR_440_DVLIM, "DVLIM",
1591                  SPR_NOACCESS, SPR_NOACCESS,
1592                  &spr_read_generic, &spr_write_generic,
1593                  0x00000000);
1594     /* XXX : not implemented */
1595     spr_register(env, SPR_440_INV0, "INV0",
1596                  SPR_NOACCESS, SPR_NOACCESS,
1597                  &spr_read_generic, &spr_write_generic,
1598                  0x00000000);
1599     /* XXX : not implemented */
1600     spr_register(env, SPR_440_INV1, "INV1",
1601                  SPR_NOACCESS, SPR_NOACCESS,
1602                  &spr_read_generic, &spr_write_generic,
1603                  0x00000000);
1604     /* XXX : not implemented */
1605     spr_register(env, SPR_440_INV2, "INV2",
1606                  SPR_NOACCESS, SPR_NOACCESS,
1607                  &spr_read_generic, &spr_write_generic,
1608                  0x00000000);
1609     /* XXX : not implemented */
1610     spr_register(env, SPR_440_INV3, "INV3",
1611                  SPR_NOACCESS, SPR_NOACCESS,
1612                  &spr_read_generic, &spr_write_generic,
1613                  0x00000000);
1614     /* XXX : not implemented */
1615     spr_register(env, SPR_440_ITV0, "ITV0",
1616                  SPR_NOACCESS, SPR_NOACCESS,
1617                  &spr_read_generic, &spr_write_generic,
1618                  0x00000000);
1619     /* XXX : not implemented */
1620     spr_register(env, SPR_440_ITV1, "ITV1",
1621                  SPR_NOACCESS, SPR_NOACCESS,
1622                  &spr_read_generic, &spr_write_generic,
1623                  0x00000000);
1624     /* XXX : not implemented */
1625     spr_register(env, SPR_440_ITV2, "ITV2",
1626                  SPR_NOACCESS, SPR_NOACCESS,
1627                  &spr_read_generic, &spr_write_generic,
1628                  0x00000000);
1629     /* XXX : not implemented */
1630     spr_register(env, SPR_440_ITV3, "ITV3",
1631                  SPR_NOACCESS, SPR_NOACCESS,
1632                  &spr_read_generic, &spr_write_generic,
1633                  0x00000000);
1634     /* XXX : not implemented */
1635     spr_register(env, SPR_440_IVLIM, "IVLIM",
1636                  SPR_NOACCESS, SPR_NOACCESS,
1637                  &spr_read_generic, &spr_write_generic,
1638                  0x00000000);
1639     /* Cache debug */
1640     /* XXX : not implemented */
1641     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1642                  SPR_NOACCESS, SPR_NOACCESS,
1643                  &spr_read_generic, SPR_NOACCESS,
1644                  0x00000000);
1645     /* XXX : not implemented */
1646     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1647                  SPR_NOACCESS, SPR_NOACCESS,
1648                  &spr_read_generic, SPR_NOACCESS,
1649                  0x00000000);
1650     /* XXX : not implemented */
1651     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1652                  SPR_NOACCESS, SPR_NOACCESS,
1653                  &spr_read_generic, SPR_NOACCESS,
1654                  0x00000000);
1655     /* XXX : not implemented */
1656     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1657                  SPR_NOACCESS, SPR_NOACCESS,
1658                  &spr_read_generic, SPR_NOACCESS,
1659                  0x00000000);
1660     /* XXX : not implemented */
1661     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1662                  SPR_NOACCESS, SPR_NOACCESS,
1663                  &spr_read_generic, SPR_NOACCESS,
1664                  0x00000000);
1665     /* XXX : not implemented */
1666     spr_register(env, SPR_440_DBDR, "DBDR",
1667                  SPR_NOACCESS, SPR_NOACCESS,
1668                  &spr_read_generic, &spr_write_generic,
1669                  0x00000000);
1670     /* Processor control */
1671     spr_register(env, SPR_4xx_CCR0, "CCR0",
1672                  SPR_NOACCESS, SPR_NOACCESS,
1673                  &spr_read_generic, &spr_write_generic,
1674                  0x00000000);
1675     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1676                  SPR_NOACCESS, SPR_NOACCESS,
1677                  &spr_read_generic, SPR_NOACCESS,
1678                  0x00000000);
1679     /* Storage control */
1680     spr_register(env, SPR_440_MMUCR, "MMUCR",
1681                  SPR_NOACCESS, SPR_NOACCESS,
1682                  &spr_read_generic, &spr_write_generic,
1683                  0x00000000);
1684 }
1685
1686 /* SPR shared between PowerPC 40x implementations */
1687 static void gen_spr_40x (CPUPPCState *env)
1688 {
1689     /* Cache */
1690     /* not emulated, as Qemu do not emulate caches */
1691     spr_register(env, SPR_40x_DCCR, "DCCR",
1692                  SPR_NOACCESS, SPR_NOACCESS,
1693                  &spr_read_generic, &spr_write_generic,
1694                  0x00000000);
1695     /* not emulated, as Qemu do not emulate caches */
1696     spr_register(env, SPR_40x_ICCR, "ICCR",
1697                  SPR_NOACCESS, SPR_NOACCESS,
1698                  &spr_read_generic, &spr_write_generic,
1699                  0x00000000);
1700     /* not emulated, as Qemu do not emulate caches */
1701     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1702                  SPR_NOACCESS, SPR_NOACCESS,
1703                  &spr_read_generic, SPR_NOACCESS,
1704                  0x00000000);
1705     /* Exception */
1706     spr_register(env, SPR_40x_DEAR, "DEAR",
1707                  SPR_NOACCESS, SPR_NOACCESS,
1708                  &spr_read_generic, &spr_write_generic,
1709                  0x00000000);
1710     spr_register(env, SPR_40x_ESR, "ESR",
1711                  SPR_NOACCESS, SPR_NOACCESS,
1712                  &spr_read_generic, &spr_write_generic,
1713                  0x00000000);
1714     spr_register(env, SPR_40x_EVPR, "EVPR",
1715                  SPR_NOACCESS, SPR_NOACCESS,
1716                  &spr_read_generic, &spr_write_excp_prefix,
1717                  0x00000000);
1718     spr_register(env, SPR_40x_SRR2, "SRR2",
1719                  &spr_read_generic, &spr_write_generic,
1720                  &spr_read_generic, &spr_write_generic,
1721                  0x00000000);
1722     spr_register(env, SPR_40x_SRR3, "SRR3",
1723                  &spr_read_generic, &spr_write_generic,
1724                  &spr_read_generic, &spr_write_generic,
1725                  0x00000000);
1726     /* Timers */
1727     spr_register(env, SPR_40x_PIT, "PIT",
1728                  SPR_NOACCESS, SPR_NOACCESS,
1729                  &spr_read_40x_pit, &spr_write_40x_pit,
1730                  0x00000000);
1731     spr_register(env, SPR_40x_TCR, "TCR",
1732                  SPR_NOACCESS, SPR_NOACCESS,
1733                  &spr_read_generic, &spr_write_booke_tcr,
1734                  0x00000000);
1735     spr_register(env, SPR_40x_TSR, "TSR",
1736                  SPR_NOACCESS, SPR_NOACCESS,
1737                  &spr_read_generic, &spr_write_booke_tsr,
1738                  0x00000000);
1739 }
1740
1741 /* SPR specific to PowerPC 405 implementation */
1742 static void gen_spr_405 (CPUPPCState *env)
1743 {
1744     /* MMU */
1745     spr_register(env, SPR_40x_PID, "PID",
1746                  SPR_NOACCESS, SPR_NOACCESS,
1747                  &spr_read_generic, &spr_write_generic,
1748                  0x00000000);
1749     spr_register(env, SPR_4xx_CCR0, "CCR0",
1750                  SPR_NOACCESS, SPR_NOACCESS,
1751                  &spr_read_generic, &spr_write_generic,
1752                  0x00700000);
1753     /* Debug interface */
1754     /* XXX : not implemented */
1755     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1756                  SPR_NOACCESS, SPR_NOACCESS,
1757                  &spr_read_generic, &spr_write_40x_dbcr0,
1758                  0x00000000);
1759     /* XXX : not implemented */
1760     spr_register(env, SPR_405_DBCR1, "DBCR1",
1761                  SPR_NOACCESS, SPR_NOACCESS,
1762                  &spr_read_generic, &spr_write_generic,
1763                  0x00000000);
1764     /* XXX : not implemented */
1765     spr_register(env, SPR_40x_DBSR, "DBSR",
1766                  SPR_NOACCESS, SPR_NOACCESS,
1767                  &spr_read_generic, &spr_write_clear,
1768                  /* Last reset was system reset */
1769                  0x00000300);
1770     /* XXX : not implemented */
1771     spr_register(env, SPR_40x_DAC1, "DAC1",
1772                  SPR_NOACCESS, SPR_NOACCESS,
1773                  &spr_read_generic, &spr_write_generic,
1774                  0x00000000);
1775     spr_register(env, SPR_40x_DAC2, "DAC2",
1776                  SPR_NOACCESS, SPR_NOACCESS,
1777                  &spr_read_generic, &spr_write_generic,
1778                  0x00000000);
1779     /* XXX : not implemented */
1780     spr_register(env, SPR_405_DVC1, "DVC1",
1781                  SPR_NOACCESS, SPR_NOACCESS,
1782                  &spr_read_generic, &spr_write_generic,
1783                  0x00000000);
1784     /* XXX : not implemented */
1785     spr_register(env, SPR_405_DVC2, "DVC2",
1786                  SPR_NOACCESS, SPR_NOACCESS,
1787                  &spr_read_generic, &spr_write_generic,
1788                  0x00000000);
1789     /* XXX : not implemented */
1790     spr_register(env, SPR_40x_IAC1, "IAC1",
1791                  SPR_NOACCESS, SPR_NOACCESS,
1792                  &spr_read_generic, &spr_write_generic,
1793                  0x00000000);
1794     spr_register(env, SPR_40x_IAC2, "IAC2",
1795                  SPR_NOACCESS, SPR_NOACCESS,
1796                  &spr_read_generic, &spr_write_generic,
1797                  0x00000000);
1798     /* XXX : not implemented */
1799     spr_register(env, SPR_405_IAC3, "IAC3",
1800                  SPR_NOACCESS, SPR_NOACCESS,
1801                  &spr_read_generic, &spr_write_generic,
1802                  0x00000000);
1803     /* XXX : not implemented */
1804     spr_register(env, SPR_405_IAC4, "IAC4",
1805                  SPR_NOACCESS, SPR_NOACCESS,
1806                  &spr_read_generic, &spr_write_generic,
1807                  0x00000000);
1808     /* Storage control */
1809     /* XXX: TODO: not implemented */
1810     spr_register(env, SPR_405_SLER, "SLER",
1811                  SPR_NOACCESS, SPR_NOACCESS,
1812                  &spr_read_generic, &spr_write_40x_sler,
1813                  0x00000000);
1814     spr_register(env, SPR_40x_ZPR, "ZPR",
1815                  SPR_NOACCESS, SPR_NOACCESS,
1816                  &spr_read_generic, &spr_write_generic,
1817                  0x00000000);
1818     /* XXX : not implemented */
1819     spr_register(env, SPR_405_SU0R, "SU0R",
1820                  SPR_NOACCESS, SPR_NOACCESS,
1821                  &spr_read_generic, &spr_write_generic,
1822                  0x00000000);
1823     /* SPRG */
1824     spr_register(env, SPR_USPRG0, "USPRG0",
1825                  &spr_read_ureg, SPR_NOACCESS,
1826                  &spr_read_ureg, SPR_NOACCESS,
1827                  0x00000000);
1828     spr_register(env, SPR_SPRG4, "SPRG4",
1829                  SPR_NOACCESS, SPR_NOACCESS,
1830                  &spr_read_generic, &spr_write_generic,
1831                  0x00000000);
1832     spr_register(env, SPR_SPRG5, "SPRG5",
1833                  SPR_NOACCESS, SPR_NOACCESS,
1834                  spr_read_generic, &spr_write_generic,
1835                  0x00000000);
1836     spr_register(env, SPR_SPRG6, "SPRG6",
1837                  SPR_NOACCESS, SPR_NOACCESS,
1838                  spr_read_generic, &spr_write_generic,
1839                  0x00000000);
1840     spr_register(env, SPR_SPRG7, "SPRG7",
1841                  SPR_NOACCESS, SPR_NOACCESS,
1842                  spr_read_generic, &spr_write_generic,
1843                  0x00000000);
1844     gen_spr_usprgh(env);
1845 }
1846
1847 /* SPR shared between PowerPC 401 & 403 implementations */
1848 static void gen_spr_401_403 (CPUPPCState *env)
1849 {
1850     /* Time base */
1851     spr_register(env, SPR_403_VTBL,  "TBL",
1852                  &spr_read_tbl, SPR_NOACCESS,
1853                  &spr_read_tbl, SPR_NOACCESS,
1854                  0x00000000);
1855     spr_register(env, SPR_403_TBL,   "TBL",
1856                  SPR_NOACCESS, SPR_NOACCESS,
1857                  SPR_NOACCESS, &spr_write_tbl,
1858                  0x00000000);
1859     spr_register(env, SPR_403_VTBU,  "TBU",
1860                  &spr_read_tbu, SPR_NOACCESS,
1861                  &spr_read_tbu, SPR_NOACCESS,
1862                  0x00000000);
1863     spr_register(env, SPR_403_TBU,   "TBU",
1864                  SPR_NOACCESS, SPR_NOACCESS,
1865                  SPR_NOACCESS, &spr_write_tbu,
1866                  0x00000000);
1867     /* Debug */
1868     /* not emulated, as Qemu do not emulate caches */
1869     spr_register(env, SPR_403_CDBCR, "CDBCR",
1870                  SPR_NOACCESS, SPR_NOACCESS,
1871                  &spr_read_generic, &spr_write_generic,
1872                  0x00000000);
1873 }
1874
1875 /* SPR specific to PowerPC 401 implementation */
1876 static void gen_spr_401 (CPUPPCState *env)
1877 {
1878     /* Debug interface */
1879     /* XXX : not implemented */
1880     spr_register(env, SPR_40x_DBCR0, "DBCR",
1881                  SPR_NOACCESS, SPR_NOACCESS,
1882                  &spr_read_generic, &spr_write_40x_dbcr0,
1883                  0x00000000);
1884     /* XXX : not implemented */
1885     spr_register(env, SPR_40x_DBSR, "DBSR",
1886                  SPR_NOACCESS, SPR_NOACCESS,
1887                  &spr_read_generic, &spr_write_clear,
1888                  /* Last reset was system reset */
1889                  0x00000300);
1890     /* XXX : not implemented */
1891     spr_register(env, SPR_40x_DAC1, "DAC",
1892                  SPR_NOACCESS, SPR_NOACCESS,
1893                  &spr_read_generic, &spr_write_generic,
1894                  0x00000000);
1895     /* XXX : not implemented */
1896     spr_register(env, SPR_40x_IAC1, "IAC",
1897                  SPR_NOACCESS, SPR_NOACCESS,
1898                  &spr_read_generic, &spr_write_generic,
1899                  0x00000000);
1900     /* Storage control */
1901     /* XXX: TODO: not implemented */
1902     spr_register(env, SPR_405_SLER, "SLER",
1903                  SPR_NOACCESS, SPR_NOACCESS,
1904                  &spr_read_generic, &spr_write_40x_sler,
1905                  0x00000000);
1906     /* not emulated, as Qemu never does speculative access */
1907     spr_register(env, SPR_40x_SGR, "SGR",
1908                  SPR_NOACCESS, SPR_NOACCESS,
1909                  &spr_read_generic, &spr_write_generic,
1910                  0xFFFFFFFF);
1911     /* not emulated, as Qemu do not emulate caches */
1912     spr_register(env, SPR_40x_DCWR, "DCWR",
1913                  SPR_NOACCESS, SPR_NOACCESS,
1914                  &spr_read_generic, &spr_write_generic,
1915                  0x00000000);
1916 }
1917
1918 static void gen_spr_401x2 (CPUPPCState *env)
1919 {
1920     gen_spr_401(env);
1921     spr_register(env, SPR_40x_PID, "PID",
1922                  SPR_NOACCESS, SPR_NOACCESS,
1923                  &spr_read_generic, &spr_write_generic,
1924                  0x00000000);
1925     spr_register(env, SPR_40x_ZPR, "ZPR",
1926                  SPR_NOACCESS, SPR_NOACCESS,
1927                  &spr_read_generic, &spr_write_generic,
1928                  0x00000000);
1929 }
1930
1931 /* SPR specific to PowerPC 403 implementation */
1932 static void gen_spr_403 (CPUPPCState *env)
1933 {
1934     /* Debug interface */
1935     /* XXX : not implemented */
1936     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1937                  SPR_NOACCESS, SPR_NOACCESS,
1938                  &spr_read_generic, &spr_write_40x_dbcr0,
1939                  0x00000000);
1940     /* XXX : not implemented */
1941     spr_register(env, SPR_40x_DBSR, "DBSR",
1942                  SPR_NOACCESS, SPR_NOACCESS,
1943                  &spr_read_generic, &spr_write_clear,
1944                  /* Last reset was system reset */
1945                  0x00000300);
1946     /* XXX : not implemented */
1947     spr_register(env, SPR_40x_DAC1, "DAC1",
1948                  SPR_NOACCESS, SPR_NOACCESS,
1949                  &spr_read_generic, &spr_write_generic,
1950                  0x00000000);
1951     /* XXX : not implemented */
1952     spr_register(env, SPR_40x_DAC2, "DAC2",
1953                  SPR_NOACCESS, SPR_NOACCESS,
1954                  &spr_read_generic, &spr_write_generic,
1955                  0x00000000);
1956     /* XXX : not implemented */
1957     spr_register(env, SPR_40x_IAC1, "IAC1",
1958                  SPR_NOACCESS, SPR_NOACCESS,
1959                  &spr_read_generic, &spr_write_generic,
1960                  0x00000000);
1961     /* XXX : not implemented */
1962     spr_register(env, SPR_40x_IAC2, "IAC2",
1963                  SPR_NOACCESS, SPR_NOACCESS,
1964                  &spr_read_generic, &spr_write_generic,
1965                  0x00000000);
1966 }
1967
1968 static void gen_spr_403_real (CPUPPCState *env)
1969 {
1970     spr_register(env, SPR_403_PBL1,  "PBL1",
1971                  SPR_NOACCESS, SPR_NOACCESS,
1972                  &spr_read_403_pbr, &spr_write_403_pbr,
1973                  0x00000000);
1974     spr_register(env, SPR_403_PBU1,  "PBU1",
1975                  SPR_NOACCESS, SPR_NOACCESS,
1976                  &spr_read_403_pbr, &spr_write_403_pbr,
1977                  0x00000000);
1978     spr_register(env, SPR_403_PBL2,  "PBL2",
1979                  SPR_NOACCESS, SPR_NOACCESS,
1980                  &spr_read_403_pbr, &spr_write_403_pbr,
1981                  0x00000000);
1982     spr_register(env, SPR_403_PBU2,  "PBU2",
1983                  SPR_NOACCESS, SPR_NOACCESS,
1984                  &spr_read_403_pbr, &spr_write_403_pbr,
1985                  0x00000000);
1986 }
1987
1988 static void gen_spr_403_mmu (CPUPPCState *env)
1989 {
1990     /* MMU */
1991     spr_register(env, SPR_40x_PID, "PID",
1992                  SPR_NOACCESS, SPR_NOACCESS,
1993                  &spr_read_generic, &spr_write_generic,
1994                  0x00000000);
1995     spr_register(env, SPR_40x_ZPR, "ZPR",
1996                  SPR_NOACCESS, SPR_NOACCESS,
1997                  &spr_read_generic, &spr_write_generic,
1998                  0x00000000);
1999 }
2000
2001 /* SPR specific to PowerPC compression coprocessor extension */
2002 static void gen_spr_compress (CPUPPCState *env)
2003 {
2004     /* XXX : not implemented */
2005     spr_register(env, SPR_401_SKR, "SKR",
2006                  SPR_NOACCESS, SPR_NOACCESS,
2007                  &spr_read_generic, &spr_write_generic,
2008                  0x00000000);
2009 }
2010
2011 #if defined (TARGET_PPC64)
2012 /* SPR specific to PowerPC 620 */
2013 static void gen_spr_620 (CPUPPCState *env)
2014 {
2015     /* Processor identification */
2016     spr_register(env, SPR_PIR, "PIR",
2017                  SPR_NOACCESS, SPR_NOACCESS,
2018                  &spr_read_generic, &spr_write_pir,
2019                  0x00000000);
2020     spr_register(env, SPR_ASR, "ASR",
2021                  SPR_NOACCESS, SPR_NOACCESS,
2022                  &spr_read_asr, &spr_write_asr,
2023                  0x00000000);
2024     /* Breakpoints */
2025     /* XXX : not implemented */
2026     spr_register(env, SPR_IABR, "IABR",
2027                  SPR_NOACCESS, SPR_NOACCESS,
2028                  &spr_read_generic, &spr_write_generic,
2029                  0x00000000);
2030     /* XXX : not implemented */
2031     spr_register(env, SPR_DABR, "DABR",
2032                  SPR_NOACCESS, SPR_NOACCESS,
2033                  &spr_read_generic, &spr_write_generic,
2034                  0x00000000);
2035     /* XXX : not implemented */
2036     spr_register(env, SPR_SIAR, "SIAR",
2037                  SPR_NOACCESS, SPR_NOACCESS,
2038                  &spr_read_generic, SPR_NOACCESS,
2039                  0x00000000);
2040     /* XXX : not implemented */
2041     spr_register(env, SPR_SDA, "SDA",
2042                  SPR_NOACCESS, SPR_NOACCESS,
2043                  &spr_read_generic, SPR_NOACCESS,
2044                  0x00000000);
2045     /* XXX : not implemented */
2046     spr_register(env, SPR_620_PMC1R, "PMC1",
2047                  SPR_NOACCESS, SPR_NOACCESS,
2048                  &spr_read_generic, SPR_NOACCESS,
2049                  0x00000000);
2050     spr_register(env, SPR_620_PMC1W, "PMC1",
2051                  SPR_NOACCESS, SPR_NOACCESS,
2052                   SPR_NOACCESS, &spr_write_generic,
2053                  0x00000000);
2054     /* XXX : not implemented */
2055     spr_register(env, SPR_620_PMC2R, "PMC2",
2056                  SPR_NOACCESS, SPR_NOACCESS,
2057                  &spr_read_generic, SPR_NOACCESS,
2058                  0x00000000);
2059     spr_register(env, SPR_620_PMC2W, "PMC2",
2060                  SPR_NOACCESS, SPR_NOACCESS,
2061                   SPR_NOACCESS, &spr_write_generic,
2062                  0x00000000);
2063     /* XXX : not implemented */
2064     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2065                  SPR_NOACCESS, SPR_NOACCESS,
2066                  &spr_read_generic, SPR_NOACCESS,
2067                  0x00000000);
2068     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2069                  SPR_NOACCESS, SPR_NOACCESS,
2070                   SPR_NOACCESS, &spr_write_generic,
2071                  0x00000000);
2072     /* External access control */
2073     /* XXX : not implemented */
2074     spr_register(env, SPR_EAR, "EAR",
2075                  SPR_NOACCESS, SPR_NOACCESS,
2076                  &spr_read_generic, &spr_write_generic,
2077                  0x00000000);
2078 #if 0 // XXX: check this
2079     /* XXX : not implemented */
2080     spr_register(env, SPR_620_PMR0, "PMR0",
2081                  SPR_NOACCESS, SPR_NOACCESS,
2082                  &spr_read_generic, &spr_write_generic,
2083                  0x00000000);
2084     /* XXX : not implemented */
2085     spr_register(env, SPR_620_PMR1, "PMR1",
2086                  SPR_NOACCESS, SPR_NOACCESS,
2087                  &spr_read_generic, &spr_write_generic,
2088                  0x00000000);
2089     /* XXX : not implemented */
2090     spr_register(env, SPR_620_PMR2, "PMR2",
2091                  SPR_NOACCESS, SPR_NOACCESS,
2092                  &spr_read_generic, &spr_write_generic,
2093                  0x00000000);
2094     /* XXX : not implemented */
2095     spr_register(env, SPR_620_PMR3, "PMR3",
2096                  SPR_NOACCESS, SPR_NOACCESS,
2097                  &spr_read_generic, &spr_write_generic,
2098                  0x00000000);
2099     /* XXX : not implemented */
2100     spr_register(env, SPR_620_PMR4, "PMR4",
2101                  SPR_NOACCESS, SPR_NOACCESS,
2102                  &spr_read_generic, &spr_write_generic,
2103                  0x00000000);
2104     /* XXX : not implemented */
2105     spr_register(env, SPR_620_PMR5, "PMR5",
2106                  SPR_NOACCESS, SPR_NOACCESS,
2107                  &spr_read_generic, &spr_write_generic,
2108                  0x00000000);
2109     /* XXX : not implemented */
2110     spr_register(env, SPR_620_PMR6, "PMR6",
2111                  SPR_NOACCESS, SPR_NOACCESS,
2112                  &spr_read_generic, &spr_write_generic,
2113                  0x00000000);
2114     /* XXX : not implemented */
2115     spr_register(env, SPR_620_PMR7, "PMR7",
2116                  SPR_NOACCESS, SPR_NOACCESS,
2117                  &spr_read_generic, &spr_write_generic,
2118                  0x00000000);
2119     /* XXX : not implemented */
2120     spr_register(env, SPR_620_PMR8, "PMR8",
2121                  SPR_NOACCESS, SPR_NOACCESS,
2122                  &spr_read_generic, &spr_write_generic,
2123                  0x00000000);
2124     /* XXX : not implemented */
2125     spr_register(env, SPR_620_PMR9, "PMR9",
2126                  SPR_NOACCESS, SPR_NOACCESS,
2127                  &spr_read_generic, &spr_write_generic,
2128                  0x00000000);
2129     /* XXX : not implemented */
2130     spr_register(env, SPR_620_PMRA, "PMR10",
2131                  SPR_NOACCESS, SPR_NOACCESS,
2132                  &spr_read_generic, &spr_write_generic,
2133                  0x00000000);
2134     /* XXX : not implemented */
2135     spr_register(env, SPR_620_PMRB, "PMR11",
2136                  SPR_NOACCESS, SPR_NOACCESS,
2137                  &spr_read_generic, &spr_write_generic,
2138                  0x00000000);
2139     /* XXX : not implemented */
2140     spr_register(env, SPR_620_PMRC, "PMR12",
2141                  SPR_NOACCESS, SPR_NOACCESS,
2142                  &spr_read_generic, &spr_write_generic,
2143                  0x00000000);
2144     /* XXX : not implemented */
2145     spr_register(env, SPR_620_PMRD, "PMR13",
2146                  SPR_NOACCESS, SPR_NOACCESS,
2147                  &spr_read_generic, &spr_write_generic,
2148                  0x00000000);
2149     /* XXX : not implemented */
2150     spr_register(env, SPR_620_PMRE, "PMR14",
2151                  SPR_NOACCESS, SPR_NOACCESS,
2152                  &spr_read_generic, &spr_write_generic,
2153                  0x00000000);
2154     /* XXX : not implemented */
2155     spr_register(env, SPR_620_PMRF, "PMR15",
2156                  SPR_NOACCESS, SPR_NOACCESS,
2157                  &spr_read_generic, &spr_write_generic,
2158                  0x00000000);
2159 #endif
2160     /* XXX : not implemented */
2161     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2162                  SPR_NOACCESS, SPR_NOACCESS,
2163                  &spr_read_generic, &spr_write_generic,
2164                  0x00000000);
2165     /* XXX : not implemented */
2166     spr_register(env, SPR_620_L2CR, "L2CR",
2167                  SPR_NOACCESS, SPR_NOACCESS,
2168                  &spr_read_generic, &spr_write_generic,
2169                  0x00000000);
2170     /* XXX : not implemented */
2171     spr_register(env, SPR_620_L2SR, "L2SR",
2172                  SPR_NOACCESS, SPR_NOACCESS,
2173                  &spr_read_generic, &spr_write_generic,
2174                  0x00000000);
2175 }
2176 #endif /* defined (TARGET_PPC64) */
2177
2178 static void gen_spr_5xx_8xx (CPUPPCState *env)
2179 {
2180     /* Exception processing */
2181     spr_register(env, SPR_DSISR, "DSISR",
2182                  SPR_NOACCESS, SPR_NOACCESS,
2183                  &spr_read_generic, &spr_write_generic,
2184                  0x00000000);
2185     spr_register(env, SPR_DAR, "DAR",
2186                  SPR_NOACCESS, SPR_NOACCESS,
2187                  &spr_read_generic, &spr_write_generic,
2188                  0x00000000);
2189     /* Timer */
2190     spr_register(env, SPR_DECR, "DECR",
2191                  SPR_NOACCESS, SPR_NOACCESS,
2192                  &spr_read_decr, &spr_write_decr,
2193                  0x00000000);
2194     /* XXX : not implemented */
2195     spr_register(env, SPR_MPC_EIE, "EIE",
2196                  SPR_NOACCESS, SPR_NOACCESS,
2197                  &spr_read_generic, &spr_write_generic,
2198                  0x00000000);
2199     /* XXX : not implemented */
2200     spr_register(env, SPR_MPC_EID, "EID",
2201                  SPR_NOACCESS, SPR_NOACCESS,
2202                  &spr_read_generic, &spr_write_generic,
2203                  0x00000000);
2204     /* XXX : not implemented */
2205     spr_register(env, SPR_MPC_NRI, "NRI",
2206                  SPR_NOACCESS, SPR_NOACCESS,
2207                  &spr_read_generic, &spr_write_generic,
2208                  0x00000000);
2209     /* XXX : not implemented */
2210     spr_register(env, SPR_MPC_CMPA, "CMPA",
2211                  SPR_NOACCESS, SPR_NOACCESS,
2212                  &spr_read_generic, &spr_write_generic,
2213                  0x00000000);
2214     /* XXX : not implemented */
2215     spr_register(env, SPR_MPC_CMPB, "CMPB",
2216                  SPR_NOACCESS, SPR_NOACCESS,
2217                  &spr_read_generic, &spr_write_generic,
2218                  0x00000000);
2219     /* XXX : not implemented */
2220     spr_register(env, SPR_MPC_CMPC, "CMPC",
2221                  SPR_NOACCESS, SPR_NOACCESS,
2222                  &spr_read_generic, &spr_write_generic,
2223                  0x00000000);
2224     /* XXX : not implemented */
2225     spr_register(env, SPR_MPC_CMPD, "CMPD",
2226                  SPR_NOACCESS, SPR_NOACCESS,
2227                  &spr_read_generic, &spr_write_generic,
2228                  0x00000000);
2229     /* XXX : not implemented */
2230     spr_register(env, SPR_MPC_ECR, "ECR",
2231                  SPR_NOACCESS, SPR_NOACCESS,
2232                  &spr_read_generic, &spr_write_generic,
2233                  0x00000000);
2234     /* XXX : not implemented */
2235     spr_register(env, SPR_MPC_DER, "DER",
2236                  SPR_NOACCESS, SPR_NOACCESS,
2237                  &spr_read_generic, &spr_write_generic,
2238                  0x00000000);
2239     /* XXX : not implemented */
2240     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2241                  SPR_NOACCESS, SPR_NOACCESS,
2242                  &spr_read_generic, &spr_write_generic,
2243                  0x00000000);
2244     /* XXX : not implemented */
2245     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2246                  SPR_NOACCESS, SPR_NOACCESS,
2247                  &spr_read_generic, &spr_write_generic,
2248                  0x00000000);
2249     /* XXX : not implemented */
2250     spr_register(env, SPR_MPC_CMPE, "CMPE",
2251                  SPR_NOACCESS, SPR_NOACCESS,
2252                  &spr_read_generic, &spr_write_generic,
2253                  0x00000000);
2254     /* XXX : not implemented */
2255     spr_register(env, SPR_MPC_CMPF, "CMPF",
2256                  SPR_NOACCESS, SPR_NOACCESS,
2257                  &spr_read_generic, &spr_write_generic,
2258                  0x00000000);
2259     /* XXX : not implemented */
2260     spr_register(env, SPR_MPC_CMPG, "CMPG",
2261                  SPR_NOACCESS, SPR_NOACCESS,
2262                  &spr_read_generic, &spr_write_generic,
2263                  0x00000000);
2264     /* XXX : not implemented */
2265     spr_register(env, SPR_MPC_CMPH, "CMPH",
2266                  SPR_NOACCESS, SPR_NOACCESS,
2267                  &spr_read_generic, &spr_write_generic,
2268                  0x00000000);
2269     /* XXX : not implemented */
2270     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2271                  SPR_NOACCESS, SPR_NOACCESS,
2272                  &spr_read_generic, &spr_write_generic,
2273                  0x00000000);
2274     /* XXX : not implemented */
2275     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2276                  SPR_NOACCESS, SPR_NOACCESS,
2277                  &spr_read_generic, &spr_write_generic,
2278                  0x00000000);
2279     /* XXX : not implemented */
2280     spr_register(env, SPR_MPC_BAR, "BAR",
2281                  SPR_NOACCESS, SPR_NOACCESS,
2282                  &spr_read_generic, &spr_write_generic,
2283                  0x00000000);
2284     /* XXX : not implemented */
2285     spr_register(env, SPR_MPC_DPDR, "DPDR",
2286                  SPR_NOACCESS, SPR_NOACCESS,
2287                  &spr_read_generic, &spr_write_generic,
2288                  0x00000000);
2289     /* XXX : not implemented */
2290     spr_register(env, SPR_MPC_IMMR, "IMMR",
2291                  SPR_NOACCESS, SPR_NOACCESS,
2292                  &spr_read_generic, &spr_write_generic,
2293                  0x00000000);
2294 }
2295
2296 static void gen_spr_5xx (CPUPPCState *env)
2297 {
2298     /* XXX : not implemented */
2299     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2300                  SPR_NOACCESS, SPR_NOACCESS,
2301                  &spr_read_generic, &spr_write_generic,
2302                  0x00000000);
2303     /* XXX : not implemented */
2304     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2305                  SPR_NOACCESS, SPR_NOACCESS,
2306                  &spr_read_generic, &spr_write_generic,
2307                  0x00000000);
2308     /* XXX : not implemented */
2309     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2310                  SPR_NOACCESS, SPR_NOACCESS,
2311                  &spr_read_generic, &spr_write_generic,
2312                  0x00000000);
2313     /* XXX : not implemented */
2314     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2315                  SPR_NOACCESS, SPR_NOACCESS,
2316                  &spr_read_generic, &spr_write_generic,
2317                  0x00000000);
2318     /* XXX : not implemented */
2319     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2320                  SPR_NOACCESS, SPR_NOACCESS,
2321                  &spr_read_generic, &spr_write_generic,
2322                  0x00000000);
2323     /* XXX : not implemented */
2324     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2325                  SPR_NOACCESS, SPR_NOACCESS,
2326                  &spr_read_generic, &spr_write_generic,
2327                  0x00000000);
2328     /* XXX : not implemented */
2329     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2330                  SPR_NOACCESS, SPR_NOACCESS,
2331                  &spr_read_generic, &spr_write_generic,
2332                  0x00000000);
2333     /* XXX : not implemented */
2334     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2335                  SPR_NOACCESS, SPR_NOACCESS,
2336                  &spr_read_generic, &spr_write_generic,
2337                  0x00000000);
2338     /* XXX : not implemented */
2339     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2340                  SPR_NOACCESS, SPR_NOACCESS,
2341                  &spr_read_generic, &spr_write_generic,
2342                  0x00000000);
2343     /* XXX : not implemented */
2344     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2345                  SPR_NOACCESS, SPR_NOACCESS,
2346                  &spr_read_generic, &spr_write_generic,
2347                  0x00000000);
2348     /* XXX : not implemented */
2349     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2350                  SPR_NOACCESS, SPR_NOACCESS,
2351                  &spr_read_generic, &spr_write_generic,
2352                  0x00000000);
2353     /* XXX : not implemented */
2354     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2355                  SPR_NOACCESS, SPR_NOACCESS,
2356                  &spr_read_generic, &spr_write_generic,
2357                  0x00000000);
2358     /* XXX : not implemented */
2359     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2360                  SPR_NOACCESS, SPR_NOACCESS,
2361                  &spr_read_generic, &spr_write_generic,
2362                  0x00000000);
2363     /* XXX : not implemented */
2364     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2365                  SPR_NOACCESS, SPR_NOACCESS,
2366                  &spr_read_generic, &spr_write_generic,
2367                  0x00000000);
2368     /* XXX : not implemented */
2369     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2370                  SPR_NOACCESS, SPR_NOACCESS,
2371                  &spr_read_generic, &spr_write_generic,
2372                  0x00000000);
2373     /* XXX : not implemented */
2374     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2375                  SPR_NOACCESS, SPR_NOACCESS,
2376                  &spr_read_generic, &spr_write_generic,
2377                  0x00000000);
2378     /* XXX : not implemented */
2379     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2380                  SPR_NOACCESS, SPR_NOACCESS,
2381                  &spr_read_generic, &spr_write_generic,
2382                  0x00000000);
2383     /* XXX : not implemented */
2384     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2385                  SPR_NOACCESS, SPR_NOACCESS,
2386                  &spr_read_generic, &spr_write_generic,
2387                  0x00000000);
2388     /* XXX : not implemented */
2389     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2390                  SPR_NOACCESS, SPR_NOACCESS,
2391                  &spr_read_generic, &spr_write_generic,
2392                  0x00000000);
2393     /* XXX : not implemented */
2394     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2395                  SPR_NOACCESS, SPR_NOACCESS,
2396                  &spr_read_generic, &spr_write_generic,
2397                  0x00000000);
2398     /* XXX : not implemented */
2399     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2400                  SPR_NOACCESS, SPR_NOACCESS,
2401                  &spr_read_generic, &spr_write_generic,
2402                  0x00000000);
2403 }
2404
2405 static void gen_spr_8xx (CPUPPCState *env)
2406 {
2407     /* XXX : not implemented */
2408     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2409                  SPR_NOACCESS, SPR_NOACCESS,
2410                  &spr_read_generic, &spr_write_generic,
2411                  0x00000000);
2412     /* XXX : not implemented */
2413     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2414                  SPR_NOACCESS, SPR_NOACCESS,
2415                  &spr_read_generic, &spr_write_generic,
2416                  0x00000000);
2417     /* XXX : not implemented */
2418     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2419                  SPR_NOACCESS, SPR_NOACCESS,
2420                  &spr_read_generic, &spr_write_generic,
2421                  0x00000000);
2422     /* XXX : not implemented */
2423     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2424                  SPR_NOACCESS, SPR_NOACCESS,
2425                  &spr_read_generic, &spr_write_generic,
2426                  0x00000000);
2427     /* XXX : not implemented */
2428     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2429                  SPR_NOACCESS, SPR_NOACCESS,
2430                  &spr_read_generic, &spr_write_generic,
2431                  0x00000000);
2432     /* XXX : not implemented */
2433     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2434                  SPR_NOACCESS, SPR_NOACCESS,
2435                  &spr_read_generic, &spr_write_generic,
2436                  0x00000000);
2437     /* XXX : not implemented */
2438     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2439                  SPR_NOACCESS, SPR_NOACCESS,
2440                  &spr_read_generic, &spr_write_generic,
2441                  0x00000000);
2442     /* XXX : not implemented */
2443     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2444                  SPR_NOACCESS, SPR_NOACCESS,
2445                  &spr_read_generic, &spr_write_generic,
2446                  0x00000000);
2447     /* XXX : not implemented */
2448     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2449                  SPR_NOACCESS, SPR_NOACCESS,
2450                  &spr_read_generic, &spr_write_generic,
2451                  0x00000000);
2452     /* XXX : not implemented */
2453     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2454                  SPR_NOACCESS, SPR_NOACCESS,
2455                  &spr_read_generic, &spr_write_generic,
2456                  0x00000000);
2457     /* XXX : not implemented */
2458     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2459                  SPR_NOACCESS, SPR_NOACCESS,
2460                  &spr_read_generic, &spr_write_generic,
2461                  0x00000000);
2462     /* XXX : not implemented */
2463     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2464                  SPR_NOACCESS, SPR_NOACCESS,
2465                  &spr_read_generic, &spr_write_generic,
2466                  0x00000000);
2467     /* XXX : not implemented */
2468     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2469                  SPR_NOACCESS, SPR_NOACCESS,
2470                  &spr_read_generic, &spr_write_generic,
2471                  0x00000000);
2472     /* XXX : not implemented */
2473     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2474                  SPR_NOACCESS, SPR_NOACCESS,
2475                  &spr_read_generic, &spr_write_generic,
2476                  0x00000000);
2477     /* XXX : not implemented */
2478     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2479                  SPR_NOACCESS, SPR_NOACCESS,
2480                  &spr_read_generic, &spr_write_generic,
2481                  0x00000000);
2482     /* XXX : not implemented */
2483     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2484                  SPR_NOACCESS, SPR_NOACCESS,
2485                  &spr_read_generic, &spr_write_generic,
2486                  0x00000000);
2487     /* XXX : not implemented */
2488     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2489                  SPR_NOACCESS, SPR_NOACCESS,
2490                  &spr_read_generic, &spr_write_generic,
2491                  0x00000000);
2492     /* XXX : not implemented */
2493     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2494                  SPR_NOACCESS, SPR_NOACCESS,
2495                  &spr_read_generic, &spr_write_generic,
2496                  0x00000000);
2497     /* XXX : not implemented */
2498     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2499                  SPR_NOACCESS, SPR_NOACCESS,
2500                  &spr_read_generic, &spr_write_generic,
2501                  0x00000000);
2502     /* XXX : not implemented */
2503     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2504                  SPR_NOACCESS, SPR_NOACCESS,
2505                  &spr_read_generic, &spr_write_generic,
2506                  0x00000000);
2507     /* XXX : not implemented */
2508     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2509                  SPR_NOACCESS, SPR_NOACCESS,
2510                  &spr_read_generic, &spr_write_generic,
2511                  0x00000000);
2512     /* XXX : not implemented */
2513     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2514                  SPR_NOACCESS, SPR_NOACCESS,
2515                  &spr_read_generic, &spr_write_generic,
2516                  0x00000000);
2517     /* XXX : not implemented */
2518     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2519                  SPR_NOACCESS, SPR_NOACCESS,
2520                  &spr_read_generic, &spr_write_generic,
2521                  0x00000000);
2522     /* XXX : not implemented */
2523     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2524                  SPR_NOACCESS, SPR_NOACCESS,
2525                  &spr_read_generic, &spr_write_generic,
2526                  0x00000000);
2527     /* XXX : not implemented */
2528     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2529                  SPR_NOACCESS, SPR_NOACCESS,
2530                  &spr_read_generic, &spr_write_generic,
2531                  0x00000000);
2532 }
2533
2534 // XXX: TODO
2535 /*
2536  * AMR     => SPR 29 (Power 2.04)
2537  * CTRL    => SPR 136 (Power 2.04)
2538  * CTRL    => SPR 152 (Power 2.04)
2539  * SCOMC   => SPR 276 (64 bits ?)
2540  * SCOMD   => SPR 277 (64 bits ?)
2541  * TBU40   => SPR 286 (Power 2.04 hypv)
2542  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2543  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2544  * HDSISR  => SPR 306 (Power 2.04 hypv)
2545  * HDAR    => SPR 307 (Power 2.04 hypv)
2546  * PURR    => SPR 309 (Power 2.04 hypv)
2547  * HDEC    => SPR 310 (Power 2.04 hypv)
2548  * HIOR    => SPR 311 (hypv)
2549  * RMOR    => SPR 312 (970)
2550  * HRMOR   => SPR 313 (Power 2.04 hypv)
2551  * HSRR0   => SPR 314 (Power 2.04 hypv)
2552  * HSRR1   => SPR 315 (Power 2.04 hypv)
2553  * LPCR    => SPR 316 (970)
2554  * LPIDR   => SPR 317 (970)
2555  * SPEFSCR => SPR 512 (Power 2.04 emb)
2556  * EPR     => SPR 702 (Power 2.04 emb)
2557  * perf    => 768-783 (Power 2.04)
2558  * perf    => 784-799 (Power 2.04)
2559  * PPR     => SPR 896 (Power 2.04)
2560  * EPLC    => SPR 947 (Power 2.04 emb)
2561  * EPSC    => SPR 948 (Power 2.04 emb)
2562  * DABRX   => 1015    (Power 2.04 hypv)
2563  * FPECR   => SPR 1022 (?)
2564  * ... and more (thermal management, performance counters, ...)
2565  */
2566
2567 /*****************************************************************************/
2568 /* Exception vectors models                                                  */
2569 static void init_excp_4xx_real (CPUPPCState *env)
2570 {
2571 #if !defined(CONFIG_USER_ONLY)
2572     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2573     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2574     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2575     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2576     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2577     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2578     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2579     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2580     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2581     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2582     env->excp_prefix = 0x00000000UL;
2583     env->ivor_mask = 0x0000FFF0UL;
2584     env->ivpr_mask = 0xFFFF0000UL;
2585     /* Hardware reset vector */
2586     env->hreset_vector = 0xFFFFFFFCUL;
2587 #endif
2588 }
2589
2590 static void init_excp_4xx_softmmu (CPUPPCState *env)
2591 {
2592 #if !defined(CONFIG_USER_ONLY)
2593     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2594     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2595     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2596     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2597     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2598     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2599     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2600     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2601     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2602     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2603     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2604     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2605     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2606     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2607     env->excp_prefix = 0x00000000UL;
2608     env->ivor_mask = 0x0000FFF0UL;
2609     env->ivpr_mask = 0xFFFF0000UL;
2610     /* Hardware reset vector */
2611     env->hreset_vector = 0xFFFFFFFCUL;
2612 #endif
2613 }
2614
2615 static void init_excp_MPC5xx (CPUPPCState *env)
2616 {
2617 #if !defined(CONFIG_USER_ONLY)
2618     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2619     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2620     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2621     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2622     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2623     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2624     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2625     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2626     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2627     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2628     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2629     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2630     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2631     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2632     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2633     env->excp_prefix = 0x00000000UL;
2634     env->ivor_mask = 0x0000FFF0UL;
2635     env->ivpr_mask = 0xFFFF0000UL;
2636     /* Hardware reset vector */
2637     env->hreset_vector = 0xFFFFFFFCUL;
2638 #endif
2639 }
2640
2641 static void init_excp_MPC8xx (CPUPPCState *env)
2642 {
2643 #if !defined(CONFIG_USER_ONLY)
2644     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2645     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2646     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2647     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2648     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2649     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2650     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2651     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2652     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2653     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2654     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2655     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2656     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2657     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2658     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2659     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2660     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2661     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2662     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2663     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2664     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2665     env->excp_prefix = 0x00000000UL;
2666     env->ivor_mask = 0x0000FFF0UL;
2667     env->ivpr_mask = 0xFFFF0000UL;
2668     /* Hardware reset vector */
2669     env->hreset_vector = 0xFFFFFFFCUL;
2670 #endif
2671 }
2672
2673 static void init_excp_G2 (CPUPPCState *env)
2674 {
2675 #if !defined(CONFIG_USER_ONLY)
2676     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2677     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2678     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2679     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2680     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2681     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2682     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2683     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2684     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2685     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2686     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2687     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2688     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2689     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2690     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2691     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2692     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2693     env->excp_prefix = 0x00000000UL;
2694     /* Hardware reset vector */
2695     env->hreset_vector = 0xFFFFFFFCUL;
2696 #endif
2697 }
2698
2699 static void init_excp_e200 (CPUPPCState *env)
2700 {
2701 #if !defined(CONFIG_USER_ONLY)
2702     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2703     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2704     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2705     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2706     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2707     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2708     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2709     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2710     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2711     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2712     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2713     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2714     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2715     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2716     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2717     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2718     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2719     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2720     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2721     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2722     env->excp_prefix = 0x00000000UL;
2723     env->ivor_mask = 0x0000FFF7UL;
2724     env->ivpr_mask = 0xFFFF0000UL;
2725     /* Hardware reset vector */
2726     env->hreset_vector = 0xFFFFFFFCUL;
2727 #endif
2728 }
2729
2730 static void init_excp_BookE (CPUPPCState *env)
2731 {
2732 #if !defined(CONFIG_USER_ONLY)
2733     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2734     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2735     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2736     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2737     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2738     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2739     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2740     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2741     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2742     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2743     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2744     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2745     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2746     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2747     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2748     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2749     env->excp_prefix = 0x00000000UL;
2750     env->ivor_mask = 0x0000FFE0UL;
2751     env->ivpr_mask = 0xFFFF0000UL;
2752     /* Hardware reset vector */
2753     env->hreset_vector = 0xFFFFFFFCUL;
2754 #endif
2755 }
2756
2757 static void init_excp_601 (CPUPPCState *env)
2758 {
2759 #if !defined(CONFIG_USER_ONLY)
2760     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2761     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2762     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2763     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2764     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2765     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2766     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2767     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2768     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2769     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2770     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2771     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2772     env->excp_prefix = 0xFFF00000UL;
2773     /* Hardware reset vector */
2774     env->hreset_vector = 0x00000100UL;
2775 #endif
2776 }
2777
2778 static void init_excp_602 (CPUPPCState *env)
2779 {
2780 #if !defined(CONFIG_USER_ONLY)
2781     /* XXX: exception prefix has a special behavior on 602 */
2782     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2783     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2784     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2785     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2786     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2787     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2788     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2789     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2790     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2791     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2792     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2793     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2794     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2795     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2796     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2797     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2798     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2799     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2800     env->excp_prefix = 0xFFF00000UL;
2801     /* Hardware reset vector */
2802     env->hreset_vector = 0xFFFFFFFCUL;
2803 #endif
2804 }
2805
2806 static void init_excp_603 (CPUPPCState *env)
2807 {
2808 #if !defined(CONFIG_USER_ONLY)
2809     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2810     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2811     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2812     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2813     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2814     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2815     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2816     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2817     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2818     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2819     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2820     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2821     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2822     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2823     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2824     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2825     env->excp_prefix = 0x00000000UL;
2826     /* Hardware reset vector */
2827     env->hreset_vector = 0xFFFFFFFCUL;
2828 #endif
2829 }
2830
2831 static void init_excp_604 (CPUPPCState *env)
2832 {
2833 #if !defined(CONFIG_USER_ONLY)
2834     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2835     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2836     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2837     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2838     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2839     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2840     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2841     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2842     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2843     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2844     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2845     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2846     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2847     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2848     env->excp_prefix = 0x00000000UL;
2849     /* Hardware reset vector */
2850     env->hreset_vector = 0xFFFFFFFCUL;
2851 #endif
2852 }
2853
2854 #if defined(TARGET_PPC64)
2855 static void init_excp_620 (CPUPPCState *env)
2856 {
2857 #if !defined(CONFIG_USER_ONLY)
2858     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2859     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2860     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2861     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2862     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2863     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2864     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2865     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2866     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2867     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2868     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2869     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2870     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2871     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2872     env->excp_prefix = 0xFFF00000UL;
2873     /* Hardware reset vector */
2874     env->hreset_vector = 0x0000000000000100ULL;
2875 #endif
2876 }
2877 #endif /* defined(TARGET_PPC64) */
2878
2879 static void init_excp_7x0 (CPUPPCState *env)
2880 {
2881 #if !defined(CONFIG_USER_ONLY)
2882     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2883     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2884     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2885     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2886     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2887     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2888     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2889     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2890     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2891     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2892     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2893     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2894     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2895     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2896     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2897     env->excp_prefix = 0x00000000UL;
2898     /* Hardware reset vector */
2899     env->hreset_vector = 0xFFFFFFFCUL;
2900 #endif
2901 }
2902
2903 static void init_excp_750cl (CPUPPCState *env)
2904 {
2905 #if !defined(CONFIG_USER_ONLY)
2906     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2907     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2908     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2909     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2910     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2911     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2912     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2913     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2914     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2915     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2916     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2917     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2918     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2919     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2920     env->excp_prefix = 0x00000000UL;
2921     /* Hardware reset vector */
2922     env->hreset_vector = 0xFFFFFFFCUL;
2923 #endif
2924 }
2925
2926 static void init_excp_750cx (CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2930     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2931     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2932     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2933     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2935     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2936     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2937     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2938     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2939     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2940     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2941     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2942     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2943     env->excp_prefix = 0x00000000UL;
2944     /* Hardware reset vector */
2945     env->hreset_vector = 0xFFFFFFFCUL;
2946 #endif
2947 }
2948
2949 /* XXX: Check if this is correct */
2950 static void init_excp_7x5 (CPUPPCState *env)
2951 {
2952 #if !defined(CONFIG_USER_ONLY)
2953     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2954     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2955     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2956     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2957     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2958     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2959     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2960     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2961     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2962     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2963     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2964     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2965     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2966     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2967     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2968     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2969     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2970     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2971     env->excp_prefix = 0x00000000UL;
2972     /* Hardware reset vector */
2973     env->hreset_vector = 0xFFFFFFFCUL;
2974 #endif
2975 }
2976
2977 static void init_excp_7400 (CPUPPCState *env)
2978 {
2979 #if !defined(CONFIG_USER_ONLY)
2980     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2981     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2982     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2983     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2984     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2985     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2986     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2987     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2988     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2989     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2990     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2991     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2992     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2993     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2994     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2995     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2996     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2997     env->excp_prefix = 0x00000000UL;
2998     /* Hardware reset vector */
2999     env->hreset_vector = 0xFFFFFFFCUL;
3000 #endif
3001 }
3002
3003 static void init_excp_7450 (CPUPPCState *env)
3004 {
3005 #if !defined(CONFIG_USER_ONLY)
3006     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3007     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3008     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3009     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3010     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3011     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3012     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3013     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3014     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3015     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3016     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3017     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3018     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3019     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3020     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3021     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3022     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3023     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3024     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3025     env->excp_prefix = 0x00000000UL;
3026     /* Hardware reset vector */
3027     env->hreset_vector = 0xFFFFFFFCUL;
3028 #endif
3029 }
3030
3031 #if defined (TARGET_PPC64)
3032 static void init_excp_970 (CPUPPCState *env)
3033 {
3034 #if !defined(CONFIG_USER_ONLY)
3035     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3036     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3037     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3038     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3039     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3040     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3041     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3043     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3044     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3045     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3046     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3047     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3048     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3049     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3050     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3051     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3052     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3053     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3054     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3055     env->excp_prefix   = 0x00000000FFF00000ULL;
3056     /* Hardware reset vector */
3057     env->hreset_vector = 0x0000000000000100ULL;
3058 #endif
3059 }
3060 #endif
3061
3062 /*****************************************************************************/
3063 /* Power management enable checks                                            */
3064 static int check_pow_none (CPUPPCState *env)
3065 {
3066     return 0;
3067 }
3068
3069 static int check_pow_nocheck (CPUPPCState *env)
3070 {
3071     return 1;
3072 }
3073
3074 static int check_pow_hid0 (CPUPPCState *env)
3075 {
3076     if (env->spr[SPR_HID0] & 0x00E00000)
3077         return 1;
3078
3079     return 0;
3080 }
3081
3082 static int check_pow_hid0_74xx (CPUPPCState *env)
3083 {
3084     if (env->spr[SPR_HID0] & 0x00600000)
3085         return 1;
3086
3087     return 0;
3088 }
3089
3090 /*****************************************************************************/
3091 /* PowerPC implementations definitions                                       */
3092
3093 /* PowerPC 401                                                               */
3094 #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3095                               PPC_WRTEE | PPC_DCR |                           \
3096                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3097                               PPC_CACHE_DCBZ |                                \
3098                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3099                               PPC_4xx_COMMON | PPC_40x_EXCP)
3100 #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3101 #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3102 #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3103 #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3104 #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3105 #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3106                               POWERPC_FLAG_BUS_CLK)
3107 #define check_pow_401        check_pow_nocheck
3108
3109 static void init_proc_401 (CPUPPCState *env)
3110 {
3111     gen_spr_40x(env);
3112     gen_spr_401_403(env);
3113     gen_spr_401(env);
3114     init_excp_4xx_real(env);
3115     env->dcache_line_size = 32;
3116     env->icache_line_size = 32;
3117     /* Allocate hardware IRQ controller */
3118     ppc40x_irq_init(env);
3119 }
3120
3121 /* PowerPC 401x2                                                             */
3122 #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3123                               PPC_DCR | PPC_WRTEE |                           \
3124                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3125                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3126                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3127                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3128                               PPC_4xx_COMMON | PPC_40x_EXCP)
3129 #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3130 #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3131 #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3132 #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3133 #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3134 #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3135                               POWERPC_FLAG_BUS_CLK)
3136 #define check_pow_401x2      check_pow_nocheck
3137
3138 static void init_proc_401x2 (CPUPPCState *env)
3139 {
3140     gen_spr_40x(env);
3141     gen_spr_401_403(env);
3142     gen_spr_401x2(env);
3143     gen_spr_compress(env);
3144     /* Memory management */
3145 #if !defined(CONFIG_USER_ONLY)
3146     env->nb_tlb = 64;
3147     env->nb_ways = 1;
3148     env->id_tlbs = 0;
3149 #endif
3150     init_excp_4xx_softmmu(env);
3151     env->dcache_line_size = 32;
3152     env->icache_line_size = 32;
3153     /* Allocate hardware IRQ controller */
3154     ppc40x_irq_init(env);
3155 }
3156
3157 /* PowerPC 401x3                                                             */
3158 #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3159                               PPC_DCR | PPC_WRTEE |                           \
3160                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3161                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3162                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3163                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3164                               PPC_4xx_COMMON | PPC_40x_EXCP)
3165 #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3166 #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3167 #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3168 #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3169 #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3170 #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3171                               POWERPC_FLAG_BUS_CLK)
3172 #define check_pow_401x3      check_pow_nocheck
3173
3174 __attribute__ (( unused ))
3175 static void init_proc_401x3 (CPUPPCState *env)
3176 {
3177     gen_spr_40x(env);
3178     gen_spr_401_403(env);
3179     gen_spr_401(env);
3180     gen_spr_401x2(env);
3181     gen_spr_compress(env);
3182     init_excp_4xx_softmmu(env);
3183     env->dcache_line_size = 32;
3184     env->icache_line_size = 32;
3185     /* Allocate hardware IRQ controller */
3186     ppc40x_irq_init(env);
3187 }
3188
3189 /* IOP480                                                                    */
3190 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3191                               PPC_DCR | PPC_WRTEE |                           \
3192                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3193                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3194                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3195                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3196                               PPC_4xx_COMMON | PPC_40x_EXCP)
3197 #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3198 #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3199 #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3200 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3201 #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3202 #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3203                               POWERPC_FLAG_BUS_CLK)
3204 #define check_pow_IOP480     check_pow_nocheck
3205
3206 static void init_proc_IOP480 (CPUPPCState *env)
3207 {
3208     gen_spr_40x(env);
3209     gen_spr_401_403(env);
3210     gen_spr_401x2(env);
3211     gen_spr_compress(env);
3212     /* Memory management */
3213 #if !defined(CONFIG_USER_ONLY)
3214     env->nb_tlb = 64;
3215     env->nb_ways = 1;
3216     env->id_tlbs = 0;
3217 #endif
3218     init_excp_4xx_softmmu(env);
3219     env->dcache_line_size = 32;
3220     env->icache_line_size = 32;
3221     /* Allocate hardware IRQ controller */
3222     ppc40x_irq_init(env);
3223 }
3224
3225 /* PowerPC 403                                                               */
3226 #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3227                               PPC_DCR | PPC_WRTEE |                           \
3228                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3229                               PPC_CACHE_DCBZ |                                \
3230                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3231                               PPC_4xx_COMMON | PPC_40x_EXCP)
3232 #define POWERPC_MSRM_403     (0x000000000007D00DULL)
3233 #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3234 #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3235 #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3236 #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3237 #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3238                               POWERPC_FLAG_BUS_CLK)
3239 #define check_pow_403        check_pow_nocheck
3240
3241 static void init_proc_403 (CPUPPCState *env)
3242 {
3243     gen_spr_40x(env);
3244     gen_spr_401_403(env);
3245     gen_spr_403(env);
3246     gen_spr_403_real(env);
3247     init_excp_4xx_real(env);
3248     env->dcache_line_size = 32;
3249     env->icache_line_size = 32;
3250     /* Allocate hardware IRQ controller */
3251     ppc40x_irq_init(env);
3252 }
3253
3254 /* PowerPC 403 GCX                                                           */
3255 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3256                               PPC_DCR | PPC_WRTEE |                           \
3257                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3258                               PPC_CACHE_DCBZ |                                \
3259                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3260                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3261                               PPC_4xx_COMMON | PPC_40x_EXCP)
3262 #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3263 #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3264 #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3265 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3266 #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3267 #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3268                               POWERPC_FLAG_BUS_CLK)
3269 #define check_pow_403GCX     check_pow_nocheck
3270
3271 static void init_proc_403GCX (CPUPPCState *env)
3272 {
3273     gen_spr_40x(env);
3274     gen_spr_401_403(env);
3275     gen_spr_403(env);
3276     gen_spr_403_real(env);
3277     gen_spr_403_mmu(env);
3278     /* Bus access control */
3279     /* not emulated, as Qemu never does speculative access */
3280     spr_register(env, SPR_40x_SGR, "SGR",
3281                  SPR_NOACCESS, SPR_NOACCESS,
3282                  &spr_read_generic, &spr_write_generic,
3283                  0xFFFFFFFF);
3284     /* not emulated, as Qemu do not emulate caches */
3285     spr_register(env, SPR_40x_DCWR, "DCWR",
3286                  SPR_NOACCESS, SPR_NOACCESS,
3287                  &spr_read_generic, &spr_write_generic,
3288                  0x00000000);
3289     /* Memory management */
3290 #if !defined(CONFIG_USER_ONLY)
3291     env->nb_tlb = 64;
3292     env->nb_ways = 1;
3293     env->id_tlbs = 0;
3294 #endif
3295     init_excp_4xx_softmmu(env);
3296     env->dcache_line_size = 32;
3297     env->icache_line_size = 32;
3298     /* Allocate hardware IRQ controller */
3299     ppc40x_irq_init(env);
3300 }
3301
3302 /* PowerPC 405                                                               */
3303 #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3304                               PPC_DCR | PPC_WRTEE |                           \
3305                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3306                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3307                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3308                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3309                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3310 #define POWERPC_MSRM_405     (0x000000000006E630ULL)
3311 #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3312 #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3313 #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3314 #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3315 #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3316                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3317 #define check_pow_405        check_pow_nocheck
3318
3319 static void init_proc_405 (CPUPPCState *env)
3320 {
3321     /* Time base */
3322     gen_tbl(env);
3323     gen_spr_40x(env);
3324     gen_spr_405(env);
3325     /* Bus access control */
3326     /* not emulated, as Qemu never does speculative access */
3327     spr_register(env, SPR_40x_SGR, "SGR",
3328                  SPR_NOACCESS, SPR_NOACCESS,
3329                  &spr_read_generic, &spr_write_generic,
3330                  0xFFFFFFFF);
3331     /* not emulated, as Qemu do not emulate caches */
3332     spr_register(env, SPR_40x_DCWR, "DCWR",
3333                  SPR_NOACCESS, SPR_NOACCESS,
3334                  &spr_read_generic, &spr_write_generic,
3335                  0x00000000);
3336     /* Memory management */
3337 #if !defined(CONFIG_USER_ONLY)
3338     env->nb_tlb = 64;
3339     env->nb_ways = 1;
3340     env->id_tlbs = 0;
3341 #endif
3342     init_excp_4xx_softmmu(env);
3343     env->dcache_line_size = 32;
3344     env->icache_line_size = 32;
3345     /* Allocate hardware IRQ controller */
3346     ppc40x_irq_init(env);
3347 }
3348
3349 /* PowerPC 440 EP                                                            */
3350 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3351                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3352                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3353                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3354                               PPC_MEM_TLBSYNC |                               \
3355                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3356                               PPC_440_SPEC)
3357 #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3358 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3359 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3360 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3361 #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3362 #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3363                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3364 #define check_pow_440EP      check_pow_nocheck
3365
3366 __attribute__ (( unused ))
3367 static void init_proc_440EP (CPUPPCState *env)
3368 {
3369     /* Time base */
3370     gen_tbl(env);
3371     gen_spr_BookE(env, 0x000000000000FFFFULL);
3372     gen_spr_440(env);
3373     gen_spr_usprgh(env);
3374     /* Processor identification */
3375     spr_register(env, SPR_BOOKE_PIR, "PIR",
3376                  SPR_NOACCESS, SPR_NOACCESS,
3377                  &spr_read_generic, &spr_write_pir,
3378                  0x00000000);
3379     /* XXX : not implemented */
3380     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3381                  SPR_NOACCESS, SPR_NOACCESS,
3382                  &spr_read_generic, &spr_write_generic,
3383                  0x00000000);
3384     /* XXX : not implemented */
3385     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3386                  SPR_NOACCESS, SPR_NOACCESS,
3387                  &spr_read_generic, &spr_write_generic,
3388                  0x00000000);
3389     /* XXX : not implemented */
3390     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3391                  SPR_NOACCESS, SPR_NOACCESS,
3392                  &spr_read_generic, &spr_write_generic,
3393                  0x00000000);
3394     /* XXX : not implemented */
3395     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3396                  SPR_NOACCESS, SPR_NOACCESS,
3397                  &spr_read_generic, &spr_write_generic,
3398                  0x00000000);
3399     /* XXX : not implemented */
3400     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3401                  SPR_NOACCESS, SPR_NOACCESS,
3402                  &spr_read_generic, &spr_write_generic,
3403                  0x00000000);
3404     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3405                  SPR_NOACCESS, SPR_NOACCESS,
3406                  &spr_read_generic, &spr_write_generic,
3407                  0x00000000);
3408     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3409                  SPR_NOACCESS, SPR_NOACCESS,
3410                  &spr_read_generic, &spr_write_generic,
3411                  0x00000000);
3412     /* XXX : not implemented */
3413     spr_register(env, SPR_440_CCR1, "CCR1",
3414                  SPR_NOACCESS, SPR_NOACCESS,
3415                  &spr_read_generic, &spr_write_generic,
3416                  0x00000000);
3417     /* Memory management */
3418 #if !defined(CONFIG_USER_ONLY)
3419     env->nb_tlb = 64;
3420     env->nb_ways = 1;
3421     env->id_tlbs = 0;
3422 #endif
3423     init_excp_BookE(env);
3424     env->dcache_line_size = 32;
3425     env->icache_line_size = 32;
3426     /* XXX: TODO: allocate internal IRQ controller */
3427 }
3428
3429 /* PowerPC 440 GP                                                            */
3430 #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3431                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3432                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3433                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3434                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3435                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3436                               PPC_440_SPEC)
3437 #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3438 #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3439 #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3440 #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3441 #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3442 #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3443                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3444 #define check_pow_440GP      check_pow_nocheck
3445
3446 __attribute__ (( unused ))
3447 static void init_proc_440GP (CPUPPCState *env)
3448 {
3449     /* Time base */
3450     gen_tbl(env);
3451     gen_spr_BookE(env, 0x000000000000FFFFULL);
3452     gen_spr_440(env);
3453     gen_spr_usprgh(env);
3454     /* Processor identification */
3455     spr_register(env, SPR_BOOKE_PIR, "PIR",
3456                  SPR_NOACCESS, SPR_NOACCESS,
3457                  &spr_read_generic, &spr_write_pir,
3458                  0x00000000);
3459     /* XXX : not implemented */
3460     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3461                  SPR_NOACCESS, SPR_NOACCESS,
3462                  &spr_read_generic, &spr_write_generic,
3463                  0x00000000);
3464     /* XXX : not implemented */
3465     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3466                  SPR_NOACCESS, SPR_NOACCESS,
3467                  &spr_read_generic, &spr_write_generic,
3468                  0x00000000);
3469     /* XXX : not implemented */
3470     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3471                  SPR_NOACCESS, SPR_NOACCESS,
3472                  &spr_read_generic, &spr_write_generic,
3473                  0x00000000);
3474     /* XXX : not implemented */
3475     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3476                  SPR_NOACCESS, SPR_NOACCESS,
3477                  &spr_read_generic, &spr_write_generic,
3478                  0x00000000);
3479     /* Memory management */
3480 #if !defined(CONFIG_USER_ONLY)
3481     env->nb_tlb = 64;
3482     env->nb_ways = 1;
3483     env->id_tlbs = 0;
3484 #endif
3485     init_excp_BookE(env);
3486     env->dcache_line_size = 32;
3487     env->icache_line_size = 32;
3488     /* XXX: TODO: allocate internal IRQ controller */
3489 }
3490
3491 /* PowerPC 440x4                                                             */
3492 #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3493                               PPC_DCR | PPC_WRTEE |                           \
3494                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3495                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3496                               PPC_MEM_TLBSYNC |                               \
3497                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3498                               PPC_440_SPEC)
3499 #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3500 #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3501 #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3502 #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3503 #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3504 #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3505                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3506 #define check_pow_440x4      check_pow_nocheck
3507
3508 __attribute__ (( unused ))
3509 static void init_proc_440x4 (CPUPPCState *env)
3510 {
3511     /* Time base */
3512     gen_tbl(env);
3513     gen_spr_BookE(env, 0x000000000000FFFFULL);
3514     gen_spr_440(env);
3515     gen_spr_usprgh(env);
3516     /* Processor identification */
3517     spr_register(env, SPR_BOOKE_PIR, "PIR",
3518                  SPR_NOACCESS, SPR_NOACCESS,
3519                  &spr_read_generic, &spr_write_pir,
3520                  0x00000000);
3521     /* XXX : not implemented */
3522     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3523                  SPR_NOACCESS, SPR_NOACCESS,
3524                  &spr_read_generic, &spr_write_generic,
3525                  0x00000000);
3526     /* XXX : not implemented */
3527     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3528                  SPR_NOACCESS, SPR_NOACCESS,
3529                  &spr_read_generic, &spr_write_generic,
3530                  0x00000000);
3531     /* XXX : not implemented */
3532     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3533                  SPR_NOACCESS, SPR_NOACCESS,
3534                  &spr_read_generic, &spr_write_generic,
3535                  0x00000000);
3536     /* XXX : not implemented */
3537     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3538                  SPR_NOACCESS, SPR_NOACCESS,
3539                  &spr_read_generic, &spr_write_generic,
3540                  0x00000000);
3541     /* Memory management */
3542 #if !defined(CONFIG_USER_ONLY)
3543     env->nb_tlb = 64;
3544     env->nb_ways = 1;
3545     env->id_tlbs = 0;
3546 #endif
3547     init_excp_BookE(env);
3548     env->dcache_line_size = 32;
3549     env->icache_line_size = 32;
3550     /* XXX: TODO: allocate internal IRQ controller */
3551 }
3552
3553 /* PowerPC 440x5                                                             */
3554 #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3555                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3556                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3557                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3558                               PPC_MEM_TLBSYNC |                               \
3559                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3560                               PPC_440_SPEC)
3561 #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3562 #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3563 #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3564 #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3565 #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3566 #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3567                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3568 #define check_pow_440x5      check_pow_nocheck
3569
3570 __attribute__ (( unused ))
3571 static void init_proc_440x5 (CPUPPCState *env)
3572 {
3573     /* Time base */
3574     gen_tbl(env);
3575     gen_spr_BookE(env, 0x000000000000FFFFULL);
3576     gen_spr_440(env);
3577     gen_spr_usprgh(env);
3578     /* Processor identification */
3579     spr_register(env, SPR_BOOKE_PIR, "PIR",
3580                  SPR_NOACCESS, SPR_NOACCESS,
3581                  &spr_read_generic, &spr_write_pir,
3582                  0x00000000);
3583     /* XXX : not implemented */
3584     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3585                  SPR_NOACCESS, SPR_NOACCESS,
3586                  &spr_read_generic, &spr_write_generic,
3587                  0x00000000);
3588     /* XXX : not implemented */
3589     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3590                  SPR_NOACCESS, SPR_NOACCESS,
3591                  &spr_read_generic, &spr_write_generic,
3592                  0x00000000);
3593     /* XXX : not implemented */
3594     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3595                  SPR_NOACCESS, SPR_NOACCESS,
3596                  &spr_read_generic, &spr_write_generic,
3597                  0x00000000);
3598     /* XXX : not implemented */
3599     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3600                  SPR_NOACCESS, SPR_NOACCESS,
3601                  &spr_read_generic, &spr_write_generic,
3602                  0x00000000);
3603     /* XXX : not implemented */
3604     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3605                  SPR_NOACCESS, SPR_NOACCESS,
3606                  &spr_read_generic, &spr_write_generic,
3607                  0x00000000);
3608     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3609                  SPR_NOACCESS, SPR_NOACCESS,
3610                  &spr_read_generic, &spr_write_generic,
3611                  0x00000000);
3612     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3613                  SPR_NOACCESS, SPR_NOACCESS,
3614                  &spr_read_generic, &spr_write_generic,
3615                  0x00000000);
3616     /* XXX : not implemented */
3617     spr_register(env, SPR_440_CCR1, "CCR1",
3618                  SPR_NOACCESS, SPR_NOACCESS,
3619                  &spr_read_generic, &spr_write_generic,
3620                  0x00000000);
3621     /* Memory management */
3622 #if !defined(CONFIG_USER_ONLY)
3623     env->nb_tlb = 64;
3624     env->nb_ways = 1;
3625     env->id_tlbs = 0;
3626 #endif
3627     init_excp_BookE(env);
3628     env->dcache_line_size = 32;
3629     env->icache_line_size = 32;
3630     /* XXX: TODO: allocate internal IRQ controller */
3631 }
3632
3633 /* PowerPC 460 (guessed)                                                     */
3634 #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3635                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3636                               PPC_WRTEE | PPC_MFAPIDI |                       \
3637                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3638                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3639                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3640                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3641                               PPC_440_SPEC)
3642 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3643 #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3644 #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3645 #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3646 #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3647 #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3648                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3649 #define check_pow_460        check_pow_nocheck
3650
3651 __attribute__ (( unused ))
3652 static void init_proc_460 (CPUPPCState *env)
3653 {
3654     /* Time base */
3655     gen_tbl(env);
3656     gen_spr_BookE(env, 0x000000000000FFFFULL);
3657     gen_spr_440(env);
3658     gen_spr_usprgh(env);
3659     /* Processor identification */
3660     spr_register(env, SPR_BOOKE_PIR, "PIR",
3661                  SPR_NOACCESS, SPR_NOACCESS,
3662                  &spr_read_generic, &spr_write_pir,
3663                  0x00000000);
3664     /* XXX : not implemented */
3665     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3666                  SPR_NOACCESS, SPR_NOACCESS,
3667                  &spr_read_generic, &spr_write_generic,
3668                  0x00000000);
3669     /* XXX : not implemented */
3670     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3671                  SPR_NOACCESS, SPR_NOACCESS,
3672                  &spr_read_generic, &spr_write_generic,
3673                  0x00000000);
3674     /* XXX : not implemented */
3675     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3676                  SPR_NOACCESS, SPR_NOACCESS,
3677                  &spr_read_generic, &spr_write_generic,
3678                  0x00000000);
3679     /* XXX : not implemented */
3680     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3681                  SPR_NOACCESS, SPR_NOACCESS,
3682                  &spr_read_generic, &spr_write_generic,
3683                  0x00000000);
3684     /* XXX : not implemented */
3685     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3686                  SPR_NOACCESS, SPR_NOACCESS,
3687                  &spr_read_generic, &spr_write_generic,
3688                  0x00000000);
3689     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3690                  SPR_NOACCESS, SPR_NOACCESS,
3691                  &spr_read_generic, &spr_write_generic,
3692                  0x00000000);
3693     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3694                  SPR_NOACCESS, SPR_NOACCESS,
3695                  &spr_read_generic, &spr_write_generic,
3696                  0x00000000);
3697     /* XXX : not implemented */
3698     spr_register(env, SPR_440_CCR1, "CCR1",
3699                  SPR_NOACCESS, SPR_NOACCESS,
3700                  &spr_read_generic, &spr_write_generic,
3701                  0x00000000);
3702     /* XXX : not implemented */
3703     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3704                  &spr_read_generic, &spr_write_generic,
3705                  &spr_read_generic, &spr_write_generic,
3706                  0x00000000);
3707     /* Memory management */
3708 #if !defined(CONFIG_USER_ONLY)
3709     env->nb_tlb = 64;
3710     env->nb_ways = 1;
3711     env->id_tlbs = 0;
3712 #endif
3713     init_excp_BookE(env);
3714     env->dcache_line_size = 32;
3715     env->icache_line_size = 32;
3716     /* XXX: TODO: allocate internal IRQ controller */
3717 }
3718
3719 /* PowerPC 460F (guessed)                                                    */
3720 #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3721                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3722                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3723                               PPC_FLOAT_STFIWX |                              \
3724                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3725                               PPC_WRTEE | PPC_MFAPIDI |                       \
3726                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3727                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3728                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3729                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3730                               PPC_440_SPEC)
3731 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3732 #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3733 #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3734 #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3735 #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3736 #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3737                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3738 #define check_pow_460F       check_pow_nocheck
3739
3740 __attribute__ (( unused ))
3741 static void init_proc_460F (CPUPPCState *env)
3742 {
3743     /* Time base */
3744     gen_tbl(env);
3745     gen_spr_BookE(env, 0x000000000000FFFFULL);
3746     gen_spr_440(env);
3747     gen_spr_usprgh(env);
3748     /* Processor identification */
3749     spr_register(env, SPR_BOOKE_PIR, "PIR",
3750                  SPR_NOACCESS, SPR_NOACCESS,
3751                  &spr_read_generic, &spr_write_pir,
3752                  0x00000000);
3753     /* XXX : not implemented */
3754     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3755                  SPR_NOACCESS, SPR_NOACCESS,
3756                  &spr_read_generic, &spr_write_generic,
3757                  0x00000000);
3758     /* XXX : not implemented */
3759     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3760                  SPR_NOACCESS, SPR_NOACCESS,
3761                  &spr_read_generic, &spr_write_generic,
3762                  0x00000000);
3763     /* XXX : not implemented */
3764     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3765                  SPR_NOACCESS, SPR_NOACCESS,
3766                  &spr_read_generic, &spr_write_generic,
3767                  0x00000000);
3768     /* XXX : not implemented */
3769     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3770                  SPR_NOACCESS, SPR_NOACCESS,
3771                  &spr_read_generic, &spr_write_generic,
3772                  0x00000000);
3773     /* XXX : not implemented */
3774     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3775                  SPR_NOACCESS, SPR_NOACCESS,
3776                  &spr_read_generic, &spr_write_generic,
3777                  0x00000000);
3778     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3779                  SPR_NOACCESS, SPR_NOACCESS,
3780                  &spr_read_generic, &spr_write_generic,
3781                  0x00000000);
3782     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3783                  SPR_NOACCESS, SPR_NOACCESS,
3784                  &spr_read_generic, &spr_write_generic,
3785                  0x00000000);
3786     /* XXX : not implemented */
3787     spr_register(env, SPR_440_CCR1, "CCR1",
3788                  SPR_NOACCESS, SPR_NOACCESS,
3789                  &spr_read_generic, &spr_write_generic,
3790                  0x00000000);
3791     /* XXX : not implemented */
3792     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3793                  &spr_read_generic, &spr_write_generic,
3794                  &spr_read_generic, &spr_write_generic,
3795                  0x00000000);
3796     /* Memory management */
3797 #if !defined(CONFIG_USER_ONLY)
3798     env->nb_tlb = 64;
3799     env->nb_ways = 1;
3800     env->id_tlbs = 0;
3801 #endif
3802     init_excp_BookE(env);
3803     env->dcache_line_size = 32;
3804     env->icache_line_size = 32;
3805     /* XXX: TODO: allocate internal IRQ controller */
3806 }
3807
3808 /* Freescale 5xx cores (aka RCPU) */
3809 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3810                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3811                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3812                               PPC_MFTB)
3813 #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3814 #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3815 #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3816 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3817 #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3818 #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3819                               POWERPC_FLAG_BUS_CLK)
3820 #define check_pow_MPC5xx     check_pow_none
3821
3822 __attribute__ (( unused ))
3823 static void init_proc_MPC5xx (CPUPPCState *env)
3824 {
3825     /* Time base */
3826     gen_tbl(env);
3827     gen_spr_5xx_8xx(env);
3828     gen_spr_5xx(env);
3829     init_excp_MPC5xx(env);
3830     env->dcache_line_size = 32;
3831     env->icache_line_size = 32;
3832     /* XXX: TODO: allocate internal IRQ controller */
3833 }
3834
3835 /* Freescale 8xx cores (aka PowerQUICC) */
3836 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3837                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3838                               PPC_CACHE_ICBI | PPC_MFTB)
3839 #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3840 #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3841 #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3842 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3843 #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3844 #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3845                               POWERPC_FLAG_BUS_CLK)
3846 #define check_pow_MPC8xx     check_pow_none
3847
3848 __attribute__ (( unused ))
3849 static void init_proc_MPC8xx (CPUPPCState *env)
3850 {
3851     /* Time base */
3852     gen_tbl(env);
3853     gen_spr_5xx_8xx(env);
3854     gen_spr_8xx(env);
3855     init_excp_MPC8xx(env);
3856     env->dcache_line_size = 32;
3857     env->icache_line_size = 32;
3858     /* XXX: TODO: allocate internal IRQ controller */
3859 }
3860
3861 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3862 /* PowerPC G2                                                                */
3863 #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3864                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3865                               PPC_FLOAT_STFIWX |                              \
3866                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3867                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3868                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3869                               PPC_SEGMENT | PPC_EXTERN)
3870 #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3871 #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3872 //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3873 #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3874 #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3875 #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3876                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3877 #define check_pow_G2         check_pow_hid0
3878
3879 static void init_proc_G2 (CPUPPCState *env)
3880 {
3881     gen_spr_ne_601(env);
3882     gen_spr_G2_755(env);
3883     gen_spr_G2(env);
3884     /* Time base */
3885     gen_tbl(env);
3886     /* External access control */
3887     /* XXX : not implemented */
3888     spr_register(env, SPR_EAR, "EAR",
3889                  SPR_NOACCESS, SPR_NOACCESS,
3890                  &spr_read_generic, &spr_write_generic,
3891                  0x00000000);
3892     /* Hardware implementation register */
3893     /* XXX : not implemented */
3894     spr_register(env, SPR_HID0, "HID0",
3895                  SPR_NOACCESS, SPR_NOACCESS,
3896                  &spr_read_generic, &spr_write_generic,
3897                  0x00000000);
3898     /* XXX : not implemented */
3899     spr_register(env, SPR_HID1, "HID1",
3900                  SPR_NOACCESS, SPR_NOACCESS,
3901                  &spr_read_generic, &spr_write_generic,
3902                  0x00000000);
3903     /* XXX : not implemented */
3904     spr_register(env, SPR_HID2, "HID2",
3905                  SPR_NOACCESS, SPR_NOACCESS,
3906                  &spr_read_generic, &spr_write_generic,
3907                  0x00000000);
3908     /* Memory management */
3909     gen_low_BATs(env);
3910     gen_high_BATs(env);
3911     gen_6xx_7xx_soft_tlb(env, 64, 2);
3912     init_excp_G2(env);
3913     env->dcache_line_size = 32;
3914     env->icache_line_size = 32;
3915     /* Allocate hardware IRQ controller */
3916     ppc6xx_irq_init(env);
3917 }
3918
3919 /* PowerPC G2LE                                                              */
3920 #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3921                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3922                               PPC_FLOAT_STFIWX |                              \
3923                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3924                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3925                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3926                               PPC_SEGMENT | PPC_EXTERN)
3927 #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3928 #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3929 #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3930 #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3931 #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3932 #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3933                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3934 #define check_pow_G2LE       check_pow_hid0
3935
3936 static void init_proc_G2LE (CPUPPCState *env)
3937 {
3938     gen_spr_ne_601(env);
3939     gen_spr_G2_755(env);
3940     gen_spr_G2(env);
3941     /* Time base */
3942     gen_tbl(env);
3943     /* External access control */
3944     /* XXX : not implemented */
3945     spr_register(env, SPR_EAR, "EAR",
3946                  SPR_NOACCESS, SPR_NOACCESS,
3947                  &spr_read_generic, &spr_write_generic,
3948                  0x00000000);
3949     /* Hardware implementation register */
3950     /* XXX : not implemented */
3951     spr_register(env, SPR_HID0, "HID0",
3952                  SPR_NOACCESS, SPR_NOACCESS,
3953                  &spr_read_generic, &spr_write_generic,
3954                  0x00000000);
3955     /* XXX : not implemented */
3956     spr_register(env, SPR_HID1, "HID1",
3957                  SPR_NOACCESS, SPR_NOACCESS,
3958                  &spr_read_generic, &spr_write_generic,
3959                  0x00000000);
3960     /* XXX : not implemented */
3961     spr_register(env, SPR_HID2, "HID2",
3962                  SPR_NOACCESS, SPR_NOACCESS,
3963                  &spr_read_generic, &spr_write_generic,
3964                  0x00000000);
3965     /* Memory management */
3966     gen_low_BATs(env);
3967     gen_high_BATs(env);
3968     gen_6xx_7xx_soft_tlb(env, 64, 2);
3969     init_excp_G2(env);
3970     env->dcache_line_size = 32;
3971     env->icache_line_size = 32;
3972     /* Allocate hardware IRQ controller */
3973     ppc6xx_irq_init(env);
3974 }
3975
3976 /* e200 core                                                                 */
3977 /* XXX: unimplemented instructions:
3978  * dcblc
3979  * dcbtlst
3980  * dcbtstls
3981  * icblc
3982  * icbtls
3983  * tlbivax
3984  * all SPE multiply-accumulate instructions
3985  */
3986 #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
3987                               PPC_SPE | PPC_SPE_SINGLE |                      \
3988                               PPC_WRTEE | PPC_RFDI |                          \
3989                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
3990                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3991                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
3992                               PPC_BOOKE)
3993 #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
3994 #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
3995 #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
3996 #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
3997 #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
3998 #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
3999                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4000                               POWERPC_FLAG_BUS_CLK)
4001 #define check_pow_e200       check_pow_hid0
4002
4003 __attribute__ (( unused ))
4004 static void init_proc_e200 (CPUPPCState *env)
4005 {
4006     /* Time base */
4007     gen_tbl(env);
4008     gen_spr_BookE(env, 0x000000070000FFFFULL);
4009     /* XXX : not implemented */
4010     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4011                  SPR_NOACCESS, SPR_NOACCESS,
4012                  &spr_read_generic, &spr_write_generic,
4013                  0x00000000);
4014     /* Memory management */
4015     gen_spr_BookE_FSL(env, 0x0000005D);
4016     /* XXX : not implemented */
4017     spr_register(env, SPR_HID0, "HID0",
4018                  SPR_NOACCESS, SPR_NOACCESS,
4019                  &spr_read_generic, &spr_write_generic,
4020                  0x00000000);
4021     /* XXX : not implemented */
4022     spr_register(env, SPR_HID1, "HID1",
4023                  SPR_NOACCESS, SPR_NOACCESS,
4024                  &spr_read_generic, &spr_write_generic,
4025                  0x00000000);
4026     /* XXX : not implemented */
4027     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4028                  SPR_NOACCESS, SPR_NOACCESS,
4029                  &spr_read_generic, &spr_write_generic,
4030                  0x00000000);
4031     /* XXX : not implemented */
4032     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4033                  SPR_NOACCESS, SPR_NOACCESS,
4034                  &spr_read_generic, &spr_write_generic,
4035                  0x00000000);
4036     /* XXX : not implemented */
4037     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4038                  SPR_NOACCESS, SPR_NOACCESS,
4039                  &spr_read_generic, &spr_write_generic,
4040                  0x00000000);
4041     /* XXX : not implemented */
4042     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4043                  SPR_NOACCESS, SPR_NOACCESS,
4044                  &spr_read_generic, &spr_write_generic,
4045                  0x00000000);
4046     /* XXX : not implemented */
4047     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4048                  SPR_NOACCESS, SPR_NOACCESS,
4049                  &spr_read_generic, &spr_write_generic,
4050                  0x00000000);
4051     /* XXX : not implemented */
4052     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4053                  SPR_NOACCESS, SPR_NOACCESS,
4054                  &spr_read_generic, &spr_write_generic,
4055                  0x00000000);
4056     /* XXX : not implemented */
4057     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4058                  SPR_NOACCESS, SPR_NOACCESS,
4059                  &spr_read_generic, &spr_write_generic,
4060                  0x00000000);
4061     /* XXX : not implemented */
4062     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4063                  SPR_NOACCESS, SPR_NOACCESS,
4064                  &spr_read_generic, &spr_write_generic,
4065                  0x00000000);
4066     /* XXX : not implemented */
4067     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4068                  SPR_NOACCESS, SPR_NOACCESS,
4069                  &spr_read_generic, &spr_write_generic,
4070                  0x00000000);
4071     /* XXX : not implemented */
4072     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4073                  SPR_NOACCESS, SPR_NOACCESS,
4074                  &spr_read_generic, &spr_write_generic,
4075                  0x00000000);
4076     /* XXX : not implemented */
4077     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4078                  SPR_NOACCESS, SPR_NOACCESS,
4079                  &spr_read_generic, &spr_write_generic,
4080                  0x00000000);
4081     /* XXX : not implemented */
4082     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4083                  SPR_NOACCESS, SPR_NOACCESS,
4084                  &spr_read_generic, &spr_write_generic,
4085                  0x00000000);
4086     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4087                  SPR_NOACCESS, SPR_NOACCESS,
4088                  &spr_read_generic, &spr_write_generic,
4089                  0x00000000);
4090     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4091                  SPR_NOACCESS, SPR_NOACCESS,
4092                  &spr_read_generic, &spr_write_generic,
4093                  0x00000000);
4094 #if !defined(CONFIG_USER_ONLY)
4095     env->nb_tlb = 64;
4096     env->nb_ways = 1;
4097     env->id_tlbs = 0;
4098 #endif
4099     init_excp_e200(env);
4100     env->dcache_line_size = 32;
4101     env->icache_line_size = 32;
4102     /* XXX: TODO: allocate internal IRQ controller */
4103 }
4104
4105 /* e300 core                                                                 */
4106 #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4107                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4108                               PPC_FLOAT_STFIWX |                              \
4109                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4110                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4111                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4112                               PPC_SEGMENT | PPC_EXTERN)
4113 #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4114 #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4115 #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4116 #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4117 #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4118 #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4119                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4120 #define check_pow_e300       check_pow_hid0
4121
4122 __attribute__ (( unused ))
4123 static void init_proc_e300 (CPUPPCState *env)
4124 {
4125     gen_spr_ne_601(env);
4126     gen_spr_603(env);
4127     /* Time base */
4128     gen_tbl(env);
4129     /* hardware implementation registers */
4130     /* XXX : not implemented */
4131     spr_register(env, SPR_HID0, "HID0",
4132                  SPR_NOACCESS, SPR_NOACCESS,
4133                  &spr_read_generic, &spr_write_generic,
4134                  0x00000000);
4135     /* XXX : not implemented */
4136     spr_register(env, SPR_HID1, "HID1",
4137                  SPR_NOACCESS, SPR_NOACCESS,
4138                  &spr_read_generic, &spr_write_generic,
4139                  0x00000000);
4140     /* Memory management */
4141     gen_low_BATs(env);
4142     gen_6xx_7xx_soft_tlb(env, 64, 2);
4143     init_excp_603(env);
4144     env->dcache_line_size = 32;
4145     env->icache_line_size = 32;
4146     /* Allocate hardware IRQ controller */
4147     ppc6xx_irq_init(env);
4148 }
4149
4150 /* e500 core                                                               */
4151 #define POWERPC_INSNS_e500   (PPC_INSNS_BASE | PPC_ISEL |             \
4152                               PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
4153                               PPC_WRTEE | PPC_RFDI |                  \
4154                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4155                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4156                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4157                               PPC_BOOKE)
4158 #define POWERPC_MSRM_e500    (0x000000000606FF30ULL)
4159 #define POWERPC_MMU_e500     (POWERPC_MMU_BOOKE_FSL)
4160 #define POWERPC_EXCP_e500    (POWERPC_EXCP_BOOKE)
4161 #define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
4162 #define POWERPC_BFDM_e500    (bfd_mach_ppc_860)
4163 #define POWERPC_FLAG_e500    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4164                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4165                               POWERPC_FLAG_BUS_CLK)
4166 #define check_pow_e500       check_pow_hid0
4167
4168 __attribute__ (( unused ))
4169 static void init_proc_e500 (CPUPPCState *env)
4170 {
4171     /* Time base */
4172     gen_tbl(env);
4173     gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4174     /* Processor identification */
4175     spr_register(env, SPR_BOOKE_PIR, "PIR",
4176                  SPR_NOACCESS, SPR_NOACCESS,
4177                  &spr_read_generic, &spr_write_pir,
4178                  0x00000000);
4179     /* XXX : not implemented */
4180     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4181                  SPR_NOACCESS, SPR_NOACCESS,
4182                  &spr_read_generic, &spr_write_generic,
4183                  0x00000000);
4184     /* Memory management */
4185 #if !defined(CONFIG_USER_ONLY)
4186     env->nb_pids = 3;
4187 #endif
4188     gen_spr_BookE_FSL(env, 0x0000005F);
4189     /* XXX : not implemented */
4190     spr_register(env, SPR_HID0, "HID0",
4191                  SPR_NOACCESS, SPR_NOACCESS,
4192                  &spr_read_generic, &spr_write_generic,
4193                  0x00000000);
4194     /* XXX : not implemented */
4195     spr_register(env, SPR_HID1, "HID1",
4196                  SPR_NOACCESS, SPR_NOACCESS,
4197                  &spr_read_generic, &spr_write_generic,
4198                  0x00000000);
4199     /* XXX : not implemented */
4200     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4201                  SPR_NOACCESS, SPR_NOACCESS,
4202                  &spr_read_generic, &spr_write_generic,
4203                  0x00000000);
4204     /* XXX : not implemented */
4205     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4206                  SPR_NOACCESS, SPR_NOACCESS,
4207                  &spr_read_generic, &spr_write_generic,
4208                  0x00000000);
4209     /* XXX : not implemented */
4210     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4211                  SPR_NOACCESS, SPR_NOACCESS,
4212                  &spr_read_generic, &spr_write_generic,
4213                  0x00000000);
4214     /* XXX : not implemented */
4215     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4216                  SPR_NOACCESS, SPR_NOACCESS,
4217                  &spr_read_generic, &spr_write_generic,
4218                  0x00000000);
4219     /* XXX : not implemented */
4220     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4221                  SPR_NOACCESS, SPR_NOACCESS,
4222                  &spr_read_generic, &spr_write_generic,
4223                  0x00000000);
4224     /* XXX : not implemented */
4225     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4226                  SPR_NOACCESS, SPR_NOACCESS,
4227                  &spr_read_generic, &spr_write_generic,
4228                  0x00000000);
4229     /* XXX : not implemented */
4230     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4231                  SPR_NOACCESS, SPR_NOACCESS,
4232                  &spr_read_generic, &spr_write_generic,
4233                  0x00000000);
4234     /* XXX : not implemented */
4235     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4236                  SPR_NOACCESS, SPR_NOACCESS,
4237                  &spr_read_generic, &spr_write_generic,
4238                  0x00000000);
4239     /* XXX : not implemented */
4240     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4241                  SPR_NOACCESS, SPR_NOACCESS,
4242                  &spr_read_generic, &spr_write_generic,
4243                  0x00000000);
4244     /* XXX : not implemented */
4245     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4246                  SPR_NOACCESS, SPR_NOACCESS,
4247                  &spr_read_generic, &spr_write_generic,
4248                  0x00000000);
4249     /* XXX : not implemented */
4250     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4251                  SPR_NOACCESS, SPR_NOACCESS,
4252                  &spr_read_generic, &spr_write_generic,
4253                  0x00000000);
4254     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4255                  SPR_NOACCESS, SPR_NOACCESS,
4256                  &spr_read_generic, &spr_write_generic,
4257                  0x00000000);
4258     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4259                  SPR_NOACCESS, SPR_NOACCESS,
4260                  &spr_read_generic, &spr_write_generic,
4261                  0x00000000);
4262 #if !defined(CONFIG_USER_ONLY)
4263     env->nb_tlb = 64;
4264     env->nb_ways = 1;
4265     env->id_tlbs = 0;
4266 #endif
4267     init_excp_e200(env);
4268     env->dcache_line_size = 32;
4269     env->icache_line_size = 32;
4270     /* XXX: TODO: allocate internal IRQ controller */
4271 }
4272
4273 /* Non-embedded PowerPC                                                      */
4274
4275 /* POWER : same as 601, without mfmsr, mfsr                                  */
4276 #if defined(TODO)
4277 #define POWERPC_INSNS_POWER  (XXX_TODO)
4278 /* POWER RSC (from RAD6000) */
4279 #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4280 #endif /* TODO */
4281
4282 /* PowerPC 601                                                               */
4283 #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4284                               PPC_FLOAT |                                     \
4285                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4286                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4287                               PPC_SEGMENT | PPC_EXTERN)
4288 #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4289 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4290 //#define POWERPC_MMU_601      (POWERPC_MMU_601)
4291 //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4292 #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4293 #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4294 #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4295 #define check_pow_601        check_pow_none
4296
4297 static void init_proc_601 (CPUPPCState *env)
4298 {
4299     gen_spr_ne_601(env);
4300     gen_spr_601(env);
4301     /* Hardware implementation registers */
4302     /* XXX : not implemented */
4303     spr_register(env, SPR_HID0, "HID0",
4304                  SPR_NOACCESS, SPR_NOACCESS,
4305                  &spr_read_generic, &spr_write_hid0_601,
4306                  0x80010080);
4307     /* XXX : not implemented */
4308     spr_register(env, SPR_HID1, "HID1",
4309                  SPR_NOACCESS, SPR_NOACCESS,
4310                  &spr_read_generic, &spr_write_generic,
4311                  0x00000000);
4312     /* XXX : not implemented */
4313     spr_register(env, SPR_601_HID2, "HID2",
4314                  SPR_NOACCESS, SPR_NOACCESS,
4315                  &spr_read_generic, &spr_write_generic,
4316                  0x00000000);
4317     /* XXX : not implemented */
4318     spr_register(env, SPR_601_HID5, "HID5",
4319                  SPR_NOACCESS, SPR_NOACCESS,
4320                  &spr_read_generic, &spr_write_generic,
4321                  0x00000000);
4322     /* Memory management */
4323     init_excp_601(env);
4324     /* XXX: beware that dcache line size is 64
4325      *      but dcbz uses 32 bytes "sectors"
4326      * XXX: this breaks clcs instruction !
4327      */
4328     env->dcache_line_size = 32;
4329     env->icache_line_size = 64;
4330     /* Allocate hardware IRQ controller */
4331     ppc6xx_irq_init(env);
4332 }
4333
4334 /* PowerPC 601v                                                              */
4335 #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4336                               PPC_FLOAT |                                     \
4337                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4338                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4339                               PPC_SEGMENT | PPC_EXTERN)
4340 #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4341 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4342 #define POWERPC_MMU_601v     (POWERPC_MMU_601)
4343 #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4344 #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4345 #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4346 #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4347 #define check_pow_601v       check_pow_none
4348
4349 static void init_proc_601v (CPUPPCState *env)
4350 {
4351     init_proc_601(env);
4352     /* XXX : not implemented */
4353     spr_register(env, SPR_601_HID15, "HID15",
4354                  SPR_NOACCESS, SPR_NOACCESS,
4355                  &spr_read_generic, &spr_write_generic,
4356                  0x00000000);
4357 }
4358
4359 /* PowerPC 602                                                               */
4360 #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4361                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4362                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4363                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4364                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4365                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4366                               PPC_SEGMENT | PPC_602_SPEC)
4367 #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4368 /* XXX: 602 MMU is quite specific. Should add a special case */
4369 #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4370 //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4371 #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4372 #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4373 #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4374                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4375 #define check_pow_602        check_pow_hid0
4376
4377 static void init_proc_602 (CPUPPCState *env)
4378 {
4379     gen_spr_ne_601(env);
4380     gen_spr_602(env);
4381     /* Time base */
4382     gen_tbl(env);
4383     /* hardware implementation registers */
4384     /* XXX : not implemented */
4385     spr_register(env, SPR_HID0, "HID0",
4386                  SPR_NOACCESS, SPR_NOACCESS,
4387                  &spr_read_generic, &spr_write_generic,
4388                  0x00000000);
4389     /* XXX : not implemented */
4390     spr_register(env, SPR_HID1, "HID1",
4391                  SPR_NOACCESS, SPR_NOACCESS,
4392                  &spr_read_generic, &spr_write_generic,
4393                  0x00000000);
4394     /* Memory management */
4395     gen_low_BATs(env);
4396     gen_6xx_7xx_soft_tlb(env, 64, 2);
4397     init_excp_602(env);
4398     env->dcache_line_size = 32;
4399     env->icache_line_size = 32;
4400     /* Allocate hardware IRQ controller */
4401     ppc6xx_irq_init(env);
4402 }
4403
4404 /* PowerPC 603                                                               */
4405 #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4406                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4407                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4408                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4409                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4410                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4411                               PPC_SEGMENT | PPC_EXTERN)
4412 #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4413 #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4414 //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4415 #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4416 #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4417 #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4418                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4419 #define check_pow_603        check_pow_hid0
4420
4421 static void init_proc_603 (CPUPPCState *env)
4422 {
4423     gen_spr_ne_601(env);
4424     gen_spr_603(env);
4425     /* Time base */
4426     gen_tbl(env);
4427     /* hardware implementation registers */
4428     /* XXX : not implemented */
4429     spr_register(env, SPR_HID0, "HID0",
4430                  SPR_NOACCESS, SPR_NOACCESS,
4431                  &spr_read_generic, &spr_write_generic,
4432                  0x00000000);
4433     /* XXX : not implemented */
4434     spr_register(env, SPR_HID1, "HID1",
4435                  SPR_NOACCESS, SPR_NOACCESS,
4436                  &spr_read_generic, &spr_write_generic,
4437                  0x00000000);
4438     /* Memory management */
4439     gen_low_BATs(env);
4440     gen_6xx_7xx_soft_tlb(env, 64, 2);
4441     init_excp_603(env);
4442     env->dcache_line_size = 32;
4443     env->icache_line_size = 32;
4444     /* Allocate hardware IRQ controller */
4445     ppc6xx_irq_init(env);
4446 }
4447
4448 /* PowerPC 603e                                                              */
4449 #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4450                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4451                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4452                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4453                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4454                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4455                               PPC_SEGMENT | PPC_EXTERN)
4456 #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4457 #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4458 //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4459 #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4460 #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4461 #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4462                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4463 #define check_pow_603E       check_pow_hid0
4464
4465 static void init_proc_603E (CPUPPCState *env)
4466 {
4467     gen_spr_ne_601(env);
4468     gen_spr_603(env);
4469     /* Time base */
4470     gen_tbl(env);
4471     /* hardware implementation registers */
4472     /* XXX : not implemented */
4473     spr_register(env, SPR_HID0, "HID0",
4474                  SPR_NOACCESS, SPR_NOACCESS,
4475                  &spr_read_generic, &spr_write_generic,
4476                  0x00000000);
4477     /* XXX : not implemented */
4478     spr_register(env, SPR_HID1, "HID1",
4479                  SPR_NOACCESS, SPR_NOACCESS,
4480                  &spr_read_generic, &spr_write_generic,
4481                  0x00000000);
4482     /* XXX : not implemented */
4483     spr_register(env, SPR_IABR, "IABR",
4484                  SPR_NOACCESS, SPR_NOACCESS,
4485                  &spr_read_generic, &spr_write_generic,
4486                  0x00000000);
4487     /* Memory management */
4488     gen_low_BATs(env);
4489     gen_6xx_7xx_soft_tlb(env, 64, 2);
4490     init_excp_603(env);
4491     env->dcache_line_size = 32;
4492     env->icache_line_size = 32;
4493     /* Allocate hardware IRQ controller */
4494     ppc6xx_irq_init(env);
4495 }
4496
4497 /* PowerPC 604                                                               */
4498 #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4499                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4500                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4501                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4502                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4503                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4504                               PPC_SEGMENT | PPC_EXTERN)
4505 #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4506 #define POWERPC_MMU_604      (POWERPC_MMU_32B)
4507 //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4508 #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4509 #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4510 #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4511                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4512 #define check_pow_604        check_pow_nocheck
4513
4514 static void init_proc_604 (CPUPPCState *env)
4515 {
4516     gen_spr_ne_601(env);
4517     gen_spr_604(env);
4518     /* Time base */
4519     gen_tbl(env);
4520     /* Hardware implementation registers */
4521     /* XXX : not implemented */
4522     spr_register(env, SPR_HID0, "HID0",
4523                  SPR_NOACCESS, SPR_NOACCESS,
4524                  &spr_read_generic, &spr_write_generic,
4525                  0x00000000);
4526     /* Memory management */
4527     gen_low_BATs(env);
4528     init_excp_604(env);
4529     env->dcache_line_size = 32;
4530     env->icache_line_size = 32;
4531     /* Allocate hardware IRQ controller */
4532     ppc6xx_irq_init(env);
4533 }
4534
4535 /* PowerPC 604E                                                              */
4536 #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4537                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4538                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4539                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4540                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4541                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4542                               PPC_SEGMENT | PPC_EXTERN)
4543 #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4544 #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4545 #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4546 #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4547 #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4548 #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4549                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4550 #define check_pow_604E       check_pow_nocheck
4551
4552 static void init_proc_604E (CPUPPCState *env)
4553 {
4554     gen_spr_ne_601(env);
4555     gen_spr_604(env);
4556     /* XXX : not implemented */
4557     spr_register(env, SPR_MMCR1, "MMCR1",
4558                  SPR_NOACCESS, SPR_NOACCESS,
4559                  &spr_read_generic, &spr_write_generic,
4560                  0x00000000);
4561     /* XXX : not implemented */
4562     spr_register(env, SPR_PMC3, "PMC3",
4563                  SPR_NOACCESS, SPR_NOACCESS,
4564                  &spr_read_generic, &spr_write_generic,
4565                  0x00000000);
4566     /* XXX : not implemented */
4567     spr_register(env, SPR_PMC4, "PMC4",
4568                  SPR_NOACCESS, SPR_NOACCESS,
4569                  &spr_read_generic, &spr_write_generic,
4570                  0x00000000);
4571     /* Time base */
4572     gen_tbl(env);
4573     /* Hardware implementation registers */
4574     /* XXX : not implemented */
4575     spr_register(env, SPR_HID0, "HID0",
4576                  SPR_NOACCESS, SPR_NOACCESS,
4577                  &spr_read_generic, &spr_write_generic,
4578                  0x00000000);
4579     /* XXX : not implemented */
4580     spr_register(env, SPR_HID1, "HID1",
4581                  SPR_NOACCESS, SPR_NOACCESS,
4582                  &spr_read_generic, &spr_write_generic,
4583                  0x00000000);
4584     /* Memory management */
4585     gen_low_BATs(env);
4586     init_excp_604(env);
4587     env->dcache_line_size = 32;
4588     env->icache_line_size = 32;
4589     /* Allocate hardware IRQ controller */
4590     ppc6xx_irq_init(env);
4591 }
4592
4593 /* PowerPC 740                                                               */
4594 #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4595                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4596                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4597                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4598                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4599                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4600                               PPC_SEGMENT | PPC_EXTERN)
4601 #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
4602 #define POWERPC_MMU_740      (POWERPC_MMU_32B)
4603 #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
4604 #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
4605 #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
4606 #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4607                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4608 #define check_pow_740        check_pow_hid0
4609
4610 static void init_proc_740 (CPUPPCState *env)
4611 {
4612     gen_spr_ne_601(env);
4613     gen_spr_7xx(env);
4614     /* Time base */
4615     gen_tbl(env);
4616     /* Thermal management */
4617     gen_spr_thrm(env);
4618     /* Hardware implementation registers */
4619     /* XXX : not implemented */
4620     spr_register(env, SPR_HID0, "HID0",
4621                  SPR_NOACCESS, SPR_NOACCESS,
4622                  &spr_read_generic, &spr_write_generic,
4623                  0x00000000);
4624     /* XXX : not implemented */
4625     spr_register(env, SPR_HID1, "HID1",
4626                  SPR_NOACCESS, SPR_NOACCESS,
4627                  &spr_read_generic, &spr_write_generic,
4628                  0x00000000);
4629     /* Memory management */
4630     gen_low_BATs(env);
4631     init_excp_7x0(env);
4632     env->dcache_line_size = 32;
4633     env->icache_line_size = 32;
4634     /* Allocate hardware IRQ controller */
4635     ppc6xx_irq_init(env);
4636 }
4637
4638 /* PowerPC 750                                                               */
4639 #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4640                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4641                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4642                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4643                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4644                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4645                               PPC_SEGMENT | PPC_EXTERN)
4646 #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
4647 #define POWERPC_MMU_750      (POWERPC_MMU_32B)
4648 #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
4649 #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
4650 #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
4651 #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4652                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4653 #define check_pow_750        check_pow_hid0
4654
4655 static void init_proc_750 (CPUPPCState *env)
4656 {
4657     gen_spr_ne_601(env);
4658     gen_spr_7xx(env);
4659     /* XXX : not implemented */
4660     spr_register(env, SPR_L2CR, "L2CR",
4661                  SPR_NOACCESS, SPR_NOACCESS,
4662                  &spr_read_generic, &spr_write_generic,
4663                  0x00000000);
4664     /* Time base */
4665     gen_tbl(env);
4666     /* Thermal management */
4667     gen_spr_thrm(env);
4668     /* Hardware implementation registers */
4669     /* XXX : not implemented */
4670     spr_register(env, SPR_HID0, "HID0",
4671                  SPR_NOACCESS, SPR_NOACCESS,
4672                  &spr_read_generic, &spr_write_generic,
4673                  0x00000000);
4674     /* XXX : not implemented */
4675     spr_register(env, SPR_HID1, "HID1",
4676                  SPR_NOACCESS, SPR_NOACCESS,
4677                  &spr_read_generic, &spr_write_generic,
4678                  0x00000000);
4679     /* Memory management */
4680     gen_low_BATs(env);
4681     /* XXX: high BATs are also present but are known to be bugged on
4682      *      die version 1.x
4683      */
4684     init_excp_7x0(env);
4685     env->dcache_line_size = 32;
4686     env->icache_line_size = 32;
4687     /* Allocate hardware IRQ controller */
4688     ppc6xx_irq_init(env);
4689 }
4690
4691 /* PowerPC 750 CL                                                            */
4692 /* XXX: not implemented:
4693  * cache lock instructions:
4694  * dcbz_l
4695  * floating point paired instructions
4696  * psq_lux
4697  * psq_lx
4698  * psq_stux
4699  * psq_stx
4700  * ps_abs
4701  * ps_add
4702  * ps_cmpo0
4703  * ps_cmpo1
4704  * ps_cmpu0
4705  * ps_cmpu1
4706  * ps_div
4707  * ps_madd
4708  * ps_madds0
4709  * ps_madds1
4710  * ps_merge00
4711  * ps_merge01
4712  * ps_merge10
4713  * ps_merge11
4714  * ps_mr
4715  * ps_msub
4716  * ps_mul
4717  * ps_muls0
4718  * ps_muls1
4719  * ps_nabs
4720  * ps_neg
4721  * ps_nmadd
4722  * ps_nmsub
4723  * ps_res
4724  * ps_rsqrte
4725  * ps_sel
4726  * ps_sub
4727  * ps_sum0
4728  * ps_sum1
4729  */
4730 #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4731                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4732                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4733                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4734                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4735                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4736                               PPC_SEGMENT | PPC_EXTERN)
4737 #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
4738 #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
4739 #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
4740 #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
4741 #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
4742 #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4743                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4744 #define check_pow_750cl      check_pow_hid0
4745
4746 static void init_proc_750cl (CPUPPCState *env)
4747 {
4748     gen_spr_ne_601(env);
4749     gen_spr_7xx(env);
4750     /* XXX : not implemented */
4751     spr_register(env, SPR_L2CR, "L2CR",
4752                  SPR_NOACCESS, SPR_NOACCESS,
4753                  &spr_read_generic, &spr_write_generic,
4754                  0x00000000);
4755     /* Time base */
4756     gen_tbl(env);
4757     /* Thermal management */
4758     /* Those registers are fake on 750CL */
4759     spr_register(env, SPR_THRM1, "THRM1",
4760                  SPR_NOACCESS, SPR_NOACCESS,
4761                  &spr_read_generic, &spr_write_generic,
4762                  0x00000000);
4763     spr_register(env, SPR_THRM2, "THRM2",
4764                  SPR_NOACCESS, SPR_NOACCESS,
4765                  &spr_read_generic, &spr_write_generic,
4766                  0x00000000);
4767     spr_register(env, SPR_THRM3, "THRM3",
4768                  SPR_NOACCESS, SPR_NOACCESS,
4769                  &spr_read_generic, &spr_write_generic,
4770                  0x00000000);
4771     /* XXX: not implemented */
4772     spr_register(env, SPR_750_TDCL, "TDCL",
4773                  SPR_NOACCESS, SPR_NOACCESS,
4774                  &spr_read_generic, &spr_write_generic,
4775                  0x00000000);
4776     spr_register(env, SPR_750_TDCH, "TDCH",
4777                  SPR_NOACCESS, SPR_NOACCESS,
4778                  &spr_read_generic, &spr_write_generic,
4779                  0x00000000);
4780     /* DMA */
4781     /* XXX : not implemented */
4782     spr_register(env, SPR_750_WPAR, "WPAR",
4783                  SPR_NOACCESS, SPR_NOACCESS,
4784                  &spr_read_generic, &spr_write_generic,
4785                  0x00000000);
4786     spr_register(env, SPR_750_DMAL, "DMAL",
4787                  SPR_NOACCESS, SPR_NOACCESS,
4788                  &spr_read_generic, &spr_write_generic,
4789                  0x00000000);
4790     spr_register(env, SPR_750_DMAU, "DMAU",
4791                  SPR_NOACCESS, SPR_NOACCESS,
4792                  &spr_read_generic, &spr_write_generic,
4793                  0x00000000);
4794     /* Hardware implementation registers */
4795     /* XXX : not implemented */
4796     spr_register(env, SPR_HID0, "HID0",
4797                  SPR_NOACCESS, SPR_NOACCESS,
4798                  &spr_read_generic, &spr_write_generic,
4799                  0x00000000);
4800     /* XXX : not implemented */
4801     spr_register(env, SPR_HID1, "HID1",
4802                  SPR_NOACCESS, SPR_NOACCESS,
4803                  &spr_read_generic, &spr_write_generic,
4804                  0x00000000);
4805     /* XXX : not implemented */
4806     spr_register(env, SPR_750CL_HID2, "HID2",
4807                  SPR_NOACCESS, SPR_NOACCESS,
4808                  &spr_read_generic, &spr_write_generic,
4809                  0x00000000);
4810     /* XXX : not implemented */
4811     spr_register(env, SPR_750CL_HID4, "HID4",
4812                  SPR_NOACCESS, SPR_NOACCESS,
4813                  &spr_read_generic, &spr_write_generic,
4814                  0x00000000);
4815     /* Quantization registers */
4816     /* XXX : not implemented */
4817     spr_register(env, SPR_750_GQR0, "GQR0",
4818                  SPR_NOACCESS, SPR_NOACCESS,
4819                  &spr_read_generic, &spr_write_generic,
4820                  0x00000000);
4821     /* XXX : not implemented */
4822     spr_register(env, SPR_750_GQR1, "GQR1",
4823                  SPR_NOACCESS, SPR_NOACCESS,
4824                  &spr_read_generic, &spr_write_generic,
4825                  0x00000000);
4826     /* XXX : not implemented */
4827     spr_register(env, SPR_750_GQR2, "GQR2",
4828                  SPR_NOACCESS, SPR_NOACCESS,
4829                  &spr_read_generic, &spr_write_generic,
4830                  0x00000000);
4831     /* XXX : not implemented */
4832     spr_register(env, SPR_750_GQR3, "GQR3",
4833                  SPR_NOACCESS, SPR_NOACCESS,
4834                  &spr_read_generic, &spr_write_generic,
4835                  0x00000000);
4836     /* XXX : not implemented */
4837     spr_register(env, SPR_750_GQR4, "GQR4",
4838                  SPR_NOACCESS, SPR_NOACCESS,
4839                  &spr_read_generic, &spr_write_generic,
4840                  0x00000000);
4841     /* XXX : not implemented */
4842     spr_register(env, SPR_750_GQR5, "GQR5",
4843                  SPR_NOACCESS, SPR_NOACCESS,
4844                  &spr_read_generic, &spr_write_generic,
4845                  0x00000000);
4846     /* XXX : not implemented */
4847     spr_register(env, SPR_750_GQR6, "GQR6",
4848                  SPR_NOACCESS, SPR_NOACCESS,
4849                  &spr_read_generic, &spr_write_generic,
4850                  0x00000000);
4851     /* XXX : not implemented */
4852     spr_register(env, SPR_750_GQR7, "GQR7",
4853                  SPR_NOACCESS, SPR_NOACCESS,
4854                  &spr_read_generic, &spr_write_generic,
4855                  0x00000000);
4856     /* Memory management */
4857     gen_low_BATs(env);
4858     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4859     gen_high_BATs(env);
4860     init_excp_750cl(env);
4861     env->dcache_line_size = 32;
4862     env->icache_line_size = 32;
4863     /* Allocate hardware IRQ controller */
4864     ppc6xx_irq_init(env);
4865 }
4866
4867 /* PowerPC 750CX                                                             */
4868 #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4869                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4870                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4871                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4872                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4873                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4874                               PPC_SEGMENT | PPC_EXTERN)
4875 #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
4876 #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
4877 #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
4878 #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
4879 #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
4880 #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4881                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4882 #define check_pow_750cx      check_pow_hid0
4883
4884 static void init_proc_750cx (CPUPPCState *env)
4885 {
4886     gen_spr_ne_601(env);
4887     gen_spr_7xx(env);
4888     /* XXX : not implemented */
4889     spr_register(env, SPR_L2CR, "L2CR",
4890                  SPR_NOACCESS, SPR_NOACCESS,
4891                  &spr_read_generic, &spr_write_generic,
4892                  0x00000000);
4893     /* Time base */
4894     gen_tbl(env);
4895     /* Thermal management */
4896     gen_spr_thrm(env);
4897     /* This register is not implemented but is present for compatibility */
4898     spr_register(env, SPR_SDA, "SDA",
4899                  SPR_NOACCESS, SPR_NOACCESS,
4900                  &spr_read_generic, &spr_write_generic,
4901                  0x00000000);
4902     /* Hardware implementation registers */
4903     /* XXX : not implemented */
4904     spr_register(env, SPR_HID0, "HID0",
4905                  SPR_NOACCESS, SPR_NOACCESS,
4906                  &spr_read_generic, &spr_write_generic,
4907                  0x00000000);
4908     /* XXX : not implemented */
4909     spr_register(env, SPR_HID1, "HID1",
4910                  SPR_NOACCESS, SPR_NOACCESS,
4911                  &spr_read_generic, &spr_write_generic,
4912                  0x00000000);
4913     /* Memory management */
4914     gen_low_BATs(env);
4915     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4916     gen_high_BATs(env);
4917     init_excp_750cx(env);
4918     env->dcache_line_size = 32;
4919     env->icache_line_size = 32;
4920     /* Allocate hardware IRQ controller */
4921     ppc6xx_irq_init(env);
4922 }
4923
4924 /* PowerPC 750FX                                                             */
4925 #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4926                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4927                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4928                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4929                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4930                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4931                               PPC_SEGMENT  | PPC_EXTERN)
4932 #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
4933 #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
4934 #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
4935 #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
4936 #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
4937 #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4938                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4939 #define check_pow_750fx      check_pow_hid0
4940
4941 static void init_proc_750fx (CPUPPCState *env)
4942 {
4943     gen_spr_ne_601(env);
4944     gen_spr_7xx(env);
4945     /* XXX : not implemented */
4946     spr_register(env, SPR_L2CR, "L2CR",
4947                  SPR_NOACCESS, SPR_NOACCESS,
4948                  &spr_read_generic, &spr_write_generic,
4949                  0x00000000);
4950     /* Time base */
4951     gen_tbl(env);
4952     /* Thermal management */
4953     gen_spr_thrm(env);
4954     /* XXX : not implemented */
4955     spr_register(env, SPR_750_THRM4, "THRM4",
4956                  SPR_NOACCESS, SPR_NOACCESS,
4957                  &spr_read_generic, &spr_write_generic,
4958                  0x00000000);
4959     /* Hardware implementation registers */
4960     /* XXX : not implemented */
4961     spr_register(env, SPR_HID0, "HID0",
4962                  SPR_NOACCESS, SPR_NOACCESS,
4963                  &spr_read_generic, &spr_write_generic,
4964                  0x00000000);
4965     /* XXX : not implemented */
4966     spr_register(env, SPR_HID1, "HID1",
4967                  SPR_NOACCESS, SPR_NOACCESS,
4968                  &spr_read_generic, &spr_write_generic,
4969                  0x00000000);
4970     /* XXX : not implemented */
4971     spr_register(env, SPR_750FX_HID2, "HID2",
4972                  SPR_NOACCESS, SPR_NOACCESS,
4973                  &spr_read_generic, &spr_write_generic,
4974                  0x00000000);
4975     /* Memory management */
4976     gen_low_BATs(env);
4977     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4978     gen_high_BATs(env);
4979     init_excp_7x0(env);
4980     env->dcache_line_size = 32;
4981     env->icache_line_size = 32;
4982     /* Allocate hardware IRQ controller */
4983     ppc6xx_irq_init(env);
4984 }
4985
4986 /* PowerPC 750GX                                                             */
4987 #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4988                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4989                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4990                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4991                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4992                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4993                               PPC_SEGMENT  | PPC_EXTERN)
4994 #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
4995 #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
4996 #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
4997 #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
4998 #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
4999 #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5000                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5001 #define check_pow_750gx      check_pow_hid0
5002
5003 static void init_proc_750gx (CPUPPCState *env)
5004 {
5005     gen_spr_ne_601(env);
5006     gen_spr_7xx(env);
5007     /* XXX : not implemented (XXX: different from 750fx) */
5008     spr_register(env, SPR_L2CR, "L2CR",
5009                  SPR_NOACCESS, SPR_NOACCESS,
5010                  &spr_read_generic, &spr_write_generic,
5011                  0x00000000);
5012     /* Time base */
5013     gen_tbl(env);
5014     /* Thermal management */
5015     gen_spr_thrm(env);
5016     /* XXX : not implemented */
5017     spr_register(env, SPR_750_THRM4, "THRM4",
5018                  SPR_NOACCESS, SPR_NOACCESS,
5019                  &spr_read_generic, &spr_write_generic,
5020                  0x00000000);
5021     /* Hardware implementation registers */
5022     /* XXX : not implemented (XXX: different from 750fx) */
5023     spr_register(env, SPR_HID0, "HID0",
5024                  SPR_NOACCESS, SPR_NOACCESS,
5025                  &spr_read_generic, &spr_write_generic,
5026                  0x00000000);
5027     /* XXX : not implemented */
5028     spr_register(env, SPR_HID1, "HID1",
5029                  SPR_NOACCESS, SPR_NOACCESS,
5030                  &spr_read_generic, &spr_write_generic,
5031                  0x00000000);
5032     /* XXX : not implemented (XXX: different from 750fx) */
5033     spr_register(env, SPR_750FX_HID2, "HID2",
5034                  SPR_NOACCESS, SPR_NOACCESS,
5035                  &spr_read_generic, &spr_write_generic,
5036                  0x00000000);
5037     /* Memory management */
5038     gen_low_BATs(env);
5039     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5040     gen_high_BATs(env);
5041     init_excp_7x0(env);
5042     env->dcache_line_size = 32;
5043     env->icache_line_size = 32;
5044     /* Allocate hardware IRQ controller */
5045     ppc6xx_irq_init(env);
5046 }
5047
5048 /* PowerPC 745                                                               */
5049 #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5050                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5051                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5052                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5053                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5054                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5055                               PPC_SEGMENT | PPC_EXTERN)
5056 #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
5057 #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
5058 #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
5059 #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
5060 #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
5061 #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5062                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5063 #define check_pow_745        check_pow_hid0
5064
5065 static void init_proc_745 (CPUPPCState *env)
5066 {
5067     gen_spr_ne_601(env);
5068     gen_spr_7xx(env);
5069     gen_spr_G2_755(env);
5070     /* Time base */
5071     gen_tbl(env);
5072     /* Thermal management */
5073     gen_spr_thrm(env);
5074     /* Hardware implementation registers */
5075     /* XXX : not implemented */
5076     spr_register(env, SPR_HID0, "HID0",
5077                  SPR_NOACCESS, SPR_NOACCESS,
5078                  &spr_read_generic, &spr_write_generic,
5079                  0x00000000);
5080     /* XXX : not implemented */
5081     spr_register(env, SPR_HID1, "HID1",
5082                  SPR_NOACCESS, SPR_NOACCESS,
5083                  &spr_read_generic, &spr_write_generic,
5084                  0x00000000);
5085     /* XXX : not implemented */
5086     spr_register(env, SPR_HID2, "HID2",
5087                  SPR_NOACCESS, SPR_NOACCESS,
5088                  &spr_read_generic, &spr_write_generic,
5089                  0x00000000);
5090     /* Memory management */
5091     gen_low_BATs(env);
5092     gen_high_BATs(env);
5093     gen_6xx_7xx_soft_tlb(env, 64, 2);
5094     init_excp_7x5(env);
5095     env->dcache_line_size = 32;
5096     env->icache_line_size = 32;
5097     /* Allocate hardware IRQ controller */
5098     ppc6xx_irq_init(env);
5099 }
5100
5101 /* PowerPC 755                                                               */
5102 #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5103                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5104                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5105                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5106                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5107                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5108                               PPC_SEGMENT | PPC_EXTERN)
5109 #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
5110 #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
5111 #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
5112 #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
5113 #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
5114 #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5115                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5116 #define check_pow_755        check_pow_hid0
5117
5118 static void init_proc_755 (CPUPPCState *env)
5119 {
5120     gen_spr_ne_601(env);
5121     gen_spr_7xx(env);
5122     gen_spr_G2_755(env);
5123     /* Time base */
5124     gen_tbl(env);
5125     /* L2 cache control */
5126     /* XXX : not implemented */
5127     spr_register(env, SPR_L2CR, "L2CR",
5128                  SPR_NOACCESS, SPR_NOACCESS,
5129                  &spr_read_generic, &spr_write_generic,
5130                  0x00000000);
5131     /* XXX : not implemented */
5132     spr_register(env, SPR_L2PMCR, "L2PMCR",
5133                  SPR_NOACCESS, SPR_NOACCESS,
5134                  &spr_read_generic, &spr_write_generic,
5135                  0x00000000);
5136     /* Thermal management */
5137     gen_spr_thrm(env);
5138     /* Hardware implementation registers */
5139     /* XXX : not implemented */
5140     spr_register(env, SPR_HID0, "HID0",
5141                  SPR_NOACCESS, SPR_NOACCESS,
5142                  &spr_read_generic, &spr_write_generic,
5143                  0x00000000);
5144     /* XXX : not implemented */
5145     spr_register(env, SPR_HID1, "HID1",
5146                  SPR_NOACCESS, SPR_NOACCESS,
5147                  &spr_read_generic, &spr_write_generic,
5148                  0x00000000);
5149     /* XXX : not implemented */
5150     spr_register(env, SPR_HID2, "HID2",
5151                  SPR_NOACCESS, SPR_NOACCESS,
5152                  &spr_read_generic, &spr_write_generic,
5153                  0x00000000);
5154     /* Memory management */
5155     gen_low_BATs(env);
5156     gen_high_BATs(env);
5157     gen_6xx_7xx_soft_tlb(env, 64, 2);
5158     init_excp_7x5(env);
5159     env->dcache_line_size = 32;
5160     env->icache_line_size = 32;
5161     /* Allocate hardware IRQ controller */
5162     ppc6xx_irq_init(env);
5163 }
5164
5165 /* PowerPC 7400 (aka G4)                                                     */
5166 #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5167                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5168                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5169                               PPC_FLOAT_STFIWX |                              \
5170                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5171                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5172                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5173                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5174                               PPC_MEM_TLBIA |                                 \
5175                               PPC_SEGMENT | PPC_EXTERN |                      \
5176                               PPC_ALTIVEC)
5177 #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
5178 #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
5179 #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
5180 #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
5181 #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
5182 #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5183                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5184                               POWERPC_FLAG_BUS_CLK)
5185 #define check_pow_7400       check_pow_hid0_74xx
5186
5187 static void init_proc_7400 (CPUPPCState *env)
5188 {
5189     gen_spr_ne_601(env);
5190     gen_spr_7xx(env);
5191     /* Time base */
5192     gen_tbl(env);
5193     /* 74xx specific SPR */
5194     gen_spr_74xx(env);
5195     /* XXX : not implemented */
5196     spr_register(env, SPR_UBAMR, "UBAMR",
5197                  &spr_read_ureg, SPR_NOACCESS,
5198                  &spr_read_ureg, SPR_NOACCESS,
5199                  0x00000000);
5200     /* XXX: this seems not implemented on all revisions. */
5201     /* XXX : not implemented */
5202     spr_register(env, SPR_MSSCR1, "MSSCR1",
5203                  SPR_NOACCESS, SPR_NOACCESS,
5204                  &spr_read_generic, &spr_write_generic,
5205                  0x00000000);
5206     /* Thermal management */
5207     gen_spr_thrm(env);
5208     /* Memory management */
5209     gen_low_BATs(env);
5210     init_excp_7400(env);
5211     env->dcache_line_size = 32;
5212     env->icache_line_size = 32;
5213     /* Allocate hardware IRQ controller */
5214     ppc6xx_irq_init(env);
5215 }
5216
5217 /* PowerPC 7410 (aka G4)                                                     */
5218 #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5219                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5220                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5221                               PPC_FLOAT_STFIWX |                              \
5222                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5223                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5224                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5225                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5226                               PPC_MEM_TLBIA |                                 \
5227                               PPC_SEGMENT | PPC_EXTERN |                      \
5228                               PPC_ALTIVEC)
5229 #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
5230 #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
5231 #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
5232 #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
5233 #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
5234 #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5235                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5236                               POWERPC_FLAG_BUS_CLK)
5237 #define check_pow_7410       check_pow_hid0_74xx
5238
5239 static void init_proc_7410 (CPUPPCState *env)
5240 {
5241     gen_spr_ne_601(env);
5242     gen_spr_7xx(env);
5243     /* Time base */
5244     gen_tbl(env);
5245     /* 74xx specific SPR */
5246     gen_spr_74xx(env);
5247     /* XXX : not implemented */
5248     spr_register(env, SPR_UBAMR, "UBAMR",
5249                  &spr_read_ureg, SPR_NOACCESS,
5250                  &spr_read_ureg, SPR_NOACCESS,
5251                  0x00000000);
5252     /* Thermal management */
5253     gen_spr_thrm(env);
5254     /* L2PMCR */
5255     /* XXX : not implemented */
5256     spr_register(env, SPR_L2PMCR, "L2PMCR",
5257                  SPR_NOACCESS, SPR_NOACCESS,
5258                  &spr_read_generic, &spr_write_generic,
5259                  0x00000000);
5260     /* LDSTDB */
5261     /* XXX : not implemented */
5262     spr_register(env, SPR_LDSTDB, "LDSTDB",
5263                  SPR_NOACCESS, SPR_NOACCESS,
5264                  &spr_read_generic, &spr_write_generic,
5265                  0x00000000);
5266     /* Memory management */
5267     gen_low_BATs(env);
5268     init_excp_7400(env);
5269     env->dcache_line_size = 32;
5270     env->icache_line_size = 32;
5271     /* Allocate hardware IRQ controller */
5272     ppc6xx_irq_init(env);
5273 }
5274
5275 /* PowerPC 7440 (aka G4)                                                     */
5276 #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5277                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5278                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5279                               PPC_FLOAT_STFIWX |                              \
5280                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5281                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5282                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5283                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5284                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5285                               PPC_SEGMENT | PPC_EXTERN |                      \
5286                               PPC_ALTIVEC)
5287 #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
5288 #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
5289 #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
5290 #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
5291 #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
5292 #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5293                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5294                               POWERPC_FLAG_BUS_CLK)
5295 #define check_pow_7440       check_pow_hid0_74xx
5296
5297 __attribute__ (( unused ))
5298 static void init_proc_7440 (CPUPPCState *env)
5299 {
5300     gen_spr_ne_601(env);
5301     gen_spr_7xx(env);
5302     /* Time base */
5303     gen_tbl(env);
5304     /* 74xx specific SPR */
5305     gen_spr_74xx(env);
5306     /* XXX : not implemented */
5307     spr_register(env, SPR_UBAMR, "UBAMR",
5308                  &spr_read_ureg, SPR_NOACCESS,
5309                  &spr_read_ureg, SPR_NOACCESS,
5310                  0x00000000);
5311     /* LDSTCR */
5312     /* XXX : not implemented */
5313     spr_register(env, SPR_LDSTCR, "LDSTCR",
5314                  SPR_NOACCESS, SPR_NOACCESS,
5315                  &spr_read_generic, &spr_write_generic,
5316                  0x00000000);
5317     /* ICTRL */
5318     /* XXX : not implemented */
5319     spr_register(env, SPR_ICTRL, "ICTRL",
5320                  SPR_NOACCESS, SPR_NOACCESS,
5321                  &spr_read_generic, &spr_write_generic,
5322                  0x00000000);
5323     /* MSSSR0 */
5324     /* XXX : not implemented */
5325     spr_register(env, SPR_MSSSR0, "MSSSR0",
5326                  SPR_NOACCESS, SPR_NOACCESS,
5327                  &spr_read_generic, &spr_write_generic,
5328                  0x00000000);
5329     /* PMC */
5330     /* XXX : not implemented */
5331     spr_register(env, SPR_PMC5, "PMC5",
5332                  SPR_NOACCESS, SPR_NOACCESS,
5333                  &spr_read_generic, &spr_write_generic,
5334                  0x00000000);
5335     /* XXX : not implemented */
5336     spr_register(env, SPR_UPMC5, "UPMC5",
5337                  &spr_read_ureg, SPR_NOACCESS,
5338                  &spr_read_ureg, SPR_NOACCESS,
5339                  0x00000000);
5340     /* XXX : not implemented */
5341     spr_register(env, SPR_PMC6, "PMC6",
5342                  SPR_NOACCESS, SPR_NOACCESS,
5343                  &spr_read_generic, &spr_write_generic,
5344                  0x00000000);
5345     /* XXX : not implemented */
5346     spr_register(env, SPR_UPMC6, "UPMC6",
5347                  &spr_read_ureg, SPR_NOACCESS,
5348                  &spr_read_ureg, SPR_NOACCESS,
5349                  0x00000000);
5350     /* Memory management */
5351     gen_low_BATs(env);
5352     gen_74xx_soft_tlb(env, 128, 2);
5353     init_excp_7450(env);
5354     env->dcache_line_size = 32;
5355     env->icache_line_size = 32;
5356     /* Allocate hardware IRQ controller */
5357     ppc6xx_irq_init(env);
5358 }
5359
5360 /* PowerPC 7450 (aka G4)                                                     */
5361 #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5362                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5363                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5364                               PPC_FLOAT_STFIWX |                              \
5365                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5366                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5367                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5368                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5369                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5370                               PPC_SEGMENT | PPC_EXTERN |                      \
5371                               PPC_ALTIVEC)
5372 #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
5373 #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
5374 #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
5375 #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
5376 #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
5377 #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5378                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5379                               POWERPC_FLAG_BUS_CLK)
5380 #define check_pow_7450       check_pow_hid0_74xx
5381
5382 __attribute__ (( unused ))
5383 static void init_proc_7450 (CPUPPCState *env)
5384 {
5385     gen_spr_ne_601(env);
5386     gen_spr_7xx(env);
5387     /* Time base */
5388     gen_tbl(env);
5389     /* 74xx specific SPR */
5390     gen_spr_74xx(env);
5391     /* Level 3 cache control */
5392     gen_l3_ctrl(env);
5393     /* L3ITCR1 */
5394     /* XXX : not implemented */
5395     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5396                  SPR_NOACCESS, SPR_NOACCESS,
5397                  &spr_read_generic, &spr_write_generic,
5398                  0x00000000);
5399     /* L3ITCR2 */
5400     /* XXX : not implemented */
5401     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5402                  SPR_NOACCESS, SPR_NOACCESS,
5403                  &spr_read_generic, &spr_write_generic,
5404                  0x00000000);
5405     /* L3ITCR3 */
5406     /* XXX : not implemented */
5407     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5408                  SPR_NOACCESS, SPR_NOACCESS,
5409                  &spr_read_generic, &spr_write_generic,
5410                  0x00000000);
5411     /* L3OHCR */
5412     /* XXX : not implemented */
5413     spr_register(env, SPR_L3OHCR, "L3OHCR",
5414                  SPR_NOACCESS, SPR_NOACCESS,
5415                  &spr_read_generic, &spr_write_generic,
5416                  0x00000000);
5417     /* XXX : not implemented */
5418     spr_register(env, SPR_UBAMR, "UBAMR",
5419                  &spr_read_ureg, SPR_NOACCESS,
5420                  &spr_read_ureg, SPR_NOACCESS,
5421                  0x00000000);
5422     /* LDSTCR */
5423     /* XXX : not implemented */
5424     spr_register(env, SPR_LDSTCR, "LDSTCR",
5425                  SPR_NOACCESS, SPR_NOACCESS,
5426                  &spr_read_generic, &spr_write_generic,
5427                  0x00000000);
5428     /* ICTRL */
5429     /* XXX : not implemented */
5430     spr_register(env, SPR_ICTRL, "ICTRL",
5431                  SPR_NOACCESS, SPR_NOACCESS,
5432                  &spr_read_generic, &spr_write_generic,
5433                  0x00000000);
5434     /* MSSSR0 */
5435     /* XXX : not implemented */
5436     spr_register(env, SPR_MSSSR0, "MSSSR0",
5437                  SPR_NOACCESS, SPR_NOACCESS,
5438                  &spr_read_generic, &spr_write_generic,
5439                  0x00000000);
5440     /* PMC */
5441     /* XXX : not implemented */
5442     spr_register(env, SPR_PMC5, "PMC5",
5443                  SPR_NOACCESS, SPR_NOACCESS,
5444                  &spr_read_generic, &spr_write_generic,
5445                  0x00000000);
5446     /* XXX : not implemented */
5447     spr_register(env, SPR_UPMC5, "UPMC5",
5448                  &spr_read_ureg, SPR_NOACCESS,
5449                  &spr_read_ureg, SPR_NOACCESS,
5450                  0x00000000);
5451     /* XXX : not implemented */
5452     spr_register(env, SPR_PMC6, "PMC6",
5453                  SPR_NOACCESS, SPR_NOACCESS,
5454                  &spr_read_generic, &spr_write_generic,
5455                  0x00000000);
5456     /* XXX : not implemented */
5457     spr_register(env, SPR_UPMC6, "UPMC6",
5458                  &spr_read_ureg, SPR_NOACCESS,
5459                  &spr_read_ureg, SPR_NOACCESS,
5460                  0x00000000);
5461     /* Memory management */
5462     gen_low_BATs(env);
5463     gen_74xx_soft_tlb(env, 128, 2);
5464     init_excp_7450(env);
5465     env->dcache_line_size = 32;
5466     env->icache_line_size = 32;
5467     /* Allocate hardware IRQ controller */
5468     ppc6xx_irq_init(env);
5469 }
5470
5471 /* PowerPC 7445 (aka G4)                                                     */
5472 #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5473                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5474                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5475                               PPC_FLOAT_STFIWX |                              \
5476                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5477                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5478                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5479                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5480                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5481                               PPC_SEGMENT | PPC_EXTERN |                      \
5482                               PPC_ALTIVEC)
5483 #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
5484 #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
5485 #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
5486 #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
5487 #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
5488 #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5489                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5490                               POWERPC_FLAG_BUS_CLK)
5491 #define check_pow_7445       check_pow_hid0_74xx
5492
5493 __attribute__ (( unused ))
5494 static void init_proc_7445 (CPUPPCState *env)
5495 {
5496     gen_spr_ne_601(env);
5497     gen_spr_7xx(env);
5498     /* Time base */
5499     gen_tbl(env);
5500     /* 74xx specific SPR */
5501     gen_spr_74xx(env);
5502     /* LDSTCR */
5503     /* XXX : not implemented */
5504     spr_register(env, SPR_LDSTCR, "LDSTCR",
5505                  SPR_NOACCESS, SPR_NOACCESS,
5506                  &spr_read_generic, &spr_write_generic,
5507                  0x00000000);
5508     /* ICTRL */
5509     /* XXX : not implemented */
5510     spr_register(env, SPR_ICTRL, "ICTRL",
5511                  SPR_NOACCESS, SPR_NOACCESS,
5512                  &spr_read_generic, &spr_write_generic,
5513                  0x00000000);
5514     /* MSSSR0 */
5515     /* XXX : not implemented */
5516     spr_register(env, SPR_MSSSR0, "MSSSR0",
5517                  SPR_NOACCESS, SPR_NOACCESS,
5518                  &spr_read_generic, &spr_write_generic,
5519                  0x00000000);
5520     /* PMC */
5521     /* XXX : not implemented */
5522     spr_register(env, SPR_PMC5, "PMC5",
5523                  SPR_NOACCESS, SPR_NOACCESS,
5524                  &spr_read_generic, &spr_write_generic,
5525                  0x00000000);
5526     /* XXX : not implemented */
5527     spr_register(env, SPR_UPMC5, "UPMC5",
5528                  &spr_read_ureg, SPR_NOACCESS,
5529                  &spr_read_ureg, SPR_NOACCESS,
5530                  0x00000000);
5531     /* XXX : not implemented */
5532     spr_register(env, SPR_PMC6, "PMC6",
5533                  SPR_NOACCESS, SPR_NOACCESS,
5534                  &spr_read_generic, &spr_write_generic,
5535                  0x00000000);
5536     /* XXX : not implemented */
5537     spr_register(env, SPR_UPMC6, "UPMC6",
5538                  &spr_read_ureg, SPR_NOACCESS,
5539                  &spr_read_ureg, SPR_NOACCESS,
5540                  0x00000000);
5541     /* SPRGs */
5542     spr_register(env, SPR_SPRG4, "SPRG4",
5543                  SPR_NOACCESS, SPR_NOACCESS,
5544                  &spr_read_generic, &spr_write_generic,
5545                  0x00000000);
5546     spr_register(env, SPR_USPRG4, "USPRG4",
5547                  &spr_read_ureg, SPR_NOACCESS,
5548                  &spr_read_ureg, SPR_NOACCESS,
5549                  0x00000000);
5550     spr_register(env, SPR_SPRG5, "SPRG5",
5551                  SPR_NOACCESS, SPR_NOACCESS,
5552                  &spr_read_generic, &spr_write_generic,
5553                  0x00000000);
5554     spr_register(env, SPR_USPRG5, "USPRG5",
5555                  &spr_read_ureg, SPR_NOACCESS,
5556                  &spr_read_ureg, SPR_NOACCESS,
5557                  0x00000000);
5558     spr_register(env, SPR_SPRG6, "SPRG6",
5559                  SPR_NOACCESS, SPR_NOACCESS,
5560                  &spr_read_generic, &spr_write_generic,
5561                  0x00000000);
5562     spr_register(env, SPR_USPRG6, "USPRG6",
5563                  &spr_read_ureg, SPR_NOACCESS,
5564                  &spr_read_ureg, SPR_NOACCESS,
5565                  0x00000000);
5566     spr_register(env, SPR_SPRG7, "SPRG7",
5567                  SPR_NOACCESS, SPR_NOACCESS,
5568                  &spr_read_generic, &spr_write_generic,
5569                  0x00000000);
5570     spr_register(env, SPR_USPRG7, "USPRG7",
5571                  &spr_read_ureg, SPR_NOACCESS,
5572                  &spr_read_ureg, SPR_NOACCESS,
5573                  0x00000000);
5574     /* Memory management */
5575     gen_low_BATs(env);
5576     gen_high_BATs(env);
5577     gen_74xx_soft_tlb(env, 128, 2);
5578     init_excp_7450(env);
5579     env->dcache_line_size = 32;
5580     env->icache_line_size = 32;
5581     /* Allocate hardware IRQ controller */
5582     ppc6xx_irq_init(env);
5583 }
5584
5585 /* PowerPC 7455 (aka G4)                                                     */
5586 #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5587                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5588                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5589                               PPC_FLOAT_STFIWX |                              \
5590                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5591                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5592                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5593                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5594                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5595                               PPC_SEGMENT | PPC_EXTERN |                      \
5596                               PPC_ALTIVEC)
5597 #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
5598 #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
5599 #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
5600 #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
5601 #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
5602 #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5603                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5604                               POWERPC_FLAG_BUS_CLK)
5605 #define check_pow_7455       check_pow_hid0_74xx
5606
5607 __attribute__ (( unused ))
5608 static void init_proc_7455 (CPUPPCState *env)
5609 {
5610     gen_spr_ne_601(env);
5611     gen_spr_7xx(env);
5612     /* Time base */
5613     gen_tbl(env);
5614     /* 74xx specific SPR */
5615     gen_spr_74xx(env);
5616     /* Level 3 cache control */
5617     gen_l3_ctrl(env);
5618     /* LDSTCR */
5619     /* XXX : not implemented */
5620     spr_register(env, SPR_LDSTCR, "LDSTCR",
5621                  SPR_NOACCESS, SPR_NOACCESS,
5622                  &spr_read_generic, &spr_write_generic,
5623                  0x00000000);
5624     /* ICTRL */
5625     /* XXX : not implemented */
5626     spr_register(env, SPR_ICTRL, "ICTRL",
5627                  SPR_NOACCESS, SPR_NOACCESS,
5628                  &spr_read_generic, &spr_write_generic,
5629                  0x00000000);
5630     /* MSSSR0 */
5631     /* XXX : not implemented */
5632     spr_register(env, SPR_MSSSR0, "MSSSR0",
5633                  SPR_NOACCESS, SPR_NOACCESS,
5634                  &spr_read_generic, &spr_write_generic,
5635                  0x00000000);
5636     /* PMC */
5637     /* XXX : not implemented */
5638     spr_register(env, SPR_PMC5, "PMC5",
5639                  SPR_NOACCESS, SPR_NOACCESS,
5640                  &spr_read_generic, &spr_write_generic,
5641                  0x00000000);
5642     /* XXX : not implemented */
5643     spr_register(env, SPR_UPMC5, "UPMC5",
5644                  &spr_read_ureg, SPR_NOACCESS,
5645                  &spr_read_ureg, SPR_NOACCESS,
5646                  0x00000000);
5647     /* XXX : not implemented */
5648     spr_register(env, SPR_PMC6, "PMC6",
5649                  SPR_NOACCESS, SPR_NOACCESS,
5650                  &spr_read_generic, &spr_write_generic,
5651                  0x00000000);
5652     /* XXX : not implemented */
5653     spr_register(env, SPR_UPMC6, "UPMC6",
5654                  &spr_read_ureg, SPR_NOACCESS,
5655                  &spr_read_ureg, SPR_NOACCESS,
5656                  0x00000000);
5657     /* SPRGs */
5658     spr_register(env, SPR_SPRG4, "SPRG4",
5659                  SPR_NOACCESS, SPR_NOACCESS,
5660                  &spr_read_generic, &spr_write_generic,
5661                  0x00000000);
5662     spr_register(env, SPR_USPRG4, "USPRG4",
5663                  &spr_read_ureg, SPR_NOACCESS,
5664                  &spr_read_ureg, SPR_NOACCESS,
5665                  0x00000000);
5666     spr_register(env, SPR_SPRG5, "SPRG5",
5667                  SPR_NOACCESS, SPR_NOACCESS,
5668                  &spr_read_generic, &spr_write_generic,
5669                  0x00000000);
5670     spr_register(env, SPR_USPRG5, "USPRG5",
5671                  &spr_read_ureg, SPR_NOACCESS,
5672                  &spr_read_ureg, SPR_NOACCESS,
5673                  0x00000000);
5674     spr_register(env, SPR_SPRG6, "SPRG6",
5675                  SPR_NOACCESS, SPR_NOACCESS,
5676                  &spr_read_generic, &spr_write_generic,
5677                  0x00000000);
5678     spr_register(env, SPR_USPRG6, "USPRG6",
5679                  &spr_read_ureg, SPR_NOACCESS,
5680                  &spr_read_ureg, SPR_NOACCESS,
5681                  0x00000000);
5682     spr_register(env, SPR_SPRG7, "SPRG7",
5683                  SPR_NOACCESS, SPR_NOACCESS,
5684                  &spr_read_generic, &spr_write_generic,
5685                  0x00000000);
5686     spr_register(env, SPR_USPRG7, "USPRG7",
5687                  &spr_read_ureg, SPR_NOACCESS,
5688                  &spr_read_ureg, SPR_NOACCESS,
5689                  0x00000000);
5690     /* Memory management */
5691     gen_low_BATs(env);
5692     gen_high_BATs(env);
5693     gen_74xx_soft_tlb(env, 128, 2);
5694     init_excp_7450(env);
5695     env->dcache_line_size = 32;
5696     env->icache_line_size = 32;
5697     /* Allocate hardware IRQ controller */
5698     ppc6xx_irq_init(env);
5699 }
5700
5701 /* PowerPC 7457 (aka G4)                                                     */
5702 #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5703                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5704                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5705                               PPC_FLOAT_STFIWX |                              \
5706                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5707                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5708                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5709                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5710                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5711                               PPC_SEGMENT | PPC_EXTERN |                      \
5712                               PPC_ALTIVEC)
5713 #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
5714 #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
5715 #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
5716 #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
5717 #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
5718 #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5719                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5720                               POWERPC_FLAG_BUS_CLK)
5721 #define check_pow_7457       check_pow_hid0_74xx
5722
5723 __attribute__ (( unused ))
5724 static void init_proc_7457 (CPUPPCState *env)
5725 {
5726     gen_spr_ne_601(env);
5727     gen_spr_7xx(env);
5728     /* Time base */
5729     gen_tbl(env);
5730     /* 74xx specific SPR */
5731     gen_spr_74xx(env);
5732     /* Level 3 cache control */
5733     gen_l3_ctrl(env);
5734     /* L3ITCR1 */
5735     /* XXX : not implemented */
5736     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5737                  SPR_NOACCESS, SPR_NOACCESS,
5738                  &spr_read_generic, &spr_write_generic,
5739                  0x00000000);
5740     /* L3ITCR2 */
5741     /* XXX : not implemented */
5742     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5743                  SPR_NOACCESS, SPR_NOACCESS,
5744                  &spr_read_generic, &spr_write_generic,
5745                  0x00000000);
5746     /* L3ITCR3 */
5747     /* XXX : not implemented */
5748     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5749                  SPR_NOACCESS, SPR_NOACCESS,
5750                  &spr_read_generic, &spr_write_generic,
5751                  0x00000000);
5752     /* L3OHCR */
5753     /* XXX : not implemented */
5754     spr_register(env, SPR_L3OHCR, "L3OHCR",
5755                  SPR_NOACCESS, SPR_NOACCESS,
5756                  &spr_read_generic, &spr_write_generic,
5757                  0x00000000);
5758     /* LDSTCR */
5759     /* XXX : not implemented */
5760     spr_register(env, SPR_LDSTCR, "LDSTCR",
5761                  SPR_NOACCESS, SPR_NOACCESS,
5762                  &spr_read_generic, &spr_write_generic,
5763                  0x00000000);
5764     /* ICTRL */
5765     /* XXX : not implemented */
5766     spr_register(env, SPR_ICTRL, "ICTRL",
5767                  SPR_NOACCESS, SPR_NOACCESS,
5768                  &spr_read_generic, &spr_write_generic,
5769                  0x00000000);
5770     /* MSSSR0 */
5771     /* XXX : not implemented */
5772     spr_register(env, SPR_MSSSR0, "MSSSR0",
5773                  SPR_NOACCESS, SPR_NOACCESS,
5774                  &spr_read_generic, &spr_write_generic,
5775                  0x00000000);
5776     /* PMC */
5777     /* XXX : not implemented */
5778     spr_register(env, SPR_PMC5, "PMC5",
5779                  SPR_NOACCESS, SPR_NOACCESS,
5780                  &spr_read_generic, &spr_write_generic,
5781                  0x00000000);
5782     /* XXX : not implemented */
5783     spr_register(env, SPR_UPMC5, "UPMC5",
5784                  &spr_read_ureg, SPR_NOACCESS,
5785                  &spr_read_ureg, SPR_NOACCESS,
5786                  0x00000000);
5787     /* XXX : not implemented */
5788     spr_register(env, SPR_PMC6, "PMC6",
5789                  SPR_NOACCESS, SPR_NOACCESS,
5790                  &spr_read_generic, &spr_write_generic,
5791                  0x00000000);
5792     /* XXX : not implemented */
5793     spr_register(env, SPR_UPMC6, "UPMC6",
5794                  &spr_read_ureg, SPR_NOACCESS,
5795                  &spr_read_ureg, SPR_NOACCESS,
5796                  0x00000000);
5797     /* SPRGs */
5798     spr_register(env, SPR_SPRG4, "SPRG4",
5799                  SPR_NOACCESS, SPR_NOACCESS,
5800                  &spr_read_generic, &spr_write_generic,
5801                  0x00000000);
5802     spr_register(env, SPR_USPRG4, "USPRG4",
5803                  &spr_read_ureg, SPR_NOACCESS,
5804                  &spr_read_ureg, SPR_NOACCESS,
5805                  0x00000000);
5806     spr_register(env, SPR_SPRG5, "SPRG5",
5807                  SPR_NOACCESS, SPR_NOACCESS,
5808                  &spr_read_generic, &spr_write_generic,
5809                  0x00000000);
5810     spr_register(env, SPR_USPRG5, "USPRG5",
5811                  &spr_read_ureg, SPR_NOACCESS,
5812                  &spr_read_ureg, SPR_NOACCESS,
5813                  0x00000000);
5814     spr_register(env, SPR_SPRG6, "SPRG6",
5815                  SPR_NOACCESS, SPR_NOACCESS,
5816                  &spr_read_generic, &spr_write_generic,
5817                  0x00000000);
5818     spr_register(env, SPR_USPRG6, "USPRG6",
5819                  &spr_read_ureg, SPR_NOACCESS,
5820                  &spr_read_ureg, SPR_NOACCESS,
5821                  0x00000000);
5822     spr_register(env, SPR_SPRG7, "SPRG7",
5823                  SPR_NOACCESS, SPR_NOACCESS,
5824                  &spr_read_generic, &spr_write_generic,
5825                  0x00000000);
5826     spr_register(env, SPR_USPRG7, "USPRG7",
5827                  &spr_read_ureg, SPR_NOACCESS,
5828                  &spr_read_ureg, SPR_NOACCESS,
5829                  0x00000000);
5830     /* Memory management */
5831     gen_low_BATs(env);
5832     gen_high_BATs(env);
5833     gen_74xx_soft_tlb(env, 128, 2);
5834     init_excp_7450(env);
5835     env->dcache_line_size = 32;
5836     env->icache_line_size = 32;
5837     /* Allocate hardware IRQ controller */
5838     ppc6xx_irq_init(env);
5839 }
5840
5841 #if defined (TARGET_PPC64)
5842 /* PowerPC 970                                                               */
5843 #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5844                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5845                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5846                               PPC_FLOAT_STFIWX |                              \
5847                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5848                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5849                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5850                               PPC_64B | PPC_ALTIVEC |                         \
5851                               PPC_SEGMENT_64B | PPC_SLBI)
5852 #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
5853 #define POWERPC_MMU_970      (POWERPC_MMU_64B)
5854 //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
5855 #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
5856 #define POWERPC_BFDM_970     (bfd_mach_ppc64)
5857 #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5858                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5859                               POWERPC_FLAG_BUS_CLK)
5860
5861 #if defined(CONFIG_USER_ONLY)
5862 #define POWERPC970_HID5_INIT 0x00000080
5863 #else
5864 #define POWERPC970_HID5_INIT 0x00000000
5865 #endif
5866
5867 static int check_pow_970 (CPUPPCState *env)
5868 {
5869     if (env->spr[SPR_HID0] & 0x00600000)
5870         return 1;
5871
5872     return 0;
5873 }
5874
5875 static void init_proc_970 (CPUPPCState *env)
5876 {
5877     gen_spr_ne_601(env);
5878     gen_spr_7xx(env);
5879     /* Time base */
5880     gen_tbl(env);
5881     /* Hardware implementation registers */
5882     /* XXX : not implemented */
5883     spr_register(env, SPR_HID0, "HID0",
5884                  SPR_NOACCESS, SPR_NOACCESS,
5885                  &spr_read_generic, &spr_write_clear,
5886                  0x60000000);
5887     /* XXX : not implemented */
5888     spr_register(env, SPR_HID1, "HID1",
5889                  SPR_NOACCESS, SPR_NOACCESS,
5890                  &spr_read_generic, &spr_write_generic,
5891                  0x00000000);
5892     /* XXX : not implemented */
5893     spr_register(env, SPR_750FX_HID2, "HID2",
5894                  SPR_NOACCESS, SPR_NOACCESS,
5895                  &spr_read_generic, &spr_write_generic,
5896                  0x00000000);
5897     /* XXX : not implemented */
5898     spr_register(env, SPR_970_HID5, "HID5",
5899                  SPR_NOACCESS, SPR_NOACCESS,
5900                  &spr_read_generic, &spr_write_generic,
5901                  POWERPC970_HID5_INIT);
5902     /* XXX : not implemented */
5903     spr_register(env, SPR_L2CR, "L2CR",
5904                  SPR_NOACCESS, SPR_NOACCESS,
5905                  &spr_read_generic, &spr_write_generic,
5906                  0x00000000);
5907     /* Memory management */
5908     /* XXX: not correct */
5909     gen_low_BATs(env);
5910     /* XXX : not implemented */
5911     spr_register(env, SPR_MMUCFG, "MMUCFG",
5912                  SPR_NOACCESS, SPR_NOACCESS,
5913                  &spr_read_generic, SPR_NOACCESS,
5914                  0x00000000); /* TOFIX */
5915     /* XXX : not implemented */
5916     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5917                  SPR_NOACCESS, SPR_NOACCESS,
5918                  &spr_read_generic, &spr_write_generic,
5919                  0x00000000); /* TOFIX */
5920     spr_register(env, SPR_HIOR, "SPR_HIOR",
5921                  SPR_NOACCESS, SPR_NOACCESS,
5922                  &spr_read_generic, &spr_write_generic,
5923                  0xFFF00000); /* XXX: This is a hack */
5924 #if !defined(CONFIG_USER_ONLY)
5925     env->slb_nr = 32;
5926 #endif
5927     init_excp_970(env);
5928     env->dcache_line_size = 128;
5929     env->icache_line_size = 128;
5930     /* Allocate hardware IRQ controller */
5931     ppc970_irq_init(env);
5932     /* Can't find information on what this should be on reset.  This
5933      * value is the one used by 74xx processors. */
5934     vscr_init(env, 0x00010000);
5935 }
5936
5937 /* PowerPC 970FX (aka G5)                                                    */
5938 #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5939                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5940                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5941                               PPC_FLOAT_STFIWX |                              \
5942                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5943                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5944                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5945                               PPC_64B | PPC_ALTIVEC |                         \
5946                               PPC_SEGMENT_64B | PPC_SLBI)
5947 #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
5948 #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
5949 #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
5950 #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
5951 #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
5952 #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5953                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5954                               POWERPC_FLAG_BUS_CLK)
5955
5956 static int check_pow_970FX (CPUPPCState *env)
5957 {
5958     if (env->spr[SPR_HID0] & 0x00600000)
5959         return 1;
5960
5961     return 0;
5962 }
5963
5964 static void init_proc_970FX (CPUPPCState *env)
5965 {
5966     gen_spr_ne_601(env);
5967     gen_spr_7xx(env);
5968     /* Time base */
5969     gen_tbl(env);
5970     /* Hardware implementation registers */
5971     /* XXX : not implemented */
5972     spr_register(env, SPR_HID0, "HID0",
5973                  SPR_NOACCESS, SPR_NOACCESS,
5974                  &spr_read_generic, &spr_write_clear,
5975                  0x60000000);
5976     /* XXX : not implemented */
5977     spr_register(env, SPR_HID1, "HID1",
5978                  SPR_NOACCESS, SPR_NOACCESS,
5979                  &spr_read_generic, &spr_write_generic,
5980                  0x00000000);
5981     /* XXX : not implemented */
5982     spr_register(env, SPR_750FX_HID2, "HID2",
5983                  SPR_NOACCESS, SPR_NOACCESS,
5984                  &spr_read_generic, &spr_write_generic,
5985                  0x00000000);
5986     /* XXX : not implemented */
5987     spr_register(env, SPR_970_HID5, "HID5",
5988                  SPR_NOACCESS, SPR_NOACCESS,
5989                  &spr_read_generic, &spr_write_generic,
5990                  POWERPC970_HID5_INIT);
5991     /* XXX : not implemented */
5992     spr_register(env, SPR_L2CR, "L2CR",
5993                  SPR_NOACCESS, SPR_NOACCESS,
5994                  &spr_read_generic, &spr_write_generic,
5995                  0x00000000);
5996     /* Memory management */
5997     /* XXX: not correct */
5998     gen_low_BATs(env);
5999     /* XXX : not implemented */
6000     spr_register(env, SPR_MMUCFG, "MMUCFG",
6001                  SPR_NOACCESS, SPR_NOACCESS,
6002                  &spr_read_generic, SPR_NOACCESS,
6003                  0x00000000); /* TOFIX */
6004     /* XXX : not implemented */
6005     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6006                  SPR_NOACCESS, SPR_NOACCESS,
6007                  &spr_read_generic, &spr_write_generic,
6008                  0x00000000); /* TOFIX */
6009     spr_register(env, SPR_HIOR, "SPR_HIOR",
6010                  SPR_NOACCESS, SPR_NOACCESS,
6011                  &spr_read_generic, &spr_write_generic,
6012                  0xFFF00000); /* XXX: This is a hack */
6013 #if !defined(CONFIG_USER_ONLY)
6014     env->slb_nr = 32;
6015 #endif
6016     init_excp_970(env);
6017     env->dcache_line_size = 128;
6018     env->icache_line_size = 128;
6019     /* Allocate hardware IRQ controller */
6020     ppc970_irq_init(env);
6021     /* Can't find information on what this should be on reset.  This
6022      * value is the one used by 74xx processors. */
6023     vscr_init(env, 0x00010000);
6024 }
6025
6026 /* PowerPC 970 GX                                                            */
6027 #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6028                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6029                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6030                               PPC_FLOAT_STFIWX |                              \
6031                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6032                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6033                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6034                               PPC_64B | PPC_ALTIVEC |                         \
6035                               PPC_SEGMENT_64B | PPC_SLBI)
6036 #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
6037 #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
6038 #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
6039 #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
6040 #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
6041 #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6042                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6043                               POWERPC_FLAG_BUS_CLK)
6044
6045 static int check_pow_970GX (CPUPPCState *env)
6046 {
6047     if (env->spr[SPR_HID0] & 0x00600000)
6048         return 1;
6049
6050     return 0;
6051 }
6052
6053 static void init_proc_970GX (CPUPPCState *env)
6054 {
6055     gen_spr_ne_601(env);
6056     gen_spr_7xx(env);
6057     /* Time base */
6058     gen_tbl(env);
6059     /* Hardware implementation registers */
6060     /* XXX : not implemented */
6061     spr_register(env, SPR_HID0, "HID0",
6062                  SPR_NOACCESS, SPR_NOACCESS,
6063                  &spr_read_generic, &spr_write_clear,
6064                  0x60000000);
6065     /* XXX : not implemented */
6066     spr_register(env, SPR_HID1, "HID1",
6067                  SPR_NOACCESS, SPR_NOACCESS,
6068                  &spr_read_generic, &spr_write_generic,
6069                  0x00000000);
6070     /* XXX : not implemented */
6071     spr_register(env, SPR_750FX_HID2, "HID2",
6072                  SPR_NOACCESS, SPR_NOACCESS,
6073                  &spr_read_generic, &spr_write_generic,
6074                  0x00000000);
6075     /* XXX : not implemented */
6076     spr_register(env, SPR_970_HID5, "HID5",
6077                  SPR_NOACCESS, SPR_NOACCESS,
6078                  &spr_read_generic, &spr_write_generic,
6079                  POWERPC970_HID5_INIT);
6080     /* XXX : not implemented */
6081     spr_register(env, SPR_L2CR, "L2CR",
6082                  SPR_NOACCESS, SPR_NOACCESS,
6083                  &spr_read_generic, &spr_write_generic,
6084                  0x00000000);
6085     /* Memory management */
6086     /* XXX: not correct */
6087     gen_low_BATs(env);
6088     /* XXX : not implemented */
6089     spr_register(env, SPR_MMUCFG, "MMUCFG",
6090                  SPR_NOACCESS, SPR_NOACCESS,
6091                  &spr_read_generic, SPR_NOACCESS,
6092                  0x00000000); /* TOFIX */
6093     /* XXX : not implemented */
6094     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6095                  SPR_NOACCESS, SPR_NOACCESS,
6096                  &spr_read_generic, &spr_write_generic,
6097                  0x00000000); /* TOFIX */
6098     spr_register(env, SPR_HIOR, "SPR_HIOR",
6099                  SPR_NOACCESS, SPR_NOACCESS,
6100                  &spr_read_generic, &spr_write_generic,
6101                  0xFFF00000); /* XXX: This is a hack */
6102 #if !defined(CONFIG_USER_ONLY)
6103     env->slb_nr = 32;
6104 #endif
6105     init_excp_970(env);
6106     env->dcache_line_size = 128;
6107     env->icache_line_size = 128;
6108     /* Allocate hardware IRQ controller */
6109     ppc970_irq_init(env);
6110     /* Can't find information on what this should be on reset.  This
6111      * value is the one used by 74xx processors. */
6112     vscr_init(env, 0x00010000);
6113 }
6114
6115 /* PowerPC 970 MP                                                            */
6116 #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6117                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6118                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6119                               PPC_FLOAT_STFIWX |                              \
6120                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6121                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6122                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6123                               PPC_64B | PPC_ALTIVEC |                         \
6124                               PPC_SEGMENT_64B | PPC_SLBI)
6125 #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
6126 #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
6127 #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
6128 #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
6129 #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
6130 #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6131                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6132                               POWERPC_FLAG_BUS_CLK)
6133
6134 static int check_pow_970MP (CPUPPCState *env)
6135 {
6136     if (env->spr[SPR_HID0] & 0x01C00000)
6137         return 1;
6138
6139     return 0;
6140 }
6141
6142 static void init_proc_970MP (CPUPPCState *env)
6143 {
6144     gen_spr_ne_601(env);
6145     gen_spr_7xx(env);
6146     /* Time base */
6147     gen_tbl(env);
6148     /* Hardware implementation registers */
6149     /* XXX : not implemented */
6150     spr_register(env, SPR_HID0, "HID0",
6151                  SPR_NOACCESS, SPR_NOACCESS,
6152                  &spr_read_generic, &spr_write_clear,
6153                  0x60000000);
6154     /* XXX : not implemented */
6155     spr_register(env, SPR_HID1, "HID1",
6156                  SPR_NOACCESS, SPR_NOACCESS,
6157                  &spr_read_generic, &spr_write_generic,
6158                  0x00000000);
6159     /* XXX : not implemented */
6160     spr_register(env, SPR_750FX_HID2, "HID2",
6161                  SPR_NOACCESS, SPR_NOACCESS,
6162                  &spr_read_generic, &spr_write_generic,
6163                  0x00000000);
6164     /* XXX : not implemented */
6165     spr_register(env, SPR_970_HID5, "HID5",
6166                  SPR_NOACCESS, SPR_NOACCESS,
6167                  &spr_read_generic, &spr_write_generic,
6168                  POWERPC970_HID5_INIT);
6169     /* XXX : not implemented */
6170     spr_register(env, SPR_L2CR, "L2CR",
6171                  SPR_NOACCESS, SPR_NOACCESS,
6172                  &spr_read_generic, &spr_write_generic,
6173                  0x00000000);
6174     /* Memory management */
6175     /* XXX: not correct */
6176     gen_low_BATs(env);
6177     /* XXX : not implemented */
6178     spr_register(env, SPR_MMUCFG, "MMUCFG",
6179                  SPR_NOACCESS, SPR_NOACCESS,
6180                  &spr_read_generic, SPR_NOACCESS,
6181                  0x00000000); /* TOFIX */
6182     /* XXX : not implemented */
6183     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6184                  SPR_NOACCESS, SPR_NOACCESS,
6185                  &spr_read_generic, &spr_write_generic,
6186                  0x00000000); /* TOFIX */
6187     spr_register(env, SPR_HIOR, "SPR_HIOR",
6188                  SPR_NOACCESS, SPR_NOACCESS,
6189                  &spr_read_generic, &spr_write_generic,
6190                  0xFFF00000); /* XXX: This is a hack */
6191 #if !defined(CONFIG_USER_ONLY)
6192     env->slb_nr = 32;
6193 #endif
6194     init_excp_970(env);
6195     env->dcache_line_size = 128;
6196     env->icache_line_size = 128;
6197     /* Allocate hardware IRQ controller */
6198     ppc970_irq_init(env);
6199     /* Can't find information on what this should be on reset.  This
6200      * value is the one used by 74xx processors. */
6201     vscr_init(env, 0x00010000);
6202 }
6203
6204 /* PowerPC 620                                                               */
6205 #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6206                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6207                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6208                               PPC_FLOAT_STFIWX |                              \
6209                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
6210                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6211                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6212                               PPC_SEGMENT | PPC_EXTERN |                      \
6213                               PPC_64B | PPC_SLBI)
6214 #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
6215 //#define POWERPC_MMU_620      (POWERPC_MMU_620)
6216 #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
6217 #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
6218 #define POWERPC_BFDM_620     (bfd_mach_ppc64)
6219 #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
6220                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6221 #define check_pow_620        check_pow_nocheck /* Check this */
6222
6223 __attribute__ (( unused ))
6224 static void init_proc_620 (CPUPPCState *env)
6225 {
6226     gen_spr_ne_601(env);
6227     gen_spr_620(env);
6228     /* Time base */
6229     gen_tbl(env);
6230     /* Hardware implementation registers */
6231     /* XXX : not implemented */
6232     spr_register(env, SPR_HID0, "HID0",
6233                  SPR_NOACCESS, SPR_NOACCESS,
6234                  &spr_read_generic, &spr_write_generic,
6235                  0x00000000);
6236     /* Memory management */
6237     gen_low_BATs(env);
6238     init_excp_620(env);
6239     env->dcache_line_size = 64;
6240     env->icache_line_size = 64;
6241     /* Allocate hardware IRQ controller */
6242     ppc6xx_irq_init(env);
6243 }
6244 #endif /* defined (TARGET_PPC64) */
6245
6246 /* Default 32 bits PowerPC target will be 604 */
6247 #define CPU_POWERPC_PPC32     CPU_POWERPC_604
6248 #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
6249 #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
6250 #define POWERPC_MMU_PPC32     POWERPC_MMU_604
6251 #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
6252 #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
6253 #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
6254 #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
6255 #define check_pow_PPC32       check_pow_604
6256 #define init_proc_PPC32       init_proc_604
6257
6258 /* Default 64 bits PowerPC target will be 970 FX */
6259 #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
6260 #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
6261 #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
6262 #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
6263 #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
6264 #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
6265 #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
6266 #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
6267 #define check_pow_PPC64       check_pow_970FX
6268 #define init_proc_PPC64       init_proc_970FX
6269
6270 /* Default PowerPC target will be PowerPC 32 */
6271 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6272 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
6273 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6274 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
6275 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
6276 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
6277 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6278 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
6279 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
6280 #define check_pow_DEFAULT     check_pow_PPC64
6281 #define init_proc_DEFAULT     init_proc_PPC64
6282 #else
6283 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
6284 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6285 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
6286 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
6287 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
6288 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6289 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
6290 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
6291 #define check_pow_DEFAULT     check_pow_PPC32
6292 #define init_proc_DEFAULT     init_proc_PPC32
6293 #endif
6294
6295 /*****************************************************************************/
6296 /* PVR definitions for most known PowerPC                                    */
6297 enum {
6298     /* PowerPC 401 family */
6299     /* Generic PowerPC 401 */
6300 #define CPU_POWERPC_401              CPU_POWERPC_401G2
6301     /* PowerPC 401 cores */
6302     CPU_POWERPC_401A1              = 0x00210000,
6303     CPU_POWERPC_401B2              = 0x00220000,
6304 #if 0
6305     CPU_POWERPC_401B3              = xxx,
6306 #endif
6307     CPU_POWERPC_401C2              = 0x00230000,
6308     CPU_POWERPC_401D2              = 0x00240000,
6309     CPU_POWERPC_401E2              = 0x00250000,
6310     CPU_POWERPC_401F2              = 0x00260000,
6311     CPU_POWERPC_401G2              = 0x00270000,
6312     /* PowerPC 401 microcontrolers */
6313 #if 0
6314     CPU_POWERPC_401GF              = xxx,
6315 #endif
6316 #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
6317     /* IBM Processor for Network Resources */
6318     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
6319 #if 0
6320     CPU_POWERPC_XIPCHIP            = xxx,
6321 #endif
6322     /* PowerPC 403 family */
6323     /* Generic PowerPC 403 */
6324 #define CPU_POWERPC_403              CPU_POWERPC_403GC
6325     /* PowerPC 403 microcontrollers */
6326     CPU_POWERPC_403GA              = 0x00200011,
6327     CPU_POWERPC_403GB              = 0x00200100,
6328     CPU_POWERPC_403GC              = 0x00200200,
6329     CPU_POWERPC_403GCX             = 0x00201400,
6330 #if 0
6331     CPU_POWERPC_403GP              = xxx,
6332 #endif
6333     /* PowerPC 405 family */
6334     /* Generic PowerPC 405 */
6335 #define CPU_POWERPC_405              CPU_POWERPC_405D4
6336     /* PowerPC 405 cores */
6337 #if 0
6338     CPU_POWERPC_405A3              = xxx,
6339 #endif
6340 #if 0
6341     CPU_POWERPC_405A4              = xxx,
6342 #endif
6343 #if 0
6344     CPU_POWERPC_405B3              = xxx,
6345 #endif
6346 #if 0
6347     CPU_POWERPC_405B4              = xxx,
6348 #endif
6349 #if 0
6350     CPU_POWERPC_405C3              = xxx,
6351 #endif
6352 #if 0
6353     CPU_POWERPC_405C4              = xxx,
6354 #endif
6355     CPU_POWERPC_405D2              = 0x20010000,
6356 #if 0
6357     CPU_POWERPC_405D3              = xxx,
6358 #endif
6359     CPU_POWERPC_405D4              = 0x41810000,
6360 #if 0
6361     CPU_POWERPC_405D5              = xxx,
6362 #endif
6363 #if 0
6364     CPU_POWERPC_405E4              = xxx,
6365 #endif
6366 #if 0
6367     CPU_POWERPC_405F4              = xxx,
6368 #endif
6369 #if 0
6370     CPU_POWERPC_405F5              = xxx,
6371 #endif
6372 #if 0
6373     CPU_POWERPC_405F6              = xxx,
6374 #endif
6375     /* PowerPC 405 microcontrolers */
6376     /* XXX: missing 0x200108a0 */
6377 #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
6378     CPU_POWERPC_405CRa             = 0x40110041,
6379     CPU_POWERPC_405CRb             = 0x401100C5,
6380     CPU_POWERPC_405CRc             = 0x40110145,
6381     CPU_POWERPC_405EP              = 0x51210950,
6382 #if 0
6383     CPU_POWERPC_405EXr             = xxx,
6384 #endif
6385     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
6386 #if 0
6387     CPU_POWERPC_405FX              = xxx,
6388 #endif
6389 #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
6390     CPU_POWERPC_405GPa             = 0x40110000,
6391     CPU_POWERPC_405GPb             = 0x40110040,
6392     CPU_POWERPC_405GPc             = 0x40110082,
6393     CPU_POWERPC_405GPd             = 0x401100C4,
6394 #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
6395     CPU_POWERPC_405GPR             = 0x50910951,
6396 #if 0
6397     CPU_POWERPC_405H               = xxx,
6398 #endif
6399 #if 0
6400     CPU_POWERPC_405L               = xxx,
6401 #endif
6402     CPU_POWERPC_405LP              = 0x41F10000,
6403 #if 0
6404     CPU_POWERPC_405PM              = xxx,
6405 #endif
6406 #if 0
6407     CPU_POWERPC_405PS              = xxx,
6408 #endif
6409 #if 0
6410     CPU_POWERPC_405S               = xxx,
6411 #endif
6412     /* IBM network processors */
6413     CPU_POWERPC_NPE405H            = 0x414100C0,
6414     CPU_POWERPC_NPE405H2           = 0x41410140,
6415     CPU_POWERPC_NPE405L            = 0x416100C0,
6416     CPU_POWERPC_NPE4GS3            = 0x40B10000,
6417 #if 0
6418     CPU_POWERPC_NPCxx1             = xxx,
6419 #endif
6420 #if 0
6421     CPU_POWERPC_NPR161             = xxx,
6422 #endif
6423 #if 0
6424     CPU_POWERPC_LC77700            = xxx,
6425 #endif
6426     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6427 #if 0
6428     CPU_POWERPC_STB01000           = xxx,
6429 #endif
6430 #if 0
6431     CPU_POWERPC_STB01010           = xxx,
6432 #endif
6433 #if 0
6434     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
6435 #endif
6436     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
6437 #if 0
6438     CPU_POWERPC_STB043             = xxx,
6439 #endif
6440 #if 0
6441     CPU_POWERPC_STB045             = xxx,
6442 #endif
6443     CPU_POWERPC_STB04              = 0x41810000,
6444     CPU_POWERPC_STB25              = 0x51510950,
6445 #if 0
6446     CPU_POWERPC_STB130             = xxx,
6447 #endif
6448     /* Xilinx cores */
6449     CPU_POWERPC_X2VP4              = 0x20010820,
6450 #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
6451     CPU_POWERPC_X2VP20             = 0x20010860,
6452 #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
6453 #if 0
6454     CPU_POWERPC_ZL10310            = xxx,
6455 #endif
6456 #if 0
6457     CPU_POWERPC_ZL10311            = xxx,
6458 #endif
6459 #if 0
6460     CPU_POWERPC_ZL10320            = xxx,
6461 #endif
6462 #if 0
6463     CPU_POWERPC_ZL10321            = xxx,
6464 #endif
6465     /* PowerPC 440 family */
6466     /* Generic PowerPC 440 */
6467 #define CPU_POWERPC_440              CPU_POWERPC_440GXf
6468     /* PowerPC 440 cores */
6469 #if 0
6470     CPU_POWERPC_440A4              = xxx,
6471 #endif
6472 #if 0
6473     CPU_POWERPC_440A5              = xxx,
6474 #endif
6475 #if 0
6476     CPU_POWERPC_440B4              = xxx,
6477 #endif
6478 #if 0
6479     CPU_POWERPC_440F5              = xxx,
6480 #endif
6481 #if 0
6482     CPU_POWERPC_440G5              = xxx,
6483 #endif
6484 #if 0
6485     CPU_POWERPC_440H4              = xxx,
6486 #endif
6487 #if 0
6488     CPU_POWERPC_440H6              = xxx,
6489 #endif
6490     /* PowerPC 440 microcontrolers */
6491 #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
6492     CPU_POWERPC_440EPa             = 0x42221850,
6493     CPU_POWERPC_440EPb             = 0x422218D3,
6494 #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
6495     CPU_POWERPC_440GPb             = 0x40120440,
6496     CPU_POWERPC_440GPc             = 0x40120481,
6497 #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
6498 #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
6499     CPU_POWERPC_440GRX             = 0x200008D0,
6500 #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
6501 #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
6502     CPU_POWERPC_440GXa             = 0x51B21850,
6503     CPU_POWERPC_440GXb             = 0x51B21851,
6504     CPU_POWERPC_440GXc             = 0x51B21892,
6505     CPU_POWERPC_440GXf             = 0x51B21894,
6506 #if 0
6507     CPU_POWERPC_440S               = xxx,
6508 #endif
6509     CPU_POWERPC_440SP              = 0x53221850,
6510     CPU_POWERPC_440SP2             = 0x53221891,
6511     CPU_POWERPC_440SPE             = 0x53421890,
6512     /* PowerPC 460 family */
6513 #if 0
6514     /* Generic PowerPC 464 */
6515 #define CPU_POWERPC_464              CPU_POWERPC_464H90
6516 #endif
6517     /* PowerPC 464 microcontrolers */
6518 #if 0
6519     CPU_POWERPC_464H90             = xxx,
6520 #endif
6521 #if 0
6522     CPU_POWERPC_464H90FP           = xxx,
6523 #endif
6524     /* Freescale embedded PowerPC cores */
6525     /* PowerPC MPC 5xx cores (aka RCPU) */
6526     CPU_POWERPC_MPC5xx             = 0x00020020,
6527 #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
6528 #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
6529 #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
6530 #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
6531 #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
6532 #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
6533 #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
6534 #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
6535 #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
6536 #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
6537 #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
6538 #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
6539 #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
6540     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6541     CPU_POWERPC_MPC8xx             = 0x00500000,
6542 #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
6543 #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
6544 #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
6545 #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
6546 #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
6547 #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
6548 #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
6549 #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
6550 #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
6551 #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
6552 #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
6553 #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
6554 #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
6555 #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
6556 #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
6557     /* G2 cores (aka PowerQUICC-II) */
6558     CPU_POWERPC_G2                 = 0x00810011,
6559     CPU_POWERPC_G2H4               = 0x80811010,
6560     CPU_POWERPC_G2gp               = 0x80821010,
6561     CPU_POWERPC_G2ls               = 0x90810010,
6562     CPU_POWERPC_MPC603             = 0x00810100,
6563     CPU_POWERPC_G2_HIP3            = 0x00810101,
6564     CPU_POWERPC_G2_HIP4            = 0x80811014,
6565     /*   G2_LE core (aka PowerQUICC-II) */
6566     CPU_POWERPC_G2LE               = 0x80820010,
6567     CPU_POWERPC_G2LEgp             = 0x80822010,
6568     CPU_POWERPC_G2LEls             = 0xA0822010,
6569     CPU_POWERPC_G2LEgp1            = 0x80822011,
6570     CPU_POWERPC_G2LEgp3            = 0x80822013,
6571     /* MPC52xx microcontrollers  */
6572     /* XXX: MPC 5121 ? */
6573 #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
6574 #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
6575 #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
6576 #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
6577 #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
6578 #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
6579 #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
6580 #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
6581     /* MPC82xx microcontrollers */
6582 #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
6583 #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
6584 #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
6585 #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
6586 #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
6587 #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
6588 #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
6589 #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
6590 #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
6591 #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
6592 #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
6593 #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
6594 #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
6595 #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
6596 #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
6597 #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
6598 #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
6599 #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
6600 #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
6601 #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
6602 #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
6603 #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
6604 #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
6605 #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
6606 #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
6607 #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
6608 #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
6609 #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
6610 #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
6611     /* e200 family */
6612     /* e200 cores */
6613 #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
6614 #if 0
6615     CPU_POWERPC_e200z0             = xxx,
6616 #endif
6617 #if 0
6618     CPU_POWERPC_e200z1             = xxx,
6619 #endif
6620 #if 0 /* ? */
6621     CPU_POWERPC_e200z3             = 0x81120000,
6622 #endif
6623     CPU_POWERPC_e200z5             = 0x81000000,
6624     CPU_POWERPC_e200z6             = 0x81120000,
6625     /* MPC55xx microcontrollers */
6626 #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
6627 #if 0
6628 #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
6629 #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
6630 #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
6631 #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
6632 #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
6633 #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
6634 #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
6635 #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
6636 #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
6637 #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
6638 #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
6639 #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
6640 #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
6641 #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
6642 #endif
6643 #if 0
6644 #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
6645 #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
6646 #endif
6647 #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
6648 #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
6649 #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
6650 #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
6651 #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
6652 #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
6653     /* e300 family */
6654     /* e300 cores */
6655 #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
6656     CPU_POWERPC_e300c1             = 0x00830010,
6657     CPU_POWERPC_e300c2             = 0x00840010,
6658     CPU_POWERPC_e300c3             = 0x00850010,
6659     CPU_POWERPC_e300c4             = 0x00860010,
6660     /* MPC83xx microcontrollers */
6661 #define CPU_POWERPC_MPC8313          CPU_POWERPC_e300c3
6662 #define CPU_POWERPC_MPC8313E         CPU_POWERPC_e300c3
6663 #define CPU_POWERPC_MPC8314          CPU_POWERPC_e300c3
6664 #define CPU_POWERPC_MPC8314E         CPU_POWERPC_e300c3
6665 #define CPU_POWERPC_MPC8315          CPU_POWERPC_e300c3
6666 #define CPU_POWERPC_MPC8315E         CPU_POWERPC_e300c3
6667 #define CPU_POWERPC_MPC8321          CPU_POWERPC_e300c2
6668 #define CPU_POWERPC_MPC8321E         CPU_POWERPC_e300c2
6669 #define CPU_POWERPC_MPC8323          CPU_POWERPC_e300c2
6670 #define CPU_POWERPC_MPC8323E         CPU_POWERPC_e300c2
6671 #define CPU_POWERPC_MPC8343A         CPU_POWERPC_e300c1
6672 #define CPU_POWERPC_MPC8343EA        CPU_POWERPC_e300c1
6673 #define CPU_POWERPC_MPC8347A         CPU_POWERPC_e300c1
6674 #define CPU_POWERPC_MPC8347AT        CPU_POWERPC_e300c1
6675 #define CPU_POWERPC_MPC8347AP        CPU_POWERPC_e300c1
6676 #define CPU_POWERPC_MPC8347EA        CPU_POWERPC_e300c1
6677 #define CPU_POWERPC_MPC8347EAT       CPU_POWERPC_e300c1
6678 #define CPU_POWERPC_MPC8347EAP       CPU_POWERPC_e300c1
6679 #define CPU_POWERPC_MPC8349          CPU_POWERPC_e300c1
6680 #define CPU_POWERPC_MPC8349A         CPU_POWERPC_e300c1
6681 #define CPU_POWERPC_MPC8349E         CPU_POWERPC_e300c1
6682 #define CPU_POWERPC_MPC8349EA        CPU_POWERPC_e300c1
6683 #define CPU_POWERPC_MPC8358E         CPU_POWERPC_e300c1
6684 #define CPU_POWERPC_MPC8360E         CPU_POWERPC_e300c1
6685 #define CPU_POWERPC_MPC8377          CPU_POWERPC_e300c4
6686 #define CPU_POWERPC_MPC8377E         CPU_POWERPC_e300c4
6687 #define CPU_POWERPC_MPC8378          CPU_POWERPC_e300c4
6688 #define CPU_POWERPC_MPC8378E         CPU_POWERPC_e300c4
6689 #define CPU_POWERPC_MPC8379          CPU_POWERPC_e300c4
6690 #define CPU_POWERPC_MPC8379E         CPU_POWERPC_e300c4
6691     /* e500 family */
6692     /* e500 cores  */
6693 #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
6694 #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
6695     CPU_POWERPC_e500_v10           = 0x80200010,
6696     CPU_POWERPC_e500_v20           = 0x80200020,
6697     CPU_POWERPC_e500v2_v10         = 0x80210010,
6698     CPU_POWERPC_e500v2_v11         = 0x80210011,
6699     CPU_POWERPC_e500v2_v20         = 0x80210020,
6700     CPU_POWERPC_e500v2_v21         = 0x80210021,
6701     CPU_POWERPC_e500v2_v22         = 0x80210022,
6702     CPU_POWERPC_e500v2_v30         = 0x80210030,
6703     /* MPC85xx microcontrollers */
6704 #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
6705 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
6706 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
6707 #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
6708 #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
6709 #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
6710 #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
6711 #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500_v10
6712 #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500_v20
6713 #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500_v20
6714 #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
6715 #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500_v20
6716 #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500_v20
6717 #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
6718 #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500_v20
6719 #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500_v20
6720 #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
6721 #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
6722 #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
6723 #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
6724 #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
6725 #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
6726 #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
6727 #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
6728 #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
6729 #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
6730 #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
6731 #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
6732 #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
6733 #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
6734 #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
6735 #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
6736 #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
6737 #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
6738 #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
6739 #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
6740 #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
6741 #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
6742 #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
6743 #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
6744 #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
6745 #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
6746 #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
6747 #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
6748 #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
6749 #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
6750 #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
6751 #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
6752 #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
6753 #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
6754 #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
6755 #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
6756 #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
6757 #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
6758 #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
6759 #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
6760 #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
6761 #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
6762 #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
6763 #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
6764 #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
6765 #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
6766 #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
6767 #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
6768 #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
6769 #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
6770 #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
6771 #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
6772 #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
6773 #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
6774     /* e600 family */
6775     /* e600 cores */
6776     CPU_POWERPC_e600               = 0x80040010,
6777     /* MPC86xx microcontrollers */
6778 #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
6779 #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
6780 #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
6781     /* PowerPC 6xx cores */
6782 #define CPU_POWERPC_601              CPU_POWERPC_601_v2
6783     CPU_POWERPC_601_v0             = 0x00010001,
6784     CPU_POWERPC_601_v1             = 0x00010001,
6785 #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
6786     CPU_POWERPC_601_v2             = 0x00010002,
6787     CPU_POWERPC_602                = 0x00050100,
6788     CPU_POWERPC_603                = 0x00030100,
6789 #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
6790     CPU_POWERPC_603E_v11           = 0x00060101,
6791     CPU_POWERPC_603E_v12           = 0x00060102,
6792     CPU_POWERPC_603E_v13           = 0x00060103,
6793     CPU_POWERPC_603E_v14           = 0x00060104,
6794     CPU_POWERPC_603E_v22           = 0x00060202,
6795     CPU_POWERPC_603E_v3            = 0x00060300,
6796     CPU_POWERPC_603E_v4            = 0x00060400,
6797     CPU_POWERPC_603E_v41           = 0x00060401,
6798     CPU_POWERPC_603E7t             = 0x00071201,
6799     CPU_POWERPC_603E7v             = 0x00070100,
6800     CPU_POWERPC_603E7v1            = 0x00070101,
6801     CPU_POWERPC_603E7v2            = 0x00070201,
6802     CPU_POWERPC_603E7              = 0x00070200,
6803     CPU_POWERPC_603P               = 0x00070000,
6804 #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
6805     /* XXX: missing 0x00040303 (604) */
6806     CPU_POWERPC_604                = 0x00040103,
6807 #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
6808     /* XXX: missing 0x00091203 */
6809     /* XXX: missing 0x00092110 */
6810     /* XXX: missing 0x00092120 */
6811     CPU_POWERPC_604E_v10           = 0x00090100,
6812     CPU_POWERPC_604E_v22           = 0x00090202,
6813     CPU_POWERPC_604E_v24           = 0x00090204,
6814     /* XXX: missing 0x000a0100 */
6815     /* XXX: missing 0x00093102 */
6816     CPU_POWERPC_604R               = 0x000a0101,
6817 #if 0
6818     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
6819 #endif
6820     /* PowerPC 740/750 cores (aka G3) */
6821     /* XXX: missing 0x00084202 */
6822 #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
6823     CPU_POWERPC_7x0_v10            = 0x00080100,
6824     CPU_POWERPC_7x0_v20            = 0x00080200,
6825     CPU_POWERPC_7x0_v21            = 0x00080201,
6826     CPU_POWERPC_7x0_v22            = 0x00080202,
6827     CPU_POWERPC_7x0_v30            = 0x00080300,
6828     CPU_POWERPC_7x0_v31            = 0x00080301,
6829     CPU_POWERPC_740E               = 0x00080100,
6830     CPU_POWERPC_750E               = 0x00080200,
6831     CPU_POWERPC_7x0P               = 0x10080000,
6832     /* XXX: missing 0x00087010 (CL ?) */
6833 #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
6834     CPU_POWERPC_750CL_v10          = 0x00087200,
6835     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
6836 #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
6837     CPU_POWERPC_750CX_v10          = 0x00082100,
6838     CPU_POWERPC_750CX_v20          = 0x00082200,
6839     CPU_POWERPC_750CX_v21          = 0x00082201,
6840     CPU_POWERPC_750CX_v22          = 0x00082202,
6841 #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
6842     CPU_POWERPC_750CXE_v21         = 0x00082211,
6843     CPU_POWERPC_750CXE_v22         = 0x00082212,
6844     CPU_POWERPC_750CXE_v23         = 0x00082213,
6845     CPU_POWERPC_750CXE_v24         = 0x00082214,
6846     CPU_POWERPC_750CXE_v24b        = 0x00083214,
6847     CPU_POWERPC_750CXE_v30         = 0x00082310,
6848     CPU_POWERPC_750CXE_v31         = 0x00082311,
6849     CPU_POWERPC_750CXE_v31b        = 0x00083311,
6850     CPU_POWERPC_750CXR             = 0x00083410,
6851     CPU_POWERPC_750FL              = 0x70000203,
6852 #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
6853     CPU_POWERPC_750FX_v10          = 0x70000100,
6854     CPU_POWERPC_750FX_v20          = 0x70000200,
6855     CPU_POWERPC_750FX_v21          = 0x70000201,
6856     CPU_POWERPC_750FX_v22          = 0x70000202,
6857     CPU_POWERPC_750FX_v23          = 0x70000203,
6858     CPU_POWERPC_750GL              = 0x70020102,
6859 #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
6860     CPU_POWERPC_750GX_v10          = 0x70020100,
6861     CPU_POWERPC_750GX_v11          = 0x70020101,
6862     CPU_POWERPC_750GX_v12          = 0x70020102,
6863 #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
6864     CPU_POWERPC_750L_v20           = 0x00088200,
6865     CPU_POWERPC_750L_v21           = 0x00088201,
6866     CPU_POWERPC_750L_v22           = 0x00088202,
6867     CPU_POWERPC_750L_v30           = 0x00088300,
6868     CPU_POWERPC_750L_v32           = 0x00088302,
6869     /* PowerPC 745/755 cores */
6870 #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
6871     CPU_POWERPC_7x5_v10            = 0x00083100,
6872     CPU_POWERPC_7x5_v11            = 0x00083101,
6873     CPU_POWERPC_7x5_v20            = 0x00083200,
6874     CPU_POWERPC_7x5_v21            = 0x00083201,
6875     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
6876     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
6877     CPU_POWERPC_7x5_v24            = 0x00083204,
6878     CPU_POWERPC_7x5_v25            = 0x00083205,
6879     CPU_POWERPC_7x5_v26            = 0x00083206,
6880     CPU_POWERPC_7x5_v27            = 0x00083207,
6881     CPU_POWERPC_7x5_v28            = 0x00083208,
6882 #if 0
6883     CPU_POWERPC_7x5P               = xxx,
6884 #endif
6885     /* PowerPC 74xx cores (aka G4) */
6886     /* XXX: missing 0x000C1101 */
6887 #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
6888     CPU_POWERPC_7400_v10           = 0x000C0100,
6889     CPU_POWERPC_7400_v11           = 0x000C0101,
6890     CPU_POWERPC_7400_v20           = 0x000C0200,
6891     CPU_POWERPC_7400_v21           = 0x000C0201,
6892     CPU_POWERPC_7400_v22           = 0x000C0202,
6893     CPU_POWERPC_7400_v26           = 0x000C0206,
6894     CPU_POWERPC_7400_v27           = 0x000C0207,
6895     CPU_POWERPC_7400_v28           = 0x000C0208,
6896     CPU_POWERPC_7400_v29           = 0x000C0209,
6897 #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
6898     CPU_POWERPC_7410_v10           = 0x800C1100,
6899     CPU_POWERPC_7410_v11           = 0x800C1101,
6900     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
6901     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
6902     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
6903 #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
6904     CPU_POWERPC_7448_v10           = 0x80040100,
6905     CPU_POWERPC_7448_v11           = 0x80040101,
6906     CPU_POWERPC_7448_v20           = 0x80040200,
6907     CPU_POWERPC_7448_v21           = 0x80040201,
6908 #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
6909     CPU_POWERPC_7450_v10           = 0x80000100,
6910     CPU_POWERPC_7450_v11           = 0x80000101,
6911     CPU_POWERPC_7450_v12           = 0x80000102,
6912     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
6913     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
6914 #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
6915     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
6916     /* XXX: this entry might be a bug in some documentation */
6917     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
6918 #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
6919     CPU_POWERPC_74x5_v10           = 0x80010100,
6920     /* XXX: missing 0x80010200 */
6921     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
6922     CPU_POWERPC_74x5_v32           = 0x80010302,
6923     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
6924     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
6925 #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
6926     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
6927     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
6928     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
6929 #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
6930     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
6931     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
6932     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
6933     /* 64 bits PowerPC */
6934 #if defined(TARGET_PPC64)
6935     CPU_POWERPC_620                = 0x00140000,
6936     CPU_POWERPC_630                = 0x00400000,
6937     CPU_POWERPC_631                = 0x00410104,
6938     CPU_POWERPC_POWER4             = 0x00350000,
6939     CPU_POWERPC_POWER4P            = 0x00380000,
6940      /* XXX: missing 0x003A0201 */
6941     CPU_POWERPC_POWER5             = 0x003A0203,
6942 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
6943     CPU_POWERPC_POWER5P            = 0x003B0000,
6944 #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
6945     CPU_POWERPC_POWER6             = 0x003E0000,
6946     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
6947     CPU_POWERPC_POWER6A            = 0x0F000002,
6948     CPU_POWERPC_970                = 0x00390202,
6949 #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
6950     CPU_POWERPC_970FX_v10          = 0x00391100,
6951     CPU_POWERPC_970FX_v20          = 0x003C0200,
6952     CPU_POWERPC_970FX_v21          = 0x003C0201,
6953     CPU_POWERPC_970FX_v30          = 0x003C0300,
6954     CPU_POWERPC_970FX_v31          = 0x003C0301,
6955     CPU_POWERPC_970GX              = 0x00450000,
6956 #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
6957     CPU_POWERPC_970MP_v10          = 0x00440100,
6958     CPU_POWERPC_970MP_v11          = 0x00440101,
6959 #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
6960     CPU_POWERPC_CELL_v10           = 0x00700100,
6961     CPU_POWERPC_CELL_v20           = 0x00700400,
6962     CPU_POWERPC_CELL_v30           = 0x00700500,
6963     CPU_POWERPC_CELL_v31           = 0x00700501,
6964 #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
6965     CPU_POWERPC_RS64               = 0x00330000,
6966     CPU_POWERPC_RS64II             = 0x00340000,
6967     CPU_POWERPC_RS64III            = 0x00360000,
6968     CPU_POWERPC_RS64IV             = 0x00370000,
6969 #endif /* defined(TARGET_PPC64) */
6970     /* Original POWER */
6971     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6972      * POWER2 (RIOS2) & RSC2 (P2SC) here
6973      */
6974 #if 0
6975     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
6976 #endif
6977 #if 0
6978     CPU_POWER2                     = xxx, /* 0x40000 ? */
6979 #endif
6980     /* PA Semi core */
6981     CPU_POWERPC_PA6T               = 0x00900000,
6982 };
6983
6984 /* System version register (used on MPC 8xxx)                                */
6985 enum {
6986     POWERPC_SVR_NONE               = 0x00000000,
6987 #define POWERPC_SVR_52xx             POWERPC_SVR_5200
6988 #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
6989     POWERPC_SVR_5200_v10           = 0x80110010,
6990     POWERPC_SVR_5200_v11           = 0x80110011,
6991     POWERPC_SVR_5200_v12           = 0x80110012,
6992 #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
6993     POWERPC_SVR_5200B_v20          = 0x80110020,
6994     POWERPC_SVR_5200B_v21          = 0x80110021,
6995 #define POWERPC_SVR_55xx             POWERPC_SVR_5567
6996 #if 0
6997     POWERPC_SVR_5533               = xxx,
6998 #endif
6999 #if 0
7000     POWERPC_SVR_5534               = xxx,
7001 #endif
7002 #if 0
7003     POWERPC_SVR_5553               = xxx,
7004 #endif
7005 #if 0
7006     POWERPC_SVR_5554               = xxx,
7007 #endif
7008 #if 0
7009     POWERPC_SVR_5561               = xxx,
7010 #endif
7011 #if 0
7012     POWERPC_SVR_5565               = xxx,
7013 #endif
7014 #if 0
7015     POWERPC_SVR_5566               = xxx,
7016 #endif
7017 #if 0
7018     POWERPC_SVR_5567               = xxx,
7019 #endif
7020 #if 0
7021     POWERPC_SVR_8313               = xxx,
7022 #endif
7023 #if 0
7024     POWERPC_SVR_8313E              = xxx,
7025 #endif
7026 #if 0
7027     POWERPC_SVR_8314               = xxx,
7028 #endif
7029 #if 0
7030     POWERPC_SVR_8314E              = xxx,
7031 #endif
7032 #if 0
7033     POWERPC_SVR_8315               = xxx,
7034 #endif
7035 #if 0
7036     POWERPC_SVR_8315E              = xxx,
7037 #endif
7038 #if 0
7039     POWERPC_SVR_8321               = xxx,
7040 #endif
7041 #if 0
7042     POWERPC_SVR_8321E              = xxx,
7043 #endif
7044 #if 0
7045     POWERPC_SVR_8323               = xxx,
7046 #endif
7047 #if 0
7048     POWERPC_SVR_8323E              = xxx,
7049 #endif
7050     POWERPC_SVR_8343A              = 0x80570030,
7051     POWERPC_SVR_8343EA             = 0x80560030,
7052 #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
7053     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
7054     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
7055 #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
7056     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
7057     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
7058     POWERPC_SVR_8349               = 0x80510010,
7059     POWERPC_SVR_8349A              = 0x80510030,
7060     POWERPC_SVR_8349E              = 0x80500010,
7061     POWERPC_SVR_8349EA             = 0x80500030,
7062 #if 0
7063     POWERPC_SVR_8358E              = xxx,
7064 #endif
7065 #if 0
7066     POWERPC_SVR_8360E              = xxx,
7067 #endif
7068 #define POWERPC_SVR_E500             0x40000000
7069     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
7070     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
7071     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
7072     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
7073     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
7074     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
7075 #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
7076     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
7077     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
7078 #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
7079     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
7080     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
7081 #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
7082     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
7083     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
7084     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
7085 #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
7086     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
7087     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
7088 #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
7089     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
7090     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
7091 #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
7092     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
7093     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
7094     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
7095     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
7096 #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
7097     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
7098     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
7099     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
7100     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
7101 #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
7102     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
7103     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
7104 #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
7105     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
7106     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
7107 #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
7108     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
7109     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
7110 #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
7111     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
7112     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
7113 #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
7114     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
7115     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
7116 #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
7117     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
7118     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
7119     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
7120     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
7121 #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
7122     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
7123     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
7124     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
7125     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
7126 #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
7127     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
7128     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
7129 #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
7130     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
7131     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
7132 #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
7133     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
7134     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
7135     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
7136     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
7137     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
7138     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
7139     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
7140     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
7141     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
7142 #if 0
7143     POWERPC_SVR_8610               = xxx,
7144 #endif
7145     POWERPC_SVR_8641               = 0x80900021,
7146     POWERPC_SVR_8641D              = 0x80900121,
7147 };
7148
7149 /*****************************************************************************/
7150 /* PowerPC CPU definitions                                                   */
7151 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
7152     {                                                                         \
7153         .name        = _name,                                                 \
7154         .pvr         = _pvr,                                                  \
7155         .svr         = _svr,                                                  \
7156         .insns_flags = glue(POWERPC_INSNS_,_type),                            \
7157         .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
7158         .mmu_model   = glue(POWERPC_MMU_,_type),                              \
7159         .excp_model  = glue(POWERPC_EXCP_,_type),                             \
7160         .bus_model   = glue(POWERPC_INPUT_,_type),                            \
7161         .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
7162         .flags       = glue(POWERPC_FLAG_,_type),                             \
7163         .init_proc   = &glue(init_proc_,_type),                               \
7164         .check_pow   = &glue(check_pow_,_type),                               \
7165     }
7166 #define POWERPC_DEF(_name, _pvr, _type)                                       \
7167 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7168
7169 static const ppc_def_t ppc_defs[] = {
7170     /* Embedded PowerPC                                                      */
7171     /* PowerPC 401 family                                                    */
7172     /* Generic PowerPC 401 */
7173     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
7174     /* PowerPC 401 cores                                                     */
7175     /* PowerPC 401A1 */
7176     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
7177     /* PowerPC 401B2                                                         */
7178     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
7179 #if defined (TODO)
7180     /* PowerPC 401B3                                                         */
7181     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
7182 #endif
7183     /* PowerPC 401C2                                                         */
7184     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
7185     /* PowerPC 401D2                                                         */
7186     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
7187     /* PowerPC 401E2                                                         */
7188     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
7189     /* PowerPC 401F2                                                         */
7190     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
7191     /* PowerPC 401G2                                                         */
7192     /* XXX: to be checked */
7193     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
7194     /* PowerPC 401 microcontrolers                                           */
7195 #if defined (TODO)
7196     /* PowerPC 401GF                                                         */
7197     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
7198 #endif
7199     /* IOP480 (401 microcontroler)                                           */
7200     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
7201     /* IBM Processor for Network Resources                                   */
7202     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
7203 #if defined (TODO)
7204     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
7205 #endif
7206     /* PowerPC 403 family                                                    */
7207     /* Generic PowerPC 403                                                   */
7208     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
7209     /* PowerPC 403 microcontrolers                                           */
7210     /* PowerPC 403 GA                                                        */
7211     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
7212     /* PowerPC 403 GB                                                        */
7213     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
7214     /* PowerPC 403 GC                                                        */
7215     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
7216     /* PowerPC 403 GCX                                                       */
7217     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
7218 #if defined (TODO)
7219     /* PowerPC 403 GP                                                        */
7220     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
7221 #endif
7222     /* PowerPC 405 family                                                    */
7223     /* Generic PowerPC 405                                                   */
7224     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
7225     /* PowerPC 405 cores                                                     */
7226 #if defined (TODO)
7227     /* PowerPC 405 A3                                                        */
7228     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
7229 #endif
7230 #if defined (TODO)
7231     /* PowerPC 405 A4                                                        */
7232     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
7233 #endif
7234 #if defined (TODO)
7235     /* PowerPC 405 B3                                                        */
7236     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
7237 #endif
7238 #if defined (TODO)
7239     /* PowerPC 405 B4                                                        */
7240     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
7241 #endif
7242 #if defined (TODO)
7243     /* PowerPC 405 C3                                                        */
7244     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
7245 #endif
7246 #if defined (TODO)
7247     /* PowerPC 405 C4                                                        */
7248     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
7249 #endif
7250     /* PowerPC 405 D2                                                        */
7251     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
7252 #if defined (TODO)
7253     /* PowerPC 405 D3                                                        */
7254     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
7255 #endif
7256     /* PowerPC 405 D4                                                        */
7257     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
7258 #if defined (TODO)
7259     /* PowerPC 405 D5                                                        */
7260     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
7261 #endif
7262 #if defined (TODO)
7263     /* PowerPC 405 E4                                                        */
7264     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
7265 #endif
7266 #if defined (TODO)
7267     /* PowerPC 405 F4                                                        */
7268     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
7269 #endif
7270 #if defined (TODO)
7271     /* PowerPC 405 F5                                                        */
7272     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
7273 #endif
7274 #if defined (TODO)
7275     /* PowerPC 405 F6                                                        */
7276     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
7277 #endif
7278     /* PowerPC 405 microcontrolers                                           */
7279     /* PowerPC 405 CR                                                        */
7280     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
7281     /* PowerPC 405 CRa                                                       */
7282     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
7283     /* PowerPC 405 CRb                                                       */
7284     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
7285     /* PowerPC 405 CRc                                                       */
7286     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
7287     /* PowerPC 405 EP                                                        */
7288     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
7289 #if defined(TODO)
7290     /* PowerPC 405 EXr                                                       */
7291     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
7292 #endif
7293     /* PowerPC 405 EZ                                                        */
7294     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
7295 #if defined(TODO)
7296     /* PowerPC 405 FX                                                        */
7297     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
7298 #endif
7299     /* PowerPC 405 GP                                                        */
7300     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
7301     /* PowerPC 405 GPa                                                       */
7302     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
7303     /* PowerPC 405 GPb                                                       */
7304     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
7305     /* PowerPC 405 GPc                                                       */
7306     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
7307     /* PowerPC 405 GPd                                                       */
7308     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
7309     /* PowerPC 405 GPe                                                       */
7310     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
7311     /* PowerPC 405 GPR                                                       */
7312     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
7313 #if defined(TODO)
7314     /* PowerPC 405 H                                                         */
7315     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
7316 #endif
7317 #if defined(TODO)
7318     /* PowerPC 405 L                                                         */
7319     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
7320 #endif
7321     /* PowerPC 405 LP                                                        */
7322     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
7323 #if defined(TODO)
7324     /* PowerPC 405 PM                                                        */
7325     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
7326 #endif
7327 #if defined(TODO)
7328     /* PowerPC 405 PS                                                        */
7329     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
7330 #endif
7331 #if defined(TODO)
7332     /* PowerPC 405 S                                                         */
7333     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
7334 #endif
7335     /* Npe405 H                                                              */
7336     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
7337     /* Npe405 H2                                                             */
7338     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
7339     /* Npe405 L                                                              */
7340     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
7341     /* Npe4GS3                                                               */
7342     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
7343 #if defined (TODO)
7344     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
7345 #endif
7346 #if defined (TODO)
7347     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
7348 #endif
7349 #if defined (TODO)
7350     /* PowerPC LC77700 (Sanyo)                                               */
7351     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
7352 #endif
7353     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
7354 #if defined (TODO)
7355     /* STB010000                                                             */
7356     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
7357 #endif
7358 #if defined (TODO)
7359     /* STB01010                                                              */
7360     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
7361 #endif
7362 #if defined (TODO)
7363     /* STB0210                                                               */
7364     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
7365 #endif
7366     /* STB03xx                                                               */
7367     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
7368 #if defined (TODO)
7369     /* STB043x                                                               */
7370     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
7371 #endif
7372 #if defined (TODO)
7373     /* STB045x                                                               */
7374     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
7375 #endif
7376     /* STB04xx                                                               */
7377     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
7378     /* STB25xx                                                               */
7379     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
7380 #if defined (TODO)
7381     /* STB130                                                                */
7382     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
7383 #endif
7384     /* Xilinx PowerPC 405 cores                                              */
7385     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
7386     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
7387     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
7388     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
7389 #if defined (TODO)
7390     /* Zarlink ZL10310                                                       */
7391     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
7392 #endif
7393 #if defined (TODO)
7394     /* Zarlink ZL10311                                                       */
7395     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
7396 #endif
7397 #if defined (TODO)
7398     /* Zarlink ZL10320                                                       */
7399     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
7400 #endif
7401 #if defined (TODO)
7402     /* Zarlink ZL10321                                                       */
7403     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
7404 #endif
7405     /* PowerPC 440 family                                                    */
7406 #if defined(TODO_USER_ONLY)
7407     /* Generic PowerPC 440                                                   */
7408     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
7409 #endif
7410     /* PowerPC 440 cores                                                     */
7411 #if defined (TODO)
7412     /* PowerPC 440 A4                                                        */
7413     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
7414 #endif
7415 #if defined (TODO)
7416     /* PowerPC 440 A5                                                        */
7417     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
7418 #endif
7419 #if defined (TODO)
7420     /* PowerPC 440 B4                                                        */
7421     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
7422 #endif
7423 #if defined (TODO)
7424     /* PowerPC 440 G4                                                        */
7425     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
7426 #endif
7427 #if defined (TODO)
7428     /* PowerPC 440 F5                                                        */
7429     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
7430 #endif
7431 #if defined (TODO)
7432     /* PowerPC 440 G5                                                        */
7433     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
7434 #endif
7435 #if defined (TODO)
7436     /* PowerPC 440H4                                                         */
7437     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
7438 #endif
7439 #if defined (TODO)
7440     /* PowerPC 440H6                                                         */
7441     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
7442 #endif
7443     /* PowerPC 440 microcontrolers                                           */
7444 #if defined(TODO_USER_ONLY)
7445     /* PowerPC 440 EP                                                        */
7446     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
7447 #endif
7448 #if defined(TODO_USER_ONLY)
7449     /* PowerPC 440 EPa                                                       */
7450     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
7451 #endif
7452 #if defined(TODO_USER_ONLY)
7453     /* PowerPC 440 EPb                                                       */
7454     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
7455 #endif
7456 #if defined(TODO_USER_ONLY)
7457     /* PowerPC 440 EPX                                                       */
7458     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
7459 #endif
7460 #if defined(TODO_USER_ONLY)
7461     /* PowerPC 440 GP                                                        */
7462     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
7463 #endif
7464 #if defined(TODO_USER_ONLY)
7465     /* PowerPC 440 GPb                                                       */
7466     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
7467 #endif
7468 #if defined(TODO_USER_ONLY)
7469     /* PowerPC 440 GPc                                                       */
7470     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
7471 #endif
7472 #if defined(TODO_USER_ONLY)
7473     /* PowerPC 440 GR                                                        */
7474     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
7475 #endif
7476 #if defined(TODO_USER_ONLY)
7477     /* PowerPC 440 GRa                                                       */
7478     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
7479 #endif
7480 #if defined(TODO_USER_ONLY)
7481     /* PowerPC 440 GRX                                                       */
7482     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
7483 #endif
7484 #if defined(TODO_USER_ONLY)
7485     /* PowerPC 440 GX                                                        */
7486     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
7487 #endif
7488 #if defined(TODO_USER_ONLY)
7489     /* PowerPC 440 GXa                                                       */
7490     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
7491 #endif
7492 #if defined(TODO_USER_ONLY)
7493     /* PowerPC 440 GXb                                                       */
7494     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
7495 #endif
7496 #if defined(TODO_USER_ONLY)
7497     /* PowerPC 440 GXc                                                       */
7498     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
7499 #endif
7500 #if defined(TODO_USER_ONLY)
7501     /* PowerPC 440 GXf                                                       */
7502     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
7503 #endif
7504 #if defined(TODO)
7505     /* PowerPC 440 S                                                         */
7506     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
7507 #endif
7508 #if defined(TODO_USER_ONLY)
7509     /* PowerPC 440 SP                                                        */
7510     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
7511 #endif
7512 #if defined(TODO_USER_ONLY)
7513     /* PowerPC 440 SP2                                                       */
7514     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
7515 #endif
7516 #if defined(TODO_USER_ONLY)
7517     /* PowerPC 440 SPE                                                       */
7518     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
7519 #endif
7520     /* PowerPC 460 family                                                    */
7521 #if defined (TODO)
7522     /* Generic PowerPC 464                                                   */
7523     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
7524 #endif
7525     /* PowerPC 464 microcontrolers                                           */
7526 #if defined (TODO)
7527     /* PowerPC 464H90                                                        */
7528     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
7529 #endif
7530 #if defined (TODO)
7531     /* PowerPC 464H90F                                                       */
7532     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
7533 #endif
7534     /* Freescale embedded PowerPC cores                                      */
7535     /* MPC5xx family (aka RCPU)                                              */
7536 #if defined(TODO_USER_ONLY)
7537     /* Generic MPC5xx core                                                   */
7538     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
7539 #endif
7540 #if defined(TODO_USER_ONLY)
7541     /* Codename for MPC5xx core                                              */
7542     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
7543 #endif
7544     /* MPC5xx microcontrollers                                               */
7545 #if defined(TODO_USER_ONLY)
7546     /* MGT560                                                                */
7547     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
7548 #endif
7549 #if defined(TODO_USER_ONLY)
7550     /* MPC509                                                                */
7551     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
7552 #endif
7553 #if defined(TODO_USER_ONLY)
7554     /* MPC533                                                                */
7555     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
7556 #endif
7557 #if defined(TODO_USER_ONLY)
7558     /* MPC534                                                                */
7559     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
7560 #endif
7561 #if defined(TODO_USER_ONLY)
7562     /* MPC555                                                                */
7563     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
7564 #endif
7565 #if defined(TODO_USER_ONLY)
7566     /* MPC556                                                                */
7567     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
7568 #endif
7569 #if defined(TODO_USER_ONLY)
7570     /* MPC560                                                                */
7571     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
7572 #endif
7573 #if defined(TODO_USER_ONLY)
7574     /* MPC561                                                                */
7575     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
7576 #endif
7577 #if defined(TODO_USER_ONLY)
7578     /* MPC562                                                                */
7579     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
7580 #endif
7581 #if defined(TODO_USER_ONLY)
7582     /* MPC563                                                                */
7583     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
7584 #endif
7585 #if defined(TODO_USER_ONLY)
7586     /* MPC564                                                                */
7587     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
7588 #endif
7589 #if defined(TODO_USER_ONLY)
7590     /* MPC565                                                                */
7591     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
7592 #endif
7593 #if defined(TODO_USER_ONLY)
7594     /* MPC566                                                                */
7595     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
7596 #endif
7597     /* MPC8xx family (aka PowerQUICC)                                        */
7598 #if defined(TODO_USER_ONLY)
7599     /* Generic MPC8xx core                                                   */
7600     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
7601 #endif
7602 #if defined(TODO_USER_ONLY)
7603     /* Codename for MPC8xx core                                              */
7604     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
7605 #endif
7606     /* MPC8xx microcontrollers                                               */
7607 #if defined(TODO_USER_ONLY)
7608     /* MGT823                                                                */
7609     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
7610 #endif
7611 #if defined(TODO_USER_ONLY)
7612     /* MPC821                                                                */
7613     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
7614 #endif
7615 #if defined(TODO_USER_ONLY)
7616     /* MPC823                                                                */
7617     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
7618 #endif
7619 #if defined(TODO_USER_ONLY)
7620     /* MPC850                                                                */
7621     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
7622 #endif
7623 #if defined(TODO_USER_ONLY)
7624     /* MPC852T                                                               */
7625     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
7626 #endif
7627 #if defined(TODO_USER_ONLY)
7628     /* MPC855T                                                               */
7629     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
7630 #endif
7631 #if defined(TODO_USER_ONLY)
7632     /* MPC857                                                                */
7633     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
7634 #endif
7635 #if defined(TODO_USER_ONLY)
7636     /* MPC859                                                                */
7637     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
7638 #endif
7639 #if defined(TODO_USER_ONLY)
7640     /* MPC860                                                                */
7641     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
7642 #endif
7643 #if defined(TODO_USER_ONLY)
7644     /* MPC862                                                                */
7645     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
7646 #endif
7647 #if defined(TODO_USER_ONLY)
7648     /* MPC866                                                                */
7649     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
7650 #endif
7651 #if defined(TODO_USER_ONLY)
7652     /* MPC870                                                                */
7653     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
7654 #endif
7655 #if defined(TODO_USER_ONLY)
7656     /* MPC875                                                                */
7657     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
7658 #endif
7659 #if defined(TODO_USER_ONLY)
7660     /* MPC880                                                                */
7661     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
7662 #endif
7663 #if defined(TODO_USER_ONLY)
7664     /* MPC885                                                                */
7665     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
7666 #endif
7667     /* MPC82xx family (aka PowerQUICC-II)                                    */
7668     /* Generic MPC52xx core                                                  */
7669     POWERPC_DEF_SVR("MPC52xx",
7670                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
7671     /* Generic MPC82xx core                                                  */
7672     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
7673     /* Codename for MPC82xx                                                  */
7674     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
7675     /* PowerPC G2 core                                                       */
7676     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
7677     /* PowerPC G2 H4 core                                                    */
7678     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
7679     /* PowerPC G2 GP core                                                    */
7680     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
7681     /* PowerPC G2 LS core                                                    */
7682     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
7683     /* PowerPC G2 HiP3 core                                                  */
7684     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
7685     /* PowerPC G2 HiP4 core                                                  */
7686     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
7687     /* PowerPC MPC603 core                                                   */
7688     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
7689     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
7690     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
7691     /* PowerPC G2LE GP core                                                  */
7692     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
7693     /* PowerPC G2LE LS core                                                  */
7694     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
7695     /* PowerPC G2LE GP1 core                                                 */
7696     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
7697     /* PowerPC G2LE GP3 core                                                 */
7698     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
7699     /* PowerPC MPC603 microcontrollers                                       */
7700     /* MPC8240                                                               */
7701     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
7702     /* PowerPC G2 microcontrollers                                           */
7703 #if defined(TODO)
7704     /* MPC5121                                                               */
7705     POWERPC_DEF_SVR("MPC5121",
7706                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
7707 #endif
7708     /* MPC5200                                                               */
7709     POWERPC_DEF_SVR("MPC5200",
7710                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
7711     /* MPC5200 v1.0                                                          */
7712     POWERPC_DEF_SVR("MPC5200_v10",
7713                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
7714     /* MPC5200 v1.1                                                          */
7715     POWERPC_DEF_SVR("MPC5200_v11",
7716                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
7717     /* MPC5200 v1.2                                                          */
7718     POWERPC_DEF_SVR("MPC5200_v12",
7719                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
7720     /* MPC5200B                                                              */
7721     POWERPC_DEF_SVR("MPC5200B",
7722                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
7723     /* MPC5200B v2.0                                                         */
7724     POWERPC_DEF_SVR("MPC5200B_v20",
7725                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7726     /* MPC5200B v2.1                                                         */
7727     POWERPC_DEF_SVR("MPC5200B_v21",
7728                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7729     /* MPC8241                                                               */
7730     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
7731     /* MPC8245                                                               */
7732     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
7733     /* MPC8247                                                               */
7734     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
7735     /* MPC8248                                                               */
7736     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
7737     /* MPC8250                                                               */
7738     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
7739     /* MPC8250 HiP3                                                          */
7740     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
7741     /* MPC8250 HiP4                                                          */
7742     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
7743     /* MPC8255                                                               */
7744     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
7745     /* MPC8255 HiP3                                                          */
7746     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
7747     /* MPC8255 HiP4                                                          */
7748     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
7749     /* MPC8260                                                               */
7750     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
7751     /* MPC8260 HiP3                                                          */
7752     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
7753     /* MPC8260 HiP4                                                          */
7754     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
7755     /* MPC8264                                                               */
7756     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
7757     /* MPC8264 HiP3                                                          */
7758     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
7759     /* MPC8264 HiP4                                                          */
7760     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
7761     /* MPC8265                                                               */
7762     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
7763     /* MPC8265 HiP3                                                          */
7764     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
7765     /* MPC8265 HiP4                                                          */
7766     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
7767     /* MPC8266                                                               */
7768     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
7769     /* MPC8266 HiP3                                                          */
7770     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
7771     /* MPC8266 HiP4                                                          */
7772     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
7773     /* MPC8270                                                               */
7774     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
7775     /* MPC8271                                                               */
7776     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
7777     /* MPC8272                                                               */
7778     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
7779     /* MPC8275                                                               */
7780     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
7781     /* MPC8280                                                               */
7782     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
7783     /* e200 family                                                           */
7784     /* Generic PowerPC e200 core                                             */
7785     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
7786     /* Generic MPC55xx core                                                  */
7787 #if defined (TODO)
7788     POWERPC_DEF_SVR("MPC55xx",
7789                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
7790 #endif
7791 #if defined (TODO)
7792     /* PowerPC e200z0 core                                                   */
7793     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
7794 #endif
7795 #if defined (TODO)
7796     /* PowerPC e200z1 core                                                   */
7797     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
7798 #endif
7799 #if defined (TODO)
7800     /* PowerPC e200z3 core                                                   */
7801     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
7802 #endif
7803     /* PowerPC e200z5 core                                                   */
7804     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
7805     /* PowerPC e200z6 core                                                   */
7806     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
7807     /* PowerPC e200 microcontrollers                                         */
7808 #if defined (TODO)
7809     /* MPC5514E                                                              */
7810     POWERPC_DEF_SVR("MPC5514E",
7811                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
7812 #endif
7813 #if defined (TODO)
7814     /* MPC5514E v0                                                           */
7815     POWERPC_DEF_SVR("MPC5514E_v0",
7816                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
7817 #endif
7818 #if defined (TODO)
7819     /* MPC5514E v1                                                           */
7820     POWERPC_DEF_SVR("MPC5514E_v1",
7821                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
7822 #endif
7823 #if defined (TODO)
7824     /* MPC5514G                                                              */
7825     POWERPC_DEF_SVR("MPC5514G",
7826                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
7827 #endif
7828 #if defined (TODO)
7829     /* MPC5514G v0                                                           */
7830     POWERPC_DEF_SVR("MPC5514G_v0",
7831                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
7832 #endif
7833 #if defined (TODO)
7834     /* MPC5514G v1                                                           */
7835     POWERPC_DEF_SVR("MPC5514G_v1",
7836                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
7837 #endif
7838 #if defined (TODO)
7839     /* MPC5515S                                                              */
7840     POWERPC_DEF_SVR("MPC5515S",
7841                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
7842 #endif
7843 #if defined (TODO)
7844     /* MPC5516E                                                              */
7845     POWERPC_DEF_SVR("MPC5516E",
7846                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
7847 #endif
7848 #if defined (TODO)
7849     /* MPC5516E v0                                                           */
7850     POWERPC_DEF_SVR("MPC5516E_v0",
7851                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
7852 #endif
7853 #if defined (TODO)
7854     /* MPC5516E v1                                                           */
7855     POWERPC_DEF_SVR("MPC5516E_v1",
7856                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
7857 #endif
7858 #if defined (TODO)
7859     /* MPC5516G                                                              */
7860     POWERPC_DEF_SVR("MPC5516G",
7861                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
7862 #endif
7863 #if defined (TODO)
7864     /* MPC5516G v0                                                           */
7865     POWERPC_DEF_SVR("MPC5516G_v0",
7866                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
7867 #endif
7868 #if defined (TODO)
7869     /* MPC5516G v1                                                           */
7870     POWERPC_DEF_SVR("MPC5516G_v1",
7871                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
7872 #endif
7873 #if defined (TODO)
7874     /* MPC5516S                                                              */
7875     POWERPC_DEF_SVR("MPC5516S",
7876                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
7877 #endif
7878 #if defined (TODO)
7879     /* MPC5533                                                               */
7880     POWERPC_DEF_SVR("MPC5533",
7881                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
7882 #endif
7883 #if defined (TODO)
7884     /* MPC5534                                                               */
7885     POWERPC_DEF_SVR("MPC5534",
7886                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
7887 #endif
7888 #if defined (TODO)
7889     /* MPC5553                                                               */
7890     POWERPC_DEF_SVR("MPC5553",
7891                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
7892 #endif
7893 #if defined (TODO)
7894     /* MPC5554                                                               */
7895     POWERPC_DEF_SVR("MPC5554",
7896                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
7897 #endif
7898 #if defined (TODO)
7899     /* MPC5561                                                               */
7900     POWERPC_DEF_SVR("MPC5561",
7901                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
7902 #endif
7903 #if defined (TODO)
7904     /* MPC5565                                                               */
7905     POWERPC_DEF_SVR("MPC5565",
7906                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
7907 #endif
7908 #if defined (TODO)
7909     /* MPC5566                                                               */
7910     POWERPC_DEF_SVR("MPC5566",
7911                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
7912 #endif
7913 #if defined (TODO)
7914     /* MPC5567                                                               */
7915     POWERPC_DEF_SVR("MPC5567",
7916                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
7917 #endif
7918     /* e300 family                                                           */
7919     /* Generic PowerPC e300 core                                             */
7920     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
7921     /* PowerPC e300c1 core                                                   */
7922     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
7923     /* PowerPC e300c2 core                                                   */
7924     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
7925     /* PowerPC e300c3 core                                                   */
7926     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
7927     /* PowerPC e300c4 core                                                   */
7928     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
7929     /* PowerPC e300 microcontrollers                                         */
7930 #if defined (TODO)
7931     /* MPC8313                                                               */
7932     POWERPC_DEF_SVR("MPC8313",
7933                     CPU_POWERPC_MPC8313,      POWERPC_SVR_8313,      e300),
7934 #endif
7935 #if defined (TODO)
7936     /* MPC8313E                                                              */
7937     POWERPC_DEF_SVR("MPC8313E",
7938                     CPU_POWERPC_MPC8313E,     POWERPC_SVR_8313E,     e300),
7939 #endif
7940 #if defined (TODO)
7941     /* MPC8314                                                               */
7942     POWERPC_DEF_SVR("MPC8314",
7943                     CPU_POWERPC_MPC8314,      POWERPC_SVR_8314,      e300),
7944 #endif
7945 #if defined (TODO)
7946     /* MPC8314E                                                              */
7947     POWERPC_DEF_SVR("MPC8314E",
7948                     CPU_POWERPC_MPC8314E,     POWERPC_SVR_8314E,     e300),
7949 #endif
7950 #if defined (TODO)
7951     /* MPC8315                                                               */
7952     POWERPC_DEF_SVR("MPC8315",
7953                     CPU_POWERPC_MPC8315,      POWERPC_SVR_8315,      e300),
7954 #endif
7955 #if defined (TODO)
7956     /* MPC8315E                                                              */
7957     POWERPC_DEF_SVR("MPC8315E",
7958                     CPU_POWERPC_MPC8315E,     POWERPC_SVR_8315E,     e300),
7959 #endif
7960 #if defined (TODO)
7961     /* MPC8321                                                               */
7962     POWERPC_DEF_SVR("MPC8321",
7963                     CPU_POWERPC_MPC8321,      POWERPC_SVR_8321,      e300),
7964 #endif
7965 #if defined (TODO)
7966     /* MPC8321E                                                              */
7967     POWERPC_DEF_SVR("MPC8321E",
7968                     CPU_POWERPC_MPC8321E,     POWERPC_SVR_8321E,     e300),
7969 #endif
7970 #if defined (TODO)
7971     /* MPC8323                                                               */
7972     POWERPC_DEF_SVR("MPC8323",
7973                     CPU_POWERPC_MPC8323,      POWERPC_SVR_8323,      e300),
7974 #endif
7975 #if defined (TODO)
7976     /* MPC8323E                                                              */
7977     POWERPC_DEF_SVR("MPC8323E",
7978                     CPU_POWERPC_MPC8323E,     POWERPC_SVR_8323E,     e300),
7979 #endif
7980     /* MPC8343A                                                              */
7981     POWERPC_DEF_SVR("MPC8343A",
7982                     CPU_POWERPC_MPC8343A,     POWERPC_SVR_8343A,     e300),
7983     /* MPC8343EA                                                             */
7984     POWERPC_DEF_SVR("MPC8343EA",
7985                     CPU_POWERPC_MPC8343EA,    POWERPC_SVR_8343EA,    e300),
7986     /* MPC8347A                                                              */
7987     POWERPC_DEF_SVR("MPC8347A",
7988                     CPU_POWERPC_MPC8347A,     POWERPC_SVR_8347A,     e300),
7989     /* MPC8347AT                                                             */
7990     POWERPC_DEF_SVR("MPC8347AT",
7991                     CPU_POWERPC_MPC8347AT,    POWERPC_SVR_8347AT,    e300),
7992     /* MPC8347AP                                                             */
7993     POWERPC_DEF_SVR("MPC8347AP",
7994                     CPU_POWERPC_MPC8347AP,    POWERPC_SVR_8347AP,    e300),
7995     /* MPC8347EA                                                             */
7996     POWERPC_DEF_SVR("MPC8347EA",
7997                     CPU_POWERPC_MPC8347EA,    POWERPC_SVR_8347EA,    e300),
7998     /* MPC8347EAT                                                            */
7999     POWERPC_DEF_SVR("MPC8347EAT",
8000                     CPU_POWERPC_MPC8347EAT,   POWERPC_SVR_8347EAT,   e300),
8001     /* MPC8343EAP                                                            */
8002     POWERPC_DEF_SVR("MPC8347EAP",
8003                     CPU_POWERPC_MPC8347EAP,   POWERPC_SVR_8347EAP,   e300),
8004     /* MPC8349                                                               */
8005     POWERPC_DEF_SVR("MPC8349",
8006                     CPU_POWERPC_MPC8349,      POWERPC_SVR_8349,      e300),
8007     /* MPC8349A                                                              */
8008     POWERPC_DEF_SVR("MPC8349A",
8009                     CPU_POWERPC_MPC8349A,     POWERPC_SVR_8349A,     e300),
8010     /* MPC8349E                                                              */
8011     POWERPC_DEF_SVR("MPC8349E",
8012                     CPU_POWERPC_MPC8349E,     POWERPC_SVR_8349E,     e300),
8013     /* MPC8349EA                                                             */
8014     POWERPC_DEF_SVR("MPC8349EA",
8015                     CPU_POWERPC_MPC8349EA,    POWERPC_SVR_8349EA,    e300),
8016 #if defined (TODO)
8017     /* MPC8358E                                                              */
8018     POWERPC_DEF_SVR("MPC8358E",
8019                     CPU_POWERPC_MPC8358E,     POWERPC_SVR_8358E,     e300),
8020 #endif
8021 #if defined (TODO)
8022     /* MPC8360E                                                              */
8023     POWERPC_DEF_SVR("MPC8360E",
8024                     CPU_POWERPC_MPC8360E,     POWERPC_SVR_8360E,     e300),
8025 #endif
8026     /* MPC8377                                                               */
8027     POWERPC_DEF_SVR("MPC8377",
8028                     CPU_POWERPC_MPC8377,      POWERPC_SVR_8377,      e300),
8029     /* MPC8377E                                                              */
8030     POWERPC_DEF_SVR("MPC8377E",
8031                     CPU_POWERPC_MPC8377E,     POWERPC_SVR_8377E,     e300),
8032     /* MPC8378                                                               */
8033     POWERPC_DEF_SVR("MPC8378",
8034                     CPU_POWERPC_MPC8378,      POWERPC_SVR_8378,      e300),
8035     /* MPC8378E                                                              */
8036     POWERPC_DEF_SVR("MPC8378E",
8037                     CPU_POWERPC_MPC8378E,     POWERPC_SVR_8378E,     e300),
8038     /* MPC8379                                                               */
8039     POWERPC_DEF_SVR("MPC8379",
8040                     CPU_POWERPC_MPC8379,      POWERPC_SVR_8379,      e300),
8041     /* MPC8379E                                                              */
8042     POWERPC_DEF_SVR("MPC8379E",
8043                     CPU_POWERPC_MPC8379E,     POWERPC_SVR_8379E,     e300),
8044     /* e500 family                                                           */
8045     /* PowerPC e500 core                                                     */
8046     POWERPC_DEF("e500",          CPU_POWERPC_e500,                   e500),
8047     /* PowerPC e500 v1.0 core                                                */
8048     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500_v10,               e500),
8049     /* PowerPC e500 v2.0 core                                                */
8050     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500_v20,               e500),
8051     /* PowerPC e500v2 core                                                   */
8052     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500),
8053     /* PowerPC e500v2 v1.0 core                                              */
8054     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500),
8055     /* PowerPC e500v2 v2.0 core                                              */
8056     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500),
8057     /* PowerPC e500v2 v2.1 core                                              */
8058     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500),
8059     /* PowerPC e500v2 v2.2 core                                              */
8060     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500),
8061     /* PowerPC e500v2 v3.0 core                                              */
8062     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500),
8063     /* PowerPC e500 microcontrollers                                         */
8064     /* MPC8533                                                               */
8065     POWERPC_DEF_SVR("MPC8533",
8066                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500),
8067     /* MPC8533 v1.0                                                          */
8068     POWERPC_DEF_SVR("MPC8533_v10",
8069                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500),
8070     /* MPC8533 v1.1                                                          */
8071     POWERPC_DEF_SVR("MPC8533_v11",
8072                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500),
8073     /* MPC8533E                                                              */
8074     POWERPC_DEF_SVR("MPC8533E",
8075                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500),
8076     /* MPC8533E v1.0                                                         */
8077     POWERPC_DEF_SVR("MPC8533E_v10",
8078                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
8079     POWERPC_DEF_SVR("MPC8533E_v11",
8080                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
8081     /* MPC8540                                                               */
8082     POWERPC_DEF_SVR("MPC8540",
8083                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500),
8084     /* MPC8540 v1.0                                                          */
8085     POWERPC_DEF_SVR("MPC8540_v10",
8086                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500),
8087     /* MPC8540 v2.0                                                          */
8088     POWERPC_DEF_SVR("MPC8540_v20",
8089                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500),
8090     /* MPC8540 v2.1                                                          */
8091     POWERPC_DEF_SVR("MPC8540_v21",
8092                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500),
8093     /* MPC8541                                                               */
8094     POWERPC_DEF_SVR("MPC8541",
8095                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500),
8096     /* MPC8541 v1.0                                                          */
8097     POWERPC_DEF_SVR("MPC8541_v10",
8098                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500),
8099     /* MPC8541 v1.1                                                          */
8100     POWERPC_DEF_SVR("MPC8541_v11",
8101                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500),
8102     /* MPC8541E                                                              */
8103     POWERPC_DEF_SVR("MPC8541E",
8104                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500),
8105     /* MPC8541E v1.0                                                         */
8106     POWERPC_DEF_SVR("MPC8541E_v10",
8107                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
8108     /* MPC8541E v1.1                                                         */
8109     POWERPC_DEF_SVR("MPC8541E_v11",
8110                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
8111     /* MPC8543                                                               */
8112     POWERPC_DEF_SVR("MPC8543",
8113                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500),
8114     /* MPC8543 v1.0                                                          */
8115     POWERPC_DEF_SVR("MPC8543_v10",
8116                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500),
8117     /* MPC8543 v1.1                                                          */
8118     POWERPC_DEF_SVR("MPC8543_v11",
8119                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500),
8120     /* MPC8543 v2.0                                                          */
8121     POWERPC_DEF_SVR("MPC8543_v20",
8122                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500),
8123     /* MPC8543 v2.1                                                          */
8124     POWERPC_DEF_SVR("MPC8543_v21",
8125                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500),
8126     /* MPC8543E                                                              */
8127     POWERPC_DEF_SVR("MPC8543E",
8128                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500),
8129     /* MPC8543E v1.0                                                         */
8130     POWERPC_DEF_SVR("MPC8543E_v10",
8131                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
8132     /* MPC8543E v1.1                                                         */
8133     POWERPC_DEF_SVR("MPC8543E_v11",
8134                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
8135     /* MPC8543E v2.0                                                         */
8136     POWERPC_DEF_SVR("MPC8543E_v20",
8137                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
8138     /* MPC8543E v2.1                                                         */
8139     POWERPC_DEF_SVR("MPC8543E_v21",
8140                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
8141     /* MPC8544                                                               */
8142     POWERPC_DEF_SVR("MPC8544",
8143                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500),
8144     /* MPC8544 v1.0                                                          */
8145     POWERPC_DEF_SVR("MPC8544_v10",
8146                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500),
8147     /* MPC8544 v1.1                                                          */
8148     POWERPC_DEF_SVR("MPC8544_v11",
8149                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500),
8150     /* MPC8544E                                                              */
8151     POWERPC_DEF_SVR("MPC8544E",
8152                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500),
8153     /* MPC8544E v1.0                                                         */
8154     POWERPC_DEF_SVR("MPC8544E_v10",
8155                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
8156     /* MPC8544E v1.1                                                         */
8157     POWERPC_DEF_SVR("MPC8544E_v11",
8158                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
8159     /* MPC8545                                                               */
8160     POWERPC_DEF_SVR("MPC8545",
8161                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500),
8162     /* MPC8545 v2.0                                                          */
8163     POWERPC_DEF_SVR("MPC8545_v20",
8164                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500),
8165     /* MPC8545 v2.1                                                          */
8166     POWERPC_DEF_SVR("MPC8545_v21",
8167                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500),
8168     /* MPC8545E                                                              */
8169     POWERPC_DEF_SVR("MPC8545E",
8170                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500),
8171     /* MPC8545E v2.0                                                         */
8172     POWERPC_DEF_SVR("MPC8545E_v20",
8173                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
8174     /* MPC8545E v2.1                                                         */
8175     POWERPC_DEF_SVR("MPC8545E_v21",
8176                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
8177     /* MPC8547E                                                              */
8178     POWERPC_DEF_SVR("MPC8547E",
8179                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500),
8180     /* MPC8547E v2.0                                                         */
8181     POWERPC_DEF_SVR("MPC8547E_v20",
8182                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
8183     /* MPC8547E v2.1                                                         */
8184     POWERPC_DEF_SVR("MPC8547E_v21",
8185                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
8186     /* MPC8548                                                               */
8187     POWERPC_DEF_SVR("MPC8548",
8188                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500),
8189     /* MPC8548 v1.0                                                          */
8190     POWERPC_DEF_SVR("MPC8548_v10",
8191                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500),
8192     /* MPC8548 v1.1                                                          */
8193     POWERPC_DEF_SVR("MPC8548_v11",
8194                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500),
8195     /* MPC8548 v2.0                                                          */
8196     POWERPC_DEF_SVR("MPC8548_v20",
8197                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500),
8198     /* MPC8548 v2.1                                                          */
8199     POWERPC_DEF_SVR("MPC8548_v21",
8200                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500),
8201     /* MPC8548E                                                              */
8202     POWERPC_DEF_SVR("MPC8548E",
8203                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500),
8204     /* MPC8548E v1.0                                                         */
8205     POWERPC_DEF_SVR("MPC8548E_v10",
8206                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
8207     /* MPC8548E v1.1                                                         */
8208     POWERPC_DEF_SVR("MPC8548E_v11",
8209                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
8210     /* MPC8548E v2.0                                                         */
8211     POWERPC_DEF_SVR("MPC8548E_v20",
8212                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
8213     /* MPC8548E v2.1                                                         */
8214     POWERPC_DEF_SVR("MPC8548E_v21",
8215                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
8216     /* MPC8555                                                               */
8217     POWERPC_DEF_SVR("MPC8555",
8218                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500),
8219     /* MPC8555 v1.0                                                          */
8220     POWERPC_DEF_SVR("MPC8555_v10",
8221                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500),
8222     /* MPC8555 v1.1                                                          */
8223     POWERPC_DEF_SVR("MPC8555_v11",
8224                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500),
8225     /* MPC8555E                                                              */
8226     POWERPC_DEF_SVR("MPC8555E",
8227                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500),
8228     /* MPC8555E v1.0                                                         */
8229     POWERPC_DEF_SVR("MPC8555E_v10",
8230                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
8231     /* MPC8555E v1.1                                                         */
8232     POWERPC_DEF_SVR("MPC8555E_v11",
8233                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
8234     /* MPC8560                                                               */
8235     POWERPC_DEF_SVR("MPC8560",
8236                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500),
8237     /* MPC8560 v1.0                                                          */
8238     POWERPC_DEF_SVR("MPC8560_v10",
8239                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500),
8240     /* MPC8560 v2.0                                                          */
8241     POWERPC_DEF_SVR("MPC8560_v20",
8242                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500),
8243     /* MPC8560 v2.1                                                          */
8244     POWERPC_DEF_SVR("MPC8560_v21",
8245                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500),
8246     /* MPC8567                                                               */
8247     POWERPC_DEF_SVR("MPC8567",
8248                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500),
8249     /* MPC8567E                                                              */
8250     POWERPC_DEF_SVR("MPC8567E",
8251                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500),
8252     /* MPC8568                                                               */
8253     POWERPC_DEF_SVR("MPC8568",
8254                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500),
8255     /* MPC8568E                                                              */
8256     POWERPC_DEF_SVR("MPC8568E",
8257                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500),
8258     /* MPC8572                                                               */
8259     POWERPC_DEF_SVR("MPC8572",
8260                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500),
8261     /* MPC8572E                                                              */
8262     POWERPC_DEF_SVR("MPC8572E",
8263                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500),
8264     /* e600 family                                                           */
8265     /* PowerPC e600 core                                                     */
8266     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
8267     /* PowerPC e600 microcontrollers                                         */
8268 #if defined (TODO)
8269     /* MPC8610                                                               */
8270     POWERPC_DEF_SVR("MPC8610",
8271                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
8272 #endif
8273     /* MPC8641                                                               */
8274     POWERPC_DEF_SVR("MPC8641",
8275                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
8276     /* MPC8641D                                                              */
8277     POWERPC_DEF_SVR("MPC8641D",
8278                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
8279     /* 32 bits "classic" PowerPC                                             */
8280     /* PowerPC 6xx family                                                    */
8281     /* PowerPC 601                                                           */
8282     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
8283     /* PowerPC 601v0                                                         */
8284     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
8285     /* PowerPC 601v1                                                         */
8286     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
8287     /* PowerPC 601v                                                          */
8288     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
8289     /* PowerPC 601v2                                                         */
8290     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
8291     /* PowerPC 602                                                           */
8292     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
8293     /* PowerPC 603                                                           */
8294     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
8295     /* Code name for PowerPC 603                                             */
8296     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
8297     /* PowerPC 603e (aka PID6)                                               */
8298     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
8299     /* Code name for PowerPC 603e                                            */
8300     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
8301     /* PowerPC 603e v1.1                                                     */
8302     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
8303     /* PowerPC 603e v1.2                                                     */
8304     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
8305     /* PowerPC 603e v1.3                                                     */
8306     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
8307     /* PowerPC 603e v1.4                                                     */
8308     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
8309     /* PowerPC 603e v2.2                                                     */
8310     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
8311     /* PowerPC 603e v3                                                       */
8312     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
8313     /* PowerPC 603e v4                                                       */
8314     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
8315     /* PowerPC 603e v4.1                                                     */
8316     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
8317     /* PowerPC 603e (aka PID7)                                               */
8318     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
8319     /* PowerPC 603e7t                                                        */
8320     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
8321     /* PowerPC 603e7v                                                        */
8322     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
8323     /* Code name for PowerPC 603ev                                           */
8324     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
8325     /* PowerPC 603e7v1                                                       */
8326     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
8327     /* PowerPC 603e7v2                                                       */
8328     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
8329     /* PowerPC 603p (aka PID7v)                                              */
8330     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
8331     /* PowerPC 603r (aka PID7t)                                              */
8332     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
8333     /* Code name for PowerPC 603r                                            */
8334     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
8335     /* PowerPC 604                                                           */
8336     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
8337     /* PowerPC 604e (aka PID9)                                               */
8338     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
8339     /* Code name for PowerPC 604e                                            */
8340     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
8341     /* PowerPC 604e v1.0                                                     */
8342     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
8343     /* PowerPC 604e v2.2                                                     */
8344     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
8345     /* PowerPC 604e v2.4                                                     */
8346     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
8347     /* PowerPC 604r (aka PIDA)                                               */
8348     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
8349     /* Code name for PowerPC 604r                                            */
8350     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
8351 #if defined(TODO)
8352     /* PowerPC 604ev                                                         */
8353     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
8354 #endif
8355     /* PowerPC 7xx family                                                    */
8356     /* Generic PowerPC 740 (G3)                                              */
8357     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
8358     /* Code name for PowerPC 740                                             */
8359     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
8360     /* Generic PowerPC 750 (G3)                                              */
8361     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
8362     /* Code name for PowerPC 750                                             */
8363     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
8364     /* PowerPC 740/750 is also known as G3                                   */
8365     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
8366     /* PowerPC 740 v1.0 (G3)                                                 */
8367     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
8368     /* PowerPC 750 v1.0 (G3)                                                 */
8369     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
8370     /* PowerPC 740 v2.0 (G3)                                                 */
8371     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
8372     /* PowerPC 750 v2.0 (G3)                                                 */
8373     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
8374     /* PowerPC 740 v2.1 (G3)                                                 */
8375     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
8376     /* PowerPC 750 v2.1 (G3)                                                 */
8377     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
8378     /* PowerPC 740 v2.2 (G3)                                                 */
8379     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
8380     /* PowerPC 750 v2.2 (G3)                                                 */
8381     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
8382     /* PowerPC 740 v3.0 (G3)                                                 */
8383     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
8384     /* PowerPC 750 v3.0 (G3)                                                 */
8385     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
8386     /* PowerPC 740 v3.1 (G3)                                                 */
8387     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
8388     /* PowerPC 750 v3.1 (G3)                                                 */
8389     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
8390     /* PowerPC 740E (G3)                                                     */
8391     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
8392     /* PowerPC 750E (G3)                                                     */
8393     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
8394     /* PowerPC 740P (G3)                                                     */
8395     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
8396     /* PowerPC 750P (G3)                                                     */
8397     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
8398     /* Code name for PowerPC 740P/750P (G3)                                  */
8399     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
8400     /* PowerPC 750CL (G3 embedded)                                           */
8401     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
8402     /* PowerPC 750CL v1.0                                                    */
8403     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
8404     /* PowerPC 750CL v2.0                                                    */
8405     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
8406     /* PowerPC 750CX (G3 embedded)                                           */
8407     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
8408     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
8409     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
8410     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8411     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
8412     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8413     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
8414     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
8415     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
8416     /* PowerPC 750CXe (G3 embedded)                                          */
8417     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
8418     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
8419     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
8420     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
8421     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
8422     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
8423     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
8424     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
8425     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
8426     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
8427     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
8428     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
8429     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
8430     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
8431     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
8432     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
8433     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
8434     /* PowerPC 750CXr (G3 embedded)                                          */
8435     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
8436     /* PowerPC 750FL (G3 embedded)                                           */
8437     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
8438     /* PowerPC 750FX (G3 embedded)                                           */
8439     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
8440     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
8441     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
8442     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
8443     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
8444     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
8445     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
8446     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
8447     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
8448     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
8449     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
8450     /* PowerPC 750GL (G3 embedded)                                           */
8451     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
8452     /* PowerPC 750GX (G3 embedded)                                           */
8453     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
8454     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
8455     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
8456     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
8457     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
8458     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
8459     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
8460     /* PowerPC 750L (G3 embedded)                                            */
8461     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
8462     /* Code name for PowerPC 750L (G3 embedded)                              */
8463     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
8464     /* PowerPC 750L v2.0 (G3 embedded)                                       */
8465     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
8466     /* PowerPC 750L v2.1 (G3 embedded)                                       */
8467     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
8468     /* PowerPC 750L v2.2 (G3 embedded)                                       */
8469     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
8470     /* PowerPC 750L v3.0 (G3 embedded)                                       */
8471     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
8472     /* PowerPC 750L v3.2 (G3 embedded)                                       */
8473     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
8474     /* Generic PowerPC 745                                                   */
8475     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
8476     /* Generic PowerPC 755                                                   */
8477     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
8478     /* Code name for PowerPC 745/755                                         */
8479     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
8480     /* PowerPC 745 v1.0                                                      */
8481     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
8482     /* PowerPC 755 v1.0                                                      */
8483     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
8484     /* PowerPC 745 v1.1                                                      */
8485     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
8486     /* PowerPC 755 v1.1                                                      */
8487     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
8488     /* PowerPC 745 v2.0                                                      */
8489     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
8490     /* PowerPC 755 v2.0                                                      */
8491     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
8492     /* PowerPC 745 v2.1                                                      */
8493     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
8494     /* PowerPC 755 v2.1                                                      */
8495     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
8496     /* PowerPC 745 v2.2                                                      */
8497     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
8498     /* PowerPC 755 v2.2                                                      */
8499     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
8500     /* PowerPC 745 v2.3                                                      */
8501     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
8502     /* PowerPC 755 v2.3                                                      */
8503     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
8504     /* PowerPC 745 v2.4                                                      */
8505     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
8506     /* PowerPC 755 v2.4                                                      */
8507     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
8508     /* PowerPC 745 v2.5                                                      */
8509     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
8510     /* PowerPC 755 v2.5                                                      */
8511     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
8512     /* PowerPC 745 v2.6                                                      */
8513     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
8514     /* PowerPC 755 v2.6                                                      */
8515     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
8516     /* PowerPC 745 v2.7                                                      */
8517     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
8518     /* PowerPC 755 v2.7                                                      */
8519     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
8520     /* PowerPC 745 v2.8                                                      */
8521     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
8522     /* PowerPC 755 v2.8                                                      */
8523     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
8524 #if defined (TODO)
8525     /* PowerPC 745P (G3)                                                     */
8526     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
8527     /* PowerPC 755P (G3)                                                     */
8528     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
8529 #endif
8530     /* PowerPC 74xx family                                                   */
8531     /* PowerPC 7400 (G4)                                                     */
8532     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
8533     /* Code name for PowerPC 7400                                            */
8534     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
8535     /* PowerPC 74xx is also well known as G4                                 */
8536     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
8537     /* PowerPC 7400 v1.0 (G4)                                                */
8538     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
8539     /* PowerPC 7400 v1.1 (G4)                                                */
8540     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
8541     /* PowerPC 7400 v2.0 (G4)                                                */
8542     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
8543     /* PowerPC 7400 v2.1 (G4)                                                */
8544     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
8545     /* PowerPC 7400 v2.2 (G4)                                                */
8546     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
8547     /* PowerPC 7400 v2.6 (G4)                                                */
8548     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
8549     /* PowerPC 7400 v2.7 (G4)                                                */
8550     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
8551     /* PowerPC 7400 v2.8 (G4)                                                */
8552     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
8553     /* PowerPC 7400 v2.9 (G4)                                                */
8554     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
8555     /* PowerPC 7410 (G4)                                                     */
8556     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
8557     /* Code name for PowerPC 7410                                            */
8558     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
8559     /* PowerPC 7410 v1.0 (G4)                                                */
8560     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
8561     /* PowerPC 7410 v1.1 (G4)                                                */
8562     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
8563     /* PowerPC 7410 v1.2 (G4)                                                */
8564     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
8565     /* PowerPC 7410 v1.3 (G4)                                                */
8566     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
8567     /* PowerPC 7410 v1.4 (G4)                                                */
8568     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
8569     /* PowerPC 7448 (G4)                                                     */
8570     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
8571     /* PowerPC 7448 v1.0 (G4)                                                */
8572     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
8573     /* PowerPC 7448 v1.1 (G4)                                                */
8574     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
8575     /* PowerPC 7448 v2.0 (G4)                                                */
8576     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
8577     /* PowerPC 7448 v2.1 (G4)                                                */
8578     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
8579     /* PowerPC 7450 (G4)                                                     */
8580     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
8581     /* Code name for PowerPC 7450                                            */
8582     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
8583     /* PowerPC 7450 v1.0 (G4)                                                */
8584     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
8585     /* PowerPC 7450 v1.1 (G4)                                                */
8586     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
8587     /* PowerPC 7450 v1.2 (G4)                                                */
8588     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
8589     /* PowerPC 7450 v2.0 (G4)                                                */
8590     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
8591     /* PowerPC 7450 v2.1 (G4)                                                */
8592     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
8593     /* PowerPC 7441 (G4)                                                     */
8594     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
8595     /* PowerPC 7451 (G4)                                                     */
8596     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
8597     /* PowerPC 7441 v2.1 (G4)                                                */
8598     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
8599     /* PowerPC 7441 v2.3 (G4)                                                */
8600     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
8601     /* PowerPC 7451 v2.3 (G4)                                                */
8602     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
8603     /* PowerPC 7441 v2.10 (G4)                                                */
8604     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
8605     /* PowerPC 7451 v2.10 (G4)                                               */
8606     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
8607     /* PowerPC 7445 (G4)                                                     */
8608     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
8609     /* PowerPC 7455 (G4)                                                     */
8610     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
8611     /* Code name for PowerPC 7445/7455                                       */
8612     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
8613     /* PowerPC 7445 v1.0 (G4)                                                */
8614     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
8615     /* PowerPC 7455 v1.0 (G4)                                                */
8616     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
8617     /* PowerPC 7445 v2.1 (G4)                                                */
8618     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
8619     /* PowerPC 7455 v2.1 (G4)                                                */
8620     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
8621     /* PowerPC 7445 v3.2 (G4)                                                */
8622     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
8623     /* PowerPC 7455 v3.2 (G4)                                                */
8624     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
8625     /* PowerPC 7445 v3.3 (G4)                                                */
8626     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
8627     /* PowerPC 7455 v3.3 (G4)                                                */
8628     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
8629     /* PowerPC 7445 v3.4 (G4)                                                */
8630     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
8631     /* PowerPC 7455 v3.4 (G4)                                                */
8632     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
8633     /* PowerPC 7447 (G4)                                                     */
8634     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
8635     /* PowerPC 7457 (G4)                                                     */
8636     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
8637     /* Code name for PowerPC 7447/7457                                       */
8638     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
8639     /* PowerPC 7447 v1.0 (G4)                                                */
8640     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
8641     /* PowerPC 7457 v1.0 (G4)                                                */
8642     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
8643     /* PowerPC 7447 v1.1 (G4)                                                */
8644     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
8645     /* PowerPC 7457 v1.1 (G4)                                                */
8646     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
8647     /* PowerPC 7457 v1.2 (G4)                                                */
8648     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
8649     /* PowerPC 7447A (G4)                                                    */
8650     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
8651     /* PowerPC 7457A (G4)                                                    */
8652     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
8653     /* PowerPC 7447A v1.0 (G4)                                               */
8654     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
8655     /* PowerPC 7457A v1.0 (G4)                                               */
8656     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
8657     /* Code name for PowerPC 7447A/7457A                                     */
8658     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
8659     /* PowerPC 7447A v1.1 (G4)                                               */
8660     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
8661     /* PowerPC 7457A v1.1 (G4)                                               */
8662     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
8663     /* PowerPC 7447A v1.2 (G4)                                               */
8664     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
8665     /* PowerPC 7457A v1.2 (G4)                                               */
8666     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
8667     /* 64 bits PowerPC                                                       */
8668 #if defined (TARGET_PPC64)
8669     /* PowerPC 620                                                           */
8670     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
8671     /* Code name for PowerPC 620                                             */
8672     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
8673 #if defined (TODO)
8674     /* PowerPC 630 (POWER3)                                                  */
8675     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
8676     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
8677     /* Code names for POWER3                                                 */
8678     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
8679     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
8680 #endif
8681 #if defined (TODO)
8682     /* PowerPC 631 (Power 3+)                                                */
8683     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
8684     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
8685 #endif
8686 #if defined (TODO)
8687     /* POWER4                                                                */
8688     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
8689 #endif
8690 #if defined (TODO)
8691     /* POWER4p                                                               */
8692     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
8693 #endif
8694 #if defined (TODO)
8695     /* POWER5                                                                */
8696     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
8697     /* POWER5GR                                                              */
8698     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
8699 #endif
8700 #if defined (TODO)
8701     /* POWER5+                                                               */
8702     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
8703     /* POWER5GS                                                              */
8704     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
8705 #endif
8706 #if defined (TODO)
8707     /* POWER6                                                                */
8708     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
8709     /* POWER6 running in POWER5 mode                                         */
8710     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
8711     /* POWER6A                                                               */
8712     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
8713 #endif
8714     /* PowerPC 970                                                           */
8715     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
8716     /* PowerPC 970FX (G5)                                                    */
8717     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
8718     /* PowerPC 970FX v1.0 (G5)                                               */
8719     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
8720     /* PowerPC 970FX v2.0 (G5)                                               */
8721     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
8722     /* PowerPC 970FX v2.1 (G5)                                               */
8723     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
8724     /* PowerPC 970FX v3.0 (G5)                                               */
8725     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
8726     /* PowerPC 970FX v3.1 (G5)                                               */
8727     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
8728     /* PowerPC 970GX (G5)                                                    */
8729     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
8730     /* PowerPC 970MP                                                         */
8731     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
8732     /* PowerPC 970MP v1.0                                                    */
8733     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
8734     /* PowerPC 970MP v1.1                                                    */
8735     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
8736 #if defined (TODO)
8737     /* PowerPC Cell                                                          */
8738     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
8739 #endif
8740 #if defined (TODO)
8741     /* PowerPC Cell v1.0                                                     */
8742     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
8743 #endif
8744 #if defined (TODO)
8745     /* PowerPC Cell v2.0                                                     */
8746     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
8747 #endif
8748 #if defined (TODO)
8749     /* PowerPC Cell v3.0                                                     */
8750     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
8751 #endif
8752 #if defined (TODO)
8753     /* PowerPC Cell v3.1                                                     */
8754     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
8755 #endif
8756 #if defined (TODO)
8757     /* PowerPC Cell v3.2                                                     */
8758     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
8759 #endif
8760 #if defined (TODO)
8761     /* RS64 (Apache/A35)                                                     */
8762     /* This one seems to support the whole POWER2 instruction set
8763      * and the PowerPC 64 one.
8764      */
8765     /* What about A10 & A30 ? */
8766     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
8767     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
8768     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
8769 #endif
8770 #if defined (TODO)
8771     /* RS64-II (NorthStar/A50)                                               */
8772     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
8773     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
8774     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
8775 #endif
8776 #if defined (TODO)
8777     /* RS64-III (Pulsar)                                                     */
8778     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
8779     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
8780 #endif
8781 #if defined (TODO)
8782     /* RS64-IV (IceStar/IStar/SStar)                                         */
8783     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
8784     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
8785     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
8786     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
8787 #endif
8788 #endif /* defined (TARGET_PPC64) */
8789     /* POWER                                                                 */
8790 #if defined (TODO)
8791     /* Original POWER                                                        */
8792     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
8793     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
8794     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
8795     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
8796     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
8797 #endif
8798 #if defined (TODO)
8799     /* POWER2                                                                */
8800     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
8801     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
8802     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
8803 #endif
8804     /* PA semi cores                                                         */
8805 #if defined (TODO)
8806     /* PA PA6T */
8807     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
8808 #endif
8809     /* Generic PowerPCs                                                      */
8810 #if defined (TARGET_PPC64)
8811     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
8812 #endif
8813     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
8814     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
8815     /* Fallback                                                              */
8816     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
8817 };
8818
8819 /*****************************************************************************/
8820 /* Generic CPU instanciation routine                                         */
8821 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8822 {
8823 #if !defined(CONFIG_USER_ONLY)
8824     int i;
8825
8826     env->irq_inputs = NULL;
8827     /* Set all exception vectors to an invalid address */
8828     for (i = 0; i < POWERPC_EXCP_NB; i++)
8829         env->excp_vectors[i] = (target_ulong)(-1ULL);
8830     env->excp_prefix = 0x00000000;
8831     env->ivor_mask = 0x00000000;
8832     env->ivpr_mask = 0x00000000;
8833     /* Default MMU definitions */
8834     env->nb_BATs = 0;
8835     env->nb_tlb = 0;
8836     env->nb_ways = 0;
8837 #endif
8838     /* Register SPR common to all PowerPC implementations */
8839     gen_spr_generic(env);
8840     spr_register(env, SPR_PVR, "PVR",
8841                  SPR_NOACCESS, SPR_NOACCESS,
8842                  &spr_read_generic, SPR_NOACCESS,
8843                  def->pvr);
8844     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8845     if (def->svr != POWERPC_SVR_NONE) {
8846         if (def->svr & POWERPC_SVR_E500) {
8847             spr_register(env, SPR_E500_SVR, "SVR",
8848                          SPR_NOACCESS, SPR_NOACCESS,
8849                          &spr_read_generic, SPR_NOACCESS,
8850                          def->svr & ~POWERPC_SVR_E500);
8851         } else {
8852             spr_register(env, SPR_SVR, "SVR",
8853                          SPR_NOACCESS, SPR_NOACCESS,
8854                          &spr_read_generic, SPR_NOACCESS,
8855                          def->svr);
8856         }
8857     }
8858     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8859     (*def->init_proc)(env);
8860     /* MSR bits & flags consistency checks */
8861     if (env->msr_mask & (1 << 25)) {
8862         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8863         case POWERPC_FLAG_SPE:
8864         case POWERPC_FLAG_VRE:
8865             break;
8866         default:
8867             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8868                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8869             exit(1);
8870         }
8871     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8872         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8873                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8874         exit(1);
8875     }
8876     if (env->msr_mask & (1 << 17)) {
8877         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8878         case POWERPC_FLAG_TGPR:
8879         case POWERPC_FLAG_CE:
8880             break;
8881         default:
8882             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8883                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8884             exit(1);
8885         }
8886     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8887         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8888                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8889         exit(1);
8890     }
8891     if (env->msr_mask & (1 << 10)) {
8892         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8893                               POWERPC_FLAG_UBLE)) {
8894         case POWERPC_FLAG_SE:
8895         case POWERPC_FLAG_DWE:
8896         case POWERPC_FLAG_UBLE:
8897             break;
8898         default:
8899             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8900                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8901                     "POWERPC_FLAG_UBLE\n");
8902             exit(1);
8903         }
8904     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8905                              POWERPC_FLAG_UBLE)) {
8906         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8907                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8908                 "POWERPC_FLAG_UBLE\n");
8909             exit(1);
8910     }
8911     if (env->msr_mask & (1 << 9)) {
8912         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8913         case POWERPC_FLAG_BE:
8914         case POWERPC_FLAG_DE:
8915             break;
8916         default:
8917             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8918                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8919             exit(1);
8920         }
8921     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8922         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8923                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8924         exit(1);
8925     }
8926     if (env->msr_mask & (1 << 2)) {
8927         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8928         case POWERPC_FLAG_PX:
8929         case POWERPC_FLAG_PMM:
8930             break;
8931         default:
8932             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8933                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8934             exit(1);
8935         }
8936     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8937         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8938                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8939         exit(1);
8940     }
8941     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8942         fprintf(stderr, "PowerPC flags inconsistency\n"
8943                 "Should define the time-base and decrementer clock source\n");
8944         exit(1);
8945     }
8946     /* Allocate TLBs buffer when needed */
8947 #if !defined(CONFIG_USER_ONLY)
8948     if (env->nb_tlb != 0) {
8949         int nb_tlb = env->nb_tlb;
8950         if (env->id_tlbs != 0)
8951             nb_tlb *= 2;
8952         env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8953         /* Pre-compute some useful values */
8954         env->tlb_per_way = env->nb_tlb / env->nb_ways;
8955     }
8956     if (env->irq_inputs == NULL) {
8957         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8958                 " Attempt Qemu to crash very soon !\n");
8959     }
8960 #endif
8961     if (env->check_pow == NULL) {
8962         fprintf(stderr, "WARNING: no power management check handler "
8963                 "registered.\n"
8964                 " Attempt Qemu to crash very soon !\n");
8965     }
8966 }
8967
8968 #if defined(PPC_DUMP_CPU)
8969 static void dump_ppc_sprs (CPUPPCState *env)
8970 {
8971     ppc_spr_t *spr;
8972 #if !defined(CONFIG_USER_ONLY)
8973     uint32_t sr, sw;
8974 #endif
8975     uint32_t ur, uw;
8976     int i, j, n;
8977
8978     printf("Special purpose registers:\n");
8979     for (i = 0; i < 32; i++) {
8980         for (j = 0; j < 32; j++) {
8981             n = (i << 5) | j;
8982             spr = &env->spr_cb[n];
8983             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8984             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8985 #if !defined(CONFIG_USER_ONLY)
8986             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8987             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8988             if (sw || sr || uw || ur) {
8989                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8990                        (i << 5) | j, (i << 5) | j, spr->name,
8991                        sw ? 'w' : '-', sr ? 'r' : '-',
8992                        uw ? 'w' : '-', ur ? 'r' : '-');
8993             }
8994 #else
8995             if (uw || ur) {
8996                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8997                        (i << 5) | j, (i << 5) | j, spr->name,
8998                        uw ? 'w' : '-', ur ? 'r' : '-');
8999             }
9000 #endif
9001         }
9002     }
9003     fflush(stdout);
9004     fflush(stderr);
9005 }
9006 #endif
9007
9008 /*****************************************************************************/
9009 #include <stdlib.h>
9010 #include <string.h>
9011
9012 /* Opcode types */
9013 enum {
9014     PPC_DIRECT   = 0, /* Opcode routine        */
9015     PPC_INDIRECT = 1, /* Indirect opcode table */
9016 };
9017
9018 static inline int is_indirect_opcode (void *handler)
9019 {
9020     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9021 }
9022
9023 static inline opc_handler_t **ind_table(void *handler)
9024 {
9025     return (opc_handler_t **)((unsigned long)handler & ~3);
9026 }
9027
9028 /* Instruction table creation */
9029 /* Opcodes tables creation */
9030 static void fill_new_table (opc_handler_t **table, int len)
9031 {
9032     int i;
9033
9034     for (i = 0; i < len; i++)
9035         table[i] = &invalid_handler;
9036 }
9037
9038 static int create_new_table (opc_handler_t **table, unsigned char idx)
9039 {
9040     opc_handler_t **tmp;
9041
9042     tmp = malloc(0x20 * sizeof(opc_handler_t));
9043     fill_new_table(tmp, 0x20);
9044     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9045
9046     return 0;
9047 }
9048
9049 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9050                             opc_handler_t *handler)
9051 {
9052     if (table[idx] != &invalid_handler)
9053         return -1;
9054     table[idx] = handler;
9055
9056     return 0;
9057 }
9058
9059 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9060                                  unsigned char idx, opc_handler_t *handler)
9061 {
9062     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9063         printf("*** ERROR: opcode %02x already assigned in main "
9064                "opcode table\n", idx);
9065 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9066         printf("           Registered handler '%s' - new handler '%s'\n",
9067                ppc_opcodes[idx]->oname, handler->oname);
9068 #endif
9069         return -1;
9070     }
9071
9072     return 0;
9073 }
9074
9075 static int register_ind_in_table (opc_handler_t **table,
9076                                   unsigned char idx1, unsigned char idx2,
9077                                   opc_handler_t *handler)
9078 {
9079     if (table[idx1] == &invalid_handler) {
9080         if (create_new_table(table, idx1) < 0) {
9081             printf("*** ERROR: unable to create indirect table "
9082                    "idx=%02x\n", idx1);
9083             return -1;
9084         }
9085     } else {
9086         if (!is_indirect_opcode(table[idx1])) {
9087             printf("*** ERROR: idx %02x already assigned to a direct "
9088                    "opcode\n", idx1);
9089 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9090             printf("           Registered handler '%s' - new handler '%s'\n",
9091                    ind_table(table[idx1])[idx2]->oname, handler->oname);
9092 #endif
9093             return -1;
9094         }
9095     }
9096     if (handler != NULL &&
9097         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9098         printf("*** ERROR: opcode %02x already assigned in "
9099                "opcode table %02x\n", idx2, idx1);
9100 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9101         printf("           Registered handler '%s' - new handler '%s'\n",
9102                ind_table(table[idx1])[idx2]->oname, handler->oname);
9103 #endif
9104         return -1;
9105     }
9106
9107     return 0;
9108 }
9109
9110 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9111                               unsigned char idx1, unsigned char idx2,
9112                               opc_handler_t *handler)
9113 {
9114     int ret;
9115
9116     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9117
9118     return ret;
9119 }
9120
9121 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9122                                  unsigned char idx1, unsigned char idx2,
9123                                  unsigned char idx3, opc_handler_t *handler)
9124 {
9125     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9126         printf("*** ERROR: unable to join indirect table idx "
9127                "[%02x-%02x]\n", idx1, idx2);
9128         return -1;
9129     }
9130     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9131                               handler) < 0) {
9132         printf("*** ERROR: unable to insert opcode "
9133                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9134         return -1;
9135     }
9136
9137     return 0;
9138 }
9139
9140 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9141 {
9142     if (insn->opc2 != 0xFF) {
9143         if (insn->opc3 != 0xFF) {
9144             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9145                                      insn->opc3, &insn->handler) < 0)
9146                 return -1;
9147         } else {
9148             if (register_ind_insn(ppc_opcodes, insn->opc1,
9149                                   insn->opc2, &insn->handler) < 0)
9150                 return -1;
9151         }
9152     } else {
9153         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9154             return -1;
9155     }
9156
9157     return 0;
9158 }
9159
9160 static int test_opcode_table (opc_handler_t **table, int len)
9161 {
9162     int i, count, tmp;
9163
9164     for (i = 0, count = 0; i < len; i++) {
9165         /* Consistency fixup */
9166         if (table[i] == NULL)
9167             table[i] = &invalid_handler;
9168         if (table[i] != &invalid_handler) {
9169             if (is_indirect_opcode(table[i])) {
9170                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9171                 if (tmp == 0) {
9172                     free(table[i]);
9173                     table[i] = &invalid_handler;
9174                 } else {
9175                     count++;
9176                 }
9177             } else {
9178                 count++;
9179             }
9180         }
9181     }
9182
9183     return count;
9184 }
9185
9186 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9187 {
9188     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9189         printf("*** WARNING: no opcode defined !\n");
9190 }
9191
9192 /*****************************************************************************/
9193 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9194 {
9195     opcode_t *opc, *start, *end;
9196
9197     fill_new_table(env->opcodes, 0x40);
9198     if (&opc_start < &opc_end) {
9199         start = &opc_start;
9200         end = &opc_end;
9201     } else {
9202         start = &opc_end;
9203         end = &opc_start;
9204     }
9205     for (opc = start + 1; opc != end; opc++) {
9206         if ((opc->handler.type & def->insns_flags) != 0) {
9207             if (register_insn(env->opcodes, opc) < 0) {
9208                 printf("*** ERROR initializing PowerPC instruction "
9209                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9210                        opc->opc3);
9211                 return -1;
9212             }
9213         }
9214     }
9215     fix_opcode_tables(env->opcodes);
9216     fflush(stdout);
9217     fflush(stderr);
9218
9219     return 0;
9220 }
9221
9222 #if defined(PPC_DUMP_CPU)
9223 static void dump_ppc_insns (CPUPPCState *env)
9224 {
9225     opc_handler_t **table, *handler;
9226     const char *p, *q;
9227     uint8_t opc1, opc2, opc3;
9228
9229     printf("Instructions set:\n");
9230     /* opc1 is 6 bits long */
9231     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9232         table = env->opcodes;
9233         handler = table[opc1];
9234         if (is_indirect_opcode(handler)) {
9235             /* opc2 is 5 bits long */
9236             for (opc2 = 0; opc2 < 0x20; opc2++) {
9237                 table = env->opcodes;
9238                 handler = env->opcodes[opc1];
9239                 table = ind_table(handler);
9240                 handler = table[opc2];
9241                 if (is_indirect_opcode(handler)) {
9242                     table = ind_table(handler);
9243                     /* opc3 is 5 bits long */
9244                     for (opc3 = 0; opc3 < 0x20; opc3++) {
9245                         handler = table[opc3];
9246                         if (handler->handler != &gen_invalid) {
9247                             /* Special hack to properly dump SPE insns */
9248                             p = strchr(handler->oname, '_');
9249                             if (p == NULL) {
9250                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
9251                                        "%s\n",
9252                                        opc1, opc2, opc3, opc1,
9253                                        (opc3 << 5) | opc2,
9254                                        handler->oname);
9255                             } else {
9256                                 q = "speundef";
9257                                 if ((p - handler->oname) != strlen(q) ||
9258                                     memcmp(handler->oname, q, strlen(q)) != 0) {
9259                                     /* First instruction */
9260                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9261                                            "%.*s\n",
9262                                            opc1, opc2 << 1, opc3, opc1,
9263                                            (opc3 << 6) | (opc2 << 1),
9264                                            (int)(p - handler->oname),
9265                                            handler->oname);
9266                                 }
9267                                 if (strcmp(p + 1, q) != 0) {
9268                                     /* Second instruction */
9269                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9270                                            "%s\n",
9271                                            opc1, (opc2 << 1) | 1, opc3, opc1,
9272                                            (opc3 << 6) | (opc2 << 1) | 1,
9273                                            p + 1);
9274                                 }
9275                             }
9276                         }
9277                     }
9278                 } else {
9279                     if (handler->handler != &gen_invalid) {
9280                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9281                                opc1, opc2, opc1, opc2, handler->oname);
9282                     }
9283                 }
9284             }
9285         } else {
9286             if (handler->handler != &gen_invalid) {
9287                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9288                        opc1, opc1, handler->oname);
9289             }
9290         }
9291     }
9292 }
9293 #endif
9294
9295 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9296 {
9297     if (n < 32) {
9298         stfq_p(mem_buf, env->fpr[n]);
9299         return 8;
9300     }
9301     if (n == 32) {
9302         /* FPSCR not implemented  */
9303         memset(mem_buf, 0, 4);
9304         return 4;
9305     }
9306     return 0;
9307 }
9308
9309 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9310 {
9311     if (n < 32) {
9312         env->fpr[n] = ldfq_p(mem_buf);
9313         return 8;
9314     }
9315     if (n == 32) {
9316         /* FPSCR not implemented  */
9317         return 4;
9318     }
9319     return 0;
9320 }
9321
9322 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9323 {
9324     if (n < 32) {
9325 #ifdef WORDS_BIGENDIAN
9326         stq_p(mem_buf, env->avr[n].u64[0]);
9327         stq_p(mem_buf+8, env->avr[n].u64[1]);
9328 #else
9329         stq_p(mem_buf, env->avr[n].u64[1]);
9330         stq_p(mem_buf+8, env->avr[n].u64[0]);
9331 #endif
9332         return 16;
9333     }
9334     if (n == 33) {
9335         stl_p(mem_buf, env->vscr);
9336         return 4;
9337     }
9338     if (n == 34) {
9339         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9340         return 4;
9341     }
9342     return 0;
9343 }
9344
9345 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9346 {
9347     if (n < 32) {
9348 #ifdef WORDS_BIGENDIAN
9349         env->avr[n].u64[0] = ldq_p(mem_buf);
9350         env->avr[n].u64[1] = ldq_p(mem_buf+8);
9351 #else
9352         env->avr[n].u64[1] = ldq_p(mem_buf);
9353         env->avr[n].u64[0] = ldq_p(mem_buf+8);
9354 #endif
9355         return 16;
9356     }
9357     if (n == 33) {
9358         env->vscr = ldl_p(mem_buf);
9359         return 4;
9360     }
9361     if (n == 34) {
9362         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9363         return 4;
9364     }
9365     return 0;
9366 }
9367
9368 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9369 {
9370     if (n < 32) {
9371 #if defined(TARGET_PPC64)
9372         stl_p(mem_buf, env->gpr[n] >> 32);
9373 #else
9374         stl_p(mem_buf, env->gprh[n]);
9375 #endif
9376         return 4;
9377     }
9378     if (n == 33) {
9379         stq_p(mem_buf, env->spe_acc);
9380         return 8;
9381     }
9382     if (n == 34) {
9383         /* SPEFSCR not implemented */
9384         memset(mem_buf, 0, 4);
9385         return 4;
9386     }
9387     return 0;
9388 }
9389
9390 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9391 {
9392     if (n < 32) {
9393 #if defined(TARGET_PPC64)
9394         target_ulong lo = (uint32_t)env->gpr[n];
9395         target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9396         env->gpr[n] = lo | hi;
9397 #else
9398         env->gprh[n] = ldl_p(mem_buf);
9399 #endif
9400         return 4;
9401     }
9402     if (n == 33) {
9403         env->spe_acc = ldq_p(mem_buf);
9404         return 8;
9405     }
9406     if (n == 34) {
9407         /* SPEFSCR not implemented */
9408         return 4;
9409     }
9410     return 0;
9411 }
9412
9413 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9414 {
9415     env->msr_mask = def->msr_mask;
9416     env->mmu_model = def->mmu_model;
9417     env->excp_model = def->excp_model;
9418     env->bus_model = def->bus_model;
9419     env->flags = def->flags;
9420     env->bfd_mach = def->bfd_mach;
9421     env->check_pow = def->check_pow;
9422     if (create_ppc_opcodes(env, def) < 0)
9423         return -1;
9424     init_ppc_proc(env, def);
9425
9426     if (def->insns_flags & PPC_FLOAT) {
9427         gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9428                                  33, "power-fpu.xml", 0);
9429     }
9430     if (def->insns_flags & PPC_ALTIVEC) {
9431         gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9432                                  34, "power-altivec.xml", 0);
9433     }
9434     if (def->insns_flags & PPC_SPE) {
9435         gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9436                                  34, "power-spe.xml", 0);
9437     }
9438
9439 #if defined(PPC_DUMP_CPU)
9440     {
9441         const char *mmu_model, *excp_model, *bus_model;
9442         switch (env->mmu_model) {
9443         case POWERPC_MMU_32B:
9444             mmu_model = "PowerPC 32";
9445             break;
9446         case POWERPC_MMU_SOFT_6xx:
9447             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9448             break;
9449         case POWERPC_MMU_SOFT_74xx:
9450             mmu_model = "PowerPC 74xx with software driven TLBs";
9451             break;
9452         case POWERPC_MMU_SOFT_4xx:
9453             mmu_model = "PowerPC 4xx with software driven TLBs";
9454             break;
9455         case POWERPC_MMU_SOFT_4xx_Z:
9456             mmu_model = "PowerPC 4xx with software driven TLBs "
9457                 "and zones protections";
9458             break;
9459         case POWERPC_MMU_REAL:
9460             mmu_model = "PowerPC real mode only";
9461             break;
9462         case POWERPC_MMU_MPC8xx:
9463             mmu_model = "PowerPC MPC8xx";
9464             break;
9465         case POWERPC_MMU_BOOKE:
9466             mmu_model = "PowerPC BookE";
9467             break;
9468         case POWERPC_MMU_BOOKE_FSL:
9469             mmu_model = "PowerPC BookE FSL";
9470             break;
9471         case POWERPC_MMU_601:
9472             mmu_model = "PowerPC 601";
9473             break;
9474 #if defined (TARGET_PPC64)
9475         case POWERPC_MMU_64B:
9476             mmu_model = "PowerPC 64";
9477             break;
9478         case POWERPC_MMU_620:
9479             mmu_model = "PowerPC 620";
9480             break;
9481 #endif
9482         default:
9483             mmu_model = "Unknown or invalid";
9484             break;
9485         }
9486         switch (env->excp_model) {
9487         case POWERPC_EXCP_STD:
9488             excp_model = "PowerPC";
9489             break;
9490         case POWERPC_EXCP_40x:
9491             excp_model = "PowerPC 40x";
9492             break;
9493         case POWERPC_EXCP_601:
9494             excp_model = "PowerPC 601";
9495             break;
9496         case POWERPC_EXCP_602:
9497             excp_model = "PowerPC 602";
9498             break;
9499         case POWERPC_EXCP_603:
9500             excp_model = "PowerPC 603";
9501             break;
9502         case POWERPC_EXCP_603E:
9503             excp_model = "PowerPC 603e";
9504             break;
9505         case POWERPC_EXCP_604:
9506             excp_model = "PowerPC 604";
9507             break;
9508         case POWERPC_EXCP_7x0:
9509             excp_model = "PowerPC 740/750";
9510             break;
9511         case POWERPC_EXCP_7x5:
9512             excp_model = "PowerPC 745/755";
9513             break;
9514         case POWERPC_EXCP_74xx:
9515             excp_model = "PowerPC 74xx";
9516             break;
9517         case POWERPC_EXCP_BOOKE:
9518             excp_model = "PowerPC BookE";
9519             break;
9520 #if defined (TARGET_PPC64)
9521         case POWERPC_EXCP_970:
9522             excp_model = "PowerPC 970";
9523             break;
9524 #endif
9525         default:
9526             excp_model = "Unknown or invalid";
9527             break;
9528         }
9529         switch (env->bus_model) {
9530         case PPC_FLAGS_INPUT_6xx:
9531             bus_model = "PowerPC 6xx";
9532             break;
9533         case PPC_FLAGS_INPUT_BookE:
9534             bus_model = "PowerPC BookE";
9535             break;
9536         case PPC_FLAGS_INPUT_405:
9537             bus_model = "PowerPC 405";
9538             break;
9539         case PPC_FLAGS_INPUT_401:
9540             bus_model = "PowerPC 401/403";
9541             break;
9542         case PPC_FLAGS_INPUT_RCPU:
9543             bus_model = "RCPU / MPC8xx";
9544             break;
9545 #if defined (TARGET_PPC64)
9546         case PPC_FLAGS_INPUT_970:
9547             bus_model = "PowerPC 970";
9548             break;
9549 #endif
9550         default:
9551             bus_model = "Unknown or invalid";
9552             break;
9553         }
9554         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9555                "    MMU model        : %s\n",
9556                def->name, def->pvr, def->msr_mask, mmu_model);
9557 #if !defined(CONFIG_USER_ONLY)
9558         if (env->tlb != NULL) {
9559             printf("                       %d %s TLB in %d ways\n",
9560                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9561                    env->nb_ways);
9562         }
9563 #endif
9564         printf("    Exceptions model : %s\n"
9565                "    Bus model        : %s\n",
9566                excp_model, bus_model);
9567         printf("    MSR features     :\n");
9568         if (env->flags & POWERPC_FLAG_SPE)
9569             printf("                        signal processing engine enable"
9570                    "\n");
9571         else if (env->flags & POWERPC_FLAG_VRE)
9572             printf("                        vector processor enable\n");
9573         if (env->flags & POWERPC_FLAG_TGPR)
9574             printf("                        temporary GPRs\n");
9575         else if (env->flags & POWERPC_FLAG_CE)
9576             printf("                        critical input enable\n");
9577         if (env->flags & POWERPC_FLAG_SE)
9578             printf("                        single-step trace mode\n");
9579         else if (env->flags & POWERPC_FLAG_DWE)
9580             printf("                        debug wait enable\n");
9581         else if (env->flags & POWERPC_FLAG_UBLE)
9582             printf("                        user BTB lock enable\n");
9583         if (env->flags & POWERPC_FLAG_BE)
9584             printf("                        branch-step trace mode\n");
9585         else if (env->flags & POWERPC_FLAG_DE)
9586             printf("                        debug interrupt enable\n");
9587         if (env->flags & POWERPC_FLAG_PX)
9588             printf("                        inclusive protection\n");
9589         else if (env->flags & POWERPC_FLAG_PMM)
9590             printf("                        performance monitor mark\n");
9591         if (env->flags == POWERPC_FLAG_NONE)
9592             printf("                        none\n");
9593         printf("    Time-base/decrementer clock source: %s\n",
9594                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9595     }
9596     dump_ppc_insns(env);
9597     dump_ppc_sprs(env);
9598     fflush(stdout);
9599 #endif
9600
9601     return 0;
9602 }
9603
9604 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9605 {
9606     const ppc_def_t *ret;
9607     uint32_t pvr_rev;
9608     int i, best, match, best_match, max;
9609
9610     ret = NULL;
9611     max = ARRAY_SIZE(ppc_defs);
9612     best = -1;
9613     pvr_rev = pvr & 0xFFFF;
9614     /* We want all specified bits to match */
9615     best_match = 32 - ctz32(pvr_rev);
9616     for (i = 0; i < max; i++) {
9617         /* We check that the 16 higher bits are the same to ensure the CPU
9618          * model will be the choosen one.
9619          */
9620         if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9621             /* We want as much as possible of the low-level 16 bits
9622              * to be the same but we allow inexact matches.
9623              */
9624             match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9625             /* We check '>=' instead of '>' because the PPC_defs table
9626              * is ordered by increasing revision.
9627              * Then, we will match the higher revision compatible
9628              * with the requested PVR
9629              */
9630             if (match >= best_match) {
9631                 best = i;
9632                 best_match = match;
9633             }
9634         }
9635     }
9636     if (best != -1)
9637         ret = &ppc_defs[best];
9638
9639     return ret;
9640 }
9641
9642 #include <ctype.h>
9643
9644 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9645 {
9646     const ppc_def_t *ret;
9647     const char *p;
9648     int i, max, len;
9649
9650     /* Check if the given name is a PVR */
9651     len = strlen(name);
9652     if (len == 10 && name[0] == '0' && name[1] == 'x') {
9653         p = name + 2;
9654         goto check_pvr;
9655     } else if (len == 8) {
9656         p = name;
9657     check_pvr:
9658         for (i = 0; i < 8; i++) {
9659             if (!qemu_isxdigit(*p++))
9660                 break;
9661         }
9662         if (i == 8)
9663             return ppc_find_by_pvr(strtoul(name, NULL, 16));
9664     }
9665     ret = NULL;
9666     max = ARRAY_SIZE(ppc_defs);
9667     for (i = 0; i < max; i++) {
9668         if (strcasecmp(name, ppc_defs[i].name) == 0) {
9669             ret = &ppc_defs[i];
9670             break;
9671         }
9672     }
9673
9674     return ret;
9675 }
9676
9677 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9678 {
9679     int i, max;
9680
9681     max = ARRAY_SIZE(ppc_defs);
9682     for (i = 0; i < max; i++) {
9683         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9684                        ppc_defs[i].name, ppc_defs[i].pvr);
9685     }
9686 }