| commit | 40569b7edc2959c7460211de0b30bbdbb87626e4 | |
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | |
| Mon, 9 Feb 2009 16:49:50 +0000 (9 16:49 +0000) | ||
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | |
| Mon, 9 Feb 2009 16:49:50 +0000 (9 16:49 +0000) | ||
| tree | c19948daf6614dda235e1c4b7fc21ada42859432 | treesnapshot (tar.gz zip) |
| parent | 071fc3b1cda1ad6f8d4b83cdf3f8cf8c395f9404 | commitdiff |
target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
Single-precision and double-precision floating-point instructions should
be separated into their own categories, since some chips only support
single-precision instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
| target-ppc/translate.c | diffblobblamehistory | |
| target-ppc/translate_init.c | diffblobblamehistory |