hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 /* PCI includes legacy ISA access.  */
   5 #include "isa.h"
   6
   7 /* imported from <linux/pci.h> */
   8 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
   9 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  10
  11 /* PCI bus */
  12 extern target_phys_addr_t pci_mem_base;
  13
  14 /* Device classes and subclasses */
  15
  16 #define PCI_CLASS_STORAGE_SCSI           0x0100
  17 #define PCI_CLASS_STORAGE_IDE            0x0101
  18 #define PCI_CLASS_STORAGE_OTHER          0x0180
  19
  20 #define PCI_CLASS_NETWORK_ETHERNET       0x0200
  21
  22 #define PCI_CLASS_DISPLAY_VGA            0x0300
  23 #define PCI_CLASS_DISPLAY_OTHER          0x0380
  24
  25 #define PCI_CLASS_MULTIMEDIA_AUDIO       0x0401
  26
  27 #define PCI_CLASS_MEMORY_RAM             0x0500
  28
  29 #define PCI_CLASS_SYSTEM_OTHER           0x0880
  30
  31 #define PCI_CLASS_SERIAL_USB             0x0c03
  32
  33 #define PCI_CLASS_BRIDGE_HOST            0x0600
  34 #define PCI_CLASS_BRIDGE_ISA             0x0601
  35 #define PCI_CLASS_BRIDGE_PCI             0x0604
  36 #define PCI_CLASS_BRIDGE_OTHER           0x0680
  37
  38 #define PCI_CLASS_PROCESSOR_CO           0x0b40
  39
  40 #define PCI_CLASS_OTHERS                 0xff
  41
  42 /* Vendors and devices. */
  43
  44 #define PCI_VENDOR_ID_LSI_LOGIC          0x1000
  45 #define PCI_DEVICE_ID_LSI_53C895A        0x0012
  46
  47 #define PCI_VENDOR_ID_DEC                0x1011
  48 #define PCI_DEVICE_ID_DEC_21154          0x0026
  49
  50 #define PCI_VENDOR_ID_CIRRUS             0x1013
  51
  52 #define PCI_VENDOR_ID_IBM                0x1014
  53 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  54
  55 #define PCI_VENDOR_ID_AMD                0x1022
  56 #define PCI_DEVICE_ID_AMD_LANCE          0x2000
  57
  58 #define PCI_VENDOR_ID_HITACHI            0x1054
  59
  60 #define PCI_VENDOR_ID_MOTOROLA           0x1057
  61 #define PCI_DEVICE_ID_MOTOROLA_MPC106    0x0002
  62 #define PCI_DEVICE_ID_MOTOROLA_RAVEN     0x4801
  63
  64 #define PCI_VENDOR_ID_APPLE              0x106b
  65 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  66 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  67 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  68 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP    0x0020
  69 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  70
  71 #define PCI_VENDOR_ID_SUN                0x108e
  72 #define PCI_DEVICE_ID_SUN_EBUS           0x1000
  73 #define PCI_DEVICE_ID_SUN_SIMBA          0x5000
  74 #define PCI_DEVICE_ID_SUN_SABRE          0xa000
  75
  76 #define PCI_VENDOR_ID_CMD                0x1095
  77 #define PCI_DEVICE_ID_CMD_646            0x0646
  78
  79 #define PCI_VENDOR_ID_REALTEK            0x10ec
  80 #define PCI_DEVICE_ID_REALTEK_RTL8029    0x8029
  81 #define PCI_DEVICE_ID_REALTEK_8139       0x8139
  82
  83 #define PCI_VENDOR_ID_XILINX             0x10ee
  84
  85 #define PCI_VENDOR_ID_MARVELL            0x11ab
  86
  87 #define PCI_VENDOR_ID_QEMU               0x1234
  88 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  89
  90 #define PCI_VENDOR_ID_ENSONIQ            0x1274
  91 #define PCI_DEVICE_ID_ENSONIQ_ES1370     0x5000
  92
  93 #define PCI_VENDOR_ID_VMWARE             0x15ad
  94 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  95 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  96 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  97 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  98 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  99
 100 #define PCI_VENDOR_ID_INTEL              0x8086
 101 #define PCI_DEVICE_ID_INTEL_82441        0x1237
 102 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
 103 #define PCI_DEVICE_ID_INTEL_82371SB_0    0x7000
 104 #define PCI_DEVICE_ID_INTEL_82371SB_1    0x7010
 105 #define PCI_DEVICE_ID_INTEL_82371SB_2    0x7020
 106 #define PCI_DEVICE_ID_INTEL_82371AB_0    0x7110
 107 #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
 108 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
 109 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
 110
 111 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
 112 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
 113 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
 114 #define PCI_SUBDEVICE_ID_QEMU            0x1100
 115
 116 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
 117 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
 118 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
 119 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
 120
 121 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 122                                 uint32_t address, uint32_t data, int len);
 123 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 124                                    uint32_t address, int len);
 125 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 126                                 uint32_t addr, uint32_t size, int type);
 127 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
 128
 129 #define PCI_ADDRESS_SPACE_MEM           0x00
 130 #define PCI_ADDRESS_SPACE_IO            0x01
 131 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
 132
 133 typedef struct PCIIORegion {
 134     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
 135     uint32_t size;
 136     uint8_t type;
 137     PCIMapIORegionFunc *map_func;
 138 } PCIIORegion;
 139
 140 #define PCI_ROM_SLOT 6
 141 #define PCI_NUM_REGIONS 7
 142
 143 #define PCI_DEVICES_MAX 64
 144
 145 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 146 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 147 #define PCI_COMMAND             0x04    /* 16 bits */
 148 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 149 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 150 #define PCI_REVISION            0x08
 151 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 152 #define PCI_SUBVENDOR_ID        0x2c    /* 16 bits */
 153 #define PCI_SUBDEVICE_ID        0x2e    /* 16 bits */
 154 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 155 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 156 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 157 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 158
 159 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 160 #define PCI_STATUS_RESERVED1    0x007
 161 #define PCI_STATUS_INT_STATUS   0x008
 162 #define PCI_STATUS_CAPABILITIES 0x010
 163 #define PCI_STATUS_66MHZ        0x020
 164 #define PCI_STATUS_RESERVED2    0x040
 165 #define PCI_STATUS_FAST_BACK    0x080
 166 #define PCI_STATUS_DEVSEL       0x600
 167
 168 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 169                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 170                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 171
 172 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 173
 174 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 175 #define PCI_COMMAND_RESERVED    0xf800
 176
 177 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 178
 179 struct PCIDevice {
 180     /* PCI config space */
 181     uint8_t config[256];
 182
 183     /* the following fields are read only */
 184     PCIBus *bus;
 185     int devfn;
 186     char name[64];
 187     PCIIORegion io_regions[PCI_NUM_REGIONS];
 188
 189     /* do not access the following fields */
 190     PCIConfigReadFunc *config_read;
 191     PCIConfigWriteFunc *config_write;
 192     PCIUnregisterFunc *unregister;
 193     /* ??? This is a PC-specific hack, and should be removed.  */
 194     int irq_index;
 195
 196     /* IRQ objects for the INTA-INTD pins.  */
 197     qemu_irq *irq;
 198
 199     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 200     int irq_state[4];
 201 };
 202
 203 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 204                                int instance_size, int devfn,
 205                                PCIConfigReadFunc *config_read,
 206                                PCIConfigWriteFunc *config_write);
 207
 208 int pci_unregister_device(PCIDevice *pci_dev);
 209
 210 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 211                             uint32_t size, int type,
 212                             PCIMapIORegionFunc *map_func);
 213
 214 int pci_map_irq(PCIDevice *pci_dev, int pin);
 215 uint32_t pci_default_read_config(PCIDevice *d,
 216                                  uint32_t address, int len);
 217 void pci_default_write_config(PCIDevice *d,
 218                               uint32_t address, uint32_t val, int len);
 219 void pci_device_save(PCIDevice *s, QEMUFile *f);
 220 int pci_device_load(PCIDevice *s, QEMUFile *f);
 221
 222 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 223 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 224 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 225                          qemu_irq *pic, int devfn_min, int nirq);
 226
 227 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 228                   const char *default_model);
 229 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 230 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 231 int pci_bus_num(PCIBus *s);
 232 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 233 PCIBus *pci_find_bus(int bus_num);
 234 PCIDevice *pci_find_device(int bus_num, int slot);
 235
 236 void pci_info(void);
 237 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 238                         pci_map_irq_fn map_irq, const char *name);
 239
 240 static inline void
 241 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 242 {
 243     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 244 }
 245
 246 static inline void
 247 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 248 {
 249     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 250 }
 251
 252 static inline void
 253 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 254 {
 255     cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
 256 }
 257
 258 /* lsi53c895a.c */
 259 #define LSI_MAX_DEVS 7
 260 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 261 void *lsi_scsi_init(PCIBus *bus, int devfn);
 262
 263 /* vmware_vga.c */
 264 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
 265                      unsigned long vga_ram_offset, int vga_ram_size);
 266
 267 /* usb-uhci.c */
 268 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 269 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 270
 271 /* usb-ohci.c */
 272 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 273
 274 /* eepro100.c */
 275
 276 PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 277 PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 278 PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 279
 280 /* ne2000.c */
 281
 282 PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 283
 284 /* rtl8139.c */
 285
 286 PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 287
 288 /* e1000.c */
 289 PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 290
 291 /* pcnet.c */
 292 PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 293
 294 /* prep_pci.c */
 295 PCIBus *pci_prep_init(qemu_irq *pic);
 296
 297 /* apb_pci.c */
 298 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 299                      target_phys_addr_t mem_base,
 300                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 301
 302 /* sh_pci.c */
 303 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 304                             qemu_irq *pic, int devfn_min, int nirq);
 305
 306 #endif