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revert to the old l.sfxxi behavior
[or1200.git] / sim / 
treeb13369bc4409b13b1771e1f2bdcb96a189e4ed5d
drwxr-xr-x   ..
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32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities