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description32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities
homepage URLhttp://www.opencores.org
ownerricky.nite@gmail.com
last changeSun, 9 Apr 2006 01:32:29 +0000 (9 01:32 +0000)
URLgit://repo.or.cz/or1200.git
https://repo.or.cz/or1200.git
push URLssh://repo.or.cz/or1200.git
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2006-04-09 lampretSee OR1200_MAC_SHIFTBY in or1200_defines.v for explanat... master commit | commitdiff | tree | snapshot (tar.gz zip)
2005-10-19 jcastilloFirst Import commit | commitdiff | tree | snapshot (tar.gz zip)
2005-10-19 jcastilloAdded support for RAMB16 Xilinx4/Spartan3 primitives commit | commitdiff | tree | snapshot (tar.gz zip)
2005-01-13 phoenixrevert to the old l.sfxxi behavior commit | commitdiff | tree | snapshot (tar.gz zip)
2005-01-07 andrejedu_hwbkpt disabled when debug unit not implemented commit | commitdiff | tree | snapshot (tar.gz zip)
2005-01-07 andrejesign/zero extension for l.sfxxi instructions corrected commit | commitdiff | tree | snapshot (tar.gz zip)
2005-01-07 andrejeflag for l.cmov instruction added commit | commitdiff | tree | snapshot (tar.gz zip)
2005-01-07 andrejel.ff1 and l.cmov instructions added commit | commitdiff | tree | snapshot (tar.gz zip)
2004-06-08 lampretNon-functional changes. Coding style fixes. commit | commitdiff | tree | snapshot (tar.gz zip)
2004-06-08 lampretGPR0 hardwired to zero. commit | commitdiff | tree | snapshot (tar.gz zip)
2004-06-08 lampretChanged behavior of the simulation generic models commit | commitdiff | tree | snapshot (tar.gz zip)
2004-05-09 lampretBy default l.cust5 insns are disabled commit | commitdiff | tree | snapshot (tar.gz zip)
2004-05-09 lampretAdded some l.cust5 custom instructions as example commit | commitdiff | tree | snapshot (tar.gz zip)
2004-04-08 simontAdd support for 512B instruction cache. commit | commitdiff | tree | snapshot (tar.gz zip)
2004-04-05 lampretMerged branch_qmem into main tree. commit | commitdiff | tree | snapshot (tar.gz zip)
2004-04-05 lampretMerged branch_qmem into main tree. commit | commitdiff | tree | snapshot (tar.gz zip)
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18 years ago master log | tree
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities