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revert to the old l.sfxxi behavior
[or1200.git] / rtl / 
tree9716a1316f7ec6d363e443f2c6b4f9cfb9e4cd12
drwxr-xr-x   ..
drwxr-xr-x - verilog tree | history
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities