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Remove FSF address from GPL notices
[openocd.git] / src / target / adi_v5_jtag.c
blob272d308fd2780f17615d0589d5e79c2a882a7da4
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
3 * lundin@mlu.mine.nu
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * Copyright (C) 2009-2010 by David Brownell
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 ***************************************************************************/
26
27 /**
28 * @file
29 * This file implements JTAG transport support for cores implementing
30 the ARM Debug Interface version 5 (ADIv5).
31 */
32
33 #ifdef HAVE_CONFIG_H
34 #include "config.h"
35 #endif
36
37 #include "arm.h"
38 #include "arm_adi_v5.h"
39 #include <helper/time_support.h>
40 #include <helper/list.h>
41
42 /*#define DEBUG_WAIT*/
43
44 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
45 #define JTAG_DP_ABORT 0x8
46 #define JTAG_DP_DPACC 0xA
47 #define JTAG_DP_APACC 0xB
48 #define JTAG_DP_IDCODE 0xE
49
50 /* three-bit ACK values for DPACC and APACC reads */
51 #define JTAG_ACK_OK_FAULT 0x2
52 #define JTAG_ACK_WAIT 0x1
53
54 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
55
56 #ifdef DEBUG_WAIT
57 static const char *dap_reg_name(int instr, int reg_addr)
58 {
59 char *reg_name = "UNK";
60
61 if (instr == JTAG_DP_DPACC) {
62 switch (reg_addr) {
63 case DP_ABORT:
64 reg_name = "ABORT";
65 break;
66 case DP_CTRL_STAT:
67 reg_name = "CTRL/STAT";
68 break;
69 case DP_SELECT:
70 reg_name = "SELECT";
71 break;
72 case DP_RDBUFF:
73 reg_name = "RDBUFF";
74 break;
75 case DP_WCR:
76 reg_name = "WCR";
77 break;
78 default:
79 reg_name = "UNK";
80 break;
81 }
82 }
83
84 if (instr == JTAG_DP_APACC) {
85 switch (reg_addr) {
86 case MEM_AP_REG_CSW:
87 reg_name = "CSW";
88 break;
89 case MEM_AP_REG_TAR:
90 reg_name = "TAR";
91 break;
92 case MEM_AP_REG_DRW:
93 reg_name = "DRW";
94 break;
95 case MEM_AP_REG_BD0:
96 reg_name = "BD0";
97 break;
98 case MEM_AP_REG_BD1:
99 reg_name = "BD1";
100 break;
101 case MEM_AP_REG_BD2:
102 reg_name = "BD2";
103 break;
104 case MEM_AP_REG_BD3:
105 reg_name = "BD3";
106 break;
107 case MEM_AP_REG_CFG:
108 reg_name = "CFG";
109 break;
110 case MEM_AP_REG_BASE:
111 reg_name = "BASE";
112 break;
113 case AP_REG_IDR:
114 reg_name = "IDR";
115 break;
116 default:
117 reg_name = "UNK";
118 break;
119 }
120 }
121
122 return reg_name;
123 }
124 #endif
125
126 struct dap_cmd {
127 struct list_head lh;
128 uint8_t instr;
129 uint8_t reg_addr;
130 uint8_t RnW;
131 uint8_t *invalue;
132 uint8_t ack;
133 uint32_t memaccess_tck;
134 uint32_t dp_select;
135
136 struct scan_field fields[2];
137 uint8_t out_addr_buf;
138 uint8_t invalue_buf[4];
139 uint8_t outvalue_buf[4];
140 };
141
142 static void log_dap_cmd(const char *header, struct dap_cmd *el)
143 {
144 #ifdef DEBUG_WAIT
145 LOG_DEBUG("%s: %2s %6s %5s 0x%08x 0x%08x %2s", header,
146 el->instr == JTAG_DP_APACC ? "AP" : "DP",
147 dap_reg_name(el->instr, el->reg_addr),
148 el->RnW == DPAP_READ ? "READ" : "WRITE",
149 buf_get_u32(el->outvalue_buf, 0, 32),
150 buf_get_u32(el->invalue, 0, 32),
151 el->ack == JTAG_ACK_OK_FAULT ? "OK" :
152 (el->ack == JTAG_ACK_WAIT ? "WAIT" : "INVAL"));
153 #endif
154 }
155
156 static struct dap_cmd *dap_cmd_new(uint8_t instr,
157 uint8_t reg_addr, uint8_t RnW,
158 uint8_t *outvalue, uint8_t *invalue,
159 uint32_t memaccess_tck)
160 {
161 struct dap_cmd *cmd;
162
163 cmd = (struct dap_cmd *)calloc(1, sizeof(struct dap_cmd));
164 if (cmd != NULL) {
165 INIT_LIST_HEAD(&cmd->lh);
166 cmd->instr = instr;
167 cmd->reg_addr = reg_addr;
168 cmd->RnW = RnW;
169 if (outvalue != NULL)
170 memcpy(cmd->outvalue_buf, outvalue, 4);
171 cmd->invalue = (invalue != NULL) ? invalue : cmd->invalue_buf;
172 cmd->memaccess_tck = memaccess_tck;
173 }
174
175 return cmd;
176 }
177
178 static void flush_journal(struct list_head *lh)
179 {
180 struct dap_cmd *el, *tmp;
181
182 list_for_each_entry_safe(el, tmp, lh, lh) {
183 list_del(&el->lh);
184 free(el);
185 }
186 }
187
188 /***************************************************************************
189 *
190 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
191 *
192 ***************************************************************************/
193
194 static int adi_jtag_dp_scan_cmd(struct adiv5_dap *dap, struct dap_cmd *cmd, uint8_t *ack)
195 {
196 struct jtag_tap *tap = dap->tap;
197 int retval;
198
199 retval = arm_jtag_set_instr(tap, cmd->instr, NULL, TAP_IDLE);
200 if (retval != ERROR_OK)
201 return retval;
202
203 /* Scan out a read or write operation using some DP or AP register.
204 * For APACC access with any sticky error flag set, this is discarded.
205 */
206 cmd->fields[0].num_bits = 3;
207 buf_set_u32(&cmd->out_addr_buf, 0, 3, ((cmd->reg_addr >> 1) & 0x6) | (cmd->RnW & 0x1));
208 cmd->fields[0].out_value = &cmd->out_addr_buf;
209 cmd->fields[0].in_value = (ack != NULL) ? ack : &cmd->ack;
210
211 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
212 * complete; data we write is discarded, data we read is unpredictable.
213 * When overrun detect is active, STICKYORUN is set.
214 */
215
216 cmd->fields[1].num_bits = 32;
217 cmd->fields[1].out_value = cmd->outvalue_buf;
218 cmd->fields[1].in_value = cmd->invalue;
219
220 jtag_add_dr_scan(tap, 2, cmd->fields, TAP_IDLE);
221
222 /* Add specified number of tck clocks after starting memory bus
223 * access, giving the hardware time to complete the access.
224 * They provide more time for the (MEM) AP to complete the read ...
225 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
226 */
227 if (cmd->instr == JTAG_DP_APACC) {
228 if (((cmd->reg_addr == MEM_AP_REG_DRW)
229 || ((cmd->reg_addr & 0xF0) == MEM_AP_REG_BD0))
230 && (cmd->memaccess_tck != 0))
231 jtag_add_runtest(cmd->memaccess_tck, TAP_IDLE);
232 }
233
234 return ERROR_OK;
235 }
236
237 static int adi_jtag_dp_scan_cmd_sync(struct adiv5_dap *dap, struct dap_cmd *cmd, uint8_t *ack)
238 {
239 int retval;
240
241 retval = adi_jtag_dp_scan_cmd(dap, cmd, ack);
242 if (retval != ERROR_OK)
243 return retval;
244
245 return jtag_execute_queue();
246 }
247
248 /**
249 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
250 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
251 * discusses operations which access these registers.
252 *
253 * Note that only one scan is performed. If RnW is set, a separate scan
254 * will be needed to collect the data which was read; the "invalue" collects
255 * the posted result of a preceding operation, not the current one.
256 *
257 * @param dap the DAP
258 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
259 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
260 * SELECT register has more addressing bits.
261 * @param RnW false iff outvalue will be written to the DP or AP
262 * @param outvalue points to a 32-bit (little-endian) integer
263 * @param invalue NULL, or points to a 32-bit (little-endian) integer
264 * @param ack points to where the three bit JTAG_ACK_* code will be stored
265 * @param memaccess_tck number of idle cycles to add after AP access
266 */
267
268 static int adi_jtag_dp_scan(struct adiv5_dap *dap,
269 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
270 uint8_t *outvalue, uint8_t *invalue,
271 uint32_t memaccess_tck, uint8_t *ack)
272 {
273 struct dap_cmd *cmd;
274 int retval;
275
276 cmd = dap_cmd_new(instr, reg_addr, RnW, outvalue, invalue, memaccess_tck);
277 if (cmd != NULL)
278 cmd->dp_select = dap->select;
279 else
280 return ERROR_JTAG_DEVICE_ERROR;
281
282 retval = adi_jtag_dp_scan_cmd(dap, cmd, ack);
283 if (retval == ERROR_OK)
284 list_add_tail(&cmd->lh, &dap->cmd_journal);
285
286 return retval;
287 }
288
289 /**
290 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
291 * This is exactly like adi_jtag_dp_scan(), except that endianness
292 * conversions are performed (so the types of invalue and outvalue
293 * must be different).
294 */
295 static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
296 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
297 uint32_t outvalue, uint32_t *invalue,
298 uint32_t memaccess_tck, uint8_t *ack)
299 {
300 uint8_t out_value_buf[4];
301 int retval;
302
303 buf_set_u32(out_value_buf, 0, 32, outvalue);
304
305 retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
306 out_value_buf, (uint8_t *)invalue, memaccess_tck, ack);
307 if (retval != ERROR_OK)
308 return retval;
309
310 if (invalue)
311 jtag_add_callback(arm_le_to_h_u32,
312 (jtag_callback_data_t) invalue);
313
314 return retval;
315 }
316
317 static int adi_jtag_finish_read(struct adiv5_dap *dap)
318 {
319 int retval = ERROR_OK;
320
321 if (dap->last_read != NULL) {
322 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
323 DP_RDBUFF, DPAP_READ, 0, dap->last_read, 0, NULL);
324 dap->last_read = NULL;
325 }
326
327 return retval;
328 }
329
330 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
331 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
332 uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck)
333 {
334 int retval;
335
336 /* Issue the read or write */
337 retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
338 RnW, outvalue, NULL, memaccess_tck, NULL);
339 if (retval != ERROR_OK)
340 return retval;
341
342 /* For reads, collect posted value; RDBUFF has no other effect.
343 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
344 */
345 if ((RnW == DPAP_READ) && (invalue != NULL)) {
346 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
347 DP_RDBUFF, DPAP_READ, 0, invalue, 0, NULL);
348 if (retval != ERROR_OK)
349 return retval;
350 }
351
352 return jtag_execute_queue();
353 }
354
355 static int jtagdp_overrun_check(struct adiv5_dap *dap)
356 {
357 int retval;
358 struct dap_cmd *el, *tmp, *prev = NULL;
359 int found_wait = 0;
360 uint64_t time_now;
361 LIST_HEAD(replay_list);
362
363 /* make sure all queued transactions are complete */
364 retval = jtag_execute_queue();
365 if (retval != ERROR_OK)
366 goto done;
367
368 /* skip all completed transactions up to the first WAIT */
369 list_for_each_entry(el, &dap->cmd_journal, lh) {
370 if (el->ack == JTAG_ACK_OK_FAULT) {
371 log_dap_cmd("LOG", el);
372 } else if (el->ack == JTAG_ACK_WAIT) {
373 found_wait = 1;
374 break;
375 } else {
376 LOG_ERROR("Invalid ACK (%1x) in DAP response", el->ack);
377 log_dap_cmd("ERR", el);
378 retval = ERROR_JTAG_DEVICE_ERROR;
379 goto done;
380 }
381 }
382
383 /*
384 * If we found a stalled transaction and a previous transaction
385 * exists, check if it's a READ access.
386 */
387 if (found_wait && el != list_first_entry(&dap->cmd_journal, struct dap_cmd, lh)) {
388 prev = list_entry(el->lh.prev, struct dap_cmd, lh);
389 if (prev->RnW == DPAP_READ) {
390 log_dap_cmd("PND", prev);
391 /* search for the next OK transaction, it contains
392 * the result of the previous READ */
393 tmp = el;
394 list_for_each_entry_from(tmp, &dap->cmd_journal, lh) {
395 if (tmp->ack == JTAG_ACK_OK_FAULT) {
396 /* recover the read value */
397 log_dap_cmd("FND", tmp);
398 if (el->invalue != el->invalue_buf) {
399 uint32_t invalue = le_to_h_u32(tmp->invalue);
400 memcpy(el->invalue, &invalue, sizeof(uint32_t));
401 }
402 prev = NULL;
403 break;
404 }
405 }
406
407 if (prev != NULL) {
408 log_dap_cmd("LST", el);
409
410 /*
411 * At this point we're sure that no previous
412 * transaction completed and the DAP/AP is still
413 * in busy state. We know that the next "OK" scan
414 * will return the READ result we need to recover.
415 * To complete the READ, we just keep polling RDBUFF
416 * until the WAIT condition clears
417 */
418 tmp = dap_cmd_new(JTAG_DP_DPACC,
419 DP_RDBUFF, DPAP_READ, NULL, NULL, 0);
420 if (tmp == NULL) {
421 retval = ERROR_JTAG_DEVICE_ERROR;
422 goto done;
423 }
424 /* synchronously retry the command until it succeeds */
425 time_now = timeval_ms();
426 do {
427 retval = adi_jtag_dp_scan_cmd_sync(dap, tmp, NULL);
428 if (retval != ERROR_OK)
429 break;
430 if (tmp->ack == JTAG_ACK_OK_FAULT) {
431 log_dap_cmd("FND", tmp);
432 if (el->invalue != el->invalue_buf) {
433 uint32_t invalue = le_to_h_u32(tmp->invalue);
434 memcpy(el->invalue, &invalue, sizeof(uint32_t));
435 }
436 break;
437 }
438 if (tmp->ack != JTAG_ACK_WAIT) {
439 LOG_ERROR("Invalid ACK (%1x) in DAP response", tmp->ack);
440 log_dap_cmd("ERR", tmp);
441 retval = ERROR_JTAG_DEVICE_ERROR;
442 break;
443 }
444
445 } while (timeval_ms() - time_now < 1000);
446
447 if (retval == ERROR_OK) {
448 /* timeout happened */
449 if (tmp->ack != JTAG_ACK_OK_FAULT) {
450 LOG_ERROR("Timeout during WAIT recovery");
451 jtag_ap_q_abort(dap, NULL);
452 retval = ERROR_JTAG_DEVICE_ERROR;
453 }
454 }
455
456 /* we're done with this command, release it */
457 free(tmp);
458
459 if (retval != ERROR_OK)
460 goto done;
461
462 }
463 /* make el->invalue point to the default invalue
464 * so that we can safely retry it without clobbering
465 * the result we just recovered */
466 el->invalue = el->invalue_buf;
467 }
468 }
469
470 /* move all remaining transactions over to the replay list */
471 list_for_each_entry_safe_from(el, tmp, &dap->cmd_journal, lh) {
472 log_dap_cmd("REP", el);
473 list_move_tail(&el->lh, &replay_list);
474 }
475
476 /* we're done with the journal, flush it */
477 flush_journal(&dap->cmd_journal);
478
479 /* check for overrun condition in the last batch of transactions */
480 if (found_wait) {
481 LOG_INFO("DAP transaction stalled (WAIT) - slowing down");
482 /* clear the sticky overrun condition */
483 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
484 DP_CTRL_STAT, DPAP_WRITE,
485 dap->dp_ctrl_stat | SSTICKYORUN, NULL, 0);
486 if (retval != ERROR_OK)
487 goto done;
488
489 /* restore SELECT register first */
490 if (!list_empty(&replay_list)) {
491 el = list_first_entry(&replay_list, struct dap_cmd, lh);
492 tmp = dap_cmd_new(JTAG_DP_DPACC,
493 DP_SELECT, DPAP_WRITE, (uint8_t *)&el->dp_select, NULL, 0);
494 if (tmp == NULL) {
495 retval = ERROR_JTAG_DEVICE_ERROR;
496 goto done;
497 }
498 list_add(&tmp->lh, &replay_list);
499
500 dap->select = DP_SELECT_INVALID;
501 }
502
503 list_for_each_entry_safe(el, tmp, &replay_list, lh) {
504 time_now = timeval_ms();
505 do {
506 retval = adi_jtag_dp_scan_cmd_sync(dap, el, NULL);
507 if (retval != ERROR_OK)
508 break;
509 log_dap_cmd("REC", el);
510 if (el->ack == JTAG_ACK_OK_FAULT) {
511 if (el->invalue != el->invalue_buf) {
512 uint32_t invalue = le_to_h_u32(el->invalue);
513 memcpy(el->invalue, &invalue, sizeof(uint32_t));
514 }
515 break;
516 }
517 if (el->ack != JTAG_ACK_WAIT) {
518 LOG_ERROR("Invalid ACK (%1x) in DAP response", el->ack);
519 log_dap_cmd("ERR", el);
520 retval = ERROR_JTAG_DEVICE_ERROR;
521 break;
522 }
523 } while (timeval_ms() - time_now < 1000);
524
525 if (retval == ERROR_OK) {
526 if (el->ack != JTAG_ACK_OK_FAULT) {
527 LOG_ERROR("Timeout during WAIT recovery");
528 jtag_ap_q_abort(dap, NULL);
529 retval = ERROR_JTAG_DEVICE_ERROR;
530 }
531 } else
532 break;
533 }
534 }
535
536 done:
537 flush_journal(&replay_list);
538 flush_journal(&dap->cmd_journal);
539 return retval;
540 }
541
542 static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
543 {
544 int retval;
545 uint32_t ctrlstat;
546
547 /* too expensive to call keep_alive() here */
548
549 /* Post CTRL/STAT read; discard any previous posted read value
550 * but collect its ACK status.
551 */
552 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
553 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
554 if (retval != ERROR_OK)
555 goto done;
556
557 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
558
559 /* Check for STICKYERR */
560 if (ctrlstat & SSTICKYERR) {
561 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
562 /* Check power to debug regions */
563 if ((ctrlstat & (CDBGPWRUPREQ | CDBGPWRUPACK | CSYSPWRUPREQ | CSYSPWRUPACK)) !=
564 (CDBGPWRUPREQ | CDBGPWRUPACK | CSYSPWRUPREQ | CSYSPWRUPACK)) {
565 LOG_ERROR("Debug regions are unpowered, an unexpected reset might have happened");
566 retval = ERROR_JTAG_DEVICE_ERROR;
567 goto done;
568 }
569
570 if (ctrlstat & SSTICKYERR)
571 LOG_ERROR("JTAG-DP STICKY ERROR");
572 if (ctrlstat & SSTICKYORUN)
573 LOG_DEBUG("JTAG-DP STICKY OVERRUN");
574
575 /* Clear Sticky Error Bits */
576 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
577 DP_CTRL_STAT, DPAP_WRITE,
578 dap->dp_ctrl_stat | SSTICKYERR, NULL, 0);
579 if (retval != ERROR_OK)
580 goto done;
581
582 if (ctrlstat & SSTICKYERR) {
583 retval = ERROR_JTAG_DEVICE_ERROR;
584 goto done;
585 }
586 }
587
588 done:
589 flush_journal(&dap->cmd_journal);
590 return retval;
591 }
592
593 /*--------------------------------------------------------------------------*/
594
595 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
596 uint32_t *data)
597 {
598 int retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC, reg,
599 DPAP_READ, 0, dap->last_read, 0, NULL);
600 dap->last_read = data;
601 return retval;
602 }
603
604 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
605 uint32_t data)
606 {
607 int retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
608 reg, DPAP_WRITE, data, dap->last_read, 0, NULL);
609 dap->last_read = NULL;
610 return retval;
611 }
612
613 /** Select the AP register bank matching bits 7:4 of reg. */
614 static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
615 {
616 struct adiv5_dap *dap = ap->dap;
617 uint32_t sel = ((uint32_t)ap->ap_num << 24) | (reg & 0x000000F0);
618
619 if (sel == dap->select)
620 return ERROR_OK;
621
622 dap->select = sel;
623
624 return jtag_dp_q_write(dap, DP_SELECT, sel);
625 }
626
627 static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
628 uint32_t *data)
629 {
630 int retval = jtag_ap_q_bankselect(ap, reg);
631 if (retval != ERROR_OK)
632 return retval;
633
634 retval = adi_jtag_dp_scan_u32(ap->dap, JTAG_DP_APACC, reg,
635 DPAP_READ, 0, ap->dap->last_read, ap->memaccess_tck, NULL);
636 ap->dap->last_read = data;
637
638 return retval;
639 }
640
641 static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
642 uint32_t data)
643 {
644 int retval = jtag_ap_q_bankselect(ap, reg);
645 if (retval != ERROR_OK)
646 return retval;
647
648 retval = adi_jtag_dp_scan_u32(ap->dap, JTAG_DP_APACC, reg,
649 DPAP_WRITE, data, ap->dap->last_read, ap->memaccess_tck, NULL);
650 ap->dap->last_read = NULL;
651 return retval;
652 }
653
654 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
655 {
656 /* for JTAG, this is the only valid ABORT register operation */
657 int retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
658 0, DPAP_WRITE, 1, NULL, 0, NULL);
659 if (retval != ERROR_OK)
660 return retval;
661
662 return jtag_execute_queue();
663 }
664
665 static int jtag_dp_run(struct adiv5_dap *dap)
666 {
667 int retval;
668 int retval2 = ERROR_OK;
669
670 retval = adi_jtag_finish_read(dap);
671 if (retval != ERROR_OK)
672 goto done;
673 retval2 = jtagdp_overrun_check(dap);
674 retval = jtagdp_transaction_endcheck(dap);
675
676 done:
677 return (retval2 != ERROR_OK) ? retval2 : retval;
678 }
679
680 static int jtag_dp_sync(struct adiv5_dap *dap)
681 {
682 return jtagdp_overrun_check(dap);
683 }
684
685 /* FIXME don't export ... just initialize as
686 * part of DAP setup
687 */
688 const struct dap_ops jtag_dp_ops = {
689 .queue_dp_read = jtag_dp_q_read,
690 .queue_dp_write = jtag_dp_q_write,
691 .queue_ap_read = jtag_ap_q_read,
692 .queue_ap_write = jtag_ap_q_write,
693 .queue_ap_abort = jtag_ap_q_abort,
694 .run = jtag_dp_run,
695 .sync = jtag_dp_sync,
696 };
697
698
699 static const uint8_t swd2jtag_bitseq[] = {
700 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
701 * putting both JTAG and SWD logic into reset state.
702 */
703 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
704 /* Switching equence disables SWD and enables JTAG
705 * NOTE: bits in the DP's IDCODE can expose the need for
706 * the old/deprecated sequence (0xae 0xde).
707 */
708 0x3c, 0xe7,
709 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
710 * putting both JTAG and SWD logic into reset state.
711 * NOTE: some docs say "at least 5".
712 */
713 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
714 };
715
716 /** Put the debug link into JTAG mode, if the target supports it.
717 * The link's initial mode may be either SWD or JTAG.
718 *
719 * @param target Enters JTAG mode (if possible).
720 *
721 * Note that targets implemented with SW-DP do not support JTAG, and
722 * that some targets which could otherwise support it may have been
723 * configured to disable JTAG signaling
724 *
725 * @return ERROR_OK or else a fault code.
726 */
727 int dap_to_jtag(struct target *target)
728 {
729 int retval;
730
731 LOG_DEBUG("Enter JTAG mode");
732
733 /* REVISIT it's nasty to need to make calls to a "jtag"
734 * subsystem if the link isn't in JTAG mode...
735 */
736
737 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
738 swd2jtag_bitseq, TAP_RESET);
739 if (retval == ERROR_OK)
740 retval = jtag_execute_queue();
741
742 /* REVISIT set up the DAP's ops vector for JTAG mode. */
743
744 return retval;
745 }
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