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Remove FSF address from GPL notices
[openocd.git] / src / flash / nor / at91samd.c
blobc9c0e80dc416c1795e15678ef927c28072d77fa2
1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "imp.h"
24 #include "helper/binarybuffer.h"
25
26 #include <target/cortex_m.h>
27
28 #define SAMD_NUM_SECTORS 16
29 #define SAMD_PAGE_SIZE_MAX 1024
30
31 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
32 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
33 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
34 #define SAMD_DSU 0x41002000 /* Device Service Unit */
35 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
36
37 #define SAMD_DSU_STATUSA 1 /* DSU status register */
38 #define SAMD_DSU_DID 0x18 /* Device ID register */
39
40 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
41 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
42 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
43 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
44 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
45 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
46 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
47
48 #define SAMD_CMDEX_KEY 0xA5UL
49 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
50
51 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
52 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
53 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
54 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
55 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
56 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
57 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
58 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
59 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
60 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
61 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
62 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
63
64 /* NVMCTRL bits */
65 #define SAMD_NVM_CTRLB_MANW 0x80
66
67 /* Known identifiers */
68 #define SAMD_PROCESSOR_M0 0x01
69 #define SAMD_FAMILY_D 0x00
70 #define SAMD_FAMILY_L 0x01
71 #define SAMD_FAMILY_C 0x02
72 #define SAMD_SERIES_20 0x00
73 #define SAMD_SERIES_21 0x01
74 #define SAMD_SERIES_22 0x02
75 #define SAMD_SERIES_10 0x02
76 #define SAMD_SERIES_11 0x03
77
78 /* Device ID macros */
79 #define SAMD_GET_PROCESSOR(id) (id >> 28)
80 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
81 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
82 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
83
84 struct samd_part {
85 uint8_t id;
86 const char *name;
87 uint32_t flash_kb;
88 uint32_t ram_kb;
89 };
90
91 /* Known SAMD10 parts */
92 static const struct samd_part samd10_parts[] = {
93 { 0x0, "SAMD10D14AMU", 16, 4 },
94 { 0x1, "SAMD10D13AMU", 8, 4 },
95 { 0x2, "SAMD10D12AMU", 4, 4 },
96 { 0x3, "SAMD10D14ASU", 16, 4 },
97 { 0x4, "SAMD10D13ASU", 8, 4 },
98 { 0x5, "SAMD10D12ASU", 4, 4 },
99 { 0x6, "SAMD10C14A", 16, 4 },
100 { 0x7, "SAMD10C13A", 8, 4 },
101 { 0x8, "SAMD10C12A", 4, 4 },
102 };
103
104 /* Known SAMD11 parts */
105 static const struct samd_part samd11_parts[] = {
106 { 0x0, "SAMD11D14AMU", 16, 4 },
107 { 0x1, "SAMD11D13AMU", 8, 4 },
108 { 0x2, "SAMD11D12AMU", 4, 4 },
109 { 0x3, "SAMD11D14ASU", 16, 4 },
110 { 0x4, "SAMD11D13ASU", 8, 4 },
111 { 0x5, "SAMD11D12ASU", 4, 4 },
112 { 0x6, "SAMD11C14A", 16, 4 },
113 { 0x7, "SAMD11C13A", 8, 4 },
114 { 0x8, "SAMD11C12A", 4, 4 },
115 };
116
117 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
118 static const struct samd_part samd20_parts[] = {
119 { 0x0, "SAMD20J18A", 256, 32 },
120 { 0x1, "SAMD20J17A", 128, 16 },
121 { 0x2, "SAMD20J16A", 64, 8 },
122 { 0x3, "SAMD20J15A", 32, 4 },
123 { 0x4, "SAMD20J14A", 16, 2 },
124 { 0x5, "SAMD20G18A", 256, 32 },
125 { 0x6, "SAMD20G17A", 128, 16 },
126 { 0x7, "SAMD20G16A", 64, 8 },
127 { 0x8, "SAMD20G15A", 32, 4 },
128 { 0x9, "SAMD20G14A", 16, 2 },
129 { 0xA, "SAMD20E18A", 256, 32 },
130 { 0xB, "SAMD20E17A", 128, 16 },
131 { 0xC, "SAMD20E16A", 64, 8 },
132 { 0xD, "SAMD20E15A", 32, 4 },
133 { 0xE, "SAMD20E14A", 16, 2 },
134 };
135
136 /* Known SAMD21 parts. */
137 static const struct samd_part samd21_parts[] = {
138 { 0x0, "SAMD21J18A", 256, 32 },
139 { 0x1, "SAMD21J17A", 128, 16 },
140 { 0x2, "SAMD21J16A", 64, 8 },
141 { 0x3, "SAMD21J15A", 32, 4 },
142 { 0x4, "SAMD21J14A", 16, 2 },
143 { 0x5, "SAMD21G18A", 256, 32 },
144 { 0x6, "SAMD21G17A", 128, 16 },
145 { 0x7, "SAMD21G16A", 64, 8 },
146 { 0x8, "SAMD21G15A", 32, 4 },
147 { 0x9, "SAMD21G14A", 16, 2 },
148 { 0xA, "SAMD21E18A", 256, 32 },
149 { 0xB, "SAMD21E17A", 128, 16 },
150 { 0xC, "SAMD21E16A", 64, 8 },
151 { 0xD, "SAMD21E15A", 32, 4 },
152 { 0xE, "SAMD21E14A", 16, 2 },
153 /* Below are B Variants (Table 3-7 from rev I of datasheet) */
154 { 0x20, "SAMD21J16B", 64, 8 },
155 { 0x21, "SAMD21J15B", 32, 4 },
156 { 0x23, "SAMD21G16B", 64, 8 },
157 { 0x24, "SAMD21G15B", 32, 4 },
158 { 0x26, "SAMD21E16B", 64, 8 },
159 { 0x27, "SAMD21E15B", 32, 4 },
160 };
161
162 /* Known SAMR21 parts. */
163 static const struct samd_part samr21_parts[] = {
164 { 0x19, "SAMR21G18A", 256, 32 },
165 { 0x1A, "SAMR21G17A", 128, 32 },
166 { 0x1B, "SAMR21G16A", 64, 32 },
167 { 0x1C, "SAMR21E18A", 256, 32 },
168 { 0x1D, "SAMR21E17A", 128, 32 },
169 { 0x1E, "SAMR21E16A", 64, 32 },
170 };
171
172 /* Known SAML21 parts. */
173 static const struct samd_part saml21_parts[] = {
174 { 0x00, "SAML21J18A", 256, 32 },
175 { 0x01, "SAML21J17A", 128, 16 },
176 { 0x02, "SAML21J16A", 64, 8 },
177 { 0x05, "SAML21G18A", 256, 32 },
178 { 0x06, "SAML21G17A", 128, 16 },
179 { 0x07, "SAML21G16A", 64, 8 },
180 { 0x0A, "SAML21E18A", 256, 32 },
181 { 0x0B, "SAML21E17A", 128, 16 },
182 { 0x0C, "SAML21E16A", 64, 8 },
183 { 0x0D, "SAML21E15A", 32, 4 },
184 { 0x0F, "SAML21J18B", 256, 32 },
185 { 0x10, "SAML21J17B", 128, 16 },
186 { 0x11, "SAML21J16B", 64, 8 },
187 { 0x14, "SAML21G18B", 256, 32 },
188 { 0x15, "SAML21G17B", 128, 16 },
189 { 0x16, "SAML21G16B", 64, 8 },
190 { 0x19, "SAML21E18B", 256, 32 },
191 { 0x1A, "SAML21E17B", 128, 16 },
192 { 0x1B, "SAML21E16B", 64, 8 },
193 { 0x1C, "SAML21E15B", 32, 4 },
194 };
195
196 /* Known SAML22 parts. */
197 static const struct samd_part saml22_parts[] = {
198 { 0x00, "SAML22N18A", 256, 32 },
199 { 0x01, "SAML22N17A", 128, 16 },
200 { 0x02, "SAML22N16A", 64, 8 },
201 { 0x05, "SAML22J18A", 256, 32 },
202 { 0x06, "SAML22J17A", 128, 16 },
203 { 0x07, "SAML22J16A", 64, 8 },
204 { 0x0A, "SAML22G18A", 256, 32 },
205 { 0x0B, "SAML22G17A", 128, 16 },
206 { 0x0C, "SAML22G16A", 64, 8 },
207 };
208
209 /* Known SAMC20 parts. */
210 static const struct samd_part samc20_parts[] = {
211 { 0x00, "SAMC20J18A", 256, 32 },
212 { 0x01, "SAMC20J17A", 128, 16 },
213 { 0x02, "SAMC20J16A", 64, 8 },
214 { 0x03, "SAMC20J15A", 32, 4 },
215 { 0x05, "SAMC20G18A", 256, 32 },
216 { 0x06, "SAMC20G17A", 128, 16 },
217 { 0x07, "SAMC20G16A", 64, 8 },
218 { 0x08, "SAMC20G15A", 32, 4 },
219 { 0x0A, "SAMC20E18A", 256, 32 },
220 { 0x0B, "SAMC20E17A", 128, 16 },
221 { 0x0C, "SAMC20E16A", 64, 8 },
222 { 0x0D, "SAMC20E15A", 32, 4 },
223 };
224
225 /* Known SAMC21 parts. */
226 static const struct samd_part samc21_parts[] = {
227 { 0x00, "SAMC21J18A", 256, 32 },
228 { 0x01, "SAMC21J17A", 128, 16 },
229 { 0x02, "SAMC21J16A", 64, 8 },
230 { 0x03, "SAMC21J15A", 32, 4 },
231 { 0x05, "SAMC21G18A", 256, 32 },
232 { 0x06, "SAMC21G17A", 128, 16 },
233 { 0x07, "SAMC21G16A", 64, 8 },
234 { 0x08, "SAMC21G15A", 32, 4 },
235 { 0x0A, "SAMC21E18A", 256, 32 },
236 { 0x0B, "SAMC21E17A", 128, 16 },
237 { 0x0C, "SAMC21E16A", 64, 8 },
238 { 0x0D, "SAMC21E15A", 32, 4 },
239 };
240
241 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
242 * processor ID, family ID, and series ID are used to determine which exact
243 * family this is and then we can use the corresponding table. */
244 struct samd_family {
245 uint8_t processor;
246 uint8_t family;
247 uint8_t series;
248 const struct samd_part *parts;
249 size_t num_parts;
250 };
251
252 /* Known SAMD families */
253 static const struct samd_family samd_families[] = {
254 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
255 samd20_parts, ARRAY_SIZE(samd20_parts) },
256 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
257 samd21_parts, ARRAY_SIZE(samd21_parts) },
258 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
259 samr21_parts, ARRAY_SIZE(samr21_parts) },
260 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
261 samd10_parts, ARRAY_SIZE(samd10_parts) },
262 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
263 samd11_parts, ARRAY_SIZE(samd11_parts) },
264 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
265 saml21_parts, ARRAY_SIZE(saml21_parts) },
266 { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
267 saml22_parts, ARRAY_SIZE(saml22_parts) },
268 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
269 samc20_parts, ARRAY_SIZE(samc20_parts) },
270 { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
271 samc21_parts, ARRAY_SIZE(samc21_parts) },
272 };
273
274 struct samd_info {
275 uint32_t page_size;
276 int num_pages;
277 int sector_size;
278
279 bool probed;
280 struct target *target;
281 struct samd_info *next;
282 };
283
284 static struct samd_info *samd_chips;
285
286
287
288 static const struct samd_part *samd_find_part(uint32_t id)
289 {
290 uint8_t processor = SAMD_GET_PROCESSOR(id);
291 uint8_t family = SAMD_GET_FAMILY(id);
292 uint8_t series = SAMD_GET_SERIES(id);
293 uint8_t devsel = SAMD_GET_DEVSEL(id);
294
295 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
296 if (samd_families[i].processor == processor &&
297 samd_families[i].series == series &&
298 samd_families[i].family == family) {
299 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
300 if (samd_families[i].parts[j].id == devsel)
301 return &samd_families[i].parts[j];
302 }
303 }
304 }
305
306 return NULL;
307 }
308
309 static int samd_protect_check(struct flash_bank *bank)
310 {
311 int res;
312 uint16_t lock;
313
314 res = target_read_u16(bank->target,
315 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
316 if (res != ERROR_OK)
317 return res;
318
319 /* Lock bits are active-low */
320 for (int i = 0; i < bank->num_sectors; i++)
321 bank->sectors[i].is_protected = !(lock & (1<<i));
322
323 return ERROR_OK;
324 }
325
326 static int samd_get_flash_page_info(struct target *target,
327 uint32_t *sizep, int *nump)
328 {
329 int res;
330 uint32_t param;
331
332 res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, &param);
333 if (res == ERROR_OK) {
334 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
335 * so 0 is 8KB and 7 is 1024KB. */
336 if (sizep)
337 *sizep = (8 << ((param >> 16) & 0x7));
338 /* The NVMP field (bits 15:0) indicates the total number of pages */
339 if (nump)
340 *nump = param & 0xFFFF;
341 } else {
342 LOG_ERROR("Couldn't read NVM Parameters register");
343 }
344
345 return res;
346 }
347
348 static int samd_probe(struct flash_bank *bank)
349 {
350 uint32_t id;
351 int res;
352 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
353 const struct samd_part *part;
354
355 if (chip->probed)
356 return ERROR_OK;
357
358 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
359 if (res != ERROR_OK) {
360 LOG_ERROR("Couldn't read Device ID register");
361 return res;
362 }
363
364 part = samd_find_part(id);
365 if (part == NULL) {
366 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
367 return ERROR_FAIL;
368 }
369
370 bank->size = part->flash_kb * 1024;
371
372 chip->sector_size = bank->size / SAMD_NUM_SECTORS;
373
374 res = samd_get_flash_page_info(bank->target, &chip->page_size,
375 &chip->num_pages);
376 if (res != ERROR_OK) {
377 LOG_ERROR("Couldn't determine Flash page size");
378 return res;
379 }
380
381 /* Sanity check: the total flash size in the DSU should match the page size
382 * multiplied by the number of pages. */
383 if (bank->size != chip->num_pages * chip->page_size) {
384 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
385 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
386 part->flash_kb, chip->num_pages, chip->page_size);
387 }
388
389 /* Allocate the sector table */
390 bank->num_sectors = SAMD_NUM_SECTORS;
391 bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
392 if (!bank->sectors)
393 return ERROR_FAIL;
394
395 /* Fill out the sector information: all SAMD sectors are the same size and
396 * there is always a fixed number of them. */
397 for (int i = 0; i < bank->num_sectors; i++) {
398 bank->sectors[i].size = chip->sector_size;
399 bank->sectors[i].offset = i * chip->sector_size;
400 /* mark as unknown */
401 bank->sectors[i].is_erased = -1;
402 bank->sectors[i].is_protected = -1;
403 }
404
405 samd_protect_check(bank);
406
407 /* Done */
408 chip->probed = true;
409
410 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
411 part->flash_kb, part->ram_kb);
412
413 return ERROR_OK;
414 }
415
416 static bool samd_check_error(struct target *target)
417 {
418 int ret;
419 bool error;
420 uint16_t status;
421
422 ret = target_read_u16(target,
423 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
424 if (ret != ERROR_OK) {
425 LOG_ERROR("Can't read NVM status");
426 return true;
427 }
428
429 if (status & 0x001C) {
430 if (status & (1 << 4)) /* NVME */
431 LOG_ERROR("SAMD: NVM Error");
432 if (status & (1 << 3)) /* LOCKE */
433 LOG_ERROR("SAMD: NVM lock error");
434 if (status & (1 << 2)) /* PROGE */
435 LOG_ERROR("SAMD: NVM programming error");
436
437 error = true;
438 } else {
439 error = false;
440 }
441
442 /* Clear the error conditions by writing a one to them */
443 ret = target_write_u16(target,
444 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
445 if (ret != ERROR_OK)
446 LOG_ERROR("Can't clear NVM error conditions");
447
448 return error;
449 }
450
451 static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
452 {
453 int res;
454
455 if (target->state != TARGET_HALTED) {
456 LOG_ERROR("Target not halted");
457 return ERROR_TARGET_NOT_HALTED;
458 }
459
460 /* Issue the NVM command */
461 res = target_write_u16(target,
462 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
463 if (res != ERROR_OK)
464 return res;
465
466 /* Check to see if the NVM command resulted in an error condition. */
467 if (samd_check_error(target))
468 return ERROR_FAIL;
469
470 return ERROR_OK;
471 }
472
473 static int samd_erase_row(struct target *target, uint32_t address)
474 {
475 int res;
476
477 /* Set an address contained in the row to be erased */
478 res = target_write_u32(target,
479 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
480
481 /* Issue the Erase Row command to erase that row. */
482 if (res == ERROR_OK)
483 res = samd_issue_nvmctrl_command(target,
484 address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
485
486 if (res != ERROR_OK) {
487 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
488 return ERROR_FAIL;
489 }
490
491 return ERROR_OK;
492 }
493
494 static bool is_user_row_reserved_bit(uint8_t bit)
495 {
496 /* See Table 9-3 in the SAMD20 datasheet for more information. */
497 switch (bit) {
498 /* Reserved bits */
499 case 3:
500 case 7:
501 /* Voltage regulator internal configuration with default value of 0x70,
502 * may not be changed. */
503 case 17 ... 24:
504 /* 41 is voltage regulator internal configuration and must not be
505 * changed. 42 through 47 are reserved. */
506 case 41 ... 47:
507 return true;
508 default:
509 break;
510 }
511
512 return false;
513 }
514
515 /* Modify the contents of the User Row in Flash. These are described in Table
516 * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
517 * and contains a combination of "fuses" and calibration data in bits 24:17.
518 * We therefore try not to erase the row's contents unless we absolutely have
519 * to and we don't permit modifying reserved bits. */
520 static int samd_modify_user_row(struct target *target, uint32_t value,
521 uint8_t startb, uint8_t endb)
522 {
523 int res;
524
525 if (is_user_row_reserved_bit(startb) || is_user_row_reserved_bit(endb)) {
526 LOG_ERROR("Can't modify bits in the requested range");
527 return ERROR_FAIL;
528 }
529
530 /* Retrieve the MCU's page size, in bytes. This is also the size of the
531 * entire User Row. */
532 uint32_t page_size;
533 res = samd_get_flash_page_info(target, &page_size, NULL);
534 if (res != ERROR_OK) {
535 LOG_ERROR("Couldn't determine Flash page size");
536 return res;
537 }
538
539 /* Make sure the size is sane before we allocate. */
540 assert(page_size > 0 && page_size <= SAMD_PAGE_SIZE_MAX);
541
542 /* Make sure we're within the single page that comprises the User Row. */
543 if (startb >= (page_size * 8) || endb >= (page_size * 8)) {
544 LOG_ERROR("Can't modify bits outside the User Row page range");
545 return ERROR_FAIL;
546 }
547
548 uint8_t *buf = malloc(page_size);
549 if (!buf)
550 return ERROR_FAIL;
551
552 /* Read the user row (comprising one page) by half-words. */
553 res = target_read_memory(target, SAMD_USER_ROW, 2, page_size / 2, buf);
554 if (res != ERROR_OK)
555 goto out_user_row;
556
557 /* We will need to erase before writing if the new value needs a '1' in any
558 * position for which the current value had a '0'. Otherwise we can avoid
559 * erasing. */
560 uint32_t cur = buf_get_u32(buf, startb, endb - startb + 1);
561 if ((~cur) & value) {
562 res = samd_erase_row(target, SAMD_USER_ROW);
563 if (res != ERROR_OK) {
564 LOG_ERROR("Couldn't erase user row");
565 goto out_user_row;
566 }
567 }
568
569 /* Modify */
570 buf_set_u32(buf, startb, endb - startb + 1, value);
571
572 /* Write the page buffer back out to the target. A Flash write will be
573 * triggered automatically. */
574 res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
575 if (res != ERROR_OK)
576 goto out_user_row;
577
578 if (samd_check_error(target)) {
579 res = ERROR_FAIL;
580 goto out_user_row;
581 }
582
583 /* Success */
584 res = ERROR_OK;
585
586 out_user_row:
587 free(buf);
588
589 return res;
590 }
591
592 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
593 {
594 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
595
596 /* We can issue lock/unlock region commands with the target running but
597 * the settings won't persist unless we're able to modify the LOCK regions
598 * and that requires the target to be halted. */
599 if (bank->target->state != TARGET_HALTED) {
600 LOG_ERROR("Target not halted");
601 return ERROR_TARGET_NOT_HALTED;
602 }
603
604 int res = ERROR_OK;
605
606 for (int s = first; s <= last; s++) {
607 if (set != bank->sectors[s].is_protected) {
608 /* Load an address that is within this sector (we use offset 0) */
609 res = target_write_u32(bank->target,
610 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
611 ((s * chip->sector_size) >> 1));
612 if (res != ERROR_OK)
613 goto exit;
614
615 /* Tell the controller to lock that sector */
616 res = samd_issue_nvmctrl_command(bank->target,
617 set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
618 if (res != ERROR_OK)
619 goto exit;
620 }
621 }
622
623 /* We've now applied our changes, however they will be undone by the next
624 * reset unless we also apply them to the LOCK bits in the User Page. The
625 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
626 * corresponding to Sector 15. A '1' means unlocked and a '0' means
627 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
628
629 res = samd_modify_user_row(bank->target, set ? 0x0000 : 0xFFFF,
630 48 + first, 48 + last);
631 if (res != ERROR_OK)
632 LOG_WARNING("SAMD: protect settings were not made persistent!");
633
634 res = ERROR_OK;
635
636 exit:
637 samd_protect_check(bank);
638
639 return res;
640 }
641
642 static int samd_erase(struct flash_bank *bank, int first, int last)
643 {
644 int res;
645 int rows_in_sector;
646 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
647
648 if (bank->target->state != TARGET_HALTED) {
649 LOG_ERROR("Target not halted");
650
651 return ERROR_TARGET_NOT_HALTED;
652 }
653
654 if (!chip->probed) {
655 if (samd_probe(bank) != ERROR_OK)
656 return ERROR_FLASH_BANK_NOT_PROBED;
657 }
658
659 /* The SAMD NVM has row erase granularity. There are four pages in a row
660 * and the number of rows in a sector depends on the sector size, which in
661 * turn depends on the Flash capacity as there is a fixed number of
662 * sectors. */
663 rows_in_sector = chip->sector_size / (chip->page_size * 4);
664
665 /* For each sector to be erased */
666 for (int s = first; s <= last; s++) {
667 if (bank->sectors[s].is_protected) {
668 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
669 return ERROR_FLASH_OPERATION_FAILED;
670 }
671
672 /* For each row in that sector */
673 for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
674 res = samd_erase_row(bank->target, r * chip->page_size * 4);
675 if (res != ERROR_OK) {
676 LOG_ERROR("SAMD: failed to erase sector %d", s);
677 return res;
678 }
679 }
680 }
681
682 return ERROR_OK;
683 }
684
685
686 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
687 uint32_t offset, uint32_t count)
688 {
689 int res;
690 uint32_t nvm_ctrlb;
691 uint32_t address;
692 uint32_t pg_offset;
693 uint32_t nb;
694 uint32_t nw;
695 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
696 uint8_t *pb = NULL;
697 bool manual_wp;
698
699 if (bank->target->state != TARGET_HALTED) {
700 LOG_ERROR("Target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (!chip->probed) {
705 if (samd_probe(bank) != ERROR_OK)
706 return ERROR_FLASH_BANK_NOT_PROBED;
707 }
708
709 /* Check if we need to do manual page write commands */
710 res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
711
712 if (res != ERROR_OK)
713 return res;
714
715 if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
716 manual_wp = true;
717 else
718 manual_wp = false;
719
720 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
721 if (res != ERROR_OK) {
722 LOG_ERROR("%s: %d", __func__, __LINE__);
723 return res;
724 }
725
726 while (count) {
727 nb = chip->page_size - offset % chip->page_size;
728 if (count < nb)
729 nb = count;
730
731 address = bank->base + offset;
732 pg_offset = offset % chip->page_size;
733
734 if (offset % 4 || (offset + nb) % 4) {
735 /* Either start or end of write is not word aligned */
736 if (!pb) {
737 pb = malloc(chip->page_size);
738 if (!pb)
739 return ERROR_FAIL;
740 }
741
742 /* Set temporary page buffer to 0xff and overwrite the relevant part */
743 memset(pb, 0xff, chip->page_size);
744 memcpy(pb + pg_offset, buffer, nb);
745
746 /* Align start address to a word boundary */
747 address -= offset % 4;
748 pg_offset -= offset % 4;
749 assert(pg_offset % 4 == 0);
750
751 /* Extend length to whole words */
752 nw = (nb + offset % 4 + 3) / 4;
753 assert(pg_offset + 4 * nw <= chip->page_size);
754
755 /* Now we have original data extended by 0xff bytes
756 * to the nearest word boundary on both start and end */
757 res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
758 } else {
759 assert(nb % 4 == 0);
760 nw = nb / 4;
761 assert(pg_offset + 4 * nw <= chip->page_size);
762
763 /* Word aligned data, use direct write from buffer */
764 res = target_write_memory(bank->target, address, 4, nw, buffer);
765 }
766 if (res != ERROR_OK) {
767 LOG_ERROR("%s: %d", __func__, __LINE__);
768 goto free_pb;
769 }
770
771 /* Devices with errata 13134 have automatic page write enabled by default
772 * For other devices issue a write page CMD to the NVM
773 * If the page has not been written up to the last word
774 * then issue CMD_WP always */
775 if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
776 res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
777 if (res != ERROR_OK) {
778 LOG_ERROR("%s: %d", __func__, __LINE__);
779 goto free_pb;
780 }
781 }
782
783 /* Access through AHB is stalled while flash is being programmed */
784 usleep(200);
785
786 if (samd_check_error(bank->target)) {
787 LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
788 res = ERROR_FAIL;
789 goto free_pb;
790 }
791
792 /* We're done with the page contents */
793 count -= nb;
794 offset += nb;
795 buffer += nb;
796 }
797
798 free_pb:
799 if (pb)
800 free(pb);
801
802 return res;
803 }
804
805 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
806 {
807 struct samd_info *chip = samd_chips;
808
809 while (chip) {
810 if (chip->target == bank->target)
811 break;
812 chip = chip->next;
813 }
814
815 if (!chip) {
816 /* Create a new chip */
817 chip = calloc(1, sizeof(*chip));
818 if (!chip)
819 return ERROR_FAIL;
820
821 chip->target = bank->target;
822 chip->probed = false;
823
824 bank->driver_priv = chip;
825
826 /* Insert it into the chips list (at head) */
827 chip->next = samd_chips;
828 samd_chips = chip;
829 }
830
831 if (bank->base != SAMD_FLASH) {
832 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
833 "[at91samd series] )",
834 bank->base, SAMD_FLASH);
835 return ERROR_FAIL;
836 }
837
838 return ERROR_OK;
839 }
840
841 COMMAND_HANDLER(samd_handle_info_command)
842 {
843 return ERROR_OK;
844 }
845
846 COMMAND_HANDLER(samd_handle_chip_erase_command)
847 {
848 struct target *target = get_current_target(CMD_CTX);
849
850 if (target) {
851 /* Enable access to the DSU by disabling the write protect bit */
852 target_write_u32(target, SAMD_PAC1, (1<<1));
853 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
854 * perform the erase. */
855 target_write_u8(target, SAMD_DSU, (1<<4));
856
857 command_print(CMD_CTX, "chip erased");
858 }
859
860 return ERROR_OK;
861 }
862
863 COMMAND_HANDLER(samd_handle_set_security_command)
864 {
865 int res = ERROR_OK;
866 struct target *target = get_current_target(CMD_CTX);
867
868 if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
869 command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
870 return ERROR_COMMAND_SYNTAX_ERROR;
871 }
872
873 if (target) {
874 if (target->state != TARGET_HALTED) {
875 LOG_ERROR("Target not halted");
876 return ERROR_TARGET_NOT_HALTED;
877 }
878
879 res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
880
881 /* Check (and clear) error conditions */
882 if (res == ERROR_OK)
883 command_print(CMD_CTX, "chip secured on next power-cycle");
884 else
885 command_print(CMD_CTX, "failed to secure chip");
886 }
887
888 return res;
889 }
890
891 COMMAND_HANDLER(samd_handle_eeprom_command)
892 {
893 int res = ERROR_OK;
894 struct target *target = get_current_target(CMD_CTX);
895
896 if (target) {
897 if (target->state != TARGET_HALTED) {
898 LOG_ERROR("Target not halted");
899 return ERROR_TARGET_NOT_HALTED;
900 }
901
902 if (CMD_ARGC >= 1) {
903 int val = atoi(CMD_ARGV[0]);
904 uint32_t code;
905
906 if (val == 0)
907 code = 7;
908 else {
909 /* Try to match size in bytes with corresponding size code */
910 for (code = 0; code <= 6; code++) {
911 if (val == (2 << (13 - code)))
912 break;
913 }
914
915 if (code > 6) {
916 command_print(CMD_CTX, "Invalid EEPROM size. Please see "
917 "datasheet for a list valid sizes.");
918 return ERROR_COMMAND_SYNTAX_ERROR;
919 }
920 }
921
922 res = samd_modify_user_row(target, code, 4, 6);
923 } else {
924 uint16_t val;
925 res = target_read_u16(target, SAMD_USER_ROW, &val);
926 if (res == ERROR_OK) {
927 uint32_t size = ((val >> 4) & 0x7); /* grab size code */
928
929 if (size == 0x7)
930 command_print(CMD_CTX, "EEPROM is disabled");
931 else {
932 /* Otherwise, 6 is 256B, 0 is 16KB */
933 command_print(CMD_CTX, "EEPROM size is %u bytes",
934 (2 << (13 - size)));
935 }
936 }
937 }
938 }
939
940 return res;
941 }
942
943 COMMAND_HANDLER(samd_handle_bootloader_command)
944 {
945 int res = ERROR_OK;
946 struct target *target = get_current_target(CMD_CTX);
947
948 if (target) {
949 if (target->state != TARGET_HALTED) {
950 LOG_ERROR("Target not halted");
951 return ERROR_TARGET_NOT_HALTED;
952 }
953
954 /* Retrieve the MCU's page size, in bytes. */
955 uint32_t page_size;
956 res = samd_get_flash_page_info(target, &page_size, NULL);
957 if (res != ERROR_OK) {
958 LOG_ERROR("Couldn't determine Flash page size");
959 return res;
960 }
961
962 if (CMD_ARGC >= 1) {
963 int val = atoi(CMD_ARGV[0]);
964 uint32_t code;
965
966 if (val == 0)
967 code = 7;
968 else {
969 /* Try to match size in bytes with corresponding size code */
970 for (code = 0; code <= 6; code++) {
971 if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
972 break;
973 }
974
975 if (code > 6) {
976 command_print(CMD_CTX, "Invalid bootloader size. Please "
977 "see datasheet for a list valid sizes.");
978 return ERROR_COMMAND_SYNTAX_ERROR;
979 }
980
981 }
982
983 res = samd_modify_user_row(target, code, 0, 2);
984 } else {
985 uint16_t val;
986 res = target_read_u16(target, SAMD_USER_ROW, &val);
987 if (res == ERROR_OK) {
988 uint32_t size = (val & 0x7); /* grab size code */
989 uint32_t nb;
990
991 if (size == 0x7)
992 nb = 0;
993 else
994 nb = (2 << (8 - size)) * page_size;
995
996 /* There are 4 pages per row */
997 command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
998 nb, (uint32_t)(nb / (page_size * 4)));
999 }
1000 }
1001 }
1002
1003 return res;
1004 }
1005
1006
1007
1008 COMMAND_HANDLER(samd_handle_reset_deassert)
1009 {
1010 struct target *target = get_current_target(CMD_CTX);
1011 struct armv7m_common *armv7m = target_to_armv7m(target);
1012 int retval = ERROR_OK;
1013 enum reset_types jtag_reset_config = jtag_get_reset_config();
1014
1015 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1016 * so we just release reset held by DSU
1017 *
1018 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1019 *
1020 * After vectreset DSU release is not needed however makes no harm
1021 */
1022 if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
1023 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
1024 if (retval == ERROR_OK)
1025 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
1026 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1027 /* do not return on error here, releasing DSU reset is more important */
1028 }
1029
1030 /* clear CPU Reset Phase Extension bit */
1031 int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
1032 if (retval2 != ERROR_OK)
1033 return retval2;
1034
1035 return retval;
1036 }
1037
1038 static const struct command_registration at91samd_exec_command_handlers[] = {
1039 {
1040 .name = "dsu_reset_deassert",
1041 .handler = samd_handle_reset_deassert,
1042 .mode = COMMAND_EXEC,
1043 .help = "deasert internal reset held by DSU"
1044 },
1045 {
1046 .name = "info",
1047 .handler = samd_handle_info_command,
1048 .mode = COMMAND_EXEC,
1049 .help = "Print information about the current at91samd chip"
1050 "and its flash configuration.",
1051 },
1052 {
1053 .name = "chip-erase",
1054 .handler = samd_handle_chip_erase_command,
1055 .mode = COMMAND_EXEC,
1056 .help = "Erase the entire Flash by using the Chip"
1057 "Erase feature in the Device Service Unit (DSU).",
1058 },
1059 {
1060 .name = "set-security",
1061 .handler = samd_handle_set_security_command,
1062 .mode = COMMAND_EXEC,
1063 .help = "Secure the chip's Flash by setting the Security Bit."
1064 "This makes it impossible to read the Flash contents."
1065 "The only way to undo this is to issue the chip-erase"
1066 "command.",
1067 },
1068 {
1069 .name = "eeprom",
1070 .usage = "[size_in_bytes]",
1071 .handler = samd_handle_eeprom_command,
1072 .mode = COMMAND_EXEC,
1073 .help = "Show or set the EEPROM size setting, stored in the User Row."
1074 "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
1075 "Changes are stored immediately but take affect after the MCU is"
1076 "reset.",
1077 },
1078 {
1079 .name = "bootloader",
1080 .usage = "[size_in_bytes]",
1081 .handler = samd_handle_bootloader_command,
1082 .mode = COMMAND_EXEC,
1083 .help = "Show or set the bootloader size, stored in the User Row."
1084 "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
1085 "Changes are stored immediately but take affect after the MCU is"
1086 "reset.",
1087 },
1088 COMMAND_REGISTRATION_DONE
1089 };
1090
1091 static const struct command_registration at91samd_command_handlers[] = {
1092 {
1093 .name = "at91samd",
1094 .mode = COMMAND_ANY,
1095 .help = "at91samd flash command group",
1096 .usage = "",
1097 .chain = at91samd_exec_command_handlers,
1098 },
1099 COMMAND_REGISTRATION_DONE
1100 };
1101
1102 struct flash_driver at91samd_flash = {
1103 .name = "at91samd",
1104 .commands = at91samd_command_handlers,
1105 .flash_bank_command = samd_flash_bank_command,
1106 .erase = samd_erase,
1107 .protect = samd_protect,
1108 .write = samd_write,
1109 .read = default_flash_read,
1110 .probe = samd_probe,
1111 .auto_probe = samd_probe,
1112 .erase_check = default_flash_blank_check,
1113 .protect_check = samd_protect_check,
1114 };
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