1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include <helper/binarybuffer.h>
25 #include <target/algorithm.h>
26 #include <target/armv7m.h>
28 /* STM32L4xxx series for reference.
30 * RM0351 (STM32L4x5/STM32L4x6)
31 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
33 * RM0394 (STM32L43x/44x/45x/46x)
34 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
36 * STM32L476RG Datasheet (for erase timing)
37 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
39 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
40 * an option byte is available to map all sectors to the first bank.
41 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
44 * RM0394 devices have a single bank only.
48 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
50 #define FLASH_ERASE_TIMEOUT 250
52 #define STM32_FLASH_BASE 0x40022000
53 #define STM32_FLASH_ACR 0x40022000
54 #define STM32_FLASH_KEYR 0x40022008
55 #define STM32_FLASH_OPTKEYR 0x4002200c
56 #define STM32_FLASH_SR 0x40022010
57 #define STM32_FLASH_CR 0x40022014
58 #define STM32_FLASH_OPTR 0x40022020
59 #define STM32_FLASH_WRP1AR 0x4002202c
60 #define STM32_FLASH_WRP2AR 0x40022030
61 #define STM32_FLASH_WRP1BR 0x4002204c
62 #define STM32_FLASH_WRP2BR 0x40022050
64 /* FLASH_CR register bits */
66 #define FLASH_PG (1 << 0)
67 #define FLASH_PER (1 << 1)
68 #define FLASH_MER1 (1 << 2)
69 #define FLASH_PAGE_SHIFT 3
70 #define FLASH_CR_BKER (1 << 11)
71 #define FLASH_MER2 (1 << 15)
72 #define FLASH_STRT (1 << 16)
73 #define FLASH_EOPIE (1 << 24)
74 #define FLASH_ERRIE (1 << 25)
75 #define FLASH_OPTLOCK (1 << 30)
76 #define FLASH_LOCK (1 << 31)
78 /* FLASH_SR register bits */
80 #define FLASH_BSY (1 << 16)
81 /* Fast programming not used => related errors not used*/
82 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
83 #define FLASH_SIZERR (1 << 6) /* Size error */
84 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
85 #define FLASH_WRPERR (1 << 4) /* Write protection error */
86 #define FLASH_PROGERR (1 << 3) /* Programming error */
87 #define FLASH_OPERR (1 << 1) /* Operation error */
88 #define FLASH_EOP (1 << 0) /* End of operation */
90 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
92 /* STM32_FLASH_OBR bit definitions (reading) */
94 #define OPT_DUALBANK 21 /* dual flash bank only */
96 /* register unlock keys */
98 #define KEY1 0x45670123
99 #define KEY2 0xCDEF89AB
101 /* option register unlock key */
102 #define OPTKEY1 0x08192A3B
103 #define OPTKEY2 0x4C5D6E7F
106 /* other registers */
107 #define DBGMCU_IDCODE 0xE0042000
108 #define FLASH_SIZE_REG 0x1FFF75E0
110 struct stm32l4_options
{
112 uint16_t bank_b_start
;
113 uint8_t user_options
;
122 /* Fixme: Handle PCROP */
125 struct stm32l4_flash_bank
{
126 struct stm32l4_options option_bytes
;
130 /* flash bank stm32l4x <base> <size> 0 0 <target#>
132 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
134 struct stm32l4_flash_bank
*stm32l4_info
;
137 return ERROR_COMMAND_SYNTAX_ERROR
;
139 stm32l4_info
= malloc(sizeof(struct stm32l4_flash_bank
));
141 return ERROR_FAIL
; /* Checkme: What better error to use?*/
142 bank
->driver_priv
= stm32l4_info
;
144 stm32l4_info
->probed
= 0;
149 static inline int stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
154 static inline int stm32l4_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
156 struct target
*target
= bank
->target
;
157 return target_read_u32(
158 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
161 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
163 struct target
*target
= bank
->target
;
165 int retval
= ERROR_OK
;
167 /* wait for busy to clear */
169 retval
= stm32l4_get_flash_status(bank
, &status
);
170 if (retval
!= ERROR_OK
)
172 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
173 if ((status
& FLASH_BSY
) == 0)
175 if (timeout
-- <= 0) {
176 LOG_ERROR("timed out waiting for flash");
183 if (status
& FLASH_WRPERR
) {
184 LOG_ERROR("stm32x device protected");
188 /* Clear but report errors */
189 if (status
& FLASH_ERROR
) {
190 /* If this operation fails, we ignore it and report the original
193 target_write_u32(target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_SR
),
194 status
& FLASH_ERROR
);
199 static int stm32l4_unlock_reg(struct target
*target
)
203 /* first check if not already unlocked
204 * otherwise writing on STM32_FLASH_KEYR will fail
206 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
207 if (retval
!= ERROR_OK
)
210 if ((ctrl
& FLASH_LOCK
) == 0)
213 /* unlock flash registers */
214 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
215 if (retval
!= ERROR_OK
)
218 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
219 if (retval
!= ERROR_OK
)
222 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
223 if (retval
!= ERROR_OK
)
226 if (ctrl
& FLASH_LOCK
) {
227 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
228 return ERROR_TARGET_FAILURE
;
234 static int stm32l4_unlock_option_reg(struct target
*target
)
238 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
239 if (retval
!= ERROR_OK
)
242 if ((ctrl
& FLASH_OPTLOCK
) == 0)
245 /* unlock option registers */
246 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
247 if (retval
!= ERROR_OK
)
250 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
251 if (retval
!= ERROR_OK
)
254 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
255 if (retval
!= ERROR_OK
)
258 if (ctrl
& FLASH_OPTLOCK
) {
259 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
260 return ERROR_TARGET_FAILURE
;
266 static int stm32l4_read_options(struct flash_bank
*bank
)
269 struct stm32l4_flash_bank
*stm32l4_info
= NULL
;
270 struct target
*target
= bank
->target
;
272 stm32l4_info
= bank
->driver_priv
;
274 /* read current option bytes */
275 int retval
= target_read_u32(target
, STM32_FLASH_OPTR
, &optiondata
);
276 if (retval
!= ERROR_OK
)
279 stm32l4_info
->option_bytes
.user_options
= (optiondata
>> 8) & 0x3ffff;
280 stm32l4_info
->option_bytes
.RDP
= optiondata
& 0xff;
282 retval
= target_read_u32(target
, STM32_FLASH_WRP1AR
, &optiondata
);
283 if (retval
!= ERROR_OK
)
285 stm32l4_info
->option_bytes
.wpr1a_start
= optiondata
& 0xff;
286 stm32l4_info
->option_bytes
.wpr1a_end
= (optiondata
>> 16) & 0xff;
288 retval
= target_read_u32(target
, STM32_FLASH_WRP2AR
, &optiondata
);
289 if (retval
!= ERROR_OK
)
291 stm32l4_info
->option_bytes
.wpr2a_start
= optiondata
& 0xff;
292 stm32l4_info
->option_bytes
.wpr2a_end
= (optiondata
>> 16) & 0xff;
294 retval
= target_read_u32(target
, STM32_FLASH_WRP1BR
, &optiondata
);
295 if (retval
!= ERROR_OK
)
297 stm32l4_info
->option_bytes
.wpr1b_start
= optiondata
& 0xff;
298 stm32l4_info
->option_bytes
.wpr1b_end
= (optiondata
>> 16) & 0xff;
300 retval
= target_read_u32(target
, STM32_FLASH_WRP2BR
, &optiondata
);
301 if (retval
!= ERROR_OK
)
303 stm32l4_info
->option_bytes
.wpr2b_start
= optiondata
& 0xff;
304 stm32l4_info
->option_bytes
.wpr2b_end
= (optiondata
>> 16) & 0xff;
306 if (stm32l4_info
->option_bytes
.RDP
!= 0xAA)
307 LOG_INFO("Device Security Bit Set");
312 static int stm32l4_write_options(struct flash_bank
*bank
)
314 struct stm32l4_flash_bank
*stm32l4_info
= NULL
;
315 struct target
*target
= bank
->target
;
318 stm32l4_info
= bank
->driver_priv
;
323 int retval
= stm32l4_unlock_option_reg(target
);
324 if (retval
!= ERROR_OK
)
326 /* FIXME: Implement Option writing!*/
330 static int stm32l4_protect_check(struct flash_bank
*bank
)
332 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
334 /* read write protection settings */
335 int retval
= stm32l4_read_options(bank
);
336 if (retval
!= ERROR_OK
) {
337 LOG_DEBUG("unable to read option bytes");
341 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
342 if (i
< stm32l4_info
->option_bytes
.bank_b_start
) {
343 if (((i
>= stm32l4_info
->option_bytes
.wpr1a_start
) &&
344 (i
<= stm32l4_info
->option_bytes
.wpr1a_end
)) ||
345 ((i
>= stm32l4_info
->option_bytes
.wpr2a_start
) &&
346 (i
<= stm32l4_info
->option_bytes
.wpr2a_end
)))
347 bank
->sectors
[i
].is_protected
= 1;
349 bank
->sectors
[i
].is_protected
= 0;
352 snb
= i
- stm32l4_info
->option_bytes
.bank_b_start
+ 256;
353 if (((snb
>= stm32l4_info
->option_bytes
.wpr1b_start
) &&
354 (snb
<= stm32l4_info
->option_bytes
.wpr1b_end
)) ||
355 ((snb
>= stm32l4_info
->option_bytes
.wpr2b_start
) &&
356 (snb
<= stm32l4_info
->option_bytes
.wpr2b_end
)))
357 bank
->sectors
[i
].is_protected
= 1;
359 bank
->sectors
[i
].is_protected
= 0;
365 static int stm32l4_erase(struct flash_bank
*bank
, int first
, int last
)
367 struct target
*target
= bank
->target
;
370 assert(first
< bank
->num_sectors
);
371 assert(last
< bank
->num_sectors
);
373 if (bank
->target
->state
!= TARGET_HALTED
) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED
;
379 retval
= stm32l4_unlock_reg(target
);
380 if (retval
!= ERROR_OK
)
385 To erase a sector, follow the procedure below:
386 1. Check that no Flash memory operation is ongoing by
387 checking the BSY bit in the FLASH_SR register
388 2. Set the PER bit and select the page and bank
389 you wish to erase in the FLASH_CR register
390 3. Set the STRT bit in the FLASH_CR register
391 4. Wait for the BSY bit to be cleared
393 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
395 for (i
= first
; i
<= last
; i
++) {
396 uint32_t erase_flags
;
397 erase_flags
= FLASH_PER
| FLASH_STRT
;
399 if (i
>= stm32l4_info
->option_bytes
.bank_b_start
) {
401 snb
= (i
- stm32l4_info
->option_bytes
.bank_b_start
) + 256;
402 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
404 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
405 retval
= target_write_u32(target
,
406 stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), erase_flags
);
407 if (retval
!= ERROR_OK
)
410 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
411 if (retval
!= ERROR_OK
)
414 bank
->sectors
[i
].is_erased
= 1;
417 retval
= target_write_u32(
418 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
419 if (retval
!= ERROR_OK
)
425 static int stm32l4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
427 struct target
*target
= bank
->target
;
428 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
430 if (target
->state
!= TARGET_HALTED
) {
431 LOG_ERROR("Target not halted");
432 return ERROR_TARGET_NOT_HALTED
;
435 /* read protection settings */
436 int retval
= stm32l4_read_options(bank
);
437 if (retval
!= ERROR_OK
) {
438 LOG_DEBUG("unable to read option bytes");
443 /* FIXME: Write First and last in a valid WRPxx_start/end combo*/
444 retval
= stm32l4_write_options(bank
);
445 if (retval
!= ERROR_OK
)
451 /* Count is in halfwords */
452 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
453 uint32_t offset
, uint32_t count
)
455 struct target
*target
= bank
->target
;
456 uint32_t buffer_size
= 16384;
457 struct working_area
*write_algorithm
;
458 struct working_area
*source
;
459 uint32_t address
= bank
->base
+ offset
;
460 struct reg_param reg_params
[5];
461 struct armv7m_algorithm armv7m_info
;
462 int retval
= ERROR_OK
;
464 static const uint8_t stm32l4_flash_write_code
[] = {
465 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
468 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
469 &write_algorithm
) != ERROR_OK
) {
470 LOG_WARNING("no working area available, can't do block memory writes");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
474 retval
= target_write_buffer(target
, write_algorithm
->address
,
475 sizeof(stm32l4_flash_write_code
),
476 stm32l4_flash_write_code
);
477 if (retval
!= ERROR_OK
)
481 while (target_alloc_working_area_try(target
, buffer_size
, &source
) !=
484 if (buffer_size
<= 256) {
485 /* we already allocated the writing code, but failed to get a
486 * buffer, free the algorithm */
487 target_free_working_area(target
, write_algorithm
);
489 LOG_WARNING("no large enough working area available, can't do block memory writes");
490 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
494 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
495 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
497 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
498 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
499 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
500 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
501 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash base */
503 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
504 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
505 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
506 buf_set_u32(reg_params
[3].value
, 0, 32, count
/ 4);
507 buf_set_u32(reg_params
[4].value
, 0, 32, STM32_FLASH_BASE
);
509 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
512 source
->address
, source
->size
,
513 write_algorithm
->address
, 0,
516 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
517 LOG_ERROR("error executing stm32l4 flash write algorithm");
519 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
521 if (error
& FLASH_WRPERR
)
522 LOG_ERROR("flash memory write protected");
525 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
526 /* Clear but report errors */
527 target_write_u32(target
, STM32_FLASH_SR
, error
);
532 target_free_working_area(target
, source
);
533 target_free_working_area(target
, write_algorithm
);
535 destroy_reg_param(®_params
[0]);
536 destroy_reg_param(®_params
[1]);
537 destroy_reg_param(®_params
[2]);
538 destroy_reg_param(®_params
[3]);
539 destroy_reg_param(®_params
[4]);
544 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
545 uint32_t offset
, uint32_t count
)
547 struct target
*target
= bank
->target
;
550 if (bank
->target
->state
!= TARGET_HALTED
) {
551 LOG_ERROR("Target not halted");
552 return ERROR_TARGET_NOT_HALTED
;
556 LOG_WARNING("offset 0x%" PRIx32
" breaks required 8-byte alignment",
558 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
562 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
564 count
= (count
+ 7) & ~7;
565 /* This pads the write chunk with random bytes by overrunning the
566 * write buffer. Padding with the erased pattern 0xff is purely
567 * cosmetical, as 8-byte flash words are ECC secured and the first
568 * write will program the ECC bits. A second write would need
569 * to reprogramm these ECC bits.
570 * But this can only be done after erase!
574 retval
= stm32l4_unlock_reg(target
);
575 if (retval
!= ERROR_OK
)
578 /* Only full double words (8-byte) can be programmed*/
579 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 2);
580 if (retval
!= ERROR_OK
) {
581 LOG_WARNING("block write failed");
585 LOG_WARNING("block write succeeded");
586 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
589 static int stm32l4_probe(struct flash_bank
*bank
)
591 struct target
*target
= bank
->target
;
592 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
594 uint16_t flash_size_in_kb
= 0xffff;
595 uint16_t max_flash_size_in_kb
;
598 uint32_t base_address
= 0x08000000;
600 stm32l4_info
->probed
= 0;
602 /* read stm32 device id register */
603 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
604 if (retval
!= ERROR_OK
)
606 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
608 /* set max flash size depending on family */
609 switch (device_id
& 0xfff) {
612 max_flash_size_in_kb
= 1024;
615 max_flash_size_in_kb
= 512;
618 max_flash_size_in_kb
= 256;
621 LOG_WARNING("Cannot identify target as a STM32L4 family.");
625 /* get flash size from target. */
626 retval
= target_read_u16(target
, FLASH_SIZE_REG
, &flash_size_in_kb
);
628 /* failed reading flash size or flash size invalid (early silicon),
629 * default to max target family */
630 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
631 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
632 max_flash_size_in_kb
);
633 flash_size_in_kb
= max_flash_size_in_kb
;
636 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
638 /* did we assign flash size? */
639 assert(flash_size_in_kb
!= 0xffff);
641 /* get options to for DUAL BANK. */
642 retval
= target_read_u32(target
, STM32_FLASH_OPTR
, &options
);
644 if (retval
!= ERROR_OK
)
647 /* only devices with < 1024 kiB may be set to single bank dual banks */
648 if ((flash_size_in_kb
== 1024) || !(options
& OPT_DUALBANK
))
649 stm32l4_info
->option_bytes
.bank_b_start
= 256;
651 stm32l4_info
->option_bytes
.bank_b_start
= flash_size_in_kb
<< 9;
653 /* did we assign flash size? */
654 assert((flash_size_in_kb
!= 0xffff) && flash_size_in_kb
);
656 /* calculate numbers of pages */
657 int num_pages
= flash_size_in_kb
/ 2;
659 /* check that calculation result makes sense */
660 assert(num_pages
> 0);
664 bank
->sectors
= NULL
;
667 bank
->base
= base_address
;
668 bank
->size
= num_pages
* (1 << 11);
669 bank
->num_sectors
= num_pages
;
670 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
672 return ERROR_FAIL
; /* Checkme: What better error to use?*/
674 for (i
= 0; i
< num_pages
; i
++) {
675 bank
->sectors
[i
].offset
= i
<< 11;
676 bank
->sectors
[i
].size
= 1 << 11;
677 bank
->sectors
[i
].is_erased
= -1;
678 bank
->sectors
[i
].is_protected
= 1;
681 stm32l4_info
->probed
= 1;
686 static int stm32l4_auto_probe(struct flash_bank
*bank
)
688 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
689 if (stm32l4_info
->probed
)
691 return stm32l4_probe(bank
);
694 static int get_stm32l4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
696 struct target
*target
= bank
->target
;
697 uint32_t dbgmcu_idcode
;
699 /* read stm32 device id register */
700 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &dbgmcu_idcode
);
701 if (retval
!= ERROR_OK
)
704 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
705 uint8_t rev_id
= dbgmcu_idcode
>> 28;
706 uint8_t rev_minor
= 0;
709 for (i
= 16; i
< 28; i
++) {
710 if (dbgmcu_idcode
& (1 << i
))
716 const char *device_str
;
720 device_str
= "STM32L496/4A6";
724 device_str
= "STM32L475/476/486";
728 device_str
= "STM32L45x/46x";
732 device_str
= "STM32L43x/44x";
736 snprintf(buf
, buf_size
, "Cannot identify target as a STM32L4\n");
740 snprintf(buf
, buf_size
, "%s - Rev: %1d.%02d",
741 device_str
, rev_id
, rev_minor
);
746 COMMAND_HANDLER(stm32l4_handle_lock_command
)
748 struct target
*target
= NULL
;
749 struct stm32l4_flash_bank
*stm32l4_info
= NULL
;
752 return ERROR_COMMAND_SYNTAX_ERROR
;
754 struct flash_bank
*bank
;
755 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
756 if (ERROR_OK
!= retval
)
759 stm32l4_info
= bank
->driver_priv
;
760 target
= bank
->target
;
762 if (target
->state
!= TARGET_HALTED
) {
763 LOG_ERROR("Target not halted");
764 return ERROR_TARGET_NOT_HALTED
;
767 if (stm32l4_read_options(bank
) != ERROR_OK
) {
768 command_print(CMD_CTX
, "%s failed to read options",
773 /* set readout protection */
774 stm32l4_info
->option_bytes
.RDP
= 0;
776 if (stm32l4_write_options(bank
) != ERROR_OK
) {
777 command_print(CMD_CTX
, "%s failed to lock device", bank
->driver
->name
);
781 command_print(CMD_CTX
, "%s locked", bank
->driver
->name
);
786 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
788 struct target
*target
= NULL
;
789 struct stm32l4_flash_bank
*stm32l4_info
= NULL
;
792 return ERROR_COMMAND_SYNTAX_ERROR
;
794 struct flash_bank
*bank
;
795 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
796 if (ERROR_OK
!= retval
)
799 stm32l4_info
= bank
->driver_priv
;
800 target
= bank
->target
;
802 if (target
->state
!= TARGET_HALTED
) {
803 LOG_ERROR("Target not halted");
804 return ERROR_TARGET_NOT_HALTED
;
807 if (stm32l4_read_options(bank
) != ERROR_OK
) {
808 command_print(CMD_CTX
, "%s failed to read options", bank
->driver
->name
);
812 /* clear readout protection and complementary option bytes
813 * this will also force a device unlock if set */
814 stm32l4_info
->option_bytes
.RDP
= 0xAA;
816 if (stm32l4_write_options(bank
) != ERROR_OK
) {
817 command_print(CMD_CTX
, "%s failed to unlock device",
822 command_print(CMD_CTX
, "%s unlocked.\n"
823 "INFO: a reset or power cycle is required "
824 "for the new settings to take effect.", bank
->driver
->name
);
829 static int stm32l4_mass_erase(struct flash_bank
*bank
, uint32_t action
)
832 struct target
*target
= bank
->target
;
834 if (target
->state
!= TARGET_HALTED
) {
835 LOG_ERROR("Target not halted");
836 return ERROR_TARGET_NOT_HALTED
;
839 retval
= stm32l4_unlock_reg(target
);
840 if (retval
!= ERROR_OK
)
843 /* mass erase flash memory */
844 retval
= target_write_u32(
845 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), action
);
846 if (retval
!= ERROR_OK
)
848 retval
= target_write_u32(
849 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
),
850 action
| FLASH_STRT
);
851 if (retval
!= ERROR_OK
)
854 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
855 if (retval
!= ERROR_OK
)
858 retval
= target_write_u32(
859 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
860 if (retval
!= ERROR_OK
)
866 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
872 command_print(CMD_CTX
, "stm32x mass_erase <STM32L4 bank>");
873 return ERROR_COMMAND_SYNTAX_ERROR
;
876 struct flash_bank
*bank
;
877 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
878 if (ERROR_OK
!= retval
)
881 action
= FLASH_MER1
| FLASH_MER2
;
882 retval
= stm32l4_mass_erase(bank
, action
);
883 if (retval
== ERROR_OK
) {
884 /* set all sectors as erased */
885 for (i
= 0; i
< bank
->num_sectors
; i
++)
886 bank
->sectors
[i
].is_erased
= 1;
888 command_print(CMD_CTX
, "stm32x mass erase complete");
890 command_print(CMD_CTX
, "stm32x mass erase failed");
896 static const struct command_registration stm32l4_exec_command_handlers
[] = {
899 .handler
= stm32l4_handle_lock_command
,
900 .mode
= COMMAND_EXEC
,
902 .help
= "Lock entire flash device.",
906 .handler
= stm32l4_handle_unlock_command
,
907 .mode
= COMMAND_EXEC
,
909 .help
= "Unlock entire protected flash device.",
912 .name
= "mass_erase",
913 .handler
= stm32l4_handle_mass_erase_command
,
914 .mode
= COMMAND_EXEC
,
916 .help
= "Erase entire flash device.",
918 COMMAND_REGISTRATION_DONE
921 static const struct command_registration stm32l4_command_handlers
[] = {
925 .help
= "stm32l4x flash command group",
927 .chain
= stm32l4_exec_command_handlers
,
929 COMMAND_REGISTRATION_DONE
932 struct flash_driver stm32l4x_flash
= {
934 .commands
= stm32l4_command_handlers
,
935 .flash_bank_command
= stm32l4_flash_bank_command
,
936 .erase
= stm32l4_erase
,
937 .protect
= stm32l4_protect
,
938 .write
= stm32l4_write
,
939 .read
= default_flash_read
,
940 .probe
= stm32l4_probe
,
941 .auto_probe
= stm32l4_auto_probe
,
942 .erase_check
= default_flash_blank_check
,
943 .protect_check
= stm32l4_protect_check
,
944 .info
= get_stm32l4_info
,
945 .free_driver_priv
= default_flash_free_driver_priv
,