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target/xtensa: avoid IHI for writes to non-executable memory
[openocd.git] / src / flash / nor / stm32l4x.c
blob039938512bfa9378cfe87be62b0fec90a7a29761
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2015 by Uwe Bonnes *
5 * bon@elektron.ikp.physik.tu-darmstadt.de *
6 * *
7 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8 * tarek.bouchkati@gmail.com *
9 ***************************************************************************/
10
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23
24 /* STM32L4xxx series for reference.
25 *
26 * RM0351 (STM32L4x5/STM32L4x6)
27 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28 *
29 * RM0394 (STM32L43x/44x/45x/46x)
30 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31 *
32 * RM0432 (STM32L4R/4Sxx)
33 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34 *
35 * STM32L476RG Datasheet (for erase timing)
36 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37 *
38 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39 * an option byte is available to map all sectors to the first bank.
40 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41 * handlers do!
42 *
43 * RM0394 devices have a single bank only.
44 *
45 * RM0432 devices have single and dual bank operating modes.
46 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49 *
50 * Bank mode is controlled by two different bits in option bytes register.
51 * - for STM32L4R/Sxx
52 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54 * - for STM32L4P5/Q5x
55 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57 */
58
59 /* STM32WBxxx series for reference.
60 *
61 * RM0493 (STM32WBA52x)
62 * http://www.st.com/resource/en/reference_manual/dm00821869.pdf
63 *
64 * RM0434 (STM32WB55/WB35x)
65 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
66 *
67 * RM0471 (STM32WB50/WB30x)
68 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
69 *
70 * RM0473 (STM32WB15x)
71 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
72 *
73 * RM0478 (STM32WB10x)
74 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
75 */
76
77 /* STM32WLxxx series for reference.
78 *
79 * RM0461 (STM32WLEx)
80 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
81 *
82 * RM0453 (STM32WL5x)
83 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
84 */
85
86 /* STM32C0xxx series for reference.
87 *
88 * RM0490 (STM32C0x1)
89 * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
90 */
91
92 /* STM32G0xxx series for reference.
93 *
94 * RM0444 (STM32G0x1)
95 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
96 *
97 * RM0454 (STM32G0x0)
98 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
99 */
100
101 /* STM32G4xxx series for reference.
102 *
103 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
104 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
105 *
106 * Cat. 2 devices have single bank only, page size is 2kByte.
107 *
108 * Cat. 3 devices have single and dual bank operating modes,
109 * Page size is 2kByte (dual mode) or 4kByte (single mode).
110 *
111 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
112 * Both banks are treated as a single OpenOCD bank.
113 *
114 * Cat. 4 devices have single bank only, page size is 2kByte.
115 */
116
117 /* STM32L5xxx series for reference.
118 *
119 * RM0428 (STM32L552xx/STM32L562xx)
120 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
121 */
122
123 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
124
125 #define FLASH_ERASE_TIMEOUT 250
126 #define FLASH_WRITE_TIMEOUT 50
127
128
129 /* relevant STM32L4 flags ****************************************************/
130 #define F_NONE 0
131 /* this flag indicates if the device flash is with dual bank architecture */
132 #define F_HAS_DUAL_BANK BIT(0)
133 /* this flags is used for dual bank devices only, it indicates if the
134 * 4 WRPxx are usable if the device is configured in single-bank mode */
135 #define F_USE_ALL_WRPXX BIT(1)
136 /* this flag indicates if the device embeds a TrustZone security feature */
137 #define F_HAS_TZ BIT(2)
138 /* this flag indicates if the device has the same flash registers as STM32L5 */
139 #define F_HAS_L5_FLASH_REGS BIT(3)
140 /* this flag indicates that programming should be done in quad-word
141 * the default programming word size is double-word */
142 #define F_QUAD_WORD_PROG BIT(4)
143 /* end of STM32L4 flags ******************************************************/
144
145
146 enum stm32l4_flash_reg_index {
147 STM32_FLASH_ACR_INDEX,
148 STM32_FLASH_KEYR_INDEX,
149 STM32_FLASH_OPTKEYR_INDEX,
150 STM32_FLASH_SR_INDEX,
151 STM32_FLASH_CR_INDEX,
152 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
153 * so it uses the C2CR for flash operations and CR for checking locks and locking */
154 STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
155 STM32_FLASH_OPTR_INDEX,
156 STM32_FLASH_WRP1AR_INDEX,
157 STM32_FLASH_WRP1BR_INDEX,
158 STM32_FLASH_WRP2AR_INDEX,
159 STM32_FLASH_WRP2BR_INDEX,
160 STM32_FLASH_REG_INDEX_NUM,
161 };
162
163 enum stm32l4_rdp {
164 RDP_LEVEL_0 = 0xAA,
165 RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
166 RDP_LEVEL_1 = 0x00,
167 RDP_LEVEL_2 = 0xCC
168 };
169
170 static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
171 [STM32_FLASH_ACR_INDEX] = 0x000,
172 [STM32_FLASH_KEYR_INDEX] = 0x008,
173 [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
174 [STM32_FLASH_SR_INDEX] = 0x010,
175 [STM32_FLASH_CR_INDEX] = 0x014,
176 [STM32_FLASH_OPTR_INDEX] = 0x020,
177 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
178 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
179 [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
180 [STM32_FLASH_WRP2BR_INDEX] = 0x050,
181 };
182
183 static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
184 [STM32_FLASH_ACR_INDEX] = 0x000,
185 [STM32_FLASH_KEYR_INDEX] = 0x008,
186 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
187 [STM32_FLASH_SR_INDEX] = 0x060,
188 [STM32_FLASH_CR_INDEX] = 0x064,
189 [STM32_FLASH_CR_WLK_INDEX] = 0x014,
190 [STM32_FLASH_OPTR_INDEX] = 0x020,
191 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
192 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
193 };
194
195 static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
196 [STM32_FLASH_ACR_INDEX] = 0x000,
197 [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
198 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
199 [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
200 [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
201 [STM32_FLASH_OPTR_INDEX] = 0x040,
202 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
203 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
204 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
205 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
206 };
207
208 static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
209 [STM32_FLASH_ACR_INDEX] = 0x000,
210 [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
211 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
212 [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
213 [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
214 [STM32_FLASH_OPTR_INDEX] = 0x040,
215 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
216 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
217 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
218 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
219 };
220
221 struct stm32l4_rev {
222 const uint16_t rev;
223 const char *str;
224 };
225
226 struct stm32l4_part_info {
227 uint16_t id;
228 const char *device_str;
229 const struct stm32l4_rev *revs;
230 const size_t num_revs;
231 const uint16_t max_flash_size_kb;
232 const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
233 const uint32_t flash_regs_base;
234 const uint32_t fsize_addr;
235 const uint32_t otp_base;
236 const uint32_t otp_size;
237 };
238
239 struct stm32l4_flash_bank {
240 bool probed;
241 uint32_t idcode;
242 unsigned int bank1_sectors;
243 bool dual_bank_mode;
244 int hole_sectors;
245 uint32_t user_bank_size;
246 uint32_t data_width;
247 uint32_t cr_bker_mask;
248 uint32_t sr_bsy_mask;
249 uint32_t wrpxxr_mask;
250 const struct stm32l4_part_info *part_info;
251 uint32_t flash_regs_base;
252 const uint32_t *flash_regs;
253 bool otp_enabled;
254 enum stm32l4_rdp rdp;
255 bool tzen;
256 uint32_t optr;
257 };
258
259 enum stm32_bank_id {
260 STM32_BANK1,
261 STM32_BANK2,
262 STM32_ALL_BANKS
263 };
264
265 struct stm32l4_wrp {
266 enum stm32l4_flash_reg_index reg_idx;
267 uint32_t value;
268 bool used;
269 int first;
270 int last;
271 int offset;
272 };
273
274 /* human readable list of families this drivers supports (sorted alphabetically) */
275 static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
276
277 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
278 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
279 };
280
281 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
282 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
283 };
284
285
286 static const struct stm32l4_rev stm32c01xx_revs[] = {
287 { 0x1000, "A" }, { 0x1001, "Z" },
288 };
289
290 static const struct stm32l4_rev stm32c03xx_revs[] = {
291 { 0x1000, "A" }, { 0x1001, "Z" },
292 };
293
294 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
295 { 0x1000, "A" },
296 };
297
298 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
299 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
300 };
301
302 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
303 { 0x1000, "A" }, { 0x2000, "B" },
304 };
305
306 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
307 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
308 };
309
310 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
311 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
312 };
313
314 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
315 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
316 };
317
318 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
319 { 0x1000, "A" },
320 };
321
322 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
323 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
324 };
325
326 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
327 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
328 };
329
330 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
331 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
332 { 0x101F, "V" },
333 };
334
335 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
336 { 0x1001, "Z" },
337 };
338
339 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
340 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
341 };
342
343 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
344 { 0x1000, "A" },
345 };
346
347 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
348 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
349 { 0x2001, "X" }, { 0x3000, "C" },
350 };
351
352 static const struct stm32l4_rev stm32wba5x_revs[] = {
353 { 0x1000, "A" },
354 };
355
356 static const struct stm32l4_rev stm32wb1xx_revs[] = {
357 { 0x1000, "A" }, { 0x2000, "B" },
358 };
359
360 static const struct stm32l4_rev stm32wb5xx_revs[] = {
361 { 0x2001, "2.1" },
362 };
363
364 static const struct stm32l4_rev stm32wb3xx_revs[] = {
365 { 0x1000, "A" },
366 };
367
368 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
369 { 0x1000, "1.0" },
370 };
371
372 static const struct stm32l4_part_info stm32l4_parts[] = {
373 {
374 .id = DEVID_STM32L47_L48XX,
375 .revs = stm32l47_l48xx_revs,
376 .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
377 .device_str = "STM32L47/L48xx",
378 .max_flash_size_kb = 1024,
379 .flags = F_HAS_DUAL_BANK,
380 .flash_regs_base = 0x40022000,
381 .fsize_addr = 0x1FFF75E0,
382 .otp_base = 0x1FFF7000,
383 .otp_size = 1024,
384 },
385 {
386 .id = DEVID_STM32L43_L44XX,
387 .revs = stm32l43_l44xx_revs,
388 .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
389 .device_str = "STM32L43/L44xx",
390 .max_flash_size_kb = 256,
391 .flags = F_NONE,
392 .flash_regs_base = 0x40022000,
393 .fsize_addr = 0x1FFF75E0,
394 .otp_base = 0x1FFF7000,
395 .otp_size = 1024,
396 },
397 {
398 .id = DEVID_STM32C01XX,
399 .revs = stm32c01xx_revs,
400 .num_revs = ARRAY_SIZE(stm32c01xx_revs),
401 .device_str = "STM32C01xx",
402 .max_flash_size_kb = 32,
403 .flags = F_NONE,
404 .flash_regs_base = 0x40022000,
405 .fsize_addr = 0x1FFF75A0,
406 .otp_base = 0x1FFF7000,
407 .otp_size = 1024,
408 },
409 {
410 .id = DEVID_STM32C03XX,
411 .revs = stm32c03xx_revs,
412 .num_revs = ARRAY_SIZE(stm32c03xx_revs),
413 .device_str = "STM32C03xx",
414 .max_flash_size_kb = 32,
415 .flags = F_NONE,
416 .flash_regs_base = 0x40022000,
417 .fsize_addr = 0x1FFF75A0,
418 .otp_base = 0x1FFF7000,
419 .otp_size = 1024,
420 },
421 {
422 .id = DEVID_STM32G05_G06XX,
423 .revs = stm32g05_g06xx_revs,
424 .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
425 .device_str = "STM32G05/G06xx",
426 .max_flash_size_kb = 64,
427 .flags = F_NONE,
428 .flash_regs_base = 0x40022000,
429 .fsize_addr = 0x1FFF75E0,
430 .otp_base = 0x1FFF7000,
431 .otp_size = 1024,
432 },
433 {
434 .id = DEVID_STM32G07_G08XX,
435 .revs = stm32_g07_g08xx_revs,
436 .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
437 .device_str = "STM32G07/G08xx",
438 .max_flash_size_kb = 128,
439 .flags = F_NONE,
440 .flash_regs_base = 0x40022000,
441 .fsize_addr = 0x1FFF75E0,
442 .otp_base = 0x1FFF7000,
443 .otp_size = 1024,
444 },
445 {
446 .id = DEVID_STM32L49_L4AXX,
447 .revs = stm32l49_l4axx_revs,
448 .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
449 .device_str = "STM32L49/L4Axx",
450 .max_flash_size_kb = 1024,
451 .flags = F_HAS_DUAL_BANK,
452 .flash_regs_base = 0x40022000,
453 .fsize_addr = 0x1FFF75E0,
454 .otp_base = 0x1FFF7000,
455 .otp_size = 1024,
456 },
457 {
458 .id = DEVID_STM32L45_L46XX,
459 .revs = stm32l45_l46xx_revs,
460 .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
461 .device_str = "STM32L45/L46xx",
462 .max_flash_size_kb = 512,
463 .flags = F_NONE,
464 .flash_regs_base = 0x40022000,
465 .fsize_addr = 0x1FFF75E0,
466 .otp_base = 0x1FFF7000,
467 .otp_size = 1024,
468 },
469 {
470 .id = DEVID_STM32L41_L42XX,
471 .revs = stm32l41_l42xx_revs,
472 .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
473 .device_str = "STM32L41/L42xx",
474 .max_flash_size_kb = 128,
475 .flags = F_NONE,
476 .flash_regs_base = 0x40022000,
477 .fsize_addr = 0x1FFF75E0,
478 .otp_base = 0x1FFF7000,
479 .otp_size = 1024,
480 },
481 {
482 .id = DEVID_STM32G03_G04XX,
483 .revs = stm32g03_g04xx_revs,
484 .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
485 .device_str = "STM32G03x/G04xx",
486 .max_flash_size_kb = 64,
487 .flags = F_NONE,
488 .flash_regs_base = 0x40022000,
489 .fsize_addr = 0x1FFF75E0,
490 .otp_base = 0x1FFF7000,
491 .otp_size = 1024,
492 },
493 {
494 .id = DEVID_STM32G0B_G0CXX,
495 .revs = stm32g0b_g0cxx_revs,
496 .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
497 .device_str = "STM32G0B/G0Cx",
498 .max_flash_size_kb = 512,
499 .flags = F_HAS_DUAL_BANK,
500 .flash_regs_base = 0x40022000,
501 .fsize_addr = 0x1FFF75E0,
502 .otp_base = 0x1FFF7000,
503 .otp_size = 1024,
504 },
505 {
506 .id = DEVID_STM32G43_G44XX,
507 .revs = stm32g43_g44xx_revs,
508 .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
509 .device_str = "STM32G43/G44xx",
510 .max_flash_size_kb = 128,
511 .flags = F_NONE,
512 .flash_regs_base = 0x40022000,
513 .fsize_addr = 0x1FFF75E0,
514 .otp_base = 0x1FFF7000,
515 .otp_size = 1024,
516 },
517 {
518 .id = DEVID_STM32G47_G48XX,
519 .revs = stm32g47_g48xx_revs,
520 .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
521 .device_str = "STM32G47/G48xx",
522 .max_flash_size_kb = 512,
523 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
524 .flash_regs_base = 0x40022000,
525 .fsize_addr = 0x1FFF75E0,
526 .otp_base = 0x1FFF7000,
527 .otp_size = 1024,
528 },
529 {
530 .id = DEVID_STM32L4R_L4SXX,
531 .revs = stm32l4r_l4sxx_revs,
532 .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
533 .device_str = "STM32L4R/L4Sxx",
534 .max_flash_size_kb = 2048,
535 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
536 .flash_regs_base = 0x40022000,
537 .fsize_addr = 0x1FFF75E0,
538 .otp_base = 0x1FFF7000,
539 .otp_size = 1024,
540 },
541 {
542 .id = DEVID_STM32L4P_L4QXX,
543 .revs = stm32l4p_l4qxx_revs,
544 .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
545 .device_str = "STM32L4P/L4Qxx",
546 .max_flash_size_kb = 1024,
547 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
548 .flash_regs_base = 0x40022000,
549 .fsize_addr = 0x1FFF75E0,
550 .otp_base = 0x1FFF7000,
551 .otp_size = 1024,
552 },
553 {
554 .id = DEVID_STM32L55_L56XX,
555 .revs = stm32l55_l56xx_revs,
556 .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
557 .device_str = "STM32L55/L56xx",
558 .max_flash_size_kb = 512,
559 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
560 .flash_regs_base = 0x40022000,
561 .fsize_addr = 0x0BFA05E0,
562 .otp_base = 0x0BFA0000,
563 .otp_size = 512,
564 },
565 {
566 .id = DEVID_STM32G49_G4AXX,
567 .revs = stm32g49_g4axx_revs,
568 .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
569 .device_str = "STM32G49/G4Axx",
570 .max_flash_size_kb = 512,
571 .flags = F_NONE,
572 .flash_regs_base = 0x40022000,
573 .fsize_addr = 0x1FFF75E0,
574 .otp_base = 0x1FFF7000,
575 .otp_size = 1024,
576 },
577 {
578 .id = DEVID_STM32U57_U58XX,
579 .revs = stm32u57_u58xx_revs,
580 .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
581 .device_str = "STM32U57/U58xx",
582 .max_flash_size_kb = 2048,
583 .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
584 .flash_regs_base = 0x40022000,
585 .fsize_addr = 0x0BFA07A0,
586 .otp_base = 0x0BFA0000,
587 .otp_size = 512,
588 },
589 {
590 .id = DEVID_STM32WBA5X,
591 .revs = stm32wba5x_revs,
592 .num_revs = ARRAY_SIZE(stm32wba5x_revs),
593 .device_str = "STM32WBA5x",
594 .max_flash_size_kb = 1024,
595 .flags = F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
596 .flash_regs_base = 0x40022000,
597 .fsize_addr = 0x0FF907A0,
598 .otp_base = 0x0FF90000,
599 .otp_size = 512,
600 },
601 {
602 .id = DEVID_STM32WB1XX,
603 .revs = stm32wb1xx_revs,
604 .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
605 .device_str = "STM32WB1x",
606 .max_flash_size_kb = 320,
607 .flags = F_NONE,
608 .flash_regs_base = 0x58004000,
609 .fsize_addr = 0x1FFF75E0,
610 .otp_base = 0x1FFF7000,
611 .otp_size = 1024,
612 },
613 {
614 .id = DEVID_STM32WB5XX,
615 .revs = stm32wb5xx_revs,
616 .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
617 .device_str = "STM32WB5x",
618 .max_flash_size_kb = 1024,
619 .flags = F_NONE,
620 .flash_regs_base = 0x58004000,
621 .fsize_addr = 0x1FFF75E0,
622 .otp_base = 0x1FFF7000,
623 .otp_size = 1024,
624 },
625 {
626 .id = DEVID_STM32WB3XX,
627 .revs = stm32wb3xx_revs,
628 .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
629 .device_str = "STM32WB3x",
630 .max_flash_size_kb = 512,
631 .flags = F_NONE,
632 .flash_regs_base = 0x58004000,
633 .fsize_addr = 0x1FFF75E0,
634 .otp_base = 0x1FFF7000,
635 .otp_size = 1024,
636 },
637 {
638 .id = DEVID_STM32WLE_WL5XX,
639 .revs = stm32wle_wl5xx_revs,
640 .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
641 .device_str = "STM32WLE/WL5x",
642 .max_flash_size_kb = 256,
643 .flags = F_NONE,
644 .flash_regs_base = 0x58004000,
645 .fsize_addr = 0x1FFF75E0,
646 .otp_base = 0x1FFF7000,
647 .otp_size = 1024,
648 },
649 };
650
651 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
652 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
653 {
654 struct stm32l4_flash_bank *stm32l4_info;
655
656 if (CMD_ARGC < 6)
657 return ERROR_COMMAND_SYNTAX_ERROR;
658
659 /* fix-up bank base address: 0 is used for normal flash memory */
660 if (bank->base == 0)
661 bank->base = STM32_FLASH_BANK_BASE;
662
663 stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
664 if (!stm32l4_info)
665 return ERROR_FAIL; /* Checkme: What better error to use?*/
666 bank->driver_priv = stm32l4_info;
667
668 stm32l4_info->probed = false;
669 stm32l4_info->otp_enabled = false;
670 stm32l4_info->user_bank_size = bank->size;
671
672 return ERROR_OK;
673 }
674
675 /* bitmap helper extension */
676 struct range {
677 unsigned int start;
678 unsigned int end;
679 };
680
681 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
682 struct range *ranges, unsigned int *ranges_count) {
683 *ranges_count = 0;
684 bool last_bit = 0, cur_bit;
685 for (unsigned int i = 0; i < nbits; i++) {
686 cur_bit = test_bit(i, bitmap);
687
688 if (cur_bit && !last_bit) {
689 (*ranges_count)++;
690 ranges[*ranges_count - 1].start = i;
691 ranges[*ranges_count - 1].end = i;
692 } else if (cur_bit && last_bit) {
693 /* update (increment) the end this range */
694 ranges[*ranges_count - 1].end = i;
695 }
696
697 last_bit = cur_bit;
698 }
699 }
700
701 static inline int range_print_one(struct range *range, char *str)
702 {
703 if (range->start == range->end)
704 return sprintf(str, "[%d]", range->start);
705
706 return sprintf(str, "[%d,%d]", range->start, range->end);
707 }
708
709 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
710 {
711 /* each range will be printed like the following: [start,end]
712 * start and end, both are unsigned int, an unsigned int takes 10 characters max
713 * plus 3 characters for '[', ',' and ']'
714 * thus means each range can take maximum 23 character
715 * after each range we add a ' ' as separator and finally we need the '\0'
716 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
717 char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
718 char *ptr = str;
719
720 for (unsigned int i = 0; i < ranges_count; i++) {
721 ptr += range_print_one(&(ranges[i]), ptr);
722
723 if (i < ranges_count - 1)
724 *(ptr++) = ' ';
725 }
726
727 return str;
728 }
729
730 /* end of bitmap helper extension */
731
732 static inline bool stm32l4_is_otp(struct flash_bank *bank)
733 {
734 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
735 return bank->base == stm32l4_info->part_info->otp_base;
736 }
737
738 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
739 {
740 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
741
742 if (!stm32l4_is_otp(bank))
743 return ERROR_FAIL;
744
745 char *op_str = enable ? "enabled" : "disabled";
746
747 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
748 bank->bank_number,
749 stm32l4_info->otp_enabled == enable ? "already " : "",
750 op_str);
751
752 stm32l4_info->otp_enabled = enable;
753
754 return ERROR_OK;
755 }
756
757 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
758 {
759 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
760 return stm32l4_info->otp_enabled;
761 }
762
763 static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
764 {
765 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
766
767 bool tzen = false;
768
769 if (stm32l4_info->part_info->flags & F_HAS_TZ)
770 tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
771
772 uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
773
774 /* for devices without TrustZone:
775 * RDP level 0 and 2 values are to 0xAA and 0xCC
776 * Any other value corresponds to RDP level 1
777 * for devices with TrusZone:
778 * RDP level 0 and 2 values are 0xAA and 0xCC
779 * RDP level 0.5 value is 0x55 only if TZEN = 1
780 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
781 */
782
783 if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
784 if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
785 rdp = RDP_LEVEL_1;
786 }
787
788 stm32l4_info->tzen = tzen;
789 stm32l4_info->rdp = rdp;
790 }
791
792 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
793 {
794 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
795 return stm32l4_info->flash_regs_base + reg_offset;
796 }
797
798 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
799 enum stm32l4_flash_reg_index reg_index)
800 {
801 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
802 return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
803 }
804
805 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
806 {
807 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
808 }
809
810 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
811 enum stm32l4_flash_reg_index reg_index, uint32_t *value)
812 {
813 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
814 return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
815 }
816
817 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
818 {
819 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
820 }
821
822 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
823 enum stm32l4_flash_reg_index reg_index, uint32_t value)
824 {
825 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
826 return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
827 }
828
829 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
830 {
831 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
832 uint32_t status;
833 int retval = ERROR_OK;
834
835 /* wait for busy to clear */
836 for (;;) {
837 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
838 if (retval != ERROR_OK)
839 return retval;
840 LOG_DEBUG("status: 0x%" PRIx32 "", status);
841 if ((status & stm32l4_info->sr_bsy_mask) == 0)
842 break;
843 if (timeout-- <= 0) {
844 LOG_ERROR("timed out waiting for flash");
845 return ERROR_FAIL;
846 }
847 alive_sleep(1);
848 }
849
850 if (status & FLASH_WRPERR) {
851 LOG_ERROR("stm32x device protected");
852 retval = ERROR_FAIL;
853 }
854
855 /* Clear but report errors */
856 if (status & FLASH_ERROR) {
857 if (retval == ERROR_OK)
858 retval = ERROR_FAIL;
859 /* If this operation fails, we ignore it and report the original
860 * retval
861 */
862 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
863 }
864
865 return retval;
866 }
867
868 /** set all FLASH_SECBB registers to the same value */
869 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
870 {
871 /* This function should be used only with device with TrustZone, do just a security check */
872 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
873 assert(stm32l4_info->part_info->flags & F_HAS_TZ);
874
875 /* based on RM0438 Rev6 for STM32L5x devices:
876 * to modify a page block-based security attribution, it is recommended to
877 * 1- check that no flash operation is ongoing on the related page
878 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
879 * this step is not need in case of JTAG direct access
880 */
881 int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
882 if (retval != ERROR_OK)
883 return retval;
884
885 /* write SECBBxRy registers */
886 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
887
888 const uint8_t secbb_regs[] = {
889 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
890 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
891 };
892
893
894 unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
895
896 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
897 * then consider only the first half of secbb_regs
898 */
899 if (!stm32l4_info->dual_bank_mode)
900 num_secbb_regs /= 2;
901
902 for (unsigned int i = 0; i < num_secbb_regs; i++) {
903 retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
904 if (retval != ERROR_OK)
905 return retval;
906 }
907
908 return ERROR_OK;
909 }
910
911 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
912 {
913 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
914 return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
915 STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
916 }
917
918 static int stm32l4_unlock_reg(struct flash_bank *bank)
919 {
920 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
921 uint32_t ctrl;
922
923 /* first check if not already unlocked
924 * otherwise writing on STM32_FLASH_KEYR will fail
925 */
926 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
927 if (retval != ERROR_OK)
928 return retval;
929
930 if ((ctrl & FLASH_LOCK) == 0)
931 return ERROR_OK;
932
933 /* unlock flash registers */
934 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
935 if (retval != ERROR_OK)
936 return retval;
937
938 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
939 if (retval != ERROR_OK)
940 return retval;
941
942 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
943 if (retval != ERROR_OK)
944 return retval;
945
946 if (ctrl & FLASH_LOCK) {
947 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
948 return ERROR_TARGET_FAILURE;
949 }
950
951 return ERROR_OK;
952 }
953
954 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
955 {
956 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
957 uint32_t ctrl;
958
959 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
960 if (retval != ERROR_OK)
961 return retval;
962
963 if ((ctrl & FLASH_OPTLOCK) == 0)
964 return ERROR_OK;
965
966 /* unlock option registers */
967 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
968 if (retval != ERROR_OK)
969 return retval;
970
971 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
972 if (retval != ERROR_OK)
973 return retval;
974
975 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
976 if (retval != ERROR_OK)
977 return retval;
978
979 if (ctrl & FLASH_OPTLOCK) {
980 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
981 return ERROR_TARGET_FAILURE;
982 }
983
984 return ERROR_OK;
985 }
986
987 static int stm32l4_perform_obl_launch(struct flash_bank *bank)
988 {
989 int retval, retval2;
990
991 retval = stm32l4_unlock_reg(bank);
992 if (retval != ERROR_OK)
993 goto err_lock;
994
995 retval = stm32l4_unlock_option_reg(bank);
996 if (retval != ERROR_OK)
997 goto err_lock;
998
999 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
1000 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
1001 * "Note: If the read protection is set while the debugger is still
1002 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
1003 */
1004
1005 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
1006 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
1007 * then just ignore the returned value */
1008 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
1009
1010 /* Need to re-probe after change */
1011 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1012 stm32l4_info->probed = false;
1013
1014 err_lock:
1015 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
1016 FLASH_LOCK | FLASH_OPTLOCK);
1017
1018 if (retval != ERROR_OK)
1019 return retval;
1020
1021 return retval2;
1022 }
1023
1024 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
1025 uint32_t value, uint32_t mask)
1026 {
1027 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1028 uint32_t optiondata;
1029 int retval, retval2;
1030
1031 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
1032 if (retval != ERROR_OK)
1033 return retval;
1034
1035 /* for STM32L5 and similar devices, use always non-secure
1036 * registers for option bytes programming */
1037 const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
1038 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
1039 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1040
1041 retval = stm32l4_unlock_reg(bank);
1042 if (retval != ERROR_OK)
1043 goto err_lock;
1044
1045 retval = stm32l4_unlock_option_reg(bank);
1046 if (retval != ERROR_OK)
1047 goto err_lock;
1048
1049 optiondata = (optiondata & ~mask) | (value & mask);
1050
1051 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1052 if (retval != ERROR_OK)
1053 goto err_lock;
1054
1055 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
1056 if (retval != ERROR_OK)
1057 goto err_lock;
1058
1059 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1060
1061 err_lock:
1062 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
1063 FLASH_LOCK | FLASH_OPTLOCK);
1064 stm32l4_info->flash_regs = saved_flash_regs;
1065
1066 if (retval != ERROR_OK)
1067 return retval;
1068
1069 return retval2;
1070 }
1071
1072 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1073 enum stm32l4_flash_reg_index reg_idx, int offset)
1074 {
1075 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1076 int ret;
1077
1078 wrpxy->reg_idx = reg_idx;
1079 wrpxy->offset = offset;
1080
1081 ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1082 if (ret != ERROR_OK)
1083 return ret;
1084
1085 wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1086 wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1087 wrpxy->used = wrpxy->first <= wrpxy->last;
1088
1089 return ERROR_OK;
1090 }
1091
1092 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1093 struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1094 {
1095 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1096 int ret;
1097
1098 *n_wrp = 0;
1099
1100 /* for single bank devices there is 2 WRP regions.
1101 * for dual bank devices there is 2 WRP regions per bank,
1102 * if configured as single bank only 2 WRP are usable
1103 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1104 * note: this should be revised, if a device will have the SWAP banks option
1105 */
1106
1107 int wrp2y_sectors_offset = -1; /* -1 : unused */
1108
1109 /* if bank_id is BANK1 or ALL_BANKS */
1110 if (dev_bank_id != STM32_BANK2) {
1111 /* get FLASH_WRP1AR */
1112 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1113 if (ret != ERROR_OK)
1114 return ret;
1115
1116 /* get WRP1BR */
1117 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1118 if (ret != ERROR_OK)
1119 return ret;
1120
1121 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1122 if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1123 wrp2y_sectors_offset = 0;
1124 }
1125
1126 /* if bank_id is BANK2 or ALL_BANKS */
1127 if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1128 wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1129
1130 if (wrp2y_sectors_offset >= 0) {
1131 /* get WRP2AR */
1132 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1133 if (ret != ERROR_OK)
1134 return ret;
1135
1136 /* get WRP2BR */
1137 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1138 if (ret != ERROR_OK)
1139 return ret;
1140 }
1141
1142 return ERROR_OK;
1143 }
1144
1145 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1146 {
1147 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1148
1149 int wrp_start = wrpxy->first - wrpxy->offset;
1150 int wrp_end = wrpxy->last - wrpxy->offset;
1151
1152 uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1153
1154 return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1155 }
1156
1157 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1158 {
1159 int ret;
1160
1161 for (unsigned int i = 0; i < n_wrp; i++) {
1162 ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1163 if (ret != ERROR_OK)
1164 return ret;
1165 }
1166
1167 return ERROR_OK;
1168 }
1169
1170 static int stm32l4_protect_check(struct flash_bank *bank)
1171 {
1172 unsigned int n_wrp;
1173 struct stm32l4_wrp wrpxy[4];
1174
1175 int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1176 if (ret != ERROR_OK)
1177 return ret;
1178
1179 /* initialize all sectors as unprotected */
1180 for (unsigned int i = 0; i < bank->num_sectors; i++)
1181 bank->sectors[i].is_protected = 0;
1182
1183 /* now check WRPxy and mark the protected sectors */
1184 for (unsigned int i = 0; i < n_wrp; i++) {
1185 if (wrpxy[i].used) {
1186 for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1187 bank->sectors[s].is_protected = 1;
1188 }
1189 }
1190
1191 return ERROR_OK;
1192 }
1193
1194 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1195 unsigned int last)
1196 {
1197 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1198 int retval, retval2;
1199
1200 assert((first <= last) && (last < bank->num_sectors));
1201
1202 if (stm32l4_is_otp(bank)) {
1203 LOG_ERROR("cannot erase OTP memory");
1204 return ERROR_FLASH_OPER_UNSUPPORTED;
1205 }
1206
1207 if (bank->target->state != TARGET_HALTED) {
1208 LOG_ERROR("Target not halted");
1209 return ERROR_TARGET_NOT_HALTED;
1210 }
1211
1212 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1213 /* set all FLASH pages as secure */
1214 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1215 if (retval != ERROR_OK) {
1216 /* restore all FLASH pages as non-secure */
1217 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1218 return retval;
1219 }
1220 }
1221
1222 retval = stm32l4_unlock_reg(bank);
1223 if (retval != ERROR_OK)
1224 goto err_lock;
1225
1226 /*
1227 Sector Erase
1228 To erase a sector, follow the procedure below:
1229 1. Check that no Flash memory operation is ongoing by
1230 checking the BSY bit in the FLASH_SR register
1231 2. Set the PER bit and select the page and bank
1232 you wish to erase in the FLASH_CR register
1233 3. Set the STRT bit in the FLASH_CR register
1234 4. Wait for the BSY bit to be cleared
1235 */
1236
1237 for (unsigned int i = first; i <= last; i++) {
1238 uint32_t erase_flags;
1239 erase_flags = FLASH_PER | FLASH_STRT;
1240
1241 if (i >= stm32l4_info->bank1_sectors) {
1242 uint8_t snb;
1243 snb = i - stm32l4_info->bank1_sectors;
1244 erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1245 } else
1246 erase_flags |= i << FLASH_PAGE_SHIFT;
1247 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
1248 if (retval != ERROR_OK)
1249 break;
1250
1251 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1252 if (retval != ERROR_OK)
1253 break;
1254 }
1255
1256 err_lock:
1257 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1258
1259 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1260 /* restore all FLASH pages as non-secure */
1261 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1262 if (retval3 != ERROR_OK)
1263 return retval3;
1264 }
1265
1266 if (retval != ERROR_OK)
1267 return retval;
1268
1269 return retval2;
1270 }
1271
1272 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1273 unsigned int first, unsigned int last)
1274 {
1275 unsigned int i;
1276
1277 /* check if the desired protection is already configured */
1278 for (i = first; i <= last; i++) {
1279 if (bank->sectors[i].is_protected != set)
1280 break;
1281 else if (i == last) {
1282 LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1283 return ERROR_OK;
1284 }
1285 }
1286
1287 /* all sectors from first to last (or part of them) could have different
1288 * protection other than the requested */
1289 unsigned int n_wrp;
1290 struct stm32l4_wrp wrpxy[4];
1291
1292 int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1293 if (ret != ERROR_OK)
1294 return ret;
1295
1296 /* use bitmap and range helpers to optimize the WRP usage */
1297 DECLARE_BITMAP(pages, bank->num_sectors);
1298 bitmap_zero(pages, bank->num_sectors);
1299
1300 for (i = 0; i < n_wrp; i++) {
1301 if (wrpxy[i].used) {
1302 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1303 set_bit(p, pages);
1304 }
1305 }
1306
1307 /* we have at most 'n_wrp' WRP areas
1308 * add one range if the user is trying to protect a fifth range */
1309 struct range ranges[n_wrp + 1];
1310 unsigned int ranges_count = 0;
1311
1312 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1313
1314 /* pretty-print the currently protected ranges */
1315 if (ranges_count > 0) {
1316 char *ranges_str = range_print_alloc(ranges, ranges_count);
1317 LOG_DEBUG("current protected areas: %s", ranges_str);
1318 free(ranges_str);
1319 } else
1320 LOG_DEBUG("current protected areas: none");
1321
1322 if (set) { /* flash protect */
1323 for (i = first; i <= last; i++)
1324 set_bit(i, pages);
1325 } else { /* flash unprotect */
1326 for (i = first; i <= last; i++)
1327 clear_bit(i, pages);
1328 }
1329
1330 /* check the ranges_count after the user request */
1331 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1332
1333 /* pretty-print the requested areas for protection */
1334 if (ranges_count > 0) {
1335 char *ranges_str = range_print_alloc(ranges, ranges_count);
1336 LOG_DEBUG("requested areas for protection: %s", ranges_str);
1337 free(ranges_str);
1338 } else
1339 LOG_DEBUG("requested areas for protection: none");
1340
1341 if (ranges_count > n_wrp) {
1342 LOG_ERROR("cannot set the requested protection "
1343 "(only %u write protection areas are available)" , n_wrp);
1344 return ERROR_FAIL;
1345 }
1346
1347 /* re-init all WRPxy as disabled (first > last)*/
1348 for (i = 0; i < n_wrp; i++) {
1349 wrpxy[i].first = wrpxy[i].offset + 1;
1350 wrpxy[i].last = wrpxy[i].offset;
1351 }
1352
1353 /* then configure WRPxy areas */
1354 for (i = 0; i < ranges_count; i++) {
1355 wrpxy[i].first = ranges[i].start;
1356 wrpxy[i].last = ranges[i].end;
1357 }
1358
1359 /* finally write WRPxy registers */
1360 return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1361 }
1362
1363 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1364 {
1365 struct target *target = bank->target;
1366 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1367
1368 if (stm32l4_is_otp(bank)) {
1369 LOG_ERROR("cannot protect/unprotect OTP memory");
1370 return ERROR_FLASH_OPER_UNSUPPORTED;
1371 }
1372
1373 if (target->state != TARGET_HALTED) {
1374 LOG_ERROR("Target not halted");
1375 return ERROR_TARGET_NOT_HALTED;
1376 }
1377
1378 /* refresh the sectors' protection */
1379 int ret = stm32l4_protect_check(bank);
1380 if (ret != ERROR_OK)
1381 return ret;
1382
1383 /* the requested sectors could be located into bank1 and/or bank2 */
1384 if (last < stm32l4_info->bank1_sectors) {
1385 return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1386 } else if (first >= stm32l4_info->bank1_sectors) {
1387 return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1388 } else {
1389 ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1390 if (ret != ERROR_OK)
1391 return ret;
1392
1393 return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1394 }
1395 }
1396
1397 /* count is the size divided by stm32l4_info->data_width */
1398 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1399 uint32_t offset, uint32_t count)
1400 {
1401 struct target *target = bank->target;
1402 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1403 struct working_area *write_algorithm;
1404 struct working_area *source;
1405 uint32_t address = bank->base + offset;
1406 struct reg_param reg_params[5];
1407 struct armv7m_algorithm armv7m_info;
1408 int retval = ERROR_OK;
1409
1410 static const uint8_t stm32l4_flash_write_code[] = {
1411 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1412 };
1413
1414 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1415 &write_algorithm) != ERROR_OK) {
1416 LOG_WARNING("no working area available, can't do block memory writes");
1417 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1418 }
1419
1420 retval = target_write_buffer(target, write_algorithm->address,
1421 sizeof(stm32l4_flash_write_code),
1422 stm32l4_flash_write_code);
1423 if (retval != ERROR_OK) {
1424 target_free_working_area(target, write_algorithm);
1425 return retval;
1426 }
1427
1428 /* data_width should be multiple of double-word */
1429 assert(stm32l4_info->data_width % 8 == 0);
1430 const size_t extra_size = sizeof(struct stm32l4_work_area);
1431 uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1432 /* buffer_size should be multiple of stm32l4_info->data_width */
1433 buffer_size &= ~(stm32l4_info->data_width - 1);
1434
1435 if (buffer_size < 256) {
1436 LOG_WARNING("large enough working area not available, can't do block memory writes");
1437 target_free_working_area(target, write_algorithm);
1438 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1439 } else if (buffer_size > 16384) {
1440 /* probably won't benefit from more than 16k ... */
1441 buffer_size = 16384;
1442 }
1443
1444 if (target_alloc_working_area_try(target, buffer_size + extra_size, &source) != ERROR_OK) {
1445 LOG_ERROR("allocating working area failed");
1446 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1447 }
1448
1449 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1450 armv7m_info.core_mode = ARM_MODE_THREAD;
1451
1452 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1453 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1454 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1455 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1456 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1457
1458 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1459 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1460 buf_set_u32(reg_params[2].value, 0, 32, address);
1461 buf_set_u32(reg_params[3].value, 0, 32, count);
1462
1463 /* write algo stack pointer */
1464 init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1465 buf_set_u32(reg_params[4].value, 0, 32, source->address +
1466 offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1467
1468 struct stm32l4_loader_params loader_extra_params;
1469
1470 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1471 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
1472 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1473 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
1474 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1475 stm32l4_info->data_width);
1476 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1477 stm32l4_info->sr_bsy_mask);
1478
1479 retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1480 (uint8_t *) &loader_extra_params);
1481 if (retval != ERROR_OK)
1482 return retval;
1483
1484 retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
1485 0, NULL,
1486 ARRAY_SIZE(reg_params), reg_params,
1487 source->address + offsetof(struct stm32l4_work_area, fifo),
1488 source->size - offsetof(struct stm32l4_work_area, fifo),
1489 write_algorithm->address, 0,
1490 &armv7m_info);
1491
1492 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1493 LOG_ERROR("error executing stm32l4 flash write algorithm");
1494
1495 uint32_t error;
1496 stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &error);
1497 error &= FLASH_ERROR;
1498
1499 if (error & FLASH_WRPERR)
1500 LOG_ERROR("flash memory write protected");
1501
1502 if (error != 0) {
1503 LOG_ERROR("flash write failed = %08" PRIx32, error);
1504 /* Clear but report errors */
1505 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
1506 retval = ERROR_FAIL;
1507 }
1508 }
1509
1510 target_free_working_area(target, source);
1511 target_free_working_area(target, write_algorithm);
1512
1513 destroy_reg_param(&reg_params[0]);
1514 destroy_reg_param(&reg_params[1]);
1515 destroy_reg_param(&reg_params[2]);
1516 destroy_reg_param(&reg_params[3]);
1517 destroy_reg_param(&reg_params[4]);
1518
1519 return retval;
1520 }
1521
1522 /* count is the size divided by stm32l4_info->data_width */
1523 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1524 uint32_t offset, uint32_t count)
1525 {
1526 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1527 struct target *target = bank->target;
1528 uint32_t address = bank->base + offset;
1529 int retval = ERROR_OK;
1530
1531 /* wait for BSY bit */
1532 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1533 if (retval != ERROR_OK)
1534 return retval;
1535
1536 /* set PG in FLASH_CR */
1537 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG);
1538 if (retval != ERROR_OK)
1539 return retval;
1540
1541
1542 /* write directly to flash memory */
1543 const uint8_t *src = buffer;
1544 const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1545 while (count--) {
1546 retval = target_write_memory(target, address, 4, data_width_in_words, src);
1547 if (retval != ERROR_OK)
1548 return retval;
1549
1550 /* wait for BSY bit */
1551 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1552 if (retval != ERROR_OK)
1553 return retval;
1554
1555 src += stm32l4_info->data_width;
1556 address += stm32l4_info->data_width;
1557 }
1558
1559 /* reset PG in FLASH_CR */
1560 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0);
1561 if (retval != ERROR_OK)
1562 return retval;
1563
1564 return retval;
1565 }
1566
1567 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1568 uint32_t offset, uint32_t count)
1569 {
1570 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1571 int retval = ERROR_OK, retval2;
1572
1573 if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
1574 LOG_ERROR("OTP memory is disabled for write commands");
1575 return ERROR_FAIL;
1576 }
1577
1578 if (bank->target->state != TARGET_HALTED) {
1579 LOG_ERROR("Target not halted");
1580 return ERROR_TARGET_NOT_HALTED;
1581 }
1582
1583 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1584 assert(stm32l4_info->data_width % 8 == 0);
1585
1586 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1587 * The flash infrastructure ensures it, do just a security check */
1588 assert(offset % stm32l4_info->data_width == 0);
1589 assert(count % stm32l4_info->data_width == 0);
1590
1591 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1592 * data to be written does not go into a gap:
1593 * suppose buffer is fully contained in bank from sector 0 to sector
1594 * num->sectors - 1 and sectors are ordered according to offset
1595 */
1596 struct flash_sector *head = &bank->sectors[0];
1597 struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1598
1599 while ((head < tail) && (offset >= (head + 1)->offset)) {
1600 /* buffer does not intersect head nor gap behind head */
1601 head++;
1602 }
1603
1604 while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1605 /* buffer does not intersect tail nor gap before tail */
1606 --tail;
1607 }
1608
1609 LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1610 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1611
1612 /* Now check that there is no gap from head to tail, this should work
1613 * even for multiple or non-symmetric gaps
1614 */
1615 while (head < tail) {
1616 if (head->offset + head->size != (head + 1)->offset) {
1617 LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1618 bank->base + head->offset + head->size,
1619 bank->base + (head + 1)->offset - 1);
1620 retval = ERROR_FLASH_DST_OUT_OF_BANK;
1621 }
1622 head++;
1623 }
1624
1625 if (retval != ERROR_OK)
1626 return retval;
1627
1628 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1629 /* set all FLASH pages as secure */
1630 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1631 if (retval != ERROR_OK) {
1632 /* restore all FLASH pages as non-secure */
1633 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1634 return retval;
1635 }
1636 }
1637
1638 retval = stm32l4_unlock_reg(bank);
1639 if (retval != ERROR_OK)
1640 goto err_lock;
1641
1642
1643 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1644 * the debug is possible only in non-secure state.
1645 * Thus means the flashloader will run in non-secure mode,
1646 * and the workarea need to be in non-secure RAM */
1647 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1648 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1649
1650 /* first try to write using the loader, for better performance */
1651 retval = stm32l4_write_block(bank, buffer, offset,
1652 count / stm32l4_info->data_width);
1653
1654 /* if resources are not available write without a loader */
1655 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1656 LOG_WARNING("falling back to programming without a flash loader (slower)");
1657 retval = stm32l4_write_block_without_loader(bank, buffer, offset,
1658 count / stm32l4_info->data_width);
1659 }
1660
1661 err_lock:
1662 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1663
1664 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1665 /* restore all FLASH pages as non-secure */
1666 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1667 if (retval3 != ERROR_OK)
1668 return retval3;
1669 }
1670
1671 if (retval != ERROR_OK) {
1672 LOG_ERROR("block write failed");
1673 return retval;
1674 }
1675 return retval2;
1676 }
1677
1678 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1679 {
1680 int retval = ERROR_OK;
1681 struct target *target = bank->target;
1682
1683 /* try reading possible IDCODE registers, in the following order */
1684 uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1685
1686 for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1687 retval = target_read_u32(target, dbgmcu_idcode[i], id);
1688 if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1689 return ERROR_OK;
1690 }
1691
1692 /* Workaround for STM32WL5x devices:
1693 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1694 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1695
1696 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1697 if (!armv7m) {
1698 LOG_ERROR("Flash requires Cortex-M target");
1699 return ERROR_TARGET_INVALID;
1700 }
1701
1702 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1703 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1704 if (cortex_m_get_impl_part(target) == CORTEX_M0P_PARTNO &&
1705 armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1706 uint32_t uid64_ids;
1707
1708 /* UID64 is contains
1709 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1710 * - Bits 31:08 : STID (company ID) = 0x0080E1
1711 * - Bits 07:00 : DEVID (device ID) = 0x15
1712 *
1713 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1714 */
1715 retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1716 if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1717 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1718 *id = DEVID_STM32WLE_WL5XX;
1719 return ERROR_OK;
1720 }
1721 }
1722
1723 LOG_ERROR("can't get the device id");
1724 return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1725 }
1726
1727 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1728 {
1729 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1730 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1731 assert(part_info);
1732
1733 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1734 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1735 if (rev_id == part_info->revs[i].rev)
1736 return part_info->revs[i].str;
1737 }
1738 return "'unknown'";
1739 }
1740
1741 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1742 {
1743 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1744 assert(stm32l4_info->part_info);
1745 return stm32l4_is_otp(bank) ? "OTP" :
1746 stm32l4_info->dual_bank_mode ? "Flash dual" :
1747 "Flash single";
1748 }
1749
1750 static int stm32l4_probe(struct flash_bank *bank)
1751 {
1752 struct target *target = bank->target;
1753 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1754 const struct stm32l4_part_info *part_info;
1755 uint16_t flash_size_kb = 0xffff;
1756
1757 if (!target_was_examined(target)) {
1758 LOG_ERROR("Target not examined yet");
1759 return ERROR_TARGET_NOT_EXAMINED;
1760 }
1761
1762 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1763 if (!armv7m) {
1764 LOG_ERROR("Flash requires Cortex-M target");
1765 return ERROR_TARGET_INVALID;
1766 }
1767
1768 stm32l4_info->probed = false;
1769
1770 /* read stm32 device id registers */
1771 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1772 if (retval != ERROR_OK)
1773 return retval;
1774
1775 const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1776
1777 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1778 if (device_id == stm32l4_parts[n].id) {
1779 stm32l4_info->part_info = &stm32l4_parts[n];
1780 break;
1781 }
1782 }
1783
1784 if (!stm32l4_info->part_info) {
1785 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1786 return ERROR_FAIL;
1787 }
1788
1789 part_info = stm32l4_info->part_info;
1790 const char *rev_str = get_stm32l4_rev_str(bank);
1791 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1792
1793 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1794 stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1795
1796 stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1797 stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1798 stm32l4_info->cr_bker_mask = FLASH_BKER;
1799 stm32l4_info->sr_bsy_mask = FLASH_BSY;
1800
1801 /* Set flash write alignment boundaries.
1802 * Ask the flash infrastructure to ensure required alignment */
1803 bank->write_start_alignment = stm32l4_info->data_width;
1804 bank->write_end_alignment = stm32l4_info->data_width;
1805
1806 /* Initialize the flash registers layout */
1807 if (part_info->flags & F_HAS_L5_FLASH_REGS)
1808 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1809 else
1810 stm32l4_info->flash_regs = stm32l4_flash_regs;
1811
1812 /* read flash option register */
1813 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
1814 if (retval != ERROR_OK)
1815 return retval;
1816
1817 stm32l4_sync_rdp_tzen(bank);
1818
1819 /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1820 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1821 if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1822 stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1823 stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1824 } else {
1825 LOG_ERROR("BUG: device supported incomplete");
1826 return ERROR_NOT_IMPLEMENTED;
1827 }
1828 }
1829
1830 if (part_info->flags & F_HAS_TZ)
1831 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1832 stm32l4_info->tzen,
1833 stm32l4_info->tzen ? "enabled" : "disabled");
1834
1835 LOG_INFO("RDP level %s (0x%02X)",
1836 stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1837 stm32l4_info->rdp);
1838
1839 if (stm32l4_is_otp(bank)) {
1840 bank->size = part_info->otp_size;
1841
1842 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1843
1844 /* OTP memory is considered as one sector */
1845 free(bank->sectors);
1846 bank->num_sectors = 1;
1847 bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1848
1849 if (!bank->sectors) {
1850 LOG_ERROR("failed to allocate bank sectors");
1851 return ERROR_FAIL;
1852 }
1853
1854 stm32l4_info->probed = true;
1855 return ERROR_OK;
1856 } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1857 LOG_ERROR("invalid bank base address");
1858 return ERROR_FAIL;
1859 }
1860
1861 /* get flash size from target. */
1862 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1863
1864 /* failed reading flash size or flash size invalid (early silicon),
1865 * default to max target family */
1866 if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1867 || flash_size_kb > part_info->max_flash_size_kb) {
1868 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1869 part_info->max_flash_size_kb);
1870 flash_size_kb = part_info->max_flash_size_kb;
1871 }
1872
1873 /* if the user sets the size manually then ignore the probed value
1874 * this allows us to work around devices that have a invalid flash size register value */
1875 if (stm32l4_info->user_bank_size) {
1876 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1877 flash_size_kb = stm32l4_info->user_bank_size / 1024;
1878 }
1879
1880 LOG_INFO("flash size = %d KiB", flash_size_kb);
1881
1882 /* did we assign a flash size? */
1883 assert((flash_size_kb != 0xffff) && flash_size_kb);
1884
1885 const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1886
1887 stm32l4_info->bank1_sectors = 0;
1888 stm32l4_info->hole_sectors = 0;
1889
1890 int num_pages = 0;
1891 int page_size_kb = 0;
1892
1893 stm32l4_info->dual_bank_mode = false;
1894
1895 switch (device_id) {
1896 case DEVID_STM32L47_L48XX:
1897 case DEVID_STM32L49_L4AXX:
1898 /* if flash size is max (1M) the device is always dual bank
1899 * STM32L47/L48xx: has variants with 512K
1900 * STM32L49/L4Axx: has variants with 512 and 256
1901 * for these variants:
1902 * if DUAL_BANK = 0 -> single bank
1903 * else -> dual bank without gap
1904 * note: the page size is invariant
1905 */
1906 page_size_kb = 2;
1907 num_pages = flash_size_kb / page_size_kb;
1908 stm32l4_info->bank1_sectors = num_pages;
1909
1910 /* check DUAL_BANK option bit if the flash is less than 1M */
1911 if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
1912 stm32l4_info->dual_bank_mode = true;
1913 stm32l4_info->bank1_sectors = num_pages / 2;
1914 }
1915 break;
1916 case DEVID_STM32L43_L44XX:
1917 case DEVID_STM32C01XX:
1918 case DEVID_STM32C03XX:
1919 case DEVID_STM32G05_G06XX:
1920 case DEVID_STM32G07_G08XX:
1921 case DEVID_STM32L45_L46XX:
1922 case DEVID_STM32L41_L42XX:
1923 case DEVID_STM32G03_G04XX:
1924 case DEVID_STM32G43_G44XX:
1925 case DEVID_STM32G49_G4AXX:
1926 case DEVID_STM32WB1XX:
1927 /* single bank flash */
1928 page_size_kb = 2;
1929 num_pages = flash_size_kb / page_size_kb;
1930 stm32l4_info->bank1_sectors = num_pages;
1931 break;
1932 case DEVID_STM32G0B_G0CXX:
1933 /* single/dual bank depending on DUAL_BANK option bit */
1934 page_size_kb = 2;
1935 num_pages = flash_size_kb / page_size_kb;
1936 stm32l4_info->bank1_sectors = num_pages;
1937 stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
1938
1939 /* check DUAL_BANK bit */
1940 if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
1941 stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
1942 stm32l4_info->dual_bank_mode = true;
1943 stm32l4_info->bank1_sectors = num_pages / 2;
1944 }
1945 break;
1946 case DEVID_STM32G47_G48XX:
1947 /* STM32G47/8 can be single/dual bank:
1948 * if DUAL_BANK = 0 -> single bank
1949 * else -> dual bank WITH gap
1950 */
1951 page_size_kb = 4;
1952 num_pages = flash_size_kb / page_size_kb;
1953 stm32l4_info->bank1_sectors = num_pages;
1954 if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
1955 stm32l4_info->dual_bank_mode = true;
1956 page_size_kb = 2;
1957 num_pages = flash_size_kb / page_size_kb;
1958 stm32l4_info->bank1_sectors = num_pages / 2;
1959
1960 /* for devices with trimmed flash, there is a gap between both banks */
1961 stm32l4_info->hole_sectors =
1962 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
1963 }
1964 break;
1965 case DEVID_STM32L4R_L4SXX:
1966 case DEVID_STM32L4P_L4QXX:
1967 /* STM32L4R/S can be single/dual bank:
1968 * if size = 2M check DBANK bit
1969 * if size = 1M check DB1M bit
1970 * STM32L4P/Q can be single/dual bank
1971 * if size = 1M check DBANK bit
1972 * if size = 512K check DB512K bit (same as DB1M bit)
1973 */
1974 page_size_kb = 8;
1975 num_pages = flash_size_kb / page_size_kb;
1976 stm32l4_info->bank1_sectors = num_pages;
1977 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
1978 (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
1979 stm32l4_info->dual_bank_mode = true;
1980 page_size_kb = 4;
1981 num_pages = flash_size_kb / page_size_kb;
1982 stm32l4_info->bank1_sectors = num_pages / 2;
1983 }
1984 break;
1985 case DEVID_STM32L55_L56XX:
1986 /* STM32L55/L56xx can be single/dual bank:
1987 * if size = 512K check DBANK bit
1988 * if size = 256K check DB256K bit
1989 *
1990 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
1991 */
1992
1993 page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
1994 num_pages = flash_size_kb / page_size_kb;
1995 stm32l4_info->bank1_sectors = num_pages;
1996
1997 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
1998 (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
1999 stm32l4_info->dual_bank_mode = true;
2000 stm32l4_info->bank1_sectors = num_pages / 2;
2001 }
2002 break;
2003 case DEVID_STM32U57_U58XX:
2004 /* if flash size is max (2M) the device is always dual bank
2005 * otherwise check DUALBANK
2006 */
2007 page_size_kb = 8;
2008 num_pages = flash_size_kb / page_size_kb;
2009 stm32l4_info->bank1_sectors = num_pages;
2010 if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
2011 stm32l4_info->dual_bank_mode = true;
2012 stm32l4_info->bank1_sectors = num_pages / 2;
2013 }
2014 break;
2015 case DEVID_STM32WBA5X:
2016 /* single bank flash */
2017 page_size_kb = 8;
2018 num_pages = flash_size_kb / page_size_kb;
2019 stm32l4_info->bank1_sectors = num_pages;
2020 break;
2021 case DEVID_STM32WB5XX:
2022 case DEVID_STM32WB3XX:
2023 /* single bank flash */
2024 page_size_kb = 4;
2025 num_pages = flash_size_kb / page_size_kb;
2026 stm32l4_info->bank1_sectors = num_pages;
2027 break;
2028 case DEVID_STM32WLE_WL5XX:
2029 /* single bank flash */
2030 page_size_kb = 2;
2031 num_pages = flash_size_kb / page_size_kb;
2032 stm32l4_info->bank1_sectors = num_pages;
2033
2034 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2035 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2036 if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
2037 stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
2038 break;
2039 default:
2040 LOG_ERROR("unsupported device");
2041 return ERROR_FAIL;
2042 }
2043
2044 /* ensure that at least there is 1 flash sector / page */
2045 if (num_pages == 0) {
2046 if (stm32l4_info->user_bank_size)
2047 LOG_ERROR("The specified flash size is less than page size");
2048
2049 LOG_ERROR("Flash pages count cannot be zero");
2050 return ERROR_FAIL;
2051 }
2052
2053 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
2054
2055 const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
2056
2057 if (gap_size_kb != 0) {
2058 LOG_INFO("gap detected from 0x%08x to 0x%08x",
2059 STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
2060 * page_size_kb * 1024,
2061 STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
2062 * page_size_kb + gap_size_kb) * 1024 - 1);
2063 }
2064
2065 /* number of significant bits in WRPxxR differs per device,
2066 * always right adjusted, on some devices non-implemented
2067 * bits read as '0', on others as '1' ...
2068 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2069 */
2070
2071 /* use *max_flash_size* instead of actual size as the trimmed versions
2072 * certainly use the same number of bits
2073 */
2074 uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2075
2076 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2077 stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2078 assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2079 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2080
2081 free(bank->sectors);
2082
2083 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2084 bank->num_sectors = num_pages;
2085 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2086 if (!bank->sectors) {
2087 LOG_ERROR("failed to allocate bank sectors");
2088 return ERROR_FAIL;
2089 }
2090
2091 for (unsigned int i = 0; i < bank->num_sectors; i++) {
2092 bank->sectors[i].offset = i * page_size_kb * 1024;
2093 /* in dual bank configuration, if there is a gap between banks
2094 * we fix up the sector offset to consider this gap */
2095 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2096 bank->sectors[i].offset += gap_size_kb * 1024;
2097 bank->sectors[i].size = page_size_kb * 1024;
2098 bank->sectors[i].is_erased = -1;
2099 bank->sectors[i].is_protected = 1;
2100 }
2101
2102 stm32l4_info->probed = true;
2103 return ERROR_OK;
2104 }
2105
2106 static int stm32l4_auto_probe(struct flash_bank *bank)
2107 {
2108 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2109 if (stm32l4_info->probed) {
2110 uint32_t optr_cur;
2111
2112 /* save flash_regs_base */
2113 uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2114
2115 /* for devices with TrustZone, use NS flash registers to read OPTR */
2116 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2117 stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2118
2119 /* read flash option register and re-probe if optr value is changed */
2120 int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur);
2121
2122 /* restore saved flash_regs_base */
2123 stm32l4_info->flash_regs_base = saved_flash_regs_base;
2124
2125 if (retval != ERROR_OK)
2126 return retval;
2127
2128 if (stm32l4_info->optr == optr_cur)
2129 return ERROR_OK;
2130 }
2131
2132 return stm32l4_probe(bank);
2133 }
2134
2135 static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
2136 {
2137 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2138 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2139
2140 if (part_info) {
2141 const uint16_t rev_id = stm32l4_info->idcode >> 16;
2142 command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2143 get_stm32l4_rev_str(bank), rev_id);
2144 if (stm32l4_info->probed)
2145 command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank));
2146 } else {
2147 command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2148 }
2149
2150 return ERROR_OK;
2151 }
2152
2153 static int stm32l4_mass_erase(struct flash_bank *bank)
2154 {
2155 int retval, retval2;
2156 struct target *target = bank->target;
2157 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2158
2159 if (stm32l4_is_otp(bank)) {
2160 LOG_ERROR("cannot erase OTP memory");
2161 return ERROR_FLASH_OPER_UNSUPPORTED;
2162 }
2163
2164 uint32_t action = FLASH_MER1;
2165
2166 if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2167 action |= FLASH_MER2;
2168
2169 if (target->state != TARGET_HALTED) {
2170 LOG_ERROR("Target not halted");
2171 return ERROR_TARGET_NOT_HALTED;
2172 }
2173
2174 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2175 /* set all FLASH pages as secure */
2176 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
2177 if (retval != ERROR_OK) {
2178 /* restore all FLASH pages as non-secure */
2179 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2180 return retval;
2181 }
2182 }
2183
2184 retval = stm32l4_unlock_reg(bank);
2185 if (retval != ERROR_OK)
2186 goto err_lock;
2187
2188 /* mass erase flash memory */
2189 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
2190 if (retval != ERROR_OK)
2191 goto err_lock;
2192
2193 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
2194 if (retval != ERROR_OK)
2195 goto err_lock;
2196
2197 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
2198 if (retval != ERROR_OK)
2199 goto err_lock;
2200
2201 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
2202
2203 err_lock:
2204 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
2205
2206 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2207 /* restore all FLASH pages as non-secure */
2208 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
2209 if (retval3 != ERROR_OK)
2210 return retval3;
2211 }
2212
2213 if (retval != ERROR_OK)
2214 return retval;
2215
2216 return retval2;
2217 }
2218
2219 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2220 {
2221 if (CMD_ARGC != 1)
2222 return ERROR_COMMAND_SYNTAX_ERROR;
2223
2224 struct flash_bank *bank;
2225 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2226 if (retval != ERROR_OK)
2227 return retval;
2228
2229 retval = stm32l4_mass_erase(bank);
2230 if (retval == ERROR_OK)
2231 command_print(CMD, "stm32l4x mass erase complete");
2232 else
2233 command_print(CMD, "stm32l4x mass erase failed");
2234
2235 return retval;
2236 }
2237
2238 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2239 {
2240 if (CMD_ARGC != 2)
2241 return ERROR_COMMAND_SYNTAX_ERROR;
2242
2243 struct flash_bank *bank;
2244 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2245 if (retval != ERROR_OK)
2246 return retval;
2247
2248 uint32_t reg_offset, reg_addr;
2249 uint32_t value = 0;
2250
2251 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2252 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2253
2254 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2255 if (retval != ERROR_OK)
2256 return retval;
2257
2258 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2259
2260 return retval;
2261 }
2262
2263 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2264 {
2265 if (CMD_ARGC != 3 && CMD_ARGC != 4)
2266 return ERROR_COMMAND_SYNTAX_ERROR;
2267
2268 struct flash_bank *bank;
2269 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2270 if (retval != ERROR_OK)
2271 return retval;
2272
2273 uint32_t reg_offset;
2274 uint32_t value = 0;
2275 uint32_t mask = 0xFFFFFFFF;
2276
2277 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2278 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2279
2280 if (CMD_ARGC > 3)
2281 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
2282
2283 command_print(CMD, "%s Option written.\n"
2284 "INFO: a reset or power cycle is required "
2285 "for the new settings to take effect.", bank->driver->name);
2286
2287 retval = stm32l4_write_option(bank, reg_offset, value, mask);
2288 return retval;
2289 }
2290
2291 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2292 {
2293 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2294 return ERROR_COMMAND_SYNTAX_ERROR;
2295
2296 struct flash_bank *bank;
2297 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2298 if (retval != ERROR_OK)
2299 return retval;
2300
2301 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2302 if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2303 LOG_ERROR("This device does not have a TrustZone");
2304 return ERROR_FAIL;
2305 }
2306
2307 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
2308 if (retval != ERROR_OK)
2309 return retval;
2310
2311 stm32l4_sync_rdp_tzen(bank);
2312
2313 if (CMD_ARGC == 1) {
2314 /* only display the TZEN value */
2315 LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2316 return ERROR_OK;
2317 }
2318
2319 bool new_tzen;
2320 COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2321
2322 if (new_tzen == stm32l4_info->tzen) {
2323 LOG_INFO("The requested TZEN is already programmed");
2324 return ERROR_OK;
2325 }
2326
2327 if (new_tzen) {
2328 if (stm32l4_info->rdp != RDP_LEVEL_0) {
2329 LOG_ERROR("TZEN can be set only when RDP level is 0");
2330 return ERROR_FAIL;
2331 }
2332 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2333 FLASH_TZEN, FLASH_TZEN);
2334 } else {
2335 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2336 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2337 if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2338 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2339 return ERROR_FAIL;
2340 }
2341
2342 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2343 RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN);
2344 }
2345
2346 if (retval != ERROR_OK)
2347 return retval;
2348
2349 return stm32l4_perform_obl_launch(bank);
2350 }
2351
2352 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2353 {
2354 if (CMD_ARGC != 1)
2355 return ERROR_COMMAND_SYNTAX_ERROR;
2356
2357 struct flash_bank *bank;
2358 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2359 if (retval != ERROR_OK)
2360 return retval;
2361
2362 retval = stm32l4_perform_obl_launch(bank);
2363 if (retval != ERROR_OK) {
2364 command_print(CMD, "stm32l4x option load failed");
2365 return retval;
2366 }
2367
2368
2369 command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2370
2371 return ERROR_OK;
2372 }
2373
2374 COMMAND_HANDLER(stm32l4_handle_lock_command)
2375 {
2376 struct target *target = NULL;
2377
2378 if (CMD_ARGC != 1)
2379 return ERROR_COMMAND_SYNTAX_ERROR;
2380
2381 struct flash_bank *bank;
2382 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2383 if (retval != ERROR_OK)
2384 return retval;
2385
2386 if (stm32l4_is_otp(bank)) {
2387 LOG_ERROR("cannot lock/unlock OTP memory");
2388 return ERROR_FLASH_OPER_UNSUPPORTED;
2389 }
2390
2391 target = bank->target;
2392
2393 if (target->state != TARGET_HALTED) {
2394 LOG_ERROR("Target not halted");
2395 return ERROR_TARGET_NOT_HALTED;
2396 }
2397
2398 /* set readout protection level 1 by erasing the RDP option byte */
2399 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2400 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2401 RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) {
2402 command_print(CMD, "%s failed to lock device", bank->driver->name);
2403 return ERROR_OK;
2404 }
2405
2406 return ERROR_OK;
2407 }
2408
2409 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2410 {
2411 struct target *target = NULL;
2412
2413 if (CMD_ARGC != 1)
2414 return ERROR_COMMAND_SYNTAX_ERROR;
2415
2416 struct flash_bank *bank;
2417 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2418 if (retval != ERROR_OK)
2419 return retval;
2420
2421 if (stm32l4_is_otp(bank)) {
2422 LOG_ERROR("cannot lock/unlock OTP memory");
2423 return ERROR_FLASH_OPER_UNSUPPORTED;
2424 }
2425
2426 target = bank->target;
2427
2428 if (target->state != TARGET_HALTED) {
2429 LOG_ERROR("Target not halted");
2430 return ERROR_TARGET_NOT_HALTED;
2431 }
2432
2433 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2434 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2435 RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) {
2436 command_print(CMD, "%s failed to unlock device", bank->driver->name);
2437 return ERROR_OK;
2438 }
2439
2440 return ERROR_OK;
2441 }
2442
2443 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2444 {
2445 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2446 return ERROR_COMMAND_SYNTAX_ERROR;
2447
2448 struct flash_bank *bank;
2449 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2450 if (retval != ERROR_OK)
2451 return retval;
2452
2453 if (stm32l4_is_otp(bank)) {
2454 LOG_ERROR("OTP memory does not have write protection areas");
2455 return ERROR_FLASH_OPER_UNSUPPORTED;
2456 }
2457
2458 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2459 enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2460 if (CMD_ARGC == 2) {
2461 if (strcmp(CMD_ARGV[1], "bank1") == 0)
2462 dev_bank_id = STM32_BANK1;
2463 else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2464 dev_bank_id = STM32_BANK2;
2465 else
2466 return ERROR_COMMAND_ARGUMENT_INVALID;
2467 }
2468
2469 if (dev_bank_id == STM32_BANK2) {
2470 if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2471 LOG_ERROR("this device has no second bank");
2472 return ERROR_FAIL;
2473 } else if (!stm32l4_info->dual_bank_mode) {
2474 LOG_ERROR("this device is configured in single bank mode");
2475 return ERROR_FAIL;
2476 }
2477 }
2478
2479 int ret;
2480 unsigned int n_wrp, i;
2481 struct stm32l4_wrp wrpxy[4];
2482
2483 ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2484 if (ret != ERROR_OK)
2485 return ret;
2486
2487 /* use bitmap and range helpers to better describe protected areas */
2488 DECLARE_BITMAP(pages, bank->num_sectors);
2489 bitmap_zero(pages, bank->num_sectors);
2490
2491 for (i = 0; i < n_wrp; i++) {
2492 if (wrpxy[i].used) {
2493 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2494 set_bit(p, pages);
2495 }
2496 }
2497
2498 /* we have at most 'n_wrp' WRP areas */
2499 struct range ranges[n_wrp];
2500 unsigned int ranges_count = 0;
2501
2502 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2503
2504 if (ranges_count > 0) {
2505 /* pretty-print the protected ranges */
2506 char *ranges_str = range_print_alloc(ranges, ranges_count);
2507 command_print(CMD, "protected areas: %s", ranges_str);
2508 free(ranges_str);
2509 } else
2510 command_print(CMD, "no protected areas");
2511
2512 return ERROR_OK;
2513 }
2514
2515 COMMAND_HANDLER(stm32l4_handle_otp_command)
2516 {
2517 if (CMD_ARGC != 2)
2518 return ERROR_COMMAND_SYNTAX_ERROR;
2519
2520 struct flash_bank *bank;
2521 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2522 if (retval != ERROR_OK)
2523 return retval;
2524
2525 if (!stm32l4_is_otp(bank)) {
2526 command_print(CMD, "the specified bank is not an OTP memory");
2527 return ERROR_FAIL;
2528 }
2529 if (strcmp(CMD_ARGV[1], "enable") == 0)
2530 stm32l4_otp_enable(bank, true);
2531 else if (strcmp(CMD_ARGV[1], "disable") == 0)
2532 stm32l4_otp_enable(bank, false);
2533 else if (strcmp(CMD_ARGV[1], "show") == 0)
2534 command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2535 bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2536 else
2537 return ERROR_COMMAND_SYNTAX_ERROR;
2538
2539 return ERROR_OK;
2540 }
2541
2542 static const struct command_registration stm32l4_exec_command_handlers[] = {
2543 {
2544 .name = "lock",
2545 .handler = stm32l4_handle_lock_command,
2546 .mode = COMMAND_EXEC,
2547 .usage = "bank_id",
2548 .help = "Lock entire flash device.",
2549 },
2550 {
2551 .name = "unlock",
2552 .handler = stm32l4_handle_unlock_command,
2553 .mode = COMMAND_EXEC,
2554 .usage = "bank_id",
2555 .help = "Unlock entire protected flash device.",
2556 },
2557 {
2558 .name = "mass_erase",
2559 .handler = stm32l4_handle_mass_erase_command,
2560 .mode = COMMAND_EXEC,
2561 .usage = "bank_id",
2562 .help = "Erase entire flash device.",
2563 },
2564 {
2565 .name = "option_read",
2566 .handler = stm32l4_handle_option_read_command,
2567 .mode = COMMAND_EXEC,
2568 .usage = "bank_id reg_offset",
2569 .help = "Read & Display device option bytes.",
2570 },
2571 {
2572 .name = "option_write",
2573 .handler = stm32l4_handle_option_write_command,
2574 .mode = COMMAND_EXEC,
2575 .usage = "bank_id reg_offset value mask",
2576 .help = "Write device option bit fields with provided value.",
2577 },
2578 {
2579 .name = "trustzone",
2580 .handler = stm32l4_handle_trustzone_command,
2581 .mode = COMMAND_EXEC,
2582 .usage = "<bank_id> [enable|disable]",
2583 .help = "Configure TrustZone security",
2584 },
2585 {
2586 .name = "wrp_info",
2587 .handler = stm32l4_handle_wrp_info_command,
2588 .mode = COMMAND_EXEC,
2589 .usage = "bank_id [bank1|bank2]",
2590 .help = "list the protected areas using WRP",
2591 },
2592 {
2593 .name = "option_load",
2594 .handler = stm32l4_handle_option_load_command,
2595 .mode = COMMAND_EXEC,
2596 .usage = "bank_id",
2597 .help = "Force re-load of device options (will cause device reset).",
2598 },
2599 {
2600 .name = "otp",
2601 .handler = stm32l4_handle_otp_command,
2602 .mode = COMMAND_EXEC,
2603 .usage = "<bank_id> <enable|disable|show>",
2604 .help = "OTP (One Time Programmable) memory write enable/disable",
2605 },
2606 COMMAND_REGISTRATION_DONE
2607 };
2608
2609 static const struct command_registration stm32l4_command_handlers[] = {
2610 {
2611 .name = "stm32l4x",
2612 .mode = COMMAND_ANY,
2613 .help = "stm32l4x flash command group",
2614 .usage = "",
2615 .chain = stm32l4_exec_command_handlers,
2616 },
2617 COMMAND_REGISTRATION_DONE
2618 };
2619
2620 const struct flash_driver stm32l4x_flash = {
2621 .name = "stm32l4x",
2622 .commands = stm32l4_command_handlers,
2623 .flash_bank_command = stm32l4_flash_bank_command,
2624 .erase = stm32l4_erase,
2625 .protect = stm32l4_protect,
2626 .write = stm32l4_write,
2627 .read = default_flash_read,
2628 .probe = stm32l4_probe,
2629 .auto_probe = stm32l4_auto_probe,
2630 .erase_check = default_flash_blank_check,
2631 .protect_check = stm32l4_protect_check,
2632 .info = get_stm32l4_info,
2633 .free_driver_priv = default_flash_free_driver_priv,
2634 };
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