?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
doc: Improve ftdi driver section
[openocd.git] / src / target / mips_m4k.c
blobdb69b95b162b2dd261c2705609b85f599de9eb32
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 * *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
25
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "breakpoints.h"
31 #include "mips32.h"
32 #include "mips_m4k.h"
33 #include "mips32_dmaacc.h"
34 #include "target_type.h"
35 #include "register.h"
36
37 static void mips_m4k_enable_breakpoints(struct target *target);
38 static void mips_m4k_enable_watchpoints(struct target *target);
39 static int mips_m4k_set_breakpoint(struct target *target,
40 struct breakpoint *breakpoint);
41 static int mips_m4k_unset_breakpoint(struct target *target,
42 struct breakpoint *breakpoint);
43 static int mips_m4k_internal_restore(struct target *target, int current,
44 uint32_t address, int handle_breakpoints,
45 int debug_execution);
46 static int mips_m4k_halt(struct target *target);
47 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
48 uint32_t count, const uint8_t *buffer);
49
50 static int mips_m4k_examine_debug_reason(struct target *target)
51 {
52 struct mips32_common *mips32 = target_to_mips32(target);
53 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
54 uint32_t break_status;
55 int retval;
56
57 if ((target->debug_reason != DBG_REASON_DBGRQ)
58 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
59 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
60 /* get info about inst breakpoint support */
61 retval = target_read_u32(target,
62 ejtag_info->ejtag_ibs_addr, &break_status);
63 if (retval != ERROR_OK)
64 return retval;
65 if (break_status & 0x1f) {
66 /* we have halted on a breakpoint */
67 retval = target_write_u32(target,
68 ejtag_info->ejtag_ibs_addr, 0);
69 if (retval != ERROR_OK)
70 return retval;
71 target->debug_reason = DBG_REASON_BREAKPOINT;
72 }
73 }
74
75 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
76 /* get info about data breakpoint support */
77 retval = target_read_u32(target,
78 ejtag_info->ejtag_dbs_addr, &break_status);
79 if (retval != ERROR_OK)
80 return retval;
81 if (break_status & 0x1f) {
82 /* we have halted on a breakpoint */
83 retval = target_write_u32(target,
84 ejtag_info->ejtag_dbs_addr, 0);
85 if (retval != ERROR_OK)
86 return retval;
87 target->debug_reason = DBG_REASON_WATCHPOINT;
88 }
89 }
90 }
91
92 return ERROR_OK;
93 }
94
95 static int mips_m4k_debug_entry(struct target *target)
96 {
97 struct mips32_common *mips32 = target_to_mips32(target);
98 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
99
100 mips32_save_context(target);
101
102 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
103 mips_ejtag_config_step(ejtag_info, 0);
104
105 /* make sure break unit configured */
106 mips32_configure_break_unit(target);
107
108 /* attempt to find halt reason */
109 mips_m4k_examine_debug_reason(target);
110
111 /* default to mips32 isa, it will be changed below if required */
112 mips32->isa_mode = MIPS32_ISA_MIPS32;
113
114 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
115 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
116
117 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
118 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
119 target_state_name(target));
120
121 return ERROR_OK;
122 }
123
124 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
125 {
126 struct target_list *head;
127 struct target *curr;
128
129 head = target->head;
130 while (head != (struct target_list *)NULL) {
131 curr = head->target;
132 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
133 return curr;
134 head = head->next;
135 }
136 return target;
137 }
138
139 static int mips_m4k_halt_smp(struct target *target)
140 {
141 int retval = ERROR_OK;
142 struct target_list *head;
143 struct target *curr;
144 head = target->head;
145 while (head != (struct target_list *)NULL) {
146 int ret = ERROR_OK;
147 curr = head->target;
148 if ((curr != target) && (curr->state != TARGET_HALTED))
149 ret = mips_m4k_halt(curr);
150
151 if (ret != ERROR_OK) {
152 LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
153 retval = ret;
154 }
155 head = head->next;
156 }
157 return retval;
158 }
159
160 static int update_halt_gdb(struct target *target)
161 {
162 int retval = ERROR_OK;
163 if (target->gdb_service->core[0] == -1) {
164 target->gdb_service->target = target;
165 target->gdb_service->core[0] = target->coreid;
166 retval = mips_m4k_halt_smp(target);
167 }
168 return retval;
169 }
170
171 static int mips_m4k_poll(struct target *target)
172 {
173 int retval = ERROR_OK;
174 struct mips32_common *mips32 = target_to_mips32(target);
175 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
176 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
177 enum target_state prev_target_state = target->state;
178
179 /* toggle to another core is done by gdb as follow */
180 /* maint packet J core_id */
181 /* continue */
182 /* the next polling trigger an halt event sent to gdb */
183 if ((target->state == TARGET_HALTED) && (target->smp) &&
184 (target->gdb_service) &&
185 (target->gdb_service->target == NULL)) {
186 target->gdb_service->target =
187 get_mips_m4k(target, target->gdb_service->core[1]);
188 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
189 return retval;
190 }
191
192 /* read ejtag control reg */
193 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
194 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
195 if (retval != ERROR_OK)
196 return retval;
197
198 /* clear this bit before handling polling
199 * as after reset registers will read zero */
200 if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
201 /* we have detected a reset, clear flag
202 * otherwise ejtag will not work */
203 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
204
205 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
206 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
207 if (retval != ERROR_OK)
208 return retval;
209 LOG_DEBUG("Reset Detected");
210 }
211
212 /* check for processor halted */
213 if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
214 if ((target->state != TARGET_HALTED)
215 && (target->state != TARGET_DEBUG_RUNNING)) {
216 if (target->state == TARGET_UNKNOWN)
217 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
218
219 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
220 * (maybe put on by HALT-ing the board in the previous session).
221 *
222 * Force enable debug entry for this session.
223 */
224 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
225 target->state = TARGET_HALTED;
226 retval = mips_m4k_debug_entry(target);
227 if (retval != ERROR_OK)
228 return retval;
229
230 if (target->smp &&
231 ((prev_target_state == TARGET_RUNNING)
232 || (prev_target_state == TARGET_RESET))) {
233 retval = update_halt_gdb(target);
234 if (retval != ERROR_OK)
235 return retval;
236 }
237 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
238 } else if (target->state == TARGET_DEBUG_RUNNING) {
239 target->state = TARGET_HALTED;
240
241 retval = mips_m4k_debug_entry(target);
242 if (retval != ERROR_OK)
243 return retval;
244
245 if (target->smp) {
246 retval = update_halt_gdb(target);
247 if (retval != ERROR_OK)
248 return retval;
249 }
250
251 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
252 }
253 } else
254 target->state = TARGET_RUNNING;
255
256 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
257
258 return ERROR_OK;
259 }
260
261 static int mips_m4k_halt(struct target *target)
262 {
263 struct mips32_common *mips32 = target_to_mips32(target);
264 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
265
266 LOG_DEBUG("target->state: %s", target_state_name(target));
267
268 if (target->state == TARGET_HALTED) {
269 LOG_DEBUG("target was already halted");
270 return ERROR_OK;
271 }
272
273 if (target->state == TARGET_UNKNOWN)
274 LOG_WARNING("target was in unknown state when halt was requested");
275
276 if (target->state == TARGET_RESET) {
277 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
278 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
279 return ERROR_TARGET_FAILURE;
280 } else {
281 /* we came here in a reset_halt or reset_init sequence
282 * debug entry was already prepared in mips_m4k_assert_reset()
283 */
284 target->debug_reason = DBG_REASON_DBGRQ;
285
286 return ERROR_OK;
287 }
288 }
289
290 /* break processor */
291 mips_ejtag_enter_debug(ejtag_info);
292
293 target->debug_reason = DBG_REASON_DBGRQ;
294
295 return ERROR_OK;
296 }
297
298 static int mips_m4k_assert_reset(struct target *target)
299 {
300 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
301 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
302
303 /* TODO: apply hw reset signal in not examined state */
304 if (!(target_was_examined(target))) {
305 LOG_WARNING("Reset is not asserted because the target is not examined.");
306 LOG_WARNING("Use a reset button or power cycle the target.");
307 return ERROR_TARGET_NOT_EXAMINED;
308 }
309
310 LOG_DEBUG("target->state: %s",
311 target_state_name(target));
312
313 enum reset_types jtag_reset_config = jtag_get_reset_config();
314
315 /* some cores support connecting while srst is asserted
316 * use that mode is it has been configured */
317
318 bool srst_asserted = false;
319
320 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
321 (jtag_reset_config & RESET_SRST_NO_GATING)) {
322 jtag_add_reset(0, 1);
323 srst_asserted = true;
324 }
325
326
327 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
328 if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
329 if (target->reset_halt) {
330 /* use hardware to catch reset */
331 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
332 } else
333 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
334 }
335
336 if (jtag_reset_config & RESET_HAS_SRST) {
337 /* here we should issue a srst only, but we may have to assert trst as well */
338 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
339 jtag_add_reset(1, 1);
340 else if (!srst_asserted)
341 jtag_add_reset(0, 1);
342 } else {
343 if (mips_m4k->is_pic32mx) {
344 LOG_DEBUG("Using MTAP reset to reset processor...");
345
346 /* use microchip specific MTAP reset */
347 mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
348 mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
349
350 mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
351 mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
352 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
353 } else {
354 /* use ejtag reset - not supported by all cores */
355 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
356 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
357 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
358 mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
359 }
360 }
361
362 target->state = TARGET_RESET;
363 jtag_add_sleep(50000);
364
365 register_cache_invalidate(mips_m4k->mips32.core_cache);
366
367 if (target->reset_halt) {
368 int retval = target_halt(target);
369 if (retval != ERROR_OK)
370 return retval;
371 }
372
373 return ERROR_OK;
374 }
375
376 static int mips_m4k_deassert_reset(struct target *target)
377 {
378 LOG_DEBUG("target->state: %s", target_state_name(target));
379
380 /* deassert reset lines */
381 jtag_add_reset(0, 0);
382
383 return ERROR_OK;
384 }
385
386 static int mips_m4k_single_step_core(struct target *target)
387 {
388 struct mips32_common *mips32 = target_to_mips32(target);
389 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
390
391 /* configure single step mode */
392 mips_ejtag_config_step(ejtag_info, 1);
393
394 /* disable interrupts while stepping */
395 mips32_enable_interrupts(target, 0);
396
397 /* exit debug mode */
398 mips_ejtag_exit_debug(ejtag_info);
399
400 mips_m4k_debug_entry(target);
401
402 return ERROR_OK;
403 }
404
405 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
406 {
407 int retval = ERROR_OK;
408 struct target_list *head;
409 struct target *curr;
410
411 head = target->head;
412 while (head != (struct target_list *)NULL) {
413 int ret = ERROR_OK;
414 curr = head->target;
415 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
416 /* resume current address , not in step mode */
417 ret = mips_m4k_internal_restore(curr, 1, address,
418 handle_breakpoints, 0);
419
420 if (ret != ERROR_OK) {
421 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
422 curr->coreid, address);
423 retval = ret;
424 }
425 }
426 head = head->next;
427 }
428 return retval;
429 }
430
431 static int mips_m4k_internal_restore(struct target *target, int current,
432 uint32_t address, int handle_breakpoints, int debug_execution)
433 {
434 struct mips32_common *mips32 = target_to_mips32(target);
435 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
436 struct breakpoint *breakpoint = NULL;
437 uint32_t resume_pc;
438
439 if (target->state != TARGET_HALTED) {
440 LOG_WARNING("target not halted");
441 return ERROR_TARGET_NOT_HALTED;
442 }
443
444 if (!debug_execution) {
445 target_free_all_working_areas(target);
446 mips_m4k_enable_breakpoints(target);
447 mips_m4k_enable_watchpoints(target);
448 }
449
450 /* current = 1: continue on current pc, otherwise continue at <address> */
451 if (!current) {
452 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
453 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
454 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
455 }
456
457 if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
458 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
459
460 if (!current)
461 resume_pc = address;
462 else
463 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
464
465 mips32_restore_context(target);
466
467 /* the front-end may request us not to handle breakpoints */
468 if (handle_breakpoints) {
469 /* Single step past breakpoint at current address */
470 breakpoint = breakpoint_find(target, resume_pc);
471 if (breakpoint) {
472 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
473 mips_m4k_unset_breakpoint(target, breakpoint);
474 mips_m4k_single_step_core(target);
475 mips_m4k_set_breakpoint(target, breakpoint);
476 }
477 }
478
479 /* enable interrupts if we are running */
480 mips32_enable_interrupts(target, !debug_execution);
481
482 /* exit debug mode */
483 mips_ejtag_exit_debug(ejtag_info);
484 target->debug_reason = DBG_REASON_NOTHALTED;
485
486 /* registers are now invalid */
487 register_cache_invalidate(mips32->core_cache);
488
489 if (!debug_execution) {
490 target->state = TARGET_RUNNING;
491 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
492 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
493 } else {
494 target->state = TARGET_DEBUG_RUNNING;
495 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
496 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
497 }
498
499 return ERROR_OK;
500 }
501
502 static int mips_m4k_resume(struct target *target, int current,
503 uint32_t address, int handle_breakpoints, int debug_execution)
504 {
505 int retval = ERROR_OK;
506
507 /* dummy resume for smp toggle in order to reduce gdb impact */
508 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
509 /* simulate a start and halt of target */
510 target->gdb_service->target = NULL;
511 target->gdb_service->core[0] = target->gdb_service->core[1];
512 /* fake resume at next poll we play the target core[1], see poll*/
513 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
514 return retval;
515 }
516
517 retval = mips_m4k_internal_restore(target, current, address,
518 handle_breakpoints,
519 debug_execution);
520
521 if (retval == ERROR_OK && target->smp) {
522 target->gdb_service->core[0] = -1;
523 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
524 }
525
526 return retval;
527 }
528
529 static int mips_m4k_step(struct target *target, int current,
530 uint32_t address, int handle_breakpoints)
531 {
532 /* get pointers to arch-specific information */
533 struct mips32_common *mips32 = target_to_mips32(target);
534 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
535 struct breakpoint *breakpoint = NULL;
536
537 if (target->state != TARGET_HALTED) {
538 LOG_WARNING("target not halted");
539 return ERROR_TARGET_NOT_HALTED;
540 }
541
542 /* current = 1: continue on current pc, otherwise continue at <address> */
543 if (!current) {
544 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
545 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
546 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
547 }
548
549 /* the front-end may request us not to handle breakpoints */
550 if (handle_breakpoints) {
551 breakpoint = breakpoint_find(target,
552 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
553 if (breakpoint)
554 mips_m4k_unset_breakpoint(target, breakpoint);
555 }
556
557 /* restore context */
558 mips32_restore_context(target);
559
560 /* configure single step mode */
561 mips_ejtag_config_step(ejtag_info, 1);
562
563 target->debug_reason = DBG_REASON_SINGLESTEP;
564
565 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
566
567 /* disable interrupts while stepping */
568 mips32_enable_interrupts(target, 0);
569
570 /* exit debug mode */
571 mips_ejtag_exit_debug(ejtag_info);
572
573 /* registers are now invalid */
574 register_cache_invalidate(mips32->core_cache);
575
576 LOG_DEBUG("target stepped ");
577 mips_m4k_debug_entry(target);
578
579 if (breakpoint)
580 mips_m4k_set_breakpoint(target, breakpoint);
581
582 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
583
584 return ERROR_OK;
585 }
586
587 static void mips_m4k_enable_breakpoints(struct target *target)
588 {
589 struct breakpoint *breakpoint = target->breakpoints;
590
591 /* set any pending breakpoints */
592 while (breakpoint) {
593 if (breakpoint->set == 0)
594 mips_m4k_set_breakpoint(target, breakpoint);
595 breakpoint = breakpoint->next;
596 }
597 }
598
599 static int mips_m4k_set_breakpoint(struct target *target,
600 struct breakpoint *breakpoint)
601 {
602 struct mips32_common *mips32 = target_to_mips32(target);
603 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
604 struct mips32_comparator *comparator_list = mips32->inst_break_list;
605 int retval;
606
607 if (breakpoint->set) {
608 LOG_WARNING("breakpoint already set");
609 return ERROR_OK;
610 }
611
612 if (breakpoint->type == BKPT_HARD) {
613 int bp_num = 0;
614
615 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
616 bp_num++;
617 if (bp_num >= mips32->num_inst_bpoints) {
618 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
619 breakpoint->unique_id);
620 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
621 }
622 breakpoint->set = bp_num + 1;
623 comparator_list[bp_num].used = 1;
624 comparator_list[bp_num].bp_value = breakpoint->address;
625
626 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
627 * Warning: there is no IB ASID registers in 2.0.
628 * Do not set it! :) */
629 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
630 comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
631
632 target_write_u32(target, comparator_list[bp_num].reg_address,
633 comparator_list[bp_num].bp_value);
634 target_write_u32(target, comparator_list[bp_num].reg_address +
635 ejtag_info->ejtag_ibm_offs, 0x00000000);
636 target_write_u32(target, comparator_list[bp_num].reg_address +
637 ejtag_info->ejtag_ibc_offs, 1);
638 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
639 breakpoint->unique_id,
640 bp_num, comparator_list[bp_num].bp_value);
641 } else if (breakpoint->type == BKPT_SOFT) {
642 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
643 if (breakpoint->length == 4) {
644 uint32_t verify = 0xffffffff;
645
646 retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
647 breakpoint->orig_instr);
648 if (retval != ERROR_OK)
649 return retval;
650 retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
651 if (retval != ERROR_OK)
652 return retval;
653
654 retval = target_read_u32(target, breakpoint->address, &verify);
655 if (retval != ERROR_OK)
656 return retval;
657 if (verify != MIPS32_SDBBP) {
658 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
659 " - check that memory is read/writable", breakpoint->address);
660 return ERROR_OK;
661 }
662 } else {
663 uint16_t verify = 0xffff;
664
665 retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
666 breakpoint->orig_instr);
667 if (retval != ERROR_OK)
668 return retval;
669 retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
670 if (retval != ERROR_OK)
671 return retval;
672
673 retval = target_read_u16(target, breakpoint->address, &verify);
674 if (retval != ERROR_OK)
675 return retval;
676 if (verify != MIPS16_SDBBP) {
677 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
678 " - check that memory is read/writable", breakpoint->address);
679 return ERROR_OK;
680 }
681 }
682
683 breakpoint->set = 20; /* Any nice value but 0 */
684 }
685
686 return ERROR_OK;
687 }
688
689 static int mips_m4k_unset_breakpoint(struct target *target,
690 struct breakpoint *breakpoint)
691 {
692 /* get pointers to arch-specific information */
693 struct mips32_common *mips32 = target_to_mips32(target);
694 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
695 struct mips32_comparator *comparator_list = mips32->inst_break_list;
696 int retval;
697
698 if (!breakpoint->set) {
699 LOG_WARNING("breakpoint not set");
700 return ERROR_OK;
701 }
702
703 if (breakpoint->type == BKPT_HARD) {
704 int bp_num = breakpoint->set - 1;
705 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
706 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
707 breakpoint->unique_id);
708 return ERROR_OK;
709 }
710 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
711 breakpoint->unique_id,
712 bp_num);
713 comparator_list[bp_num].used = 0;
714 comparator_list[bp_num].bp_value = 0;
715 target_write_u32(target, comparator_list[bp_num].reg_address +
716 ejtag_info->ejtag_ibc_offs, 0);
717
718 } else {
719 /* restore original instruction (kept in target endianness) */
720 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
721 if (breakpoint->length == 4) {
722 uint32_t current_instr;
723
724 /* check that user program has not modified breakpoint instruction */
725 retval = target_read_memory(target, breakpoint->address, 4, 1,
726 (uint8_t *)&current_instr);
727 if (retval != ERROR_OK)
728 return retval;
729
730 /**
731 * target_read_memory() gets us data in _target_ endianess.
732 * If we want to use this data on the host for comparisons with some macros
733 * we must first transform it to _host_ endianess using target_buffer_get_u32().
734 */
735 current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
736
737 if (current_instr == MIPS32_SDBBP) {
738 retval = target_write_memory(target, breakpoint->address, 4, 1,
739 breakpoint->orig_instr);
740 if (retval != ERROR_OK)
741 return retval;
742 }
743 } else {
744 uint16_t current_instr;
745
746 /* check that user program has not modified breakpoint instruction */
747 retval = target_read_memory(target, breakpoint->address, 2, 1,
748 (uint8_t *)&current_instr);
749 if (retval != ERROR_OK)
750 return retval;
751 current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
752 if (current_instr == MIPS16_SDBBP) {
753 retval = target_write_memory(target, breakpoint->address, 2, 1,
754 breakpoint->orig_instr);
755 if (retval != ERROR_OK)
756 return retval;
757 }
758 }
759 }
760 breakpoint->set = 0;
761
762 return ERROR_OK;
763 }
764
765 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
766 {
767 struct mips32_common *mips32 = target_to_mips32(target);
768
769 if (breakpoint->type == BKPT_HARD) {
770 if (mips32->num_inst_bpoints_avail < 1) {
771 LOG_INFO("no hardware breakpoint available");
772 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
773 }
774
775 mips32->num_inst_bpoints_avail--;
776 }
777
778 return mips_m4k_set_breakpoint(target, breakpoint);
779 }
780
781 static int mips_m4k_remove_breakpoint(struct target *target,
782 struct breakpoint *breakpoint)
783 {
784 /* get pointers to arch-specific information */
785 struct mips32_common *mips32 = target_to_mips32(target);
786
787 if (target->state != TARGET_HALTED) {
788 LOG_WARNING("target not halted");
789 return ERROR_TARGET_NOT_HALTED;
790 }
791
792 if (breakpoint->set)
793 mips_m4k_unset_breakpoint(target, breakpoint);
794
795 if (breakpoint->type == BKPT_HARD)
796 mips32->num_inst_bpoints_avail++;
797
798 return ERROR_OK;
799 }
800
801 static int mips_m4k_set_watchpoint(struct target *target,
802 struct watchpoint *watchpoint)
803 {
804 struct mips32_common *mips32 = target_to_mips32(target);
805 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
806 struct mips32_comparator *comparator_list = mips32->data_break_list;
807 int wp_num = 0;
808 /*
809 * watchpoint enabled, ignore all byte lanes in value register
810 * and exclude both load and store accesses from watchpoint
811 * condition evaluation
812 */
813 int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
814 (0xff << EJTAG_DBCn_BLM_SHIFT);
815
816 if (watchpoint->set) {
817 LOG_WARNING("watchpoint already set");
818 return ERROR_OK;
819 }
820
821 while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
822 wp_num++;
823 if (wp_num >= mips32->num_data_bpoints) {
824 LOG_ERROR("Can not find free FP Comparator");
825 return ERROR_FAIL;
826 }
827
828 if (watchpoint->length != 4) {
829 LOG_ERROR("Only watchpoints of length 4 are supported");
830 return ERROR_TARGET_UNALIGNED_ACCESS;
831 }
832
833 if (watchpoint->address % 4) {
834 LOG_ERROR("Watchpoints address should be word aligned");
835 return ERROR_TARGET_UNALIGNED_ACCESS;
836 }
837
838 switch (watchpoint->rw) {
839 case WPT_READ:
840 enable &= ~EJTAG_DBCn_NOLB;
841 break;
842 case WPT_WRITE:
843 enable &= ~EJTAG_DBCn_NOSB;
844 break;
845 case WPT_ACCESS:
846 enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
847 break;
848 default:
849 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
850 }
851
852 watchpoint->set = wp_num + 1;
853 comparator_list[wp_num].used = 1;
854 comparator_list[wp_num].bp_value = watchpoint->address;
855
856 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
857 * There is as well no ASID register support. */
858 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
859 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
860 else
861 target_write_u32(target, comparator_list[wp_num].reg_address +
862 ejtag_info->ejtag_dbasid_offs, 0x00000000);
863
864 target_write_u32(target, comparator_list[wp_num].reg_address,
865 comparator_list[wp_num].bp_value);
866 target_write_u32(target, comparator_list[wp_num].reg_address +
867 ejtag_info->ejtag_dbm_offs, 0x00000000);
868
869 target_write_u32(target, comparator_list[wp_num].reg_address +
870 ejtag_info->ejtag_dbc_offs, enable);
871 /* TODO: probably this value is ignored on 2.0 */
872 target_write_u32(target, comparator_list[wp_num].reg_address +
873 ejtag_info->ejtag_dbv_offs, 0);
874 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
875
876 return ERROR_OK;
877 }
878
879 static int mips_m4k_unset_watchpoint(struct target *target,
880 struct watchpoint *watchpoint)
881 {
882 /* get pointers to arch-specific information */
883 struct mips32_common *mips32 = target_to_mips32(target);
884 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
885 struct mips32_comparator *comparator_list = mips32->data_break_list;
886
887 if (!watchpoint->set) {
888 LOG_WARNING("watchpoint not set");
889 return ERROR_OK;
890 }
891
892 int wp_num = watchpoint->set - 1;
893 if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
894 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
895 return ERROR_OK;
896 }
897 comparator_list[wp_num].used = 0;
898 comparator_list[wp_num].bp_value = 0;
899 target_write_u32(target, comparator_list[wp_num].reg_address +
900 ejtag_info->ejtag_dbc_offs, 0);
901 watchpoint->set = 0;
902
903 return ERROR_OK;
904 }
905
906 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
907 {
908 struct mips32_common *mips32 = target_to_mips32(target);
909
910 if (mips32->num_data_bpoints_avail < 1) {
911 LOG_INFO("no hardware watchpoints available");
912 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
913 }
914
915 mips32->num_data_bpoints_avail--;
916
917 mips_m4k_set_watchpoint(target, watchpoint);
918 return ERROR_OK;
919 }
920
921 static int mips_m4k_remove_watchpoint(struct target *target,
922 struct watchpoint *watchpoint)
923 {
924 /* get pointers to arch-specific information */
925 struct mips32_common *mips32 = target_to_mips32(target);
926
927 if (target->state != TARGET_HALTED) {
928 LOG_WARNING("target not halted");
929 return ERROR_TARGET_NOT_HALTED;
930 }
931
932 if (watchpoint->set)
933 mips_m4k_unset_watchpoint(target, watchpoint);
934
935 mips32->num_data_bpoints_avail++;
936
937 return ERROR_OK;
938 }
939
940 static void mips_m4k_enable_watchpoints(struct target *target)
941 {
942 struct watchpoint *watchpoint = target->watchpoints;
943
944 /* set any pending watchpoints */
945 while (watchpoint) {
946 if (watchpoint->set == 0)
947 mips_m4k_set_watchpoint(target, watchpoint);
948 watchpoint = watchpoint->next;
949 }
950 }
951
952 static int mips_m4k_read_memory(struct target *target, uint32_t address,
953 uint32_t size, uint32_t count, uint8_t *buffer)
954 {
955 struct mips32_common *mips32 = target_to_mips32(target);
956 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
957
958 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
959 address, size, count);
960
961 if (target->state != TARGET_HALTED) {
962 LOG_WARNING("target not halted");
963 return ERROR_TARGET_NOT_HALTED;
964 }
965
966 /* sanitize arguments */
967 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
968 return ERROR_COMMAND_SYNTAX_ERROR;
969
970 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
971 return ERROR_TARGET_UNALIGNED_ACCESS;
972
973 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
974 void *t = NULL;
975
976 if (size > 1) {
977 t = malloc(count * size * sizeof(uint8_t));
978 if (t == NULL) {
979 LOG_ERROR("Out of memory");
980 return ERROR_FAIL;
981 }
982 } else
983 t = buffer;
984
985 /* if noDMA off, use DMAACC mode for memory read */
986 int retval;
987 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
988 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
989 else
990 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
991
992 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
993 /* endianness, but byte array should represent target endianness */
994 if (ERROR_OK == retval) {
995 switch (size) {
996 case 4:
997 target_buffer_set_u32_array(target, buffer, count, t);
998 break;
999 case 2:
1000 target_buffer_set_u16_array(target, buffer, count, t);
1001 break;
1002 }
1003 }
1004
1005 if ((size > 1) && (t != NULL))
1006 free(t);
1007
1008 return retval;
1009 }
1010
1011 static int mips_m4k_write_memory(struct target *target, uint32_t address,
1012 uint32_t size, uint32_t count, const uint8_t *buffer)
1013 {
1014 struct mips32_common *mips32 = target_to_mips32(target);
1015 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1016
1017 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1018 address, size, count);
1019
1020 if (target->state != TARGET_HALTED) {
1021 LOG_WARNING("target not halted");
1022 return ERROR_TARGET_NOT_HALTED;
1023 }
1024
1025 if (size == 4 && count > 32) {
1026 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1027 if (retval == ERROR_OK)
1028 return ERROR_OK;
1029 LOG_WARNING("Falling back to non-bulk write");
1030 }
1031
1032 /* sanitize arguments */
1033 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1034 return ERROR_COMMAND_SYNTAX_ERROR;
1035
1036 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1037 return ERROR_TARGET_UNALIGNED_ACCESS;
1038
1039 /** correct endianess if we have word or hword access */
1040 void *t = NULL;
1041 if (size > 1) {
1042 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1043 /* endianness, but byte array represents target endianness */
1044 t = malloc(count * size * sizeof(uint8_t));
1045 if (t == NULL) {
1046 LOG_ERROR("Out of memory");
1047 return ERROR_FAIL;
1048 }
1049
1050 switch (size) {
1051 case 4:
1052 target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1053 break;
1054 case 2:
1055 target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1056 break;
1057 }
1058 buffer = t;
1059 }
1060
1061 /* if noDMA off, use DMAACC mode for memory write */
1062 int retval;
1063 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1064 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1065 else
1066 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1067
1068 if (t != NULL)
1069 free(t);
1070
1071 if (ERROR_OK != retval)
1072 return retval;
1073
1074 return ERROR_OK;
1075 }
1076
1077 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1078 struct target *target)
1079 {
1080 mips32_build_reg_cache(target);
1081
1082 return ERROR_OK;
1083 }
1084
1085 static int mips_m4k_init_arch_info(struct target *target,
1086 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1087 {
1088 struct mips32_common *mips32 = &mips_m4k->mips32;
1089
1090 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1091
1092 /* initialize mips4k specific info */
1093 mips32_init_arch_info(target, mips32, tap);
1094 mips32->arch_info = mips_m4k;
1095
1096 return ERROR_OK;
1097 }
1098
1099 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1100 {
1101 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1102
1103 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1104
1105 return ERROR_OK;
1106 }
1107
1108 static int mips_m4k_examine(struct target *target)
1109 {
1110 int retval;
1111 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1112 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1113 uint32_t idcode = 0;
1114
1115 if (!target_was_examined(target)) {
1116 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1117 if (retval != ERROR_OK)
1118 return retval;
1119 ejtag_info->idcode = idcode;
1120
1121 if (((idcode >> 1) & 0x7FF) == 0x29) {
1122 /* we are using a pic32mx so select ejtag port
1123 * as it is not selected by default */
1124 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1125 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1126 mips_m4k->is_pic32mx = true;
1127 }
1128 }
1129
1130 /* init rest of ejtag interface */
1131 retval = mips_ejtag_init(ejtag_info);
1132 if (retval != ERROR_OK)
1133 return retval;
1134
1135 retval = mips32_examine(target);
1136 if (retval != ERROR_OK)
1137 return retval;
1138
1139 return ERROR_OK;
1140 }
1141
1142 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
1143 uint32_t count, const uint8_t *buffer)
1144 {
1145 struct mips32_common *mips32 = target_to_mips32(target);
1146 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1147 struct working_area *fast_data_area;
1148 int retval;
1149 int write_t = 1;
1150
1151 LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
1152
1153 /* check alignment */
1154 if (address & 0x3u)
1155 return ERROR_TARGET_UNALIGNED_ACCESS;
1156
1157 if (mips32->fast_data_area == NULL) {
1158 /* Get memory for block write handler
1159 * we preserve this area between calls and gain a speed increase
1160 * of about 3kb/sec when writing flash
1161 * this will be released/nulled by the system when the target is resumed or reset */
1162 retval = target_alloc_working_area(target,
1163 MIPS32_FASTDATA_HANDLER_SIZE,
1164 &mips32->fast_data_area);
1165 if (retval != ERROR_OK) {
1166 LOG_ERROR("No working area available");
1167 return retval;
1168 }
1169
1170 /* reset fastadata state so the algo get reloaded */
1171 ejtag_info->fast_access_save = -1;
1172 }
1173
1174 fast_data_area = mips32->fast_data_area;
1175
1176 if (address <= fast_data_area->address + fast_data_area->size &&
1177 fast_data_area->address <= address + count) {
1178 LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area "
1179 "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").",
1180 fast_data_area->address, address, address + count);
1181 LOG_ERROR("Change work-area-phys or load_image address!");
1182 return ERROR_FAIL;
1183 }
1184
1185 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1186 /* but byte array represents target endianness */
1187 uint32_t *t = NULL;
1188 t = malloc(count * sizeof(uint32_t));
1189 if (t == NULL) {
1190 LOG_ERROR("Out of memory");
1191 return ERROR_FAIL;
1192 }
1193
1194 target_buffer_get_u32_array(target, buffer, count, t);
1195
1196 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1197 count, t);
1198
1199 if (t != NULL)
1200 free(t);
1201
1202 if (retval != ERROR_OK)
1203 LOG_ERROR("Fastdata access Failed");
1204
1205 return retval;
1206 }
1207
1208 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1209 struct mips_m4k_common *mips_m4k)
1210 {
1211 if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1212 command_print(cmd_ctx, "target is not an MIPS_M4K");
1213 return ERROR_TARGET_INVALID;
1214 }
1215 return ERROR_OK;
1216 }
1217
1218 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1219 {
1220 int retval;
1221 struct target *target = get_current_target(CMD_CTX);
1222 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1223 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1224
1225 retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1226 if (retval != ERROR_OK)
1227 return retval;
1228
1229 if (target->state != TARGET_HALTED) {
1230 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1231 return ERROR_OK;
1232 }
1233
1234 /* two or more argument, access a single register/select (write if third argument is given) */
1235 if (CMD_ARGC < 2)
1236 return ERROR_COMMAND_SYNTAX_ERROR;
1237 else {
1238 uint32_t cp0_reg, cp0_sel;
1239 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1240 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1241
1242 if (CMD_ARGC == 2) {
1243 uint32_t value;
1244 retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1245 if (retval != ERROR_OK) {
1246 command_print(CMD_CTX,
1247 "couldn't access reg %" PRIi32,
1248 cp0_reg);
1249 return ERROR_OK;
1250 }
1251 command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1252 cp0_reg, cp0_sel, value);
1253
1254 } else if (CMD_ARGC == 3) {
1255 uint32_t value;
1256 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1257 retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1258 if (retval != ERROR_OK) {
1259 command_print(CMD_CTX,
1260 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1261 cp0_reg, cp0_sel);
1262 return ERROR_OK;
1263 }
1264 command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1265 cp0_reg, cp0_sel, value);
1266 }
1267 }
1268
1269 return ERROR_OK;
1270 }
1271
1272 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1273 {
1274 struct target *target = get_current_target(CMD_CTX);
1275 /* check target is an smp target */
1276 struct target_list *head;
1277 struct target *curr;
1278 head = target->head;
1279 target->smp = 0;
1280 if (head != (struct target_list *)NULL) {
1281 while (head != (struct target_list *)NULL) {
1282 curr = head->target;
1283 curr->smp = 0;
1284 head = head->next;
1285 }
1286 /* fixes the target display to the debugger */
1287 target->gdb_service->target = target;
1288 }
1289 return ERROR_OK;
1290 }
1291
1292 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1293 {
1294 struct target *target = get_current_target(CMD_CTX);
1295 struct target_list *head;
1296 struct target *curr;
1297 head = target->head;
1298 if (head != (struct target_list *)NULL) {
1299 target->smp = 1;
1300 while (head != (struct target_list *)NULL) {
1301 curr = head->target;
1302 curr->smp = 1;
1303 head = head->next;
1304 }
1305 }
1306 return ERROR_OK;
1307 }
1308
1309 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1310 {
1311 struct target *target = get_current_target(CMD_CTX);
1312 int retval = ERROR_OK;
1313 struct target_list *head;
1314 head = target->head;
1315 if (head != (struct target_list *)NULL) {
1316 if (CMD_ARGC == 1) {
1317 int coreid = 0;
1318 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1319 if (ERROR_OK != retval)
1320 return retval;
1321 target->gdb_service->core[1] = coreid;
1322
1323 }
1324 command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
1325 , target->gdb_service->core[1]);
1326 }
1327 return ERROR_OK;
1328 }
1329
1330 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1331 {
1332 struct target *target = get_current_target(CMD_CTX);
1333 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1334 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1335
1336 if (CMD_ARGC == 1)
1337 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1338 else if (CMD_ARGC > 1)
1339 return ERROR_COMMAND_SYNTAX_ERROR;
1340
1341 command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1342 if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1343 ejtag_info->mode = 0;
1344 command_print(CMD_CTX, "running in legacy mode");
1345 } else {
1346 ejtag_info->mode = 1;
1347 command_print(CMD_CTX, "running in fast queued mode");
1348 }
1349
1350 return ERROR_OK;
1351 }
1352
1353 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1354 {
1355 .name = "cp0",
1356 .handler = mips_m4k_handle_cp0_command,
1357 .mode = COMMAND_EXEC,
1358 .usage = "regnum [value]",
1359 .help = "display/modify cp0 register",
1360 },
1361 {
1362 .name = "smp_off",
1363 .handler = mips_m4k_handle_smp_off_command,
1364 .mode = COMMAND_EXEC,
1365 .help = "Stop smp handling",
1366 .usage = "",},
1367
1368 {
1369 .name = "smp_on",
1370 .handler = mips_m4k_handle_smp_on_command,
1371 .mode = COMMAND_EXEC,
1372 .help = "Restart smp handling",
1373 .usage = "",
1374 },
1375 {
1376 .name = "smp_gdb",
1377 .handler = mips_m4k_handle_smp_gdb_command,
1378 .mode = COMMAND_EXEC,
1379 .help = "display/fix current core played to gdb",
1380 .usage = "",
1381 },
1382 {
1383 .name = "scan_delay",
1384 .handler = mips_m4k_handle_scan_delay_command,
1385 .mode = COMMAND_ANY,
1386 .help = "display/set scan delay in nano seconds",
1387 .usage = "[value]",
1388 },
1389 COMMAND_REGISTRATION_DONE
1390 };
1391
1392 const struct command_registration mips_m4k_command_handlers[] = {
1393 {
1394 .chain = mips32_command_handlers,
1395 },
1396 {
1397 .name = "mips_m4k",
1398 .mode = COMMAND_ANY,
1399 .help = "mips_m4k command group",
1400 .usage = "",
1401 .chain = mips_m4k_exec_command_handlers,
1402 },
1403 COMMAND_REGISTRATION_DONE
1404 };
1405
1406 struct target_type mips_m4k_target = {
1407 .name = "mips_m4k",
1408
1409 .poll = mips_m4k_poll,
1410 .arch_state = mips32_arch_state,
1411
1412 .halt = mips_m4k_halt,
1413 .resume = mips_m4k_resume,
1414 .step = mips_m4k_step,
1415
1416 .assert_reset = mips_m4k_assert_reset,
1417 .deassert_reset = mips_m4k_deassert_reset,
1418
1419 .get_gdb_reg_list = mips32_get_gdb_reg_list,
1420
1421 .read_memory = mips_m4k_read_memory,
1422 .write_memory = mips_m4k_write_memory,
1423 .checksum_memory = mips32_checksum_memory,
1424 .blank_check_memory = mips32_blank_check_memory,
1425
1426 .run_algorithm = mips32_run_algorithm,
1427
1428 .add_breakpoint = mips_m4k_add_breakpoint,
1429 .remove_breakpoint = mips_m4k_remove_breakpoint,
1430 .add_watchpoint = mips_m4k_add_watchpoint,
1431 .remove_watchpoint = mips_m4k_remove_watchpoint,
1432
1433 .commands = mips_m4k_command_handlers,
1434 .target_create = mips_m4k_target_create,
1435 .init_target = mips_m4k_init_target,
1436 .examine = mips_m4k_examine,
1437 };
Official OpenOCD Mirror