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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / mips_m4k.c
blobad98089614cd6e4577fefe5d5b057ad3996baa83
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2008 by Spencer Oliver *
5 * spen@spen-soft.co.uk *
6 * *
7 * Copyright (C) 2008 by David T.L. Wong *
8 * *
9 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
10 * *
11 * Copyright (C) 2011 by Drasko DRASKOVIC *
12 * drasko.draskovic@gmail.com *
13 ***************************************************************************/
14
15 #ifdef HAVE_CONFIG_H
16 #include "config.h"
17 #endif
18
19 #include "breakpoints.h"
20 #include "mips32.h"
21 #include "mips_m4k.h"
22 #include "mips32_dmaacc.h"
23 #include "target_type.h"
24 #include "register.h"
25 #include "smp.h"
26
27 static void mips_m4k_enable_breakpoints(struct target *target);
28 static void mips_m4k_enable_watchpoints(struct target *target);
29 static int mips_m4k_set_breakpoint(struct target *target,
30 struct breakpoint *breakpoint);
31 static int mips_m4k_unset_breakpoint(struct target *target,
32 struct breakpoint *breakpoint);
33 static int mips_m4k_internal_restore(struct target *target, int current,
34 target_addr_t address, int handle_breakpoints,
35 int debug_execution);
36 static int mips_m4k_halt(struct target *target);
37 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
38 uint32_t count, const uint8_t *buffer);
39 static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t address,
40 uint32_t count, uint8_t *buffer);
41
42 static int mips_m4k_examine_debug_reason(struct target *target)
43 {
44 struct mips32_common *mips32 = target_to_mips32(target);
45 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
46 uint32_t break_status;
47 int retval;
48
49 if ((target->debug_reason != DBG_REASON_DBGRQ)
50 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
51 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
52 /* get info about inst breakpoint support */
53 retval = target_read_u32(target,
54 ejtag_info->ejtag_ibs_addr, &break_status);
55 if (retval != ERROR_OK)
56 return retval;
57 if (break_status & 0x1f) {
58 /* we have halted on a breakpoint */
59 retval = target_write_u32(target,
60 ejtag_info->ejtag_ibs_addr, 0);
61 if (retval != ERROR_OK)
62 return retval;
63 target->debug_reason = DBG_REASON_BREAKPOINT;
64 }
65 }
66
67 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
68 /* get info about data breakpoint support */
69 retval = target_read_u32(target,
70 ejtag_info->ejtag_dbs_addr, &break_status);
71 if (retval != ERROR_OK)
72 return retval;
73 if (break_status & 0x1f) {
74 /* we have halted on a breakpoint */
75 retval = target_write_u32(target,
76 ejtag_info->ejtag_dbs_addr, 0);
77 if (retval != ERROR_OK)
78 return retval;
79 target->debug_reason = DBG_REASON_WATCHPOINT;
80 }
81 }
82 }
83
84 return ERROR_OK;
85 }
86
87 static int mips_m4k_debug_entry(struct target *target)
88 {
89 struct mips32_common *mips32 = target_to_mips32(target);
90 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
91
92 mips32_save_context(target);
93
94 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
95 mips_ejtag_config_step(ejtag_info, 0);
96
97 /* make sure break unit configured */
98 mips32_configure_break_unit(target);
99
100 /* attempt to find halt reason */
101 mips_m4k_examine_debug_reason(target);
102
103 mips32_cpu_probe(target);
104
105 mips32_read_config_regs(target);
106
107 /* default to mips32 isa, it will be changed below if required */
108 mips32->isa_mode = MIPS32_ISA_MIPS32;
109
110 /* other than mips32 only and isa bit set ? */
111 if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1))
112 mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;
113
114 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
115 buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32),
116 target_state_name(target));
117
118 return ERROR_OK;
119 }
120
121 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
122 {
123 struct target_list *head;
124
125 foreach_smp_target(head, target->smp_targets) {
126 struct target *curr = head->target;
127 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
128 return curr;
129 }
130 return target;
131 }
132
133 static int mips_m4k_halt_smp(struct target *target)
134 {
135 int retval = ERROR_OK;
136 struct target_list *head;
137
138 foreach_smp_target(head, target->smp_targets) {
139 int ret = ERROR_OK;
140 struct target *curr = head->target;
141 if ((curr != target) && (curr->state != TARGET_HALTED))
142 ret = mips_m4k_halt(curr);
143
144 if (ret != ERROR_OK) {
145 LOG_TARGET_ERROR(curr, "halt failed.");
146 retval = ret;
147 }
148 }
149 return retval;
150 }
151
152 static int update_halt_gdb(struct target *target)
153 {
154 int retval = ERROR_OK;
155 if (target->gdb_service->core[0] == -1) {
156 target->gdb_service->target = target;
157 target->gdb_service->core[0] = target->coreid;
158 retval = mips_m4k_halt_smp(target);
159 }
160 return retval;
161 }
162
163 static int mips_m4k_poll(struct target *target)
164 {
165 int retval = ERROR_OK;
166 struct mips32_common *mips32 = target_to_mips32(target);
167 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
168 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
169 enum target_state prev_target_state = target->state;
170
171 /* toggle to another core is done by gdb as follow */
172 /* maint packet J core_id */
173 /* continue */
174 /* the next polling trigger an halt event sent to gdb */
175 if ((target->state == TARGET_HALTED) && (target->smp) &&
176 (target->gdb_service) &&
177 (!target->gdb_service->target)) {
178 target->gdb_service->target =
179 get_mips_m4k(target, target->gdb_service->core[1]);
180 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
181 return retval;
182 }
183
184 /* read ejtag control reg */
185 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
186 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
187 if (retval != ERROR_OK)
188 return retval;
189
190 ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;
191
192 /* clear this bit before handling polling
193 * as after reset registers will read zero */
194 if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
195 /* we have detected a reset, clear flag
196 * otherwise ejtag will not work */
197 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
198
199 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
200 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
201 if (retval != ERROR_OK)
202 return retval;
203 LOG_DEBUG("Reset Detected");
204 }
205
206 /* check for processor halted */
207 if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
208 if ((target->state != TARGET_HALTED)
209 && (target->state != TARGET_DEBUG_RUNNING)) {
210 if (target->state == TARGET_UNKNOWN)
211 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
212
213 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
214 * (maybe put on by HALT-ing the board in the previous session).
215 *
216 * Force enable debug entry for this session.
217 */
218 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
219 target->state = TARGET_HALTED;
220 retval = mips_m4k_debug_entry(target);
221 if (retval != ERROR_OK)
222 return retval;
223
224 if (target->smp &&
225 ((prev_target_state == TARGET_RUNNING)
226 || (prev_target_state == TARGET_RESET))) {
227 retval = update_halt_gdb(target);
228 if (retval != ERROR_OK)
229 return retval;
230 }
231 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
232 } else if (target->state == TARGET_DEBUG_RUNNING) {
233 target->state = TARGET_HALTED;
234
235 retval = mips_m4k_debug_entry(target);
236 if (retval != ERROR_OK)
237 return retval;
238
239 if (target->smp) {
240 retval = update_halt_gdb(target);
241 if (retval != ERROR_OK)
242 return retval;
243 }
244
245 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
246 }
247 } else
248 target->state = TARGET_RUNNING;
249
250 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
251
252 return ERROR_OK;
253 }
254
255 static int mips_m4k_halt(struct target *target)
256 {
257 struct mips32_common *mips32 = target_to_mips32(target);
258 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
259
260 LOG_DEBUG("target->state: %s", target_state_name(target));
261
262 if (target->state == TARGET_HALTED) {
263 LOG_DEBUG("target was already halted");
264 return ERROR_OK;
265 }
266
267 if (target->state == TARGET_UNKNOWN)
268 LOG_WARNING("target was in unknown state when halt was requested");
269
270 if (target->state == TARGET_RESET) {
271 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
272 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
273 return ERROR_TARGET_FAILURE;
274 } else {
275 /* we came here in a reset_halt or reset_init sequence
276 * debug entry was already prepared in mips_m4k_assert_reset()
277 */
278 target->debug_reason = DBG_REASON_DBGRQ;
279
280 return ERROR_OK;
281 }
282 }
283
284 /* break processor */
285 mips_ejtag_enter_debug(ejtag_info);
286
287 target->debug_reason = DBG_REASON_DBGRQ;
288
289 return ERROR_OK;
290 }
291
292 static int mips_m4k_assert_reset(struct target *target)
293 {
294 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
295 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
296
297 /* TODO: apply hw reset signal in not examined state */
298 if (!(target_was_examined(target))) {
299 LOG_WARNING("Reset is not asserted because the target is not examined.");
300 LOG_WARNING("Use a reset button or power cycle the target.");
301 return ERROR_TARGET_NOT_EXAMINED;
302 }
303
304 LOG_DEBUG("target->state: %s",
305 target_state_name(target));
306
307 enum reset_types jtag_reset_config = jtag_get_reset_config();
308
309 /* some cores support connecting while srst is asserted
310 * use that mode is it has been configured */
311
312 bool srst_asserted = false;
313
314 if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
315 (jtag_reset_config & RESET_SRST_NO_GATING)) {
316 jtag_add_reset(0, 1);
317 srst_asserted = true;
318 }
319
320
321 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
322 if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
323 if (target->reset_halt) {
324 /* use hardware to catch reset */
325 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
326 } else
327 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
328 }
329
330 if (jtag_reset_config & RESET_HAS_SRST) {
331 /* here we should issue a srst only, but we may have to assert trst as well */
332 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
333 jtag_add_reset(1, 1);
334 else if (!srst_asserted)
335 jtag_add_reset(0, 1);
336 } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
337 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
338 } else {
339 if (mips_m4k->is_pic32mx) {
340 LOG_DEBUG("Using MTAP reset to reset processor...");
341
342 /* use microchip specific MTAP reset */
343 mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
344 mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
345
346 mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
347 mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
348 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
349 } else {
350 /* use ejtag reset - not supported by all cores */
351 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
352 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
353 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
354 mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
355 }
356 }
357
358 target->state = TARGET_RESET;
359 jtag_add_sleep(50000);
360
361 register_cache_invalidate(mips_m4k->mips32.core_cache);
362
363 if (target->reset_halt) {
364 int retval = target_halt(target);
365 if (retval != ERROR_OK)
366 return retval;
367 }
368
369 return ERROR_OK;
370 }
371
372 static int mips_m4k_deassert_reset(struct target *target)
373 {
374 LOG_DEBUG("target->state: %s", target_state_name(target));
375
376 /* deassert reset lines */
377 jtag_add_reset(0, 0);
378
379 return ERROR_OK;
380 }
381
382 static int mips_m4k_single_step_core(struct target *target)
383 {
384 struct mips32_common *mips32 = target_to_mips32(target);
385 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
386
387 /* configure single step mode */
388 mips_ejtag_config_step(ejtag_info, 1);
389
390 /* disable interrupts while stepping */
391 mips32_enable_interrupts(target, 0);
392
393 /* exit debug mode */
394 mips_ejtag_exit_debug(ejtag_info);
395
396 mips_m4k_debug_entry(target);
397
398 return ERROR_OK;
399 }
400
401 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
402 {
403 int retval = ERROR_OK;
404 struct target_list *head;
405
406 foreach_smp_target(head, target->smp_targets) {
407 int ret = ERROR_OK;
408 struct target *curr = head->target;
409 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
410 /* resume current address , not in step mode */
411 ret = mips_m4k_internal_restore(curr, 1, address,
412 handle_breakpoints, 0);
413
414 if (ret != ERROR_OK) {
415 LOG_TARGET_ERROR(curr, "failed to resume at address: 0x%" PRIx32,
416 address);
417 retval = ret;
418 }
419 }
420 }
421 return retval;
422 }
423
424 static int mips_m4k_internal_restore(struct target *target, int current,
425 target_addr_t address, int handle_breakpoints, int debug_execution)
426 {
427 struct mips32_common *mips32 = target_to_mips32(target);
428 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
429 struct breakpoint *breakpoint = NULL;
430 uint32_t resume_pc;
431
432 if (target->state != TARGET_HALTED) {
433 LOG_WARNING("target not halted");
434 return ERROR_TARGET_NOT_HALTED;
435 }
436
437 if (!debug_execution) {
438 target_free_all_working_areas(target);
439 mips_m4k_enable_breakpoints(target);
440 mips_m4k_enable_watchpoints(target);
441 }
442
443 /* current = 1: continue on current pc, otherwise continue at <address> */
444 if (!current) {
445 mips_m4k_isa_filter(mips32->isa_imp, &address);
446 buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
447 mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true;
448 mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
449 }
450
451 if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
452 buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode);
453
454 if (!current)
455 resume_pc = address;
456 else
457 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
458
459 mips32_restore_context(target);
460
461 /* the front-end may request us not to handle breakpoints */
462 if (handle_breakpoints) {
463 /* Single step past breakpoint at current address */
464 breakpoint = breakpoint_find(target, resume_pc);
465 if (breakpoint) {
466 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
467 breakpoint->address);
468 mips_m4k_unset_breakpoint(target, breakpoint);
469 mips_m4k_single_step_core(target);
470 mips_m4k_set_breakpoint(target, breakpoint);
471 }
472 }
473
474 /* enable interrupts if we are running */
475 mips32_enable_interrupts(target, !debug_execution);
476
477 /* exit debug mode */
478 mips_ejtag_exit_debug(ejtag_info);
479 target->debug_reason = DBG_REASON_NOTHALTED;
480
481 /* registers are now invalid */
482 register_cache_invalidate(mips32->core_cache);
483
484 if (!debug_execution) {
485 target->state = TARGET_RUNNING;
486 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
487 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
488 } else {
489 target->state = TARGET_DEBUG_RUNNING;
490 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
491 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
492 }
493
494 return ERROR_OK;
495 }
496
497 static int mips_m4k_resume(struct target *target, int current,
498 target_addr_t address, int handle_breakpoints, int debug_execution)
499 {
500 int retval = ERROR_OK;
501
502 /* dummy resume for smp toggle in order to reduce gdb impact */
503 if ((target->smp) && (target->gdb_service->core[1] != -1)) {
504 /* simulate a start and halt of target */
505 target->gdb_service->target = NULL;
506 target->gdb_service->core[0] = target->gdb_service->core[1];
507 /* fake resume at next poll we play the target core[1], see poll*/
508 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
509 return retval;
510 }
511
512 retval = mips_m4k_internal_restore(target, current, address,
513 handle_breakpoints,
514 debug_execution);
515
516 if (retval == ERROR_OK && target->smp) {
517 target->gdb_service->core[0] = -1;
518 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
519 }
520
521 return retval;
522 }
523
524 static int mips_m4k_step(struct target *target, int current,
525 target_addr_t address, int handle_breakpoints)
526 {
527 /* get pointers to arch-specific information */
528 struct mips32_common *mips32 = target_to_mips32(target);
529 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
530 struct breakpoint *breakpoint = NULL;
531
532 if (target->state != TARGET_HALTED) {
533 LOG_WARNING("target not halted");
534 return ERROR_TARGET_NOT_HALTED;
535 }
536
537 /* current = 1: continue on current pc, otherwise continue at <address> */
538 if (!current) {
539 mips_m4k_isa_filter(mips32->isa_imp, &address);
540 buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
541 mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true;
542 mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
543 }
544
545 /* the front-end may request us not to handle breakpoints */
546 if (handle_breakpoints) {
547 breakpoint = breakpoint_find(target,
548 buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
549 if (breakpoint)
550 mips_m4k_unset_breakpoint(target, breakpoint);
551 }
552
553 /* restore context */
554 mips32_restore_context(target);
555
556 /* configure single step mode */
557 mips_ejtag_config_step(ejtag_info, 1);
558
559 target->debug_reason = DBG_REASON_SINGLESTEP;
560
561 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
562
563 /* disable interrupts while stepping */
564 mips32_enable_interrupts(target, 0);
565
566 /* exit debug mode */
567 mips_ejtag_exit_debug(ejtag_info);
568
569 /* registers are now invalid */
570 register_cache_invalidate(mips32->core_cache);
571
572 LOG_DEBUG("target stepped ");
573 mips_m4k_debug_entry(target);
574
575 if (breakpoint)
576 mips_m4k_set_breakpoint(target, breakpoint);
577
578 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
579
580 return ERROR_OK;
581 }
582
583 static void mips_m4k_enable_breakpoints(struct target *target)
584 {
585 struct breakpoint *breakpoint = target->breakpoints;
586
587 /* set any pending breakpoints */
588 while (breakpoint) {
589 if (!breakpoint->is_set)
590 mips_m4k_set_breakpoint(target, breakpoint);
591 breakpoint = breakpoint->next;
592 }
593 }
594
595 static int mips_m4k_set_breakpoint(struct target *target,
596 struct breakpoint *breakpoint)
597 {
598 struct mips32_common *mips32 = target_to_mips32(target);
599 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
600 struct mips32_comparator *comparator_list = mips32->inst_break_list;
601 int retval;
602
603 if (breakpoint->is_set) {
604 LOG_WARNING("breakpoint already set");
605 return ERROR_OK;
606 }
607
608 if (breakpoint->type == BKPT_HARD) {
609 int bp_num = 0;
610
611 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
612 bp_num++;
613 if (bp_num >= mips32->num_inst_bpoints) {
614 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
615 breakpoint->unique_id);
616 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
617 }
618 breakpoint_hw_set(breakpoint, bp_num);
619 comparator_list[bp_num].used = 1;
620 comparator_list[bp_num].bp_value = breakpoint->address;
621
622 if (breakpoint->length != 4) /* make sure isa bit set */
623 comparator_list[bp_num].bp_value |= 1;
624 else /* make sure isa bit cleared */
625 comparator_list[bp_num].bp_value &= ~1;
626
627 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
628 * Warning: there is no IB ASID registers in 2.0.
629 * Do not set it! :) */
630 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
631 comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
632
633 target_write_u32(target, comparator_list[bp_num].reg_address,
634 comparator_list[bp_num].bp_value);
635 target_write_u32(target, comparator_list[bp_num].reg_address +
636 ejtag_info->ejtag_ibm_offs, 0x00000000);
637 target_write_u32(target, comparator_list[bp_num].reg_address +
638 ejtag_info->ejtag_ibc_offs, 1);
639 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
640 breakpoint->unique_id,
641 bp_num, comparator_list[bp_num].bp_value);
642 } else if (breakpoint->type == BKPT_SOFT) {
643 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
644
645 uint32_t isa_req = breakpoint->length & 1; /* micro mips request bit */
646 uint32_t bplength = breakpoint->length & ~1; /* drop micro mips request bit for length */
647 uint32_t bpaddr = breakpoint->address & ~1; /* drop isa bit from address, if set */
648
649 if (bplength == 4) {
650 uint32_t verify = 0xffffffff;
651 uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
652 if (ejtag_info->endianness && isa_req)
653 sdbbp32_instr = SWAP16(sdbbp32_instr);
654
655 if ((breakpoint->address & 3) == 0) { /* word aligned */
656
657 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
658 if (retval != ERROR_OK)
659 return retval;
660
661 retval = target_write_u32(target, bpaddr, sdbbp32_instr);
662 if (retval != ERROR_OK)
663 return retval;
664
665 retval = target_read_u32(target, bpaddr, &verify);
666 if (retval != ERROR_OK)
667 return retval;
668
669 if (verify != sdbbp32_instr)
670 verify = 0;
671
672 } else { /* 16 bit aligned */
673 retval = target_read_memory(target, bpaddr, 2, 2, breakpoint->orig_instr);
674 if (retval != ERROR_OK)
675 return retval;
676
677 uint8_t sdbbp_buf[4];
678 target_buffer_set_u32(target, sdbbp_buf, sdbbp32_instr);
679
680 retval = target_write_memory(target, bpaddr, 2, 2, sdbbp_buf);
681 if (retval != ERROR_OK)
682 return retval;
683
684 retval = target_read_memory(target, bpaddr, 2, 2, sdbbp_buf);
685 if (retval != ERROR_OK)
686 return retval;
687
688 if (target_buffer_get_u32(target, sdbbp_buf) != sdbbp32_instr)
689 verify = 0;
690 }
691
692 if (verify == 0) {
693 LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
694 " - check that memory is read/writable", breakpoint->address);
695 return ERROR_OK;
696 }
697
698 } else {
699 uint16_t verify = 0xffff;
700
701 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
702 if (retval != ERROR_OK)
703 return retval;
704
705 retval = target_write_u16(target, bpaddr, MIPS16_SDBBP(isa_req));
706 if (retval != ERROR_OK)
707 return retval;
708
709 retval = target_read_u16(target, bpaddr, &verify);
710 if (retval != ERROR_OK)
711 return retval;
712
713 if (verify != MIPS16_SDBBP(isa_req)) {
714 LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
715 " - check that memory is read/writable", breakpoint->address);
716 return ERROR_OK;
717 }
718 }
719
720 breakpoint->is_set = true;
721 }
722
723 return ERROR_OK;
724 }
725
726 static int mips_m4k_unset_breakpoint(struct target *target,
727 struct breakpoint *breakpoint)
728 {
729 /* get pointers to arch-specific information */
730 struct mips32_common *mips32 = target_to_mips32(target);
731 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
732 struct mips32_comparator *comparator_list = mips32->inst_break_list;
733 int retval;
734
735 if (!breakpoint->is_set) {
736 LOG_WARNING("breakpoint not set");
737 return ERROR_OK;
738 }
739
740 if (breakpoint->type == BKPT_HARD) {
741 int bp_num = breakpoint->number;
742 if (bp_num >= mips32->num_inst_bpoints) {
743 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
744 breakpoint->unique_id);
745 return ERROR_OK;
746 }
747 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
748 breakpoint->unique_id,
749 bp_num);
750 comparator_list[bp_num].used = 0;
751 comparator_list[bp_num].bp_value = 0;
752 target_write_u32(target, comparator_list[bp_num].reg_address +
753 ejtag_info->ejtag_ibc_offs, 0);
754
755 } else {
756 /* restore original instruction (kept in target endianness) */
757 uint32_t isa_req = breakpoint->length & 1;
758 uint32_t bplength = breakpoint->length & ~1;
759 uint8_t current_instr[4];
760 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
761 if (bplength == 4) {
762 uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
763 if (ejtag_info->endianness && isa_req)
764 sdbbp32_instr = SWAP16(sdbbp32_instr);
765
766 if ((breakpoint->address & 3) == 0) { /* 32bit aligned */
767 /* check that user program has not modified breakpoint instruction */
768 retval = target_read_memory(target, breakpoint->address, 4, 1, current_instr);
769 if (retval != ERROR_OK)
770 return retval;
771 /**
772 * target_read_memory() gets us data in _target_ endianness.
773 * If we want to use this data on the host for comparisons with some macros
774 * we must first transform it to _host_ endianness using target_buffer_get_u16().
775 */
776 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
777 retval = target_write_memory(target, breakpoint->address, 4, 1,
778 breakpoint->orig_instr);
779 if (retval != ERROR_OK)
780 return retval;
781 }
782 } else { /* 16bit aligned */
783 retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
784 if (retval != ERROR_OK)
785 return retval;
786
787 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
788 retval = target_write_memory(target, breakpoint->address, 2, 2,
789 breakpoint->orig_instr);
790 if (retval != ERROR_OK)
791 return retval;
792 }
793 }
794 } else {
795 /* check that user program has not modified breakpoint instruction */
796 retval = target_read_memory(target, breakpoint->address, 2, 1, current_instr);
797 if (retval != ERROR_OK)
798 return retval;
799
800 if (target_buffer_get_u16(target, current_instr) == MIPS16_SDBBP(isa_req)) {
801 retval = target_write_memory(target, breakpoint->address, 2, 1,
802 breakpoint->orig_instr);
803 if (retval != ERROR_OK)
804 return retval;
805 }
806 }
807 }
808
809 breakpoint->is_set = false;
810
811 return ERROR_OK;
812 }
813
814 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
815 {
816 struct mips32_common *mips32 = target_to_mips32(target);
817
818 if ((breakpoint->length > 5 || breakpoint->length < 2) || /* out of range */
819 (breakpoint->length == 4 && (breakpoint->address & 2)) || /* mips32 unaligned */
820 (mips32->isa_imp == MIPS32_ONLY && breakpoint->length != 4) || /* misp32 specific */
821 ((mips32->isa_imp & 1) != (breakpoint->length & 1))) /* isa not implemented */
822 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
823
824 if (breakpoint->type == BKPT_HARD) {
825 if (mips32->num_inst_bpoints_avail < 1) {
826 LOG_INFO("no hardware breakpoint available");
827 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
828 }
829
830 mips32->num_inst_bpoints_avail--;
831 }
832
833 return mips_m4k_set_breakpoint(target, breakpoint);
834 }
835
836 static int mips_m4k_remove_breakpoint(struct target *target,
837 struct breakpoint *breakpoint)
838 {
839 /* get pointers to arch-specific information */
840 struct mips32_common *mips32 = target_to_mips32(target);
841
842 if (target->state != TARGET_HALTED) {
843 LOG_WARNING("target not halted");
844 return ERROR_TARGET_NOT_HALTED;
845 }
846
847 if (breakpoint->is_set)
848 mips_m4k_unset_breakpoint(target, breakpoint);
849
850 if (breakpoint->type == BKPT_HARD)
851 mips32->num_inst_bpoints_avail++;
852
853 return ERROR_OK;
854 }
855
856 static int mips_m4k_set_watchpoint(struct target *target,
857 struct watchpoint *watchpoint)
858 {
859 struct mips32_common *mips32 = target_to_mips32(target);
860 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
861 struct mips32_comparator *comparator_list = mips32->data_break_list;
862 int wp_num = 0;
863 /*
864 * watchpoint enabled, ignore all byte lanes in value register
865 * and exclude both load and store accesses from watchpoint
866 * condition evaluation
867 */
868 int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
869 (0xff << EJTAG_DBCN_BLM_SHIFT);
870
871 if (watchpoint->is_set) {
872 LOG_WARNING("watchpoint already set");
873 return ERROR_OK;
874 }
875
876 while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
877 wp_num++;
878 if (wp_num >= mips32->num_data_bpoints) {
879 LOG_ERROR("Can not find free FP Comparator");
880 return ERROR_FAIL;
881 }
882
883 if (watchpoint->length != 4) {
884 LOG_ERROR("Only watchpoints of length 4 are supported");
885 return ERROR_TARGET_UNALIGNED_ACCESS;
886 }
887
888 if (watchpoint->address % 4) {
889 LOG_ERROR("Watchpoints address should be word aligned");
890 return ERROR_TARGET_UNALIGNED_ACCESS;
891 }
892
893 switch (watchpoint->rw) {
894 case WPT_READ:
895 enable &= ~EJTAG_DBCN_NOLB;
896 break;
897 case WPT_WRITE:
898 enable &= ~EJTAG_DBCN_NOSB;
899 break;
900 case WPT_ACCESS:
901 enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
902 break;
903 default:
904 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
905 }
906
907 watchpoint_set(watchpoint, wp_num);
908 comparator_list[wp_num].used = 1;
909 comparator_list[wp_num].bp_value = watchpoint->address;
910
911 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
912 * There is as well no ASID register support. */
913 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
914 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
915 else
916 target_write_u32(target, comparator_list[wp_num].reg_address +
917 ejtag_info->ejtag_dbasid_offs, 0x00000000);
918
919 target_write_u32(target, comparator_list[wp_num].reg_address,
920 comparator_list[wp_num].bp_value);
921 target_write_u32(target, comparator_list[wp_num].reg_address +
922 ejtag_info->ejtag_dbm_offs, 0x00000000);
923
924 target_write_u32(target, comparator_list[wp_num].reg_address +
925 ejtag_info->ejtag_dbc_offs, enable);
926 /* TODO: probably this value is ignored on 2.0 */
927 target_write_u32(target, comparator_list[wp_num].reg_address +
928 ejtag_info->ejtag_dbv_offs, 0);
929 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
930
931 return ERROR_OK;
932 }
933
934 static int mips_m4k_unset_watchpoint(struct target *target,
935 struct watchpoint *watchpoint)
936 {
937 /* get pointers to arch-specific information */
938 struct mips32_common *mips32 = target_to_mips32(target);
939 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
940 struct mips32_comparator *comparator_list = mips32->data_break_list;
941
942 if (!watchpoint->is_set) {
943 LOG_WARNING("watchpoint not set");
944 return ERROR_OK;
945 }
946
947 int wp_num = watchpoint->number;
948 if (wp_num >= mips32->num_data_bpoints) {
949 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
950 return ERROR_OK;
951 }
952 comparator_list[wp_num].used = 0;
953 comparator_list[wp_num].bp_value = 0;
954 target_write_u32(target, comparator_list[wp_num].reg_address +
955 ejtag_info->ejtag_dbc_offs, 0);
956 watchpoint->is_set = false;
957
958 return ERROR_OK;
959 }
960
961 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
962 {
963 struct mips32_common *mips32 = target_to_mips32(target);
964
965 if (mips32->num_data_bpoints_avail < 1) {
966 LOG_INFO("no hardware watchpoints available");
967 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
968 }
969
970 mips32->num_data_bpoints_avail--;
971
972 mips_m4k_set_watchpoint(target, watchpoint);
973 return ERROR_OK;
974 }
975
976 static int mips_m4k_remove_watchpoint(struct target *target,
977 struct watchpoint *watchpoint)
978 {
979 /* get pointers to arch-specific information */
980 struct mips32_common *mips32 = target_to_mips32(target);
981
982 if (target->state != TARGET_HALTED) {
983 LOG_WARNING("target not halted");
984 return ERROR_TARGET_NOT_HALTED;
985 }
986
987 if (watchpoint->is_set)
988 mips_m4k_unset_watchpoint(target, watchpoint);
989
990 mips32->num_data_bpoints_avail++;
991
992 return ERROR_OK;
993 }
994
995 static void mips_m4k_enable_watchpoints(struct target *target)
996 {
997 struct watchpoint *watchpoint = target->watchpoints;
998
999 /* set any pending watchpoints */
1000 while (watchpoint) {
1001 if (!watchpoint->is_set)
1002 mips_m4k_set_watchpoint(target, watchpoint);
1003 watchpoint = watchpoint->next;
1004 }
1005 }
1006
1007 static int mips_m4k_read_memory(struct target *target, target_addr_t address,
1008 uint32_t size, uint32_t count, uint8_t *buffer)
1009 {
1010 struct mips32_common *mips32 = target_to_mips32(target);
1011 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1012
1013 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1014 address, size, count);
1015
1016 if (target->state != TARGET_HALTED) {
1017 LOG_WARNING("target not halted");
1018 return ERROR_TARGET_NOT_HALTED;
1019 }
1020
1021 /* sanitize arguments */
1022 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1023 return ERROR_COMMAND_SYNTAX_ERROR;
1024
1025 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1026 return ERROR_TARGET_UNALIGNED_ACCESS;
1027
1028 if (size == 4 && count > 32) {
1029 int retval = mips_m4k_bulk_read_memory(target, address, count, buffer);
1030 if (retval == ERROR_OK)
1031 return ERROR_OK;
1032 LOG_WARNING("Falling back to non-bulk read");
1033 }
1034 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1035 void *t = NULL;
1036
1037 if (size > 1) {
1038 t = malloc(count * size * sizeof(uint8_t));
1039 if (!t) {
1040 LOG_ERROR("Out of memory");
1041 return ERROR_FAIL;
1042 }
1043 } else
1044 t = buffer;
1045
1046 /* if noDMA off, use DMAACC mode for memory read */
1047 int retval;
1048 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1049 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
1050 else
1051 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
1052
1053 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1054 /* endianness, but byte array should represent target endianness */
1055 if (retval == ERROR_OK) {
1056 switch (size) {
1057 case 4:
1058 target_buffer_set_u32_array(target, buffer, count, t);
1059 break;
1060 case 2:
1061 target_buffer_set_u16_array(target, buffer, count, t);
1062 break;
1063 }
1064 }
1065
1066 if (size > 1)
1067 free(t);
1068
1069 return retval;
1070 }
1071
1072 static int mips_m4k_write_memory(struct target *target, target_addr_t address,
1073 uint32_t size, uint32_t count, const uint8_t *buffer)
1074 {
1075 struct mips32_common *mips32 = target_to_mips32(target);
1076 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1077
1078 LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1079 address, size, count);
1080
1081 if (target->state != TARGET_HALTED) {
1082 LOG_WARNING("target not halted");
1083 return ERROR_TARGET_NOT_HALTED;
1084 }
1085
1086 if (size == 4 && count > 32) {
1087 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1088 if (retval == ERROR_OK)
1089 return ERROR_OK;
1090 LOG_WARNING("Falling back to non-bulk write");
1091 }
1092
1093 /* sanitize arguments */
1094 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1095 return ERROR_COMMAND_SYNTAX_ERROR;
1096
1097 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1098 return ERROR_TARGET_UNALIGNED_ACCESS;
1099
1100 /** correct endianness if we have word or hword access */
1101 void *t = NULL;
1102 if (size > 1) {
1103 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1104 /* endianness, but byte array represents target endianness */
1105 t = malloc(count * size * sizeof(uint8_t));
1106 if (!t) {
1107 LOG_ERROR("Out of memory");
1108 return ERROR_FAIL;
1109 }
1110
1111 switch (size) {
1112 case 4:
1113 target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1114 break;
1115 case 2:
1116 target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1117 break;
1118 }
1119 buffer = t;
1120 }
1121
1122 /* if noDMA off, use DMAACC mode for memory write */
1123 int retval;
1124 if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1125 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1126 else
1127 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1128
1129 free(t);
1130
1131 if (retval != ERROR_OK)
1132 return retval;
1133
1134 return ERROR_OK;
1135 }
1136
1137 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1138 struct target *target)
1139 {
1140 mips32_build_reg_cache(target);
1141
1142 return ERROR_OK;
1143 }
1144
1145 static int mips_m4k_init_arch_info(struct target *target,
1146 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1147 {
1148 struct mips32_common *mips32 = &mips_m4k->mips32;
1149
1150 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1151
1152 /* initialize mips4k specific info */
1153 mips32_init_arch_info(target, mips32, tap);
1154 mips32->arch_info = mips_m4k;
1155
1156 return ERROR_OK;
1157 }
1158
1159 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1160 {
1161 struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1162
1163 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1164
1165 return ERROR_OK;
1166 }
1167
1168 static int mips_m4k_examine(struct target *target)
1169 {
1170 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1171 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1172
1173 if (!target_was_examined(target)) {
1174 int retval = mips_ejtag_get_idcode(ejtag_info);
1175 if (retval != ERROR_OK) {
1176 LOG_ERROR("idcode read failed");
1177 return retval;
1178 }
1179 if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {
1180 /* we are using a pic32mx so select ejtag port
1181 * as it is not selected by default */
1182 mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1183 LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
1184 mips_m4k->is_pic32mx = true;
1185 }
1186 }
1187
1188 /* init rest of ejtag interface */
1189 int retval = mips_ejtag_init(ejtag_info);
1190 if (retval != ERROR_OK)
1191 return retval;
1192
1193 return mips32_examine(target);
1194 }
1195
1196 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
1197 uint32_t count, const uint8_t *buffer)
1198 {
1199 struct mips32_common *mips32 = target_to_mips32(target);
1200 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1201 struct working_area *fast_data_area;
1202 int retval;
1203 int write_t = 1;
1204
1205 LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1206 address, count);
1207
1208 /* check alignment */
1209 if (address & 0x3u)
1210 return ERROR_TARGET_UNALIGNED_ACCESS;
1211
1212 if (!mips32->fast_data_area) {
1213 /* Get memory for block write handler
1214 * we preserve this area between calls and gain a speed increase
1215 * of about 3kb/sec when writing flash
1216 * this will be released/nulled by the system when the target is resumed or reset */
1217 retval = target_alloc_working_area(target,
1218 MIPS32_FASTDATA_HANDLER_SIZE,
1219 &mips32->fast_data_area);
1220 if (retval != ERROR_OK) {
1221 LOG_ERROR("No working area available");
1222 return retval;
1223 }
1224
1225 /* reset fastadata state so the algo get reloaded */
1226 ejtag_info->fast_access_save = -1;
1227 }
1228
1229 fast_data_area = mips32->fast_data_area;
1230
1231 if (address < (fast_data_area->address + fast_data_area->size) &&
1232 fast_data_area->address < (address + count)) {
1233 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
1234 "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1235 fast_data_area->address, address, address + count);
1236 LOG_ERROR("Change work-area-phys or load_image address!");
1237 return ERROR_FAIL;
1238 }
1239
1240 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1241 /* but byte array represents target endianness */
1242 uint32_t *t = NULL;
1243 t = malloc(count * sizeof(uint32_t));
1244 if (!t) {
1245 LOG_ERROR("Out of memory");
1246 return ERROR_FAIL;
1247 }
1248
1249 target_buffer_get_u32_array(target, buffer, count, t);
1250
1251 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1252 count, t);
1253
1254 free(t);
1255
1256 if (retval != ERROR_OK)
1257 LOG_ERROR("Fastdata access Failed");
1258
1259 return retval;
1260 }
1261
1262 static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t address,
1263 uint32_t count, uint8_t *buffer)
1264 {
1265 struct mips32_common *mips32 = target_to_mips32(target);
1266 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1267 struct working_area *fast_data_area;
1268 int retval;
1269 int write_t = 0;
1270
1271 LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1272 address, count);
1273
1274 /* check alignment */
1275 if (address & 0x3u)
1276 return ERROR_TARGET_UNALIGNED_ACCESS;
1277
1278 if (!mips32->fast_data_area) {
1279 /* Get memory for block read handler
1280 * we preserve this area between calls and gain a speed increase
1281 * of about 3kb/sec when reading flash
1282 * this will be released/nulled by the system when the target is resumed or reset */
1283 retval = target_alloc_working_area(target,
1284 MIPS32_FASTDATA_HANDLER_SIZE,
1285 &mips32->fast_data_area);
1286 if (retval != ERROR_OK) {
1287 LOG_ERROR("No working area available");
1288 return retval;
1289 }
1290
1291 /* reset fastadata state so the algo get reloaded */
1292 ejtag_info->fast_access_save = -1;
1293 }
1294
1295 fast_data_area = mips32->fast_data_area;
1296
1297 if (address < (fast_data_area->address + fast_data_area->size) &&
1298 fast_data_area->address < (address + count)) {
1299 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within read area "
1300 "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1301 fast_data_area->address, address, address + count);
1302 LOG_ERROR("Change work-area-phys or load_image address!");
1303 return ERROR_FAIL;
1304 }
1305
1306 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1307 /* but byte array represents target endianness */
1308 uint32_t *t = malloc(count * sizeof(uint32_t));
1309 if (!t) {
1310 LOG_ERROR("Out of memory");
1311 return ERROR_FAIL;
1312 }
1313
1314 retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1315 count, t);
1316
1317 target_buffer_set_u32_array(target, buffer, count, t);
1318
1319 free(t);
1320
1321 if (retval != ERROR_OK)
1322 LOG_ERROR("Fastdata access Failed");
1323
1324 return retval;
1325 }
1326
1327 static int mips_m4k_verify_pointer(struct command_invocation *cmd,
1328 struct mips_m4k_common *mips_m4k)
1329 {
1330 if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1331 command_print(cmd, "target is not an MIPS_M4K");
1332 return ERROR_TARGET_INVALID;
1333 }
1334 return ERROR_OK;
1335 }
1336
1337 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1338 {
1339 int retval;
1340 struct target *target = get_current_target(CMD_CTX);
1341 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1342 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1343
1344 retval = mips_m4k_verify_pointer(CMD, mips_m4k);
1345 if (retval != ERROR_OK)
1346 return retval;
1347
1348 if (target->state != TARGET_HALTED) {
1349 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
1350 return ERROR_OK;
1351 }
1352
1353 /* two or more argument, access a single register/select (write if third argument is given) */
1354 if (CMD_ARGC < 2)
1355 return ERROR_COMMAND_SYNTAX_ERROR;
1356 else {
1357 uint32_t cp0_reg, cp0_sel;
1358 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1359 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1360
1361 if (CMD_ARGC == 2) {
1362 uint32_t value;
1363 retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1364 if (retval != ERROR_OK) {
1365 command_print(CMD,
1366 "couldn't access reg %" PRIu32,
1367 cp0_reg);
1368 return ERROR_OK;
1369 }
1370 command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1371 cp0_reg, cp0_sel, value);
1372
1373 } else if (CMD_ARGC == 3) {
1374 uint32_t value;
1375 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1376 retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1377 if (retval != ERROR_OK) {
1378 command_print(CMD,
1379 "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
1380 cp0_reg, cp0_sel);
1381 return ERROR_OK;
1382 }
1383 command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1384 cp0_reg, cp0_sel, value);
1385 }
1386 }
1387
1388 return ERROR_OK;
1389 }
1390
1391 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1392 {
1393 struct target *target = get_current_target(CMD_CTX);
1394 struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1395 struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1396
1397 if (CMD_ARGC == 1)
1398 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1399 else if (CMD_ARGC > 1)
1400 return ERROR_COMMAND_SYNTAX_ERROR;
1401
1402 command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
1403 if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1404 ejtag_info->mode = 0;
1405 command_print(CMD, "running in legacy mode");
1406 } else {
1407 ejtag_info->mode = 1;
1408 command_print(CMD, "running in fast queued mode");
1409 }
1410
1411 return ERROR_OK;
1412 }
1413
1414 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1415 {
1416 .name = "cp0",
1417 .handler = mips_m4k_handle_cp0_command,
1418 .mode = COMMAND_EXEC,
1419 .usage = "regnum [value]",
1420 .help = "display/modify cp0 register",
1421 },
1422 {
1423 .name = "scan_delay",
1424 .handler = mips_m4k_handle_scan_delay_command,
1425 .mode = COMMAND_ANY,
1426 .help = "display/set scan delay in nano seconds",
1427 .usage = "[value]",
1428 },
1429 {
1430 .chain = smp_command_handlers,
1431 },
1432 COMMAND_REGISTRATION_DONE
1433 };
1434
1435 static const struct command_registration mips_m4k_command_handlers[] = {
1436 {
1437 .chain = mips32_command_handlers,
1438 },
1439 {
1440 .name = "mips_m4k",
1441 .mode = COMMAND_ANY,
1442 .help = "mips_m4k command group",
1443 .usage = "",
1444 .chain = mips_m4k_exec_command_handlers,
1445 },
1446 COMMAND_REGISTRATION_DONE
1447 };
1448
1449 struct target_type mips_m4k_target = {
1450 .name = "mips_m4k",
1451
1452 .poll = mips_m4k_poll,
1453 .arch_state = mips32_arch_state,
1454
1455 .halt = mips_m4k_halt,
1456 .resume = mips_m4k_resume,
1457 .step = mips_m4k_step,
1458
1459 .assert_reset = mips_m4k_assert_reset,
1460 .deassert_reset = mips_m4k_deassert_reset,
1461
1462 .get_gdb_reg_list = mips32_get_gdb_reg_list,
1463
1464 .read_memory = mips_m4k_read_memory,
1465 .write_memory = mips_m4k_write_memory,
1466 .checksum_memory = mips32_checksum_memory,
1467 .blank_check_memory = mips32_blank_check_memory,
1468
1469 .run_algorithm = mips32_run_algorithm,
1470
1471 .add_breakpoint = mips_m4k_add_breakpoint,
1472 .remove_breakpoint = mips_m4k_remove_breakpoint,
1473 .add_watchpoint = mips_m4k_add_watchpoint,
1474 .remove_watchpoint = mips_m4k_remove_watchpoint,
1475
1476 .commands = mips_m4k_command_handlers,
1477 .target_create = mips_m4k_target_create,
1478 .init_target = mips_m4k_init_target,
1479 .examine = mips_m4k_examine,
1480 };
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