1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
11 * Copyright (C) 2009-2010 by David Brownell
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 ***************************************************************************/
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
43 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
44 #define JTAG_DP_ABORT 0x8
45 #define JTAG_DP_DPACC 0xA
46 #define JTAG_DP_APACC 0xB
47 #define JTAG_DP_IDCODE 0xE
49 /* three-bit ACK values for DPACC and APACC reads */
50 #define JTAG_ACK_OK_FAULT 0x2
51 #define JTAG_ACK_WAIT 0x1
53 /***************************************************************************
55 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
57 ***************************************************************************/
60 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
61 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
62 * discusses operations which access these registers.
64 * Note that only one scan is performed. If RnW is set, a separate scan
65 * will be needed to collect the data which was read; the "invalue" collects
66 * the posted result of a preceding operation, not the current one.
69 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
70 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
71 * SELECT register has more addressing bits.
72 * @param RnW false iff outvalue will be written to the DP or AP
73 * @param outvalue points to a 32-bit (little-endian) integer
74 * @param invalue NULL, or points to a 32-bit (little-endian) integer
75 * @param ack points to where the three bit JTAG_ACK_* code will be stored
78 static int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
79 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
80 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
82 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
83 struct scan_field fields
[2];
87 retval
= arm_jtag_set_instr(jtag_info
, instr
, NULL
, TAP_IDLE
);
88 if (retval
!= ERROR_OK
)
91 /* Scan out a read or write operation using some DP or AP register.
92 * For APACC access with any sticky error flag set, this is discarded.
94 fields
[0].num_bits
= 3;
95 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
96 fields
[0].out_value
= &out_addr_buf
;
97 fields
[0].in_value
= ack
;
99 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
100 * complete; data we write is discarded, data we read is unpredictable.
101 * When overrun detect is active, STICKYORUN is set.
104 fields
[1].num_bits
= 32;
105 fields
[1].out_value
= outvalue
;
106 fields
[1].in_value
= invalue
;
108 jtag_add_dr_scan(jtag_info
->tap
, 2, fields
, TAP_IDLE
);
110 /* Add specified number of tck clocks after starting memory bus
111 * access, giving the hardware time to complete the access.
112 * They provide more time for the (MEM) AP to complete the read ...
113 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
115 if ((instr
== JTAG_DP_APACC
)
116 && ((reg_addr
== AP_REG_DRW
)
117 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
118 && (dap
->memaccess_tck
!= 0))
119 jtag_add_runtest(dap
->memaccess_tck
,
126 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
127 * This is exactly like adi_jtag_dp_scan(), except that endianness
128 * conversions are performed (so the types of invalue and outvalue
129 * must be different).
131 static int adi_jtag_dp_scan_u32(struct adiv5_dap
*dap
,
132 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
133 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
135 uint8_t out_value_buf
[4];
138 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
140 retval
= adi_jtag_dp_scan(dap
, instr
, reg_addr
, RnW
,
141 out_value_buf
, (uint8_t *)invalue
, ack
);
142 if (retval
!= ERROR_OK
)
146 jtag_add_callback(arm_le_to_h_u32
,
147 (jtag_callback_data_t
) invalue
);
153 * Utility to write AP registers.
155 static inline int adi_jtag_ap_write_check(struct adiv5_dap
*dap
,
156 uint8_t reg_addr
, uint8_t *outvalue
)
158 return adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg_addr
, DPAP_WRITE
,
159 outvalue
, NULL
, NULL
);
162 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap
*dap
,
163 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
164 uint32_t outvalue
, uint32_t *invalue
)
168 /* Issue the read or write */
169 retval
= adi_jtag_dp_scan_u32(dap
, instr
, reg_addr
,
170 RnW
, outvalue
, NULL
, NULL
);
171 if (retval
!= ERROR_OK
)
174 /* For reads, collect posted value; RDBUFF has no other effect.
175 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
177 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
178 retval
= adi_jtag_dp_scan_u32(dap
, JTAG_DP_DPACC
,
179 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &dap
->ack
);
183 static int jtagdp_transaction_endcheck(struct adiv5_dap
*dap
)
188 /* too expensive to call keep_alive() here */
192 * It is easy to be in a JTAG clock range where the target
193 * is not operating in a stable fashion. This happens
196 * - the user may construct a simple test case to try to see
197 * if a higher JTAG clock works to eke out more performance.
198 * This simple case may pass, but more complex situations can
201 * - The mostly works JTAG clock rate and the complete failure
202 * JTAG clock rate may be as much as 2-4x apart. This seems
203 * to be especially true on RC oscillator driven parts.
205 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
206 * times here seems to "make things better here", it is just
207 * hiding problems with too high a JTAG clock.
209 * Note that even if some parts have RCLK/RTCK, that doesn't
210 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
211 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
212 * before the RC oscillator phase is not yet complete.
215 /* Post CTRL/STAT read; discard any previous posted read value
216 * but collect its ACK status.
218 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
219 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
220 if (retval
!= ERROR_OK
)
222 retval
= jtag_execute_queue();
223 if (retval
!= ERROR_OK
)
226 dap
->ack
= dap
->ack
& 0x7;
228 /* common code path avoids calling timeval_ms() */
229 if (dap
->ack
!= JTAG_ACK_OK_FAULT
) {
230 long long then
= timeval_ms();
232 while (dap
->ack
!= JTAG_ACK_OK_FAULT
) {
233 if (dap
->ack
== JTAG_ACK_WAIT
) {
234 if ((timeval_ms()-then
) > 1000) {
235 /* NOTE: this would be a good spot
236 * to use JTAG_DP_ABORT.
238 LOG_WARNING("Timeout (1000ms) waiting "
240 "in JTAG-DP transaction");
241 return ERROR_JTAG_DEVICE_ERROR
;
244 LOG_WARNING("Invalid ACK %#x "
245 "in JTAG-DP transaction",
247 return ERROR_JTAG_DEVICE_ERROR
;
250 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
251 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
252 if (retval
!= ERROR_OK
)
254 retval
= jtag_execute_queue();
255 if (retval
!= ERROR_OK
)
257 dap
->ack
= dap
->ack
& 0x7;
261 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
263 /* Check for STICKYERR and STICKYORUN */
264 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
)) {
265 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
266 /* Check power to debug regions */
267 if ((ctrlstat
& 0xf0000000) != 0xf0000000) {
268 retval
= ahbap_debugport_init(dap
);
269 if (retval
!= ERROR_OK
)
272 uint32_t mem_ap_csw
, mem_ap_tar
;
274 /* Maybe print information about last intended
275 * MEM-AP access; but not if autoincrementing.
276 * *Real* CSW and TAR values are always shown.
278 if (dap
->ap_tar_value
!= (uint32_t) -1)
279 LOG_DEBUG("MEM-AP Cached values: "
281 ", ap_csw 0x%" PRIx32
282 ", ap_tar 0x%" PRIx32
,
287 if (ctrlstat
& SSTICKYORUN
)
288 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
289 "memaccess, or reduce jtag speed");
291 if (ctrlstat
& SSTICKYERR
)
292 LOG_ERROR("JTAG-DP STICKY ERROR");
294 /* Clear Sticky Error Bits */
295 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
296 DP_CTRL_STAT
, DPAP_WRITE
,
297 dap
->dp_ctrl_stat
| SSTICKYORUN
299 if (retval
!= ERROR_OK
)
301 retval
= adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
302 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
303 if (retval
!= ERROR_OK
)
305 retval
= jtag_execute_queue();
306 if (retval
!= ERROR_OK
)
309 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
311 retval
= dap_queue_ap_read(dap
,
312 AP_REG_CSW
, &mem_ap_csw
);
313 if (retval
!= ERROR_OK
)
316 retval
= dap_queue_ap_read(dap
,
317 AP_REG_TAR
, &mem_ap_tar
);
318 if (retval
!= ERROR_OK
)
321 retval
= jtag_execute_queue();
322 if (retval
!= ERROR_OK
)
324 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
325 PRIx32
, mem_ap_csw
, mem_ap_tar
);
328 retval
= jtag_execute_queue();
329 if (retval
!= ERROR_OK
)
331 return ERROR_JTAG_DEVICE_ERROR
;
337 /*--------------------------------------------------------------------------*/
339 static int jtag_idcode_q_read(struct adiv5_dap
*dap
,
340 uint8_t *ack
, uint32_t *data
)
342 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
344 struct scan_field fields
[1];
346 /* This is a standard JTAG operation -- no DAP tweakage */
347 retval
= arm_jtag_set_instr(jtag_info
, JTAG_DP_IDCODE
, NULL
, TAP_IDLE
);
348 if (retval
!= ERROR_OK
)
351 fields
[0].num_bits
= 32;
352 fields
[0].out_value
= NULL
;
353 fields
[0].in_value
= (void *) data
;
355 jtag_add_dr_scan(jtag_info
->tap
, 1, fields
, TAP_IDLE
);
357 jtag_add_callback(arm_le_to_h_u32
,
358 (jtag_callback_data_t
) data
);
363 static int jtag_dp_q_read(struct adiv5_dap
*dap
, unsigned reg
,
366 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
367 reg
, DPAP_READ
, 0, data
);
370 static int jtag_dp_q_write(struct adiv5_dap
*dap
, unsigned reg
,
373 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_DPACC
,
374 reg
, DPAP_WRITE
, data
, NULL
);
377 /** Select the AP register bank matching bits 7:4 of reg. */
378 static int jtag_ap_q_bankselect(struct adiv5_dap
*dap
, unsigned reg
)
380 uint32_t select_ap_bank
= reg
& 0x000000F0;
382 if (select_ap_bank
== dap
->ap_bank_value
)
384 dap
->ap_bank_value
= select_ap_bank
;
386 select_ap_bank
|= dap
->ap_current
;
388 return jtag_dp_q_write(dap
, DP_SELECT
, select_ap_bank
);
391 static int jtag_ap_q_read(struct adiv5_dap
*dap
, unsigned reg
,
394 int retval
= jtag_ap_q_bankselect(dap
, reg
);
396 if (retval
!= ERROR_OK
)
399 return adi_jtag_scan_inout_check_u32(dap
, JTAG_DP_APACC
, reg
,
403 static int jtag_ap_q_write(struct adiv5_dap
*dap
, unsigned reg
,
406 uint8_t out_value_buf
[4];
408 int retval
= jtag_ap_q_bankselect(dap
, reg
);
409 if (retval
!= ERROR_OK
)
412 buf_set_u32(out_value_buf
, 0, 32, data
);
414 return adi_jtag_ap_write_check(dap
, reg
, out_value_buf
);
417 static int jtag_ap_q_read_block(struct adiv5_dap
*dap
, unsigned reg
,
418 uint32_t blocksize
, uint8_t *buffer
)
421 int retval
= ERROR_OK
;
423 /* Scan out first read */
424 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg
,
425 DPAP_READ
, 0, NULL
, NULL
);
426 if (retval
!= ERROR_OK
)
429 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++) {
430 /* Scan out next read; scan in posted value for the
431 * previous one. Assumes read is acked "OK/FAULT",
432 * and CTRL_STAT says that meant "OK".
434 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg
,
435 DPAP_READ
, 0, buffer
+ 4 * readcount
,
437 if (retval
!= ERROR_OK
)
441 /* Scan in last posted value; RDBUFF has no other effect,
442 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
444 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_DPACC
, DP_RDBUFF
,
445 DPAP_READ
, 0, buffer
+ 4 * readcount
,
451 static int jtag_ap_q_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
453 /* for JTAG, this is the only valid ABORT register operation */
454 return adi_jtag_dp_scan_u32(dap
, JTAG_DP_ABORT
,
455 0, DPAP_WRITE
, 1, NULL
, ack
);
458 static int jtag_dp_run(struct adiv5_dap
*dap
)
460 return jtagdp_transaction_endcheck(dap
);
463 /* FIXME don't export ... just initialize as
466 const struct dap_ops jtag_dp_ops
= {
467 .queue_idcode_read
= jtag_idcode_q_read
,
468 .queue_dp_read
= jtag_dp_q_read
,
469 .queue_dp_write
= jtag_dp_q_write
,
470 .queue_ap_read
= jtag_ap_q_read
,
471 .queue_ap_write
= jtag_ap_q_write
,
472 .queue_ap_read_block
= jtag_ap_q_read_block
,
473 .queue_ap_abort
= jtag_ap_q_abort
,
478 static const uint8_t swd2jtag_bitseq
[] = {
479 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
480 * putting both JTAG and SWD logic into reset state.
482 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
483 /* Switching equence disables SWD and enables JTAG
484 * NOTE: bits in the DP's IDCODE can expose the need for
485 * the old/deprecated sequence (0xae 0xde).
488 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
489 * putting both JTAG and SWD logic into reset state.
490 * NOTE: some docs say "at least 5".
492 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
495 /** Put the debug link into JTAG mode, if the target supports it.
496 * The link's initial mode may be either SWD or JTAG.
498 * @param target Enters JTAG mode (if possible).
500 * Note that targets implemented with SW-DP do not support JTAG, and
501 * that some targets which could otherwise support it may have been
502 * configured to disable JTAG signaling
504 * @return ERROR_OK or else a fault code.
506 int dap_to_jtag(struct target
*target
)
510 LOG_DEBUG("Enter JTAG mode");
512 /* REVISIT it's nasty to need to make calls to a "jtag"
513 * subsystem if the link isn't in JTAG mode...
516 retval
= jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq
),
517 swd2jtag_bitseq
, TAP_RESET
);
518 if (retval
== ERROR_OK
)
519 retval
= jtag_execute_queue();
521 /* REVISIT set up the DAP's ops vector for JTAG mode. */