hppa: Improve handling of REG+D addresses when generating PA 2.0 code

hppa: Improve handling of REG+D addresses when generating PA 2.0 code

In looking at PR 112415, it became clear that improvements could be
made in the handling of loads and stores using REG+D addresses.  A
change in 2002 conflated two issues:

1) We can't generate insns with 14-bit displacements before reload
completes when generating PA 1.x code since floating-point loads and
stores only support 5-bit offsets in PA 1.x.

2) The GNU ELF 32-bit linker lacks relocation support for PA 2.0
floating point instructions with 14-bit displacements.  These
relocations affect instructions with symbolic references.

The result of the change was to block creation of PA 2.0 instructions
with 14-bit REG_D displacements for SImode, DImode, SFmode and DFmode
on the GNU linux target before reload.  This was unnecessary as these
instructions don't need relocation.

This change revises the INT14_OK_STRICT define to allow creation
of instructions with 14-bit REG+D addresses before reload when
generating PA 2.0 code.

2024-03-17  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

	PR rtl-optimization/112415
	* config/pa/pa.cc (pa_emit_move_sequence): Revise condition
	for symbolic memory operands.
	(pa_legitimate_address_p): Revise LO_SUM condition.
	* config/pa/pa.h (INT14_OK_STRICT): Revise define.  Move
	comment about GNU linker to predicates.md.
	* config/pa/predicates.md (floating_point_store_memory_operand):
	Revise condition for symbolic memory operands.  Update
	comment.