| blob | 5f1c9db9247bde2b8880a965b03e26e94aa3f14a |
1 2024-03-27 Segher Boessenkool <segher@kernel.crashing.org>
3 PR rtl-optimization/101523
4 * combine.cc (try_combine): Don't do a 2-insn combination if
5 it does not in fact change I2.
7 2024-03-27 Jakub Jelinek <jakub@redhat.com>
9 * doc/invoke.texi (Spec Files): Use @var{S} instead of S,
10 @var{X} instead of X etc. for other placeholders.
12 2024-03-27 Richard Biener <rguenther@suse.de>
14 PR tree-optimization/114057
15 * tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Mark
16 BB reduction remain defs as scalar uses.
18 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
20 * config/aarch64/aarch64-option-extensions.def (rcpc3):
21 Fix FEATURE_STRING field to "lrcpc3".
23 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
25 * config/aarch64/aarch64-option-extensions.def: Add LSE128
26 AARCH64_OPT_EXTENSION, adding it as a dependency for the D128
27 feature.
28 * doc/invoke.texi (AArch64 Options): Document +lse128.
30 2024-03-26 Richard Sandiford <richard.sandiford@arm.com>
32 * config/aarch64/aarch64-feature-deps.h: Use constexpr for
33 out-of-line statics.
35 2024-03-26 Cupertino Miranda <cupertino.miranda@oracle.com>
37 PR target/114431
38 * btfout.cc (get_name_for_datasec_entry): Add function.
39 (btf_asm_datasec_entry): Print label when possible.
41 2024-03-26 Richard Ball <richard.ball@arm.com>
43 PR target/114272
44 * config/aarch64/aarch64-cores.def (AARCH64_CORE):
45 Change SCHEDULER_IDENT from cortexa55 to cortexa53
46 for Cortex-A510 and Cortex-A520.
48 2024-03-26 Jakub Jelinek <jakub@redhat.com>
50 PR middle-end/111151
51 * fold-const.cc (extract_muldiv_1) <case MAX_EXPR>: Punt for
52 MULT_EXPR altogether, or for MAX_EXPR if c is -1.
54 2024-03-26 Jakub Jelinek <jakub@redhat.com>
56 PR sanitizer/111736
57 * tsan.cc (instrument_expr): Punt on non-generic address space
58 accesses.
60 2024-03-26 Richard Biener <rguenther@suse.de>
62 PR tree-optimization/114471
63 * tree-vect-stmts.cc (vectorizable_operation): Verify operand
64 types are compatible with the result type.
66 2024-03-26 Richard Biener <rguenther@suse.de>
68 PR tree-optimization/114464
69 * tree-vect-loop.cc (vectorizable_recurr): Verify the latch
70 vector type is compatible with what we chose for the recurrence.
72 2024-03-26 Jakub Jelinek <jakub@redhat.com>
74 * cfgloopmanip.cc (update_loop_exit_probability_scale_dom_bbs):
75 Fix comment typo - multple -> multiple.
76 * config/i386/x86-tune.def (X86_TUNE_ACCUMULATE_OUTGOING_ARGS):
77 Likewise.
79 2024-03-26 YunQiang Su <syq@gcc.gnu.org>
81 * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
82 __mips_strict_alignment if STRICT_ALIGNMENT.
84 2024-03-25 Richard Biener <rguenther@suse.de>
86 * config.gcc (amdgcn): Add gfx1036 entries.
87 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
88 (gcn_local_sym_hash): Likewise.
89 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
90 (TARGET_GFX1036): New macro.
91 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
92 (gcn_omp_device_kind_arch_isa): Likewise.
93 (output_file_start): Likewise.
94 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
95 (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
96 * config/gcn/gcn.opt: Add gfx1036.
97 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
98 (main): Handle gfx1036.
99 * config/gcn/t-omp-device: Add gfx1036 isa.
100 * doc/install.texi (amdgcn): Add gfx1036.
101 * doc/invoke.texi (-march): Likewise.
103 2024-03-25 Pan Li <pan2.li@intel.com>
105 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
106 when V is disabled and init the RVV types and intrinic APIs.
107 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
108 error if V ext is disabled.
109 * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
110 Ditto.
111 (riscv_arguments_is_vector_type_p): Ditto.
112 (riscv_vector_cc_function_p): Ditto.
113 * config/riscv/riscv_vector.h: Remove error if V is disable.
115 2024-03-23 John David Anglin <danglin@gcc.gnu.org>
117 * config/pa/pa.cc (pa_output_global_address): Handle
118 UNSPEC_DLTIND14R addresses.
119 * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
120 UNSPEC_DLTIND14R address.
122 2024-03-23 Jakub Jelinek <jakub@redhat.com>
124 PR tree-optimization/114433
125 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
126 m_bitfld_load check save_first rather than m_first.
128 2024-03-23 Jakub Jelinek <jakub@redhat.com>
130 PR tree-optimization/114425
131 * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
132 _Complex large/huge _BitInt types like the large/huge _BitInt types.
134 2024-03-23 Jakub Jelinek <jakub@redhat.com>
136 PR middle-end/111683
137 * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
138 and comp_step is RS_NONZERO, return false if any reference in the
139 component doesn't have DR_STEP a multiple of access size.
141 2024-03-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
143 * config/xtensa/xtensa.md: Add new split pattern described above.
145 2024-03-22 Georg-Johann Lay <avr@gjlay.de>
147 * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
148 for deprecated SIGNAL and INTERRUPT usage without respective header.
150 2024-03-22 Andrew Stubbs <ams@baylibre.com>
152 * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
153 (atomic_load<mode>): Adjust RDNA cache settings.
154 (atomic_store<mode>): Likewise.
155 (atomic_exchange<mode>): Likewise.
157 2024-03-22 Andrew Stubbs <ams@baylibre.com>
159 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
160 RDNA devices.
162 2024-03-22 Andrew Stubbs <ams@baylibre.com>
164 * config.gcc (amdgcn): Add gfx1103 entries.
165 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
166 (gcn_local_sym_hash): Likewise.
167 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
168 (TARGET_GFX1103): New macro.
169 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
170 (gcn_omp_device_kind_arch_isa): Likewise.
171 (output_file_start): Likewise.
172 (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
173 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
174 * config/gcn/gcn.opt: Add gfx1103.
175 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
176 (main): Handle gfx1103.
177 * config/gcn/t-omp-device: Add gfx1103 isa.
178 * doc/install.texi (amdgcn): Add gfx1103.
179 * doc/invoke.texi (-march): Likewise.
181 2024-03-22 Andrew Stubbs <ams@baylibre.com>
183 * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
184 bitmasks.
185 (do_compare_and_jump): Remove now-redundant similar code.
186 * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
187 bitmasks.
188 (add_mask_and_len_args): Likewise.
190 2024-03-22 Pan Li <pan2.li@intel.com>
192 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
193 macro __riscv_v_fixed_vlen when zvl.
194 * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
195 New static func to take care of the RVV types decorated by
196 the attributes.
198 2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
200 PR c/109619
201 * builtins.cc (fold_builtin_1): Use error_operand_p
202 instead of checking against ERROR_MARK.
203 (fold_builtin_2): Likewise.
204 (fold_builtin_3): Likewise.
206 2024-03-22 Jakub Jelinek <jakub@redhat.com>
208 PR sanitizer/111736
209 * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
210 SANITIZE_NULL instrumentation for non-generic address spaces
211 for which targetm.addr_space.zero_address_valid (as) is true.
213 2024-03-22 Jakub Jelinek <jakub@redhat.com>
215 PR tree-optimization/114405
216 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
217 Set rprec to limb_prec rather than 0 if tprec is divisible by
218 limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
219 % limb_prec rather than tprec % limb_prec and use just rprec instead
220 of rprec + bo_bit. For build_bit_field_ref offset, divide
221 (tprec + bo_bit) by limb_prec rather than just tprec.
223 2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
225 PR target/114194
226 * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
227 Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
229 2024-03-22 Jeff Law <jlaw@ventanamicro.com>
231 * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
232 tie for scalable and final stack adjustment if needed.
233 Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
235 2024-03-22 Pan Li <pan2.li@intel.com>
237 PR target/114352
238 * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
239 New struct for func decl and target name.
240 (struct riscv_func_target_hasher): New hasher for hash table mapping
241 from the fn_decl to fn_target_name.
242 (riscv_func_decl_hash): New func to compute the hash for fn_decl.
243 (riscv_func_target_hasher::hash): New func to impl hash interface.
244 (riscv_func_target_hasher::equal): New func to impl equal interface.
245 (riscv_cmdline_subset_list): New static var for cmdline subset list.
246 (riscv_func_target_table_lazy_init): New func to lazy init the func
247 target hash table.
248 (riscv_func_target_get): New func to get target name from hash table.
249 (riscv_func_target_put): New func to put target name into hash table.
250 (riscv_func_target_remove_and_destory): New func to remove target
251 info from the hash table and destory it.
252 (riscv_parse_arch_string): Set the static var cmdline_subset_list.
253 * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
254 var for cmdline subset list.
255 (riscv_func_target_get): New func decl.
256 (riscv_func_target_put): Ditto.
257 (riscv_func_target_remove_and_destory): Ditto.
258 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
259 Take cmdline_subset_list instead of current_subset_list when clone.
260 (riscv_process_target_attr): Record the func target info to hash table.
261 (riscv_option_valid_attribute_p): Add new arg tree fndel.
262 * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
263 func target info and print the arch message.
265 2024-03-22 Pan Li <pan2.li@intel.com>
267 PR target/114352
268 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
269 Replace implied, combine and check to func finalize.
270 (riscv_subset_list::finalize): New func impl to take care of
271 implied, combine ext and related checks.
272 * config/riscv/riscv-subset.h: Add func decl for finalize.
273 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
274 Finalize the ext before return succeed.
275 * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
276 machine mode before when set cur function.
278 2024-03-21 Andrew Stubbs <ams@baylibre.com>
280 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
282 2024-03-21 Andrew Stubbs <ams@baylibre.com>
284 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
286 2024-03-21 Andrew Stubbs <ams@baylibre.com>
288 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
289 device_malloc call.
291 2024-03-21 liuhongt <hongtao.liu@intel.com>
293 PR tree-optimization/114396
294 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
295 and true to wi::from_mpz.
297 2024-03-21 Richard Biener <rguenther@suse.de>
299 PR tree-optimization/111736
300 * asan.cc (instrument_derefs): Do not instrument accesses
301 to non-generic address-spaces.
303 2024-03-21 Richard Biener <rguenther@suse.de>
305 PR tree-optimization/113727
306 * tree-sra.cc (analyze_access_subtree): Do not allow
307 replacements in subtrees when grp_partial_lhs.
309 2024-03-21 liuhongt <hongtao.liu@intel.com>
311 PR middle-end/114347
312 * doc/invoke.texi: Document -fexcess-precision=16.
314 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
316 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
317 field contains a DECL_NAME.
319 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
321 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
322 Add assert to validate the string is set.
323 * config/bpf/core-builtins.cc (cr_final): Make string struct
324 field as const.
325 (process_enum_value): Correct for field type change.
326 (process_type): Set access string to "0".
328 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
330 * config/bpf/core-builtins.cc (core_field_info): Add
331 support for POINTER_PLUS_EXPR in the root of the field expression.
332 (bpf_core_get_index): Likewise.
333 (pack_field_expr): Make the BTF type to point to the structure
334 related node, instead of its pointer type.
335 (make_core_safe_access_index): Correct to new code.
337 2024-03-20 Xi Ruoyao <xry111@xry111.site>
339 PR target/114407
340 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
341 Fix typo in diagnostic message, enabing -> enabling.
343 2024-03-20 Jakub Jelinek <jakub@redhat.com>
345 PR target/114175
346 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
347 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
348 if arg.type is NULL.
350 2024-03-20 Jakub Jelinek <jakub@redhat.com>
352 PR target/114175
353 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
354 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
355 if arg.type is NULL.
357 2024-03-20 Jakub Jelinek <jakub@redhat.com>
359 PR target/114175
360 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
361 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
362 if arg.type is NULL.
364 2024-03-20 Jakub Jelinek <jakub@redhat.com>
366 PR target/114175
367 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
368 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
369 if arg.type is NULL.
371 2024-03-20 Jakub Jelinek <jakub@redhat.com>
373 PR target/114175
374 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
375 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
376 if arg.type is NULL.
378 2024-03-20 Jakub Jelinek <jakub@redhat.com>
380 PR target/114175
381 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
382 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
383 if arg.type is NULL.
385 2024-03-20 Jakub Jelinek <jakub@redhat.com>
387 PR target/114175
388 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
389 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
390 if arg.type is NULL.
392 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
394 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
396 2024-03-20 Jakub Jelinek <jakub@redhat.com>
398 PR tree-optimization/114365
399 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
400 a PHI node, set iv2 to its result afterwards.
402 2024-03-20 Jakub Jelinek <jakub@redhat.com>
404 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
405 probabbility -> probability.
406 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
408 2024-03-20 Jakub Jelinek <jakub@redhat.com>
410 PR bootstrap/114369
411 * system.h (vec_step): Define to vec_step_ when compiling
412 with clang on PowerPC.
414 2024-03-20 demin.han <demin.han@starfivetech.com>
416 PR target/112651
417 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
418 (enum rvv_max_lmul_enum): Ditto
419 (TARGET_MAX_LMUL): Ditto
420 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
421 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
422 (costs::better_main_loop_than_p): Ditto
423 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
425 2024-03-20 Richard Biener <rguenther@suse.de>
427 PR middle-end/113396
428 * tree-dfa.cc (get_ref_base_and_extent): Use index range
429 bounds only if they fit within the address-range constraints
430 of offset_int.
432 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
434 * config/loongarch/loongarch.cc
435 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
436 UNITS_PER_FPREG macros.
437 (loongarch_hard_regno_nregs): Ditto.
438 (loongarch_class_max_nregs): Ditto.
439 (loongarch_get_separate_components): Ditto.
440 (loongarch_process_components): Ditto.
441 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
442 (UNITS_PER_HWFPVALUE): Ditto.
443 (UNITS_PER_FPVALUE): Ditto.
445 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
447 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
448 of loongarch_expand_vec_cmp()'s return value.
449 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
450 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
451 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
452 * config/loongarch/loongarch-protos.h
453 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
454 type from bool to void.
455 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
457 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
459 * config/loongarch/loongarch-protos.h
460 (loongarch_cfun_has_cprestore_slot_p): Delete.
461 (loongarch_adjust_insn_length): Delete.
462 (current_section_name): Delete.
463 (loongarch_split_symbol_type): Delete.
464 * config/loongarch/loongarch.cc
465 (loongarch_case_values_threshold): Delete.
466 (loongarch_spill_class): Delete.
467 (TARGET_OPTAB_SUPPORTED_P): Delete.
468 (TARGET_CASE_VALUES_THRESHOLD): Delete.
469 (TARGET_SPILL_CLASS): Delete.
471 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
473 PR c++/111918
474 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
475 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
476 Make use of DK_ANY to indicate a diagnostic was initially enabled.
477 (diagnostic_context::diagnostic_enabled): Do not change the type of
478 a diagnostic if the saved classification is type DK_ANY.
480 2024-03-19 Martin Jambor <mjambor@suse.cz>
482 PR ipa/108802
483 PR ipa/114254
484 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
485 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
486 a pointer parameter.
487 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
488 parameter, also recognize the case when pfn pointer is loaded in its
489 own BB.
491 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
493 PR target/99829
494 * lra-constraints.cc (lra_constraints): Prevent removing insn
495 with reverse equivalence to memory if the memory was reloaded.
497 2024-03-19 David Malcolm <dmalcolm@redhat.com>
499 PR middle-end/114348
500 * diagnostic-format-json.cc
501 (json_stderr_output_format::machine_readable_stderr_p): New.
502 (json_file_output_format::machine_readable_stderr_p): New.
503 * diagnostic-format-sarif.cc
504 (sarif_stream_output_format::machine_readable_stderr_p): New.
505 (sarif_file_output_format::machine_readable_stderr_p): New.
506 * diagnostic.cc (diagnostic_context::action_after_output): Move
507 "fnotice" to before "finish" call, so that we still have the
508 diagnostic_context.
509 (fnotice): Bail out if the user requested one of the
510 machine-readable diagnostic output formats on stderr.
511 * diagnostic.h
512 (diagnostic_output_format::machine_readable_stderr_p): New pure
513 virtual function.
514 (diagnostic_text_output_format::machine_readable_stderr_p): New.
515 (diagnostic_context::get_output_format): New accessor.
517 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
519 PR target/114175
520 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
521 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
522 if arg.type is NULL
524 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
526 * doc/install.texi (Prerequisites): Document use of autogen for
527 libstdc++.
529 2024-03-19 Richard Biener <rguenther@suse.de>
531 PR tree-optimization/114151
532 PR tree-optimization/114269
533 PR tree-optimization/114322
534 PR tree-optimization/114074
535 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
536 unsigned arithmetic when actual overflow on constant operands
537 is observed.
539 2024-03-19 Jakub Jelinek <jakub@redhat.com>
541 PR target/114175
542 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
543 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
544 if arg.type is NULL.
546 2024-03-19 Xi Ruoyao <xry111@xry111.site>
548 PR target/114175
549 * config/loongarch/loongarch.cc
550 (loongarch_setup_incoming_varargs): Only skip
551 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
552 functions if arg.type is NULL.
554 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
556 PR target/114323
557 * config/arm/arm-mve-builtins.cc
558 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
559 into account.
561 2024-03-19 Jakub Jelinek <jakub@redhat.com>
563 PR target/114175
564 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
565 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
566 if arg.type is NULL.
568 2024-03-19 Jakub Jelinek <jakub@redhat.com>
570 PR target/114175
571 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
572 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
573 if arg.type is NULL.
575 2024-03-19 Richard Biener <rguenther@suse.de>
577 PR tree-optimization/114375
578 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
579 load permutation for masked loads but reject it when any
580 such is necessary.
581 * tree-vect-stmts.cc (vectorizable_load): Reject masked
582 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
583 supported.
585 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
587 * common/config/riscv/riscv-common.cc: Create XCVbi extension
588 support.
589 * config/riscv/riscv.opt: Likewise.
590 * config/riscv/corev.md: Implement cv_branch<mode> pattern
591 for cv.beqimm and cv.bneimm.
592 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
593 branch instruction pattern.
594 * config/riscv/constraints.md: Implement constraints
595 cv_bi_s5 - signed 5-bit immediate.
596 * config/riscv/predicates.md: Implement predicate
597 const_int5s_operand - signed 5 bit immediate.
598 * doc/sourcebuild.texi: Add XCVbi documentation.
600 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
602 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
603 (RISCV_CORE): Ditto.
604 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
605 option.
606 * config/riscv/riscv.cc: New def.
607 * config/riscv/riscv.md: New include.
608 * config/riscv/xiangshan.md: New file.
610 2024-03-18 David Malcolm <dmalcolm@redhat.com>
612 PR analyzer/110902
613 PR analyzer/110928
614 PR analyzer/111305
615 PR analyzer/111441
616 * selftest.h (ASSERT_NE_AT): New macro.
618 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
620 PR target/111822
621 * config/i386/i386-features.cc (smode_convert_cst): New function
622 to handle SImode, DImode and TImode immediates, generalized from
623 timode_convert_cst.
624 (timode_convert_cst): Remove.
625 (scalar_chain::convert_op): Unify from
626 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
627 (general_scalar_chain::convert_op): Remove.
628 (timode_scalar_chain::convert_op): Remove.
629 (timode_scalar_chain::convert_insn): Update the call to
630 renamed timode_convert_cst.
631 * config/i386/i386-features.h (class scalar_chain):
632 Redeclare convert_op as protected class member.
633 (class general_calar_chain): Remove convert_op.
634 (class timode_scalar_chain): Ditto.
636 2024-03-18 Jan Hubicka <jh@suse.cz>
638 * config/i386/zn4zn5.md: Add file missed in the previous commit.
640 2024-03-18 Jan Hubicka <jh@suse.cz>
641 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
643 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
644 * common/config/i386/i386-common.cc (processor_names): Add znver5.
645 (processor_alias_table): Likewise.
646 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
647 family.
648 (processor_subtypes): Add znver5.
649 * config.gcc (x86_64-*-* |...): Likewise.
650 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
651 march=native detect znver5 cpu's.
652 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
653 znver5.
654 * config/i386/i386-options.cc (m_ZNVER5): New definition
655 (processor_cost_table): Add znver5.
656 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
657 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
658 (PTA_ZNVER5): New definition.
659 * config/i386/i386.md (define_attr "cpu"): Add znver5.
660 (Scheduling descriptions) Add znver5.md.
661 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
662 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
663 (ix86_adjust_cost): Likewise.
664 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
665 (avx512_store_by_pieces): Add m_ZNVER5.
666 * doc/extend.texi: Add znver5.
667 * doc/invoke.texi: Likewise.
668 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
670 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
672 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
673 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
674 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
675 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
676 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
677 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
679 2024-03-18 liuhongt <hongtao.liu@intel.com>
681 PR target/114334
682 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
683 (MODEF248): New mode iterator.
684 (ssevecmodesuffix): Hanlde BF and HF.
685 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
686 (<code><mode>3): Ditto.
688 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
690 PR rtl-optimization/112415
691 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
692 for symbolic memory operands.
693 (pa_legitimate_address_p): Revise LO_SUM condition.
694 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
695 comment about GNU linker to predicates.md.
696 * config/pa/predicates.md (floating_point_store_memory_operand):
697 Revise condition for symbolic memory operands. Update
698 comment.
700 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
702 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
704 2024-03-16 Jakub Jelinek <jakub@redhat.com>
706 PR target/114175
707 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
708 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
709 if arg.type is NULL.
711 2024-03-16 Jakub Jelinek <jakub@redhat.com>
713 PR tree-optimization/114329
714 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
715 build_bit_field_ref method.
716 (bitint_large_huge::build_bit_field_ref): New method.
717 (bitint_large_huge::lower_mergeable_stmt): Use it.
719 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
721 * config/riscv/riscv.opt.urls: Regenerated.
722 * config/rs6000/sysv4.opt.urls: Likewise.
723 * config/xtensa/xtensa.opt.urls: Likewise.
725 2024-03-15 Jakub Jelinek <jakub@redhat.com>
727 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
728 betwee -> between.
729 * edit-context.cc (class line_event): Fix comment typo,
730 betweeen -> between.
732 2024-03-15 Jakub Jelinek <jakub@redhat.com>
734 PR target/114339
735 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
736 a pasto, compare code against LE rather than GE.
738 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
740 * match.pd: Fix truncation pattern for -fno-signed-zeroes
742 2024-03-15 Jakub Jelinek <jakub@redhat.com>
744 PR middle-end/114332
745 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
747 2024-03-15 Jakub Jelinek <jakub@redhat.com>
749 PR tree-optimization/113466
750 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
751 member.
752 (bitint_large_huge::bitint_large_huge): Initialize it.
753 (bitint_large_huge::~bitint_large_huge): Release it.
754 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
755 before which at least one statement has been inserted.
756 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
757 calls to a different block and add corresponding PHIs.
759 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
761 * config/mips/mips.opt: Support -mstrict-align, and use
762 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
763 as alias.
764 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
765 * config/mips/mips.opt.urls: Regenerate.
766 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
768 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
770 PR middle-end/114108
771 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
772 vect_convert_output with the correct vecitype.
774 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
776 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
777 Remove masking of operand 3.
779 2024-03-14 Jason Merrill <jason@redhat.com>
781 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
782 comments.
784 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
786 PR target/114288
787 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
788 14-bit displacements before reload for modes that may use
789 a floating-point load or store.
791 2024-03-14 David Faust <david.faust@oracle.com>
793 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
795 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
797 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
798 patterns ahead of the l32i.n and s32i.n.
800 2024-03-14 Jakub Jelinek <jakub@redhat.com>
802 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
804 2024-03-14 Jakub Jelinek <jakub@redhat.com>
806 PR middle-end/113907
807 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
808 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
809 functions.
811 2024-03-14 Xi Ruoyao <xry111@xry111.site>
813 * config/loongarch/loongarch.md (any_ge): Remove.
814 (sge<u>_<X:mode><GPR:mode>): Remove.
816 2024-03-14 Jakub Jelinek <jakub@redhat.com>
818 PR target/114310
819 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
820 TImode force newval into a register.
822 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
824 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
825 (OMP_CLAUSE__CACHE__READONLY): New macro.
826 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
827 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
828 OMP_CLAUSE__CACHE__READONLY.
829 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
830 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
832 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
834 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
835 for misaligned symbols.
836 * config/s390/s390.opt: Improve documentation.
838 2024-03-14 Jakub Jelinek <jakub@redhat.com>
840 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
841 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
842 are computed, recompute immediate dominator of other_edge->src
843 and other_edge->dest.
844 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
845 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
846 with update it for bb splitting.
848 2024-03-14 liuhongt <hongtao.liu@intel.com>
850 * config/i386/i386-features.cc
851 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
852 (convert_scalars_to_vector): Ditto.
853 * config/i386/i386-features.h (class scalar_chain): New
854 memeber control_flow_insns.
856 2024-03-13 Jakub Jelinek <jakub@redhat.com>
858 PR middle-end/114319
859 * gimple-ssa-store-merging.cc
860 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
861 allow matching __builtin_bswap64 if there is bswapsi2 optab.
863 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
865 * config/s390/s390.cc (s390_secondary_reload): Guard
866 SYMBOL_FLAG_NOTALIGN2_P.
868 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
870 * config/s390/s390-builtin-types.def: Update to reflect latest
871 changes.
872 * config/s390/s390-builtins.def: Streamline vector builtins with
873 LLVM.
875 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
877 * config/s390/s390-builtins.def (vec_permi): Deprecate.
878 (vec_ctd): Deprecate.
879 (vec_ctd_s64): Deprecate.
880 (vec_ctd_u64): Deprecate.
881 (vec_ctsl): Deprecate.
882 (vec_ctul): Deprecate.
883 (vec_ld2f): Deprecate.
884 (vec_st2f): Deprecate.
885 (vec_insert): Deprecate overloads with bool vectors.
887 2024-03-13 Jakub Jelinek <jakub@redhat.com>
889 PR middle-end/114313
890 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
891 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
892 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
893 rhs_type to limb_access for the bitfield load cases.
894 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
895 lhs_type to limb_access if nlhs is non-NULL.
897 2024-03-13 Jakub Jelinek <jakub@redhat.com>
899 PR sanitizer/112709
900 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
901 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
902 gsi_safe_insert_before instead of gsi_insert_before.
904 2024-03-13 Jakub Jelinek <jakub@redhat.com>
906 PR sanitizer/112709
907 * gimple-iterator.h (gsi_safe_insert_before,
908 gsi_safe_insert_seq_before): Declare.
909 * gimple-iterator.cc: Include gimplify.h.
910 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
911 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
912 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
913 instrument_nonnull_arg, instrument_nonnull_return): Use
914 gsi_safe_insert_before instead of gsi_insert_before.
915 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
916 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
917 instead of force_gimple_operand_gsi.
918 (instrument_object_size): Likewise. Use gsi_safe_insert_before
919 instead of gsi_insert_before.
921 2024-03-12 Richard Biener <rguenther@suse.de>
923 PR tree-optimization/114121
924 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
925 converted operand properly.
926 (chrec_fold_multiply): Likewise. Handle missed recursion.
928 2024-03-12 Jakub Jelinek <jakub@redhat.com>
930 PR sanitizer/112709
931 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
932 stores on the caller side unless it is a call to a builtin or
933 internal function or function doesn't return by hidden reference.
934 (maybe_instrument_call): Likewise.
935 (instrument_derefs): Instrument stores to RESULT_DECL if
936 returning by hidden reference.
938 2024-03-12 Jakub Jelinek <jakub@redhat.com>
940 PR tree-optimization/114293
941 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
942 max is smaller than min, set max to ~(size_t)0.
944 2024-03-12 Pan Li <pan2.li@intel.com>
946 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
947 code style greater than 80 chars.
948 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
949 with 3 space(s) and argument unalignment.
951 2024-03-12 Richard Biener <rguenther@suse.de>
953 PR tree-optimization/114297
954 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
955 live stmts SLP node to vect_create_epilog_for_reduction.
957 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
959 PR driver/114314
960 * common.opt (fmultiflags): Add RejectNegative.
962 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
964 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
965 * config/aarch64/aarch64.opt: Likewise.
966 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
967 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
968 (aarch64_expand_epilogue): Likewise.
969 (aarch64_post_cfi_startproc): Likewise.
970 (aarch64_handle_no_branch_protection): Copy and rename.
971 (aarch64_handle_standard_branch_protection): Likewise.
972 (aarch64_handle_pac_ret_protection): Likewise.
973 (aarch64_handle_pac_ret_leaf): Likewise.
974 (aarch64_handle_pac_ret_b_key): Likewise.
975 (aarch64_handle_bti_protection): Likewise.
976 (aarch64_override_options): Update branch protection validation.
977 (aarch64_handle_attr_branch_protection): Likewise.
978 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
979 Pass branch protection type description as argument.
980 (struct aarch_branch_protect_type): Move from aarch-common.h.
981 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
982 Remove.
983 (aarch_handle_standard_branch_protection): Remove.
984 (aarch_handle_pac_ret_protection): Remove.
985 (aarch_handle_pac_ret_leaf): Remove.
986 (aarch_handle_pac_ret_b_key): Remove.
987 (aarch_handle_bti_protection): Remove.
988 (aarch_validate_mbranch_protection): Pass branch protection type
989 description as argument.
990 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
991 (struct aarch_branch_protect_type): Remove.
992 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
993 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
994 (arm_handle_standard_branch_protection): Likewise.
995 (arm_handle_pac_ret_protection): Likewise.
996 (arm_handle_pac_ret_leaf): Likewise.
997 (arm_handle_bti_protection): Likewise.
998 (arm_configure_build_target): Update branch protection validation.
999 * config/arm/arm.opt: Remove aarch_ra_sign_key.
1001 2024-03-11 Richard Biener <rguenther@suse.de>
1003 PR middle-end/114299
1004 * gimplify.cc (internal_get_tmp_var): When gimplification
1005 of VAL failed, return a decl.
1007 2024-03-11 Jakub Jelinek <jakub@redhat.com>
1009 PR tree-optimization/114278
1010 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
1011 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
1013 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
1015 PR debug/113519
1016 PR debug/113777
1017 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
1018 generate the DIE with the same parent as in the regular case.
1020 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
1022 PR middle-end/95351
1023 * fold-const.cc (merge_truthop_with_opposite_arm): Use
1024 the type of the operands of the comparison and not the type
1025 of the comparison.
1027 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1029 PR tree-optimization/110199
1030 * tree-ssa-scopedtables.cc
1031 (avail_exprs_stack::simplify_binary_operation): Generalize handling
1032 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
1033 comparison operands for other cases.
1035 2024-03-10 Pan Li <pan2.li@intel.com>
1037 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
1038 during transform process.
1039 (vectorizable_load): Ditto.
1041 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1043 PR target/102250
1044 * doc/install.texi: Document need for python when building
1045 RISC-V compilers.
1047 2024-03-10 jlaw <jeffreyalaw@gmail.com>
1049 PR target/111362
1050 * mode-switching.cc (optimize_mode_switching): Only process
1051 NONDEBUG insns.
1053 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
1055 * config/avr/avr.md: Fix typos in comment, indentation glitches
1056 and some other nits.
1058 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1060 PR target/114284
1061 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
1062 src containing MEMs unless prop.likely_profitable_p ().
1064 2024-03-09 Xi Ruoyao <xry111@xry111.site>
1066 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
1067 Support 'Q' for R_LARCH_RELAX for TLS IE.
1068 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
1069 IE.
1070 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
1072 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
1074 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
1075 usum_widenqihi and add_zero_extend1.
1076 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
1077 sub+sign_extend.
1078 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
1079 Compute exact insn lengths.
1080 (*usum_widenqihi3): Allow input operands to commute.
1082 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1084 * config/i386/i386.opt.urls: Regenerate.
1086 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
1088 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
1089 In loongarch64, a sign extension operation is added when
1090 operands[2] is a register operand and the mode is SImode.
1092 2024-03-08 Martin Jambor <mjambor@suse.cz>
1094 PR ipa/113757
1095 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
1096 id->killed_new_ssa_names.
1098 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
1100 PR target/113790
1101 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
1102 for non-reload pseudo too.
1104 2024-03-08 David Faust <david.faust@oracle.com>
1106 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
1107 not attempt inline expansion if size is above threshold.
1108 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
1109 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
1110 Document.
1112 2024-03-08 Richard Biener <rguenther@suse.de>
1114 PR tree-optimization/114269
1115 PR tree-optimization/114074
1116 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
1117 in the third CASE_CONVERT case as well.
1118 (chrec_fold_multiply): Handle sign-conversions from unsigned
1119 by performing the operation in the unsigned type.
1121 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
1123 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
1124 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
1126 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1128 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
1129 asm_noperands < 0 means it is not asm goto too.
1131 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1133 PR target/38534
1134 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
1135 option.
1136 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
1137 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
1138 ix86_noreturn_no_callee_saved_registers is enabled.
1139 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
1141 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1143 PR debug/113918
1144 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
1145 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
1147 2024-03-08 demin.han <demin.han@starfivetech.com>
1149 PR target/114264
1150 * config/riscv/riscv-vector-costs.cc: Fix ICE
1152 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
1154 * fwprop.cc (forward_propagate_into): Return false for volatile set
1155 source rtx.
1157 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
1159 PR target/113618
1160 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
1161 (aarch64_expand_cpymem): Emit single load/store only.
1162 (aarch64_set_one_block): Emit single stores only.
1164 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
1166 PR middle-end/114196
1167 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
1168 vectorization guards.
1170 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
1172 * doc/cppopts.texi: Remove incorrect claim about -dD not
1173 outputting predefined macros.
1175 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
1177 PR target/113950
1178 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
1179 and simplify else if with else.
1181 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
1183 * system.h: Include safe-ctype.h after C++ standard headers.
1185 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1187 PR rtl-optimization/110079
1188 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
1189 asm goto.
1191 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1193 PR middle-end/105533
1194 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
1195 if val is not HOST_WIDE_INT_MIN or if mode has exactly
1196 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
1197 val - 1.
1199 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1201 PR middle-end/105533
1202 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
1203 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
1204 LOG2_BITS_PER_UNIT.
1206 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
1208 * config.gcc: Add a case for loongarch*-*-linux-musl*.
1209 * config/loongarch/linux.h: Disable the multilib-compatible
1210 treatment for *musl* targets.
1211 * config/loongarch/musl.h: New file.
1213 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1215 PR tree-optimization/114009
1216 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
1217 argument even for GENERIC, not just for GIMPLE.
1218 * match.pd (a * !a -> 0): New simplifications.
1220 2024-03-07 demin.han <demin.han@starfivetech.com>
1222 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
1223 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
1224 (expand_vec_cmp_float): Adapt arguments
1226 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1228 PR target/114232
1229 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
1230 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1231 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1232 (<plusminus:insn>v2qi3): Enable for optimize_size instead
1233 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1234 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1235 (<any_shift:insn>v2qi3): Enable for optimize_size instead
1236 of optimize_function_for_size_p.
1238 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1240 PR target/114200
1241 PR target/114202
1242 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
1244 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1246 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
1247 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
1248 offset handling.
1249 (costs::add_stmt_cost): Also adjust cost for statements without
1250 stmt_info.
1251 * config/riscv/riscv-vector-costs.h: Define zero constant.
1253 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
1255 PR target/113915
1256 * config/arm/arm.md (NOCOND): Improve comment.
1257 (arm_rev*) Add predicable.
1258 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
1259 PREDICABLE_YES.
1261 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
1263 PR target/113001
1264 PR target/112871
1265 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
1266 operands when the comparison operand is the same as the false
1267 arm for a NE test.
1269 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1271 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
1272 Eliminate common code and use generic code instead.
1274 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
1276 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1277 rtx cost.
1279 2024-03-06 Richard Biener <rguenther@suse.de>
1281 PR tree-optimization/114239
1282 * tree-vect-loop.cc (vect_get_vect_def): Remove.
1283 (vect_create_epilog_for_reduction): The passed in stmt_info
1284 should now be the live stmt that produces the scalar reduction
1285 result. Revert PR114192 fix. Base reduction info off
1286 info_for_reduction. Remove special handling of
1287 early-break/peeled, restore original vector def gathering.
1288 Make sure to pick the correct exit PHIs.
1289 (vectorizable_live_operation): Pass in the proper stmt_info
1290 for early break exits.
1292 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
1294 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1295 out-of-class definitions of static constants.
1297 2024-03-06 Richard Biener <rguenther@suse.de>
1299 PR tree-optimization/114249
1300 * tree-vect-slp.cc (vect_build_slp_instance): Move making
1301 a BB reduction lane number even ...
1302 (vect_slp_check_for_roots): ... here to avoid leaking
1303 pattern defs.
1305 2024-03-06 Richard Biener <rguenther@suse.de>
1307 PR tree-optimization/114246
1308 * tree-ssa-dse.cc (increment_start_addr): Strip useless
1309 type conversions from the adjusted address.
1311 2024-03-06 Jakub Jelinek <jakub@redhat.com>
1313 PR rtl-optimization/114190
1314 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1315 Call df_remove_problem for df_note before calling df_analyze.
1317 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
1318 Indu Bhagat <indu.bhagat@oracle.com>
1320 PR debug/114186
1321 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1322 in the correct order of the dimensions.
1323 (gen_ctf_subrange_type): Refactor out handling of
1324 DW_TAG_subrange_type DIE to here.
1326 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1328 PR sanitizer/97696
1329 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1331 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1333 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1334 and luti_strided.
1335 * config/aarch64/aarch64-sme.md
1336 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1337 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1338 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1339 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1340 (early_ra::maybe_convert_to_strided_access): Remove support for
1341 strided LUTI2 and LUTI4.
1343 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
1345 PR target/113510
1346 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1347 low_register_operand.
1349 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
1351 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1352 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1353 to "X = Y, X o= CST".
1355 2024-03-05 Xi Ruoyao <xry111@xry111.site>
1357 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1358 s9 as an alias of r22.
1360 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
1362 * config/avr/avr-protos.h (avr_out_insv): New proto.
1363 * config/avr/avr.cc (avr_out_insv): New function.
1364 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1365 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1366 * config/avr/avr.md (define_attr "adjust_len") Add insv.
1367 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1368 Add constraint alternative where the 3rd operand is a power
1369 of 2, and the source register may differ from the destination.
1370 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1371 instructions. Set attr "length" to "insv".
1372 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1374 2024-03-05 Richard Biener <rguenther@suse.de>
1376 PR tree-optimization/114231
1377 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1378 processing a BB SLP root.
1380 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1382 PR rtl-optimization/114211
1383 * lower-subreg.cc (resolve_simple_move): For double-word
1384 rotates by BITS_PER_WORD if there is overlap between source
1385 and destination use a temporary.
1387 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1389 PR middle-end/114157
1390 * gimple-lower-bitint.cc: Include stor-layout.h.
1391 (mergeable_op): Return true for BIT_FIELD_REF.
1392 (struct bitint_large_huge): Declare handle_bit_field_ref method.
1393 (bitint_large_huge::handle_bit_field_ref): New method.
1394 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1396 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1398 PR target/114116
1399 * config/i386/i386.h (enum call_saved_registers_type): Add
1400 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1401 * config/i386/i386-options.cc (ix86_set_func_type): Remove
1402 has_no_callee_saved_registers variable, add no_callee_saved_registers
1403 instead, initialize it depending on whether it is
1404 no_callee_saved_registers function or not. Don't set it if
1405 no_caller_saved_registers attribute is present. Adjust users.
1406 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1407 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1408 TYPE_NO_CALLEE_SAVED_REGISTERS.
1409 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1411 2024-03-05 Pan Li <pan2.li@intel.com>
1413 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1414 mode_size related code.
1416 2024-03-05 Patrick Palka <ppalka@redhat.com>
1418 * doc/invoke.texi (-Wno-global-module): Document.
1420 2024-03-04 David Faust <david.faust@oracle.com>
1422 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1423 * config/bpf/bpf.cc (bpf_expand_setmem): New.
1424 * config/bpf/bpf.md (setmemdi): New define_expand.
1426 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1428 PR rtl-optimization/113010
1429 * combine.cc (simplify_comparison): Guard the
1430 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1431 and initialize inner_mode.
1433 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1435 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1436 VMLALDAVAXQ_U cases.
1437 (VMLALDAVXQ): Remove iterator.
1438 (VMLALDAVXQ_P): Likewise.
1439 (VMLALDAVAXQ): Likewise.
1440 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1441 mode iterator attribute with V4BI mode.
1442 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1443 VMLALDAVAXQ_U): Remove unused unspecs.
1445 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1447 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1448 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1449 attribute.
1450 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1451 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1452 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1453 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1454 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1455 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1456 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1457 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1458 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1459 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1461 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1463 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1464 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1465 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1466 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1467 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1468 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1469 (arm_vcx1q<a>v16qi): Likewise.
1470 (arm_vcx1qav16qi): Likewise.
1471 (arm_vcx1qv16qi): Likewise.
1472 (arm_vcx2q<a>_p_v16qi): Likewise.
1473 (arm_vcx2q<a>v16qi): Likewise.
1474 (arm_vcx2qav16qi): Likewise.
1475 (arm_vcx2qv16qi): Likewise.
1476 (arm_vcx3q<a>_p_v16qi): Likewise.
1477 (arm_vcx3q<a>v16qi): Likewise.
1478 (arm_vcx3qav16qi): Likewise.
1479 (arm_vcx3qv16qi): Likewise.
1480 (@mve_<mve_insn>q_<supf><mode>): Likewise.
1481 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1482 (@mve_<mve_insn>q_<supf>v4si): Likewise.
1483 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1484 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1485 (@mve_<mve_insn>q_f<mode>): Likewise.
1486 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1487 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1488 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1489 (@mve_<mve_insn>q_m_f<mode>): Likewise.
1490 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1491 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1492 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1493 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1494 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1495 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1496 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1497 (mve_v<absneg_str>q_f<mode>): Likewise.
1498 (mve_<mve_addsubmul>q<mode>): Likewise.
1499 (mve_<mve_addsubmul>q_f<mode>): Likewise.
1500 (mve_vadciq_<supf>v4si): Likewise.
1501 (mve_vadciq_m_<supf>v4si): Likewise.
1502 (mve_vadcq_<supf>v4si): Likewise.
1503 (mve_vadcq_m_<supf>v4si): Likewise.
1504 (mve_vandq_<supf><mode>): Likewise.
1505 (mve_vandq_f<mode>): Likewise.
1506 (mve_vandq_m_<supf><mode>): Likewise.
1507 (mve_vandq_m_f<mode>): Likewise.
1508 (mve_vandq_s<mode>): Likewise.
1509 (mve_vandq_u<mode>): Likewise.
1510 (mve_vbicq_<supf><mode>): Likewise.
1511 (mve_vbicq_f<mode>): Likewise.
1512 (mve_vbicq_m_<supf><mode>): Likewise.
1513 (mve_vbicq_m_f<mode>): Likewise.
1514 (mve_vbicq_m_n_<supf><mode>): Likewise.
1515 (mve_vbicq_n_<supf><mode>): Likewise.
1516 (mve_vbicq_s<mode>): Likewise.
1517 (mve_vbicq_u<mode>): Likewise.
1518 (@mve_vclzq_s<mode>): Likewise.
1519 (mve_vclzq_u<mode>): Likewise.
1520 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1521 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1522 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1523 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1524 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1525 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1526 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1527 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1528 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1529 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1530 (mve_vcvtaq_<supf><mode>): Likewise.
1531 (mve_vcvtaq_m_<supf><mode>): Likewise.
1532 (mve_vcvtbq_f16_f32v8hf): Likewise.
1533 (mve_vcvtbq_f32_f16v4sf): Likewise.
1534 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1535 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1536 (mve_vcvtmq_<supf><mode>): Likewise.
1537 (mve_vcvtmq_m_<supf><mode>): Likewise.
1538 (mve_vcvtnq_<supf><mode>): Likewise.
1539 (mve_vcvtnq_m_<supf><mode>): Likewise.
1540 (mve_vcvtpq_<supf><mode>): Likewise.
1541 (mve_vcvtpq_m_<supf><mode>): Likewise.
1542 (mve_vcvtq_from_f_<supf><mode>): Likewise.
1543 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1544 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1545 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1546 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1547 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1548 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1549 (mve_vcvtq_to_f_<supf><mode>): Likewise.
1550 (mve_vcvttq_f16_f32v8hf): Likewise.
1551 (mve_vcvttq_f32_f16v4sf): Likewise.
1552 (mve_vcvttq_m_f16_f32v8hf): Likewise.
1553 (mve_vcvttq_m_f32_f16v4sf): Likewise.
1554 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1555 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1556 (mve_veorq_s><mode>): Likewise.
1557 (mve_veorq_u><mode>): Likewise.
1558 (mve_veorq_f<mode>): Likewise.
1559 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1560 (mve_vidupq_u<mode>_insn): Likewise.
1561 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1562 (mve_viwdupq_wb_u<mode>_insn): Likewise.
1563 (mve_vldrbq_<supf><mode>): Likewise.
1564 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1565 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1566 (mve_vldrbq_z_<supf><mode>): Likewise.
1567 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1568 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1569 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1570 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1571 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1572 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1573 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1574 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1575 (mve_vldrhq_<supf><mode>): Likewise.
1576 (mve_vldrhq_fv8hf): Likewise.
1577 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1578 (mve_vldrhq_gather_offset_fv8hf): Likewise.
1579 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1580 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1581 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1582 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1583 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1584 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1585 (mve_vldrhq_z_<supf><mode>): Likewise.
1586 (mve_vldrhq_z_fv8hf): Likewise.
1587 (mve_vldrwq_<supf>v4si): Likewise.
1588 (mve_vldrwq_fv4sf): Likewise.
1589 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1590 (mve_vldrwq_gather_base_fv4sf): Likewise.
1591 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1592 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1593 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1594 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1595 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1596 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1597 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1598 (mve_vldrwq_gather_offset_fv4sf): Likewise.
1599 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1600 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1601 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1602 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1603 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1604 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1605 (mve_vldrwq_z_<supf>v4si): Likewise.
1606 (mve_vldrwq_z_fv4sf): Likewise.
1607 (mve_vmvnq_s<mode>): Likewise.
1608 (mve_vmvnq_u<mode>): Likewise.
1609 (mve_vornq_<supf><mode>): Likewise.
1610 (mve_vornq_f<mode>): Likewise.
1611 (mve_vornq_m_<supf><mode>): Likewise.
1612 (mve_vornq_m_f<mode>): Likewise.
1613 (mve_vornq_s<mode>): Likewise.
1614 (mve_vornq_u<mode>): Likewise.
1615 (mve_vorrq_<supf><mode>): Likewise.
1616 (mve_vorrq_f<mode>): Likewise.
1617 (mve_vorrq_m_<supf><mode>): Likewise.
1618 (mve_vorrq_m_f<mode>): Likewise.
1619 (mve_vorrq_m_n_<supf><mode>): Likewise.
1620 (mve_vorrq_n_<supf><mode>): Likewise.
1621 (mve_vorrq_s<mode>): Likewise.
1622 (mve_vorrq_s<mode>): Likewise.
1623 (mve_vsbciq_<supf>v4si): Likewise.
1624 (mve_vsbciq_m_<supf>v4si): Likewise.
1625 (mve_vsbcq_<supf>v4si): Likewise.
1626 (mve_vsbcq_m_<supf>v4si): Likewise.
1627 (mve_vshlcq_<supf><mode>): Likewise.
1628 (mve_vshlcq_m_<supf><mode>): Likewise.
1629 (mve_vshrq_m_n_<supf><mode>): Likewise.
1630 (mve_vshrq_n_<supf><mode>): Likewise.
1631 (mve_vstrbq_<supf><mode>): Likewise.
1632 (mve_vstrbq_p_<supf><mode>): Likewise.
1633 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1634 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1635 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1636 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1637 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1638 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1639 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1640 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1641 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1642 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1643 (mve_vstrhq_<supf><mode>): Likewise.
1644 (mve_vstrhq_fv8hf): Likewise.
1645 (mve_vstrhq_p_<supf><mode>): Likewise.
1646 (mve_vstrhq_p_fv8hf): Likewise.
1647 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1648 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1649 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1650 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1651 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1652 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1653 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1654 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1655 (mve_vstrwq_<supf>v4si): Likewise.
1656 (mve_vstrwq_fv4sf): Likewise.
1657 (mve_vstrwq_p_<supf>v4si): Likewise.
1658 (mve_vstrwq_p_fv4sf): Likewise.
1659 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1660 (mve_vstrwq_scatter_base_fv4sf): Likewise.
1661 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1662 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1663 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1664 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1665 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1666 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1667 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1668 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1669 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1670 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1671 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1672 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1673 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1674 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1676 2024-03-04 Marek Polacek <polacek@redhat.com>
1678 * doc/extend.texi: Update [[gnu::no_dangling]].
1680 2024-03-04 Andrew Stubbs <ams@baylibre.com>
1682 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1683 * expr.cc (store_constructor): Likewise.
1684 (do_store_flag): Likewise.
1686 2024-03-04 Mark Wielaard <mark@klomp.org>
1688 * common.opt.urls: Regenerate.
1689 * config/avr/avr.opt.urls: Likewise.
1690 * config/i386/i386.opt.urls: Likewise.
1691 * config/pru/pru.opt.urls: Likewise.
1692 * config/riscv/riscv.opt.urls: Likewise.
1693 * config/rs6000/rs6000.opt.urls: Likewise.
1695 2024-03-04 Richard Biener <rguenther@suse.de>
1697 PR tree-optimization/114197
1698 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1699 there are volatile bitfield accesses.
1700 (pass_if_conversion::execute): Throw away result if the
1701 if-converted and original loops are not nested as expected.
1703 2024-03-04 Richard Biener <rguenther@suse.de>
1705 PR tree-optimization/114164
1706 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1707 the code generated for mask argument setup is not supported.
1709 2024-03-04 Richard Biener <rguenther@suse.de>
1711 PR tree-optimization/114203
1712 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1713 adjustment before making the result defined at zero.
1715 2024-03-04 Richard Biener <rguenther@suse.de>
1717 PR tree-optimization/114192
1718 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1719 appropriate def for the live out stmt in case of an alternate
1720 exit.
1722 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1724 PR middle-end/114209
1725 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1726 unshare_expr when creating a MEM_REF from MEM_REF.
1727 (bitint_large_huge::lower_stmt): Call unshare_expr.
1729 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1731 PR target/114184
1732 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1733 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1734 register.
1736 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
1738 PR target/114187
1739 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1740 lowpart_subreg to perform type conversion, to avoid confusion
1741 over the offset to use in the call to simplify_reg_subreg.
1743 2024-03-03 Greg McGary <gkm@rivosinc.com>
1745 PR rtl-optimization/113010
1746 * combine.cc (simplify_comparison): Simplify a SUBREG on
1747 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1748 MEM load.
1750 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1752 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
1753 Use bool in place of int for boolean logic (if possible).
1754 Move declarations to definitions (if possible).
1755 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
1756 * config/avr/avr-dimode.md: Same.
1757 * config/avr/constraints.md: Same.
1758 * config/avr/predicates.md: Same.
1760 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
1762 PR target/113720
1763 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
1764 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
1765 simplify insn RTX using UMUL_HIGHPART rtx_code.
1766 (*umuldi3_highpart_const): Remove.
1768 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1770 PR target/114100
1771 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
1772 * config/avr/avr.cc (_reg_unused_after): Make static. And
1773 add 3rd argument to skip the current insn.
1774 (reg_unused_after): Adjust call of reg_unused_after.
1775 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
1776 unneeded frame pointer adjustments.
1778 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1780 PR target/92729
1781 * config/avr/avr.md (define_attr "cc"): Remove.
1782 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1783 from prototype.
1784 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1785 its uses. Add insn argument.
1786 (avr_out_plus_symbol): Remove pcc argument and its uses.
1787 (avr_out_plus): Remove pcc argument and its uses.
1788 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1789 (avr_out_round): Adjust call of avr_out_plus.
1791 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1793 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1794 from r14-9273.
1796 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
1798 PR target/101737
1799 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1800 is not an insn, but e.g. a code label.
1802 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1804 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1805 * config/avr/avr.cc: Use them instead of magic numbers when it
1806 means a register number.
1808 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1810 * config/avr/avr.cc: Adjust some comments.
1812 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1814 PR target/114100
1815 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1816 the low part of the frame pointer with 8-bit stack pointer.
1818 2024-03-01 Patrick Palka <ppalka@redhat.com>
1820 PR c++/104919
1821 PR c++/106009
1822 * tree-inline.cc (remap_decl): Handle copy_decl returning the
1823 original decl.
1824 (remap_decls): Handle remap_decl returning the original decl.
1825 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
1826 CONST_DECL.
1828 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
1830 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
1831 type attribute.
1832 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
1833 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
1834 (movhi_internal, movqi_internal): Likewise.
1835 (movsf_softfloat, movsf_hardfloat): Likewise.
1836 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
1837 (movdf_softfloat): Likewise.
1839 2024-03-01 Marek Polacek <polacek@redhat.com>
1841 PR c++/110358
1842 PR c++/109642
1843 * doc/extend.texi: Document gnu::no_dangling.
1844 * doc/invoke.texi: Mention that gnu::no_dangling disables
1845 -Wdangling-reference.
1847 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1849 * config/avr/avr.opt: Overhaul help screen.
1851 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1852 Tobias Burnus <tburnus@baylibre.com>
1854 PR c++/110347
1855 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
1856 lang_hooks.decls.omp_disregard_value_expr for
1857 (first)private in target regions.
1859 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1861 PR middle-end/114136
1862 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
1863 n_named_args initially before INIT_CUMULATIVE_ARGS to
1864 structure_value_addr_parm rather than 0, after it don't modify
1865 it if strict_argument_naming and clear only if
1866 !pretend_outgoing_varargs_named.
1868 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1870 PR debug/114015
1871 * dwarf2out.cc (should_move_die_to_comdat): Return false for
1872 aggregates without DW_AT_byte_size attribute or with non-constant
1873 DW_AT_byte_size.
1875 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1877 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
1878 valid values for level.
1880 2024-03-01 Richard Biener <rguenther@suse.de>
1882 PR middle-end/114070
1883 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
1884 Allow the folding if before lowering and the current IL
1885 isn't supported with vcond_mask.
1887 2024-03-01 xuli <xuli1@eswincomputing.com>
1889 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
1890 attribute to riscv_attribute_table.
1891 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
1892 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
1893 * doc/extend.texi: Add riscv_vector_cc attribute description.
1895 2024-03-01 Pan Li <pan2.li@intel.com>
1897 PR target/112817
1898 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
1899 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
1900 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
1901 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
1902 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
1903 comments for option replacement.
1904 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
1905 riscv_autovec_preference to rvv_vector_bits.
1906 (vls_mode_valid_p): Ditto.
1907 (estimated_poly_value): Ditto.
1908 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
1909 vector chunks and honor new option mrvv-vector-bits.
1910 (riscv_override_options_internal): Update comments and rename the
1911 vector chunks.
1912 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
1913 internal option param=riscv-autovec-preference.
1915 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1917 * function.cc (assign_parms): Only call assign_parms_setup_varargs
1918 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
1920 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1922 PR middle-end/114156
1923 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
1924 rhs1 of a VCE to have no underlying variable if it is a load and
1925 handle that case.
1927 2024-02-29 David Malcolm <dmalcolm@redhat.com>
1929 PR analyzer/114159
1930 * function.cc (function_name): Make param const.
1931 * function.h (function_name): Likewise.
1933 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1935 PR target/114100
1936 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
1937 * config/avr/avr.opt (-mfuse-add=): New target option.
1938 * common/config/avr/avr-common.cc (avr_option_optimization_table)
1939 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
1940 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
1941 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
1942 * config/avr/avr-protos.h (avr_split_tiny_move)
1943 (make_avr_pass_fuse_add): New protos.
1944 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
1945 avr_split_tiny_move to split indirect memory accesses.
1946 (gen_move_clobbercc): New define_expand helper.
1947 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
1948 (avr_pass_fuse_add): New class from rtl_opt_pass.
1949 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
1950 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
1951 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
1952 of PLUS addressing for AVR_TINY.
1953 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
1954 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
1955 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
1957 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1959 PR target/114132
1960 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
1961 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
1962 (avr_function_arg): Set it.
1963 (avr_frame_pointer_required_p): Use it instead of .nregs.
1965 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
1967 PR target/108174
1968 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
1969 static and mark with GTY.
1971 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1973 * config/loongarch/loongarch.md
1974 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
1976 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1978 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
1979 (crc): New define_int_attr.
1980 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
1981 into ...
1982 (loongarch_<crc>_w_<size>_w): ... here.
1984 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
1986 PR target/114130
1987 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
1988 extend the expected value if needed.
1990 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1992 * config.gcc (target_gtfiles): Change coreout to btfext-out.
1993 (extra_objs): Change coreout to btfext-out.
1994 * config/bpf/coreout.cc: Rename to btfext-out.cc.
1995 * config/bpf/btfext-out.cc: Add.
1996 * config/bpf/coreout.h: Rename to btfext-out.h.
1997 * config/bpf/btfext-out.h: Add.
1998 * config/bpf/core-builtins.cc: Change include.
1999 * config/bpf/core-builtins.h: Change include.
2000 * config/bpf/t-bpf: Accomodate renamed files.
2002 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2004 PR target/113453
2005 * config/bpf/bpf.cc (bpf_function_prologue): Define target
2006 hook.
2007 * config/bpf/coreout.cc (brf_ext_info_section)
2008 (btf_ext_info): Move from coreout.h
2009 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
2010 (bpf_core_reloc): Rename to btf_ext_core_reloc.
2011 (btf_ext): Add static variable.
2012 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
2013 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
2014 (btf_ext_add_string, btf_funcinfo_type_callback)
2015 (btf_add_func_info_for, btf_validate_funcinfo)
2016 (btf_ext_info_len, output_btfext_func_info): Add function.
2017 (output_btfext_header, bpf_core_reloc_add)
2018 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
2019 Change to support new structs.
2020 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
2021 Move and change in coreout.cc.
2022 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
2024 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2026 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
2027 enabled by default for BPF.
2028 (bpf_file_end): Call BTF deallocation.
2029 (bpf_asm_init_sections): Correct condition.
2030 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
2031 deallocation.
2032 (ctf_debuf_finish): Correct condition for calling
2033 ctf_debug_finalize.
2035 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2037 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
2038 (traverse_btf_func_types): Define function.
2039 * ctfc.h (funcs_traverse_callback): Typedef for function
2040 prototype.
2041 (traverse_btf_func_types): Add prototype.
2043 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
2045 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
2047 2024-02-28 Richard Biener <rguenther@suse.de>
2049 PR tree-optimization/113831
2050 PR tree-optimization/108355
2051 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
2052 PR113831 fix.
2054 2024-02-28 Richard Biener <rguenther@suse.de>
2056 PR tree-optimization/114121
2057 * tree-ssa-sccvn.h (vn_reference_s::offset,
2058 vn_reference_s::max_size): New fields.
2059 (vn_reference_insert_pieces): Adjust prototype.
2060 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
2061 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
2062 size, allow using "don't know" state.
2063 (vn_walk_cb_data::finish): Pass along offset/max_size.
2064 (vn_reference_lookup_or_insert_for_pieces): Take offset and
2065 max_size as argument and use it.
2066 (vn_reference_lookup_3): Properly adjust offset and max_size
2067 according to the adjusted ao_ref.
2068 (vn_reference_lookup_pieces): Initialize offset and max_size.
2069 (vn_reference_lookup): Likewise.
2070 (vn_reference_lookup_call): Likewise.
2071 (vn_reference_insert): Likewise.
2072 (visit_reference_op_call): Likewise.
2073 (vn_reference_insert_pieces): Take offset and max_size
2074 as argument and use it.
2076 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
2078 PR tree-optimization/114075
2079 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
2080 point vectors
2082 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2084 PR tree-optimization/114041
2085 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
2086 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
2088 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2090 PR tree-optimization/113988
2091 * stor-layout.h (bitwise_mode_for_size): Declare.
2092 * stor-layout.cc (bitwise_mode_for_size): New function.
2093 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
2094 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
2095 Use BITS_PER_UNIT instead of 8.
2097 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
2099 PR target/113871
2100 * config/i386/mmx.md (V248FI): Add V2BF mode.
2101 (V24FI_32): Ditto.
2103 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
2105 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
2106 if either ref->offset is not byte aligned or ref->size is not known
2107 to be equal to ref->max_size.
2108 (maybe_trim_complex_store): Fix description.
2109 (maybe_trim_constructor_store): Likewise.
2110 (maybe_trim_partially_dead_store): Likewise.
2112 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
2114 * config/arm/mmintrin.h: Warn if this header is included without
2115 defining __ENABLE_DEPRECATED_IWMMXT.
2117 2024-02-27 Richard Biener <rguenther@suse.de>
2119 PR tree-optimization/114074
2120 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
2121 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
2122 Handle poly vs. non-poly multiplication correctly with respect
2123 to undefined behavior on overflow.
2125 2024-02-27 Jakub Jelinek <jakub@redhat.com>
2127 PR rtl-optimization/114044
2128 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
2129 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
2130 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
2131 expand_PARITY): Declare.
2132 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
2133 expand_CTZ, expand_FFS, expand_PARITY): New functions.
2134 (expand_POPCOUNT): Use expand_bitquery.
2136 2024-02-27 Richard Biener <rguenther@suse.de>
2138 PR tree-optimization/114081
2139 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2140 Perform manual dominator update for prologue peeling.
2141 (vect_do_peeling): Properly update dominators after adding the
2142 prologue-around guard.
2144 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2146 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
2147 (mstrict-X): Tag as "Optimization".
2149 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2151 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
2152 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2154 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2155 H.J. Lu <hjl.tools@gmail.com>
2157 PR rtl-optimization/113617
2158 * varasm.cc (default_elf_select_rtx_section): For
2159 references to private symbols in comdat sections
2160 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
2161 or .rodata.<comdat> comdat sections.
2163 2024-02-26 Richard Biener <rguenther@suse.de>
2165 PR tree-optimization/114099
2166 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2167 Create and fill in a needed virtual LC PHI for the alternate
2168 exits. Remove code dealing with that missing.
2170 2024-02-26 Richard Biener <rguenther@suse.de>
2172 PR tree-optimization/114068
2173 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
2174 New function.
2175 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
2176 on the main exit if needed. Remove band-aid for the case
2177 it was missing.
2179 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2181 PR target/114097
2182 * config/i386/i386-options.cc (ix86_set_func_type): Check
2183 interrupt instead of noreturn attribute.
2185 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2187 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
2188 !TARGET_64BIT.
2190 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2192 PR tree-optimization/114090
2193 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
2194 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
2195 types.
2196 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
2198 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2200 PR middle-end/114084
2201 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
2202 if all subtrees of var0 come from one of the op0 or op1 operands
2203 and all subtrees of con0 come from the other one. Don't clear
2204 variables which are never used afterwards.
2206 2024-02-26 Richard Biener <rguenther@suse.de>
2208 PR middle-end/114070
2209 * genmatch.cc (parser::parse_c_expr): Do not record operand
2210 lists but only mark operators used.
2211 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
2212 Properly guard the case of tcc_comparison changing the VEC_COND
2213 value operand type.
2215 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2217 PR target/114094
2218 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
2219 to printed instruction.
2221 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2223 PR target/114098
2224 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
2225 __builtin_ia32_ldtilecfg.
2226 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
2227 * config/i386/i386-builtin.def (BDESC): Add
2228 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
2229 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
2230 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
2231 * config/i386/i386.md (ldtilecfg): New pattern.
2232 (sttilecfg): Likewise.
2234 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
2236 PR tree-optimization/113205
2237 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
2238 the proposed layout if it does not allow a source partition with
2239 layout 2 to keep that layout.
2241 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2243 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
2244 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
2245 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
2246 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
2247 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
2248 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
2249 macros.
2250 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
2251 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
2252 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
2253 HOST_WIDE_INT_UC macros.
2254 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
2255 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
2256 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
2257 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
2258 macros.
2259 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
2260 * config/i386/constraints.md (define_constraint "L"): Use
2261 HOST_WIDE_INT_C macro.
2262 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
2263 macro.
2264 (movl + movb peephole2): Likewise.
2265 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
2266 (const_32bit_mask): Likewise.
2268 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2270 PR middle-end/114073
2271 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
2272 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
2273 types like vector or complex types.
2274 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
2275 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
2276 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2278 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
2280 PR target/114028
2281 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2282 Return false if inner mode is already Pmode.
2283 (rvv_builder::is_all_same_sequence): New function.
2284 (expand_vec_init): Emit broadcast if sequence is all same.
2286 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2288 PR target/113613
2289 * config/aarch64/aarch64-early-ra.cc
2290 (early_ra::m_current_region): New member variable.
2291 (early_ra::m_fpr_recency): Likewise.
2292 (early_ra::start_new_region): Bump m_current_region.
2293 (early_ra::allocate_colors): Prefer less recently used registers
2294 in the event of a tie. Add a comment to explain why we prefer(ed)
2295 higher-numbered registers.
2296 (early_ra::find_oldest_color): Prefer less recently used registers
2297 here too.
2298 (early_ra::finalize_allocation): Update recency information for
2299 allocated registers.
2300 (early_ra::process_blocks): Initialize m_current_region and
2301 m_fpr_recency.
2303 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2305 PR target/113295
2306 * config/aarch64/aarch64-early-ra.cc
2307 (early_ra::test_strictness): New enum.
2308 (early_ra::is_chain_candidate): Add a strictness parameter to
2309 control whether only correctness matters, or whether both correctness
2310 and heuristics should be used. Handle multiple levels of equivalence.
2311 (early_ra::find_related_start): Update call accordingly.
2312 (early_ra::strided_polarity_pref): Likewise.
2313 (early_ra::form_chains): Likewise.
2314 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2315 correctness mode rather than trying to inline the test.
2317 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2319 PR target/113295
2320 * config/aarch64/aarch64-early-ra.cc
2321 (early_ra::find_related_start): Account for definitions by shared
2322 registers when testing for a single register definition.
2323 (early_ra::accumulate_defs): New function.
2324 (early_ra::record_copy): If A shares B's register, fold A's
2325 definition information into B's. Fold A's use information into B's.
2327 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
2329 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2330 if R_X86_64_CODE_6_GOTTPOFF is supported.
2331 * config.in: Regenerated.
2332 * configure: Likewise.
2333 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2334 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2336 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
2338 PR target/108120
2339 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2340 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2342 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2344 PR rtl-optimization/114054
2345 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2346 temp variable instead of target parameter for result.
2348 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2350 PR tree-optimization/114040
2351 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2352 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2353 probability from likely to unlikely. When handling the true true
2354 store, first cast to limb_access_type and then to l's type.
2356 2024-02-23 Richard Biener <rguenther@suse.de>
2358 PR target/90785
2359 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2361 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2363 PR other/109668
2364 * config/riscv/arch-canonicalize: Move to python3
2365 * config/riscv/multilib-generator: Likewise
2367 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2369 * doc/invoke.texi: Document -mcpu.
2371 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
2373 * configure: Regenerate.
2374 * configure.ac: Add parameter "--fatal-warnings" to assemble
2375 when checking whether the assemble support conditional branch
2376 relaxation.
2378 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2380 PR c/114007
2381 * doc/extend.texi: (__extension__): Remove comments about scope
2382 tokens vs. two colons.
2384 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
2386 PR tree-optimization/109804
2387 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2388 DEMANGLE_COMPONENT_UNNAMED_TYPE.
2390 2024-02-22 Richard Biener <rguenther@suse.de>
2392 PR tree-optimization/114048
2393 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2394 can also produce -1 off.
2396 2024-02-22 Richard Biener <rguenther@suse.de>
2398 PR tree-optimization/114027
2399 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2400 condition reduction classification only for single-element
2401 chains.
2403 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2405 PR ipa/111960
2406 * profile-count.h (profile_count::dump): Remove overload with
2407 char * first argument.
2408 * profile-count.cc (profile_count::dump): Change overload with char *
2409 first argument which uses sprintf into the overfload with FILE *
2410 first argument and use fprintf instead. Remove overload which wrapped
2411 it.
2413 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2415 PR tree-optimization/113993
2416 * tree-call-cdce.cc (get_no_error_domain): Handle
2417 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
2418 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2419 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2420 the as the F128 suffixed cases, otherwise as non-suffixed ones.
2421 Handle BUILT_IN_{EXP,POW}10L for
2422 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2423 as (-inf, 4932).
2425 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2427 PR tree-optimization/114038
2428 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2429 loop exit condition if end is divisible by limb_prec.
2431 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
2433 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2434 problem of mabi=, mno-flush-func, mexplicit-relocs;
2435 add missing leading - of mbranch-cost option.
2436 * config/mips/mips.opt.urls: Regenerate.
2438 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
2440 PR target/109987
2441 * config/rs6000/constraints.md (we): Update internal doc without
2442 referring to option -mpower9-vector.
2443 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2444 special handlings.
2445 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2446 OTHER_P8_VECTOR_MASKS): Merge to ...
2447 (OTHER_VSX_VECTOR_MASKS): ... here.
2448 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2449 some error message handlings and explicit option mask adjustments on
2450 explicit option power{8,9}-vector conflicting with other options.
2451 (rs6000_print_isa_options): Update comments.
2452 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2453 related array items and handlings.
2454 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2455 special handlings.
2456 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2457 WarnRemoved.
2458 * doc/extend.texi: Remove documentation referring to option
2459 -mpower8-vector.
2460 * doc/invoke.texi: Remove documentation for option
2461 -mpower{8,9}-vector and adjust some documentation referring to them.
2462 * doc/md.texi: Update documentation for constraint we.
2463 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2465 2024-02-22 Pan Li <pan2.li@intel.com>
2467 PR target/114017
2468 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2469 the version to 0.12.
2471 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2473 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2475 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2476 Robin Dapp <rdapp.gcc@gmail.com>
2478 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2479 (generic_ooo_vec_load): Ditto
2480 (generic_ooo_vec_store): Ditto
2481 (generic_ooo_vec_loadstore_seg): Ditto
2482 (generic_ooo_vec_alu): Ditto
2483 (generic_ooo_vec_fcmp): Ditto
2484 (generic_ooo_vec_imul): Ditto
2485 (generic_ooo_vec_fadd): Ditto
2486 (generic_ooo_vec_fmul): Ditto
2487 (generic_ooo_crypto): Ditto
2488 (generic_ooo_perm): Ditto
2489 (generic_ooo_vec_reduction): Ditto
2490 (generic_ooo_vec_ordered_reduction): Ditto
2491 (generic_ooo_vec_idiv): Ditto
2492 (generic_ooo_vec_float_divsqrt): Ditto
2493 (generic_ooo_vec_mask): Ditto
2494 (generic_ooo_vec_vesetvl): Ditto
2495 (generic_ooo_vec_setrm): Ditto
2496 (generic_ooo_vec_readlen): Ditto
2497 * config/riscv/riscv.md: Include generic-vector-ooo
2498 * config/riscv/generic-vector-ooo.md: New file. To here
2500 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2502 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2503 (generic_ooo_branch): Ditto
2504 * config/riscv/generic.md (generic_sfb_alu): Ditto
2505 (generic_fmul_half): Ditto
2506 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2507 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2508 (sifive_7_popcount): Ditto
2509 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2510 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2511 * config/riscv/vector.md: Change rdfrm to fmove
2512 * config/riscv/zc.md: Change pushpop to load/store
2514 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
2516 * doc/invoke.texi (Warning Options): Fix typos.
2518 2024-02-21 David Faust <david.faust@oracle.com>
2520 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2521 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2522 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2524 2024-02-21 Martin Jambor <mjambor@suse.cz>
2526 PR ipa/113476
2527 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2528 initializers in the contructor.
2529 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2530 * ipa-cp.h: New file.
2531 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2532 (ipcp_value_source): Move to ipa-cp.h.
2533 (ipcp_value_base): Likewise.
2534 (ipcp_value): Likewise.
2535 (ipcp_lattice): Likewise.
2536 (ipcp_agg_lattice): Likewise.
2537 (ipcp_bits_lattice): Likewise.
2538 (ipcp_vr_lattice): Likewise.
2539 (ipcp_param_lattices): Likewise.
2540 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2541 (ipa_value_from_jfunc): Adjust a check for empty lattices.
2542 (ipa_context_from_jfunc): Likewise.
2543 (ipa_agg_value_from_jfunc): Likewise.
2544 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2545 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2546 just in contiguous memory.
2547 (ipcp_store_vr_results): Adjust a check for empty lattices.
2548 * auto-profile.cc: Include sreal.h and ipa-cp.h.
2549 * cgraph.cc: Likewise.
2550 * cgraphclones.cc: Likewise.
2551 * cgraphunit.cc: Likewise.
2552 * config/aarch64/aarch64.cc: Likewise.
2553 * config/i386/i386-builtins.cc: Likewise.
2554 * config/i386/i386-expand.cc: Likewise.
2555 * config/i386/i386-features.cc: Likewise.
2556 * config/i386/i386-options.cc: Likewise.
2557 * config/i386/i386.cc: Likewise.
2558 * config/rs6000/rs6000.cc: Likewise.
2559 * config/s390/s390.cc: Likewise.
2560 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2561 files to be included in gtype-desc.cc.
2562 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2563 * ipa-devirt.cc: Likewise.
2564 * ipa-fnsummary.cc: Likewise.
2565 * ipa-icf.cc: Likewise.
2566 * ipa-inline-analysis.cc: Likewise.
2567 * ipa-inline-transform.cc: Likewise.
2568 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2569 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2570 * ipa-param-manipulation.cc: Likewise.
2571 * ipa-predicate.cc: Likewise.
2572 * ipa-profile.cc: Likewise.
2573 * ipa-prop.cc: Likewise.
2574 (ipa_node_params_t::duplicate): Assert new lattices remain empty
2575 instead of setting them to NULL.
2576 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2577 * ipa-split.cc: Likewise.
2578 * ipa-sra.cc: Likewise.
2579 * ipa-strub.cc: Likewise.
2580 * ipa-utils.cc: Likewise.
2581 * ipa.cc: Likewise.
2582 * toplev.cc: Likewise.
2583 * tree-ssa-ccp.cc: Likewise.
2584 * tree-ssa-sccvn.cc: Likewise.
2585 * tree-vrp.cc: Likewise.
2587 2024-02-21 Tamar Christina <tamar.christina@arm.com>
2589 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2590 Armv8.7-a.
2592 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2594 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2595 Use aarch64_gen_compare_zero_and_branch rather than emitting
2596 a CBZ directly.
2598 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2600 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2601 Remove duplicated call.
2603 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2605 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2606 Check that each individual piece of state is shared in the same
2607 way, rather than using an aggregate check for PSTATE.ZA.
2609 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2611 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2612 In the code that commits a lazy save, only zero ZA if the function
2613 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
2615 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2617 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2618 directly inserting the associated sequence
2619 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2620 ...here instead.
2622 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2624 PR target/113995
2625 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2626 fold the SVE allocation into the initial allocation if the
2627 initial allocation includes a VG save.
2629 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2631 PR target/113220
2632 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2633 contain jumps even if called after initial RTL expansion.
2634 * mode-switching.cc: Include cfgbuild.h.
2635 (optimize_mode_switching): Allow the sequence returned by the
2636 emit hook to contain internal jumps. Record which blocks
2637 contain such jumps and split the blocks at the end.
2638 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2639 non-debug insns when scanning the sequence.
2641 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
2643 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2644 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2646 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2648 * doc/invoke.texi (-mmcu): Add information about MCU specs.
2650 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2652 * doc/invoke.texi (-minrt): Clarify that main
2653 must take no arguments.
2655 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2657 * config/avr/builtins.def: Use function prototypes of given size
2658 and signedness.
2659 * config/avr/avr.cc (avr_init_builtins): Adjust types required
2660 by builtins.def.
2661 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2663 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2665 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2666 instead of @table.
2668 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
2670 * config/bpf/bpf.opt: Add help information for -mcpu.
2672 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
2674 PR target/113805
2675 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2676 New pass.
2677 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2678 Declare.
2679 * config/aarch64/aarch64.md (is_call): New attribute.
2680 (*and<mode>3nr_compare0): Rename to...
2681 (@aarch64_and<mode>3nr_compare0): ...this.
2682 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2683 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2684 * config/aarch64/aarch64-speculation.cc: Update file comment to
2685 describe the new late pass.
2686 (aarch64_do_track_speculation): Handle is_call insns like other calls.
2687 (pass_track_speculation): Add an is_late member variable.
2688 (pass_track_speculation::gate): Run the late pass for streaming-
2689 compatible functions and the early pass for other functions.
2690 (make_pass_track_speculation): Update accordingly.
2691 (make_pass_late_track_speculation): New function.
2692 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2693 function.
2694 (aarch64_guard_switch_pstate_sm): Use it.
2696 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
2698 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2699 Register these builtins with a pointer to uint64_t rather than unsigned
2700 DI mode.
2702 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2704 PR target/113615
2705 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2706 Conditionalize on '!TARGET_RDNA2_PLUS'.
2707 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2708 (gcn_expand_reduc_scalar):
2709 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2711 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2713 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2714 '__gfx90a__' target CPU definition. Add some safeguards for the future.
2716 2024-02-19 Richard Biener <rguenther@suse.de>
2718 PR rtl-optimization/54052
2719 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2720 local defs by LR_OUT.
2722 2024-02-19 Jakub Jelinek <jakub@redhat.com>
2724 PR tree-optimization/113967
2725 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2726 in condition that @rpos is multiple of vector element size.
2728 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2730 PR target/113696
2731 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2732 Suppress vsetvl fusion.
2734 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
2736 PR target/113912
2737 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2738 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2739 (ix86_emit_save_regs): Don't generate push2 if
2740 ix86_can_use_push2pop2 return false.
2741 (ix86_expand_epilogue): Don't generate pop2 if
2742 ix86_can_use_push2pop2 return false.
2744 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2746 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2747 Note on complete device support.
2749 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2751 * doc/extend.texi (AVR Function Attributes): Fuse description
2752 of "signal" and "interrupt" attribute. Link pseudo instruction.
2754 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2756 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
2757 symbol type conversions.
2758 (__cacop_d): Likewise.
2759 (__cpucfg): Likewise.
2760 (__asrtle_d): Likewise.
2761 (__asrtgt_d): Likewise.
2762 (__lddir_d): Likewise.
2763 (__ldpte_d): Likewise.
2764 (__crc_w_b_w): Likewise.
2765 (__crc_w_h_w): Likewise.
2766 (__crc_w_w_w): Likewise.
2767 (__crc_w_d_w): Likewise.
2768 (__crcc_w_b_w): Likewise.
2769 (__crcc_w_h_w): Likewise.
2770 (__crcc_w_w_w): Likewise.
2771 (__crcc_w_d_w): Likewise.
2772 (__csrrd_w): Likewise.
2773 (__csrwr_w): Likewise.
2774 (__csrxchg_w): Likewise.
2775 (__csrrd_d): Likewise.
2776 (__csrwr_d): Likewise.
2777 (__csrxchg_d): Likewise.
2778 (__iocsrrd_b): Likewise.
2779 (__iocsrrd_h): Likewise.
2780 (__iocsrrd_w): Likewise.
2781 (__iocsrrd_d): Likewise.
2782 (__iocsrwr_b): Likewise.
2783 (__iocsrwr_h): Likewise.
2784 (__iocsrwr_w): Likewise.
2785 (__iocsrwr_d): Likewise.
2786 (__frecipe_s): Likewise.
2787 (__frecipe_d): Likewise.
2788 (__frsqrte_s): Likewise.
2789 (__frsqrte_d): Likewise.
2791 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2793 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2794 function return value type to unsigned short.
2796 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
2798 * doc/sourcebuild.texi: add scan-assembler-bound
2800 2024-02-16 Jason Merrill <jason@redhat.com>
2802 * gdbhooks.py: Fix regex syntax.
2804 2024-02-16 Richard Biener <rguenther@suse.de>
2806 PR tree-optimization/113895
2807 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2808 consistency checking when there are out-of-bound array
2809 accesses. Allow -1 off when from an array reference with
2810 constant index.
2812 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2814 PR target/106543
2815 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2816 pattern.
2818 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2820 * doc/sourcebuild.texi (Effective-Target Keywords, Other
2821 attribugs): Document linker_plugin.
2822 (Require Support): Document dg-require-linker-plugin.
2824 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2826 PR target/109349
2827 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
2828 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
2829 (RISCV_MINOR_VERSION_BASE): Ditto.
2830 (RISCV_REVISION_VERSION_BASE): Ditto.
2831 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
2832 rather than magic number.
2833 * config/riscv/riscv.h (riscv_arch_help): New.
2834 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
2835 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
2836 --print-supported-extensions.
2837 * config/riscv/riscv.opt (march=help): New.
2838 (print-supported-extensions): New.
2839 (-print-supported-extensions): New.
2840 * doc/invoke.texi (RISC-V Options): Document -march=help.
2842 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
2844 PR target/113780
2845 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
2846 for indirect calls with 4 or more arguments in pac-enabled functions.
2848 2024-02-15 David Faust <david.faust@oracle.com>
2850 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
2851 use ldxb instead of ldxh.
2853 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2855 PR middle-end/113921
2856 * cfgrtl.h (prepend_insn_to_edge): New declaration.
2857 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
2858 comment.
2859 (prepend_insn_to_edge): New function.
2860 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
2861 insert_insn_on_edge.
2863 2024-02-15 Richard Biener <rguenther@suse.de>
2865 PR tree-optimization/111156
2866 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
2867 at the pattern stmt if any.
2869 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
2871 PR target/113927
2872 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
2873 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
2874 * config/avr/avr.cc (avr_adiw_reg_p): New function.
2875 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
2876 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
2877 * config/avr/avr.md: Same.
2878 (attr "isa") <tiny, no_tiny>: Remove.
2879 <adiw, no_adiw>: Add.
2880 (define_insn, define_insn_and_split): When an alternative has
2881 constraint "w", then set attribute "isa" to "adiw".
2882 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
2883 Built-in define __AVR_HAVE_ADIW__.
2884 * doc/invoke.texi (AVR Options): Document it.
2886 2024-02-15 Andrew Stubbs <ams@baylibre.com>
2888 * config/gcn/gcn-valu.md
2889 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
2890 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
2891 details are supported on RDNA devices.
2893 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2895 PR middle-end/113508
2896 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
2897 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
2898 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
2899 Add sentence about what the mode m is.
2901 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2903 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
2904 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
2905 var.
2907 2024-02-15 Richard Biener <rguenther@suse.de>
2909 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
2910 stmts.
2912 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2914 PR tree-optimization/113567
2915 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
2916 _BitInt multiplication, division or modulo with
2917 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
2918 force the affected inputs into a new SSA_NAME.
2920 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
2922 PR target/113871
2923 * config/i386/mmx.md (V248FI): New mode iterator.
2924 (V24FI_32): DItto.
2925 (vec_shl_<V248FI:mode>): New expander.
2926 (vec_shl_<V24FI_32:mode>): Ditto.
2927 (vec_shr_<V248FI:mode>): Ditto.
2928 (vec_shr_<V24FI_32:mode>): Ditto.
2929 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
2930 (vec_shr_<V248FI:mode>): Ditto.
2932 2024-02-14 Jan Hubicka <jh@suse.cz>
2934 PR tree-optimization/111054
2935 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
2937 2024-02-14 Tamar Christina <tamar.christina@arm.com>
2939 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
2941 2024-02-14 Richard Biener <rguenther@suse.de>
2943 PR tree-optimization/113910
2944 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
2945 the hashval_t hash.
2947 2024-02-14 Jakub Jelinek <jakub@redhat.com>
2949 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
2950 (pp_integer_with_precision): For unsigned ptrdiff_t printing
2951 with u, o or x print ptrdiff_t argument converted to
2952 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
2954 2024-02-14 Richard Biener <rguenther@suse.de>
2956 PR middle-end/113576
2957 * expr.cc (do_store_flag): For vector bool compares of vectors
2958 with padding zero that.
2959 * dojump.cc (do_compare_and_jump): Likewise.
2961 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
2963 * doc/install.texi (Prerequisites): Update gettext link.
2965 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
2967 PR target/113876
2968 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
2969 Return false if the incoming stack isn't 16-byte aligned.
2971 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
2973 PR middle-end/113904
2974 * omp-general.cc (struct omp_ts_info): Update for splitting of
2975 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2976 * omp-selectors.h (enum omp_tp_type): Replace
2977 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2979 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
2981 PR target/113742
2982 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
2983 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
2985 2024-02-13 Richard Biener <rguenther@suse.de>
2987 PR tree-optimization/113895
2988 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
2989 offset to discover constant array indices in bits, handle
2990 COMPONENT_REF to bitfields.
2992 2024-02-13 Richard Biener <rguenther@suse.de>
2994 PR tree-optimization/113831
2995 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
2996 typo in comment.
2998 2024-02-13 Richard Biener <rguenther@suse.de>
3000 PR tree-optimization/113902
3001 * tree-vect-loop.cc (move_early_exit_stmts): Track
3002 last_seen_vuse for VUSE updating.
3004 2024-02-13 Tamar Christina <tamar.christina@arm.com>
3006 PR tree-optimization/113734
3007 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
3008 an early break loop as partial.
3010 2024-02-13 Richard Biener <rguenther@suse.de>
3012 PR tree-optimization/113898
3013 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
3014 missing accumulated off adjustment.
3016 2024-02-13 Jakub Jelinek <jakub@redhat.com>
3018 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
3019 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
3020 it against UINT_MAX and ULONG_MAX.
3022 2024-02-13 David Malcolm <dmalcolm@redhat.com>
3024 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
3025 to...
3026 (emit_diagnostic_valist_meta): ...this.
3027 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
3028 (emit_diagnostic_valist_meta): ...this.
3030 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3032 PR tree-optimization/113849
3033 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
3034 fast path for widening casts where !m_upwards_2limb and lhs_type
3035 has precision which is a multiple of limb_prec.
3037 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3039 PR c++/113674
3040 * attribs.cc (extract_attribute_substring): Remove.
3041 (lookup_scoped_attribute_spec): Don't call it.
3043 2024-02-12 Jakub Jelinek <jakub@redhat.com>
3045 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
3046 and cast to fmt_size_t instead of %lu and cast to unsigned long.
3048 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
3050 * Makefile.in: Add no-info dependency.
3051 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
3052 available.
3053 * configure: Regenerate.
3055 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
3057 PR target/113855
3058 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
3059 available to all sub-targets.
3060 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
3061 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
3063 2024-02-12 Richard Biener <rguenther@suse.de>
3065 PR tree-optimization/113831
3066 PR tree-optimization/108355
3067 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
3068 we see variable array indices and get_ref_base_and_extent
3069 can resolve those to constants fix up the ops to constants
3070 as well.
3071 (ao_ref_init_from_vn_reference): Use 'off' member for
3072 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
3073 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
3075 2024-02-12 Pan Li <pan2.li@intel.com>
3077 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
3078 Replace args to arguments for misspelled term.
3080 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
3082 PR target/112944
3083 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
3084 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
3085 when not linked with -mrodata-in-ram.
3087 2024-02-12 Richard Biener <rguenther@suse.de>
3089 PR tree-optimization/113863
3090 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3091 Record crossed virtual PHIs.
3092 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
3093 virtual PHIs.
3095 2024-02-10 Marek Polacek <polacek@redhat.com>
3097 DR 2237
3098 PR c++/107126
3099 PR c++/97202
3100 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
3102 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3104 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
3105 computation of idx for i == 4 of bitint_prec_huge.
3107 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3109 PR middle-end/110754
3110 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
3111 decls create PARM_DECL with pointer to original type, set
3112 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
3113 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
3114 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
3115 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
3116 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
3117 of the var as argument.
3119 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3121 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
3122 size_t and precision 4 for ptrdiff_t. Formatting fix.
3123 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
3124 Formatting fixes.
3125 (test_pp_format): Test t and z modifiers.
3126 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
3128 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3130 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
3131 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
3132 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3133 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
3134 and casts to fmt_size_t instead of "%ld" and casts to long.
3135 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
3136 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
3137 instead of "%lu" and casts to unsigned long.
3138 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
3139 unsigned long.
3140 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3141 and casts to fmt_size_t instead of "%ld" and casts to long.
3142 * cfgexpand.cc (dump_stack_var_partition): Use
3143 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
3144 and casts to unsigned long.
3145 * gengtype.cc (adjust_field_rtx_def): Likewise.
3146 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3147 and casts to fmt_size_t instead of "%ld" and casts to long.
3148 * postreload-gcse.cc (dump_hash_table): Likewise.
3149 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
3150 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3151 (ggc_internal_alloc, ggc_free): Likewise.
3152 * genpreds.cc (write_lookup_constraint_1): Likewise.
3153 (write_insn_constraint_len): Likewise.
3154 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
3155 and casts to fmt_size_t instead of "%ld" and casts to long.
3156 * varasm.cc (output_constant_pool_contents): Use
3157 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
3158 * var-tracking.cc (dump_var): Likewise.
3160 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3162 PR tree-optimization/113783
3163 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
3164 through VIEW_CONVERT_EXPR for final cast checks. Handle
3165 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
3166 INTEGER_TYPEs.
3167 (gimple_lower_bitint): Don't merge mergeable operations or other
3168 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
3169 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
3170 mode is BLKmode.
3172 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3174 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
3175 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
3176 HOST_SIZE_T_PRINT_HEX_PURE): Define.
3177 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
3178 fixes.
3180 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3182 PR middle-end/113415
3183 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
3184 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
3185 of hand written loop with emit_insn of copy_insn and emit original
3186 after_rtl_seq on the last edge.
3188 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3190 PR tree-optimization/113818
3191 * gimple-lower-bitint.cc (add_eh_edge): New function.
3192 (bitint_large_huge::handle_load,
3193 bitint_large_huge::lower_mergeable_stmt,
3194 bitint_large_huge::lower_muldiv_stmt): Use it.
3196 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3198 PR tree-optimization/113774
3199 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
3200 emit any comparison if m_first and low + 1 is equal to
3201 m_upwards_2limb, simplify condition for that. If not
3202 single_comparison, not m_first and we can prove that the idx <= low
3203 comparison will be always true, emit instead of idx <= low
3204 comparison low <= low such that cfg cleanup will optimize it at
3205 the end of the pass.
3207 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
3209 PR tree-optimization/113735
3210 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
3211 limit_check().
3213 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3215 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
3216 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
3218 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
3220 PR target/113711
3221 PR target/113733
3222 * config/i386/constraints.md: List all constraints with j prefix.
3223 (j>): Change auto-dec to auto-inc in documentation.
3224 (je): Changed to a memory constraint with APX NDD TLS operand
3225 check.
3226 (jM): New memory constraint for APX NDD instructions.
3227 (jO): Likewise.
3228 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
3229 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
3230 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
3231 (*add<mode>_1[SWI48]): Use je and jM.
3232 (addsi_1_zext): Use jM.
3233 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
3234 (*sub<mode>_1[SWI]): Use jM.
3235 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
3236 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
3237 (*and<dwi>3_doubleword): Likewise.
3238 (*anddi_1): Use jM.
3239 (*andsi_1_zext): Likewise.
3240 (*and<mode>_1[SWI24]): Likewise.
3241 (*<code><dwi>3_doubleword[any_or]): Use rjO
3242 (*code<mode>_1[any_or SWI248]): Use jM.
3243 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
3244 * config/i386/predicates.md (apx_ndd_memory_operand): New.
3245 (apx_ndd_add_memory_operand): Likewise.
3247 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3249 PR target/113824
3250 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
3251 * doc/avr-mmcu.texi: Rebuild.
3253 2024-02-08 Tamar Christina <tamar.christina@arm.com>
3255 PR tree-optimization/113808
3256 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
3257 value cross iterations.
3259 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3261 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
3262 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
3264 2024-02-08 Richard Biener <rguenther@suse.de>
3266 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3267 Revert last change to dr_may_alias_p.
3269 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3271 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
3272 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
3273 Remove spec asm_misc.
3274 * config/avr/specs.h: Same.
3276 2024-02-08 Pan Li <pan2.li@intel.com>
3278 PR target/113766
3279 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3280 sure the c.arg_num is >= 2 before checking.
3281 (struct build_frm_base): Ditto.
3282 (struct narrow_alu_def): Ditto.
3284 2024-02-07 Richard Biener <rguenther@suse.de>
3286 PR tree-optimization/113796
3287 * tree-if-conv.cc (combine_blocks): Wipe range-info before
3288 replacing PHIs and inserting predicates.
3290 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
3291 Uros Bizjak <ubizjak@gmail.com>
3293 PR target/113690
3294 * config/i386/i386-features.cc (timode_convert_cst): New helper
3295 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3296 CONST_VECTOR.
3297 (timode_scalar_chain::convert_op): Use timode_convert_cst.
3298 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3299 Use timode_convert_cst.
3301 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
3303 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3304 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3305 (AARCH64_FL_DEBUGv8p9): Likewise.
3306 (AARCH64_FL_FGT2): Likewise.Likewise.
3307 (AARCH64_FL_ITE): Likewise.
3308 (AARCH64_FL_PFAR): Likewise.
3309 (AARCH64_FL_PMUv3_ICNTR): Likewise.
3310 (AARCH64_FL_PMUv3_SS): Likewise.
3311 (AARCH64_FL_PMUv3p9): Likewise.
3312 (AARCH64_FL_RASv2): Likewise.
3313 (AARCH64_FL_S1PIE): Likewise.
3314 (AARCH64_FL_S1POE): Likewise.
3315 (AARCH64_FL_S2PIE): Likewise.
3316 (AARCH64_FL_S2POE): Likewise.
3317 (AARCH64_FL_SCTLR2): Likewise.
3318 (AARCH64_FL_SEBEP): Likewise.
3319 (AARCH64_FL_SPE_FDS): Likewise.
3320 (AARCH64_FL_TCR2): Likewise.
3322 2024-02-07 Richard Biener <rguenther@suse.de>
3324 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3325 Only check whether reads are in-bound in places that are not safe.
3326 Fix dependence check. Add missing newline. Clarify comments.
3328 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3330 PR tree-optimization/113750
3331 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3332 for single predecessor when doing early break vect.
3333 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3334 after labels.
3336 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3338 PR tree-optimization/113731
3339 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3340 method.
3341 * gimple-iterator.h (gsi_move_before): Default new param to
3342 GSI_SAME_STMT.
3343 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3344 GSI_NEW_STMT.
3346 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3348 PR tree-optimization/113756
3349 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3350 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3351 of lh_bits value and mask.
3353 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3355 PR tree-optimization/113753
3356 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3357 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
3358 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3359 so that they start with r[half_blocks_needed] lowest bit. Fix up
3360 computation of top mask for SIGNED.
3362 2024-02-07 Pan Li <pan2.li@intel.com>
3364 PR target/113766
3365 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3366 the signature of func.
3367 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3368 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3369 overloaded func with empty args error.
3371 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
3373 PR target/113689
3374 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3375 R10_REG after sorry.
3377 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
3379 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3380 Move before new caller, and add ".default" suffix.
3381 (get_suffixed_assembler_name): New.
3382 (make_resolver_func): Use get_suffixed_assembler_name.
3383 (aarch64_generate_version_dispatcher_body): Redo name mangling.
3385 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3387 PR target/113763
3388 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3389 element from std::pair<unsigned int, char> to an unnamed struct.
3390 Adjust uses of tile range variable.
3392 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3394 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3395 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3397 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3399 PR sanitizer/110676
3400 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3401 reset maxlen to sizetype maximum.
3403 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3405 PR tree-optimization/113736
3406 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3407 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3409 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3411 PR tree-optimization/113759
3412 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3413 or from_unsignedN differs from properties of typeN, update typeN
3414 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
3415 uselessly convertible to typeN, convert it using fold_convert or
3416 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3417 (convert_plusminus_to_widen): Likewise.
3419 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
3421 PR target/112577
3422 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3423 vector structure modes correctly.
3425 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
3427 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3428 warning.
3430 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
3432 PR target/113689
3433 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3434 (x86_function_profiler): Call x86_64_select_profile_regnum to
3435 get a scratch register for large model profiling.
3437 2024-02-05 Richard Ball <richard.ball@arm.com>
3439 * config/arm/arm.cc (arm_output_mi_thunk): Emit
3440 insn for bti_c when bti is enabled.
3442 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3444 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3445 neg.
3447 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3449 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3450 (neg<mode>2): Change the mode iterator from MSA to IMSA because
3451 in FP arithmetic we cannot use (0 - x) for -x.
3452 (neg<mode>2): New define_insn to implement FP vector negation,
3453 using a bnegi instruction to negate the sign bit.
3455 2024-02-05 Richard Biener <rguenther@suse.de>
3457 PR tree-optimization/113707
3458 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3459 checking the avail set treat out-of-region defines as
3460 available.
3462 2024-02-05 Richard Biener <rguenther@suse.de>
3464 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3465 the default mode when building a pointer.
3467 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3469 PR tree-optimization/113737
3470 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3471 has just a single label, remove it and make single successor edge
3472 EDGE_FALLTHRU.
3474 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3476 PR target/113059
3477 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3478 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3479 df_analyze call.
3481 2024-02-05 Richard Biener <rguenther@suse.de>
3483 PR target/113255
3484 * config/i386/i386-expand.cc
3485 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3486 Use a new pseudo for the skipped number of bytes.
3488 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3490 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3491 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3492 sifive-p670.
3494 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3496 * config/riscv/riscv.md: Include sifive-p400.md.
3497 * config/riscv/sifive-p400.md: New file.
3498 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3499 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3500 Add sifive_p400.
3501 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3502 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3503 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3505 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3507 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3508 Add missing ":SI" to the match_operator.
3510 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3512 * config/xtensa/xtensa.md (SHI): New mode iterator.
3513 (2 split patterns related to constsynth):
3514 Change to also accept HImode operands.
3516 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
3518 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3519 similarly.
3521 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3523 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3524 incorrect expand.
3525 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3526 (elmsgnbit): Likewise.
3527 (neg<mode:FVEC>2): New define_insn.
3528 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3529 are now instantiated in simd.md.
3531 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3533 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3534 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3535 MAX_MACHINE_MODE.
3537 2024-02-04 Li Wei <liwei@loongson.cn>
3539 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3540 (loongarch_expand_vselect_vconcat): Ditto.
3541 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3542 all 128-bit constant permutation situations.
3543 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3544 (loongarch_is_imm_set_shuffle): Renamed function name.
3545 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3546 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3547 extract-even and extract-odd permutations.
3548 (loongarch_is_odd_extraction): Delete.
3549 (loongarch_is_even_extraction): Ditto.
3550 (loongarch_expand_vec_perm_const): Adjust.
3552 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3554 PR middle-end/113722
3555 * wide-int.cc (wi::bswap_large): Rename third argument from
3556 len to xlen and adjust use in safe_uhwi. Add len variable, set
3557 it to BLOCKS_NEEDED (precision) and use it for clearing of val
3558 and as canonize argument. Clear val using memset instead of
3559 a loop.
3561 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3563 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3564 mmi.preferred_base + mmi.size - sizeof (void *).
3566 2024-02-03 Xi Ruoyao <xry111@xry111.site>
3568 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3569 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3570 the ODR-violating locale declaration.
3572 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3574 PR tree-optimization/113588
3575 PR tree-optimization/113467
3576 * tree-vect-data-refs.cc
3577 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
3578 (vect_analyze_early_break_dependences): Update comments.
3580 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
3582 PR target/59778
3583 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3584 and PA_BUILTIN_SET_FPSR builtins.
3585 * (pa_builtins_icode): Declare.
3586 * (def_builtin, pa_fpu_init_builtins): New.
3587 * (pa_init_builtins): Initialize FPU builtins.
3588 * (pa_builtin_decl, pa_expand_builtin_1): New.
3589 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3590 PA_BUILTIN_SET_FPSR builtins.
3591 * (pa_atomic_assign_expand_fenv): New.
3592 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3593 UNSPECV constants.
3594 (get_fpsr, put_fpsr): New expanders.
3595 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3596 insn patterns.
3598 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3600 PR target/113697
3601 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3603 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
3605 * doc/extend.texi (Common Type Attributes): Fix typo in
3606 description of hardbool.
3608 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3610 PR tree-optimization/113692
3611 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3612 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3613 final_cast_p.
3615 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3617 PR middle-end/113699
3618 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3619 uninitialized large/huge _BitInt SSA_NAME inputs.
3621 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3623 PR middle-end/113705
3624 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3625 around wi::to_wide in order to compare value in prec precision.
3627 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
3629 Revert:
3630 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3632 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3634 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3636 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3638 2024-02-02 Pan Li <pan2.li@intel.com>
3640 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3641 (riscv_pass_by_reference): Ditto.
3642 (riscv_fntype_abi): Ditto.
3644 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3646 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3647 (pre_vsetvl::cleaup): Remove vsetvl_pre.
3648 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3650 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
3652 * config/loongarch/larchintrin.h
3653 (__frecipe_s): Update function return type.
3654 (__frecipe_d): Ditto.
3655 (__frsqrte_s): Ditto.
3656 (__frsqrte_d): Ditto.
3658 2024-02-02 Li Wei <liwei@loongson.cn>
3660 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3661 (loongarch_vector_costs::add_stmt_cost): Adjust.
3663 2024-02-02 Xi Ruoyao <xry111@xry111.site>
3665 * config/loongarch/loongarch.md (unspec): Add
3666 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3667 (la_pcrel64_two_parts): New define_insn.
3668 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3669 typo in the comment.
3670 (loongarch_call_tls_get_addr): If -mcmodel=extreme
3671 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3672 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
3673 note to allow CSE addressing __tls_get_addr.
3674 (loongarch_legitimize_tls_address): If -mcmodel=extreme
3675 -mexplicit-relocs={always,auto}, address TLS IE symbols with
3676 la_pcrel64_two_parts.
3677 (loongarch_split_symbol): If -mcmodel=extreme
3678 -mexplicit-relocs={always,auto}, address symbols with
3679 la_pcrel64_two_parts.
3680 (loongarch_output_mi_thunk): Clean up unreachable code. If
3681 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3682 thunks with la_pcrel64_two_parts.
3684 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3686 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3687 Add support for call36.
3689 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3691 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3692 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3693 the macro instruction loading symbol address is not applicable.
3694 (loongarch_call_tls_get_addr): Adjust code.
3695 (loongarch_legitimize_tls_address): Likewise.
3697 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3699 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3700 Add function declaration.
3701 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3702 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3703 is not allowed
3704 (loongarch_load_tls): Added macro support in extreme mode.
3705 (loongarch_call_tls_get_addr): Likewise.
3706 (loongarch_legitimize_tls_address): Likewise.
3707 (loongarch_force_address): Likewise.
3708 (loongarch_legitimize_move): Likewise.
3709 (loongarch_output_mi_thunk): Likewise.
3710 (loongarch_option_override_internal): Remove the code that detects
3711 explicit relocs status.
3712 (loongarch_handle_model_attribute): Likewise.
3713 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3714 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3715 (symbolic_off64_or_reg_operand): Likewise.
3717 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3719 * config/loongarch/loongarch.cc (loongarch_load_tls):
3720 Load all types of tls symbols through one function.
3721 (loongarch_got_load_tls_gd): Delete.
3722 (loongarch_got_load_tls_ld): Delete.
3723 (loongarch_got_load_tls_ie): Delete.
3724 (loongarch_got_load_tls_le): Delete.
3725 (loongarch_call_tls_get_addr): Modify the called function name.
3726 (loongarch_legitimize_tls_address): Likewise.
3727 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3728 (@load_tls<mode>): New template.
3729 (@got_load_tls_ld<mode>): Delete.
3730 (@got_load_tls_le<mode>): Delete.
3731 (@got_load_tls_ie<mode>): Delete.
3733 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3735 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3736 (loongarch_legitimize_address): Add logical transformation code.
3738 2024-02-01 Marek Polacek <polacek@redhat.com>
3740 * doc/invoke.texi: Update -Wdangling-reference documentation.
3742 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
3744 PR target/113701
3745 * config/i386/i386.md (*cmp<dwi>_doubleword):
3746 Do not force SUBREG pieces to pseudos.
3748 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
3750 * config/pa/pa.md (atomic_storedi_1): Fix bug in
3751 alternative 1.
3753 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
3755 * config/avr/avr.cc: Tabify.
3757 2024-02-01 Richard Ball <richard.ball@arm.com>
3759 PR tree-optimization/111268
3760 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
3761 Add variable-length check for vector input arguments
3762 to a function.
3764 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3766 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
3767 hard-code number of SGPR/VGPR/AVGPR registers.
3768 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
3769 SGPR/VGPR/AVGPR registers.
3771 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3773 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
3774 attribute, and include sifive-p600.md.
3775 * config/riscv/generic-ooo.md: Update type attribute.
3776 * config/riscv/generic.md: Update type attribute.
3777 * config/riscv/sifive-7.md: Update type attribute.
3778 * config/riscv/sifive-p600.md: New file.
3779 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3780 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3781 Add sifive_p600.
3782 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3783 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3784 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3786 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3788 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3789 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3790 * config/riscv/riscv.opt: New macro for 7 new unprivileged
3791 extensions.
3792 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3793 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3795 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3797 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3798 -static-libasan. Add missing whitespace.
3800 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3802 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3803 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3804 Don't 'define_constants'.
3806 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3808 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3810 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3812 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3813 [TARGET_RDNA3]: Adjust.
3815 2024-02-01 Richard Biener <rguenther@suse.de>
3817 PR tree-optimization/113693
3818 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3819 data when available.
3821 2024-02-01 Jakub Jelinek <jakub@redhat.com>
3822 Jason Merrill <jason@redhat.com>
3824 PR c++/113531
3825 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
3826 on variables which were promoted to TREE_STATIC.
3828 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
3829 Richard Biener <rguenther@suse.de>
3831 PR target/113560
3832 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
3833 information via tree_non_zero_bits to check if this operand
3834 is suitably extended for a widening (or highpart) multiplication.
3835 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
3836 isn't already of the claimed type.
3838 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3840 Revert:
3841 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3843 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3844 (generic_ooo_branch): ditto
3845 * config/riscv/generic.md (generic_sfb_alu): ditto
3846 (generic_fmul_half): ditto
3847 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3848 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3849 (sifive_7_popcount): ditto
3850 * config/riscv/vector.md: change rdfrm to fmove
3851 * config/riscv/zc.md: change pushpop to load/store
3853 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3855 Revert:
3856 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3857 Robin Dapp <rdapp.gcc@gmail.com>
3859 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3860 (generic_ooo_vec_load): ditto
3861 (generic_ooo_vec_store): ditto
3862 (generic_ooo_vec_loadstore_seg): ditto
3863 (generic_ooo_vec_alu): ditto
3864 (generic_ooo_vec_fcmp): ditto
3865 (generic_ooo_vec_imul): ditto
3866 (generic_ooo_vec_fadd): ditto
3867 (generic_ooo_vec_fmul): ditto
3868 (generic_ooo_crypto): ditto
3869 (generic_ooo_perm): ditto
3870 (generic_ooo_vec_reduction): ditto
3871 (generic_ooo_vec_ordered_reduction): ditto
3872 (generic_ooo_vec_idiv): ditto
3873 (generic_ooo_vec_float_divsqrt): ditto
3874 (generic_ooo_vec_mask): ditto
3875 (generic_ooo_vec_vesetvl): ditto
3876 (generic_ooo_vec_setrm): ditto
3877 (generic_ooo_vec_readlen): ditto
3878 * config/riscv/riscv.md: include generic-vector-ooo
3879 * config/riscv/generic-vector-ooo.md: New file. to here
3881 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3883 Revert:
3884 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3886 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3888 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3890 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3892 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3893 Robin Dapp <rdapp.gcc@gmail.com>
3895 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3896 (generic_ooo_vec_load): ditto
3897 (generic_ooo_vec_store): ditto
3898 (generic_ooo_vec_loadstore_seg): ditto
3899 (generic_ooo_vec_alu): ditto
3900 (generic_ooo_vec_fcmp): ditto
3901 (generic_ooo_vec_imul): ditto
3902 (generic_ooo_vec_fadd): ditto
3903 (generic_ooo_vec_fmul): ditto
3904 (generic_ooo_crypto): ditto
3905 (generic_ooo_perm): ditto
3906 (generic_ooo_vec_reduction): ditto
3907 (generic_ooo_vec_ordered_reduction): ditto
3908 (generic_ooo_vec_idiv): ditto
3909 (generic_ooo_vec_float_divsqrt): ditto
3910 (generic_ooo_vec_mask): ditto
3911 (generic_ooo_vec_vesetvl): ditto
3912 (generic_ooo_vec_setrm): ditto
3913 (generic_ooo_vec_readlen): ditto
3914 * config/riscv/riscv.md: include generic-vector-ooo
3915 * config/riscv/generic-vector-ooo.md: New file. to here
3917 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3919 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3920 (generic_ooo_branch): ditto
3921 * config/riscv/generic.md (generic_sfb_alu): ditto
3922 (generic_fmul_half): ditto
3923 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3924 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3925 (sifive_7_popcount): ditto
3926 * config/riscv/vector.md: change rdfrm to fmove
3927 * config/riscv/zc.md: change pushpop to load/store
3929 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
3931 PR target/113657
3932 * config/aarch64/aarch64-simd.md (split for movv8di):
3933 For strict aligned mode, use DImode instead of TImode.
3935 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
3937 PR middle-end/113607
3938 * match.pd: Make sure else values match when folding a
3939 vec_cond into a conditional operation.
3941 2024-01-31 Marek Polacek <polacek@redhat.com>
3943 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
3945 2024-01-31 Tamar Christina <tamar.christina@arm.com>
3946 Matthew Malcomson <matthew.malcomson@arm.com>
3948 PR sanitizer/112644
3949 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
3950 memcmp.
3951 * builtins.cc (expand_builtin): Include HWASAN when checking for
3952 builtin inlining.
3954 2024-01-31 Richard Biener <rguenther@suse.de>
3956 PR middle-end/110176
3957 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
3958 to match INTEGER_CST only without outstanding conversion.
3960 2024-01-31 Alex Coplan <alex.coplan@arm.com>
3962 PR target/111677
3963 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
3964 V16QImode for the full 16-byte FPR saves in the vector PCS case.
3966 2024-01-31 Richard Biener <rguenther@suse.de>
3968 PR tree-optimization/111444
3969 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
3970 vn_reference_lookup_2 when optimistically skipping may-defs.
3972 2024-01-31 Richard Biener <rguenther@suse.de>
3974 PR tree-optimization/113630
3975 * tree-ssa-pre.cc (compute_avail): Avoid registering a
3976 reference with a representation with not matching base
3977 access size.
3979 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3981 PR rtl-optimization/113656
3982 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
3983 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
3985 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3987 PR debug/113637
3988 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
3989 with BLKmode are larger than DWARF2_ADDR_SIZE.
3991 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3993 PR tree-optimization/113639
3994 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3995 For VIEW_CONVERT_EXPR set rhs1 to its operand.
3997 2024-01-31 Richard Biener <rguenther@suse.de>
3999 PR tree-optimization/113670
4000 * tree-vect-data-refs.cc (vect_check_gather_scatter):
4001 Make sure we can take the address of the reference base.
4003 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
4005 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
4006 ATA5835, ATtiny64AUTO, ATA5700M322.
4007 * doc/avr-mmcu.texi: Rebuild.
4009 2024-01-31 Alexandre Oliva <oliva@adacore.com>
4011 PR debug/113394
4012 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
4013 caller.
4015 2024-01-31 Alexandre Oliva <oliva@adacore.com>
4017 PR middle-end/112917
4018 PR middle-end/113100
4019 * builtins.cc (expand_builtin_stack_address): Use
4020 STACK_ADDRESS_OFFSET.
4021 * doc/extend.texi (__builtin_stack_address): Adjust.
4022 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
4023 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
4024 * doc/tm.texi: Rebuilt.
4026 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4028 PR target/113495
4029 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
4030 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
4031 (pre_vsetvl::compute_transparent): New function.
4032 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
4034 2024-01-30 Fangrui Song <maskray@google.com>
4036 PR target/105576
4037 * config/i386/constraints.md: Define constraint "Ws".
4038 * doc/md.texi: Document it.
4040 2024-01-30 Marek Polacek <polacek@redhat.com>
4042 PR c++/110358
4043 PR c++/109640
4044 * doc/invoke.texi: Update -Wdangling-reference description.
4046 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
4048 * config/xtensa/constraints.md (R, T, U):
4049 Change define_constraint to define_memory_constraint.
4050 * config/xtensa/predicates.md (move_operand): Don't check that a
4051 constant pool operand size is a multiple of UNITS_PER_WORD.
4052 * config/xtensa/xtensa.cc
4053 (xtensa_lra_p, TARGET_LRA_P): Remove.
4054 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
4055 clause as it can no longer be true.
4056 (fixup_subreg_mem): Drop function.
4057 (xtensa_output_integer_literal_parts): Consider 16-bit wide
4058 constants.
4059 (xtensa_legitimate_constant_p): Add short-circuit path for
4060 integer load instructions. Don't check that mode size is
4061 at least UNITS_PER_WORD.
4062 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
4063 rather reload_in_progress and reload_completed.
4064 (doloop_end): Drop operand 2.
4065 (movhi_internal): Add alternative loading constant from a
4066 literal pool.
4067 (define_split for DI register_operand): Don't limit to
4068 !TARGET_AUTO_LITPOOLS.
4069 * config/xtensa/xtensa.opt (mlra): Change to no effect.
4071 2024-01-30 Pan Li <pan2.li@intel.com>
4073 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
4074 calculate the gpr count required by vls mode.
4075 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
4076 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
4077 for vls mode.
4078 (riscv_get_arg_info): Add vls mode handling.
4079 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
4081 2024-01-30 Richard Biener <rguenther@suse.de>
4083 PR tree-optimization/113659
4084 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4085 Handle main exit without virtual use.
4087 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
4089 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
4091 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
4093 PR libgcc/113403
4094 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
4095 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
4096 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
4097 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
4098 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
4099 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
4101 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4103 PR target/113623
4104 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
4105 Mark all registers that occur in addresses as needing a GPR.
4107 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4109 PR target/113636
4110 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
4111 the containing insn as an extra parameter. Reset debug instructions
4112 if they reference a register that is no longer used by real insns.
4113 (early_ra::apply_allocation): Update calls accordingly.
4115 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4117 PR tree-optimization/113603
4118 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
4119 count_nonzero_bytes call refetch si using get_strinfo in case it
4120 has been unshared in the meantime.
4122 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4124 PR middle-end/101195
4125 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
4126 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
4128 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
4130 * config/riscv/thead.cc (th_print_operand_address): Change %ld
4131 to %lld.
4133 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
4134 Manolis Tsamis <manolis.tsamis@vrull.eu>
4135 Philipp Tomsich <philipp.tomsich@vrull.eu>
4137 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
4138 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
4139 Likewise.
4140 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
4141 Call on framework moved later.
4143 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
4145 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
4146 instruction in naked function epilogues.
4148 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
4150 PR target/113655
4151 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
4152 gcc_cv_as_mips_explicit_relocs.
4153 * configure: Regnerated.
4155 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
4157 PR target/108933
4158 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
4159 Correct generated RTL.
4160 (arm_rev16si2_alt1): Correctly handle conditional execution.
4161 (arm_rev16si2_alt2): Likewise.
4163 2024-01-29 Richard Biener <rguenther@suse.de>
4165 PR middle-end/113622
4166 * expr.cc (expand_assignment): Spill hard registers if
4167 we index them with a variable offset.
4169 2024-01-29 Richard Biener <rguenther@suse.de>
4171 PR middle-end/113622
4172 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
4173 Also allow DECL_HARD_REGISTER variables.
4175 2024-01-29 Alex Coplan <alex.coplan@arm.com>
4177 PR target/113616
4178 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
4179 Use iterate_safely when iterating over debug uses.
4180 (fixup_debug_uses): Likewise.
4181 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
4182 over nondebug insns instead of manually maintaining the next insn.
4183 * iterator-utils.h (class safe_iterator): New.
4184 (iterate_safely): New.
4186 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
4188 PR target/38534
4189 * config/i386/i386-options.cc (ix86_set_func_type): Save
4190 callee-saved registers in noreturn functions for -O0/-Og.
4192 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4194 PR target/113615
4195 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
4196 define for !TARGET_RDNA2_PLUS.
4198 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
4200 PR target/113281
4201 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
4202 workaround for right shifts.
4203 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
4204 (vect_determine_precisions_from_range): Be more selective about
4205 which codes can be narrowed based on their input and output ranges.
4206 For shifts, require at least one more bit of precision than the
4207 maximum shift amount.
4209 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4211 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
4213 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4215 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
4216 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
4217 LLVM 13.0.1+.
4219 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4221 PR other/111966
4222 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
4223 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
4224 (SET_SRAM_ECC_UNSET): ... this.
4225 (copy_early_debug_info): Remove gfx900 special case, now handled as
4226 part of the generic handling.
4227 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
4229 2024-01-29 Jakub Jelinek <jakub@redhat.com>
4231 PR tree-optimization/110603
4232 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
4233 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
4234 overwritten anyway). Avoid creating invalid range with minlen
4235 larger than maxlen. Formatting fix.
4237 2024-01-29 Richard Biener <rguenther@suse.de>
4239 PR debug/103047
4240 * tree-inline.cc (initialize_inlined_parameters): Reverse
4241 the decl chain of inlined parameters.
4243 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4245 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
4246 alignment of CFString constants by setting DECL_USER_ALIGN.
4248 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4249 Jakub Jelinek <jakub@redhat.com>
4251 PR libgcc/113402
4252 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
4253 and BUILT_IN_GCC_NESTED_PTR_DELETED.
4254 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
4255 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
4256 rename the library fallbacks to __gcc_nested_func_ptr_created and
4257 __gcc_nested_func_ptr_deleted.
4258 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
4259 and __gcc_nested_func_ptr_deleted.
4260 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
4261 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
4262 * tree.cc (build_common_builtin_nodes): Build the
4263 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
4264 builtins only for non-explicit.
4266 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
4268 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
4270 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4272 PR target/38534
4273 * config/i386/i386-options.cc (ix86_set_func_type): Don't
4274 save and restore callee saved registers for a noreturn function
4275 with nothrow or compiled with -fno-exceptions.
4277 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4279 PR target/103503
4280 PR target/113312
4281 * config/i386/i386-expand.cc (ix86_expand_call): Replace
4282 no_caller_saved_registers check with call_saved_registers check.
4283 Clobber all registers that are not used by the callee with
4284 no_callee_saved_registers attribute.
4285 * config/i386/i386-options.cc (ix86_set_func_type): Set
4286 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4287 noreturn function. Disallow no_callee_saved_registers with
4288 interrupt or no_caller_saved_registers attributes together.
4289 (ix86_set_current_function): Replace no_caller_saved_registers
4290 check with call_saved_registers check.
4291 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4292 (ix86_handle_call_saved_registers_attribute): This.
4293 (ix86_gnu_attributes): Add
4294 ix86_handle_call_saved_registers_attribute.
4295 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4296 no_caller_saved_registers check with call_saved_registers check.
4297 (ix86_function_ok_for_sibcall): Don't allow callee with
4298 no_callee_saved_registers attribute when the calling function
4299 has callee-saved registers.
4300 (ix86_comp_type_attributes): Also check
4301 no_callee_saved_registers.
4302 (ix86_epilogue_uses): Replace no_caller_saved_registers check
4303 with call_saved_registers check.
4304 (ix86_hard_regno_scratch_ok): Likewise.
4305 (ix86_save_reg): Replace no_caller_saved_registers check with
4306 call_saved_registers check. Don't save any registers for
4307 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
4308 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4309 no_callee_saved_registers attribute is called.
4310 (find_drap_reg): Replace no_caller_saved_registers check with
4311 call_saved_registers check.
4312 * config/i386/i386.h (call_saved_registers_type): New enum.
4313 (machine_function): Replace no_caller_saved_registers with
4314 call_saved_registers.
4315 * doc/extend.texi: Document no_callee_saved_registers attribute.
4317 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4319 PR tree-optimization/113614
4320 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4321 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4322 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4324 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4326 PR tree-optimization/113568
4327 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4328 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4329 in the widening extension checks.
4331 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4333 * gimple-lower-bitint.cc (gimple_lower_bitint): For
4334 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4336 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
4338 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4339 the warning for an attribute-always_inline without inline declaration.
4341 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
4343 PR other/113575
4344 * genopinit.cc (main): Split init_all_optabs into functions
4345 of 1000 patterns each.
4347 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4349 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4350 TM_MULTILIB_CONFIG.
4351 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4352 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4353 -march/-mtune.
4355 2024-01-26 Andrew Stubbs <ams@baylibre.com>
4357 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4358 * config/gcn/gcn-valu.md (all_convert): New iterator.
4359 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4360 define_expand, and rename the old one to ...
4361 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4362 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4363 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4364 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4365 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4366 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4367 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4368 (<u>mulqihi3_scalar): Likewise.
4370 2024-01-26 Richard Biener <rguenther@suse.de>
4372 PR tree-optimization/113602
4373 * tree-data-ref.cc (dr_analyze_innermost): Fail when
4374 the base object isn't addressable.
4376 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4378 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4379 "--amdhsa-code-object-version=" argument.
4380 (ASM_SPEC): Use it; replace previous version of it.
4382 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4384 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4385 (pre_vsetvl::emit_vsetvl): Ditto.
4387 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4389 * config/loongarch/lasx.md (vec_extract<mode>_0):
4390 New define_insn_and_split patten.
4392 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4394 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4396 2024-01-26 Li Wei <liwei@loongson.cn>
4398 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4400 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4402 PR target/113469
4403 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4405 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
4407 PR target/100212
4408 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4409 undefined shift after the call to exact_log2.
4411 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
4413 PR target/100204
4414 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4415 before taking the negative of it.
4417 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
4419 PR target/113526
4420 * lra-constraints.cc (curr_insn_transform): Change class even for
4421 spilled pseudo successfully matched with with NO_REGS.
4423 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
4425 PR target/113601
4426 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4428 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
4430 PR target/112987
4431 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4432 (aarch64_expand_epilogue): Use the new function.
4433 (aarch64_split_compare_and_swap): Likewise.
4434 (aarch64_split_atomic_op): Likewise.
4436 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
4438 PR middle-end/112971
4439 * fold-const.cc (simplify_const_binop): New function for binop
4440 simplification of two constant vectors when element-wise
4441 handling is not necessary.
4442 (const_binop): Call new function.
4444 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
4446 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4447 * config/riscv/constraints.md: Likewise.
4448 * config/riscv/corev.def: Likewise.
4449 * config/riscv/corev.md: Likewise.
4450 * config/riscv/predicates.md: Likewise.
4451 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4452 * config/riscv/riscv-ftypes.def: Likewise.
4453 * config/riscv/riscv.opt: Likewise.
4454 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4455 * doc/extend.texi: Add XCVbitmanip builtin documentation.
4456 * doc/sourcebuild.texi: Likewise.
4458 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
4460 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4462 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
4464 PR target/113538
4465 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4466 (riscv_fntype_abi): Ditto.
4467 * config/riscv/riscv.opt: Ditto.
4469 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4471 PR middle-end/113574
4472 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4473 count against TYPE_PRECISION rather than TYPE_SIZE.
4475 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4477 PR target/113572
4478 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4479 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4481 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4483 PR target/113550
4484 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4485 whether each split instruction is a load that clobbers the source
4486 address. Emit that instruction last if so.
4488 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4490 PR target/113485
4491 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4492 pattern.
4493 (<optab><Vnarrowq><mode>2): Use it instead of generating a
4494 paradoxical subreg for the input.
4496 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4498 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4499 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4500 predecessors dump information.
4502 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4504 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4505 redundant full available computation.
4506 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4508 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4510 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4511 * doc/rtl.texi (CONST_VECTOR): Likewise.
4513 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4515 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4516 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4517 (pass_vsetvl::execute): Ditto.
4518 * config/riscv/riscv.opt: Ditto.
4520 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
4522 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4523 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4525 2024-01-25 Richard Biener <rguenther@suse.de>
4527 PR tree-optimization/113576
4528 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4529 exits with may_be_zero niters when its the last one.
4531 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
4533 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4534 For symbols of type tls, non-zero Offset is not generated.
4536 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
4538 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4539 P9 with m32 and mpowerpc64.
4541 2024-01-25 liuhongt <hongtao.liu@intel.com>
4543 * config/i386/i386-options.cc (ix86_option_override_internal):
4544 Enable -mlam=u57 by default when compiled with
4545 -fsanitize=hwaddress.
4547 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
4549 * common/config/riscv/riscv-common.cc (riscv_implied_info):
4550 Remove {"ztso", "a"}.
4552 2024-01-24 Martin Jambor <mjambor@suse.cz>
4554 PR ipa/108007
4555 PR ipa/112616
4556 * cgraph.h (cgraph_edge): Add a parameter to
4557 redirect_call_stmt_to_callee.
4558 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4559 parameter to modify_call.
4560 (ipa_release_ssas_in_hash): Declare.
4561 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4562 parameter killed_ssas, pass it to padjs->modify_call.
4563 * ipa-param-manipulation.cc (purge_all_uses): New function.
4564 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4565 Instead of substituting uses, invoke purge_all_uses. If
4566 hash of killed SSAs has not been provided, create a temporary one
4567 and release SSAs that have been added to it.
4568 (compare_ssa_versions): New function.
4569 (ipa_release_ssas_in_hash): Likewise.
4570 * tree-inline.cc (redirect_all_calls): Create
4571 id->killed_new_ssa_names earlier, pass it to edge redirection,
4572 adjust a comment.
4573 (copy_body): Release SSAs in id->killed_new_ssa_names.
4575 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
4577 PR target/113486
4578 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4579 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4581 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
4583 PR target/113095
4584 * config/riscv/sfb.md: New splitters to rewrite single bit
4585 sign extension as the condition to SFB instructions.
4587 2024-01-24 Jan Hubicka <jh@suse.cz>
4589 PR middle-end/88345
4590 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4591 (fmin-function-alignment): New parameter.
4592 * doc/invoke.texi: (-fmin-function-alignment): Document.
4593 (-falign-functions,-falign-loops,-falign-labels): Mention that
4594 aglinments are ignored in cold code.
4595 * varasm.cc (assemble_start_function): Handle min-function-alignment.
4597 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4599 PR target/109636
4600 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4601 mulv2di3): Remove.
4602 * config/aarch64/iterators.md (VQDIV): Remove.
4603 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4604 SVE_I_SIMD_DI): New.
4605 (VPRED, sve_lane_con): Add V4SI and V2DI.
4606 * config/aarch64/aarch64-sve.md (<optab><mode>3,
4607 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4608 (mul<mode>3): New, split from <optab><mode>3.
4609 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4610 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4611 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4612 SVE_FULL_HSDI_SIMD_DI.
4614 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4616 PR tree-optimization/113552
4617 * config/aarch64/aarch64.cc
4618 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4620 2024-01-24 Martin Jambor <mjambor@suse.cz>
4622 PR ipa/113490
4623 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4624 count is equal or greater than the limit. Use the limit from the
4625 callee.
4627 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
4629 * configure.ac: Detect the explicit relocs support for
4630 mips, and define C macro MIPS_EXPLICIT_RELOCS.
4631 * config.in: Regenerated.
4632 * configure: Regenerated.
4633 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4634 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4635 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4636 !TARGET_EXPLICIT_RELOCS instead of just set it.
4637 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4638 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4639 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4640 and define -m(no-)explicit-relocs as aliases.
4642 2024-01-24 Alex Coplan <alex.coplan@arm.com>
4644 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4645 to 1.
4646 (-mlate-ldp-fusion): Likewise.
4648 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4650 * tree-vect-loop.cc (vect_get_vect_def,
4651 vect_create_epilog_for_reduction): Rename main_exit_p to
4652 last_val_reduc_p.
4654 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4656 PR tree-optimization/113364
4657 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4658 early exits then we must reduce from the first offset for all of them.
4660 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4662 PR target/113495
4663 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4664 (get_regno): Ditto.
4665 (get_bb_index): Ditto.
4666 (pre_vsetvl::compute_avl_def_data): Ditto.
4667 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4668 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4670 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
4671 Richard Sandiford <richard.sandiford@arm.com>
4673 PR target/100942
4674 * ccmp.cc (ccmp_candidate_p): Add outer argument.
4675 Allow if the outer is true and the lhs is used more
4676 than once.
4677 (expand_ccmp_expr): Update call to ccmp_candidate_p.
4678 * expr.h (expand_expr_real_gassign): Declare.
4679 * expr.cc (expand_expr_real_gassign): New function, split out from...
4680 (expand_expr_real_1): ...here.
4681 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4683 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4685 PR target/113089
4686 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4687 (fixup_debug_use): New.
4688 (fixup_debug_uses_trailing_add): New.
4689 (fixup_debug_uses): New. Use it ...
4690 (ldp_bb_info::fuse_pair): ... here.
4691 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4692 fix up debug uses of the base register that are affected by
4693 folding in the trailing add insn.
4695 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4697 PR target/113089
4698 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4699 Update trailing nondebug uses of the base register in the case
4700 of cancelling writeback.
4702 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4704 PR target/113089
4705 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4706 (debug_insn_use_iterator): New.
4707 (set_info::first_debug_insn_use): New.
4708 (set_info::debug_insn_uses): New.
4709 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4710 (set_info::first_debug_insn_use): New.
4711 (set_info::debug_insn_uses): New.
4713 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4715 PR target/113356
4716 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4717 Don't record hazards against the opposite insn in the pair.
4719 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4721 PR target/113070
4722 * config/aarch64/aarch64-ldp-fusion.cc
4723 (struct stp_change_builder): New.
4724 (decide_stp_strategy): Reanme to ...
4725 (try_repurpose_store): ... this.
4726 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4727 construct stp changes. Fix up uses when inserting new stp insns.
4729 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4731 PR target/113070
4732 * rtl-ssa.h: Include hash-set.h.
4733 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4734 new_sets parameter and use it to keep track of new user-created sets.
4735 (function_info::apply_changes_to_insn): Also call add_def on new sets.
4736 (function_info::change_insns): Add hash_set to keep track of new
4737 user-created defs. Plumb it through.
4738 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4739 apply_changes_to_insn.
4741 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4743 PR target/113070
4744 * rtl-ssa/accesses.cc (function_info::create_use): New.
4745 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4746 Ensure new uses end up referring to permanent defs.
4747 * rtl-ssa/functions.h (function_info::create_use): Declare.
4749 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4751 PR target/113070
4752 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
4753 to finalize_new_accesses from the backwards placement loop, run it
4754 forwards in a separate loop.
4756 2024-01-23 Richard Biener <rguenther@suse.de>
4758 PR tree-optimization/113552
4759 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
4760 floor_log2 instead of exact_log2 on the number of calls.
4762 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
4763 Jakub Jelinek <jakub@redhat.com>
4765 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
4766 decl.
4768 2024-01-23 Richard Biener <rguenther@suse.de>
4770 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4771 Separate single and multi-exit case when creating PHIs between
4772 the main and epilogue.
4774 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
4776 PR target/112989
4777 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4778 MODE_single variants of functions that don't take tuple arguments.
4780 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4782 PR target/113114
4783 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4784 Don't assert recog success, just punt if the writeback pair
4785 isn't recognized.
4787 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4789 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4790 ATTRIBUTE_UNUSED to decl.
4792 2024-01-23 Richard Biener <rguenther@suse.de>
4794 PR debug/107058
4795 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4796 handle unexpected but bogus DIE contexts when not checking
4797 enabled.
4799 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4801 PR tree-optimization/113462
4802 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4803 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4804 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4805 sizes between 129 and 8192 bytes.
4807 2024-01-23 Xi Ruoyao <xry111@xry111.site>
4809 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4810 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4811 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4812 (loongarch_call_tls_get_addr): Do not split symbols of
4813 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4814 EXPLICIT_RELOCS_AUTO.
4816 2024-01-23 Richard Biener <rguenther@suse.de>
4818 * alias.cc (known_base_value_p): Remove.
4819 (find_base_value): Remove PLUS/MINUS handling
4820 when both operands are not CONST_INT_P.
4822 2024-01-23 Richard Biener <rguenther@suse.de>
4824 PR rtl-optimization/113255
4825 * alias.cc (find_base_term): Remove PLUS/MINUS handling
4826 when both operands are not CONST_INT_P.
4828 2024-01-23 Richard Biener <rguenther@suse.de>
4830 PR debug/112718
4831 * dwarf2out.cc (dwarf2out_finish): Reset all type units
4832 for the fat part of an LTO compile.
4834 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
4836 * doc/sourcebuild.texi: Add attributes for keywords.
4838 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
4840 PR c++/90463
4841 * doc/invoke.texi (Warning Options): Correct lists of options
4842 enabled by -Wall and -Wextra by checking against common.opt
4843 and c-family/c.opt.
4845 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
4847 PR target/113030
4848 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
4849 instead of cpu_optaliases.
4850 (check_arch): Use arch_opt_alias instead of arch_optaliases.
4852 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4854 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
4855 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
4856 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
4858 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4860 PR target/109092
4861 * config/riscv/riscv.md: Use reg instead of subreg.
4863 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
4865 PR other/111966
4866 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
4867 to match the compiler default.
4868 (simple_object_copy_lto_debug_sections): Never unlink the outfile
4869 on error as the caller does so.
4870 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
4871 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
4873 2024-01-22 Richard Biener <rguenther@suse.de>
4875 PR tree-optimization/113373
4876 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4877 Create LC PHIs in the exit blocks where necessary.
4878 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
4879 to handle missing LC PHIs.
4880 (find_connected_edge): Remove.
4881 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
4883 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4885 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
4887 2024-01-22 xuli <xuli1@eswincomputing.com>
4889 PR target/113420
4890 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
4891 (registered_function::overloaded_hash):refactor.
4892 (resolve_overloaded_builtin):avoid internal ICE.
4894 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
4896 PR target/82420
4897 PR target/111279
4898 * calls.cc (emit_library_call_value_1): Pass valid TYPE
4899 to emit_push_insn.
4900 * expr.cc (emit_push_insn): Likewise.
4902 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4904 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
4905 correcction version of last change.
4907 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4909 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
4910 fix bugs in signature.
4912 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
4913 Richard Biener <rguenther@suse.de>
4915 PR rtl-optimization/111267
4916 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
4917 profitable_p method to likely_profitable_p.
4918 (try_fwprop_subst_node): Update call to likely_profitable_p.
4919 Only bail-out early when !prop.likely_profitable_p for instructions
4920 that are not single sets. When comparing costs, bail-out if the
4921 cost is unchanged and !prop.likely_profitable_p.
4923 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4925 PR c++/90464
4926 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
4927 isn't enabled by -Wunused unless -Wextra is provided, and that
4928 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
4929 -Wunused doesn't enable -Wunused-* options documented as behaving
4930 otherwise, and list them explicitly.
4932 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4934 PR c/109708
4935 * doc/invoke.texi (Warning Options): Fix broken example and
4936 clean up/reorganize the others. Also describe what the short-form
4937 options mean.
4939 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
4941 PR c/102998
4942 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
4943 (Warning Options): Correct/edit discussion of -Warray-parameter
4944 to make the first example less confusing, and fill in missing info.
4946 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4948 PR tree-optimization/113462
4949 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
4950 Handle rhs1 INTEGER_CST like SSA_NAME.
4952 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4954 PR tree-optimization/113491
4955 * tree-switch-conversion.cc (switch_conversion::build_constructors):
4956 If elt.index has precision higher than sizetype, fold_convert it to
4957 sizetype.
4958 (switch_conversion::array_value_type): Return type if type is
4959 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
4960 (switch_conversion::build_arrays): Use unsigned_type_for rather than
4961 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
4962 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
4963 higher than sizetype, use sizetype as tidx type and fold_convert the
4964 subtraction to sizetype.
4966 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4968 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
4969 (riscv_vector_mode_supported_any_target_p): Ditto.
4971 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4973 PR target/110934
4974 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
4975 (TARGET_ZERO_CALL_USED_REGS): Define.
4977 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4979 PR target/108640
4980 * config/m68k/m68k.cc (output_andsi3): Use QImode for
4981 address adjusted for 1-byte RMW access.
4982 (output_iorsi3): Likewise.
4983 (output_xorsi3): Likewise.
4985 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4987 * doc/invoke.texi (RISC-V Options): Add list of supported
4988 extensions.
4990 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4992 PR target/113495
4993 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
4994 (RVV_VUNDEF): Ditto.
4995 * config/riscv/riscv-vsetvl.cc: Add timevar.
4997 2024-01-19 Richard Biener <rguenther@suse.de>
4999 PR debug/113488
5000 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
5001 an early DIE but there should be, do not pretend there is.
5003 2024-01-19 Richard Biener <rguenther@suse.de>
5005 PR tree-optimization/113494
5006 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5007 Handle endless loop on exit. Handle re-allocated PHI.
5009 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5011 PR tree-optimization/113464
5012 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
5013 optimize loads into GIMPLE_ASM stmts.
5015 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5017 PR tree-optimization/113463
5018 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
5019 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
5020 lhs.
5022 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5024 PR tree-optimization/113459
5025 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
5026 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
5027 of SCALAR_INT_TYPE_MODE if type has BLKmode.
5028 (vn_reference_lookup_3): Likewise. Formatting fix.
5030 2024-01-19 Jakub Jelinek <jakub@redhat.com>
5031 Richard Biener <rguenther@suse.de>
5033 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
5034 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
5035 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
5036 but adjust_address also for BLKmode mode and MEM op0.
5038 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
5040 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
5041 extensions.
5043 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5045 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
5047 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5049 * common/config/riscv/riscv-common.cc
5050 (riscv_subset_list::parse_std_ext): Remove.
5051 (riscv_subset_list::parse_multiletter_ext): Remove.
5052 * config/riscv/riscv-subset.h
5053 (riscv_subset_list::parse_std_ext): Remove.
5054 (riscv_subset_list::parse_multiletter_ext): Remove.
5056 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5058 * common/config/riscv/riscv-common.cc
5059 (riscv_subset_list::parse_single_std_ext): New parameter.
5060 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
5061 (riscv_subset_list::parse_single_ext): Ditto.
5062 (riscv_subset_list::parse): Relax the order for the input of ISA
5063 string.
5064 * config/riscv/riscv-subset.h
5065 (riscv_subset_list::parse_single_std_ext): New parameter.
5066 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
5067 (riscv_subset_list::parse_single_ext): Ditto.
5069 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5071 * common/config/riscv/riscv-common.cc
5072 (riscv_subset_list::parse_base_ext): New.
5073 (riscv_subset_list::parse): Extract part of logic into
5074 riscv_subset_list::parse_base_ext.
5075 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
5076 New.
5078 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
5080 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
5081 sorry message.
5083 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
5085 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
5086 UNSPEC_CLMUL_VC.
5088 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
5090 PR c/110029
5091 * doc/extend.texi (Common Variable Attributes): Explain what
5092 happens when multiple variables with cleanups are in the same scope.
5094 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5096 PR ipa/108470
5097 * doc/extend.texi (Common Function Attributes): Document that
5098 noinline also disables some interprocedural optimizations and
5099 improve flow to the part about using inline asm instead to
5100 disable calls from being optimized away completely. Remove the
5101 sentence that says noipa is mainly for internal compiler testing.
5103 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
5105 PR tree-optimization/69807
5106 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
5108 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
5110 PR target/108521
5111 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
5112 from x86 Windows Options.
5114 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5116 PR c/107942
5117 * doc/extend.texi (C Extensions): Add new section to menu.
5118 (Function Attributes): Move dangling index entries to....
5119 (Const and Volatile Functions): New section.
5121 2024-01-18 David Malcolm <dmalcolm@redhat.com>
5123 PR middle-end/112684
5124 * toplev.cc (toplev::main): Don't ICE in
5125 -fdiagnostics-generate-patch when exiting after options,
5126 since no edit context will have been created.
5128 2024-01-18 Richard Biener <rguenther@suse.de>
5130 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
5131 operands vector.
5133 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5135 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
5136 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
5138 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5139 Jin Ma <jinma@linux.alibaba.com>
5140 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5141 Christoph Müllner <christoph.muellner@vrull.eu>
5143 * config/riscv/thead.cc
5144 (th_asm_output_opcode): Rewrite some instructions.
5146 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5147 Jin Ma <jinma@linux.alibaba.com>
5148 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5149 Christoph Müllner <christoph.muellner@vrull.eu>
5151 * config/riscv/riscv.md (none,thv,rvv): New attribute.
5152 (no,yes): Add an attribute to disable alternative
5153 for xtheadvector or RVV1.0.
5154 * config/riscv/vector.md:
5155 Disable alternatives that destination register overlaps
5156 source register group for xtheadvector.
5158 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5159 Jin Ma <jinma@linux.alibaba.com>
5160 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5161 Christoph Müllner <christoph.muellner@vrull.eu>
5163 * config/riscv/riscv-vector-builtins-bases.cc
5164 (class th_loadstore_width): Define new builtin bases.
5165 (class th_extract): Define new builtin bases.
5166 (BASE): Define new builtin bases.
5167 * config/riscv/riscv-vector-builtins-bases.h:
5168 Define new builtin class.
5169 * config/riscv/riscv-vector-builtins-shapes.cc
5170 (struct th_loadstore_width_def): Define new builtin shapes.
5171 (struct th_indexed_loadstore_width_def):
5172 Define new builtin shapes.
5173 (struct th_extract_def): Define new builtin shapes.
5174 (SHAPE): Define new builtin shapes.
5175 * config/riscv/riscv-vector-builtins-shapes.h:
5176 Define new builtin shapes.
5177 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
5178 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
5179 * config/riscv/riscv-vector-builtins.h
5180 (enum required_ext): Add new XTheadVector member.
5181 (struct function_group_info): Likewise.
5182 * config/riscv/t-riscv:
5183 Add thead-vector-builtins-functions.def
5184 * config/riscv/thead-vector.md
5185 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
5186 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
5187 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
5188 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
5189 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
5190 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
5191 (@pred_th_extract<mode>): Likewise.
5192 (*pred_th_extract<mode>): Likewise.
5193 * config/riscv/thead-vector-builtins-functions.def: New file.
5195 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5196 Jin Ma <jinma@linux.alibaba.com>
5197 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5198 Christoph Müllner <christoph.muellner@vrull.eu>
5200 * config.gcc: Add files for XTheadVector intrinsics.
5201 * config/riscv/autovec.md: Guard XTheadVector.
5202 * config/riscv/predicates.md: Disable immediate vl
5203 for XTheadVector.
5204 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
5205 Add pragma for XTheadVector.
5206 * config/riscv/riscv-string.cc (riscv_expand_block_move):
5207 Guard XTheadVector.
5208 * config/riscv/riscv-v.cc (vls_mode_valid_p):
5209 Avoid autovec.
5210 * config/riscv/riscv-vector-builtins-bases.cc:
5211 Do not normalize vsetvl instructions for XTheadVector.
5212 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
5213 New check type function.
5214 (build_one): Adjust for XTheadVector.
5215 * config/riscv/riscv-vector-switch.def (ENTRY):
5216 Disable fractional mode for the XTheadVector extension.
5217 (TUPLE_ENTRY): Likewise.
5218 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
5219 Guard XTheadVector.
5220 (riscv_preferred_simd_mode): Likewsie.
5221 (riscv_autovectorize_vector_modes): Likewise.
5222 (riscv_vector_mode_supported_any_target_p): Likewise.
5223 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
5224 * config/riscv/thead.cc (th_asm_output_opcode):
5225 Rewrite vsetvl instructions.
5226 * config/riscv/vector.md:
5227 Include thead-vector.md and change fractional LMUL
5228 into 1 for vbool.
5229 * config/riscv/riscv_th_vector.h: New file.
5230 * config/riscv/thead-vector.md: New file.
5232 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5233 Jin Ma <jinma@linux.alibaba.com>
5234 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5235 Christoph Müllner <christoph.muellner@vrull.eu>
5237 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
5238 Add new function to add assembler insn code prefix/suffix.
5239 (th_asm_output_opcode):
5240 Add Thead function to add assembler insn code prefix/suffix.
5241 * config/riscv/riscv.cc (riscv_asm_output_opcode):
5242 Implement function to add assembler insn code prefix/suffix.
5243 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
5244 Add new function to add assembler insn code prefix/suffix.
5245 * config/riscv/thead.cc (th_asm_output_opcode):
5246 Implement Thead function to add assembler insn code
5247 prefix/suffix.
5249 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5250 Jin Ma <jinma@linux.alibaba.com>
5251 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5252 Christoph Müllner <christoph.muellner@vrull.eu>
5254 * common/config/riscv/riscv-common.cc
5255 (riscv_subset_list::parse): Add new vendor extension.
5256 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
5257 Add test marco.
5258 * config/riscv/riscv.opt: Add new mask.
5260 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5262 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
5263 to be conditional on macosx-version-min.
5265 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5267 * config/darwin.cc (darwin_objc1_section): Use the correct
5268 meta-data version for constant strings.
5269 (machopic_select_section): Assert if we fail to handle CFString
5270 sections as Obejctive-C meta-data or drectly.
5272 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5274 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
5275 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
5276 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5277 versions when the object format is Mach-O.
5279 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5281 PR target/105522
5282 * config/darwin.cc (machopic_select_section): Handle C and C++
5283 CFStrings.
5284 (darwin_rename_builtins): Move this out of the CFString code.
5285 (darwin_libc_has_function): Likewise.
5286 (darwin_build_constant_cfstring): Create an anonymous var to
5287 hold each CFString.
5288 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5289 CFstrings.
5291 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5293 PR bootstrap/113445
5294 * haifa-sched.cc (dep_list_size): Make global.
5295 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5296 * sched-int.h (dep_list_size): Declare.
5298 2024-01-18 Martin Jambor <mjambor@suse.cz>
5300 PR tree-optimization/110422
5301 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5302 gotos.
5304 2024-01-18 Richard Biener <rguenther@suse.de>
5306 PR tree-optimization/113475
5307 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5308 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5309 (phi_analyzer::~phi_analyzer): Deallocate and free collected
5310 phi_grous.
5311 (phi_analyzer::process_phi): Record allocated phi_groups.
5313 2024-01-18 Richard Biener <rguenther@suse.de>
5315 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5316 storage for gvec_oprnds elements.
5318 2024-01-18 Richard Biener <rguenther@suse.de>
5320 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5321 prefer all later exits we can handle.
5322 (vect_analyze_loop_form): Free the allocated loop body.
5323 Adjust comments.
5325 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5327 * config/avr/avr-log.cc: Tabify.
5329 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5331 * config/riscv/autovec.md: Support vi variant.
5333 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5335 * config/avr/avr-devices.cc: Tabify.
5337 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5339 * config/avr/avr-c.cc: Tabify.
5341 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5343 * config/avr/driver-avr.cc: Tabify.
5345 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5347 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5349 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5351 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5353 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5355 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5356 minline-strcmp, minline-strncmp, minline-strlen,
5357 -param=riscv-vector-abi): Remove Bool keywords.
5359 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5361 PR target/113122
5362 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5363 support. Add missing space after , in emitted assembly in some
5364 cases. Formatting fixes.
5366 2024-01-18 Xi Ruoyao <xry111@xry111.site>
5368 * config/loongarch/loongarch.md (movsi_internal): Remove
5369 constraint z.
5371 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5373 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5374 in the diagnostic, and capitalize the device name.
5375 (print_mcu): Generate specs such that:
5376 <*check_rodata_in_ram>: New.
5377 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5378 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5379 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5381 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5383 PR other/113399
5384 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5385 Common and Optimization.
5387 2024-01-18 Richard Biener <rguenther@suse.de>
5389 PR tree-optimization/113431
5390 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5391 When there is an invariant load we might not preserve
5392 scalar order.
5394 2024-01-18 Richard Biener <rguenther@suse.de>
5396 PR tree-optimization/113374
5397 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5398 * tree-vect-loop.cc (move_early_exit_stmts): Update
5399 virtual LC PHIs.
5400 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5401 Refactor. Preserve virtual LC PHIs on all exits.
5403 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
5405 * config/loongarch/loongarch.cc (loongarch_split_symbol):
5406 Assign the '/u' attribute to the mem.
5408 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5410 PR middle-end/110847
5411 * doc/invoke.texi (Option Summary): Document negative forms of
5412 -Wtsan and -Wxor-used-as-pow.
5413 (Warning Options): Likewise.
5415 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5417 PR target/113429
5418 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5420 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5422 * doc/extend.texi (Common Function Attributes): Re-alphabetize
5423 the table.
5424 (Common Variable Attributes): Likewise.
5425 (Common Type Attributes): Likewise.
5427 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5429 PR middle-end/111659
5430 * doc/extend.texi (Common Variable Attributes): Fix long lines
5431 in documentation of strict_flex_array + other minor copy-editing.
5432 Add a cross-reference to -Wstrict-flex-arrays.
5433 * doc/invoke.texi (Option Summary): Fix whitespace in tables
5434 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5435 (C Dialect Options): Combine the docs for the two
5436 -fstrict-flex-arrays forms into a single entry. Note this option
5437 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
5438 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5439 Minor copy-editing. Add cross references to the strict_flex_array
5440 attribute and -fstrict-flex-arrays option. Add note that this
5441 option depends on -ftree-vrp.
5443 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
5445 PR target/113221
5446 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5447 only allow REG operands instead of allowing all.
5449 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5451 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5452 Remove redundant checks in else condition for readablity.
5453 (earliest_fuse_vsetvl_info) Print iteration count in debug
5454 prints.
5455 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5456 dump details in certain cases.
5458 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5460 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5461 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5462 * config/riscv/riscv-vsetvl.cc
5463 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5464 (pass_vsetvl::execute): Use vsetvl_strategy.
5466 2024-01-17 Jan Hubicka <jh@suse.cz>
5468 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5469 accidental hack reseting offset.
5471 2024-01-17 Jan Hubicka <jh@suse.cz>
5473 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5474 handling of X86_TUNE_AVOID_512FMA_CHAINS.
5476 2024-01-17 Jan Hubicka <jh@suse.cz>
5477 Jakub Jelinek <jakub@redhat.com>
5479 PR tree-optimization/110852
5480 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5481 binary operations
5482 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5483 PRED_COMBINED_VALUE_PREDICTIONS_PHI
5484 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5485 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5487 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5489 PR tree-optimization/113421
5490 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5491 comment.
5492 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5493 formatting. Start at vop rather than cvop even if stmt is a store
5494 and needs_operand_addr.
5496 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5498 PR middle-end/113410
5499 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5500 If access_nelts is integral with larger precision than sizetype,
5501 fold_convert it to sizetype.
5503 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5505 PR tree-optimization/113408
5506 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5507 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5508 to handle_cast.
5510 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5512 PR middle-end/113406
5513 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5514 regardless of whether is_gimple_reg_type (restype) or not.
5516 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5518 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5519 funcions -> functions, and use were instead of was.
5520 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5521 and guaranteee -> guarantee.
5522 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5524 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5526 PR middle-end/113409
5527 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5528 INTEGER_TYPE.
5529 (omp_extract_for_data): Use build_bitint_type rather than
5530 build_nonstandard_integer_type if either iter_type or loop->v type
5531 is BITINT_TYPE.
5532 * omp-expand.cc (expand_omp_for_generic,
5533 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5534 BITINT_TYPE like INTEGER_TYPE.
5536 2024-01-17 Richard Biener <rguenther@suse.de>
5538 PR tree-optimization/113371
5539 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5540 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5541 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5542 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5544 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5546 PR rtl-optimization/96388
5547 PR rtl-optimization/111554
5548 * sched-deps.cc (find_inc): Avoid exponential behavior.
5550 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5552 PR c/111693
5553 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5554 from C++ Language Options to Warning Options. Add entry for
5555 -Wuse-after-free.
5556 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5557 from here....
5558 (Warning Options): ...to here. Minor copy-editing to fix typo
5559 and grammar.
5561 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
5563 * config/mips/mips.cc (mips_compute_frame_info): If another
5564 register is used as global_pointer, mark $GP live false.
5566 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5568 PR target/112973
5569 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5570 give the section a light copy-editing pass.
5572 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5574 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5575 * config/aarch64/aarch64-tune.md: Regenerated.
5576 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5578 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5580 PR target/112573
5581 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5582 badly formed CONST expressions.
5584 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5586 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5588 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5590 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5591 * config/sparc/sync.md (membar_storeload): Turn into named insn
5592 and add GR712RC errata workaround.
5593 (membar_v8): Add GR712RC errata workaround.
5595 2024-01-16 Andreas Larsson <andreas@gaisler.com>
5597 * config/sparc/sync.md (*membar_storeload_leon3): Remove
5598 (*membar_storeload): Enable for LEON
5600 2024-01-16 Jakub Jelinek <jakub@redhat.com>
5602 PR tree-optimization/113372
5603 PR middle-end/90348
5604 PR middle-end/110115
5605 PR middle-end/111422
5606 * cfgexpand.cc (add_scope_conflicts_2): New function.
5607 (add_scope_conflicts_1): Use it.
5609 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
5611 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5612 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5613 * doc/avr-mmcu.texi: Regenerate.
5615 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
5617 PR tree-optimization/113091
5618 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5619 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5620 scalar use with new function.
5621 (vect_bb_slp_mark_live_stmts): New function as entry to existing
5622 overriden functions with same name.
5623 (vect_slp_analyze_operations): Call new entry function to mark
5624 live statements.
5626 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5628 PR target/113404
5629 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5630 for RVV in big-endian mode.
5632 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
5634 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5635 (riscv_pass_in_vector_p): Delete.
5636 (riscv_init_cumulative_args): Delete the checking.
5637 (riscv_get_arg_info): Delete the checking.
5638 (riscv_function_value): Delete the checking.
5639 * config/riscv/riscv.h: Delete the member for checking.
5641 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5643 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5645 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5647 * config.gcc: Include riscv_bitmanip.h.
5648 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5649 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5650 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5651 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5652 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5653 * config/riscv/riscv-ftypes.def (2): New ftypes.
5654 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5655 (RISCV_BUILTIN_NO_PREFIX): Likewise.
5656 * config/riscv/riscv_bitmanip.h: New file.
5658 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5660 * config.gcc: Include riscv_crypto.h.
5661 * config/riscv/riscv_crypto.h: New file.
5663 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
5665 PR middle-end/113354
5666 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5667 in the insn if the corresponding operand does not require hard
5668 register anymore.
5670 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5672 PR target/107201
5673 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5674 * config/avr/driver-avr.cc (avr_no_devlib): New function.
5675 (avr_devicespecs_file): Use it to remove -nodevicelib from the
5676 options for cores only.
5677 * config/avr/avr-arch.h (avr_get_parch): New prototype.
5678 * config/avr/avr-devices.cc (avr_get_parch): New function.
5680 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5682 PR target/113247
5683 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5684 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5685 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5687 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5689 PR target/113281
5690 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5691 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5692 * config/riscv/riscv-vector-costs.h: New function.
5694 2024-01-15 Richard Biener <rguenther@suse.de>
5696 PR tree-optimization/113385
5697 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5698 First redirect, then split the exit edge.
5700 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5702 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5703 Remove m_num_vector_iterations.
5704 * config/riscv/riscv-vector-costs.h: Ditto.
5706 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
5708 PR target/113156
5709 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5710 (-mbranch-cost): Set "Optimization" flag.
5712 2024-01-15 Jakub Jelinek <jakub@redhat.com>
5714 PR tree-optimization/113370
5715 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5716 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5717 set it to just prec % limb_prec.
5719 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5721 PR target/113393
5722 * config/riscv/vector.md: Fix ternary attributes.
5724 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
5726 PR target/112944
5727 * configure.ac [target=avr]: Check availability of emulations
5728 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5729 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5730 * configure: Regenerate.
5731 * config.in: Regenerate.
5732 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5733 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5734 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5735 * config/avr/avr-arch.h (enum avr_device_specific_features):
5736 Add AVR_ISA_FLMAP.
5737 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5738 AVR_ISA_FLMAP.
5739 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5740 (avr_set_core_architecture): Set avr_arch_index.
5741 (have_avrxmega2_flmap, have_avrxmega4_flmap)
5742 (have_avrxmega3_rodata_in_flash): Set new static const bool according
5743 to configure results.
5744 (avr_rodata_in_flash_p): New function using them.
5745 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5746 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5747 (avr_asm_named_section): Track avr_has_rodata_p.
5748 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5749 and not avr_rodata_in_flash_p ().
5750 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5751 (LINK_SPEC): Add %(link_rodata_in_ram).
5752 (LINK_ARCH_SPEC): Remove.
5753 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
5754 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
5755 const bool according to configure results.
5756 (diagnose_mrodata_in_ram): New function.
5757 (print_mcu): Generate specs with the following changes:
5758 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
5759 need to extend avr/specs.h each time we add a new bell or whistle.
5760 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
5761 -m[no-]rodata-in-ram.
5762 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
5763 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
5764 <*cpp>: Add %(cpp_rodata_in_ram).
5765 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
5766 requested.
5767 <*self_spec>: Add -mflmap or %<mflmap as needed.
5769 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
5771 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
5772 not the GPR iterator. Adjust pattern name and mode attribute
5773 accordingly.
5775 2024-01-13 Jakub Jelinek <jakub@redhat.com>
5777 PR tree-optimization/113361
5778 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5779 Fix up determination of the type for > limb_prec constants.
5781 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5783 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5784 Add web-link to the avr-gcc wiki.
5786 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5788 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5789 documentation for a version without argument, which is not supported.
5791 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5793 * config/arm/arm_neon.h
5794 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5795 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5796 (vld1_f16_x4, vld1_f32_x4): New.
5797 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5798 (vld1_bf16_x4): New.
5799 (vld1q_types_x4): Updated to use vld1q_x4
5800 from arm_neon_builtins.def
5801 * config/arm/arm_neon_builtins.def
5802 (vld1_x4): Updated entries.
5803 (vld1q_x4): New entries, but comes from the old vld1_x4
5804 * config/arm/neon.md
5805 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5807 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5809 * config/arm/arm_neon.h
5810 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5811 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5812 (vld1_f16_x3, vld1_f32_x3): New.
5813 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5814 (vld1_bf16_x3): New.
5815 (vld1q_types_x3): Updated to use vld1q_x3 from
5816 arm_neon_builtins.def
5817 * config/arm/arm_neon_builtins.def
5818 (vld1_x3): Updated entries.
5819 (vld1q_x3): New entries, but comes from the old vld1_x2
5820 * config/arm/neon.md
5821 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
5823 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5825 * config/arm/arm_neon.h
5826 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
5827 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
5828 (vld1_f16_x2, vld1_f32_x2): New.
5829 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
5830 (vld1_bf16_x2): New.
5831 (vld1q_types_x2): Updated to use vld1q_x2 from
5832 arm_neon_builtins.def
5833 * config/arm/arm_neon_builtins.def
5834 (vld1_x2): Updated entries.
5835 (vld1q_x2): New entries, but comes from the old vld1_x2
5836 * config/arm/neon.md
5837 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5838 neon_vld1_x2<mode>.
5840 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5842 * config/arm/arm_neon.h
5843 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
5844 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
5845 (vst1q_f16_x4, vst1q_f32_x4): New.
5846 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
5847 (vst1q_bf16_x4): New.
5848 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
5849 * config/arm/neon.md
5850 (neon_vst1q_x4<mode>): New.
5851 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
5852 * config/arm/unspecs.md
5853 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
5855 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5857 * config/arm/arm_neon.h
5858 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
5859 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
5860 (vst1q_f16_x3, vst1q_f32_x3): New.
5861 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
5862 (vst1q_bf16_x3): New.
5863 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
5864 * config/arm/neon.md
5865 (neon_vst1q_x3<mode>): New.
5866 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
5867 * config/arm/unspecs.md
5868 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
5870 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5872 * config/arm/arm_neon.h
5873 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
5874 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
5875 (vst1q_f16_x2, vst1q_f32_x2): New.
5876 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
5877 (vst1q_bf16_x2): New.
5878 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
5879 * config/arm/neon.md
5880 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5881 neon_vst1_x2<mode>.
5882 * config/arm/iterators.md
5883 (VMEMX2): New mode iterator.
5884 (VMEMX2_q): New mode attribute.
5886 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5888 * config/arm/arm_neon.h
5889 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
5890 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
5891 (vst1_f16_x4, vst1_f32_x4): New.
5892 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
5893 (vst1_bf16_x4): New.
5894 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
5895 * config/arm/neon.md (vst1_x4<mode>): New.
5897 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5899 * config/arm/arm_neon.h
5900 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
5901 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
5902 (vst1_f16_x3, vst1_f32_x3): New.
5903 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
5904 (vst1_bf16_x3): New.
5905 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
5906 * config/arm/neon.md (vst1_x3<mode>): New.
5908 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5910 * config/arm/arm_neon.h
5911 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
5912 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
5913 (vst1_f16_x2, vst1_f32_x2): New.
5914 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
5915 (vst1_bf16_x2): New.
5916 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
5917 * config/arm/neon.md (vst1_x2<mode>): New.
5919 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5921 * config/arm/arm_neon.h
5922 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
5923 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
5924 (vld1q_f16_x4, vld1q_f32_x4): New.
5925 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
5926 (vld1q_bf16_x4): New.
5927 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
5928 * config/arm/neon.md
5929 (neon_vld1_x4<mode>): New.
5930 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
5931 * config/arm/unspecs.md
5932 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
5934 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5936 * config/arm/arm_neon.h
5937 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
5938 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
5939 (vld1q_f16_x3, vld1q_f32_x3): New.
5940 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
5941 (vld1q_bf16_x3): New.
5942 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
5943 * config/arm/neon.md
5944 (neon_vld1_x3<mode>): New.
5945 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
5946 * config/arm/unspecs.md
5947 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
5949 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5951 * config/arm/arm_neon.h
5952 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
5953 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
5954 (vld1q_f16_x2, vld1q_f32_x2): New.
5955 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
5956 (vld1q_bf16_x2): New.
5957 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
5958 * config/arm/neon.md (vld1_x2<mode>): New.
5960 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5962 PR tree-optimization/113287
5963 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
5965 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5967 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
5968 * tree-vect-loop.cc (vect_transform_loop): Likewise.
5970 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5972 PR tree-optimization/113178
5973 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
5974 alternate exits.
5976 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5978 PR tree-optimization/113237
5979 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
5980 existing LCSSA variable for exit when all exits are early break.
5982 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5984 PR tree-optimization/113137
5985 PR tree-optimization/113136
5986 PR tree-optimization/113172
5987 PR tree-optimization/113178
5988 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5989 Maintain PHIs on inverted loops.
5990 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
5991 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
5992 latch.
5993 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
5995 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5997 PR tree-optimization/113135
5998 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
5999 dependency analysis.
6001 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
6003 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
6004 diagnostics class member name for abort of error.
6006 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
6008 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
6009 format string to %s argument.
6011 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
6012 Jakub Jelinek <jakub@redhat.com>
6014 PR middle-end/113182
6015 * varasm.cc (process_pending_assemble_externals,
6016 assemble_external_libcall): Use targetm.strip_name_encoding
6017 before calling get_identifier.
6019 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6021 PR target/113196
6022 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
6023 New member variable.
6024 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
6025 Declare.
6026 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
6027 * config/aarch64/aarch64-simd.md
6028 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
6029 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
6030 zip2 for zero-extends to...
6031 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
6032 instruction. Fix big-endian handling.
6033 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
6034 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
6035 zip1 for zero-extends to...
6036 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
6037 Fix big-endian handling.
6038 (*aarch64_zip1_uxtl): New pattern.
6039 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
6040 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
6041 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
6042 (aarch64_gen_shareable_zero): Use it.
6043 (aarch64_split_simd_shift_p): New function.
6045 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6047 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
6048 (function_beg_insn): New macro.
6049 * function.cc (expand_function_start): Initialize function_beg_insn.
6051 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6053 PR target/112989
6054 * config/aarch64/aarch64-sve-builtins.h
6055 (function_builder::m_overload_names): Replace with...
6056 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
6057 new global.
6058 (add_overloaded_function): Update accordingly, using get_identifier
6059 to get a GGC-friendly record of the name.
6061 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
6063 PR target/112989
6064 * config/aarch64/aarch64-sve-builtins.def: Don't include
6065 aarch64-sve-builtins-sme.def.
6066 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
6067 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
6068 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
6069 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
6070 requires AARCH64_FL_SME2.
6071 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
6072 AARCH64_FL_SME adjustment here.
6073 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
6074 include SME intrinsics.
6075 (sme_function_groups): New array.
6076 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
6077 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
6079 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6081 PR target/113281
6082 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
6083 (struct cpu_vector_cost): Add regmove struct.
6084 (get_vector_costs): Export as global.
6085 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
6086 (costs::add_stmt_cost): Ditto.
6087 * config/riscv/riscv.cc (get_common_costs): Export global function.
6089 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6091 PR tree-optimization/113334
6092 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
6093 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
6094 to determine if number should be extended by all ones rather than zero
6095 extended.
6097 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6099 PR tree-optimization/113330
6100 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
6101 too large size.
6103 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6105 PR tree-optimization/113323
6106 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
6107 check for lhs being large/huge _BitInt not in m_names.
6109 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6111 PR tree-optimization/113316
6112 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
6113 uninitialized large/huge _BitInt arguments to calls.
6115 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6117 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
6118 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
6119 CEIL (TYPE_PRECISION (t), limb_prec).
6120 (bitint_large_huge::handle_cast): Likewise.
6122 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
6124 PR sanitizer/113284
6125 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6126 Use assemble_function_label_final () for Power ELF V1 ABI.
6127 * output.h (assemble_function_label_final): New function.
6128 * varasm.cc (assemble_function_label_raw): Use
6129 assemble_function_label_final ().
6130 (assemble_function_label_final): New function.
6132 2024-01-12 Richard Biener <rguenther@suse.de>
6134 PR middle-end/113344
6135 * match.pd ((double)float CMP (double)float -> float CMP float):
6136 Perform result type check only for vectors.
6137 * fold-const.cc (fold_binary_loc): Likewise.
6139 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6141 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
6142 (usdot_prod<mode>): Ditto.
6143 (sdot_prod<mode>): Ditto.
6144 (udot_prod<mode>): Ditto.
6146 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6148 PR target/113288
6149 * config/i386/i386-c.cc (ix86_target_macros_internal):
6150 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
6152 2024-01-12 Richard Biener <rguenther@suse.de>
6154 PR target/112280
6155 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
6156 Do not generate code when d.testing_p.
6158 2024-01-12 liuhongt <hongtao.liu@intel.com>
6160 PR target/113039
6161 * doc/invoke.texi (fcf-protection=): Update documents.
6163 2024-01-12 Pan Li <pan2.li@intel.com>
6165 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
6166 comments of predicate func riscv_v_ext_mode_p.
6168 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
6170 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
6171 Modify ABI-name length of vfloat16m8_t
6173 2024-01-12 Li Wei <liwei@loongson.cn>
6175 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
6176 Adjust.
6178 2024-01-12 Li Wei <liwei@loongson.cn>
6180 * config/loongarch/loongarch.md (add<mode>3): Removed.
6181 (*addsi3): New.
6182 (addsi3): Ditto.
6183 (adddi3): Ditto.
6184 (*addsi3_extended): Removed.
6185 (addsi3_extended): New.
6187 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
6189 * config/riscv/thead.md: Add limits for splits.
6191 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6193 PR middle-end/113322
6194 * expr.cc (do_store_flag): Don't try single bit tests with
6195 comparison on vector types.
6197 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6199 PR tree-optimization/113301
6200 * match.pd (`1/x`): Delay signed case until late.
6202 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6204 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
6205 and -msp8 to...
6206 (AVR Internal Options): ...this new @subsubsection.
6208 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
6210 PR rtl-optimization/112918
6211 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
6212 (in_class_p): Restrict condition for narrowing class in case of
6213 allow_all_reload_class_changes_p.
6214 (process_alt_operands): Try to match operand without and with
6215 narrowing reg class. Discourage narrowing the class. Finish insn
6216 matching only if there is no class narrowing.
6217 (curr_insn_transform): Pass true to in_class_p for reg operand win.
6219 2024-01-11 Richard Biener <rguenther@suse.de>
6221 PR tree-optimization/112505
6222 * tree-vect-loop.cc (vectorizable_induction): Reject
6223 bit-precision induction.
6225 2024-01-11 Richard Biener <rguenther@suse.de>
6227 PR tree-optimization/113126
6228 * match.pd ((double)float CMP (double)float -> float CMP float):
6229 Make sure the boolean type is the same.
6230 * fold-const.cc (fold_binary_loc): Likewise.
6232 2024-01-11 Richard Biener <rguenther@suse.de>
6234 PR tree-optimization/112636
6235 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
6236 estimate_numbers_of_iterations before querying
6237 get_max_loop_iterations_int.
6238 (pass_ch::execute): Initialize SCEV and loops appropriately.
6240 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6242 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
6243 Reduced Tiny.
6244 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
6245 * doc/extend.texi (AVR Variable Attributes): Improve documentation
6246 of io, io_low and address attributes.
6247 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
6248 * doc/avr-mmcu.texi: Rebuild.
6250 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
6252 PR target/113233
6253 * config/loongarch/genopts/loongarch.opt.in: Mark options with
6254 the "Save" property.
6255 * config/loongarch/loongarch.opt: Same.
6256 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
6257 according to la_target.
6258 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
6259 RESTORE} for the la_target structure; Rename option conditions
6260 to have the same "la_" prefix.
6261 * config/loongarch/loongarch.h: Same.
6263 2024-01-11 Pan Li <pan2.li@intel.com>
6265 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
6266 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
6268 2024-01-11 Alex Coplan <alex.coplan@arm.com>
6270 PR target/113077
6271 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
6272 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
6273 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
6274 synthesize these if needed. Update caller ...
6275 (ldp_bb_info::fuse_pair): ... here.
6276 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6277 and either insn is frame-related.
6278 (find_trailing_add): Punt on frame-related insns.
6279 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6280 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6282 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
6284 * config/mips/mips.cc (mips_start_function_definition):
6285 Add ATTRIBUTE_UNUSED.
6287 2024-01-11 Richard Biener <rguenther@suse.de>
6289 PR middle-end/112740
6290 * expr.cc (store_constructor): Check the integer vector
6291 mask has a single bit per element before using sign-extension
6292 to expand an uniform vector.
6294 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6296 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6297 preempt VLS on unknown NITERS loop.
6299 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
6301 * doc/invoke.texi: Add -mevex512.
6303 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
6305 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6306 (*nor<mode>3): Likewise.
6307 (nor<mode>3): Likewise.
6308 (*negsi2_extended): New template.
6309 (*<optab>si3_internal): Likewise.
6310 (*one_cmplsi2_internal): Likewise.
6311 (*norsi3_internal): Likewise.
6312 (*<optab>nsi_internal): Likewise.
6313 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6314 modified bit operation to make the optimization work.
6316 2024-01-11 liuhongt <hongtao.liu@intel.com>
6318 PR target/104401
6319 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6321 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6323 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6324 (get_vector_costs): Ditto.
6325 (riscv_builtin_vectorization_cost): Ditto.
6327 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6329 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6331 2024-01-10 Antoni Boucher <bouanto@zoho.com>
6333 PR jit/111396
6334 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6335 ipa_free_size_summary.
6336 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6337 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6338 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6339 * ipa-prop.h (ipa_prop_cc_finalize): New function.
6340 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6341 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6342 ipa_sra_cc_finalize): New functions.
6343 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6344 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6345 ipa_sra_cc_finalize
6346 Include ipa-utils.h.
6348 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
6350 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6351 (th_int_get_save_adjustment): Likewise.
6352 (th_int_adjust_cfi_prologue): Likewise.
6353 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6354 (TH_INT_INTERRUPT): New macro.
6355 (riscv_expand_prologue): Add the processing of XTheadInt.
6356 (riscv_expand_epilogue): Likewise.
6357 * config/riscv/riscv.h (BITSET_P): Moved to here.
6358 * config/riscv/riscv.md: New unspec.
6359 * config/riscv/thead.cc (th_int_get_mask): New function.
6360 (th_int_get_save_adjustment): Likewise.
6361 (th_int_adjust_cfi_prologue): Likewise.
6362 * config/riscv/thead.md (th_int_push): New pattern.
6363 (th_int_pop): new pattern.
6365 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6367 PR tree-optimization/112468
6368 * doc/sourcebuild.texi: Document ifn_copysign.
6369 * match.pd: Only apply transformation if target supports the IFN.
6371 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
6373 PR tree-optimization/112581
6374 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6375 mark_ssa_maybe_undefs.
6376 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6377 variables can not be reassociated.
6378 (init_range_entry): Check for uninitialized variables too.
6379 (init_reassoc): Call mark_ssa_maybe_undefs.
6381 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
6383 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6384 Also handle sign extension.
6386 2024-01-10 Alex Coplan <alex.coplan@arm.com>
6388 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6389 to 0.
6390 (-mlate-ldp-fusion): Likewise.
6392 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6394 PR tree-optimization/113287
6395 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6396 instead of using BRANCH_EDGE to determine true edge.
6398 2024-01-10 Richard Biener <rguenther@suse.de>
6400 PR tree-optimization/113078
6401 * tree-vect-loop.cc (check_reduction_path): Canonicalize
6402 .COND_SUB to .COND_ADD.
6404 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6406 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6407 Handle prefix mappings before calling find_opt.
6408 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6409 "-fno-"-prefixed command-line option.
6410 * opts-common.cc (get_option_prefix_remapping): New.
6411 * opts.h (get_option_prefix_remapping): New decl.
6413 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6415 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6416 m_urlifier to pp_output_formatted_text.
6417 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6418 (obstack_append_string): New overload, taking a length.
6419 (urlify_quoted_string): Pass in an obstack ptr, rather than using
6420 that of the pp's buffer. Generalize to handle trailing text in
6421 the buffer beyond the run of quoted text.
6422 (class quoting_info): New.
6423 (on_begin_quote): New.
6424 (on_end_quote): New.
6425 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6426 it to calls to on_begin_quote and on_end_quote.
6427 (struct auto_obstack): New.
6428 (quoting_info::handle_phase_3): New.
6429 (pp_output_formatted_text): Add urlifier param. Use it if there
6430 is deferred urlification. Delete m_quotes.
6431 (selftest::pp_printf_with_urlifier): Pass urlifier to
6432 pp_output_formatted_text.
6433 (selftest::test_urlification): Update results for the existing
6434 case of quoted text stradding chunks; add more such test cases.
6435 * pretty-print.h (class quoting_info): New forward decl.
6436 (chunk_info::m_quotes): New field.
6437 (pp_output_formatted_text): Add optional urlifier param.
6439 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6441 * pretty-print.cc (selftest::test_pp_format): Add selftest
6442 coverage for numbered args.
6444 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6446 PR tree-optimization/113144
6447 PR tree-optimization/113145
6448 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6449 Update all BB that the original exits dominated.
6451 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
6453 * dwarf2out.cc (modified_type_die): Extend the support of reverse
6454 storage order to enumeration types if -gstrict-dwarf is not passed.
6455 (gen_enumeration_type_die): Add REVERSE parameter and generate the
6456 DIE immediately after the existing one if it is true.
6457 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6458 call to gen_enumeration_type_die.
6459 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6460 first recursive call as well as the call to gen_tagged_type_die.
6461 (gen_type_die): Add REVERSE parameter and pass it in the call to
6462 gen_type_die_with_usage.
6464 2024-01-10 Jakub Jelinek <jakub@redhat.com>
6466 PR tree-optimization/113120
6467 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6468 with root->size TYPE_PRECISION don't build anything new.
6469 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6470 rather than build_nonstandard_integer_type.
6472 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
6474 * config/i386/i386.opt: Adjust document.
6475 * doc/invoke.texi: Add description for
6476 -mapx-inline-asm-use-gpr32.
6478 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6480 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6481 (avg<v_double_trunc>3_floor): New pattern.
6482 (<u>avg<v_double_trunc>3_ceil): Remove.
6483 (avg<v_double_trunc>3_ceil): New pattern.
6484 (uavg<mode>3_floor): Ditto.
6485 (uavg<mode>3_ceil): Ditto.
6486 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6487 (enum insn_type): Ditto.
6488 * config/riscv/riscv-v.cc: Ditto.
6489 * config/riscv/vector-iterators.md (ashiftrt): Remove.
6490 (ASHIFTRT): Ditto.
6491 * config/riscv/vector.md: Add VLS modes.
6493 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6495 PR target/111480
6496 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6497 (vczlsbb_char): New int attribute.
6498 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6499 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6500 (*vctzlsbb_zext_<mode>): Rename to ...
6501 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6502 cover vclzlsbb.
6504 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6506 PR target/112606
6507 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6508 of the last argument from altivec_register_operand to any_operand. If
6509 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6510 otherwise if it doesn't satisfy altivec_register_operand, force it to
6511 REG using copy_to_mode_reg.
6513 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6515 PR middle-end/113100
6516 * builtins.cc (expand_builtin_stack_address): Guard stack point
6517 adjustment with SPARC_STACK_BOUNDARY_HACK.
6519 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6521 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6522 argument string definitions.
6523 * config/loongarch/loongarch-str.h: Same.
6524 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6525 as aliases to -mexplicit-relocs={always,none}
6526 * config/loongarch/loongarch.opt: Regenerate.
6527 * config/loongarch/loongarch.cc: Same.
6529 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6531 * config/loongarch/loongarch-def.h: Define constants with
6532 enums instead of Macros.
6534 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6536 * config/loongarch/genopts/loongarch-strings: Rename.
6537 * config/loongarch/genopts/loongarch.opt.in: Same.
6538 * config/loongarch/loongarch-cpu.cc: Same.
6539 * config/loongarch/loongarch-def.cc: Same.
6540 * config/loongarch/loongarch-def.h: Same.
6541 * config/loongarch/loongarch-opts.cc: Same.
6542 * config/loongarch/loongarch-opts.h: Same.
6543 * config/loongarch/loongarch-str.h: Same.
6544 * config/loongarch/loongarch.opt: Same.
6546 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6548 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6549 variable with the common la_ prefix.
6550 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6551 flags as saved using TargetVariable.
6552 * config/loongarch/loongarch.opt: Same.
6553 * config/loongarch/loongarch-def.h: Define evolution_set to
6554 mark changes to the -march default.
6555 * config/loongarch/loongarch-driver.cc: Same.
6556 * config/loongarch/loongarch-opts.cc: Same.
6557 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6558 conditions around the la_target structure.
6559 * config/loongarch/loongarch.cc: Same.
6560 * config/loongarch/loongarch.md: Same.
6561 * config/loongarch/loongarch-builtins.cc: Same.
6562 * config/loongarch/loongarch-c.cc: Same.
6563 * config/loongarch/lasx.md: Same.
6564 * config/loongarch/lsx.md: Same.
6565 * config/loongarch/sync.md: Same.
6567 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
6569 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6570 no less.
6572 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
6574 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6576 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6578 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6579 restart_loop.
6580 (vectorizable_live_operation): Likewise.
6582 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6584 PR tree-optimization/113199
6585 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6586 BIT_FIELD_REF.
6588 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6590 PR target/113270
6591 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6592 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6593 GTY(()) declaration before the definition, drop GTY(()) drom the
6594 definition.
6596 2024-01-09 Richard Biener <rguenther@suse.de>
6598 PR tree-optimization/113026
6599 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6600 redundant and wrong niter bound setting. Move niter
6601 bound adjustment down.
6603 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6605 PR middle-end/113163
6606 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6607 Reject non-linear inductions that aren't supported.
6609 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6611 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6612 left shift implementation strategies.
6613 (arc_shift_info): Type for each entry of the shift strategy table.
6614 (arc_shift_context_idx): Return a integer value for each code
6615 generation context, used as an index
6616 (arc_ashl_alg): Table indexed by context and shifted bit count.
6617 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6618 left shift implementation.
6619 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6620 provide accurate costs, when optimizing for speed or size.
6622 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6624 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6626 2024-01-09 Julian Brown <julian@codesourcery.com>
6628 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6629 processed out before gimplification.
6630 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6631 * tree.def (OMP_ARRAY_SECTION): New tree code.
6633 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6635 PR tree-optimization/113210
6636 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6637 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6638 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6639 minus 1.
6641 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
6643 PR rtl-optimization/113140
6644 * reorg.cc (fill_slots_from_thread): If we are to branch after the
6645 last instruction of the function, create an end label.
6647 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6648 Hongtao Liu <hongtao.liu@intel.com>
6650 PR target/112992
6651 * config/i386/i386-expand.cc
6652 (ix86_convert_const_wide_int_to_broadcast): Allow call to
6653 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6654 (ix86_broadcast_from_constant): Revert recent change; Return a
6655 suitable MEMREF independently of mode/target combinations.
6656 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6657 to decide whether expansion is possible/preferrable. Only try
6658 forcing DImode constants to memory (and trying again) if calling
6659 ix86_expand_vector_init_duplicate fails with an DImode immediate
6660 constant.
6661 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6662 V4SImode for suitable immediate constants.
6663 <case E_V4DImode>: Try using V8SImode for suitable constants.
6664 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6665 <case E_V2HImode>: Likewise.
6666 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6667 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6668 <label widen>: Handle CONT_INTs via simplify_binary_operation.
6669 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6670 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6671 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6672 (ix86_expand_vector_init): Move try using a broadcast for all_same
6673 with ix86_expand_vector_init_duplicate before using constant pool.
6675 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6677 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6679 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6681 * config/arm/arm-cpus.in (cortex-m52): New cpu.
6682 * config/arm/arm-tables.opt: Regenerate.
6683 * config/arm/arm-tune.md: Regenerate.
6685 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
6687 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6688 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6689 (@vec_concatz<mode>): New insn pattern.
6690 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6691 Handle VALS containing two vectors.
6693 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6695 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6696 (vundefined): Ditto.
6698 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
6700 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6701 Add new function_base for crypto vector.
6702 (class bitmanip): Ditto.
6703 (class b_reverse):Ditto.
6704 (class vwsll): Ditto.
6705 (class clmul): Ditto.
6706 (class vg_nhab): Ditto.
6707 (class crypto_vv):Ditto.
6708 (class crypto_vi):Ditto.
6709 (class vaeskf2_vsm3c):Ditto.
6710 (class vsm3me): Ditto.
6711 (BASE): Add BASE declaration for crypto vector.
6712 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6713 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6714 Add crypto vector intrinsic definition.
6715 (vbrev): Ditto.
6716 (vclz): Ditto.
6717 (vctz): Ditto.
6718 (vwsll): Ditto.
6719 (vandn): Ditto.
6720 (vbrev8): Ditto.
6721 (vrev8): Ditto.
6722 (vrol): Ditto.
6723 (vror): Ditto.
6724 (vclmul): Ditto.
6725 (vclmulh): Ditto.
6726 (vghsh): Ditto.
6727 (vgmul): Ditto.
6728 (vaesef): Ditto.
6729 (vaesem): Ditto.
6730 (vaesdf): Ditto.
6731 (vaesdm): Ditto.
6732 (vaesz): Ditto.
6733 (vaeskf1): Ditto.
6734 (vaeskf2): Ditto.
6735 (vsha2ms): Ditto.
6736 (vsha2ch): Ditto.
6737 (vsha2cl): Ditto.
6738 (vsm4k): Ditto.
6739 (vsm4r): Ditto.
6740 (vsm3me): Ditto.
6741 (vsm3c): Ditto.
6742 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6743 Add new function_shape for crypto vector.
6744 (struct crypto_vi_def): Ditto.
6745 (struct crypto_vv_no_op_type_def): Ditto.
6746 (SHAPE): Add SHAPE declaration of crypto vector.
6747 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6748 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6749 Add new data type for crypto vector.
6750 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6751 (vuint32mf2_t): Ditto.
6752 (vuint32m1_t): Ditto.
6753 (vuint32m2_t): Ditto.
6754 (vuint32m4_t): Ditto.
6755 (vuint32m8_t): Ditto.
6756 (vuint64m1_t): Ditto.
6757 (vuint64m2_t): Ditto.
6758 (vuint64m4_t): Ditto.
6759 (vuint64m8_t): Ditto.
6760 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6761 Add new data struct for crypto vector.
6762 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6763 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6764 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6766 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
6768 PR sanitizer/113251
6769 * varasm.cc (assemble_function_label_raw): Do not call
6770 asan_function_start () without the current function.
6772 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6774 PR target/113225
6775 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
6776 extern and kernel_helper attributed function decls.
6778 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6780 * btfout.cc (output_btf_strs): Changed.
6782 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6784 * config/gcn/mkoffload.cc (main): Handle gfx1100
6785 when setting the default XNACK.
6787 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6789 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6790 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6791 (ASM_SPEC): Handle gfx1100.
6792 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6793 (enum gcn_isa): Add ISA_RDNA3.
6794 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6795 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6796 * config/gcn/gcn.cc (gcn_option_override,
6797 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6798 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6799 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6800 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6801 with gfx1100.
6802 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6803 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6804 __gfx1100__.
6805 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6806 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6807 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6808 (isa_has_combined_avgprs, main): Handle gfx1100.
6809 * config/gcn/t-omp-device (isa): Add gfx1100.
6811 2024-01-08 Richard Biener <rguenther@suse.de>
6813 * doc/invoke.texi (-mmovbe): Clarify.
6815 2024-01-08 Richard Biener <rguenther@suse.de>
6817 PR tree-optimization/113026
6818 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6819 Avoid an epilog in more cases.
6820 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
6821 epilogues niter upper bounds and estimates.
6823 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6825 PR tree-optimization/113228
6826 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
6828 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6830 PR tree-optimization/113120
6831 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
6832 large _BitInt zero INTEGER_CST PHI argument.
6834 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6836 PR tree-optimization/113119
6837 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
6838 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
6839 is before REALPART_EXPR.
6841 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
6843 PR target/112952
6844 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
6845 range when diagnosing attribute "io" and "io_low" are out of range.
6846 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
6847 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
6848 in contexts other than static storage.
6849 (avr_asm_output_aligned_decl_common): Move output of decls with
6850 attribute "address", "io", and "io_low" to...
6851 (avr_output_addr_attrib): ...this new function.
6852 (avr_asm_asm_output_aligned_bss): Remove output for decls with
6853 attribute "address", "io", and "io_low".
6854 (avr_encode_section_info): Rectify handling of decls with attribute
6855 "address", "io", and "io_low".
6857 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6859 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
6860 (elf_flags): Remove XNACK from the default value.
6861 (main): Set a default XNACK according to the arch.
6863 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6865 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
6866 (process_asm): Don't count avgprs.
6868 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
6870 * config/i386/i386.opt: Add supported sub-features.
6871 * doc/extend.texi: Add description for target attribute.
6873 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
6875 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
6877 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
6878 Uros Bizjak <ubizjak@gmail.com>
6880 PR target/113231
6881 * config/i386/i386-features.cc (compute_convert_gain): Include
6882 the overhead of explicit load and store (movd) instructions when
6883 converting non-store scalar operations with memory destinations.
6884 Various indentation whitespace fixes.
6886 2024-01-07 Tamar Christina <tamar.christina@arm.com>
6888 * config/arm/neon.md (cbranch<mode>4): New.
6890 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6892 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
6894 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
6896 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
6898 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6900 PR target/113248
6901 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
6902 Update the MAX_SEW.
6904 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6906 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
6907 (variable_vectorized_p): Teach loop invariant.
6908 (has_unexpected_spills_p): Ditto.
6910 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6912 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
6913 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
6914 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
6916 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
6918 PR target/113104
6919 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
6920 (aarch64-vect-compare-costs): ...this.
6921 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
6922 Replace with...
6923 (-param=aarch64-vect-compare-costs=): ...this new param.
6924 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
6925 Don't disable it when vectorizing for Advanced SIMD only.
6926 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
6927 whenever aarch64_vect_compare_costs is true.
6929 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
6931 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
6932 Modify the method of determining the memory offset of [x]vld/[x]vst.
6933 (lasx_mxst_<lasxfmt_f>): Likewise.
6934 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
6935 (loongarch_address_insns): Likewise.
6936 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
6937 (lsx_st_<lsxfmt_f>): Likewise.
6938 * config/loongarch/predicates.md (aq10b_operand): Likewise.
6939 (aq10h_operand): Likewise.
6940 (aq10w_operand): Likewise.
6941 (aq10d_operand): Likewise.
6943 2024-01-05 Alex Coplan <alex.coplan@arm.com>
6945 PR target/113217
6946 * config/aarch64/aarch64-ldp-fusion.cc
6947 (ldp_bb_info::try_fuse_pair): If the second access can throw,
6948 narrow the move range to exactly that insn.
6950 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6952 * asan.cc (asan_function_start): Drop switch_to_section ().
6953 (asan_emit_stack_protection): Set .LASANPC alignment.
6954 * config/i386/i386.cc: Use assemble_function_label_raw ()
6955 instead of ASM_OUTPUT_LABEL ().
6956 * config/s390/s390.cc (s390_asm_output_function_label):
6957 Likewise.
6958 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
6959 * final.cc (final_start_function_1): Drop
6960 asan_function_start ().
6961 * output.h (assemble_function_label_raw): New function.
6962 * varasm.cc (assemble_function_label_raw): Likewise.
6964 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6966 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
6967 Use ASM_OUTPUT_FUNCTION_LABEL ().
6968 * config/alpha/alpha.cc (alpha_start_function): Likewise.
6969 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6970 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
6971 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6972 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6973 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
6974 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6975 * config/ia64/ia64.cc (ia64_start_function): Likewise.
6976 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
6977 Likewise.
6978 * config/microblaze/microblaze.cc (microblaze_function_prologue):
6979 Likewise.
6980 * config/mips/mips.cc (mips_start_unique_function): Return the
6981 tree.
6982 (mips_start_function_definition): Use
6983 ASM_OUTPUT_FUNCTION_LABEL ().
6984 (mips_finish_stub): Pass the tree to
6985 mips_start_function_definition ().
6986 (mips16_build_function_stub): Likewise.
6987 (mips16_build_call_stub): Likewise.
6988 (mips_output_function_prologue): Likewise.
6989 * config/pa/pa.cc (pa_output_function_label): Use
6990 ASM_OUTPUT_FUNCTION_LABEL ().
6991 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
6992 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6993 Likewise.
6994 (rs6000_xcoff_declare_function_name): Likewise.
6996 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6998 PR tree-optimization/113201
6999 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
7000 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
7002 2024-01-05 Jakub Jelinek <jakub@redhat.com>
7004 PR tree-optimization/90693
7005 * tree-ssa-math-opts.cc (match_single_bit_test): If
7006 tree_expr_nonzero_p (arg), remember it in the second argument to
7007 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
7008 arg ^ (arg - 1) > arg - 1.
7009 * internal-fn.cc (expand_POPCOUNT): If second argument to
7010 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
7011 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
7013 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
7015 * config/riscv/riscv-v.cc (expand_load_store):
7016 Remove `value`.
7017 (expand_cond_len_op): Ditto.
7018 (expand_gather_scatter): Ditto.
7019 (expand_lanes_load_store): Ditto.
7020 (expand_fold_extract_last): Ditto.
7022 2024-01-05 Pan Li <pan2.li@intel.com>
7024 Revert:
7025 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7027 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7028 Add new function_base for crypto vector.
7029 (class bitmanip): Ditto.
7030 (class b_reverse):Ditto.
7031 (class vwsll): Ditto.
7032 (class clmul): Ditto.
7033 (class vg_nhab): Ditto.
7034 (class crypto_vv):Ditto.
7035 (class crypto_vi):Ditto.
7036 (class vaeskf2_vsm3c):Ditto.
7037 (class vsm3me): Ditto.
7038 (BASE): Add BASE declaration for crypto vector.
7039 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7040 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7041 Add crypto vector intrinsic definition.
7042 (vbrev): Ditto.
7043 (vclz): Ditto.
7044 (vctz): Ditto.
7045 (vwsll): Ditto.
7046 (vandn): Ditto.
7047 (vbrev8): Ditto.
7048 (vrev8): Ditto.
7049 (vrol): Ditto.
7050 (vror): Ditto.
7051 (vclmul): Ditto.
7052 (vclmulh): Ditto.
7053 (vghsh): Ditto.
7054 (vgmul): Ditto.
7055 (vaesef): Ditto.
7056 (vaesem): Ditto.
7057 (vaesdf): Ditto.
7058 (vaesdm): Ditto.
7059 (vaesz): Ditto.
7060 (vaeskf1): Ditto.
7061 (vaeskf2): Ditto.
7062 (vsha2ms): Ditto.
7063 (vsha2ch): Ditto.
7064 (vsha2cl): Ditto.
7065 (vsm4k): Ditto.
7066 (vsm4r): Ditto.
7067 (vsm3me): Ditto.
7068 (vsm3c): Ditto.
7069 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7070 Add new function_shape for crypto vector.
7071 (struct crypto_vi_def): Ditto.
7072 (struct crypto_vv_no_op_type_def): Ditto.
7073 (SHAPE): Add SHAPE declaration of crypto vector.
7074 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7075 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7076 Add new data type for crypto vector.
7077 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7078 (vuint32mf2_t): Ditto.
7079 (vuint32m1_t): Ditto.
7080 (vuint32m2_t): Ditto.
7081 (vuint32m4_t): Ditto.
7082 (vuint32m8_t): Ditto.
7083 (vuint64m1_t): Ditto.
7084 (vuint64m2_t): Ditto.
7085 (vuint64m4_t): Ditto.
7086 (vuint64m8_t): Ditto.
7087 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7088 Add new data struct for crypto vector.
7089 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7090 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7091 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7093 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7095 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7096 Add new function_base for crypto vector.
7097 (class bitmanip): Ditto.
7098 (class b_reverse):Ditto.
7099 (class vwsll): Ditto.
7100 (class clmul): Ditto.
7101 (class vg_nhab): Ditto.
7102 (class crypto_vv):Ditto.
7103 (class crypto_vi):Ditto.
7104 (class vaeskf2_vsm3c):Ditto.
7105 (class vsm3me): Ditto.
7106 (BASE): Add BASE declaration for crypto vector.
7107 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7108 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7109 Add crypto vector intrinsic definition.
7110 (vbrev): Ditto.
7111 (vclz): Ditto.
7112 (vctz): Ditto.
7113 (vwsll): Ditto.
7114 (vandn): Ditto.
7115 (vbrev8): Ditto.
7116 (vrev8): Ditto.
7117 (vrol): Ditto.
7118 (vror): Ditto.
7119 (vclmul): Ditto.
7120 (vclmulh): Ditto.
7121 (vghsh): Ditto.
7122 (vgmul): Ditto.
7123 (vaesef): Ditto.
7124 (vaesem): Ditto.
7125 (vaesdf): Ditto.
7126 (vaesdm): Ditto.
7127 (vaesz): Ditto.
7128 (vaeskf1): Ditto.
7129 (vaeskf2): Ditto.
7130 (vsha2ms): Ditto.
7131 (vsha2ch): Ditto.
7132 (vsha2cl): Ditto.
7133 (vsm4k): Ditto.
7134 (vsm4r): Ditto.
7135 (vsm3me): Ditto.
7136 (vsm3c): Ditto.
7137 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7138 Add new function_shape for crypto vector.
7139 (struct crypto_vi_def): Ditto.
7140 (struct crypto_vv_no_op_type_def): Ditto.
7141 (SHAPE): Add SHAPE declaration of crypto vector.
7142 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7143 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7144 Add new data type for crypto vector.
7145 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7146 (vuint32mf2_t): Ditto.
7147 (vuint32m1_t): Ditto.
7148 (vuint32m2_t): Ditto.
7149 (vuint32m4_t): Ditto.
7150 (vuint32m8_t): Ditto.
7151 (vuint64m1_t): Ditto.
7152 (vuint64m2_t): Ditto.
7153 (vuint64m4_t): Ditto.
7154 (vuint64m8_t): Ditto.
7155 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7156 Add new data struct for crypto vector.
7157 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7158 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7159 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7161 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7163 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7165 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
7167 PR tree-optimization/113186
7168 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
7169 Match `^` with the `==` for 1bit integral types.
7170 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
7171 integral types.
7173 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7175 * toplev.cc (general_init): Pass lang_mask to urlifier.
7177 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7179 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
7180 param.
7181 (diagnostic_context::make_option_url): Update for lang_mask param.
7182 * gcc-urlifier.cc: Include "opts.h" and "options.h".
7183 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
7184 (gcc_urlifier::m_lang_mask): New field.
7185 (doc_urls): Make static.
7186 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
7187 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7188 Look for an option by name before trying a binary search in
7189 doc_urls.
7190 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7191 (gcc_urlifier::get_url_suffix_for_option): New.
7192 (make_gcc_urlifier): Add lang_mask param.
7193 (selftest::gcc_urlifier_cc_tests): Update for above changes.
7194 Verify that a URL is found for "-fpack-struct".
7195 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
7196 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
7197 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
7198 to make_gcc_urlifier.
7199 * opts-diagnostic.h (get_option_url): Add lang_mask param.
7200 * opts.cc (get_option_html_page): Remove special-casing for
7201 analyzer and LTO.
7202 (get_option_url_suffix): New.
7203 (get_option_url): Reimplement.
7204 (selftest::test_get_option_html_page): Rename to...
7205 (selftest::test_get_option_url_suffix): ...this and update for
7206 above changes.
7207 (selftest::opts_cc_tests): Update for renaming.
7208 * opts.h: Include "rich-location.h".
7209 (get_option_url_suffix): New decl.
7211 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7213 * Makefile.in (ALL_OPT_URL_FILES): New.
7214 (GCC_OBJS): Add options-urls.o.
7215 (OBJS): Likewise.
7216 (OBJS-libcommon): Likewise.
7217 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
7218 inputs to opt-gather.awk.
7219 (options-urls.cc): New Makefile target.
7220 * opt-functions.awk (url_suffix): New function.
7221 (lang_url_suffix): New function.
7222 * options-urls-cc-gen.awk: New file.
7223 * opts.h (get_opt_url_suffix): New decl.
7225 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7227 * params.opt.urls: New file, autogenerated by
7228 regenerate-opt-urls.py.
7230 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7232 * common.opt.urls: New file, autogenerated by
7233 regenerate-opt-urls.py.
7234 * config/aarch64/aarch64.opt.urls: Likewise.
7235 * config/alpha/alpha.opt.urls: Likewise.
7236 * config/alpha/elf.opt.urls: Likewise.
7237 * config/arc/arc-tables.opt.urls: Likewise.
7238 * config/arc/arc.opt.urls: Likewise.
7239 * config/arm/arm-tables.opt.urls: Likewise.
7240 * config/arm/arm.opt.urls: Likewise.
7241 * config/arm/vxworks.opt.urls: Likewise.
7242 * config/avr/avr.opt.urls: Likewise.
7243 * config/bpf/bpf.opt.urls: Likewise.
7244 * config/c6x/c6x-tables.opt.urls: Likewise.
7245 * config/c6x/c6x.opt.urls: Likewise.
7246 * config/cris/cris.opt.urls: Likewise.
7247 * config/cris/elf.opt.urls: Likewise.
7248 * config/csky/csky.opt.urls: Likewise.
7249 * config/csky/csky_tables.opt.urls: Likewise.
7250 * config/darwin.opt.urls: Likewise.
7251 * config/dragonfly.opt.urls: Likewise.
7252 * config/epiphany/epiphany.opt.urls: Likewise.
7253 * config/fr30/fr30.opt.urls: Likewise.
7254 * config/freebsd.opt.urls: Likewise.
7255 * config/frv/frv.opt.urls: Likewise.
7256 * config/ft32/ft32.opt.urls: Likewise.
7257 * config/fused-madd.opt.urls: Likewise.
7258 * config/g.opt.urls: Likewise.
7259 * config/gcn/gcn.opt.urls: Likewise.
7260 * config/gnu-user.opt.urls: Likewise.
7261 * config/h8300/h8300.opt.urls: Likewise.
7262 * config/hpux11.opt.urls: Likewise.
7263 * config/i386/cygming.opt.urls: Likewise.
7264 * config/i386/cygwin.opt.urls: Likewise.
7265 * config/i386/djgpp.opt.urls: Likewise.
7266 * config/i386/i386.opt.urls: Likewise.
7267 * config/i386/mingw-w64.opt.urls: Likewise.
7268 * config/i386/mingw.opt.urls: Likewise.
7269 * config/i386/nto.opt.urls: Likewise.
7270 * config/ia64/ia64.opt.urls: Likewise.
7271 * config/ia64/ilp32.opt.urls: Likewise.
7272 * config/ia64/vms.opt.urls: Likewise.
7273 * config/iq2000/iq2000.opt.urls: Likewise.
7274 * config/linux-android.opt.urls: Likewise.
7275 * config/linux.opt.urls: Likewise.
7276 * config/lm32/lm32.opt.urls: Likewise.
7277 * config/loongarch/loongarch.opt.urls: Likewise.
7278 * config/lynx.opt.urls: Likewise.
7279 * config/m32c/m32c.opt.urls: Likewise.
7280 * config/m32r/m32r.opt.urls: Likewise.
7281 * config/m68k/ieee.opt.urls: Likewise.
7282 * config/m68k/m68k-tables.opt.urls: Likewise.
7283 * config/m68k/m68k.opt.urls: Likewise.
7284 * config/m68k/uclinux.opt.urls: Likewise.
7285 * config/mcore/mcore.opt.urls: Likewise.
7286 * config/microblaze/microblaze.opt.urls: Likewise.
7287 * config/mips/mips-tables.opt.urls: Likewise.
7288 * config/mips/mips.opt.urls: Likewise.
7289 * config/mips/sde.opt.urls: Likewise.
7290 * config/mmix/mmix.opt.urls: Likewise.
7291 * config/mn10300/mn10300.opt.urls: Likewise.
7292 * config/moxie/moxie.opt.urls: Likewise.
7293 * config/msp430/msp430.opt.urls: Likewise.
7294 * config/nds32/nds32-elf.opt.urls: Likewise.
7295 * config/nds32/nds32-linux.opt.urls: Likewise.
7296 * config/nds32/nds32.opt.urls: Likewise.
7297 * config/netbsd-elf.opt.urls: Likewise.
7298 * config/netbsd.opt.urls: Likewise.
7299 * config/nios2/elf.opt.urls: Likewise.
7300 * config/nios2/nios2.opt.urls: Likewise.
7301 * config/nvptx/nvptx-gen.opt.urls: Likewise.
7302 * config/nvptx/nvptx.opt.urls: Likewise.
7303 * config/openbsd.opt.urls: Likewise.
7304 * config/or1k/elf.opt.urls: Likewise.
7305 * config/or1k/or1k.opt.urls: Likewise.
7306 * config/pa/pa-hpux.opt.urls: Likewise.
7307 * config/pa/pa-hpux1010.opt.urls: Likewise.
7308 * config/pa/pa-hpux1111.opt.urls: Likewise.
7309 * config/pa/pa-hpux1131.opt.urls: Likewise.
7310 * config/pa/pa.opt.urls: Likewise.
7311 * config/pa/pa64-hpux.opt.urls: Likewise.
7312 * config/pdp11/pdp11.opt.urls: Likewise.
7313 * config/pru/pru.opt.urls: Likewise.
7314 * config/riscv/riscv.opt.urls: Likewise.
7315 * config/rl78/rl78.opt.urls: Likewise.
7316 * config/rpath.opt.urls: Likewise.
7317 * config/rs6000/476.opt.urls: Likewise.
7318 * config/rs6000/aix64.opt.urls: Likewise.
7319 * config/rs6000/darwin.opt.urls: Likewise.
7320 * config/rs6000/linux64.opt.urls: Likewise.
7321 * config/rs6000/rs6000-tables.opt.urls: Likewise.
7322 * config/rs6000/rs6000.opt.urls: Likewise.
7323 * config/rs6000/sysv4.opt.urls: Likewise.
7324 * config/rtems.opt.urls: Likewise.
7325 * config/rx/elf.opt.urls: Likewise.
7326 * config/rx/rx.opt.urls: Likewise.
7327 * config/s390/s390.opt.urls: Likewise.
7328 * config/s390/tpf.opt.urls: Likewise.
7329 * config/sh/sh.opt.urls: Likewise.
7330 * config/sh/superh.opt.urls: Likewise.
7331 * config/sol2.opt.urls: Likewise.
7332 * config/sparc/long-double-switch.opt.urls: Likewise.
7333 * config/sparc/sparc.opt.urls: Likewise.
7334 * config/stormy16/stormy16.opt.urls: Likewise.
7335 * config/v850/v850.opt.urls: Likewise.
7336 * config/vax/elf.opt.urls: Likewise.
7337 * config/vax/vax.opt.urls: Likewise.
7338 * config/visium/visium.opt.urls: Likewise.
7339 * config/vms/vms.opt.urls: Likewise.
7340 * config/vxworks-smp.opt.urls: Likewise.
7341 * config/vxworks.opt.urls: Likewise.
7342 * config/xtensa/elf.opt.urls: Likewise.
7343 * config/xtensa/uclinux.opt.urls: Likewise.
7344 * config/xtensa/xtensa.opt.urls: Likewise.
7345 * config/bfin/bfin.opt.urls: New file.
7347 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7349 * Makefile.in (OPT_URLS_HTML_DEPS): New.
7350 (regenerate-opt-urls): New target.
7351 (regenerate-opt-urls-unit-test): New target.
7352 * doc/options.texi (Option properties): Add UrlSuffix and
7353 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
7354 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7355 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7356 and Makefile.in's OPT_URLS_HTML_DEPS.
7357 (Anatomy of a Target Back End): Add
7358 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7359 * regenerate-opt-urls.py: New file.
7361 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7363 * diagnostic-format-sarif.cc
7364 (sarif_builder::make_logical_location_object): Convert to...
7365 (make_sarif_logical_location_object): ...this.
7366 (sarif_builder::set_any_logical_locs_arr): Update for above
7367 change.
7368 (sarif_builder::make_thread_flow_location_object): Call
7369 maybe_add_sarif_properties on each diagnostic_event.
7370 * diagnostic-format-sarif.h (class logical_location): New forward
7371 decl.
7372 (make_sarif_logical_location_object): New decl.
7373 * diagnostic-path.h (class sarif_object): New forward decl.
7374 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7376 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
7377 Patrick Lin <patrick@andestech.com>
7378 Rufus Chen <rufus@andestech.com>
7379 Monk Chiang <monk.chiang@sifive.com>
7381 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7382 with Nan-boxing value.
7383 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7385 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
7386 Jeff Law <jlaw@ventanamicro.com>
7388 PR rtl-optimization/104914
7389 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7390 a sign or zero extension is only required if the modified field
7391 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
7392 targets, don't refer to the temporarily incorrectly extended value
7393 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7395 2024-01-04 Pan Li <pan2.li@intel.com>
7397 Revert:
7398 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7400 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7402 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7404 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7406 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
7408 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7409 offset of fcsr.
7411 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7413 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7414 (compute_nregs_for_mode): Refine LMUL.
7415 (max_number_of_live_regs): Ditto.
7416 (compute_estimated_lmul): Ditto.
7417 (has_unexpected_spills_p): Ditto.
7419 2024-01-04 Li Wei <liwei@loongson.cn>
7421 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7422 Remove useless forward declaration.
7423 (loongarch_is_even_extraction): Remove useless forward declaration.
7424 (loongarch_try_expand_lsx_vshuf_const): Removed.
7425 (loongarch_expand_vec_perm_const_1): Merged.
7426 (loongarch_is_double_duplicate): Removed.
7427 (loongarch_is_center_extraction): Ditto.
7428 (loongarch_is_reversing_permutation): Ditto.
7429 (loongarch_is_di_misalign_extract): Ditto.
7430 (loongarch_is_si_misalign_extract): Ditto.
7431 (loongarch_is_lasx_lowpart_extract): Ditto.
7432 (loongarch_is_op_reverse_perm): Ditto.
7433 (loongarch_is_single_op_perm): Ditto.
7434 (loongarch_is_divisible_perm): Ditto.
7435 (loongarch_is_triple_stride_extract): Ditto.
7436 (loongarch_expand_vec_perm_const_2): Merged.
7437 (loongarch_expand_vec_perm_const): New.
7438 (loongarch_vectorize_vec_perm_const): Adjust.
7440 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
7442 * omp-general.cc: Fix comment typos and misplaced/confusing
7443 comments. Delete redundant include of omp-general.h.
7445 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7447 PR rtl-optimization/104914
7448 * config/mips/mips.md (insqisi_extended): New patterns.
7449 (inshisi_extended): Ditto.
7451 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7453 * config/mips/mips.cc (mips_insn_cost): New function.
7455 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7457 * config/mips/mips.md (perf_ratio): New attribute.
7459 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7461 PR target/113206
7462 PR target/113209
7463 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7464 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7465 blocks belong to infinite loop.
7466 (pre_vsetvl::emit_vsetvl): Remove fake edges.
7467 * config/riscv/t-riscv: Add a new include file.
7469 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7471 * config/riscv/vector.md: Fix indent.
7473 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7475 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7476 OMP_CLAUSE__SIMDUID_.
7477 * tree.cc (omp_clause_num_ops): Update position of entry for
7478 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7479 (omp_clause_code_name): Likewise.
7481 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7483 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7484 printing of FUNC_MAP/IND_FUNC_MAP labels.
7486 2024-01-03 Jakub Jelinek <jakub@redhat.com>
7488 * gcc.cc (process_command): Update copyright notice dates.
7489 * gcov-dump.cc (print_version): Ditto.
7490 * gcov.cc (print_version): Ditto.
7491 * gcov-tool.cc (print_version): Ditto.
7492 * gengtype.cc (create_file): Ditto.
7493 * doc/cpp.texi: Bump @copying's copyright year.
7494 * doc/cppinternals.texi: Ditto.
7495 * doc/gcc.texi: Ditto.
7496 * doc/gccint.texi: Ditto.
7497 * doc/gcov.texi: Ditto.
7498 * doc/install.texi: Ditto.
7499 * doc/invoke.texi: Ditto.
7501 2024-01-03 Xi Ruoyao <xry111@xry111.site>
7503 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7504 (fmin<mode>3): Likewise.
7505 (reduc_fmax_scal_<mode>3): New define_expand.
7506 (reduc_fmin_scal_<mode>3): Likewise.
7508 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7510 PR target/113112
7511 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7512 (max_number_of_live_regs): Ditto.
7513 (has_unexpected_spills_p): Ditto.
7515 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
7516 Jin Ma <jinma@linux.alibaba.com>
7517 Xianmiao Qu <cooper.qu@linux.alibaba.com>
7518 Christoph Müllner <christoph.muellner@vrull.eu>
7520 * config/riscv/vector.md:
7521 Use vector_length_operand for vsetvl patterns.
7523 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7525 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7526 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7528 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
7530 * config/aarch64/aarch64-tuning-flags.def
7531 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7532 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7533 * config/aarch64/aarch64.cc
7534 (aarch64_override_options_internal): Set
7535 param_fully_pipelined_fma according to tuning option.
7536 * config/aarch64/tuning_models/ampere1.h: Add
7537 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7538 * config/aarch64/tuning_models/ampere1a.h: Likewise.
7539 * config/aarch64/tuning_models/ampere1b.h: Likewise.
7541 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7543 * config/riscv/vector-crypto.md: Modify copyright year.
7545 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7547 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7549 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
7551 * config.in: Regenerate.
7552 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7553 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7554 Added TLS Le Relax support.
7555 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7556 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7557 * configure: Regenerate.
7558 * configure.ac: Check if binutils supports TLS le relax.
7560 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7562 * config/riscv/iterators.md: Add rotate insn name.
7563 * config/riscv/riscv.md: Add new insns name for crypto vector.
7564 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7565 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7566 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7568 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7570 PR target/113112
7571 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7572 pointer type liveness count.
7573 \f
7574 Copyright (C) 2024 Free Software Foundation, Inc.
7576 Copying and distribution of this file, with or without modification,
7577 are permitted in any medium without royalty provided the copyright
7578 notice and this notice are preserved.