| blob | 10fa4283430bbe7ecf471478756acb085b6bd20a |
1 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
3 * config.gcc (target_gtfiles): Change coreout to btfext-out.
4 (extra_objs): Change coreout to btfext-out.
5 * config/bpf/coreout.cc: Rename to btfext-out.cc.
6 * config/bpf/btfext-out.cc: Add.
7 * config/bpf/coreout.h: Rename to btfext-out.h.
8 * config/bpf/btfext-out.h: Add.
9 * config/bpf/core-builtins.cc: Change include.
10 * config/bpf/core-builtins.h: Change include.
11 * config/bpf/t-bpf: Accomodate renamed files.
13 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
15 PR target/113453
16 * config/bpf/bpf.cc (bpf_function_prologue): Define target
17 hook.
18 * config/bpf/coreout.cc (brf_ext_info_section)
19 (btf_ext_info): Move from coreout.h
20 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
21 (bpf_core_reloc): Rename to btf_ext_core_reloc.
22 (btf_ext): Add static variable.
23 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
24 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
25 (btf_ext_add_string, btf_funcinfo_type_callback)
26 (btf_add_func_info_for, btf_validate_funcinfo)
27 (btf_ext_info_len, output_btfext_func_info): Add function.
28 (output_btfext_header, bpf_core_reloc_add)
29 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
30 Change to support new structs.
31 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
32 Move and change in coreout.cc.
33 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
35 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
37 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
38 enabled by default for BPF.
39 (bpf_file_end): Call BTF deallocation.
40 (bpf_asm_init_sections): Correct condition.
41 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
42 deallocation.
43 (ctf_debuf_finish): Correct condition for calling
44 ctf_debug_finalize.
46 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
48 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
49 (traverse_btf_func_types): Define function.
50 * ctfc.h (funcs_traverse_callback): Typedef for function
51 prototype.
52 (traverse_btf_func_types): Add prototype.
54 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
56 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
58 2024-02-28 Richard Biener <rguenther@suse.de>
60 PR tree-optimization/113831
61 PR tree-optimization/108355
62 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
63 PR113831 fix.
65 2024-02-28 Richard Biener <rguenther@suse.de>
67 PR tree-optimization/114121
68 * tree-ssa-sccvn.h (vn_reference_s::offset,
69 vn_reference_s::max_size): New fields.
70 (vn_reference_insert_pieces): Adjust prototype.
71 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
72 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
73 size, allow using "don't know" state.
74 (vn_walk_cb_data::finish): Pass along offset/max_size.
75 (vn_reference_lookup_or_insert_for_pieces): Take offset and
76 max_size as argument and use it.
77 (vn_reference_lookup_3): Properly adjust offset and max_size
78 according to the adjusted ao_ref.
79 (vn_reference_lookup_pieces): Initialize offset and max_size.
80 (vn_reference_lookup): Likewise.
81 (vn_reference_lookup_call): Likewise.
82 (vn_reference_insert): Likewise.
83 (visit_reference_op_call): Likewise.
84 (vn_reference_insert_pieces): Take offset and max_size
85 as argument and use it.
87 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
89 PR tree-optimization/114075
90 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
91 point vectors
93 2024-02-28 Jakub Jelinek <jakub@redhat.com>
95 PR tree-optimization/114041
96 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
97 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
99 2024-02-28 Jakub Jelinek <jakub@redhat.com>
101 PR tree-optimization/113988
102 * stor-layout.h (bitwise_mode_for_size): Declare.
103 * stor-layout.cc (bitwise_mode_for_size): New function.
104 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
105 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
106 Use BITS_PER_UNIT instead of 8.
108 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
110 PR target/113871
111 * config/i386/mmx.md (V248FI): Add V2BF mode.
112 (V24FI_32): Ditto.
114 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
116 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
117 if either ref->offset is not byte aligned or ref->size is not known
118 to be equal to ref->max_size.
119 (maybe_trim_complex_store): Fix description.
120 (maybe_trim_constructor_store): Likewise.
121 (maybe_trim_partially_dead_store): Likewise.
123 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
125 * config/arm/mmintrin.h: Warn if this header is included without
126 defining __ENABLE_DEPRECATED_IWMMXT.
128 2024-02-27 Richard Biener <rguenther@suse.de>
130 PR tree-optimization/114074
131 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
132 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
133 Handle poly vs. non-poly multiplication correctly with respect
134 to undefined behavior on overflow.
136 2024-02-27 Jakub Jelinek <jakub@redhat.com>
138 PR rtl-optimization/114044
139 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
140 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
141 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
142 expand_PARITY): Declare.
143 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
144 expand_CTZ, expand_FFS, expand_PARITY): New functions.
145 (expand_POPCOUNT): Use expand_bitquery.
147 2024-02-27 Richard Biener <rguenther@suse.de>
149 PR tree-optimization/114081
150 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
151 Perform manual dominator update for prologue peeling.
152 (vect_do_peeling): Properly update dominators after adding the
153 prologue-around guard.
155 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
157 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
158 (mstrict-X): Tag as "Optimization".
160 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
162 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
163 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
165 2024-02-26 Jakub Jelinek <jakub@redhat.com>
166 H.J. Lu <hjl.tools@gmail.com>
168 PR rtl-optimization/113617
169 * varasm.cc (default_elf_select_rtx_section): For
170 references to private symbols in comdat sections
171 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
172 or .rodata.<comdat> comdat sections.
174 2024-02-26 Richard Biener <rguenther@suse.de>
176 PR tree-optimization/114099
177 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
178 Create and fill in a needed virtual LC PHI for the alternate
179 exits. Remove code dealing with that missing.
181 2024-02-26 Richard Biener <rguenther@suse.de>
183 PR tree-optimization/114068
184 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
185 New function.
186 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
187 on the main exit if needed. Remove band-aid for the case
188 it was missing.
190 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
192 PR target/114097
193 * config/i386/i386-options.cc (ix86_set_func_type): Check
194 interrupt instead of noreturn attribute.
196 2024-02-26 Jakub Jelinek <jakub@redhat.com>
198 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
199 !TARGET_64BIT.
201 2024-02-26 Jakub Jelinek <jakub@redhat.com>
203 PR tree-optimization/114090
204 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
205 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
206 types.
207 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
209 2024-02-26 Jakub Jelinek <jakub@redhat.com>
211 PR middle-end/114084
212 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
213 if all subtrees of var0 come from one of the op0 or op1 operands
214 and all subtrees of con0 come from the other one. Don't clear
215 variables which are never used afterwards.
217 2024-02-26 Richard Biener <rguenther@suse.de>
219 PR middle-end/114070
220 * genmatch.cc (parser::parse_c_expr): Do not record operand
221 lists but only mark operators used.
222 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
223 Properly guard the case of tcc_comparison changing the VEC_COND
224 value operand type.
226 2024-02-26 Jakub Jelinek <jakub@redhat.com>
228 PR target/114094
229 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
230 to printed instruction.
232 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
234 PR target/114098
235 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
236 __builtin_ia32_ldtilecfg.
237 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
238 * config/i386/i386-builtin.def (BDESC): Add
239 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
240 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
241 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
242 * config/i386/i386.md (ldtilecfg): New pattern.
243 (sttilecfg): Likewise.
245 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
247 PR tree-optimization/113205
248 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
249 the proposed layout if it does not allow a source partition with
250 layout 2 to keep that layout.
252 2024-02-24 Jakub Jelinek <jakub@redhat.com>
254 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
255 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
256 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
257 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
258 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
259 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
260 macros.
261 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
262 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
263 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
264 HOST_WIDE_INT_UC macros.
265 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
266 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
267 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
268 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
269 macros.
270 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
271 * config/i386/constraints.md (define_constraint "L"): Use
272 HOST_WIDE_INT_C macro.
273 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
274 macro.
275 (movl + movb peephole2): Likewise.
276 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
277 (const_32bit_mask): Likewise.
279 2024-02-24 Jakub Jelinek <jakub@redhat.com>
281 PR middle-end/114073
282 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
283 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
284 types like vector or complex types.
285 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
286 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
287 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
289 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
291 PR target/114028
292 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
293 Return false if inner mode is already Pmode.
294 (rvv_builder::is_all_same_sequence): New function.
295 (expand_vec_init): Emit broadcast if sequence is all same.
297 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
299 PR target/113613
300 * config/aarch64/aarch64-early-ra.cc
301 (early_ra::m_current_region): New member variable.
302 (early_ra::m_fpr_recency): Likewise.
303 (early_ra::start_new_region): Bump m_current_region.
304 (early_ra::allocate_colors): Prefer less recently used registers
305 in the event of a tie. Add a comment to explain why we prefer(ed)
306 higher-numbered registers.
307 (early_ra::find_oldest_color): Prefer less recently used registers
308 here too.
309 (early_ra::finalize_allocation): Update recency information for
310 allocated registers.
311 (early_ra::process_blocks): Initialize m_current_region and
312 m_fpr_recency.
314 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
316 PR target/113295
317 * config/aarch64/aarch64-early-ra.cc
318 (early_ra::test_strictness): New enum.
319 (early_ra::is_chain_candidate): Add a strictness parameter to
320 control whether only correctness matters, or whether both correctness
321 and heuristics should be used. Handle multiple levels of equivalence.
322 (early_ra::find_related_start): Update call accordingly.
323 (early_ra::strided_polarity_pref): Likewise.
324 (early_ra::form_chains): Likewise.
325 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
326 correctness mode rather than trying to inline the test.
328 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
330 PR target/113295
331 * config/aarch64/aarch64-early-ra.cc
332 (early_ra::find_related_start): Account for definitions by shared
333 registers when testing for a single register definition.
334 (early_ra::accumulate_defs): New function.
335 (early_ra::record_copy): If A shares B's register, fold A's
336 definition information into B's. Fold A's use information into B's.
338 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
340 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
341 if R_X86_64_CODE_6_GOTTPOFF is supported.
342 * config.in: Regenerated.
343 * configure: Likewise.
344 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
345 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
347 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
349 PR target/108120
350 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
351 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
353 2024-02-23 Jakub Jelinek <jakub@redhat.com>
355 PR rtl-optimization/114054
356 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
357 temp variable instead of target parameter for result.
359 2024-02-23 Jakub Jelinek <jakub@redhat.com>
361 PR tree-optimization/114040
362 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
363 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
364 probability from likely to unlikely. When handling the true true
365 store, first cast to limb_access_type and then to l's type.
367 2024-02-23 Richard Biener <rguenther@suse.de>
369 PR target/90785
370 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
372 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
374 PR other/109668
375 * config/riscv/arch-canonicalize: Move to python3
376 * config/riscv/multilib-generator: Likewise
378 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
380 * doc/invoke.texi: Document -mcpu.
382 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
384 * configure: Regenerate.
385 * configure.ac: Add parameter "--fatal-warnings" to assemble
386 when checking whether the assemble support conditional branch
387 relaxation.
389 2024-02-22 Jakub Jelinek <jakub@redhat.com>
391 PR c/114007
392 * doc/extend.texi: (__extension__): Remove comments about scope
393 tokens vs. two colons.
395 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
397 PR tree-optimization/109804
398 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
399 DEMANGLE_COMPONENT_UNNAMED_TYPE.
401 2024-02-22 Richard Biener <rguenther@suse.de>
403 PR tree-optimization/114048
404 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
405 can also produce -1 off.
407 2024-02-22 Richard Biener <rguenther@suse.de>
409 PR tree-optimization/114027
410 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
411 condition reduction classification only for single-element
412 chains.
414 2024-02-22 Jakub Jelinek <jakub@redhat.com>
416 PR ipa/111960
417 * profile-count.h (profile_count::dump): Remove overload with
418 char * first argument.
419 * profile-count.cc (profile_count::dump): Change overload with char *
420 first argument which uses sprintf into the overfload with FILE *
421 first argument and use fprintf instead. Remove overload which wrapped
422 it.
424 2024-02-22 Jakub Jelinek <jakub@redhat.com>
426 PR tree-optimization/113993
427 * tree-call-cdce.cc (get_no_error_domain): Handle
428 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
429 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
430 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
431 the as the F128 suffixed cases, otherwise as non-suffixed ones.
432 Handle BUILT_IN_{EXP,POW}10L for
433 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
434 as (-inf, 4932).
436 2024-02-22 Jakub Jelinek <jakub@redhat.com>
438 PR tree-optimization/114038
439 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
440 loop exit condition if end is divisible by limb_prec.
442 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
444 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
445 problem of mabi=, mno-flush-func, mexplicit-relocs;
446 add missing leading - of mbranch-cost option.
447 * config/mips/mips.opt.urls: Regenerate.
449 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
451 PR target/109987
452 * config/rs6000/constraints.md (we): Update internal doc without
453 referring to option -mpower9-vector.
454 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
455 special handlings.
456 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
457 OTHER_P8_VECTOR_MASKS): Merge to ...
458 (OTHER_VSX_VECTOR_MASKS): ... here.
459 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
460 some error message handlings and explicit option mask adjustments on
461 explicit option power{8,9}-vector conflicting with other options.
462 (rs6000_print_isa_options): Update comments.
463 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
464 related array items and handlings.
465 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
466 special handlings.
467 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
468 WarnRemoved.
469 * doc/extend.texi: Remove documentation referring to option
470 -mpower8-vector.
471 * doc/invoke.texi: Remove documentation for option
472 -mpower{8,9}-vector and adjust some documentation referring to them.
473 * doc/md.texi: Update documentation for constraint we.
474 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
476 2024-02-22 Pan Li <pan2.li@intel.com>
478 PR target/114017
479 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
480 the version to 0.12.
482 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
484 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
486 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
487 Robin Dapp <rdapp.gcc@gmail.com>
489 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
490 (generic_ooo_vec_load): Ditto
491 (generic_ooo_vec_store): Ditto
492 (generic_ooo_vec_loadstore_seg): Ditto
493 (generic_ooo_vec_alu): Ditto
494 (generic_ooo_vec_fcmp): Ditto
495 (generic_ooo_vec_imul): Ditto
496 (generic_ooo_vec_fadd): Ditto
497 (generic_ooo_vec_fmul): Ditto
498 (generic_ooo_crypto): Ditto
499 (generic_ooo_perm): Ditto
500 (generic_ooo_vec_reduction): Ditto
501 (generic_ooo_vec_ordered_reduction): Ditto
502 (generic_ooo_vec_idiv): Ditto
503 (generic_ooo_vec_float_divsqrt): Ditto
504 (generic_ooo_vec_mask): Ditto
505 (generic_ooo_vec_vesetvl): Ditto
506 (generic_ooo_vec_setrm): Ditto
507 (generic_ooo_vec_readlen): Ditto
508 * config/riscv/riscv.md: Include generic-vector-ooo
509 * config/riscv/generic-vector-ooo.md: New file. To here
511 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
513 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
514 (generic_ooo_branch): Ditto
515 * config/riscv/generic.md (generic_sfb_alu): Ditto
516 (generic_fmul_half): Ditto
517 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
518 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
519 (sifive_7_popcount): Ditto
520 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
521 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
522 * config/riscv/vector.md: Change rdfrm to fmove
523 * config/riscv/zc.md: Change pushpop to load/store
525 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
527 * doc/invoke.texi (Warning Options): Fix typos.
529 2024-02-21 David Faust <david.faust@oracle.com>
531 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
532 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
533 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
535 2024-02-21 Martin Jambor <mjambor@suse.cz>
537 PR ipa/113476
538 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
539 initializers in the contructor.
540 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
541 * ipa-cp.h: New file.
542 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
543 (ipcp_value_source): Move to ipa-cp.h.
544 (ipcp_value_base): Likewise.
545 (ipcp_value): Likewise.
546 (ipcp_lattice): Likewise.
547 (ipcp_agg_lattice): Likewise.
548 (ipcp_bits_lattice): Likewise.
549 (ipcp_vr_lattice): Likewise.
550 (ipcp_param_lattices): Likewise.
551 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
552 (ipa_value_from_jfunc): Adjust a check for empty lattices.
553 (ipa_context_from_jfunc): Likewise.
554 (ipa_agg_value_from_jfunc): Likewise.
555 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
556 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
557 just in contiguous memory.
558 (ipcp_store_vr_results): Adjust a check for empty lattices.
559 * auto-profile.cc: Include sreal.h and ipa-cp.h.
560 * cgraph.cc: Likewise.
561 * cgraphclones.cc: Likewise.
562 * cgraphunit.cc: Likewise.
563 * config/aarch64/aarch64.cc: Likewise.
564 * config/i386/i386-builtins.cc: Likewise.
565 * config/i386/i386-expand.cc: Likewise.
566 * config/i386/i386-features.cc: Likewise.
567 * config/i386/i386-options.cc: Likewise.
568 * config/i386/i386.cc: Likewise.
569 * config/rs6000/rs6000.cc: Likewise.
570 * config/s390/s390.cc: Likewise.
571 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
572 files to be included in gtype-desc.cc.
573 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
574 * ipa-devirt.cc: Likewise.
575 * ipa-fnsummary.cc: Likewise.
576 * ipa-icf.cc: Likewise.
577 * ipa-inline-analysis.cc: Likewise.
578 * ipa-inline-transform.cc: Likewise.
579 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
580 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
581 * ipa-param-manipulation.cc: Likewise.
582 * ipa-predicate.cc: Likewise.
583 * ipa-profile.cc: Likewise.
584 * ipa-prop.cc: Likewise.
585 (ipa_node_params_t::duplicate): Assert new lattices remain empty
586 instead of setting them to NULL.
587 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
588 * ipa-split.cc: Likewise.
589 * ipa-sra.cc: Likewise.
590 * ipa-strub.cc: Likewise.
591 * ipa-utils.cc: Likewise.
592 * ipa.cc: Likewise.
593 * toplev.cc: Likewise.
594 * tree-ssa-ccp.cc: Likewise.
595 * tree-ssa-sccvn.cc: Likewise.
596 * tree-vrp.cc: Likewise.
598 2024-02-21 Tamar Christina <tamar.christina@arm.com>
600 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
601 Armv8.7-a.
603 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
605 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
606 Use aarch64_gen_compare_zero_and_branch rather than emitting
607 a CBZ directly.
609 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
611 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
612 Remove duplicated call.
614 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
616 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
617 Check that each individual piece of state is shared in the same
618 way, rather than using an aggregate check for PSTATE.ZA.
620 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
622 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
623 In the code that commits a lazy save, only zero ZA if the function
624 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
626 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
628 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
629 directly inserting the associated sequence
630 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
631 ...here instead.
633 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
635 PR target/113995
636 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
637 fold the SVE allocation into the initial allocation if the
638 initial allocation includes a VG save.
640 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
642 PR target/113220
643 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
644 contain jumps even if called after initial RTL expansion.
645 * mode-switching.cc: Include cfgbuild.h.
646 (optimize_mode_switching): Allow the sequence returned by the
647 emit hook to contain internal jumps. Record which blocks
648 contain such jumps and split the blocks at the end.
649 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
650 non-debug insns when scanning the sequence.
652 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
654 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
655 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
657 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
659 * doc/invoke.texi (-mmcu): Add information about MCU specs.
661 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
663 * doc/invoke.texi (-minrt): Clarify that main
664 must take no arguments.
666 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
668 * config/avr/builtins.def: Use function prototypes of given size
669 and signedness.
670 * config/avr/avr.cc (avr_init_builtins): Adjust types required
671 by builtins.def.
672 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
674 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
676 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
677 instead of @table.
679 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
681 * config/bpf/bpf.opt: Add help information for -mcpu.
683 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
685 PR target/113805
686 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
687 New pass.
688 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
689 Declare.
690 * config/aarch64/aarch64.md (is_call): New attribute.
691 (*and<mode>3nr_compare0): Rename to...
692 (@aarch64_and<mode>3nr_compare0): ...this.
693 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
694 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
695 * config/aarch64/aarch64-speculation.cc: Update file comment to
696 describe the new late pass.
697 (aarch64_do_track_speculation): Handle is_call insns like other calls.
698 (pass_track_speculation): Add an is_late member variable.
699 (pass_track_speculation::gate): Run the late pass for streaming-
700 compatible functions and the early pass for other functions.
701 (make_pass_track_speculation): Update accordingly.
702 (make_pass_late_track_speculation): New function.
703 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
704 function.
705 (aarch64_guard_switch_pstate_sm): Use it.
707 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
709 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
710 Register these builtins with a pointer to uint64_t rather than unsigned
711 DI mode.
713 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
715 PR target/113615
716 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
717 Conditionalize on '!TARGET_RDNA2_PLUS'.
718 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
719 (gcn_expand_reduc_scalar):
720 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
722 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
724 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
725 '__gfx90a__' target CPU definition. Add some safeguards for the future.
727 2024-02-19 Richard Biener <rguenther@suse.de>
729 PR rtl-optimization/54052
730 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
731 local defs by LR_OUT.
733 2024-02-19 Jakub Jelinek <jakub@redhat.com>
735 PR tree-optimization/113967
736 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
737 in condition that @rpos is multiple of vector element size.
739 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
741 PR target/113696
742 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
743 Suppress vsetvl fusion.
745 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
747 PR target/113912
748 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
749 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
750 (ix86_emit_save_regs): Don't generate push2 if
751 ix86_can_use_push2pop2 return false.
752 (ix86_expand_epilogue): Don't generate pop2 if
753 ix86_can_use_push2pop2 return false.
755 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
757 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
758 Note on complete device support.
760 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
762 * doc/extend.texi (AVR Function Attributes): Fuse description
763 of "signal" and "interrupt" attribute. Link pseudo instruction.
765 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
767 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
768 symbol type conversions.
769 (__cacop_d): Likewise.
770 (__cpucfg): Likewise.
771 (__asrtle_d): Likewise.
772 (__asrtgt_d): Likewise.
773 (__lddir_d): Likewise.
774 (__ldpte_d): Likewise.
775 (__crc_w_b_w): Likewise.
776 (__crc_w_h_w): Likewise.
777 (__crc_w_w_w): Likewise.
778 (__crc_w_d_w): Likewise.
779 (__crcc_w_b_w): Likewise.
780 (__crcc_w_h_w): Likewise.
781 (__crcc_w_w_w): Likewise.
782 (__crcc_w_d_w): Likewise.
783 (__csrrd_w): Likewise.
784 (__csrwr_w): Likewise.
785 (__csrxchg_w): Likewise.
786 (__csrrd_d): Likewise.
787 (__csrwr_d): Likewise.
788 (__csrxchg_d): Likewise.
789 (__iocsrrd_b): Likewise.
790 (__iocsrrd_h): Likewise.
791 (__iocsrrd_w): Likewise.
792 (__iocsrrd_d): Likewise.
793 (__iocsrwr_b): Likewise.
794 (__iocsrwr_h): Likewise.
795 (__iocsrwr_w): Likewise.
796 (__iocsrwr_d): Likewise.
797 (__frecipe_s): Likewise.
798 (__frecipe_d): Likewise.
799 (__frsqrte_s): Likewise.
800 (__frsqrte_d): Likewise.
802 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
804 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
805 function return value type to unsigned short.
807 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
809 * doc/sourcebuild.texi: add scan-assembler-bound
811 2024-02-16 Jason Merrill <jason@redhat.com>
813 * gdbhooks.py: Fix regex syntax.
815 2024-02-16 Richard Biener <rguenther@suse.de>
817 PR tree-optimization/113895
818 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
819 consistency checking when there are out-of-bound array
820 accesses. Allow -1 off when from an array reference with
821 constant index.
823 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
825 PR target/106543
826 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
827 pattern.
829 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
831 * doc/sourcebuild.texi (Effective-Target Keywords, Other
832 attribugs): Document linker_plugin.
833 (Require Support): Document dg-require-linker-plugin.
835 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
837 PR target/109349
838 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
839 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
840 (RISCV_MINOR_VERSION_BASE): Ditto.
841 (RISCV_REVISION_VERSION_BASE): Ditto.
842 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
843 rather than magic number.
844 * config/riscv/riscv.h (riscv_arch_help): New.
845 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
846 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
847 --print-supported-extensions.
848 * config/riscv/riscv.opt (march=help): New.
849 (print-supported-extensions): New.
850 (-print-supported-extensions): New.
851 * doc/invoke.texi (RISC-V Options): Document -march=help.
853 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
855 PR target/113780
856 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
857 for indirect calls with 4 or more arguments in pac-enabled functions.
859 2024-02-15 David Faust <david.faust@oracle.com>
861 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
862 use ldxb instead of ldxh.
864 2024-02-15 Jakub Jelinek <jakub@redhat.com>
866 PR middle-end/113921
867 * cfgrtl.h (prepend_insn_to_edge): New declaration.
868 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
869 comment.
870 (prepend_insn_to_edge): New function.
871 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
872 insert_insn_on_edge.
874 2024-02-15 Richard Biener <rguenther@suse.de>
876 PR tree-optimization/111156
877 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
878 at the pattern stmt if any.
880 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
882 PR target/113927
883 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
884 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
885 * config/avr/avr.cc (avr_adiw_reg_p): New function.
886 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
887 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
888 * config/avr/avr.md: Same.
889 (attr "isa") <tiny, no_tiny>: Remove.
890 <adiw, no_adiw>: Add.
891 (define_insn, define_insn_and_split): When an alternative has
892 constraint "w", then set attribute "isa" to "adiw".
893 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
894 Built-in define __AVR_HAVE_ADIW__.
895 * doc/invoke.texi (AVR Options): Document it.
897 2024-02-15 Andrew Stubbs <ams@baylibre.com>
899 * config/gcn/gcn-valu.md
900 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
901 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
902 details are supported on RDNA devices.
904 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
906 PR middle-end/113508
907 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
908 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
909 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
910 Add sentence about what the mode m is.
912 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
914 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
915 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
916 var.
918 2024-02-15 Richard Biener <rguenther@suse.de>
920 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
921 stmts.
923 2024-02-15 Jakub Jelinek <jakub@redhat.com>
925 PR tree-optimization/113567
926 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
927 _BitInt multiplication, division or modulo with
928 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
929 force the affected inputs into a new SSA_NAME.
931 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
933 PR target/113871
934 * config/i386/mmx.md (V248FI): New mode iterator.
935 (V24FI_32): DItto.
936 (vec_shl_<V248FI:mode>): New expander.
937 (vec_shl_<V24FI_32:mode>): Ditto.
938 (vec_shr_<V248FI:mode>): Ditto.
939 (vec_shr_<V24FI_32:mode>): Ditto.
940 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
941 (vec_shr_<V248FI:mode>): Ditto.
943 2024-02-14 Jan Hubicka <jh@suse.cz>
945 PR tree-optimization/111054
946 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
948 2024-02-14 Tamar Christina <tamar.christina@arm.com>
950 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
952 2024-02-14 Richard Biener <rguenther@suse.de>
954 PR tree-optimization/113910
955 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
956 the hashval_t hash.
958 2024-02-14 Jakub Jelinek <jakub@redhat.com>
960 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
961 (pp_integer_with_precision): For unsigned ptrdiff_t printing
962 with u, o or x print ptrdiff_t argument converted to
963 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
965 2024-02-14 Richard Biener <rguenther@suse.de>
967 PR middle-end/113576
968 * expr.cc (do_store_flag): For vector bool compares of vectors
969 with padding zero that.
970 * dojump.cc (do_compare_and_jump): Likewise.
972 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
974 * doc/install.texi (Prerequisites): Update gettext link.
976 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
978 PR target/113876
979 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
980 Return false if the incoming stack isn't 16-byte aligned.
982 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
984 PR middle-end/113904
985 * omp-general.cc (struct omp_ts_info): Update for splitting of
986 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
987 * omp-selectors.h (enum omp_tp_type): Replace
988 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
990 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
992 PR target/113742
993 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
994 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
996 2024-02-13 Richard Biener <rguenther@suse.de>
998 PR tree-optimization/113895
999 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1000 offset to discover constant array indices in bits, handle
1001 COMPONENT_REF to bitfields.
1003 2024-02-13 Richard Biener <rguenther@suse.de>
1005 PR tree-optimization/113831
1006 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1007 typo in comment.
1009 2024-02-13 Richard Biener <rguenther@suse.de>
1011 PR tree-optimization/113902
1012 * tree-vect-loop.cc (move_early_exit_stmts): Track
1013 last_seen_vuse for VUSE updating.
1015 2024-02-13 Tamar Christina <tamar.christina@arm.com>
1017 PR tree-optimization/113734
1018 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1019 an early break loop as partial.
1021 2024-02-13 Richard Biener <rguenther@suse.de>
1023 PR tree-optimization/113898
1024 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1025 missing accumulated off adjustment.
1027 2024-02-13 Jakub Jelinek <jakub@redhat.com>
1029 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1030 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1031 it against UINT_MAX and ULONG_MAX.
1033 2024-02-13 David Malcolm <dmalcolm@redhat.com>
1035 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1036 to...
1037 (emit_diagnostic_valist_meta): ...this.
1038 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
1039 (emit_diagnostic_valist_meta): ...this.
1041 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1043 PR tree-optimization/113849
1044 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
1045 fast path for widening casts where !m_upwards_2limb and lhs_type
1046 has precision which is a multiple of limb_prec.
1048 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1050 PR c++/113674
1051 * attribs.cc (extract_attribute_substring): Remove.
1052 (lookup_scoped_attribute_spec): Don't call it.
1054 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1056 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
1057 and cast to fmt_size_t instead of %lu and cast to unsigned long.
1059 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
1061 * Makefile.in: Add no-info dependency.
1062 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
1063 available.
1064 * configure: Regenerate.
1066 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
1068 PR target/113855
1069 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
1070 available to all sub-targets.
1071 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1072 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1074 2024-02-12 Richard Biener <rguenther@suse.de>
1076 PR tree-optimization/113831
1077 PR tree-optimization/108355
1078 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
1079 we see variable array indices and get_ref_base_and_extent
1080 can resolve those to constants fix up the ops to constants
1081 as well.
1082 (ao_ref_init_from_vn_reference): Use 'off' member for
1083 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
1084 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
1086 2024-02-12 Pan Li <pan2.li@intel.com>
1088 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
1089 Replace args to arguments for misspelled term.
1091 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
1093 PR target/112944
1094 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
1095 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
1096 when not linked with -mrodata-in-ram.
1098 2024-02-12 Richard Biener <rguenther@suse.de>
1100 PR tree-optimization/113863
1101 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1102 Record crossed virtual PHIs.
1103 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
1104 virtual PHIs.
1106 2024-02-10 Marek Polacek <polacek@redhat.com>
1108 DR 2237
1109 PR c++/107126
1110 PR c++/97202
1111 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
1113 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1115 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
1116 computation of idx for i == 4 of bitint_prec_huge.
1118 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1120 PR middle-end/110754
1121 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
1122 decls create PARM_DECL with pointer to original type, set
1123 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
1124 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
1125 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
1126 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
1127 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
1128 of the var as argument.
1130 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1132 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
1133 size_t and precision 4 for ptrdiff_t. Formatting fix.
1134 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
1135 Formatting fixes.
1136 (test_pp_format): Test t and z modifiers.
1137 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
1139 2024-02-10 Jakub Jelinek <jakub@redhat.com>
1141 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
1142 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
1143 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1144 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
1145 and casts to fmt_size_t instead of "%ld" and casts to long.
1146 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
1147 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
1148 instead of "%lu" and casts to unsigned long.
1149 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
1150 unsigned long.
1151 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1152 and casts to fmt_size_t instead of "%ld" and casts to long.
1153 * cfgexpand.cc (dump_stack_var_partition): Use
1154 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
1155 and casts to unsigned long.
1156 * gengtype.cc (adjust_field_rtx_def): Likewise.
1157 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
1158 and casts to fmt_size_t instead of "%ld" and casts to long.
1159 * postreload-gcse.cc (dump_hash_table): Likewise.
1160 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
1161 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
1162 (ggc_internal_alloc, ggc_free): Likewise.
1163 * genpreds.cc (write_lookup_constraint_1): Likewise.
1164 (write_insn_constraint_len): Likewise.
1165 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
1166 and casts to fmt_size_t instead of "%ld" and casts to long.
1167 * varasm.cc (output_constant_pool_contents): Use
1168 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
1169 * var-tracking.cc (dump_var): Likewise.
1171 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1173 PR tree-optimization/113783
1174 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
1175 through VIEW_CONVERT_EXPR for final cast checks. Handle
1176 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
1177 INTEGER_TYPEs.
1178 (gimple_lower_bitint): Don't merge mergeable operations or other
1179 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
1180 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
1181 mode is BLKmode.
1183 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1185 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
1186 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
1187 HOST_SIZE_T_PRINT_HEX_PURE): Define.
1188 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
1189 fixes.
1191 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1193 PR middle-end/113415
1194 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
1195 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
1196 of hand written loop with emit_insn of copy_insn and emit original
1197 after_rtl_seq on the last edge.
1199 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1201 PR tree-optimization/113818
1202 * gimple-lower-bitint.cc (add_eh_edge): New function.
1203 (bitint_large_huge::handle_load,
1204 bitint_large_huge::lower_mergeable_stmt,
1205 bitint_large_huge::lower_muldiv_stmt): Use it.
1207 2024-02-09 Jakub Jelinek <jakub@redhat.com>
1209 PR tree-optimization/113774
1210 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
1211 emit any comparison if m_first and low + 1 is equal to
1212 m_upwards_2limb, simplify condition for that. If not
1213 single_comparison, not m_first and we can prove that the idx <= low
1214 comparison will be always true, emit instead of idx <= low
1215 comparison low <= low such that cfg cleanup will optimize it at
1216 the end of the pass.
1218 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
1220 PR tree-optimization/113735
1221 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
1222 limit_check().
1224 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1226 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
1227 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
1229 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
1231 PR target/113711
1232 PR target/113733
1233 * config/i386/constraints.md: List all constraints with j prefix.
1234 (j>): Change auto-dec to auto-inc in documentation.
1235 (je): Changed to a memory constraint with APX NDD TLS operand
1236 check.
1237 (jM): New memory constraint for APX NDD instructions.
1238 (jO): Likewise.
1239 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
1240 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
1241 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
1242 (*add<mode>_1[SWI48]): Use je and jM.
1243 (addsi_1_zext): Use jM.
1244 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
1245 (*sub<mode>_1[SWI]): Use jM.
1246 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
1247 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
1248 (*and<dwi>3_doubleword): Likewise.
1249 (*anddi_1): Use jM.
1250 (*andsi_1_zext): Likewise.
1251 (*and<mode>_1[SWI24]): Likewise.
1252 (*<code><dwi>3_doubleword[any_or]): Use rjO
1253 (*code<mode>_1[any_or SWI248]): Use jM.
1254 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
1255 * config/i386/predicates.md (apx_ndd_memory_operand): New.
1256 (apx_ndd_add_memory_operand): Likewise.
1258 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1260 PR target/113824
1261 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
1262 * doc/avr-mmcu.texi: Rebuild.
1264 2024-02-08 Tamar Christina <tamar.christina@arm.com>
1266 PR tree-optimization/113808
1267 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
1268 value cross iterations.
1270 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1272 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
1273 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
1275 2024-02-08 Richard Biener <rguenther@suse.de>
1277 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1278 Revert last change to dr_may_alias_p.
1280 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
1282 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
1283 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
1284 Remove spec asm_misc.
1285 * config/avr/specs.h: Same.
1287 2024-02-08 Pan Li <pan2.li@intel.com>
1289 PR target/113766
1290 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
1291 sure the c.arg_num is >= 2 before checking.
1292 (struct build_frm_base): Ditto.
1293 (struct narrow_alu_def): Ditto.
1295 2024-02-07 Richard Biener <rguenther@suse.de>
1297 PR tree-optimization/113796
1298 * tree-if-conv.cc (combine_blocks): Wipe range-info before
1299 replacing PHIs and inserting predicates.
1301 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
1302 Uros Bizjak <ubizjak@gmail.com>
1304 PR target/113690
1305 * config/i386/i386-features.cc (timode_convert_cst): New helper
1306 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
1307 CONST_VECTOR.
1308 (timode_scalar_chain::convert_op): Use timode_convert_cst.
1309 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
1310 Use timode_convert_cst.
1312 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
1314 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1315 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
1316 (AARCH64_FL_DEBUGv8p9): Likewise.
1317 (AARCH64_FL_FGT2): Likewise.Likewise.
1318 (AARCH64_FL_ITE): Likewise.
1319 (AARCH64_FL_PFAR): Likewise.
1320 (AARCH64_FL_PMUv3_ICNTR): Likewise.
1321 (AARCH64_FL_PMUv3_SS): Likewise.
1322 (AARCH64_FL_PMUv3p9): Likewise.
1323 (AARCH64_FL_RASv2): Likewise.
1324 (AARCH64_FL_S1PIE): Likewise.
1325 (AARCH64_FL_S1POE): Likewise.
1326 (AARCH64_FL_S2PIE): Likewise.
1327 (AARCH64_FL_S2POE): Likewise.
1328 (AARCH64_FL_SCTLR2): Likewise.
1329 (AARCH64_FL_SEBEP): Likewise.
1330 (AARCH64_FL_SPE_FDS): Likewise.
1331 (AARCH64_FL_TCR2): Likewise.
1333 2024-02-07 Richard Biener <rguenther@suse.de>
1335 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
1336 Only check whether reads are in-bound in places that are not safe.
1337 Fix dependence check. Add missing newline. Clarify comments.
1339 2024-02-07 Tamar Christina <tamar.christina@arm.com>
1341 PR tree-optimization/113750
1342 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
1343 for single predecessor when doing early break vect.
1344 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
1345 after labels.
1347 2024-02-07 Tamar Christina <tamar.christina@arm.com>
1349 PR tree-optimization/113731
1350 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
1351 method.
1352 * gimple-iterator.h (gsi_move_before): Default new param to
1353 GSI_SAME_STMT.
1354 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
1355 GSI_NEW_STMT.
1357 2024-02-07 Jakub Jelinek <jakub@redhat.com>
1359 PR tree-optimization/113756
1360 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
1361 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
1362 of lh_bits value and mask.
1364 2024-02-07 Jakub Jelinek <jakub@redhat.com>
1366 PR tree-optimization/113753
1367 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
1368 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
1369 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
1370 so that they start with r[half_blocks_needed] lowest bit. Fix up
1371 computation of top mask for SIGNED.
1373 2024-02-07 Pan Li <pan2.li@intel.com>
1375 PR target/113766
1376 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
1377 the signature of func.
1378 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
1379 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
1380 overloaded func with empty args error.
1382 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
1384 PR target/113689
1385 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
1386 R10_REG after sorry.
1388 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
1390 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
1391 Move before new caller, and add ".default" suffix.
1392 (get_suffixed_assembler_name): New.
1393 (make_resolver_func): Use get_suffixed_assembler_name.
1394 (aarch64_generate_version_dispatcher_body): Redo name mangling.
1396 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1398 PR target/113763
1399 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
1400 element from std::pair<unsigned int, char> to an unnamed struct.
1401 Adjust uses of tile range variable.
1403 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1405 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
1406 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
1408 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1410 PR sanitizer/110676
1411 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
1412 reset maxlen to sizetype maximum.
1414 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1416 PR tree-optimization/113736
1417 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
1418 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
1420 2024-02-06 Jakub Jelinek <jakub@redhat.com>
1422 PR tree-optimization/113759
1423 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
1424 or from_unsignedN differs from properties of typeN, update typeN
1425 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
1426 uselessly convertible to typeN, convert it using fold_convert or
1427 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
1428 (convert_plusminus_to_widen): Likewise.
1430 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
1432 PR target/112577
1433 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
1434 vector structure modes correctly.
1436 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
1438 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
1439 warning.
1441 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
1443 PR target/113689
1444 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
1445 (x86_function_profiler): Call x86_64_select_profile_regnum to
1446 get a scratch register for large model profiling.
1448 2024-02-05 Richard Ball <richard.ball@arm.com>
1450 * config/arm/arm.cc (arm_output_mi_thunk): Emit
1451 insn for bti_c when bti is enabled.
1453 2024-02-05 Xi Ruoyao <xry111@xry111.site>
1455 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
1456 neg.
1458 2024-02-05 Xi Ruoyao <xry111@xry111.site>
1460 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
1461 (neg<mode>2): Change the mode iterator from MSA to IMSA because
1462 in FP arithmetic we cannot use (0 - x) for -x.
1463 (neg<mode>2): New define_insn to implement FP vector negation,
1464 using a bnegi instruction to negate the sign bit.
1466 2024-02-05 Richard Biener <rguenther@suse.de>
1468 PR tree-optimization/113707
1469 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
1470 checking the avail set treat out-of-region defines as
1471 available.
1473 2024-02-05 Richard Biener <rguenther@suse.de>
1475 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
1476 the default mode when building a pointer.
1478 2024-02-05 Jakub Jelinek <jakub@redhat.com>
1480 PR tree-optimization/113737
1481 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
1482 has just a single label, remove it and make single successor edge
1483 EDGE_FALLTHRU.
1485 2024-02-05 Jakub Jelinek <jakub@redhat.com>
1487 PR target/113059
1488 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1489 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
1490 df_analyze call.
1492 2024-02-05 Richard Biener <rguenther@suse.de>
1494 PR target/113255
1495 * config/i386/i386-expand.cc
1496 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
1497 Use a new pseudo for the skipped number of bytes.
1499 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
1501 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
1502 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
1503 sifive-p670.
1505 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
1507 * config/riscv/riscv.md: Include sifive-p400.md.
1508 * config/riscv/sifive-p400.md: New file.
1509 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
1510 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
1511 Add sifive_p400.
1512 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
1513 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
1514 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
1516 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1518 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
1519 Add missing ":SI" to the match_operator.
1521 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1523 * config/xtensa/xtensa.md (SHI): New mode iterator.
1524 (2 split patterns related to constsynth):
1525 Change to also accept HImode operands.
1527 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
1529 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
1530 similarly.
1532 2024-02-04 Xi Ruoyao <xry111@xry111.site>
1534 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
1535 incorrect expand.
1536 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
1537 (elmsgnbit): Likewise.
1538 (neg<mode:FVEC>2): New define_insn.
1539 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
1540 are now instantiated in simd.md.
1542 2024-02-04 Xi Ruoyao <xry111@xry111.site>
1544 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
1545 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
1546 MAX_MACHINE_MODE.
1548 2024-02-04 Li Wei <liwei@loongson.cn>
1550 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
1551 (loongarch_expand_vselect_vconcat): Ditto.
1552 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
1553 all 128-bit constant permutation situations.
1554 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
1555 (loongarch_is_imm_set_shuffle): Renamed function name.
1556 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
1557 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
1558 extract-even and extract-odd permutations.
1559 (loongarch_is_odd_extraction): Delete.
1560 (loongarch_is_even_extraction): Ditto.
1561 (loongarch_expand_vec_perm_const): Adjust.
1563 2024-02-03 Jakub Jelinek <jakub@redhat.com>
1565 PR middle-end/113722
1566 * wide-int.cc (wi::bswap_large): Rename third argument from
1567 len to xlen and adjust use in safe_uhwi. Add len variable, set
1568 it to BLOCKS_NEEDED (precision) and use it for clearing of val
1569 and as canonize argument. Clear val using memset instead of
1570 a loop.
1572 2024-02-03 Jakub Jelinek <jakub@redhat.com>
1574 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
1575 mmi.preferred_base + mmi.size - sizeof (void *).
1577 2024-02-03 Xi Ruoyao <xry111@xry111.site>
1579 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
1580 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
1581 the ODR-violating locale declaration.
1583 2024-02-02 Tamar Christina <tamar.christina@arm.com>
1585 PR tree-optimization/113588
1586 PR tree-optimization/113467
1587 * tree-vect-data-refs.cc
1588 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
1589 (vect_analyze_early_break_dependences): Update comments.
1591 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
1593 PR target/59778
1594 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
1595 and PA_BUILTIN_SET_FPSR builtins.
1596 * (pa_builtins_icode): Declare.
1597 * (def_builtin, pa_fpu_init_builtins): New.
1598 * (pa_init_builtins): Initialize FPU builtins.
1599 * (pa_builtin_decl, pa_expand_builtin_1): New.
1600 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
1601 PA_BUILTIN_SET_FPSR builtins.
1602 * (pa_atomic_assign_expand_fenv): New.
1603 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
1604 UNSPECV constants.
1605 (get_fpsr, put_fpsr): New expanders.
1606 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
1607 insn patterns.
1609 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1611 PR target/113697
1612 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
1614 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
1616 * doc/extend.texi (Common Type Attributes): Fix typo in
1617 description of hardbool.
1619 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1621 PR tree-optimization/113692
1622 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
1623 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
1624 final_cast_p.
1626 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1628 PR middle-end/113699
1629 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
1630 uninitialized large/huge _BitInt SSA_NAME inputs.
1632 2024-02-02 Jakub Jelinek <jakub@redhat.com>
1634 PR middle-end/113705
1635 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
1636 around wi::to_wide in order to compare value in prec precision.
1638 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
1640 Revert:
1641 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1643 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
1645 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1647 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
1649 2024-02-02 Pan Li <pan2.li@intel.com>
1651 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
1652 (riscv_pass_by_reference): Ditto.
1653 (riscv_fntype_abi): Ditto.
1655 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1657 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
1658 (pre_vsetvl::cleaup): Remove vsetvl_pre.
1659 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
1661 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
1663 * config/loongarch/larchintrin.h
1664 (__frecipe_s): Update function return type.
1665 (__frecipe_d): Ditto.
1666 (__frsqrte_s): Ditto.
1667 (__frsqrte_d): Ditto.
1669 2024-02-02 Li Wei <liwei@loongson.cn>
1671 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
1672 (loongarch_vector_costs::add_stmt_cost): Adjust.
1674 2024-02-02 Xi Ruoyao <xry111@xry111.site>
1676 * config/loongarch/loongarch.md (unspec): Add
1677 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
1678 (la_pcrel64_two_parts): New define_insn.
1679 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
1680 typo in the comment.
1681 (loongarch_call_tls_get_addr): If -mcmodel=extreme
1682 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
1683 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
1684 note to allow CSE addressing __tls_get_addr.
1685 (loongarch_legitimize_tls_address): If -mcmodel=extreme
1686 -mexplicit-relocs={always,auto}, address TLS IE symbols with
1687 la_pcrel64_two_parts.
1688 (loongarch_split_symbol): If -mcmodel=extreme
1689 -mexplicit-relocs={always,auto}, address symbols with
1690 la_pcrel64_two_parts.
1691 (loongarch_output_mi_thunk): Clean up unreachable code. If
1692 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
1693 thunks with la_pcrel64_two_parts.
1695 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1697 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
1698 Add support for call36.
1700 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1702 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
1703 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
1704 the macro instruction loading symbol address is not applicable.
1705 (loongarch_call_tls_get_addr): Adjust code.
1706 (loongarch_legitimize_tls_address): Likewise.
1708 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1710 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
1711 Add function declaration.
1712 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
1713 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
1714 is not allowed
1715 (loongarch_load_tls): Added macro support in extreme mode.
1716 (loongarch_call_tls_get_addr): Likewise.
1717 (loongarch_legitimize_tls_address): Likewise.
1718 (loongarch_force_address): Likewise.
1719 (loongarch_legitimize_move): Likewise.
1720 (loongarch_output_mi_thunk): Likewise.
1721 (loongarch_option_override_internal): Remove the code that detects
1722 explicit relocs status.
1723 (loongarch_handle_model_attribute): Likewise.
1724 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
1725 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
1726 (symbolic_off64_or_reg_operand): Likewise.
1728 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1730 * config/loongarch/loongarch.cc (loongarch_load_tls):
1731 Load all types of tls symbols through one function.
1732 (loongarch_got_load_tls_gd): Delete.
1733 (loongarch_got_load_tls_ld): Delete.
1734 (loongarch_got_load_tls_ie): Delete.
1735 (loongarch_got_load_tls_le): Delete.
1736 (loongarch_call_tls_get_addr): Modify the called function name.
1737 (loongarch_legitimize_tls_address): Likewise.
1738 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
1739 (@load_tls<mode>): New template.
1740 (@got_load_tls_ld<mode>): Delete.
1741 (@got_load_tls_le<mode>): Delete.
1742 (@got_load_tls_ie<mode>): Delete.
1744 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
1746 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
1747 (loongarch_legitimize_address): Add logical transformation code.
1749 2024-02-01 Marek Polacek <polacek@redhat.com>
1751 * doc/invoke.texi: Update -Wdangling-reference documentation.
1753 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
1755 PR target/113701
1756 * config/i386/i386.md (*cmp<dwi>_doubleword):
1757 Do not force SUBREG pieces to pseudos.
1759 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
1761 * config/pa/pa.md (atomic_storedi_1): Fix bug in
1762 alternative 1.
1764 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
1766 * config/avr/avr.cc: Tabify.
1768 2024-02-01 Richard Ball <richard.ball@arm.com>
1770 PR tree-optimization/111268
1771 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
1772 Add variable-length check for vector input arguments
1773 to a function.
1775 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1777 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
1778 hard-code number of SGPR/VGPR/AVGPR registers.
1779 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
1780 SGPR/VGPR/AVGPR registers.
1782 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
1784 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
1785 attribute, and include sifive-p600.md.
1786 * config/riscv/generic-ooo.md: Update type attribute.
1787 * config/riscv/generic.md: Update type attribute.
1788 * config/riscv/sifive-7.md: Update type attribute.
1789 * config/riscv/sifive-p600.md: New file.
1790 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
1791 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
1792 Add sifive_p600.
1793 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
1794 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
1795 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
1797 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
1799 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
1800 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
1801 * config/riscv/riscv.opt: New macro for 7 new unprivileged
1802 extensions.
1803 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
1804 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
1806 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1808 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
1809 -static-libasan. Add missing whitespace.
1811 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1813 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
1814 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
1815 Don't 'define_constants'.
1817 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1819 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
1821 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
1823 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
1824 [TARGET_RDNA3]: Adjust.
1826 2024-02-01 Richard Biener <rguenther@suse.de>
1828 PR tree-optimization/113693
1829 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
1830 data when available.
1832 2024-02-01 Jakub Jelinek <jakub@redhat.com>
1833 Jason Merrill <jason@redhat.com>
1835 PR c++/113531
1836 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
1837 on variables which were promoted to TREE_STATIC.
1839 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
1840 Richard Biener <rguenther@suse.de>
1842 PR target/113560
1843 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
1844 information via tree_non_zero_bits to check if this operand
1845 is suitably extended for a widening (or highpart) multiplication.
1846 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
1847 isn't already of the claimed type.
1849 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1851 Revert:
1852 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1854 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1855 (generic_ooo_branch): ditto
1856 * config/riscv/generic.md (generic_sfb_alu): ditto
1857 (generic_fmul_half): ditto
1858 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1859 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1860 (sifive_7_popcount): ditto
1861 * config/riscv/vector.md: change rdfrm to fmove
1862 * config/riscv/zc.md: change pushpop to load/store
1864 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1866 Revert:
1867 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1868 Robin Dapp <rdapp.gcc@gmail.com>
1870 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1871 (generic_ooo_vec_load): ditto
1872 (generic_ooo_vec_store): ditto
1873 (generic_ooo_vec_loadstore_seg): ditto
1874 (generic_ooo_vec_alu): ditto
1875 (generic_ooo_vec_fcmp): ditto
1876 (generic_ooo_vec_imul): ditto
1877 (generic_ooo_vec_fadd): ditto
1878 (generic_ooo_vec_fmul): ditto
1879 (generic_ooo_crypto): ditto
1880 (generic_ooo_perm): ditto
1881 (generic_ooo_vec_reduction): ditto
1882 (generic_ooo_vec_ordered_reduction): ditto
1883 (generic_ooo_vec_idiv): ditto
1884 (generic_ooo_vec_float_divsqrt): ditto
1885 (generic_ooo_vec_mask): ditto
1886 (generic_ooo_vec_vesetvl): ditto
1887 (generic_ooo_vec_setrm): ditto
1888 (generic_ooo_vec_readlen): ditto
1889 * config/riscv/riscv.md: include generic-vector-ooo
1890 * config/riscv/generic-vector-ooo.md: New file. to here
1892 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1894 Revert:
1895 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1897 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1899 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1901 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1903 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1904 Robin Dapp <rdapp.gcc@gmail.com>
1906 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1907 (generic_ooo_vec_load): ditto
1908 (generic_ooo_vec_store): ditto
1909 (generic_ooo_vec_loadstore_seg): ditto
1910 (generic_ooo_vec_alu): ditto
1911 (generic_ooo_vec_fcmp): ditto
1912 (generic_ooo_vec_imul): ditto
1913 (generic_ooo_vec_fadd): ditto
1914 (generic_ooo_vec_fmul): ditto
1915 (generic_ooo_crypto): ditto
1916 (generic_ooo_perm): ditto
1917 (generic_ooo_vec_reduction): ditto
1918 (generic_ooo_vec_ordered_reduction): ditto
1919 (generic_ooo_vec_idiv): ditto
1920 (generic_ooo_vec_float_divsqrt): ditto
1921 (generic_ooo_vec_mask): ditto
1922 (generic_ooo_vec_vesetvl): ditto
1923 (generic_ooo_vec_setrm): ditto
1924 (generic_ooo_vec_readlen): ditto
1925 * config/riscv/riscv.md: include generic-vector-ooo
1926 * config/riscv/generic-vector-ooo.md: New file. to here
1928 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
1930 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1931 (generic_ooo_branch): ditto
1932 * config/riscv/generic.md (generic_sfb_alu): ditto
1933 (generic_fmul_half): ditto
1934 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1935 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1936 (sifive_7_popcount): ditto
1937 * config/riscv/vector.md: change rdfrm to fmove
1938 * config/riscv/zc.md: change pushpop to load/store
1940 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
1942 PR target/113657
1943 * config/aarch64/aarch64-simd.md (split for movv8di):
1944 For strict aligned mode, use DImode instead of TImode.
1946 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
1948 PR middle-end/113607
1949 * match.pd: Make sure else values match when folding a
1950 vec_cond into a conditional operation.
1952 2024-01-31 Marek Polacek <polacek@redhat.com>
1954 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
1956 2024-01-31 Tamar Christina <tamar.christina@arm.com>
1957 Matthew Malcomson <matthew.malcomson@arm.com>
1959 PR sanitizer/112644
1960 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
1961 memcmp.
1962 * builtins.cc (expand_builtin): Include HWASAN when checking for
1963 builtin inlining.
1965 2024-01-31 Richard Biener <rguenther@suse.de>
1967 PR middle-end/110176
1968 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
1969 to match INTEGER_CST only without outstanding conversion.
1971 2024-01-31 Alex Coplan <alex.coplan@arm.com>
1973 PR target/111677
1974 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
1975 V16QImode for the full 16-byte FPR saves in the vector PCS case.
1977 2024-01-31 Richard Biener <rguenther@suse.de>
1979 PR tree-optimization/111444
1980 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
1981 vn_reference_lookup_2 when optimistically skipping may-defs.
1983 2024-01-31 Richard Biener <rguenther@suse.de>
1985 PR tree-optimization/113630
1986 * tree-ssa-pre.cc (compute_avail): Avoid registering a
1987 reference with a representation with not matching base
1988 access size.
1990 2024-01-31 Jakub Jelinek <jakub@redhat.com>
1992 PR rtl-optimization/113656
1993 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
1994 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
1996 2024-01-31 Jakub Jelinek <jakub@redhat.com>
1998 PR debug/113637
1999 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2000 with BLKmode are larger than DWARF2_ADDR_SIZE.
2002 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2004 PR tree-optimization/113639
2005 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2006 For VIEW_CONVERT_EXPR set rhs1 to its operand.
2008 2024-01-31 Richard Biener <rguenther@suse.de>
2010 PR tree-optimization/113670
2011 * tree-vect-data-refs.cc (vect_check_gather_scatter):
2012 Make sure we can take the address of the reference base.
2014 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
2016 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2017 ATA5835, ATtiny64AUTO, ATA5700M322.
2018 * doc/avr-mmcu.texi: Rebuild.
2020 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2022 PR debug/113394
2023 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
2024 caller.
2026 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2028 PR middle-end/112917
2029 PR middle-end/113100
2030 * builtins.cc (expand_builtin_stack_address): Use
2031 STACK_ADDRESS_OFFSET.
2032 * doc/extend.texi (__builtin_stack_address): Adjust.
2033 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2034 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2035 * doc/tm.texi: Rebuilt.
2037 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2039 PR target/113495
2040 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
2041 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
2042 (pre_vsetvl::compute_transparent): New function.
2043 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2045 2024-01-30 Fangrui Song <maskray@google.com>
2047 PR target/105576
2048 * config/i386/constraints.md: Define constraint "Ws".
2049 * doc/md.texi: Document it.
2051 2024-01-30 Marek Polacek <polacek@redhat.com>
2053 PR c++/110358
2054 PR c++/109640
2055 * doc/invoke.texi: Update -Wdangling-reference description.
2057 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2059 * config/xtensa/constraints.md (R, T, U):
2060 Change define_constraint to define_memory_constraint.
2061 * config/xtensa/predicates.md (move_operand): Don't check that a
2062 constant pool operand size is a multiple of UNITS_PER_WORD.
2063 * config/xtensa/xtensa.cc
2064 (xtensa_lra_p, TARGET_LRA_P): Remove.
2065 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
2066 clause as it can no longer be true.
2067 (fixup_subreg_mem): Drop function.
2068 (xtensa_output_integer_literal_parts): Consider 16-bit wide
2069 constants.
2070 (xtensa_legitimate_constant_p): Add short-circuit path for
2071 integer load instructions. Don't check that mode size is
2072 at least UNITS_PER_WORD.
2073 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
2074 rather reload_in_progress and reload_completed.
2075 (doloop_end): Drop operand 2.
2076 (movhi_internal): Add alternative loading constant from a
2077 literal pool.
2078 (define_split for DI register_operand): Don't limit to
2079 !TARGET_AUTO_LITPOOLS.
2080 * config/xtensa/xtensa.opt (mlra): Change to no effect.
2082 2024-01-30 Pan Li <pan2.li@intel.com>
2084 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
2085 calculate the gpr count required by vls mode.
2086 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
2087 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
2088 for vls mode.
2089 (riscv_get_arg_info): Add vls mode handling.
2090 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
2092 2024-01-30 Richard Biener <rguenther@suse.de>
2094 PR tree-optimization/113659
2095 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2096 Handle main exit without virtual use.
2098 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
2100 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
2102 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
2104 PR libgcc/113403
2105 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
2106 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
2107 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
2108 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
2109 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
2110 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
2112 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2114 PR target/113623
2115 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
2116 Mark all registers that occur in addresses as needing a GPR.
2118 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
2120 PR target/113636
2121 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
2122 the containing insn as an extra parameter. Reset debug instructions
2123 if they reference a register that is no longer used by real insns.
2124 (early_ra::apply_allocation): Update calls accordingly.
2126 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2128 PR tree-optimization/113603
2129 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
2130 count_nonzero_bytes call refetch si using get_strinfo in case it
2131 has been unshared in the meantime.
2133 2024-01-30 Jakub Jelinek <jakub@redhat.com>
2135 PR middle-end/101195
2136 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
2137 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
2139 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
2141 * config/riscv/thead.cc (th_print_operand_address): Change %ld
2142 to %lld.
2144 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
2145 Manolis Tsamis <manolis.tsamis@vrull.eu>
2146 Philipp Tomsich <philipp.tomsich@vrull.eu>
2148 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
2149 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
2150 Likewise.
2151 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
2152 Call on framework moved later.
2154 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
2156 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
2157 instruction in naked function epilogues.
2159 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
2161 PR target/113655
2162 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
2163 gcc_cv_as_mips_explicit_relocs.
2164 * configure: Regnerated.
2166 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
2168 PR target/108933
2169 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
2170 Correct generated RTL.
2171 (arm_rev16si2_alt1): Correctly handle conditional execution.
2172 (arm_rev16si2_alt2): Likewise.
2174 2024-01-29 Richard Biener <rguenther@suse.de>
2176 PR middle-end/113622
2177 * expr.cc (expand_assignment): Spill hard registers if
2178 we index them with a variable offset.
2180 2024-01-29 Richard Biener <rguenther@suse.de>
2182 PR middle-end/113622
2183 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
2184 Also allow DECL_HARD_REGISTER variables.
2186 2024-01-29 Alex Coplan <alex.coplan@arm.com>
2188 PR target/113616
2189 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
2190 Use iterate_safely when iterating over debug uses.
2191 (fixup_debug_uses): Likewise.
2192 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
2193 over nondebug insns instead of manually maintaining the next insn.
2194 * iterator-utils.h (class safe_iterator): New.
2195 (iterate_safely): New.
2197 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
2199 PR target/38534
2200 * config/i386/i386-options.cc (ix86_set_func_type): Save
2201 callee-saved registers in noreturn functions for -O0/-Og.
2203 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2205 PR target/113615
2206 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
2207 define for !TARGET_RDNA2_PLUS.
2209 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
2211 PR target/113281
2212 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
2213 workaround for right shifts.
2214 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
2215 (vect_determine_precisions_from_range): Be more selective about
2216 which codes can be narrowed based on their input and output ranges.
2217 For shifts, require at least one more bit of precision than the
2218 maximum shift amount.
2220 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2222 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
2224 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2226 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
2227 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
2228 LLVM 13.0.1+.
2230 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
2232 PR other/111966
2233 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
2234 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
2235 (SET_SRAM_ECC_UNSET): ... this.
2236 (copy_early_debug_info): Remove gfx900 special case, now handled as
2237 part of the generic handling.
2238 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
2240 2024-01-29 Jakub Jelinek <jakub@redhat.com>
2242 PR tree-optimization/110603
2243 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
2244 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
2245 overwritten anyway). Avoid creating invalid range with minlen
2246 larger than maxlen. Formatting fix.
2248 2024-01-29 Richard Biener <rguenther@suse.de>
2250 PR debug/103047
2251 * tree-inline.cc (initialize_inlined_parameters): Reverse
2252 the decl chain of inlined parameters.
2254 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2256 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
2257 alignment of CFString constants by setting DECL_USER_ALIGN.
2259 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
2260 Jakub Jelinek <jakub@redhat.com>
2262 PR libgcc/113402
2263 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
2264 and BUILT_IN_GCC_NESTED_PTR_DELETED.
2265 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
2266 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
2267 rename the library fallbacks to __gcc_nested_func_ptr_created and
2268 __gcc_nested_func_ptr_deleted.
2269 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
2270 and __gcc_nested_func_ptr_deleted.
2271 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
2272 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
2273 * tree.cc (build_common_builtin_nodes): Build the
2274 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
2275 builtins only for non-explicit.
2277 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
2279 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
2281 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2283 PR target/38534
2284 * config/i386/i386-options.cc (ix86_set_func_type): Don't
2285 save and restore callee saved registers for a noreturn function
2286 with nothrow or compiled with -fno-exceptions.
2288 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
2290 PR target/103503
2291 PR target/113312
2292 * config/i386/i386-expand.cc (ix86_expand_call): Replace
2293 no_caller_saved_registers check with call_saved_registers check.
2294 Clobber all registers that are not used by the callee with
2295 no_callee_saved_registers attribute.
2296 * config/i386/i386-options.cc (ix86_set_func_type): Set
2297 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
2298 noreturn function. Disallow no_callee_saved_registers with
2299 interrupt or no_caller_saved_registers attributes together.
2300 (ix86_set_current_function): Replace no_caller_saved_registers
2301 check with call_saved_registers check.
2302 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
2303 (ix86_handle_call_saved_registers_attribute): This.
2304 (ix86_gnu_attributes): Add
2305 ix86_handle_call_saved_registers_attribute.
2306 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
2307 no_caller_saved_registers check with call_saved_registers check.
2308 (ix86_function_ok_for_sibcall): Don't allow callee with
2309 no_callee_saved_registers attribute when the calling function
2310 has callee-saved registers.
2311 (ix86_comp_type_attributes): Also check
2312 no_callee_saved_registers.
2313 (ix86_epilogue_uses): Replace no_caller_saved_registers check
2314 with call_saved_registers check.
2315 (ix86_hard_regno_scratch_ok): Likewise.
2316 (ix86_save_reg): Replace no_caller_saved_registers check with
2317 call_saved_registers check. Don't save any registers for
2318 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
2319 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
2320 no_callee_saved_registers attribute is called.
2321 (find_drap_reg): Replace no_caller_saved_registers check with
2322 call_saved_registers check.
2323 * config/i386/i386.h (call_saved_registers_type): New enum.
2324 (machine_function): Replace no_caller_saved_registers with
2325 call_saved_registers.
2326 * doc/extend.texi: Document no_callee_saved_registers attribute.
2328 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2330 PR tree-optimization/113614
2331 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
2332 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
2333 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
2335 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2337 PR tree-optimization/113568
2338 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
2339 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
2340 in the widening extension checks.
2342 2024-01-27 Jakub Jelinek <jakub@redhat.com>
2344 * gimple-lower-bitint.cc (gimple_lower_bitint): For
2345 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
2347 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
2349 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
2350 the warning for an attribute-always_inline without inline declaration.
2352 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
2354 PR other/113575
2355 * genopinit.cc (main): Split init_all_optabs into functions
2356 of 1000 patterns each.
2358 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
2360 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
2361 TM_MULTILIB_CONFIG.
2362 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
2363 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
2364 -march/-mtune.
2366 2024-01-26 Andrew Stubbs <ams@baylibre.com>
2368 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
2369 * config/gcn/gcn-valu.md (all_convert): New iterator.
2370 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
2371 define_expand, and rename the old one to ...
2372 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
2373 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
2374 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
2375 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
2376 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
2377 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
2378 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
2379 (<u>mulqihi3_scalar): Likewise.
2381 2024-01-26 Richard Biener <rguenther@suse.de>
2383 PR tree-optimization/113602
2384 * tree-data-ref.cc (dr_analyze_innermost): Fail when
2385 the base object isn't addressable.
2387 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
2389 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
2390 "--amdhsa-code-object-version=" argument.
2391 (ASM_SPEC): Use it; replace previous version of it.
2393 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2395 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
2396 (pre_vsetvl::emit_vsetvl): Ditto.
2398 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
2400 * config/loongarch/lasx.md (vec_extract<mode>_0):
2401 New define_insn_and_split patten.
2403 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
2405 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
2407 2024-01-26 Li Wei <liwei@loongson.cn>
2409 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
2411 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2413 PR target/113469
2414 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
2416 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
2418 PR target/100212
2419 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
2420 undefined shift after the call to exact_log2.
2422 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
2424 PR target/100204
2425 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
2426 before taking the negative of it.
2428 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
2430 PR target/113526
2431 * lra-constraints.cc (curr_insn_transform): Change class even for
2432 spilled pseudo successfully matched with with NO_REGS.
2434 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
2436 PR target/113601
2437 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
2439 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
2441 PR target/112987
2442 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
2443 (aarch64_expand_epilogue): Use the new function.
2444 (aarch64_split_compare_and_swap): Likewise.
2445 (aarch64_split_atomic_op): Likewise.
2447 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
2449 PR middle-end/112971
2450 * fold-const.cc (simplify_const_binop): New function for binop
2451 simplification of two constant vectors when element-wise
2452 handling is not necessary.
2453 (const_binop): Call new function.
2455 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
2457 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
2458 * config/riscv/constraints.md: Likewise.
2459 * config/riscv/corev.def: Likewise.
2460 * config/riscv/corev.md: Likewise.
2461 * config/riscv/predicates.md: Likewise.
2462 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
2463 * config/riscv/riscv-ftypes.def: Likewise.
2464 * config/riscv/riscv.opt: Likewise.
2465 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
2466 * doc/extend.texi: Add XCVbitmanip builtin documentation.
2467 * doc/sourcebuild.texi: Likewise.
2469 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
2471 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
2473 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
2475 PR target/113538
2476 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
2477 (riscv_fntype_abi): Ditto.
2478 * config/riscv/riscv.opt: Ditto.
2480 2024-01-25 Jakub Jelinek <jakub@redhat.com>
2482 PR middle-end/113574
2483 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
2484 count against TYPE_PRECISION rather than TYPE_SIZE.
2486 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2488 PR target/113572
2489 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
2490 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
2492 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2494 PR target/113550
2495 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
2496 whether each split instruction is a load that clobbers the source
2497 address. Emit that instruction last if so.
2499 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
2501 PR target/113485
2502 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
2503 pattern.
2504 (<optab><Vnarrowq><mode>2): Use it instead of generating a
2505 paradoxical subreg for the input.
2507 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2509 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
2510 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
2511 predecessors dump information.
2513 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2515 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
2516 redundant full available computation.
2517 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
2519 2024-01-25 Jakub Jelinek <jakub@redhat.com>
2521 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
2522 * doc/rtl.texi (CONST_VECTOR): Likewise.
2524 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2526 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
2527 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
2528 (pass_vsetvl::execute): Ditto.
2529 * config/riscv/riscv.opt: Ditto.
2531 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
2533 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
2534 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
2536 2024-01-25 Richard Biener <rguenther@suse.de>
2538 PR tree-optimization/113576
2539 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
2540 exits with may_be_zero niters when its the last one.
2542 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
2544 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2545 For symbols of type tls, non-zero Offset is not generated.
2547 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
2549 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
2550 P9 with m32 and mpowerpc64.
2552 2024-01-25 liuhongt <hongtao.liu@intel.com>
2554 * config/i386/i386-options.cc (ix86_option_override_internal):
2555 Enable -mlam=u57 by default when compiled with
2556 -fsanitize=hwaddress.
2558 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
2560 * common/config/riscv/riscv-common.cc (riscv_implied_info):
2561 Remove {"ztso", "a"}.
2563 2024-01-24 Martin Jambor <mjambor@suse.cz>
2565 PR ipa/108007
2566 PR ipa/112616
2567 * cgraph.h (cgraph_edge): Add a parameter to
2568 redirect_call_stmt_to_callee.
2569 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
2570 parameter to modify_call.
2571 (ipa_release_ssas_in_hash): Declare.
2572 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
2573 parameter killed_ssas, pass it to padjs->modify_call.
2574 * ipa-param-manipulation.cc (purge_all_uses): New function.
2575 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
2576 Instead of substituting uses, invoke purge_all_uses. If
2577 hash of killed SSAs has not been provided, create a temporary one
2578 and release SSAs that have been added to it.
2579 (compare_ssa_versions): New function.
2580 (ipa_release_ssas_in_hash): Likewise.
2581 * tree-inline.cc (redirect_all_calls): Create
2582 id->killed_new_ssa_names earlier, pass it to edge redirection,
2583 adjust a comment.
2584 (copy_body): Release SSAs in id->killed_new_ssa_names.
2586 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
2588 PR target/113486
2589 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
2590 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
2592 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
2594 PR target/113095
2595 * config/riscv/sfb.md: New splitters to rewrite single bit
2596 sign extension as the condition to SFB instructions.
2598 2024-01-24 Jan Hubicka <jh@suse.cz>
2600 PR middle-end/88345
2601 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
2602 (fmin-function-alignment): New parameter.
2603 * doc/invoke.texi: (-fmin-function-alignment): Document.
2604 (-falign-functions,-falign-loops,-falign-labels): Mention that
2605 aglinments are ignored in cold code.
2606 * varasm.cc (assemble_start_function): Handle min-function-alignment.
2608 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2610 PR target/109636
2611 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
2612 mulv2di3): Remove.
2613 * config/aarch64/iterators.md (VQDIV): Remove.
2614 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
2615 SVE_I_SIMD_DI): New.
2616 (VPRED, sve_lane_con): Add V4SI and V2DI.
2617 * config/aarch64/aarch64-sve.md (<optab><mode>3,
2618 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
2619 (mul<mode>3): New, split from <optab><mode>3.
2620 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
2621 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
2622 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
2623 SVE_FULL_HSDI_SIMD_DI.
2625 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2627 PR tree-optimization/113552
2628 * config/aarch64/aarch64.cc
2629 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
2631 2024-01-24 Martin Jambor <mjambor@suse.cz>
2633 PR ipa/113490
2634 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
2635 count is equal or greater than the limit. Use the limit from the
2636 callee.
2638 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
2640 * configure.ac: Detect the explicit relocs support for
2641 mips, and define C macro MIPS_EXPLICIT_RELOCS.
2642 * config.in: Regenerated.
2643 * configure: Regenerated.
2644 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
2645 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
2646 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
2647 !TARGET_EXPLICIT_RELOCS instead of just set it.
2648 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
2649 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
2650 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
2651 and define -m(no-)explicit-relocs as aliases.
2653 2024-01-24 Alex Coplan <alex.coplan@arm.com>
2655 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
2656 to 1.
2657 (-mlate-ldp-fusion): Likewise.
2659 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2661 * tree-vect-loop.cc (vect_get_vect_def,
2662 vect_create_epilog_for_reduction): Rename main_exit_p to
2663 last_val_reduc_p.
2665 2024-01-24 Tamar Christina <tamar.christina@arm.com>
2667 PR tree-optimization/113364
2668 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
2669 early exits then we must reduce from the first offset for all of them.
2671 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2673 PR target/113495
2674 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
2675 (get_regno): Ditto.
2676 (get_bb_index): Ditto.
2677 (pre_vsetvl::compute_avl_def_data): Ditto.
2678 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
2679 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
2681 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
2682 Richard Sandiford <richard.sandiford@arm.com>
2684 PR target/100942
2685 * ccmp.cc (ccmp_candidate_p): Add outer argument.
2686 Allow if the outer is true and the lhs is used more
2687 than once.
2688 (expand_ccmp_expr): Update call to ccmp_candidate_p.
2689 * expr.h (expand_expr_real_gassign): Declare.
2690 * expr.cc (expand_expr_real_gassign): New function, split out from...
2691 (expand_expr_real_1): ...here.
2692 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
2694 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2696 PR target/113089
2697 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
2698 (fixup_debug_use): New.
2699 (fixup_debug_uses_trailing_add): New.
2700 (fixup_debug_uses): New. Use it ...
2701 (ldp_bb_info::fuse_pair): ... here.
2702 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
2703 fix up debug uses of the base register that are affected by
2704 folding in the trailing add insn.
2706 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2708 PR target/113089
2709 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
2710 Update trailing nondebug uses of the base register in the case
2711 of cancelling writeback.
2713 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2715 PR target/113089
2716 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
2717 (debug_insn_use_iterator): New.
2718 (set_info::first_debug_insn_use): New.
2719 (set_info::debug_insn_uses): New.
2720 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
2721 (set_info::first_debug_insn_use): New.
2722 (set_info::debug_insn_uses): New.
2724 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2726 PR target/113356
2727 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
2728 Don't record hazards against the opposite insn in the pair.
2730 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2732 PR target/113070
2733 * config/aarch64/aarch64-ldp-fusion.cc
2734 (struct stp_change_builder): New.
2735 (decide_stp_strategy): Reanme to ...
2736 (try_repurpose_store): ... this.
2737 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
2738 construct stp changes. Fix up uses when inserting new stp insns.
2740 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2742 PR target/113070
2743 * rtl-ssa.h: Include hash-set.h.
2744 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
2745 new_sets parameter and use it to keep track of new user-created sets.
2746 (function_info::apply_changes_to_insn): Also call add_def on new sets.
2747 (function_info::change_insns): Add hash_set to keep track of new
2748 user-created defs. Plumb it through.
2749 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
2750 apply_changes_to_insn.
2752 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2754 PR target/113070
2755 * rtl-ssa/accesses.cc (function_info::create_use): New.
2756 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
2757 Ensure new uses end up referring to permanent defs.
2758 * rtl-ssa/functions.h (function_info::create_use): Declare.
2760 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2762 PR target/113070
2763 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
2764 to finalize_new_accesses from the backwards placement loop, run it
2765 forwards in a separate loop.
2767 2024-01-23 Richard Biener <rguenther@suse.de>
2769 PR tree-optimization/113552
2770 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
2771 floor_log2 instead of exact_log2 on the number of calls.
2773 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
2774 Jakub Jelinek <jakub@redhat.com>
2776 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
2777 decl.
2779 2024-01-23 Richard Biener <rguenther@suse.de>
2781 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2782 Separate single and multi-exit case when creating PHIs between
2783 the main and epilogue.
2785 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
2787 PR target/112989
2788 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
2789 MODE_single variants of functions that don't take tuple arguments.
2791 2024-01-23 Alex Coplan <alex.coplan@arm.com>
2793 PR target/113114
2794 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
2795 Don't assert recog success, just punt if the writeback pair
2796 isn't recognized.
2798 2024-01-23 Jakub Jelinek <jakub@redhat.com>
2800 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
2801 ATTRIBUTE_UNUSED to decl.
2803 2024-01-23 Richard Biener <rguenther@suse.de>
2805 PR debug/107058
2806 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
2807 handle unexpected but bogus DIE contexts when not checking
2808 enabled.
2810 2024-01-23 Jakub Jelinek <jakub@redhat.com>
2812 PR tree-optimization/113462
2813 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
2814 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
2815 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
2816 sizes between 129 and 8192 bytes.
2818 2024-01-23 Xi Ruoyao <xry111@xry111.site>
2820 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2821 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
2822 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
2823 (loongarch_call_tls_get_addr): Do not split symbols of
2824 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
2825 EXPLICIT_RELOCS_AUTO.
2827 2024-01-23 Richard Biener <rguenther@suse.de>
2829 * alias.cc (known_base_value_p): Remove.
2830 (find_base_value): Remove PLUS/MINUS handling
2831 when both operands are not CONST_INT_P.
2833 2024-01-23 Richard Biener <rguenther@suse.de>
2835 PR rtl-optimization/113255
2836 * alias.cc (find_base_term): Remove PLUS/MINUS handling
2837 when both operands are not CONST_INT_P.
2839 2024-01-23 Richard Biener <rguenther@suse.de>
2841 PR debug/112718
2842 * dwarf2out.cc (dwarf2out_finish): Reset all type units
2843 for the fat part of an LTO compile.
2845 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
2847 * doc/sourcebuild.texi: Add attributes for keywords.
2849 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
2851 PR c++/90463
2852 * doc/invoke.texi (Warning Options): Correct lists of options
2853 enabled by -Wall and -Wextra by checking against common.opt
2854 and c-family/c.opt.
2856 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
2858 PR target/113030
2859 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
2860 instead of cpu_optaliases.
2861 (check_arch): Use arch_opt_alias instead of arch_optaliases.
2863 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2865 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
2866 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
2867 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
2869 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2871 PR target/109092
2872 * config/riscv/riscv.md: Use reg instead of subreg.
2874 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
2876 PR other/111966
2877 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
2878 to match the compiler default.
2879 (simple_object_copy_lto_debug_sections): Never unlink the outfile
2880 on error as the caller does so.
2881 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
2882 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
2884 2024-01-22 Richard Biener <rguenther@suse.de>
2886 PR tree-optimization/113373
2887 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2888 Create LC PHIs in the exit blocks where necessary.
2889 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
2890 to handle missing LC PHIs.
2891 (find_connected_edge): Remove.
2892 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
2894 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2896 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
2898 2024-01-22 xuli <xuli1@eswincomputing.com>
2900 PR target/113420
2901 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
2902 (registered_function::overloaded_hash):refactor.
2903 (resolve_overloaded_builtin):avoid internal ICE.
2905 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
2907 PR target/82420
2908 PR target/111279
2909 * calls.cc (emit_library_call_value_1): Pass valid TYPE
2910 to emit_push_insn.
2911 * expr.cc (emit_push_insn): Likewise.
2913 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
2915 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
2916 correcction version of last change.
2918 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
2920 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
2921 fix bugs in signature.
2923 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
2924 Richard Biener <rguenther@suse.de>
2926 PR rtl-optimization/111267
2927 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
2928 profitable_p method to likely_profitable_p.
2929 (try_fwprop_subst_node): Update call to likely_profitable_p.
2930 Only bail-out early when !prop.likely_profitable_p for instructions
2931 that are not single sets. When comparing costs, bail-out if the
2932 cost is unchanged and !prop.likely_profitable_p.
2934 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
2936 PR c++/90464
2937 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
2938 isn't enabled by -Wunused unless -Wextra is provided, and that
2939 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
2940 -Wunused doesn't enable -Wunused-* options documented as behaving
2941 otherwise, and list them explicitly.
2943 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
2945 PR c/109708
2946 * doc/invoke.texi (Warning Options): Fix broken example and
2947 clean up/reorganize the others. Also describe what the short-form
2948 options mean.
2950 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
2952 PR c/102998
2953 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
2954 (Warning Options): Correct/edit discussion of -Warray-parameter
2955 to make the first example less confusing, and fill in missing info.
2957 2024-01-20 Jakub Jelinek <jakub@redhat.com>
2959 PR tree-optimization/113462
2960 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
2961 Handle rhs1 INTEGER_CST like SSA_NAME.
2963 2024-01-20 Jakub Jelinek <jakub@redhat.com>
2965 PR tree-optimization/113491
2966 * tree-switch-conversion.cc (switch_conversion::build_constructors):
2967 If elt.index has precision higher than sizetype, fold_convert it to
2968 sizetype.
2969 (switch_conversion::array_value_type): Return type if type is
2970 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
2971 (switch_conversion::build_arrays): Use unsigned_type_for rather than
2972 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
2973 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
2974 higher than sizetype, use sizetype as tidx type and fold_convert the
2975 subtraction to sizetype.
2977 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2979 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
2980 (riscv_vector_mode_supported_any_target_p): Ditto.
2982 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
2984 PR target/110934
2985 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
2986 (TARGET_ZERO_CALL_USED_REGS): Define.
2988 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
2990 PR target/108640
2991 * config/m68k/m68k.cc (output_andsi3): Use QImode for
2992 address adjusted for 1-byte RMW access.
2993 (output_iorsi3): Likewise.
2994 (output_xorsi3): Likewise.
2996 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
2998 * doc/invoke.texi (RISC-V Options): Add list of supported
2999 extensions.
3001 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3003 PR target/113495
3004 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3005 (RVV_VUNDEF): Ditto.
3006 * config/riscv/riscv-vsetvl.cc: Add timevar.
3008 2024-01-19 Richard Biener <rguenther@suse.de>
3010 PR debug/113488
3011 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3012 an early DIE but there should be, do not pretend there is.
3014 2024-01-19 Richard Biener <rguenther@suse.de>
3016 PR tree-optimization/113494
3017 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3018 Handle endless loop on exit. Handle re-allocated PHI.
3020 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3022 PR tree-optimization/113464
3023 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3024 optimize loads into GIMPLE_ASM stmts.
3026 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3028 PR tree-optimization/113463
3029 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3030 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3031 lhs.
3033 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3035 PR tree-optimization/113459
3036 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
3037 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
3038 of SCALAR_INT_TYPE_MODE if type has BLKmode.
3039 (vn_reference_lookup_3): Likewise. Formatting fix.
3041 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3042 Richard Biener <rguenther@suse.de>
3044 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
3045 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
3046 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
3047 but adjust_address also for BLKmode mode and MEM op0.
3049 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
3051 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
3052 extensions.
3054 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3056 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
3058 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3060 * common/config/riscv/riscv-common.cc
3061 (riscv_subset_list::parse_std_ext): Remove.
3062 (riscv_subset_list::parse_multiletter_ext): Remove.
3063 * config/riscv/riscv-subset.h
3064 (riscv_subset_list::parse_std_ext): Remove.
3065 (riscv_subset_list::parse_multiletter_ext): Remove.
3067 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3069 * common/config/riscv/riscv-common.cc
3070 (riscv_subset_list::parse_single_std_ext): New parameter.
3071 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3072 (riscv_subset_list::parse_single_ext): Ditto.
3073 (riscv_subset_list::parse): Relax the order for the input of ISA
3074 string.
3075 * config/riscv/riscv-subset.h
3076 (riscv_subset_list::parse_single_std_ext): New parameter.
3077 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3078 (riscv_subset_list::parse_single_ext): Ditto.
3080 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3082 * common/config/riscv/riscv-common.cc
3083 (riscv_subset_list::parse_base_ext): New.
3084 (riscv_subset_list::parse): Extract part of logic into
3085 riscv_subset_list::parse_base_ext.
3086 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
3087 New.
3089 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3091 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
3092 sorry message.
3094 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
3096 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
3097 UNSPEC_CLMUL_VC.
3099 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
3101 PR c/110029
3102 * doc/extend.texi (Common Variable Attributes): Explain what
3103 happens when multiple variables with cleanups are in the same scope.
3105 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3107 PR ipa/108470
3108 * doc/extend.texi (Common Function Attributes): Document that
3109 noinline also disables some interprocedural optimizations and
3110 improve flow to the part about using inline asm instead to
3111 disable calls from being optimized away completely. Remove the
3112 sentence that says noipa is mainly for internal compiler testing.
3114 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
3116 PR tree-optimization/69807
3117 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
3119 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
3121 PR target/108521
3122 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
3123 from x86 Windows Options.
3125 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3127 PR c/107942
3128 * doc/extend.texi (C Extensions): Add new section to menu.
3129 (Function Attributes): Move dangling index entries to....
3130 (Const and Volatile Functions): New section.
3132 2024-01-18 David Malcolm <dmalcolm@redhat.com>
3134 PR middle-end/112684
3135 * toplev.cc (toplev::main): Don't ICE in
3136 -fdiagnostics-generate-patch when exiting after options,
3137 since no edit context will have been created.
3139 2024-01-18 Richard Biener <rguenther@suse.de>
3141 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
3142 operands vector.
3144 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3146 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
3147 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
3149 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3150 Jin Ma <jinma@linux.alibaba.com>
3151 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3152 Christoph Müllner <christoph.muellner@vrull.eu>
3154 * config/riscv/thead.cc
3155 (th_asm_output_opcode): Rewrite some instructions.
3157 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3158 Jin Ma <jinma@linux.alibaba.com>
3159 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3160 Christoph Müllner <christoph.muellner@vrull.eu>
3162 * config/riscv/riscv.md (none,thv,rvv): New attribute.
3163 (no,yes): Add an attribute to disable alternative
3164 for xtheadvector or RVV1.0.
3165 * config/riscv/vector.md:
3166 Disable alternatives that destination register overlaps
3167 source register group for xtheadvector.
3169 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3170 Jin Ma <jinma@linux.alibaba.com>
3171 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3172 Christoph Müllner <christoph.muellner@vrull.eu>
3174 * config/riscv/riscv-vector-builtins-bases.cc
3175 (class th_loadstore_width): Define new builtin bases.
3176 (class th_extract): Define new builtin bases.
3177 (BASE): Define new builtin bases.
3178 * config/riscv/riscv-vector-builtins-bases.h:
3179 Define new builtin class.
3180 * config/riscv/riscv-vector-builtins-shapes.cc
3181 (struct th_loadstore_width_def): Define new builtin shapes.
3182 (struct th_indexed_loadstore_width_def):
3183 Define new builtin shapes.
3184 (struct th_extract_def): Define new builtin shapes.
3185 (SHAPE): Define new builtin shapes.
3186 * config/riscv/riscv-vector-builtins-shapes.h:
3187 Define new builtin shapes.
3188 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
3189 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
3190 * config/riscv/riscv-vector-builtins.h
3191 (enum required_ext): Add new XTheadVector member.
3192 (struct function_group_info): Likewise.
3193 * config/riscv/t-riscv:
3194 Add thead-vector-builtins-functions.def
3195 * config/riscv/thead-vector.md
3196 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
3197 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
3198 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
3199 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
3200 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
3201 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
3202 (@pred_th_extract<mode>): Likewise.
3203 (*pred_th_extract<mode>): Likewise.
3204 * config/riscv/thead-vector-builtins-functions.def: New file.
3206 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3207 Jin Ma <jinma@linux.alibaba.com>
3208 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3209 Christoph Müllner <christoph.muellner@vrull.eu>
3211 * config.gcc: Add files for XTheadVector intrinsics.
3212 * config/riscv/autovec.md: Guard XTheadVector.
3213 * config/riscv/predicates.md: Disable immediate vl
3214 for XTheadVector.
3215 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
3216 Add pragma for XTheadVector.
3217 * config/riscv/riscv-string.cc (riscv_expand_block_move):
3218 Guard XTheadVector.
3219 * config/riscv/riscv-v.cc (vls_mode_valid_p):
3220 Avoid autovec.
3221 * config/riscv/riscv-vector-builtins-bases.cc:
3222 Do not normalize vsetvl instructions for XTheadVector.
3223 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
3224 New check type function.
3225 (build_one): Adjust for XTheadVector.
3226 * config/riscv/riscv-vector-switch.def (ENTRY):
3227 Disable fractional mode for the XTheadVector extension.
3228 (TUPLE_ENTRY): Likewise.
3229 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
3230 Guard XTheadVector.
3231 (riscv_preferred_simd_mode): Likewsie.
3232 (riscv_autovectorize_vector_modes): Likewise.
3233 (riscv_vector_mode_supported_any_target_p): Likewise.
3234 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
3235 * config/riscv/thead.cc (th_asm_output_opcode):
3236 Rewrite vsetvl instructions.
3237 * config/riscv/vector.md:
3238 Include thead-vector.md and change fractional LMUL
3239 into 1 for vbool.
3240 * config/riscv/riscv_th_vector.h: New file.
3241 * config/riscv/thead-vector.md: New file.
3243 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3244 Jin Ma <jinma@linux.alibaba.com>
3245 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3246 Christoph Müllner <christoph.muellner@vrull.eu>
3248 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
3249 Add new function to add assembler insn code prefix/suffix.
3250 (th_asm_output_opcode):
3251 Add Thead function to add assembler insn code prefix/suffix.
3252 * config/riscv/riscv.cc (riscv_asm_output_opcode):
3253 Implement function to add assembler insn code prefix/suffix.
3254 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
3255 Add new function to add assembler insn code prefix/suffix.
3256 * config/riscv/thead.cc (th_asm_output_opcode):
3257 Implement Thead function to add assembler insn code
3258 prefix/suffix.
3260 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3261 Jin Ma <jinma@linux.alibaba.com>
3262 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3263 Christoph Müllner <christoph.muellner@vrull.eu>
3265 * common/config/riscv/riscv-common.cc
3266 (riscv_subset_list::parse): Add new vendor extension.
3267 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
3268 Add test marco.
3269 * config/riscv/riscv.opt: Add new mask.
3271 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3273 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
3274 to be conditional on macosx-version-min.
3276 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3278 * config/darwin.cc (darwin_objc1_section): Use the correct
3279 meta-data version for constant strings.
3280 (machopic_select_section): Assert if we fail to handle CFString
3281 sections as Obejctive-C meta-data or drectly.
3283 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3285 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
3286 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
3287 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
3288 versions when the object format is Mach-O.
3290 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
3292 PR target/105522
3293 * config/darwin.cc (machopic_select_section): Handle C and C++
3294 CFStrings.
3295 (darwin_rename_builtins): Move this out of the CFString code.
3296 (darwin_libc_has_function): Likewise.
3297 (darwin_build_constant_cfstring): Create an anonymous var to
3298 hold each CFString.
3299 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
3300 CFstrings.
3302 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3304 PR bootstrap/113445
3305 * haifa-sched.cc (dep_list_size): Make global.
3306 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
3307 * sched-int.h (dep_list_size): Declare.
3309 2024-01-18 Martin Jambor <mjambor@suse.cz>
3311 PR tree-optimization/110422
3312 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
3313 gotos.
3315 2024-01-18 Richard Biener <rguenther@suse.de>
3317 PR tree-optimization/113475
3318 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
3319 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
3320 (phi_analyzer::~phi_analyzer): Deallocate and free collected
3321 phi_grous.
3322 (phi_analyzer::process_phi): Record allocated phi_groups.
3324 2024-01-18 Richard Biener <rguenther@suse.de>
3326 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
3327 storage for gvec_oprnds elements.
3329 2024-01-18 Richard Biener <rguenther@suse.de>
3331 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
3332 prefer all later exits we can handle.
3333 (vect_analyze_loop_form): Free the allocated loop body.
3334 Adjust comments.
3336 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3338 * config/avr/avr-log.cc: Tabify.
3340 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3342 * config/riscv/autovec.md: Support vi variant.
3344 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3346 * config/avr/avr-devices.cc: Tabify.
3348 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3350 * config/avr/avr-c.cc: Tabify.
3352 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3354 * config/avr/driver-avr.cc: Tabify.
3356 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3358 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
3360 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3362 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
3364 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3366 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
3367 minline-strcmp, minline-strncmp, minline-strlen,
3368 -param=riscv-vector-abi): Remove Bool keywords.
3370 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3372 PR target/113122
3373 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
3374 support. Add missing space after , in emitted assembly in some
3375 cases. Formatting fixes.
3377 2024-01-18 Xi Ruoyao <xry111@xry111.site>
3379 * config/loongarch/loongarch.md (movsi_internal): Remove
3380 constraint z.
3382 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
3384 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
3385 in the diagnostic, and capitalize the device name.
3386 (print_mcu): Generate specs such that:
3387 <*check_rodata_in_ram>: New.
3388 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
3389 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
3390 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
3392 2024-01-18 Jakub Jelinek <jakub@redhat.com>
3394 PR other/113399
3395 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
3396 Common and Optimization.
3398 2024-01-18 Richard Biener <rguenther@suse.de>
3400 PR tree-optimization/113431
3401 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
3402 When there is an invariant load we might not preserve
3403 scalar order.
3405 2024-01-18 Richard Biener <rguenther@suse.de>
3407 PR tree-optimization/113374
3408 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
3409 * tree-vect-loop.cc (move_early_exit_stmts): Update
3410 virtual LC PHIs.
3411 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3412 Refactor. Preserve virtual LC PHIs on all exits.
3414 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
3416 * config/loongarch/loongarch.cc (loongarch_split_symbol):
3417 Assign the '/u' attribute to the mem.
3419 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3421 PR middle-end/110847
3422 * doc/invoke.texi (Option Summary): Document negative forms of
3423 -Wtsan and -Wxor-used-as-pow.
3424 (Warning Options): Likewise.
3426 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3428 PR target/113429
3429 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
3431 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
3433 * doc/extend.texi (Common Function Attributes): Re-alphabetize
3434 the table.
3435 (Common Variable Attributes): Likewise.
3436 (Common Type Attributes): Likewise.
3438 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3440 PR middle-end/111659
3441 * doc/extend.texi (Common Variable Attributes): Fix long lines
3442 in documentation of strict_flex_array + other minor copy-editing.
3443 Add a cross-reference to -Wstrict-flex-arrays.
3444 * doc/invoke.texi (Option Summary): Fix whitespace in tables
3445 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
3446 (C Dialect Options): Combine the docs for the two
3447 -fstrict-flex-arrays forms into a single entry. Note this option
3448 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
3449 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
3450 Minor copy-editing. Add cross references to the strict_flex_array
3451 attribute and -fstrict-flex-arrays option. Add note that this
3452 option depends on -ftree-vrp.
3454 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
3456 PR target/113221
3457 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
3458 only allow REG operands instead of allowing all.
3460 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
3462 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
3463 Remove redundant checks in else condition for readablity.
3464 (earliest_fuse_vsetvl_info) Print iteration count in debug
3465 prints.
3466 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
3467 dump details in certain cases.
3469 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
3471 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
3472 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
3473 * config/riscv/riscv-vsetvl.cc
3474 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
3475 (pass_vsetvl::execute): Use vsetvl_strategy.
3477 2024-01-17 Jan Hubicka <jh@suse.cz>
3479 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
3480 accidental hack reseting offset.
3482 2024-01-17 Jan Hubicka <jh@suse.cz>
3484 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
3485 handling of X86_TUNE_AVOID_512FMA_CHAINS.
3487 2024-01-17 Jan Hubicka <jh@suse.cz>
3488 Jakub Jelinek <jakub@redhat.com>
3490 PR tree-optimization/110852
3491 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
3492 binary operations
3493 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
3494 PRED_COMBINED_VALUE_PREDICTIONS_PHI
3495 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
3496 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
3498 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3500 PR tree-optimization/113421
3501 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
3502 comment.
3503 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
3504 formatting. Start at vop rather than cvop even if stmt is a store
3505 and needs_operand_addr.
3507 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3509 PR middle-end/113410
3510 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
3511 If access_nelts is integral with larger precision than sizetype,
3512 fold_convert it to sizetype.
3514 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3516 PR tree-optimization/113408
3517 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
3518 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
3519 to handle_cast.
3521 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3523 PR middle-end/113406
3524 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
3525 regardless of whether is_gimple_reg_type (restype) or not.
3527 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3529 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
3530 funcions -> functions, and use were instead of was.
3531 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
3532 and guaranteee -> guarantee.
3533 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
3535 2024-01-17 Jakub Jelinek <jakub@redhat.com>
3537 PR middle-end/113409
3538 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
3539 INTEGER_TYPE.
3540 (omp_extract_for_data): Use build_bitint_type rather than
3541 build_nonstandard_integer_type if either iter_type or loop->v type
3542 is BITINT_TYPE.
3543 * omp-expand.cc (expand_omp_for_generic,
3544 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
3545 BITINT_TYPE like INTEGER_TYPE.
3547 2024-01-17 Richard Biener <rguenther@suse.de>
3549 PR tree-optimization/113371
3550 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
3551 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
3552 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
3553 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
3555 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
3557 PR rtl-optimization/96388
3558 PR rtl-optimization/111554
3559 * sched-deps.cc (find_inc): Avoid exponential behavior.
3561 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3563 PR c/111693
3564 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
3565 from C++ Language Options to Warning Options. Add entry for
3566 -Wuse-after-free.
3567 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
3568 from here....
3569 (Warning Options): ...to here. Minor copy-editing to fix typo
3570 and grammar.
3572 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
3574 * config/mips/mips.cc (mips_compute_frame_info): If another
3575 register is used as global_pointer, mark $GP live false.
3577 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
3579 PR target/112973
3580 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
3581 give the section a light copy-editing pass.
3583 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
3585 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
3586 * config/aarch64/aarch64-tune.md: Regenerated.
3587 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
3589 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
3591 PR target/112573
3592 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
3593 badly formed CONST expressions.
3595 2024-01-16 Daniel Cederman <cederman@gaisler.com>
3597 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
3599 2024-01-16 Daniel Cederman <cederman@gaisler.com>
3601 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
3602 * config/sparc/sync.md (membar_storeload): Turn into named insn
3603 and add GR712RC errata workaround.
3604 (membar_v8): Add GR712RC errata workaround.
3606 2024-01-16 Andreas Larsson <andreas@gaisler.com>
3608 * config/sparc/sync.md (*membar_storeload_leon3): Remove
3609 (*membar_storeload): Enable for LEON
3611 2024-01-16 Jakub Jelinek <jakub@redhat.com>
3613 PR tree-optimization/113372
3614 PR middle-end/90348
3615 PR middle-end/110115
3616 PR middle-end/111422
3617 * cfgexpand.cc (add_scope_conflicts_2): New function.
3618 (add_scope_conflicts_1): Use it.
3620 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
3622 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
3623 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
3624 * doc/avr-mmcu.texi: Regenerate.
3626 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
3628 PR tree-optimization/113091
3629 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
3630 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
3631 scalar use with new function.
3632 (vect_bb_slp_mark_live_stmts): New function as entry to existing
3633 overriden functions with same name.
3634 (vect_slp_analyze_operations): Call new entry function to mark
3635 live statements.
3637 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3639 PR target/113404
3640 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
3641 for RVV in big-endian mode.
3643 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
3645 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
3646 (riscv_pass_in_vector_p): Delete.
3647 (riscv_init_cumulative_args): Delete the checking.
3648 (riscv_get_arg_info): Delete the checking.
3649 (riscv_function_value): Delete the checking.
3650 * config/riscv/riscv.h: Delete the member for checking.
3652 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
3654 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
3656 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
3658 * config.gcc: Include riscv_bitmanip.h.
3659 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
3660 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
3661 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
3662 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
3663 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
3664 * config/riscv/riscv-ftypes.def (2): New ftypes.
3665 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
3666 (RISCV_BUILTIN_NO_PREFIX): Likewise.
3667 * config/riscv/riscv_bitmanip.h: New file.
3669 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
3671 * config.gcc: Include riscv_crypto.h.
3672 * config/riscv/riscv_crypto.h: New file.
3674 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
3676 PR middle-end/113354
3677 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
3678 in the insn if the corresponding operand does not require hard
3679 register anymore.
3681 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
3683 PR target/107201
3684 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
3685 * config/avr/driver-avr.cc (avr_no_devlib): New function.
3686 (avr_devicespecs_file): Use it to remove -nodevicelib from the
3687 options for cores only.
3688 * config/avr/avr-arch.h (avr_get_parch): New prototype.
3689 * config/avr/avr-devices.cc (avr_get_parch): New function.
3691 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3693 PR target/113247
3694 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
3695 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
3696 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
3698 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3700 PR target/113281
3701 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
3702 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
3703 * config/riscv/riscv-vector-costs.h: New function.
3705 2024-01-15 Richard Biener <rguenther@suse.de>
3707 PR tree-optimization/113385
3708 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3709 First redirect, then split the exit edge.
3711 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3713 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
3714 Remove m_num_vector_iterations.
3715 * config/riscv/riscv-vector-costs.h: Ditto.
3717 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
3719 PR target/113156
3720 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
3721 (-mbranch-cost): Set "Optimization" flag.
3723 2024-01-15 Jakub Jelinek <jakub@redhat.com>
3725 PR tree-optimization/113370
3726 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
3727 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
3728 set it to just prec % limb_prec.
3730 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3732 PR target/113393
3733 * config/riscv/vector.md: Fix ternary attributes.
3735 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
3737 PR target/112944
3738 * configure.ac [target=avr]: Check availability of emulations
3739 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
3740 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
3741 * configure: Regenerate.
3742 * config.in: Regenerate.
3743 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
3744 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
3745 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
3746 * config/avr/avr-arch.h (enum avr_device_specific_features):
3747 Add AVR_ISA_FLMAP.
3748 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
3749 AVR_ISA_FLMAP.
3750 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
3751 (avr_set_core_architecture): Set avr_arch_index.
3752 (have_avrxmega2_flmap, have_avrxmega4_flmap)
3753 (have_avrxmega3_rodata_in_flash): Set new static const bool according
3754 to configure results.
3755 (avr_rodata_in_flash_p): New function using them.
3756 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
3757 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
3758 (avr_asm_named_section): Track avr_has_rodata_p.
3759 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
3760 and not avr_rodata_in_flash_p ().
3761 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
3762 (LINK_SPEC): Add %(link_rodata_in_ram).
3763 (LINK_ARCH_SPEC): Remove.
3764 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
3765 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
3766 const bool according to configure results.
3767 (diagnose_mrodata_in_ram): New function.
3768 (print_mcu): Generate specs with the following changes:
3769 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
3770 need to extend avr/specs.h each time we add a new bell or whistle.
3771 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
3772 -m[no-]rodata-in-ram.
3773 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
3774 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
3775 <*cpp>: Add %(cpp_rodata_in_ram).
3776 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
3777 requested.
3778 <*self_spec>: Add -mflmap or %<mflmap as needed.
3780 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
3782 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
3783 not the GPR iterator. Adjust pattern name and mode attribute
3784 accordingly.
3786 2024-01-13 Jakub Jelinek <jakub@redhat.com>
3788 PR tree-optimization/113361
3789 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3790 Fix up determination of the type for > limb_prec constants.
3792 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3794 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
3795 Add web-link to the avr-gcc wiki.
3797 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
3799 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
3800 documentation for a version without argument, which is not supported.
3802 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3804 * config/arm/arm_neon.h
3805 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
3806 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
3807 (vld1_f16_x4, vld1_f32_x4): New.
3808 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
3809 (vld1_bf16_x4): New.
3810 (vld1q_types_x4): Updated to use vld1q_x4
3811 from arm_neon_builtins.def
3812 * config/arm/arm_neon_builtins.def
3813 (vld1_x4): Updated entries.
3814 (vld1q_x4): New entries, but comes from the old vld1_x4
3815 * config/arm/neon.md
3816 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
3818 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3820 * config/arm/arm_neon.h
3821 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
3822 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
3823 (vld1_f16_x3, vld1_f32_x3): New.
3824 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
3825 (vld1_bf16_x3): New.
3826 (vld1q_types_x3): Updated to use vld1q_x3 from
3827 arm_neon_builtins.def
3828 * config/arm/arm_neon_builtins.def
3829 (vld1_x3): Updated entries.
3830 (vld1q_x3): New entries, but comes from the old vld1_x2
3831 * config/arm/neon.md
3832 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
3834 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3836 * config/arm/arm_neon.h
3837 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
3838 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
3839 (vld1_f16_x2, vld1_f32_x2): New.
3840 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
3841 (vld1_bf16_x2): New.
3842 (vld1q_types_x2): Updated to use vld1q_x2 from
3843 arm_neon_builtins.def
3844 * config/arm/arm_neon_builtins.def
3845 (vld1_x2): Updated entries.
3846 (vld1q_x2): New entries, but comes from the old vld1_x2
3847 * config/arm/neon.md
3848 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3849 neon_vld1_x2<mode>.
3851 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3853 * config/arm/arm_neon.h
3854 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
3855 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
3856 (vst1q_f16_x4, vst1q_f32_x4): New.
3857 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
3858 (vst1q_bf16_x4): New.
3859 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
3860 * config/arm/neon.md
3861 (neon_vst1q_x4<mode>): New.
3862 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
3863 * config/arm/unspecs.md
3864 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
3866 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3868 * config/arm/arm_neon.h
3869 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
3870 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
3871 (vst1q_f16_x3, vst1q_f32_x3): New.
3872 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
3873 (vst1q_bf16_x3): New.
3874 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
3875 * config/arm/neon.md
3876 (neon_vst1q_x3<mode>): New.
3877 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
3878 * config/arm/unspecs.md
3879 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
3881 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3883 * config/arm/arm_neon.h
3884 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
3885 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
3886 (vst1q_f16_x2, vst1q_f32_x2): New.
3887 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
3888 (vst1q_bf16_x2): New.
3889 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
3890 * config/arm/neon.md
3891 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3892 neon_vst1_x2<mode>.
3893 * config/arm/iterators.md
3894 (VMEMX2): New mode iterator.
3895 (VMEMX2_q): New mode attribute.
3897 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3899 * config/arm/arm_neon.h
3900 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
3901 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
3902 (vst1_f16_x4, vst1_f32_x4): New.
3903 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
3904 (vst1_bf16_x4): New.
3905 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
3906 * config/arm/neon.md (vst1_x4<mode>): New.
3908 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3910 * config/arm/arm_neon.h
3911 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
3912 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
3913 (vst1_f16_x3, vst1_f32_x3): New.
3914 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
3915 (vst1_bf16_x3): New.
3916 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
3917 * config/arm/neon.md (vst1_x3<mode>): New.
3919 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3921 * config/arm/arm_neon.h
3922 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
3923 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
3924 (vst1_f16_x2, vst1_f32_x2): New.
3925 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
3926 (vst1_bf16_x2): New.
3927 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
3928 * config/arm/neon.md (vst1_x2<mode>): New.
3930 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3932 * config/arm/arm_neon.h
3933 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
3934 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
3935 (vld1q_f16_x4, vld1q_f32_x4): New.
3936 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
3937 (vld1q_bf16_x4): New.
3938 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
3939 * config/arm/neon.md
3940 (neon_vld1_x4<mode>): New.
3941 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
3942 * config/arm/unspecs.md
3943 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
3945 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3947 * config/arm/arm_neon.h
3948 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
3949 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
3950 (vld1q_f16_x3, vld1q_f32_x3): New.
3951 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
3952 (vld1q_bf16_x3): New.
3953 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
3954 * config/arm/neon.md
3955 (neon_vld1_x3<mode>): New.
3956 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
3957 * config/arm/unspecs.md
3958 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
3960 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
3962 * config/arm/arm_neon.h
3963 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
3964 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
3965 (vld1q_f16_x2, vld1q_f32_x2): New.
3966 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
3967 (vld1q_bf16_x2): New.
3968 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
3969 * config/arm/neon.md (vld1_x2<mode>): New.
3971 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3973 PR tree-optimization/113287
3974 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
3976 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3978 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
3979 * tree-vect-loop.cc (vect_transform_loop): Likewise.
3981 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3983 PR tree-optimization/113178
3984 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
3985 alternate exits.
3987 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3989 PR tree-optimization/113237
3990 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
3991 existing LCSSA variable for exit when all exits are early break.
3993 2024-01-12 Tamar Christina <tamar.christina@arm.com>
3995 PR tree-optimization/113137
3996 PR tree-optimization/113136
3997 PR tree-optimization/113172
3998 PR tree-optimization/113178
3999 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4000 Maintain PHIs on inverted loops.
4001 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4002 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4003 latch.
4004 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4006 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4008 PR tree-optimization/113135
4009 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4010 dependency analysis.
4012 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
4014 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4015 diagnostics class member name for abort of error.
4017 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4019 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4020 format string to %s argument.
4022 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
4023 Jakub Jelinek <jakub@redhat.com>
4025 PR middle-end/113182
4026 * varasm.cc (process_pending_assemble_externals,
4027 assemble_external_libcall): Use targetm.strip_name_encoding
4028 before calling get_identifier.
4030 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4032 PR target/113196
4033 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4034 New member variable.
4035 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4036 Declare.
4037 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
4038 * config/aarch64/aarch64-simd.md
4039 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
4040 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
4041 zip2 for zero-extends to...
4042 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
4043 instruction. Fix big-endian handling.
4044 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
4045 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
4046 zip1 for zero-extends to...
4047 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
4048 Fix big-endian handling.
4049 (*aarch64_zip1_uxtl): New pattern.
4050 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
4051 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
4052 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
4053 (aarch64_gen_shareable_zero): Use it.
4054 (aarch64_split_simd_shift_p): New function.
4056 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4058 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
4059 (function_beg_insn): New macro.
4060 * function.cc (expand_function_start): Initialize function_beg_insn.
4062 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4064 PR target/112989
4065 * config/aarch64/aarch64-sve-builtins.h
4066 (function_builder::m_overload_names): Replace with...
4067 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
4068 new global.
4069 (add_overloaded_function): Update accordingly, using get_identifier
4070 to get a GGC-friendly record of the name.
4072 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4074 PR target/112989
4075 * config/aarch64/aarch64-sve-builtins.def: Don't include
4076 aarch64-sve-builtins-sme.def.
4077 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
4078 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
4079 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
4080 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
4081 requires AARCH64_FL_SME2.
4082 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
4083 AARCH64_FL_SME adjustment here.
4084 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
4085 include SME intrinsics.
4086 (sme_function_groups): New array.
4087 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
4088 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
4090 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4092 PR target/113281
4093 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
4094 (struct cpu_vector_cost): Add regmove struct.
4095 (get_vector_costs): Export as global.
4096 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
4097 (costs::add_stmt_cost): Ditto.
4098 * config/riscv/riscv.cc (get_common_costs): Export global function.
4100 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4102 PR tree-optimization/113334
4103 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
4104 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
4105 to determine if number should be extended by all ones rather than zero
4106 extended.
4108 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4110 PR tree-optimization/113330
4111 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
4112 too large size.
4114 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4116 PR tree-optimization/113323
4117 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
4118 check for lhs being large/huge _BitInt not in m_names.
4120 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4122 PR tree-optimization/113316
4123 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
4124 uninitialized large/huge _BitInt arguments to calls.
4126 2024-01-12 Jakub Jelinek <jakub@redhat.com>
4128 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
4129 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
4130 CEIL (TYPE_PRECISION (t), limb_prec).
4131 (bitint_large_huge::handle_cast): Likewise.
4133 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
4135 PR sanitizer/113284
4136 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4137 Use assemble_function_label_final () for Power ELF V1 ABI.
4138 * output.h (assemble_function_label_final): New function.
4139 * varasm.cc (assemble_function_label_raw): Use
4140 assemble_function_label_final ().
4141 (assemble_function_label_final): New function.
4143 2024-01-12 Richard Biener <rguenther@suse.de>
4145 PR middle-end/113344
4146 * match.pd ((double)float CMP (double)float -> float CMP float):
4147 Perform result type check only for vectors.
4148 * fold-const.cc (fold_binary_loc): Likewise.
4150 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4152 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
4153 (usdot_prod<mode>): Ditto.
4154 (sdot_prod<mode>): Ditto.
4155 (udot_prod<mode>): Ditto.
4157 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
4159 PR target/113288
4160 * config/i386/i386-c.cc (ix86_target_macros_internal):
4161 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
4163 2024-01-12 Richard Biener <rguenther@suse.de>
4165 PR target/112280
4166 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
4167 Do not generate code when d.testing_p.
4169 2024-01-12 liuhongt <hongtao.liu@intel.com>
4171 PR target/113039
4172 * doc/invoke.texi (fcf-protection=): Update documents.
4174 2024-01-12 Pan Li <pan2.li@intel.com>
4176 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
4177 comments of predicate func riscv_v_ext_mode_p.
4179 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
4181 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
4182 Modify ABI-name length of vfloat16m8_t
4184 2024-01-12 Li Wei <liwei@loongson.cn>
4186 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
4187 Adjust.
4189 2024-01-12 Li Wei <liwei@loongson.cn>
4191 * config/loongarch/loongarch.md (add<mode>3): Removed.
4192 (*addsi3): New.
4193 (addsi3): Ditto.
4194 (adddi3): Ditto.
4195 (*addsi3_extended): Removed.
4196 (addsi3_extended): New.
4198 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
4200 * config/riscv/thead.md: Add limits for splits.
4202 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4204 PR middle-end/113322
4205 * expr.cc (do_store_flag): Don't try single bit tests with
4206 comparison on vector types.
4208 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
4210 PR tree-optimization/113301
4211 * match.pd (`1/x`): Delay signed case until late.
4213 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4215 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
4216 and -msp8 to...
4217 (AVR Internal Options): ...this new @subsubsection.
4219 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
4221 PR rtl-optimization/112918
4222 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
4223 (in_class_p): Restrict condition for narrowing class in case of
4224 allow_all_reload_class_changes_p.
4225 (process_alt_operands): Try to match operand without and with
4226 narrowing reg class. Discourage narrowing the class. Finish insn
4227 matching only if there is no class narrowing.
4228 (curr_insn_transform): Pass true to in_class_p for reg operand win.
4230 2024-01-11 Richard Biener <rguenther@suse.de>
4232 PR tree-optimization/112505
4233 * tree-vect-loop.cc (vectorizable_induction): Reject
4234 bit-precision induction.
4236 2024-01-11 Richard Biener <rguenther@suse.de>
4238 PR tree-optimization/113126
4239 * match.pd ((double)float CMP (double)float -> float CMP float):
4240 Make sure the boolean type is the same.
4241 * fold-const.cc (fold_binary_loc): Likewise.
4243 2024-01-11 Richard Biener <rguenther@suse.de>
4245 PR tree-optimization/112636
4246 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
4247 estimate_numbers_of_iterations before querying
4248 get_max_loop_iterations_int.
4249 (pass_ch::execute): Initialize SCEV and loops appropriately.
4251 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
4253 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
4254 Reduced Tiny.
4255 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
4256 * doc/extend.texi (AVR Variable Attributes): Improve documentation
4257 of io, io_low and address attributes.
4258 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
4259 * doc/avr-mmcu.texi: Rebuild.
4261 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
4263 PR target/113233
4264 * config/loongarch/genopts/loongarch.opt.in: Mark options with
4265 the "Save" property.
4266 * config/loongarch/loongarch.opt: Same.
4267 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
4268 according to la_target.
4269 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
4270 RESTORE} for the la_target structure; Rename option conditions
4271 to have the same "la_" prefix.
4272 * config/loongarch/loongarch.h: Same.
4274 2024-01-11 Pan Li <pan2.li@intel.com>
4276 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
4277 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
4279 2024-01-11 Alex Coplan <alex.coplan@arm.com>
4281 PR target/113077
4282 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
4283 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
4284 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
4285 synthesize these if needed. Update caller ...
4286 (ldp_bb_info::fuse_pair): ... here.
4287 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
4288 and either insn is frame-related.
4289 (find_trailing_add): Punt on frame-related insns.
4290 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
4291 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
4293 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
4295 * config/mips/mips.cc (mips_start_function_definition):
4296 Add ATTRIBUTE_UNUSED.
4298 2024-01-11 Richard Biener <rguenther@suse.de>
4300 PR middle-end/112740
4301 * expr.cc (store_constructor): Check the integer vector
4302 mask has a single bit per element before using sign-extension
4303 to expand an uniform vector.
4305 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4307 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
4308 preempt VLS on unknown NITERS loop.
4310 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
4312 * doc/invoke.texi: Add -mevex512.
4314 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
4316 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
4317 (*nor<mode>3): Likewise.
4318 (nor<mode>3): Likewise.
4319 (*negsi2_extended): New template.
4320 (*<optab>si3_internal): Likewise.
4321 (*one_cmplsi2_internal): Likewise.
4322 (*norsi3_internal): Likewise.
4323 (*<optab>nsi_internal): Likewise.
4324 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
4325 modified bit operation to make the optimization work.
4327 2024-01-11 liuhongt <hongtao.liu@intel.com>
4329 PR target/104401
4330 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
4332 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4334 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
4335 (get_vector_costs): Ditto.
4336 (riscv_builtin_vectorization_cost): Ditto.
4338 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4340 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
4342 2024-01-10 Antoni Boucher <bouanto@zoho.com>
4344 PR jit/111396
4345 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
4346 ipa_free_size_summary.
4347 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
4348 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
4349 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
4350 * ipa-prop.h (ipa_prop_cc_finalize): New function.
4351 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
4352 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
4353 ipa_sra_cc_finalize): New functions.
4354 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
4355 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
4356 ipa_sra_cc_finalize
4357 Include ipa-utils.h.
4359 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
4361 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
4362 (th_int_get_save_adjustment): Likewise.
4363 (th_int_adjust_cfi_prologue): Likewise.
4364 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
4365 (TH_INT_INTERRUPT): New macro.
4366 (riscv_expand_prologue): Add the processing of XTheadInt.
4367 (riscv_expand_epilogue): Likewise.
4368 * config/riscv/riscv.h (BITSET_P): Moved to here.
4369 * config/riscv/riscv.md: New unspec.
4370 * config/riscv/thead.cc (th_int_get_mask): New function.
4371 (th_int_get_save_adjustment): Likewise.
4372 (th_int_adjust_cfi_prologue): Likewise.
4373 * config/riscv/thead.md (th_int_push): New pattern.
4374 (th_int_pop): new pattern.
4376 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4378 PR tree-optimization/112468
4379 * doc/sourcebuild.texi: Document ifn_copysign.
4380 * match.pd: Only apply transformation if target supports the IFN.
4382 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
4384 PR tree-optimization/112581
4385 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
4386 mark_ssa_maybe_undefs.
4387 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
4388 variables can not be reassociated.
4389 (init_range_entry): Check for uninitialized variables too.
4390 (init_reassoc): Call mark_ssa_maybe_undefs.
4392 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
4394 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
4395 Also handle sign extension.
4397 2024-01-10 Alex Coplan <alex.coplan@arm.com>
4399 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4400 to 0.
4401 (-mlate-ldp-fusion): Likewise.
4403 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4405 PR tree-optimization/113287
4406 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
4407 instead of using BRANCH_EDGE to determine true edge.
4409 2024-01-10 Richard Biener <rguenther@suse.de>
4411 PR tree-optimization/113078
4412 * tree-vect-loop.cc (check_reduction_path): Canonicalize
4413 .COND_SUB to .COND_ADD.
4415 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4417 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
4418 Handle prefix mappings before calling find_opt.
4419 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
4420 "-fno-"-prefixed command-line option.
4421 * opts-common.cc (get_option_prefix_remapping): New.
4422 * opts.h (get_option_prefix_remapping): New decl.
4424 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4426 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
4427 m_urlifier to pp_output_formatted_text.
4428 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
4429 (obstack_append_string): New overload, taking a length.
4430 (urlify_quoted_string): Pass in an obstack ptr, rather than using
4431 that of the pp's buffer. Generalize to handle trailing text in
4432 the buffer beyond the run of quoted text.
4433 (class quoting_info): New.
4434 (on_begin_quote): New.
4435 (on_end_quote): New.
4436 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
4437 it to calls to on_begin_quote and on_end_quote.
4438 (struct auto_obstack): New.
4439 (quoting_info::handle_phase_3): New.
4440 (pp_output_formatted_text): Add urlifier param. Use it if there
4441 is deferred urlification. Delete m_quotes.
4442 (selftest::pp_printf_with_urlifier): Pass urlifier to
4443 pp_output_formatted_text.
4444 (selftest::test_urlification): Update results for the existing
4445 case of quoted text stradding chunks; add more such test cases.
4446 * pretty-print.h (class quoting_info): New forward decl.
4447 (chunk_info::m_quotes): New field.
4448 (pp_output_formatted_text): Add optional urlifier param.
4450 2024-01-10 David Malcolm <dmalcolm@redhat.com>
4452 * pretty-print.cc (selftest::test_pp_format): Add selftest
4453 coverage for numbered args.
4455 2024-01-10 Tamar Christina <tamar.christina@arm.com>
4457 PR tree-optimization/113144
4458 PR tree-optimization/113145
4459 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4460 Update all BB that the original exits dominated.
4462 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
4464 * dwarf2out.cc (modified_type_die): Extend the support of reverse
4465 storage order to enumeration types if -gstrict-dwarf is not passed.
4466 (gen_enumeration_type_die): Add REVERSE parameter and generate the
4467 DIE immediately after the existing one if it is true.
4468 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
4469 call to gen_enumeration_type_die.
4470 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
4471 first recursive call as well as the call to gen_tagged_type_die.
4472 (gen_type_die): Add REVERSE parameter and pass it in the call to
4473 gen_type_die_with_usage.
4475 2024-01-10 Jakub Jelinek <jakub@redhat.com>
4477 PR tree-optimization/113120
4478 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
4479 with root->size TYPE_PRECISION don't build anything new.
4480 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
4481 rather than build_nonstandard_integer_type.
4483 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
4485 * config/i386/i386.opt: Adjust document.
4486 * doc/invoke.texi: Add description for
4487 -mapx-inline-asm-use-gpr32.
4489 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4491 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
4492 (avg<v_double_trunc>3_floor): New pattern.
4493 (<u>avg<v_double_trunc>3_ceil): Remove.
4494 (avg<v_double_trunc>3_ceil): New pattern.
4495 (uavg<mode>3_floor): Ditto.
4496 (uavg<mode>3_ceil): Ditto.
4497 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
4498 (enum insn_type): Ditto.
4499 * config/riscv/riscv-v.cc: Ditto.
4500 * config/riscv/vector-iterators.md (ashiftrt): Remove.
4501 (ASHIFTRT): Ditto.
4502 * config/riscv/vector.md: Add VLS modes.
4504 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4506 PR target/111480
4507 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
4508 (vczlsbb_char): New int attribute.
4509 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
4510 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
4511 (*vctzlsbb_zext_<mode>): Rename to ...
4512 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
4513 cover vclzlsbb.
4515 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4517 PR target/112606
4518 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
4519 of the last argument from altivec_register_operand to any_operand. If
4520 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
4521 otherwise if it doesn't satisfy altivec_register_operand, force it to
4522 REG using copy_to_mode_reg.
4524 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
4526 PR middle-end/113100
4527 * builtins.cc (expand_builtin_stack_address): Guard stack point
4528 adjustment with SPARC_STACK_BOUNDARY_HACK.
4530 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4532 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
4533 argument string definitions.
4534 * config/loongarch/loongarch-str.h: Same.
4535 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
4536 as aliases to -mexplicit-relocs={always,none}
4537 * config/loongarch/loongarch.opt: Regenerate.
4538 * config/loongarch/loongarch.cc: Same.
4540 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4542 * config/loongarch/loongarch-def.h: Define constants with
4543 enums instead of Macros.
4545 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4547 * config/loongarch/genopts/loongarch-strings: Rename.
4548 * config/loongarch/genopts/loongarch.opt.in: Same.
4549 * config/loongarch/loongarch-cpu.cc: Same.
4550 * config/loongarch/loongarch-def.cc: Same.
4551 * config/loongarch/loongarch-def.h: Same.
4552 * config/loongarch/loongarch-opts.cc: Same.
4553 * config/loongarch/loongarch-opts.h: Same.
4554 * config/loongarch/loongarch-str.h: Same.
4555 * config/loongarch/loongarch.opt: Same.
4557 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
4559 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
4560 variable with the common la_ prefix.
4561 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
4562 flags as saved using TargetVariable.
4563 * config/loongarch/loongarch.opt: Same.
4564 * config/loongarch/loongarch-def.h: Define evolution_set to
4565 mark changes to the -march default.
4566 * config/loongarch/loongarch-driver.cc: Same.
4567 * config/loongarch/loongarch-opts.cc: Same.
4568 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
4569 conditions around the la_target structure.
4570 * config/loongarch/loongarch.cc: Same.
4571 * config/loongarch/loongarch.md: Same.
4572 * config/loongarch/loongarch-builtins.cc: Same.
4573 * config/loongarch/loongarch-c.cc: Same.
4574 * config/loongarch/lasx.md: Same.
4575 * config/loongarch/lsx.md: Same.
4576 * config/loongarch/sync.md: Same.
4578 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
4580 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
4581 no less.
4583 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
4585 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
4587 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4589 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
4590 restart_loop.
4591 (vectorizable_live_operation): Likewise.
4593 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4595 PR tree-optimization/113199
4596 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
4597 BIT_FIELD_REF.
4599 2024-01-09 Jakub Jelinek <jakub@redhat.com>
4601 PR target/113270
4602 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
4603 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
4604 GTY(()) declaration before the definition, drop GTY(()) drom the
4605 definition.
4607 2024-01-09 Richard Biener <rguenther@suse.de>
4609 PR tree-optimization/113026
4610 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
4611 redundant and wrong niter bound setting. Move niter
4612 bound adjustment down.
4614 2024-01-09 Tamar Christina <tamar.christina@arm.com>
4616 PR middle-end/113163
4617 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
4618 Reject non-linear inductions that aren't supported.
4620 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
4622 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
4623 left shift implementation strategies.
4624 (arc_shift_info): Type for each entry of the shift strategy table.
4625 (arc_shift_context_idx): Return a integer value for each code
4626 generation context, used as an index
4627 (arc_ashl_alg): Table indexed by context and shifted bit count.
4628 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
4629 left shift implementation.
4630 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
4631 provide accurate costs, when optimizing for speed or size.
4633 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4635 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
4637 2024-01-09 Julian Brown <julian@codesourcery.com>
4639 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
4640 processed out before gimplification.
4641 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
4642 * tree.def (OMP_ARRAY_SECTION): New tree code.
4644 2024-01-09 Jakub Jelinek <jakub@redhat.com>
4646 PR tree-optimization/113210
4647 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
4648 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
4649 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
4650 minus 1.
4652 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
4654 PR rtl-optimization/113140
4655 * reorg.cc (fill_slots_from_thread): If we are to branch after the
4656 last instruction of the function, create an end label.
4658 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
4659 Hongtao Liu <hongtao.liu@intel.com>
4661 PR target/112992
4662 * config/i386/i386-expand.cc
4663 (ix86_convert_const_wide_int_to_broadcast): Allow call to
4664 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
4665 (ix86_broadcast_from_constant): Revert recent change; Return a
4666 suitable MEMREF independently of mode/target combinations.
4667 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
4668 to decide whether expansion is possible/preferrable. Only try
4669 forcing DImode constants to memory (and trying again) if calling
4670 ix86_expand_vector_init_duplicate fails with an DImode immediate
4671 constant.
4672 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
4673 V4SImode for suitable immediate constants.
4674 <case E_V4DImode>: Try using V8SImode for suitable constants.
4675 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
4676 <case E_V2HImode>: Likewise.
4677 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
4678 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
4679 <label widen>: Handle CONT_INTs via simplify_binary_operation.
4680 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
4681 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
4682 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
4683 (ix86_expand_vector_init): Move try using a broadcast for all_same
4684 with ix86_expand_vector_init_duplicate before using constant pool.
4686 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
4688 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
4690 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
4692 * config/arm/arm-cpus.in (cortex-m52): New cpu.
4693 * config/arm/arm-tables.opt: Regenerate.
4694 * config/arm/arm-tune.md: Regenerate.
4696 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
4698 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
4699 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
4700 (@vec_concatz<mode>): New insn pattern.
4701 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
4702 Handle VALS containing two vectors.
4704 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4706 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
4707 (vundefined): Ditto.
4709 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
4711 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4712 Add new function_base for crypto vector.
4713 (class bitmanip): Ditto.
4714 (class b_reverse):Ditto.
4715 (class vwsll): Ditto.
4716 (class clmul): Ditto.
4717 (class vg_nhab): Ditto.
4718 (class crypto_vv):Ditto.
4719 (class crypto_vi):Ditto.
4720 (class vaeskf2_vsm3c):Ditto.
4721 (class vsm3me): Ditto.
4722 (BASE): Add BASE declaration for crypto vector.
4723 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4724 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4725 Add crypto vector intrinsic definition.
4726 (vbrev): Ditto.
4727 (vclz): Ditto.
4728 (vctz): Ditto.
4729 (vwsll): Ditto.
4730 (vandn): Ditto.
4731 (vbrev8): Ditto.
4732 (vrev8): Ditto.
4733 (vrol): Ditto.
4734 (vror): Ditto.
4735 (vclmul): Ditto.
4736 (vclmulh): Ditto.
4737 (vghsh): Ditto.
4738 (vgmul): Ditto.
4739 (vaesef): Ditto.
4740 (vaesem): Ditto.
4741 (vaesdf): Ditto.
4742 (vaesdm): Ditto.
4743 (vaesz): Ditto.
4744 (vaeskf1): Ditto.
4745 (vaeskf2): Ditto.
4746 (vsha2ms): Ditto.
4747 (vsha2ch): Ditto.
4748 (vsha2cl): Ditto.
4749 (vsm4k): Ditto.
4750 (vsm4r): Ditto.
4751 (vsm3me): Ditto.
4752 (vsm3c): Ditto.
4753 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4754 Add new function_shape for crypto vector.
4755 (struct crypto_vi_def): Ditto.
4756 (struct crypto_vv_no_op_type_def): Ditto.
4757 (SHAPE): Add SHAPE declaration of crypto vector.
4758 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4759 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4760 Add new data type for crypto vector.
4761 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4762 (vuint32mf2_t): Ditto.
4763 (vuint32m1_t): Ditto.
4764 (vuint32m2_t): Ditto.
4765 (vuint32m4_t): Ditto.
4766 (vuint32m8_t): Ditto.
4767 (vuint64m1_t): Ditto.
4768 (vuint64m2_t): Ditto.
4769 (vuint64m4_t): Ditto.
4770 (vuint64m8_t): Ditto.
4771 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4772 Add new data struct for crypto vector.
4773 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4774 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4775 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4777 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
4779 PR sanitizer/113251
4780 * varasm.cc (assemble_function_label_raw): Do not call
4781 asan_function_start () without the current function.
4783 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
4785 PR target/113225
4786 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
4787 extern and kernel_helper attributed function decls.
4789 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
4791 * btfout.cc (output_btf_strs): Changed.
4793 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
4795 * config/gcn/mkoffload.cc (main): Handle gfx1100
4796 when setting the default XNACK.
4798 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
4800 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
4801 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
4802 (ASM_SPEC): Handle gfx1100.
4803 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
4804 (enum gcn_isa): Add ISA_RDNA3.
4805 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
4806 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4807 * config/gcn/gcn.cc (gcn_option_override,
4808 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
4809 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
4810 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4811 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
4812 with gfx1100.
4813 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
4814 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
4815 __gfx1100__.
4816 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4817 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
4818 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
4819 (isa_has_combined_avgprs, main): Handle gfx1100.
4820 * config/gcn/t-omp-device (isa): Add gfx1100.
4822 2024-01-08 Richard Biener <rguenther@suse.de>
4824 * doc/invoke.texi (-mmovbe): Clarify.
4826 2024-01-08 Richard Biener <rguenther@suse.de>
4828 PR tree-optimization/113026
4829 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
4830 Avoid an epilog in more cases.
4831 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
4832 epilogues niter upper bounds and estimates.
4834 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4836 PR tree-optimization/113228
4837 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
4839 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4841 PR tree-optimization/113120
4842 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
4843 large _BitInt zero INTEGER_CST PHI argument.
4845 2024-01-08 Jakub Jelinek <jakub@redhat.com>
4847 PR tree-optimization/113119
4848 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
4849 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
4850 is before REALPART_EXPR.
4852 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
4854 PR target/112952
4855 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
4856 range when diagnosing attribute "io" and "io_low" are out of range.
4857 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
4858 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
4859 in contexts other than static storage.
4860 (avr_asm_output_aligned_decl_common): Move output of decls with
4861 attribute "address", "io", and "io_low" to...
4862 (avr_output_addr_attrib): ...this new function.
4863 (avr_asm_asm_output_aligned_bss): Remove output for decls with
4864 attribute "address", "io", and "io_low".
4865 (avr_encode_section_info): Rectify handling of decls with attribute
4866 "address", "io", and "io_low".
4868 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
4870 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
4871 (elf_flags): Remove XNACK from the default value.
4872 (main): Set a default XNACK according to the arch.
4874 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
4876 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
4877 (process_asm): Don't count avgprs.
4879 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
4881 * config/i386/i386.opt: Add supported sub-features.
4882 * doc/extend.texi: Add description for target attribute.
4884 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
4886 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
4888 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
4889 Uros Bizjak <ubizjak@gmail.com>
4891 PR target/113231
4892 * config/i386/i386-features.cc (compute_convert_gain): Include
4893 the overhead of explicit load and store (movd) instructions when
4894 converting non-store scalar operations with memory destinations.
4895 Various indentation whitespace fixes.
4897 2024-01-07 Tamar Christina <tamar.christina@arm.com>
4899 * config/arm/neon.md (cbranch<mode>4): New.
4901 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4903 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
4905 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
4907 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
4909 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4911 PR target/113248
4912 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
4913 Update the MAX_SEW.
4915 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4917 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
4918 (variable_vectorized_p): Teach loop invariant.
4919 (has_unexpected_spills_p): Ditto.
4921 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4923 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
4924 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
4925 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
4927 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
4929 PR target/113104
4930 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
4931 (aarch64-vect-compare-costs): ...this.
4932 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
4933 Replace with...
4934 (-param=aarch64-vect-compare-costs=): ...this new param.
4935 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
4936 Don't disable it when vectorizing for Advanced SIMD only.
4937 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
4938 whenever aarch64_vect_compare_costs is true.
4940 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
4942 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
4943 Modify the method of determining the memory offset of [x]vld/[x]vst.
4944 (lasx_mxst_<lasxfmt_f>): Likewise.
4945 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
4946 (loongarch_address_insns): Likewise.
4947 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
4948 (lsx_st_<lsxfmt_f>): Likewise.
4949 * config/loongarch/predicates.md (aq10b_operand): Likewise.
4950 (aq10h_operand): Likewise.
4951 (aq10w_operand): Likewise.
4952 (aq10d_operand): Likewise.
4954 2024-01-05 Alex Coplan <alex.coplan@arm.com>
4956 PR target/113217
4957 * config/aarch64/aarch64-ldp-fusion.cc
4958 (ldp_bb_info::try_fuse_pair): If the second access can throw,
4959 narrow the move range to exactly that insn.
4961 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
4963 * asan.cc (asan_function_start): Drop switch_to_section ().
4964 (asan_emit_stack_protection): Set .LASANPC alignment.
4965 * config/i386/i386.cc: Use assemble_function_label_raw ()
4966 instead of ASM_OUTPUT_LABEL ().
4967 * config/s390/s390.cc (s390_asm_output_function_label):
4968 Likewise.
4969 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
4970 * final.cc (final_start_function_1): Drop
4971 asan_function_start ().
4972 * output.h (assemble_function_label_raw): New function.
4973 * varasm.cc (assemble_function_label_raw): Likewise.
4975 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
4977 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
4978 Use ASM_OUTPUT_FUNCTION_LABEL ().
4979 * config/alpha/alpha.cc (alpha_start_function): Likewise.
4980 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4981 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
4982 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4983 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4984 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
4985 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4986 * config/ia64/ia64.cc (ia64_start_function): Likewise.
4987 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
4988 Likewise.
4989 * config/microblaze/microblaze.cc (microblaze_function_prologue):
4990 Likewise.
4991 * config/mips/mips.cc (mips_start_unique_function): Return the
4992 tree.
4993 (mips_start_function_definition): Use
4994 ASM_OUTPUT_FUNCTION_LABEL ().
4995 (mips_finish_stub): Pass the tree to
4996 mips_start_function_definition ().
4997 (mips16_build_function_stub): Likewise.
4998 (mips16_build_call_stub): Likewise.
4999 (mips_output_function_prologue): Likewise.
5000 * config/pa/pa.cc (pa_output_function_label): Use
5001 ASM_OUTPUT_FUNCTION_LABEL ().
5002 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5003 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5004 Likewise.
5005 (rs6000_xcoff_declare_function_name): Likewise.
5007 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5009 PR tree-optimization/113201
5010 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5011 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5013 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5015 PR tree-optimization/90693
5016 * tree-ssa-math-opts.cc (match_single_bit_test): If
5017 tree_expr_nonzero_p (arg), remember it in the second argument to
5018 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5019 arg ^ (arg - 1) > arg - 1.
5020 * internal-fn.cc (expand_POPCOUNT): If second argument to
5021 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5022 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5024 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
5026 * config/riscv/riscv-v.cc (expand_load_store):
5027 Remove `value`.
5028 (expand_cond_len_op): Ditto.
5029 (expand_gather_scatter): Ditto.
5030 (expand_lanes_load_store): Ditto.
5031 (expand_fold_extract_last): Ditto.
5033 2024-01-05 Pan Li <pan2.li@intel.com>
5035 Revert:
5036 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5038 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5039 Add new function_base for crypto vector.
5040 (class bitmanip): Ditto.
5041 (class b_reverse):Ditto.
5042 (class vwsll): Ditto.
5043 (class clmul): Ditto.
5044 (class vg_nhab): Ditto.
5045 (class crypto_vv):Ditto.
5046 (class crypto_vi):Ditto.
5047 (class vaeskf2_vsm3c):Ditto.
5048 (class vsm3me): Ditto.
5049 (BASE): Add BASE declaration for crypto vector.
5050 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5051 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5052 Add crypto vector intrinsic definition.
5053 (vbrev): Ditto.
5054 (vclz): Ditto.
5055 (vctz): Ditto.
5056 (vwsll): Ditto.
5057 (vandn): Ditto.
5058 (vbrev8): Ditto.
5059 (vrev8): Ditto.
5060 (vrol): Ditto.
5061 (vror): Ditto.
5062 (vclmul): Ditto.
5063 (vclmulh): Ditto.
5064 (vghsh): Ditto.
5065 (vgmul): Ditto.
5066 (vaesef): Ditto.
5067 (vaesem): Ditto.
5068 (vaesdf): Ditto.
5069 (vaesdm): Ditto.
5070 (vaesz): Ditto.
5071 (vaeskf1): Ditto.
5072 (vaeskf2): Ditto.
5073 (vsha2ms): Ditto.
5074 (vsha2ch): Ditto.
5075 (vsha2cl): Ditto.
5076 (vsm4k): Ditto.
5077 (vsm4r): Ditto.
5078 (vsm3me): Ditto.
5079 (vsm3c): Ditto.
5080 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5081 Add new function_shape for crypto vector.
5082 (struct crypto_vi_def): Ditto.
5083 (struct crypto_vv_no_op_type_def): Ditto.
5084 (SHAPE): Add SHAPE declaration of crypto vector.
5085 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5086 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5087 Add new data type for crypto vector.
5088 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5089 (vuint32mf2_t): Ditto.
5090 (vuint32m1_t): Ditto.
5091 (vuint32m2_t): Ditto.
5092 (vuint32m4_t): Ditto.
5093 (vuint32m8_t): Ditto.
5094 (vuint64m1_t): Ditto.
5095 (vuint64m2_t): Ditto.
5096 (vuint64m4_t): Ditto.
5097 (vuint64m8_t): Ditto.
5098 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5099 Add new data struct for crypto vector.
5100 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5101 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5102 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5104 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5106 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5107 Add new function_base for crypto vector.
5108 (class bitmanip): Ditto.
5109 (class b_reverse):Ditto.
5110 (class vwsll): Ditto.
5111 (class clmul): Ditto.
5112 (class vg_nhab): Ditto.
5113 (class crypto_vv):Ditto.
5114 (class crypto_vi):Ditto.
5115 (class vaeskf2_vsm3c):Ditto.
5116 (class vsm3me): Ditto.
5117 (BASE): Add BASE declaration for crypto vector.
5118 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5119 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5120 Add crypto vector intrinsic definition.
5121 (vbrev): Ditto.
5122 (vclz): Ditto.
5123 (vctz): Ditto.
5124 (vwsll): Ditto.
5125 (vandn): Ditto.
5126 (vbrev8): Ditto.
5127 (vrev8): Ditto.
5128 (vrol): Ditto.
5129 (vror): Ditto.
5130 (vclmul): Ditto.
5131 (vclmulh): Ditto.
5132 (vghsh): Ditto.
5133 (vgmul): Ditto.
5134 (vaesef): Ditto.
5135 (vaesem): Ditto.
5136 (vaesdf): Ditto.
5137 (vaesdm): Ditto.
5138 (vaesz): Ditto.
5139 (vaeskf1): Ditto.
5140 (vaeskf2): Ditto.
5141 (vsha2ms): Ditto.
5142 (vsha2ch): Ditto.
5143 (vsha2cl): Ditto.
5144 (vsm4k): Ditto.
5145 (vsm4r): Ditto.
5146 (vsm3me): Ditto.
5147 (vsm3c): Ditto.
5148 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5149 Add new function_shape for crypto vector.
5150 (struct crypto_vi_def): Ditto.
5151 (struct crypto_vv_no_op_type_def): Ditto.
5152 (SHAPE): Add SHAPE declaration of crypto vector.
5153 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5154 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5155 Add new data type for crypto vector.
5156 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5157 (vuint32mf2_t): Ditto.
5158 (vuint32m1_t): Ditto.
5159 (vuint32m2_t): Ditto.
5160 (vuint32m4_t): Ditto.
5161 (vuint32m8_t): Ditto.
5162 (vuint64m1_t): Ditto.
5163 (vuint64m2_t): Ditto.
5164 (vuint64m4_t): Ditto.
5165 (vuint64m8_t): Ditto.
5166 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5167 Add new data struct for crypto vector.
5168 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5169 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5170 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5172 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5174 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5176 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
5178 PR tree-optimization/113186
5179 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
5180 Match `^` with the `==` for 1bit integral types.
5181 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
5182 integral types.
5184 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5186 * toplev.cc (general_init): Pass lang_mask to urlifier.
5188 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5190 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
5191 param.
5192 (diagnostic_context::make_option_url): Update for lang_mask param.
5193 * gcc-urlifier.cc: Include "opts.h" and "options.h".
5194 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
5195 (gcc_urlifier::m_lang_mask): New field.
5196 (doc_urls): Make static.
5197 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
5198 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5199 Look for an option by name before trying a binary search in
5200 doc_urls.
5201 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
5202 (gcc_urlifier::get_url_suffix_for_option): New.
5203 (make_gcc_urlifier): Add lang_mask param.
5204 (selftest::gcc_urlifier_cc_tests): Update for above changes.
5205 Verify that a URL is found for "-fpack-struct".
5206 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
5207 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
5208 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
5209 to make_gcc_urlifier.
5210 * opts-diagnostic.h (get_option_url): Add lang_mask param.
5211 * opts.cc (get_option_html_page): Remove special-casing for
5212 analyzer and LTO.
5213 (get_option_url_suffix): New.
5214 (get_option_url): Reimplement.
5215 (selftest::test_get_option_html_page): Rename to...
5216 (selftest::test_get_option_url_suffix): ...this and update for
5217 above changes.
5218 (selftest::opts_cc_tests): Update for renaming.
5219 * opts.h: Include "rich-location.h".
5220 (get_option_url_suffix): New decl.
5222 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5224 * Makefile.in (ALL_OPT_URL_FILES): New.
5225 (GCC_OBJS): Add options-urls.o.
5226 (OBJS): Likewise.
5227 (OBJS-libcommon): Likewise.
5228 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
5229 inputs to opt-gather.awk.
5230 (options-urls.cc): New Makefile target.
5231 * opt-functions.awk (url_suffix): New function.
5232 (lang_url_suffix): New function.
5233 * options-urls-cc-gen.awk: New file.
5234 * opts.h (get_opt_url_suffix): New decl.
5236 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5238 * params.opt.urls: New file, autogenerated by
5239 regenerate-opt-urls.py.
5241 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5243 * common.opt.urls: New file, autogenerated by
5244 regenerate-opt-urls.py.
5245 * config/aarch64/aarch64.opt.urls: Likewise.
5246 * config/alpha/alpha.opt.urls: Likewise.
5247 * config/alpha/elf.opt.urls: Likewise.
5248 * config/arc/arc-tables.opt.urls: Likewise.
5249 * config/arc/arc.opt.urls: Likewise.
5250 * config/arm/arm-tables.opt.urls: Likewise.
5251 * config/arm/arm.opt.urls: Likewise.
5252 * config/arm/vxworks.opt.urls: Likewise.
5253 * config/avr/avr.opt.urls: Likewise.
5254 * config/bpf/bpf.opt.urls: Likewise.
5255 * config/c6x/c6x-tables.opt.urls: Likewise.
5256 * config/c6x/c6x.opt.urls: Likewise.
5257 * config/cris/cris.opt.urls: Likewise.
5258 * config/cris/elf.opt.urls: Likewise.
5259 * config/csky/csky.opt.urls: Likewise.
5260 * config/csky/csky_tables.opt.urls: Likewise.
5261 * config/darwin.opt.urls: Likewise.
5262 * config/dragonfly.opt.urls: Likewise.
5263 * config/epiphany/epiphany.opt.urls: Likewise.
5264 * config/fr30/fr30.opt.urls: Likewise.
5265 * config/freebsd.opt.urls: Likewise.
5266 * config/frv/frv.opt.urls: Likewise.
5267 * config/ft32/ft32.opt.urls: Likewise.
5268 * config/fused-madd.opt.urls: Likewise.
5269 * config/g.opt.urls: Likewise.
5270 * config/gcn/gcn.opt.urls: Likewise.
5271 * config/gnu-user.opt.urls: Likewise.
5272 * config/h8300/h8300.opt.urls: Likewise.
5273 * config/hpux11.opt.urls: Likewise.
5274 * config/i386/cygming.opt.urls: Likewise.
5275 * config/i386/cygwin.opt.urls: Likewise.
5276 * config/i386/djgpp.opt.urls: Likewise.
5277 * config/i386/i386.opt.urls: Likewise.
5278 * config/i386/mingw-w64.opt.urls: Likewise.
5279 * config/i386/mingw.opt.urls: Likewise.
5280 * config/i386/nto.opt.urls: Likewise.
5281 * config/ia64/ia64.opt.urls: Likewise.
5282 * config/ia64/ilp32.opt.urls: Likewise.
5283 * config/ia64/vms.opt.urls: Likewise.
5284 * config/iq2000/iq2000.opt.urls: Likewise.
5285 * config/linux-android.opt.urls: Likewise.
5286 * config/linux.opt.urls: Likewise.
5287 * config/lm32/lm32.opt.urls: Likewise.
5288 * config/loongarch/loongarch.opt.urls: Likewise.
5289 * config/lynx.opt.urls: Likewise.
5290 * config/m32c/m32c.opt.urls: Likewise.
5291 * config/m32r/m32r.opt.urls: Likewise.
5292 * config/m68k/ieee.opt.urls: Likewise.
5293 * config/m68k/m68k-tables.opt.urls: Likewise.
5294 * config/m68k/m68k.opt.urls: Likewise.
5295 * config/m68k/uclinux.opt.urls: Likewise.
5296 * config/mcore/mcore.opt.urls: Likewise.
5297 * config/microblaze/microblaze.opt.urls: Likewise.
5298 * config/mips/mips-tables.opt.urls: Likewise.
5299 * config/mips/mips.opt.urls: Likewise.
5300 * config/mips/sde.opt.urls: Likewise.
5301 * config/mmix/mmix.opt.urls: Likewise.
5302 * config/mn10300/mn10300.opt.urls: Likewise.
5303 * config/moxie/moxie.opt.urls: Likewise.
5304 * config/msp430/msp430.opt.urls: Likewise.
5305 * config/nds32/nds32-elf.opt.urls: Likewise.
5306 * config/nds32/nds32-linux.opt.urls: Likewise.
5307 * config/nds32/nds32.opt.urls: Likewise.
5308 * config/netbsd-elf.opt.urls: Likewise.
5309 * config/netbsd.opt.urls: Likewise.
5310 * config/nios2/elf.opt.urls: Likewise.
5311 * config/nios2/nios2.opt.urls: Likewise.
5312 * config/nvptx/nvptx-gen.opt.urls: Likewise.
5313 * config/nvptx/nvptx.opt.urls: Likewise.
5314 * config/openbsd.opt.urls: Likewise.
5315 * config/or1k/elf.opt.urls: Likewise.
5316 * config/or1k/or1k.opt.urls: Likewise.
5317 * config/pa/pa-hpux.opt.urls: Likewise.
5318 * config/pa/pa-hpux1010.opt.urls: Likewise.
5319 * config/pa/pa-hpux1111.opt.urls: Likewise.
5320 * config/pa/pa-hpux1131.opt.urls: Likewise.
5321 * config/pa/pa.opt.urls: Likewise.
5322 * config/pa/pa64-hpux.opt.urls: Likewise.
5323 * config/pdp11/pdp11.opt.urls: Likewise.
5324 * config/pru/pru.opt.urls: Likewise.
5325 * config/riscv/riscv.opt.urls: Likewise.
5326 * config/rl78/rl78.opt.urls: Likewise.
5327 * config/rpath.opt.urls: Likewise.
5328 * config/rs6000/476.opt.urls: Likewise.
5329 * config/rs6000/aix64.opt.urls: Likewise.
5330 * config/rs6000/darwin.opt.urls: Likewise.
5331 * config/rs6000/linux64.opt.urls: Likewise.
5332 * config/rs6000/rs6000-tables.opt.urls: Likewise.
5333 * config/rs6000/rs6000.opt.urls: Likewise.
5334 * config/rs6000/sysv4.opt.urls: Likewise.
5335 * config/rtems.opt.urls: Likewise.
5336 * config/rx/elf.opt.urls: Likewise.
5337 * config/rx/rx.opt.urls: Likewise.
5338 * config/s390/s390.opt.urls: Likewise.
5339 * config/s390/tpf.opt.urls: Likewise.
5340 * config/sh/sh.opt.urls: Likewise.
5341 * config/sh/superh.opt.urls: Likewise.
5342 * config/sol2.opt.urls: Likewise.
5343 * config/sparc/long-double-switch.opt.urls: Likewise.
5344 * config/sparc/sparc.opt.urls: Likewise.
5345 * config/stormy16/stormy16.opt.urls: Likewise.
5346 * config/v850/v850.opt.urls: Likewise.
5347 * config/vax/elf.opt.urls: Likewise.
5348 * config/vax/vax.opt.urls: Likewise.
5349 * config/visium/visium.opt.urls: Likewise.
5350 * config/vms/vms.opt.urls: Likewise.
5351 * config/vxworks-smp.opt.urls: Likewise.
5352 * config/vxworks.opt.urls: Likewise.
5353 * config/xtensa/elf.opt.urls: Likewise.
5354 * config/xtensa/uclinux.opt.urls: Likewise.
5355 * config/xtensa/xtensa.opt.urls: Likewise.
5356 * config/bfin/bfin.opt.urls: New file.
5358 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5360 * Makefile.in (OPT_URLS_HTML_DEPS): New.
5361 (regenerate-opt-urls): New target.
5362 (regenerate-opt-urls-unit-test): New target.
5363 * doc/options.texi (Option properties): Add UrlSuffix and
5364 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
5365 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
5366 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
5367 and Makefile.in's OPT_URLS_HTML_DEPS.
5368 (Anatomy of a Target Back End): Add
5369 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
5370 * regenerate-opt-urls.py: New file.
5372 2024-01-04 David Malcolm <dmalcolm@redhat.com>
5374 * diagnostic-format-sarif.cc
5375 (sarif_builder::make_logical_location_object): Convert to...
5376 (make_sarif_logical_location_object): ...this.
5377 (sarif_builder::set_any_logical_locs_arr): Update for above
5378 change.
5379 (sarif_builder::make_thread_flow_location_object): Call
5380 maybe_add_sarif_properties on each diagnostic_event.
5381 * diagnostic-format-sarif.h (class logical_location): New forward
5382 decl.
5383 (make_sarif_logical_location_object): New decl.
5384 * diagnostic-path.h (class sarif_object): New forward decl.
5385 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
5387 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
5388 Patrick Lin <patrick@andestech.com>
5389 Rufus Chen <rufus@andestech.com>
5390 Monk Chiang <monk.chiang@sifive.com>
5392 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
5393 with Nan-boxing value.
5394 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
5396 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
5397 Jeff Law <jlaw@ventanamicro.com>
5399 PR rtl-optimization/104914
5400 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
5401 a sign or zero extension is only required if the modified field
5402 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
5403 targets, don't refer to the temporarily incorrectly extended value
5404 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
5406 2024-01-04 Pan Li <pan2.li@intel.com>
5408 Revert:
5409 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5411 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5413 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5415 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
5417 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
5419 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
5420 offset of fcsr.
5422 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5424 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
5425 (compute_nregs_for_mode): Refine LMUL.
5426 (max_number_of_live_regs): Ditto.
5427 (compute_estimated_lmul): Ditto.
5428 (has_unexpected_spills_p): Ditto.
5430 2024-01-04 Li Wei <liwei@loongson.cn>
5432 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
5433 Remove useless forward declaration.
5434 (loongarch_is_even_extraction): Remove useless forward declaration.
5435 (loongarch_try_expand_lsx_vshuf_const): Removed.
5436 (loongarch_expand_vec_perm_const_1): Merged.
5437 (loongarch_is_double_duplicate): Removed.
5438 (loongarch_is_center_extraction): Ditto.
5439 (loongarch_is_reversing_permutation): Ditto.
5440 (loongarch_is_di_misalign_extract): Ditto.
5441 (loongarch_is_si_misalign_extract): Ditto.
5442 (loongarch_is_lasx_lowpart_extract): Ditto.
5443 (loongarch_is_op_reverse_perm): Ditto.
5444 (loongarch_is_single_op_perm): Ditto.
5445 (loongarch_is_divisible_perm): Ditto.
5446 (loongarch_is_triple_stride_extract): Ditto.
5447 (loongarch_expand_vec_perm_const_2): Merged.
5448 (loongarch_expand_vec_perm_const): New.
5449 (loongarch_vectorize_vec_perm_const): Adjust.
5451 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
5453 * omp-general.cc: Fix comment typos and misplaced/confusing
5454 comments. Delete redundant include of omp-general.h.
5456 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5458 PR rtl-optimization/104914
5459 * config/mips/mips.md (insqisi_extended): New patterns.
5460 (inshisi_extended): Ditto.
5462 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5464 * config/mips/mips.cc (mips_insn_cost): New function.
5466 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
5468 * config/mips/mips.md (perf_ratio): New attribute.
5470 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5472 PR target/113206
5473 PR target/113209
5474 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
5475 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
5476 blocks belong to infinite loop.
5477 (pre_vsetvl::emit_vsetvl): Remove fake edges.
5478 * config/riscv/t-riscv: Add a new include file.
5480 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5482 * config/riscv/vector.md: Fix indent.
5484 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
5486 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
5487 OMP_CLAUSE__SIMDUID_.
5488 * tree.cc (omp_clause_num_ops): Update position of entry for
5489 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
5490 (omp_clause_code_name): Likewise.
5492 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
5494 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
5495 printing of FUNC_MAP/IND_FUNC_MAP labels.
5497 2024-01-03 Jakub Jelinek <jakub@redhat.com>
5499 * gcc.cc (process_command): Update copyright notice dates.
5500 * gcov-dump.cc (print_version): Ditto.
5501 * gcov.cc (print_version): Ditto.
5502 * gcov-tool.cc (print_version): Ditto.
5503 * gengtype.cc (create_file): Ditto.
5504 * doc/cpp.texi: Bump @copying's copyright year.
5505 * doc/cppinternals.texi: Ditto.
5506 * doc/gcc.texi: Ditto.
5507 * doc/gccint.texi: Ditto.
5508 * doc/gcov.texi: Ditto.
5509 * doc/install.texi: Ditto.
5510 * doc/invoke.texi: Ditto.
5512 2024-01-03 Xi Ruoyao <xry111@xry111.site>
5514 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
5515 (fmin<mode>3): Likewise.
5516 (reduc_fmax_scal_<mode>3): New define_expand.
5517 (reduc_fmin_scal_<mode>3): Likewise.
5519 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5521 PR target/113112
5522 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
5523 (max_number_of_live_regs): Ditto.
5524 (has_unexpected_spills_p): Ditto.
5526 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5527 Jin Ma <jinma@linux.alibaba.com>
5528 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5529 Christoph Müllner <christoph.muellner@vrull.eu>
5531 * config/riscv/vector.md:
5532 Use vector_length_operand for vsetvl patterns.
5534 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5536 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
5537 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
5539 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
5541 * config/aarch64/aarch64-tuning-flags.def
5542 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
5543 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
5544 * config/aarch64/aarch64.cc
5545 (aarch64_override_options_internal): Set
5546 param_fully_pipelined_fma according to tuning option.
5547 * config/aarch64/tuning_models/ampere1.h: Add
5548 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
5549 * config/aarch64/tuning_models/ampere1a.h: Likewise.
5550 * config/aarch64/tuning_models/ampere1b.h: Likewise.
5552 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
5554 * config/riscv/vector-crypto.md: Modify copyright year.
5556 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5558 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
5560 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
5562 * config.in: Regenerate.
5563 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
5564 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
5565 Added TLS Le Relax support.
5566 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
5567 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
5568 * configure: Regenerate.
5569 * configure.ac: Check if binutils supports TLS le relax.
5571 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
5573 * config/riscv/iterators.md: Add rotate insn name.
5574 * config/riscv/riscv.md: Add new insns name for crypto vector.
5575 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
5576 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
5577 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
5579 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5581 PR target/113112
5582 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
5583 pointer type liveness count.
5584 \f
5585 Copyright (C) 2024 Free Software Foundation, Inc.
5587 Copying and distribution of this file, with or without modification,
5588 are permitted in any medium without royalty provided the copyright
5589 notice and this notice are preserved.