| blob | 9ae55a7b811386a82c903567e2d69b9c7b8ef350 |
1 ;; Patterns for the Intel Wireless MMX technology architecture.
2 ;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 2, or (at your option) any later
10 ;; version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 (define_insn "iwmmxt_iordi3"
23 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
24 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
25 (match_operand:DI 2 "register_operand" "y,r,r")))]
26 "TARGET_REALLY_IWMMXT"
27 "@
28 wor%?\\t%0, %1, %2
29 #
30 #"
31 [(set_attr "predicable" "yes")
32 (set_attr "length" "4,8,8")])
34 (define_insn "iwmmxt_xordi3"
35 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
36 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
37 (match_operand:DI 2 "register_operand" "y,r,r")))]
38 "TARGET_REALLY_IWMMXT"
39 "@
40 wxor%?\\t%0, %1, %2
41 #
42 #"
43 [(set_attr "predicable" "yes")
44 (set_attr "length" "4,8,8")])
46 (define_insn "iwmmxt_anddi3"
47 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
48 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
49 (match_operand:DI 2 "register_operand" "y,r,r")))]
50 "TARGET_REALLY_IWMMXT"
51 "@
52 wand%?\\t%0, %1, %2
53 #
54 #"
55 [(set_attr "predicable" "yes")
56 (set_attr "length" "4,8,8")])
58 (define_insn "iwmmxt_nanddi3"
59 [(set (match_operand:DI 0 "register_operand" "=y")
60 (and:DI (match_operand:DI 1 "register_operand" "y")
61 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
62 "TARGET_REALLY_IWMMXT"
63 "wandn%?\\t%0, %1, %2"
64 [(set_attr "predicable" "yes")])
66 (define_insn "*iwmmxt_arm_movdi"
67 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
68 (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))]
69 "TARGET_REALLY_IWMMXT
70 && ( register_operand (operands[0], DImode)
71 || register_operand (operands[1], DImode))"
72 "*
73 {
74 switch (which_alternative)
75 {
76 default:
77 return output_move_double (operands);
78 case 0:
79 return \"#\";
80 case 3:
81 return \"wmov%?\\t%0,%1\";
82 case 4:
83 return \"tmcrr%?\\t%0,%Q1,%R1\";
84 case 5:
85 return \"tmrrc%?\\t%Q0,%R0,%1\";
86 case 6:
87 return \"wldrd%?\\t%0,%1\";
88 case 7:
89 return \"wstrd%?\\t%1,%0\";
90 }
91 }"
92 [(set_attr "length" "8,8,8,4,4,4,4,4")
93 (set_attr "type" "*,load1,store2,*,*,*,*,*")
94 (set_attr "pool_range" "*,1020,*,*,*,*,*,*")
95 (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
96 )
98 (define_insn "*iwmmxt_movsi_insn"
99 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
100 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))]
101 "TARGET_REALLY_IWMMXT
102 && ( register_operand (operands[0], SImode)
103 || register_operand (operands[1], SImode))"
104 "*
105 switch (which_alternative)
106 {
107 case 0: return \"mov\\t%0, %1\";
108 case 1: return \"mvn\\t%0, #%B1\";
109 case 2: return \"ldr\\t%0, %1\";
110 case 3: return \"str\\t%1, %0\";
111 case 4: return \"tmcr\\t%0, %1\";
112 case 5: return \"tmrc\\t%0, %1\";
113 case 6: return arm_output_load_gr (operands);
114 case 7: return \"wstrw\\t%1, %0\";
115 default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
116 }"
117 [(set_attr "type" "*,*,load1,store1,*,*,load1,store1,*")
118 (set_attr "length" "*,*,*, *,*,*, 16, *,8")
119 (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*")
120 (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*")
121 ;; Note - the "predicable" attribute is not allowed to have alternatives.
122 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
123 ;; predicating any of the alternatives in this template. Instead,
124 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
125 (set_attr "predicable" "no")
126 ;; Also - we have to pretend that these insns clobber the condition code
127 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
128 ;; them.
129 (set_attr "conds" "clob")]
130 )
132 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
133 ;; cond_exec version explicitly, with appropriate constraints.
135 (define_insn "*cond_iwmmxt_movsi_insn"
136 [(cond_exec
137 (match_operator 2 "arm_comparison_operator"
138 [(match_operand 3 "cc_register" "")
139 (const_int 0)])
140 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
141 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
142 "TARGET_REALLY_IWMMXT
143 && ( register_operand (operands[0], SImode)
144 || register_operand (operands[1], SImode))"
145 "*
146 switch (which_alternative)
147 {
148 case 0: return \"mov%?\\t%0, %1\";
149 case 1: return \"mvn%?\\t%0, #%B1\";
150 case 2: return \"ldr%?\\t%0, %1\";
151 case 3: return \"str%?\\t%1, %0\";
152 case 4: return \"tmcr%?\\t%0, %1\";
153 default: return \"tmrc%?\\t%0, %1\";
154 }"
155 [(set_attr "type" "*,*,load1,store1,*,*")
156 (set_attr "pool_range" "*,*,4096, *,*,*")
157 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
158 )
160 (define_insn "movv8qi_internal"
161 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
162 (match_operand:V8QI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
163 "TARGET_REALLY_IWMMXT"
164 "*
165 switch (which_alternative)
166 {
167 case 0: return \"wmov%?\\t%0, %1\";
168 case 1: return \"wstrd%?\\t%1, %0\";
169 case 2: return \"wldrd%?\\t%0, %1\";
170 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
171 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
172 case 5: return \"#\";
173 default: return output_move_double (operands);
174 }"
175 [(set_attr "predicable" "yes")
176 (set_attr "length" "4, 4, 4,4,4,8, 8")
177 (set_attr "type" "*,store1,load1,*,*,*,load1")
178 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
179 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
181 (define_insn "movv4hi_internal"
182 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
183 (match_operand:V4HI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
184 "TARGET_REALLY_IWMMXT"
185 "*
186 switch (which_alternative)
187 {
188 case 0: return \"wmov%?\\t%0, %1\";
189 case 1: return \"wstrd%?\\t%1, %0\";
190 case 2: return \"wldrd%?\\t%0, %1\";
191 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
192 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
193 case 5: return \"#\";
194 default: return output_move_double (operands);
195 }"
196 [(set_attr "predicable" "yes")
197 (set_attr "length" "4, 4, 4,4,4,8, 8")
198 (set_attr "type" "*,store1,load1,*,*,*,load1")
199 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
200 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
202 (define_insn "movv2si_internal"
203 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r")
204 (match_operand:V2SI 1 "general_operand" "y,y,mi,y,r,r,mi"))]
205 "TARGET_REALLY_IWMMXT"
206 "*
207 switch (which_alternative)
208 {
209 case 0: return \"wmov%?\\t%0, %1\";
210 case 1: return \"wstrd%?\\t%1, %0\";
211 case 2: return \"wldrd%?\\t%0, %1\";
212 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
213 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
214 case 5: return \"#\";
215 default: return output_move_double (operands);
216 }"
217 [(set_attr "predicable" "yes")
218 (set_attr "length" "4, 4, 4,4,4,8, 24")
219 (set_attr "type" "*,store1,load1,*,*,*,load1")
220 (set_attr "pool_range" "*, *, 256,*,*,*, 256")
221 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244")])
223 ;; This pattern should not be needed. It is to match a
224 ;; wierd case generated by GCC when no optimizations are
225 ;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/
226 ;; compile/simd-5.c at -O0). The mode for operands[1] is
227 ;; deliberately omitted.
228 (define_insn "movv2si_internal_2"
229 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
230 (match_operand 1 "immediate_operand" "mi"))]
231 "TARGET_REALLY_IWMMXT"
232 "* return output_move_double (operands);"
233 [(set_attr "predicable" "yes")
234 (set_attr "length" "8")
235 (set_attr "type" "load1")
236 (set_attr "pool_range" "256")
237 (set_attr "neg_pool_range" "244")])
239 ;; Vector add/subtract
241 (define_insn "addv8qi3"
242 [(set (match_operand:V8QI 0 "register_operand" "=y")
243 (plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
244 (match_operand:V8QI 2 "register_operand" "y")))]
245 "TARGET_REALLY_IWMMXT"
246 "waddb%?\\t%0, %1, %2"
247 [(set_attr "predicable" "yes")])
249 (define_insn "addv4hi3"
250 [(set (match_operand:V4HI 0 "register_operand" "=y")
251 (plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
252 (match_operand:V4HI 2 "register_operand" "y")))]
253 "TARGET_REALLY_IWMMXT"
254 "waddh%?\\t%0, %1, %2"
255 [(set_attr "predicable" "yes")])
257 (define_insn "addv2si3"
258 [(set (match_operand:V2SI 0 "register_operand" "=y")
259 (plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
260 (match_operand:V2SI 2 "register_operand" "y")))]
261 "TARGET_REALLY_IWMMXT"
262 "waddw%?\\t%0, %1, %2"
263 [(set_attr "predicable" "yes")])
265 (define_insn "ssaddv8qi3"
266 [(set (match_operand:V8QI 0 "register_operand" "=y")
267 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
268 (match_operand:V8QI 2 "register_operand" "y")))]
269 "TARGET_REALLY_IWMMXT"
270 "waddbss%?\\t%0, %1, %2"
271 [(set_attr "predicable" "yes")])
273 (define_insn "ssaddv4hi3"
274 [(set (match_operand:V4HI 0 "register_operand" "=y")
275 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
276 (match_operand:V4HI 2 "register_operand" "y")))]
277 "TARGET_REALLY_IWMMXT"
278 "waddhss%?\\t%0, %1, %2"
279 [(set_attr "predicable" "yes")])
281 (define_insn "ssaddv2si3"
282 [(set (match_operand:V2SI 0 "register_operand" "=y")
283 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
284 (match_operand:V2SI 2 "register_operand" "y")))]
285 "TARGET_REALLY_IWMMXT"
286 "waddwss%?\\t%0, %1, %2"
287 [(set_attr "predicable" "yes")])
289 (define_insn "usaddv8qi3"
290 [(set (match_operand:V8QI 0 "register_operand" "=y")
291 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
292 (match_operand:V8QI 2 "register_operand" "y")))]
293 "TARGET_REALLY_IWMMXT"
294 "waddbus%?\\t%0, %1, %2"
295 [(set_attr "predicable" "yes")])
297 (define_insn "usaddv4hi3"
298 [(set (match_operand:V4HI 0 "register_operand" "=y")
299 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
300 (match_operand:V4HI 2 "register_operand" "y")))]
301 "TARGET_REALLY_IWMMXT"
302 "waddhus%?\\t%0, %1, %2"
303 [(set_attr "predicable" "yes")])
305 (define_insn "usaddv2si3"
306 [(set (match_operand:V2SI 0 "register_operand" "=y")
307 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
308 (match_operand:V2SI 2 "register_operand" "y")))]
309 "TARGET_REALLY_IWMMXT"
310 "waddwus%?\\t%0, %1, %2"
311 [(set_attr "predicable" "yes")])
313 (define_insn "subv8qi3"
314 [(set (match_operand:V8QI 0 "register_operand" "=y")
315 (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
316 (match_operand:V8QI 2 "register_operand" "y")))]
317 "TARGET_REALLY_IWMMXT"
318 "wsubb%?\\t%0, %1, %2"
319 [(set_attr "predicable" "yes")])
321 (define_insn "subv4hi3"
322 [(set (match_operand:V4HI 0 "register_operand" "=y")
323 (minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
324 (match_operand:V4HI 2 "register_operand" "y")))]
325 "TARGET_REALLY_IWMMXT"
326 "wsubh%?\\t%0, %1, %2"
327 [(set_attr "predicable" "yes")])
329 (define_insn "subv2si3"
330 [(set (match_operand:V2SI 0 "register_operand" "=y")
331 (minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
332 (match_operand:V2SI 2 "register_operand" "y")))]
333 "TARGET_REALLY_IWMMXT"
334 "wsubw%?\\t%0, %1, %2"
335 [(set_attr "predicable" "yes")])
337 (define_insn "sssubv8qi3"
338 [(set (match_operand:V8QI 0 "register_operand" "=y")
339 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
340 (match_operand:V8QI 2 "register_operand" "y")))]
341 "TARGET_REALLY_IWMMXT"
342 "wsubbss%?\\t%0, %1, %2"
343 [(set_attr "predicable" "yes")])
345 (define_insn "sssubv4hi3"
346 [(set (match_operand:V4HI 0 "register_operand" "=y")
347 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
348 (match_operand:V4HI 2 "register_operand" "y")))]
349 "TARGET_REALLY_IWMMXT"
350 "wsubhss%?\\t%0, %1, %2"
351 [(set_attr "predicable" "yes")])
353 (define_insn "sssubv2si3"
354 [(set (match_operand:V2SI 0 "register_operand" "=y")
355 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
356 (match_operand:V2SI 2 "register_operand" "y")))]
357 "TARGET_REALLY_IWMMXT"
358 "wsubwss%?\\t%0, %1, %2"
359 [(set_attr "predicable" "yes")])
361 (define_insn "ussubv8qi3"
362 [(set (match_operand:V8QI 0 "register_operand" "=y")
363 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
364 (match_operand:V8QI 2 "register_operand" "y")))]
365 "TARGET_REALLY_IWMMXT"
366 "wsubbus%?\\t%0, %1, %2"
367 [(set_attr "predicable" "yes")])
369 (define_insn "ussubv4hi3"
370 [(set (match_operand:V4HI 0 "register_operand" "=y")
371 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
372 (match_operand:V4HI 2 "register_operand" "y")))]
373 "TARGET_REALLY_IWMMXT"
374 "wsubhus%?\\t%0, %1, %2"
375 [(set_attr "predicable" "yes")])
377 (define_insn "ussubv2si3"
378 [(set (match_operand:V2SI 0 "register_operand" "=y")
379 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
380 (match_operand:V2SI 2 "register_operand" "y")))]
381 "TARGET_REALLY_IWMMXT"
382 "wsubwus%?\\t%0, %1, %2"
383 [(set_attr "predicable" "yes")])
385 (define_insn "mulv4hi3"
386 [(set (match_operand:V4HI 0 "register_operand" "=y")
387 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
388 (match_operand:V4HI 2 "register_operand" "y")))]
389 "TARGET_REALLY_IWMMXT"
390 "wmulul%?\\t%0, %1, %2"
391 [(set_attr "predicable" "yes")])
393 (define_insn "smulv4hi3_highpart"
394 [(set (match_operand:V4HI 0 "register_operand" "=y")
395 (truncate:V4HI
396 (lshiftrt:V4SI
397 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
398 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
399 (const_int 16))))]
400 "TARGET_REALLY_IWMMXT"
401 "wmulsm%?\\t%0, %1, %2"
402 [(set_attr "predicable" "yes")])
404 (define_insn "umulv4hi3_highpart"
405 [(set (match_operand:V4HI 0 "register_operand" "=y")
406 (truncate:V4HI
407 (lshiftrt:V4SI
408 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
409 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
410 (const_int 16))))]
411 "TARGET_REALLY_IWMMXT"
412 "wmulum%?\\t%0, %1, %2"
413 [(set_attr "predicable" "yes")])
415 (define_insn "iwmmxt_wmacs"
416 [(set (match_operand:DI 0 "register_operand" "=y")
417 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
418 (match_operand:V4HI 2 "register_operand" "y")
419 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
420 "TARGET_REALLY_IWMMXT"
421 "wmacs%?\\t%0, %2, %3"
422 [(set_attr "predicable" "yes")])
424 (define_insn "iwmmxt_wmacsz"
425 [(set (match_operand:DI 0 "register_operand" "=y")
426 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
427 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
428 "TARGET_REALLY_IWMMXT"
429 "wmacsz%?\\t%0, %1, %2"
430 [(set_attr "predicable" "yes")])
432 (define_insn "iwmmxt_wmacu"
433 [(set (match_operand:DI 0 "register_operand" "=y")
434 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
435 (match_operand:V4HI 2 "register_operand" "y")
436 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
437 "TARGET_REALLY_IWMMXT"
438 "wmacu%?\\t%0, %2, %3"
439 [(set_attr "predicable" "yes")])
441 (define_insn "iwmmxt_wmacuz"
442 [(set (match_operand:DI 0 "register_operand" "=y")
443 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
444 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
445 "TARGET_REALLY_IWMMXT"
446 "wmacuz%?\\t%0, %1, %2"
447 [(set_attr "predicable" "yes")])
449 ;; Same as xordi3, but don't show input operands so that we don't think
450 ;; they are live.
451 (define_insn "iwmmxt_clrdi"
452 [(set (match_operand:DI 0 "register_operand" "=y")
453 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
454 "TARGET_REALLY_IWMMXT"
455 "wxor%?\\t%0, %0, %0"
456 [(set_attr "predicable" "yes")])
458 ;; Seems like cse likes to generate these, so we have to support them.
460 (define_insn "*iwmmxt_clrv8qi"
461 [(set (match_operand:V8QI 0 "register_operand" "=y")
462 (const_vector:V8QI [(const_int 0) (const_int 0)
463 (const_int 0) (const_int 0)
464 (const_int 0) (const_int 0)
465 (const_int 0) (const_int 0)]))]
466 "TARGET_REALLY_IWMMXT"
467 "wxor%?\\t%0, %0, %0"
468 [(set_attr "predicable" "yes")])
470 (define_insn "*iwmmxt_clrv4hi"
471 [(set (match_operand:V4HI 0 "register_operand" "=y")
472 (const_vector:V4HI [(const_int 0) (const_int 0)
473 (const_int 0) (const_int 0)]))]
474 "TARGET_REALLY_IWMMXT"
475 "wxor%?\\t%0, %0, %0"
476 [(set_attr "predicable" "yes")])
478 (define_insn "*iwmmxt_clrv2si"
479 [(set (match_operand:V2SI 0 "register_operand" "=y")
480 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
481 "TARGET_REALLY_IWMMXT"
482 "wxor%?\\t%0, %0, %0"
483 [(set_attr "predicable" "yes")])
485 ;; Unsigned averages/sum of absolute differences
487 (define_insn "iwmmxt_uavgrndv8qi3"
488 [(set (match_operand:V8QI 0 "register_operand" "=y")
489 (ashiftrt:V8QI
490 (plus:V8QI (plus:V8QI
491 (match_operand:V8QI 1 "register_operand" "y")
492 (match_operand:V8QI 2 "register_operand" "y"))
493 (const_vector:V8QI [(const_int 1)
494 (const_int 1)
495 (const_int 1)
496 (const_int 1)
497 (const_int 1)
498 (const_int 1)
499 (const_int 1)
500 (const_int 1)]))
501 (const_int 1)))]
502 "TARGET_REALLY_IWMMXT"
503 "wavg2br%?\\t%0, %1, %2"
504 [(set_attr "predicable" "yes")])
506 (define_insn "iwmmxt_uavgrndv4hi3"
507 [(set (match_operand:V4HI 0 "register_operand" "=y")
508 (ashiftrt:V4HI
509 (plus:V4HI (plus:V4HI
510 (match_operand:V4HI 1 "register_operand" "y")
511 (match_operand:V4HI 2 "register_operand" "y"))
512 (const_vector:V4HI [(const_int 1)
513 (const_int 1)
514 (const_int 1)
515 (const_int 1)]))
516 (const_int 1)))]
517 "TARGET_REALLY_IWMMXT"
518 "wavg2hr%?\\t%0, %1, %2"
519 [(set_attr "predicable" "yes")])
522 (define_insn "iwmmxt_uavgv8qi3"
523 [(set (match_operand:V8QI 0 "register_operand" "=y")
524 (ashiftrt:V8QI (plus:V8QI
525 (match_operand:V8QI 1 "register_operand" "y")
526 (match_operand:V8QI 2 "register_operand" "y"))
527 (const_int 1)))]
528 "TARGET_REALLY_IWMMXT"
529 "wavg2b%?\\t%0, %1, %2"
530 [(set_attr "predicable" "yes")])
532 (define_insn "iwmmxt_uavgv4hi3"
533 [(set (match_operand:V4HI 0 "register_operand" "=y")
534 (ashiftrt:V4HI (plus:V4HI
535 (match_operand:V4HI 1 "register_operand" "y")
536 (match_operand:V4HI 2 "register_operand" "y"))
537 (const_int 1)))]
538 "TARGET_REALLY_IWMMXT"
539 "wavg2h%?\\t%0, %1, %2"
540 [(set_attr "predicable" "yes")])
542 (define_insn "iwmmxt_psadbw"
543 [(set (match_operand:V8QI 0 "register_operand" "=y")
544 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
545 (match_operand:V8QI 2 "register_operand" "y"))))]
546 "TARGET_REALLY_IWMMXT"
547 "psadbw%?\\t%0, %1, %2"
548 [(set_attr "predicable" "yes")])
551 ;; Insert/extract/shuffle
553 (define_insn "iwmmxt_tinsrb"
554 [(set (match_operand:V8QI 0 "register_operand" "=y")
555 (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0")
556 (vec_duplicate:V8QI
557 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
558 (match_operand:SI 3 "immediate_operand" "i")))]
559 "TARGET_REALLY_IWMMXT"
560 "tinsrb%?\\t%0, %2, %3"
561 [(set_attr "predicable" "yes")])
563 (define_insn "iwmmxt_tinsrh"
564 [(set (match_operand:V4HI 0 "register_operand" "=y")
565 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
566 (vec_duplicate:V4HI
567 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
568 (match_operand:SI 3 "immediate_operand" "i")))]
569 "TARGET_REALLY_IWMMXT"
570 "tinsrh%?\\t%0, %2, %3"
571 [(set_attr "predicable" "yes")])
573 (define_insn "iwmmxt_tinsrw"
574 [(set (match_operand:V2SI 0 "register_operand" "=y")
575 (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0")
576 (vec_duplicate:V2SI
577 (match_operand:SI 2 "nonimmediate_operand" "r"))
578 (match_operand:SI 3 "immediate_operand" "i")))]
579 "TARGET_REALLY_IWMMXT"
580 "tinsrw%?\\t%0, %2, %3"
581 [(set_attr "predicable" "yes")])
583 (define_insn "iwmmxt_textrmub"
584 [(set (match_operand:SI 0 "register_operand" "=r")
585 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
586 (parallel
587 [(match_operand:SI 2 "immediate_operand" "i")]))))]
588 "TARGET_REALLY_IWMMXT"
589 "textrmub%?\\t%0, %1, %2"
590 [(set_attr "predicable" "yes")])
592 (define_insn "iwmmxt_textrmsb"
593 [(set (match_operand:SI 0 "register_operand" "=r")
594 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
595 (parallel
596 [(match_operand:SI 2 "immediate_operand" "i")]))))]
597 "TARGET_REALLY_IWMMXT"
598 "textrmsb%?\\t%0, %1, %2"
599 [(set_attr "predicable" "yes")])
601 (define_insn "iwmmxt_textrmuh"
602 [(set (match_operand:SI 0 "register_operand" "=r")
603 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
604 (parallel
605 [(match_operand:SI 2 "immediate_operand" "i")]))))]
606 "TARGET_REALLY_IWMMXT"
607 "textrmuh%?\\t%0, %1, %2"
608 [(set_attr "predicable" "yes")])
610 (define_insn "iwmmxt_textrmsh"
611 [(set (match_operand:SI 0 "register_operand" "=r")
612 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
613 (parallel
614 [(match_operand:SI 2 "immediate_operand" "i")]))))]
615 "TARGET_REALLY_IWMMXT"
616 "textrmsh%?\\t%0, %1, %2"
617 [(set_attr "predicable" "yes")])
619 ;; There are signed/unsigned variants of this instruction, but they are
620 ;; pointless.
621 (define_insn "iwmmxt_textrmw"
622 [(set (match_operand:SI 0 "register_operand" "=r")
623 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
624 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
625 "TARGET_REALLY_IWMMXT"
626 "textrmsw%?\\t%0, %1, %2"
627 [(set_attr "predicable" "yes")])
629 (define_insn "iwmmxt_wshufh"
630 [(set (match_operand:V4HI 0 "register_operand" "=y")
631 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
632 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
633 "TARGET_REALLY_IWMMXT"
634 "wshufh%?\\t%0, %1, %2"
635 [(set_attr "predicable" "yes")])
637 ;; Mask-generating comparisons
638 ;;
639 ;; Note - you cannot use patterns like these here:
640 ;;
641 ;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
642 ;;
643 ;; Because GCC will assume that the truth value (1 or 0) is installed
644 ;; into the entire destination vector, (with the '1' going into the least
645 ;; significant element of the vector). This is not how these instructions
646 ;; behave.
647 ;;
648 ;; Unfortunately the current patterns are illegal. They are SET insns
649 ;; without a SET in them. They work in most cases for ordinary code
650 ;; generation, but there are circumstances where they can cause gcc to fail.
651 ;; XXX - FIXME.
653 (define_insn "eqv8qi3"
654 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
655 (match_operand:V8QI 1 "register_operand" "y")
656 (match_operand:V8QI 2 "register_operand" "y")]
657 VUNSPEC_WCMP_EQ)]
658 "TARGET_REALLY_IWMMXT"
659 "wcmpeqb%?\\t%0, %1, %2"
660 [(set_attr "predicable" "yes")])
662 (define_insn "eqv4hi3"
663 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
664 (match_operand:V4HI 1 "register_operand" "y")
665 (match_operand:V4HI 2 "register_operand" "y")]
666 VUNSPEC_WCMP_EQ)]
667 "TARGET_REALLY_IWMMXT"
668 "wcmpeqh%?\\t%0, %1, %2"
669 [(set_attr "predicable" "yes")])
671 (define_insn "eqv2si3"
672 [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
673 (match_operand:V2SI 1 "register_operand" "y")
674 (match_operand:V2SI 2 "register_operand" "y")]
675 VUNSPEC_WCMP_EQ)]
676 "TARGET_REALLY_IWMMXT"
677 "wcmpeqw%?\\t%0, %1, %2"
678 [(set_attr "predicable" "yes")])
680 (define_insn "gtuv8qi3"
681 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
682 (match_operand:V8QI 1 "register_operand" "y")
683 (match_operand:V8QI 2 "register_operand" "y")]
684 VUNSPEC_WCMP_GTU)]
685 "TARGET_REALLY_IWMMXT"
686 "wcmpgtub%?\\t%0, %1, %2"
687 [(set_attr "predicable" "yes")])
689 (define_insn "gtuv4hi3"
690 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
691 (match_operand:V4HI 1 "register_operand" "y")
692 (match_operand:V4HI 2 "register_operand" "y")]
693 VUNSPEC_WCMP_GTU)]
694 "TARGET_REALLY_IWMMXT"
695 "wcmpgtuh%?\\t%0, %1, %2"
696 [(set_attr "predicable" "yes")])
698 (define_insn "gtuv2si3"
699 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
700 (match_operand:V2SI 1 "register_operand" "y")
701 (match_operand:V2SI 2 "register_operand" "y")]
702 VUNSPEC_WCMP_GTU)]
703 "TARGET_REALLY_IWMMXT"
704 "wcmpgtuw%?\\t%0, %1, %2"
705 [(set_attr "predicable" "yes")])
707 (define_insn "gtv8qi3"
708 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
709 (match_operand:V8QI 1 "register_operand" "y")
710 (match_operand:V8QI 2 "register_operand" "y")]
711 VUNSPEC_WCMP_GT)]
712 "TARGET_REALLY_IWMMXT"
713 "wcmpgtsb%?\\t%0, %1, %2"
714 [(set_attr "predicable" "yes")])
716 (define_insn "gtv4hi3"
717 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
718 (match_operand:V4HI 1 "register_operand" "y")
719 (match_operand:V4HI 2 "register_operand" "y")]
720 VUNSPEC_WCMP_GT)]
721 "TARGET_REALLY_IWMMXT"
722 "wcmpgtsh%?\\t%0, %1, %2"
723 [(set_attr "predicable" "yes")])
725 (define_insn "gtv2si3"
726 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
727 (match_operand:V2SI 1 "register_operand" "y")
728 (match_operand:V2SI 2 "register_operand" "y")]
729 VUNSPEC_WCMP_GT)]
730 "TARGET_REALLY_IWMMXT"
731 "wcmpgtsw%?\\t%0, %1, %2"
732 [(set_attr "predicable" "yes")])
734 ;; Max/min insns
736 (define_insn "smaxv8qi3"
737 [(set (match_operand:V8QI 0 "register_operand" "=y")
738 (smax:V8QI (match_operand:V8QI 1 "register_operand" "y")
739 (match_operand:V8QI 2 "register_operand" "y")))]
740 "TARGET_REALLY_IWMMXT"
741 "wmaxsb%?\\t%0, %1, %2"
742 [(set_attr "predicable" "yes")])
744 (define_insn "umaxv8qi3"
745 [(set (match_operand:V8QI 0 "register_operand" "=y")
746 (umax:V8QI (match_operand:V8QI 1 "register_operand" "y")
747 (match_operand:V8QI 2 "register_operand" "y")))]
748 "TARGET_REALLY_IWMMXT"
749 "wmaxub%?\\t%0, %1, %2"
750 [(set_attr "predicable" "yes")])
752 (define_insn "smaxv4hi3"
753 [(set (match_operand:V4HI 0 "register_operand" "=y")
754 (smax:V4HI (match_operand:V4HI 1 "register_operand" "y")
755 (match_operand:V4HI 2 "register_operand" "y")))]
756 "TARGET_REALLY_IWMMXT"
757 "wmaxsh%?\\t%0, %1, %2"
758 [(set_attr "predicable" "yes")])
760 (define_insn "umaxv4hi3"
761 [(set (match_operand:V4HI 0 "register_operand" "=y")
762 (umax:V4HI (match_operand:V4HI 1 "register_operand" "y")
763 (match_operand:V4HI 2 "register_operand" "y")))]
764 "TARGET_REALLY_IWMMXT"
765 "wmaxuh%?\\t%0, %1, %2"
766 [(set_attr "predicable" "yes")])
768 (define_insn "smaxv2si3"
769 [(set (match_operand:V2SI 0 "register_operand" "=y")
770 (smax:V2SI (match_operand:V2SI 1 "register_operand" "y")
771 (match_operand:V2SI 2 "register_operand" "y")))]
772 "TARGET_REALLY_IWMMXT"
773 "wmaxsw%?\\t%0, %1, %2"
774 [(set_attr "predicable" "yes")])
776 (define_insn "umaxv2si3"
777 [(set (match_operand:V2SI 0 "register_operand" "=y")
778 (umax:V2SI (match_operand:V2SI 1 "register_operand" "y")
779 (match_operand:V2SI 2 "register_operand" "y")))]
780 "TARGET_REALLY_IWMMXT"
781 "wmaxuw%?\\t%0, %1, %2"
782 [(set_attr "predicable" "yes")])
784 (define_insn "sminv8qi3"
785 [(set (match_operand:V8QI 0 "register_operand" "=y")
786 (smin:V8QI (match_operand:V8QI 1 "register_operand" "y")
787 (match_operand:V8QI 2 "register_operand" "y")))]
788 "TARGET_REALLY_IWMMXT"
789 "wminsb%?\\t%0, %1, %2"
790 [(set_attr "predicable" "yes")])
792 (define_insn "uminv8qi3"
793 [(set (match_operand:V8QI 0 "register_operand" "=y")
794 (umin:V8QI (match_operand:V8QI 1 "register_operand" "y")
795 (match_operand:V8QI 2 "register_operand" "y")))]
796 "TARGET_REALLY_IWMMXT"
797 "wminub%?\\t%0, %1, %2"
798 [(set_attr "predicable" "yes")])
800 (define_insn "sminv4hi3"
801 [(set (match_operand:V4HI 0 "register_operand" "=y")
802 (smin:V4HI (match_operand:V4HI 1 "register_operand" "y")
803 (match_operand:V4HI 2 "register_operand" "y")))]
804 "TARGET_REALLY_IWMMXT"
805 "wminsh%?\\t%0, %1, %2"
806 [(set_attr "predicable" "yes")])
808 (define_insn "uminv4hi3"
809 [(set (match_operand:V4HI 0 "register_operand" "=y")
810 (umin:V4HI (match_operand:V4HI 1 "register_operand" "y")
811 (match_operand:V4HI 2 "register_operand" "y")))]
812 "TARGET_REALLY_IWMMXT"
813 "wminuh%?\\t%0, %1, %2"
814 [(set_attr "predicable" "yes")])
816 (define_insn "sminv2si3"
817 [(set (match_operand:V2SI 0 "register_operand" "=y")
818 (smin:V2SI (match_operand:V2SI 1 "register_operand" "y")
819 (match_operand:V2SI 2 "register_operand" "y")))]
820 "TARGET_REALLY_IWMMXT"
821 "wminsw%?\\t%0, %1, %2"
822 [(set_attr "predicable" "yes")])
824 (define_insn "uminv2si3"
825 [(set (match_operand:V2SI 0 "register_operand" "=y")
826 (umin:V2SI (match_operand:V2SI 1 "register_operand" "y")
827 (match_operand:V2SI 2 "register_operand" "y")))]
828 "TARGET_REALLY_IWMMXT"
829 "wminuw%?\\t%0, %1, %2"
830 [(set_attr "predicable" "yes")])
832 ;; Pack/unpack insns.
834 (define_insn "iwmmxt_wpackhss"
835 [(set (match_operand:V8QI 0 "register_operand" "=y")
836 (vec_concat:V8QI
837 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
838 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
839 "TARGET_REALLY_IWMMXT"
840 "wpackhss%?\\t%0, %1, %2"
841 [(set_attr "predicable" "yes")])
843 (define_insn "iwmmxt_wpackwss"
844 [(set (match_operand:V4HI 0 "register_operand" "=y")
845 (vec_concat:V4HI
846 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
847 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
848 "TARGET_REALLY_IWMMXT"
849 "wpackwss%?\\t%0, %1, %2"
850 [(set_attr "predicable" "yes")])
852 (define_insn "iwmmxt_wpackdss"
853 [(set (match_operand:V2SI 0 "register_operand" "=y")
854 (vec_concat:V2SI
855 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
856 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
857 "TARGET_REALLY_IWMMXT"
858 "wpackdss%?\\t%0, %1, %2"
859 [(set_attr "predicable" "yes")])
861 (define_insn "iwmmxt_wpackhus"
862 [(set (match_operand:V8QI 0 "register_operand" "=y")
863 (vec_concat:V8QI
864 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
865 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
866 "TARGET_REALLY_IWMMXT"
867 "wpackhus%?\\t%0, %1, %2"
868 [(set_attr "predicable" "yes")])
870 (define_insn "iwmmxt_wpackwus"
871 [(set (match_operand:V4HI 0 "register_operand" "=y")
872 (vec_concat:V4HI
873 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
874 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
875 "TARGET_REALLY_IWMMXT"
876 "wpackwus%?\\t%0, %1, %2"
877 [(set_attr "predicable" "yes")])
879 (define_insn "iwmmxt_wpackdus"
880 [(set (match_operand:V2SI 0 "register_operand" "=y")
881 (vec_concat:V2SI
882 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
883 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
884 "TARGET_REALLY_IWMMXT"
885 "wpackdus%?\\t%0, %1, %2"
886 [(set_attr "predicable" "yes")])
889 (define_insn "iwmmxt_wunpckihb"
890 [(set (match_operand:V8QI 0 "register_operand" "=y")
891 (vec_merge:V8QI
892 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
893 (parallel [(const_int 4)
894 (const_int 0)
895 (const_int 5)
896 (const_int 1)
897 (const_int 6)
898 (const_int 2)
899 (const_int 7)
900 (const_int 3)]))
901 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
902 (parallel [(const_int 0)
903 (const_int 4)
904 (const_int 1)
905 (const_int 5)
906 (const_int 2)
907 (const_int 6)
908 (const_int 3)
909 (const_int 7)]))
910 (const_int 85)))]
911 "TARGET_REALLY_IWMMXT"
912 "wunpckihb%?\\t%0, %1, %2"
913 [(set_attr "predicable" "yes")])
915 (define_insn "iwmmxt_wunpckihh"
916 [(set (match_operand:V4HI 0 "register_operand" "=y")
917 (vec_merge:V4HI
918 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
919 (parallel [(const_int 0)
920 (const_int 2)
921 (const_int 1)
922 (const_int 3)]))
923 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
924 (parallel [(const_int 2)
925 (const_int 0)
926 (const_int 3)
927 (const_int 1)]))
928 (const_int 5)))]
929 "TARGET_REALLY_IWMMXT"
930 "wunpckihh%?\\t%0, %1, %2"
931 [(set_attr "predicable" "yes")])
933 (define_insn "iwmmxt_wunpckihw"
934 [(set (match_operand:V2SI 0 "register_operand" "=y")
935 (vec_merge:V2SI
936 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
937 (parallel [(const_int 0)
938 (const_int 1)]))
939 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
940 (parallel [(const_int 1)
941 (const_int 0)]))
942 (const_int 1)))]
943 "TARGET_REALLY_IWMMXT"
944 "wunpckihw%?\\t%0, %1, %2"
945 [(set_attr "predicable" "yes")])
947 (define_insn "iwmmxt_wunpckilb"
948 [(set (match_operand:V8QI 0 "register_operand" "=y")
949 (vec_merge:V8QI
950 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
951 (parallel [(const_int 0)
952 (const_int 4)
953 (const_int 1)
954 (const_int 5)
955 (const_int 2)
956 (const_int 6)
957 (const_int 3)
958 (const_int 7)]))
959 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
960 (parallel [(const_int 4)
961 (const_int 0)
962 (const_int 5)
963 (const_int 1)
964 (const_int 6)
965 (const_int 2)
966 (const_int 7)
967 (const_int 3)]))
968 (const_int 85)))]
969 "TARGET_REALLY_IWMMXT"
970 "wunpckilb%?\\t%0, %1, %2"
971 [(set_attr "predicable" "yes")])
973 (define_insn "iwmmxt_wunpckilh"
974 [(set (match_operand:V4HI 0 "register_operand" "=y")
975 (vec_merge:V4HI
976 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
977 (parallel [(const_int 2)
978 (const_int 0)
979 (const_int 3)
980 (const_int 1)]))
981 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
982 (parallel [(const_int 0)
983 (const_int 2)
984 (const_int 1)
985 (const_int 3)]))
986 (const_int 5)))]
987 "TARGET_REALLY_IWMMXT"
988 "wunpckilh%?\\t%0, %1, %2"
989 [(set_attr "predicable" "yes")])
991 (define_insn "iwmmxt_wunpckilw"
992 [(set (match_operand:V2SI 0 "register_operand" "=y")
993 (vec_merge:V2SI
994 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
995 (parallel [(const_int 1)
996 (const_int 0)]))
997 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
998 (parallel [(const_int 0)
999 (const_int 1)]))
1000 (const_int 1)))]
1001 "TARGET_REALLY_IWMMXT"
1002 "wunpckilw%?\\t%0, %1, %2"
1003 [(set_attr "predicable" "yes")])
1005 (define_insn "iwmmxt_wunpckehub"
1006 [(set (match_operand:V4HI 0 "register_operand" "=y")
1007 (zero_extend:V4HI
1008 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1009 (parallel [(const_int 4) (const_int 5)
1010 (const_int 6) (const_int 7)]))))]
1011 "TARGET_REALLY_IWMMXT"
1012 "wunpckehub%?\\t%0, %1"
1013 [(set_attr "predicable" "yes")])
1015 (define_insn "iwmmxt_wunpckehuh"
1016 [(set (match_operand:V2SI 0 "register_operand" "=y")
1017 (zero_extend:V2SI
1018 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1019 (parallel [(const_int 2) (const_int 3)]))))]
1020 "TARGET_REALLY_IWMMXT"
1021 "wunpckehuh%?\\t%0, %1"
1022 [(set_attr "predicable" "yes")])
1024 (define_insn "iwmmxt_wunpckehuw"
1025 [(set (match_operand:DI 0 "register_operand" "=y")
1026 (zero_extend:DI
1027 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1028 (parallel [(const_int 1)]))))]
1029 "TARGET_REALLY_IWMMXT"
1030 "wunpckehuw%?\\t%0, %1"
1031 [(set_attr "predicable" "yes")])
1033 (define_insn "iwmmxt_wunpckehsb"
1034 [(set (match_operand:V4HI 0 "register_operand" "=y")
1035 (sign_extend:V4HI
1036 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1037 (parallel [(const_int 4) (const_int 5)
1038 (const_int 6) (const_int 7)]))))]
1039 "TARGET_REALLY_IWMMXT"
1040 "wunpckehsb%?\\t%0, %1"
1041 [(set_attr "predicable" "yes")])
1043 (define_insn "iwmmxt_wunpckehsh"
1044 [(set (match_operand:V2SI 0 "register_operand" "=y")
1045 (sign_extend:V2SI
1046 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1047 (parallel [(const_int 2) (const_int 3)]))))]
1048 "TARGET_REALLY_IWMMXT"
1049 "wunpckehsh%?\\t%0, %1"
1050 [(set_attr "predicable" "yes")])
1052 (define_insn "iwmmxt_wunpckehsw"
1053 [(set (match_operand:DI 0 "register_operand" "=y")
1054 (sign_extend:DI
1055 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1056 (parallel [(const_int 1)]))))]
1057 "TARGET_REALLY_IWMMXT"
1058 "wunpckehsw%?\\t%0, %1"
1059 [(set_attr "predicable" "yes")])
1061 (define_insn "iwmmxt_wunpckelub"
1062 [(set (match_operand:V4HI 0 "register_operand" "=y")
1063 (zero_extend:V4HI
1064 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1065 (parallel [(const_int 0) (const_int 1)
1066 (const_int 2) (const_int 3)]))))]
1067 "TARGET_REALLY_IWMMXT"
1068 "wunpckelub%?\\t%0, %1"
1069 [(set_attr "predicable" "yes")])
1071 (define_insn "iwmmxt_wunpckeluh"
1072 [(set (match_operand:V2SI 0 "register_operand" "=y")
1073 (zero_extend:V2SI
1074 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1075 (parallel [(const_int 0) (const_int 1)]))))]
1076 "TARGET_REALLY_IWMMXT"
1077 "wunpckeluh%?\\t%0, %1"
1078 [(set_attr "predicable" "yes")])
1080 (define_insn "iwmmxt_wunpckeluw"
1081 [(set (match_operand:DI 0 "register_operand" "=y")
1082 (zero_extend:DI
1083 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1084 (parallel [(const_int 0)]))))]
1085 "TARGET_REALLY_IWMMXT"
1086 "wunpckeluw%?\\t%0, %1"
1087 [(set_attr "predicable" "yes")])
1089 (define_insn "iwmmxt_wunpckelsb"
1090 [(set (match_operand:V4HI 0 "register_operand" "=y")
1091 (sign_extend:V4HI
1092 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
1093 (parallel [(const_int 0) (const_int 1)
1094 (const_int 2) (const_int 3)]))))]
1095 "TARGET_REALLY_IWMMXT"
1096 "wunpckelsb%?\\t%0, %1"
1097 [(set_attr "predicable" "yes")])
1099 (define_insn "iwmmxt_wunpckelsh"
1100 [(set (match_operand:V2SI 0 "register_operand" "=y")
1101 (sign_extend:V2SI
1102 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
1103 (parallel [(const_int 0) (const_int 1)]))))]
1104 "TARGET_REALLY_IWMMXT"
1105 "wunpckelsh%?\\t%0, %1"
1106 [(set_attr "predicable" "yes")])
1108 (define_insn "iwmmxt_wunpckelsw"
1109 [(set (match_operand:DI 0 "register_operand" "=y")
1110 (sign_extend:DI
1111 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
1112 (parallel [(const_int 0)]))))]
1113 "TARGET_REALLY_IWMMXT"
1114 "wunpckelsw%?\\t%0, %1"
1115 [(set_attr "predicable" "yes")])
1117 ;; Shifts
1119 (define_insn "rorv4hi3"
1120 [(set (match_operand:V4HI 0 "register_operand" "=y")
1121 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1122 (match_operand:SI 2 "register_operand" "z")))]
1123 "TARGET_REALLY_IWMMXT"
1124 "wrorhg%?\\t%0, %1, %2"
1125 [(set_attr "predicable" "yes")])
1127 (define_insn "rorv2si3"
1128 [(set (match_operand:V2SI 0 "register_operand" "=y")
1129 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1130 (match_operand:SI 2 "register_operand" "z")))]
1131 "TARGET_REALLY_IWMMXT"
1132 "wrorwg%?\\t%0, %1, %2"
1133 [(set_attr "predicable" "yes")])
1135 (define_insn "rordi3"
1136 [(set (match_operand:DI 0 "register_operand" "=y")
1137 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1138 (match_operand:SI 2 "register_operand" "z")))]
1139 "TARGET_REALLY_IWMMXT"
1140 "wrordg%?\\t%0, %1, %2"
1141 [(set_attr "predicable" "yes")])
1143 (define_insn "ashrv4hi3"
1144 [(set (match_operand:V4HI 0 "register_operand" "=y")
1145 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1146 (match_operand:SI 2 "register_operand" "z")))]
1147 "TARGET_REALLY_IWMMXT"
1148 "wsrahg%?\\t%0, %1, %2"
1149 [(set_attr "predicable" "yes")])
1151 (define_insn "ashrv2si3"
1152 [(set (match_operand:V2SI 0 "register_operand" "=y")
1153 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1154 (match_operand:SI 2 "register_operand" "z")))]
1155 "TARGET_REALLY_IWMMXT"
1156 "wsrawg%?\\t%0, %1, %2"
1157 [(set_attr "predicable" "yes")])
1159 (define_insn "ashrdi3_iwmmxt"
1160 [(set (match_operand:DI 0 "register_operand" "=y")
1161 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1162 (match_operand:SI 2 "register_operand" "z")))]
1163 "TARGET_REALLY_IWMMXT"
1164 "wsradg%?\\t%0, %1, %2"
1165 [(set_attr "predicable" "yes")])
1167 (define_insn "lshrv4hi3"
1168 [(set (match_operand:V4HI 0 "register_operand" "=y")
1169 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1170 (match_operand:SI 2 "register_operand" "z")))]
1171 "TARGET_REALLY_IWMMXT"
1172 "wsrlhg%?\\t%0, %1, %2"
1173 [(set_attr "predicable" "yes")])
1175 (define_insn "lshrv2si3"
1176 [(set (match_operand:V2SI 0 "register_operand" "=y")
1177 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1178 (match_operand:SI 2 "register_operand" "z")))]
1179 "TARGET_REALLY_IWMMXT"
1180 "wsrlwg%?\\t%0, %1, %2"
1181 [(set_attr "predicable" "yes")])
1183 (define_insn "lshrdi3_iwmmxt"
1184 [(set (match_operand:DI 0 "register_operand" "=y")
1185 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1186 (match_operand:SI 2 "register_operand" "z")))]
1187 "TARGET_REALLY_IWMMXT"
1188 "wsrldg%?\\t%0, %1, %2"
1189 [(set_attr "predicable" "yes")])
1191 (define_insn "ashlv4hi3"
1192 [(set (match_operand:V4HI 0 "register_operand" "=y")
1193 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1194 (match_operand:SI 2 "register_operand" "z")))]
1195 "TARGET_REALLY_IWMMXT"
1196 "wsllhg%?\\t%0, %1, %2"
1197 [(set_attr "predicable" "yes")])
1199 (define_insn "ashlv2si3"
1200 [(set (match_operand:V2SI 0 "register_operand" "=y")
1201 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1202 (match_operand:SI 2 "register_operand" "z")))]
1203 "TARGET_REALLY_IWMMXT"
1204 "wsllwg%?\\t%0, %1, %2"
1205 [(set_attr "predicable" "yes")])
1207 (define_insn "ashldi3_iwmmxt"
1208 [(set (match_operand:DI 0 "register_operand" "=y")
1209 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1210 (match_operand:SI 2 "register_operand" "z")))]
1211 "TARGET_REALLY_IWMMXT"
1212 "wslldg%?\\t%0, %1, %2"
1213 [(set_attr "predicable" "yes")])
1215 (define_insn "rorv4hi3_di"
1216 [(set (match_operand:V4HI 0 "register_operand" "=y")
1217 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
1218 (match_operand:DI 2 "register_operand" "y")))]
1219 "TARGET_REALLY_IWMMXT"
1220 "wrorh%?\\t%0, %1, %2"
1221 [(set_attr "predicable" "yes")])
1223 (define_insn "rorv2si3_di"
1224 [(set (match_operand:V2SI 0 "register_operand" "=y")
1225 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
1226 (match_operand:DI 2 "register_operand" "y")))]
1227 "TARGET_REALLY_IWMMXT"
1228 "wrorw%?\\t%0, %1, %2"
1229 [(set_attr "predicable" "yes")])
1231 (define_insn "rordi3_di"
1232 [(set (match_operand:DI 0 "register_operand" "=y")
1233 (rotatert:DI (match_operand:DI 1 "register_operand" "y")
1234 (match_operand:DI 2 "register_operand" "y")))]
1235 "TARGET_REALLY_IWMMXT"
1236 "wrord%?\\t%0, %1, %2"
1237 [(set_attr "predicable" "yes")])
1239 (define_insn "ashrv4hi3_di"
1240 [(set (match_operand:V4HI 0 "register_operand" "=y")
1241 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1242 (match_operand:DI 2 "register_operand" "y")))]
1243 "TARGET_REALLY_IWMMXT"
1244 "wsrah%?\\t%0, %1, %2"
1245 [(set_attr "predicable" "yes")])
1247 (define_insn "ashrv2si3_di"
1248 [(set (match_operand:V2SI 0 "register_operand" "=y")
1249 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1250 (match_operand:DI 2 "register_operand" "y")))]
1251 "TARGET_REALLY_IWMMXT"
1252 "wsraw%?\\t%0, %1, %2"
1253 [(set_attr "predicable" "yes")])
1255 (define_insn "ashrdi3_di"
1256 [(set (match_operand:DI 0 "register_operand" "=y")
1257 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
1258 (match_operand:DI 2 "register_operand" "y")))]
1259 "TARGET_REALLY_IWMMXT"
1260 "wsrad%?\\t%0, %1, %2"
1261 [(set_attr "predicable" "yes")])
1263 (define_insn "lshrv4hi3_di"
1264 [(set (match_operand:V4HI 0 "register_operand" "=y")
1265 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
1266 (match_operand:DI 2 "register_operand" "y")))]
1267 "TARGET_REALLY_IWMMXT"
1268 "wsrlh%?\\t%0, %1, %2"
1269 [(set_attr "predicable" "yes")])
1271 (define_insn "lshrv2si3_di"
1272 [(set (match_operand:V2SI 0 "register_operand" "=y")
1273 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
1274 (match_operand:DI 2 "register_operand" "y")))]
1275 "TARGET_REALLY_IWMMXT"
1276 "wsrlw%?\\t%0, %1, %2"
1277 [(set_attr "predicable" "yes")])
1279 (define_insn "lshrdi3_di"
1280 [(set (match_operand:DI 0 "register_operand" "=y")
1281 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
1282 (match_operand:DI 2 "register_operand" "y")))]
1283 "TARGET_REALLY_IWMMXT"
1284 "wsrld%?\\t%0, %1, %2"
1285 [(set_attr "predicable" "yes")])
1287 (define_insn "ashlv4hi3_di"
1288 [(set (match_operand:V4HI 0 "register_operand" "=y")
1289 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
1290 (match_operand:DI 2 "register_operand" "y")))]
1291 "TARGET_REALLY_IWMMXT"
1292 "wsllh%?\\t%0, %1, %2"
1293 [(set_attr "predicable" "yes")])
1295 (define_insn "ashlv2si3_di"
1296 [(set (match_operand:V2SI 0 "register_operand" "=y")
1297 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
1298 (match_operand:DI 2 "register_operand" "y")))]
1299 "TARGET_REALLY_IWMMXT"
1300 "wsllw%?\\t%0, %1, %2"
1301 [(set_attr "predicable" "yes")])
1303 (define_insn "ashldi3_di"
1304 [(set (match_operand:DI 0 "register_operand" "=y")
1305 (ashift:DI (match_operand:DI 1 "register_operand" "y")
1306 (match_operand:DI 2 "register_operand" "y")))]
1307 "TARGET_REALLY_IWMMXT"
1308 "wslld%?\\t%0, %1, %2"
1309 [(set_attr "predicable" "yes")])
1311 (define_insn "iwmmxt_wmadds"
1312 [(set (match_operand:V4HI 0 "register_operand" "=y")
1313 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1314 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
1315 "TARGET_REALLY_IWMMXT"
1316 "wmadds%?\\t%0, %1, %2"
1317 [(set_attr "predicable" "yes")])
1319 (define_insn "iwmmxt_wmaddu"
1320 [(set (match_operand:V4HI 0 "register_operand" "=y")
1321 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1322 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
1323 "TARGET_REALLY_IWMMXT"
1324 "wmaddu%?\\t%0, %1, %2"
1325 [(set_attr "predicable" "yes")])
1327 (define_insn "iwmmxt_tmia"
1328 [(set (match_operand:DI 0 "register_operand" "=y")
1329 (plus:DI (match_operand:DI 1 "register_operand" "0")
1330 (mult:DI (sign_extend:DI
1331 (match_operand:SI 2 "register_operand" "r"))
1332 (sign_extend:DI
1333 (match_operand:SI 3 "register_operand" "r")))))]
1334 "TARGET_REALLY_IWMMXT"
1335 "tmia%?\\t%0, %2, %3"
1336 [(set_attr "predicable" "yes")])
1338 (define_insn "iwmmxt_tmiaph"
1339 [(set (match_operand:DI 0 "register_operand" "=y")
1340 (plus:DI (match_operand:DI 1 "register_operand" "0")
1341 (plus:DI
1342 (mult:DI (sign_extend:DI
1343 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1344 (sign_extend:DI
1345 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1346 (mult:DI (sign_extend:DI
1347 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1348 (sign_extend:DI
1349 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1350 "TARGET_REALLY_IWMMXT"
1351 "tmiaph%?\\t%0, %2, %3"
1352 [(set_attr "predicable" "yes")])
1354 (define_insn "iwmmxt_tmiabb"
1355 [(set (match_operand:DI 0 "register_operand" "=y")
1356 (plus:DI (match_operand:DI 1 "register_operand" "0")
1357 (mult:DI (sign_extend:DI
1358 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1359 (sign_extend:DI
1360 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1361 "TARGET_REALLY_IWMMXT"
1362 "tmiabb%?\\t%0, %2, %3"
1363 [(set_attr "predicable" "yes")])
1365 (define_insn "iwmmxt_tmiatb"
1366 [(set (match_operand:DI 0 "register_operand" "=y")
1367 (plus:DI (match_operand:DI 1 "register_operand" "0")
1368 (mult:DI (sign_extend:DI
1369 (truncate:HI (ashiftrt:SI
1370 (match_operand:SI 2 "register_operand" "r")
1371 (const_int 16))))
1372 (sign_extend:DI
1373 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1374 "TARGET_REALLY_IWMMXT"
1375 "tmiatb%?\\t%0, %2, %3"
1376 [(set_attr "predicable" "yes")])
1378 (define_insn "iwmmxt_tmiabt"
1379 [(set (match_operand:DI 0 "register_operand" "=y")
1380 (plus:DI (match_operand:DI 1 "register_operand" "0")
1381 (mult:DI (sign_extend:DI
1382 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1383 (sign_extend:DI
1384 (truncate:HI (ashiftrt:SI
1385 (match_operand:SI 3 "register_operand" "r")
1386 (const_int 16)))))))]
1387 "TARGET_REALLY_IWMMXT"
1388 "tmiabt%?\\t%0, %2, %3"
1389 [(set_attr "predicable" "yes")])
1391 (define_insn "iwmmxt_tmiatt"
1392 [(set (match_operand:DI 0 "register_operand" "=y")
1393 (plus:DI (match_operand:DI 1 "register_operand" "0")
1394 (mult:DI (sign_extend:DI
1395 (truncate:HI (ashiftrt:SI
1396 (match_operand:SI 2 "register_operand" "r")
1397 (const_int 16))))
1398 (sign_extend:DI
1399 (truncate:HI (ashiftrt:SI
1400 (match_operand:SI 3 "register_operand" "r")
1401 (const_int 16)))))))]
1402 "TARGET_REALLY_IWMMXT"
1403 "tmiatt%?\\t%0, %2, %3"
1404 [(set_attr "predicable" "yes")])
1406 (define_insn "iwmmxt_tbcstqi"
1407 [(set (match_operand:V8QI 0 "register_operand" "=y")
1408 (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1409 "TARGET_REALLY_IWMMXT"
1410 "tbcstb%?\\t%0, %1"
1411 [(set_attr "predicable" "yes")])
1413 (define_insn "iwmmxt_tbcsthi"
1414 [(set (match_operand:V4HI 0 "register_operand" "=y")
1415 (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1416 "TARGET_REALLY_IWMMXT"
1417 "tbcsth%?\\t%0, %1"
1418 [(set_attr "predicable" "yes")])
1420 (define_insn "iwmmxt_tbcstsi"
1421 [(set (match_operand:V2SI 0 "register_operand" "=y")
1422 (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1423 "TARGET_REALLY_IWMMXT"
1424 "tbcstw%?\\t%0, %1"
1425 [(set_attr "predicable" "yes")])
1427 (define_insn "iwmmxt_tmovmskb"
1428 [(set (match_operand:SI 0 "register_operand" "=r")
1429 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1430 "TARGET_REALLY_IWMMXT"
1431 "tmovmskb%?\\t%0, %1"
1432 [(set_attr "predicable" "yes")])
1434 (define_insn "iwmmxt_tmovmskh"
1435 [(set (match_operand:SI 0 "register_operand" "=r")
1436 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1437 "TARGET_REALLY_IWMMXT"
1438 "tmovmskh%?\\t%0, %1"
1439 [(set_attr "predicable" "yes")])
1441 (define_insn "iwmmxt_tmovmskw"
1442 [(set (match_operand:SI 0 "register_operand" "=r")
1443 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1444 "TARGET_REALLY_IWMMXT"
1445 "tmovmskw%?\\t%0, %1"
1446 [(set_attr "predicable" "yes")])
1448 (define_insn "iwmmxt_waccb"
1449 [(set (match_operand:DI 0 "register_operand" "=y")
1450 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1451 "TARGET_REALLY_IWMMXT"
1452 "waccb%?\\t%0, %1"
1453 [(set_attr "predicable" "yes")])
1455 (define_insn "iwmmxt_wacch"
1456 [(set (match_operand:DI 0 "register_operand" "=y")
1457 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1458 "TARGET_REALLY_IWMMXT"
1459 "wacch%?\\t%0, %1"
1460 [(set_attr "predicable" "yes")])
1462 (define_insn "iwmmxt_waccw"
1463 [(set (match_operand:DI 0 "register_operand" "=y")
1464 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1465 "TARGET_REALLY_IWMMXT"
1466 "waccw%?\\t%0, %1"
1467 [(set_attr "predicable" "yes")])
1469 (define_insn "iwmmxt_walign"
1470 [(set (match_operand:V8QI 0 "register_operand" "=y,y")
1471 (subreg:V8QI (ashiftrt:TI
1472 (subreg:TI (vec_concat:V16QI
1473 (match_operand:V8QI 1 "register_operand" "y,y")
1474 (match_operand:V8QI 2 "register_operand" "y,y")) 0)
1475 (mult:SI
1476 (match_operand:SI 3 "nonmemory_operand" "i,z")
1477 (const_int 8))) 0))]
1478 "TARGET_REALLY_IWMMXT"
1479 "@
1480 waligni%?\\t%0, %1, %2, %3
1481 walignr%U3%?\\t%0, %1, %2"
1482 [(set_attr "predicable" "yes")])
1484 (define_insn "iwmmxt_tmrc"
1485 [(set (match_operand:SI 0 "register_operand" "=r")
1486 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1487 VUNSPEC_TMRC))]
1488 "TARGET_REALLY_IWMMXT"
1489 "tmrc%?\\t%0, %w1"
1490 [(set_attr "predicable" "yes")])
1492 (define_insn "iwmmxt_tmcr"
1493 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
1494 (match_operand:SI 1 "register_operand" "r")]
1495 VUNSPEC_TMCR)]
1496 "TARGET_REALLY_IWMMXT"
1497 "tmcr%?\\t%w0, %1"
1498 [(set_attr "predicable" "yes")])
1500 (define_insn "iwmmxt_wsadb"
1501 [(set (match_operand:V8QI 0 "register_operand" "=y")
1502 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1503 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
1504 "TARGET_REALLY_IWMMXT"
1505 "wsadb%?\\t%0, %1, %2"
1506 [(set_attr "predicable" "yes")])
1508 (define_insn "iwmmxt_wsadh"
1509 [(set (match_operand:V4HI 0 "register_operand" "=y")
1510 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1511 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
1512 "TARGET_REALLY_IWMMXT"
1513 "wsadh%?\\t%0, %1, %2"
1514 [(set_attr "predicable" "yes")])
1516 (define_insn "iwmmxt_wsadbz"
1517 [(set (match_operand:V8QI 0 "register_operand" "=y")
1518 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1519 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1520 "TARGET_REALLY_IWMMXT"
1521 "wsadbz%?\\t%0, %1, %2"
1522 [(set_attr "predicable" "yes")])
1524 (define_insn "iwmmxt_wsadhz"
1525 [(set (match_operand:V4HI 0 "register_operand" "=y")
1526 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
1527 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1528 "TARGET_REALLY_IWMMXT"
1529 "wsadhz%?\\t%0, %1, %2"
1530 [(set_attr "predicable" "yes")])