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* system.h: Poison NO_RECURSIVE_FUNCTION_CSE.
[official-gcc.git] / gcc / config / mips / mips.h
blobe22e1699f75b3fc8d1a9779bc0d5754a856839c0
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_SB1,
71 PROCESSOR_SR71000
72 };
73
74 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
75 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
76 to work on a 64 bit machine. */
77
78 #define ABI_32 0
79 #define ABI_N32 1
80 #define ABI_64 2
81 #define ABI_EABI 3
82 #define ABI_O64 4
83
84 /* Information about one recognized processor. Defined here for the
85 benefit of TARGET_CPU_CPP_BUILTINS. */
86 struct mips_cpu_info {
87 /* The 'canonical' name of the processor as far as GCC is concerned.
88 It's typically a manufacturer's prefix followed by a numerical
89 designation. It should be lower case. */
90 const char *name;
91
92 /* The internal processor number that most closely matches this
93 entry. Several processors can have the same value, if there's no
94 difference between them from GCC's point of view. */
95 enum processor_type cpu;
96
97 /* The ISA level that the processor implements. */
98 int isa;
99 };
100
101 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
102 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
103 extern const char *current_function_file; /* filename current function is in */
104 extern int num_source_filenames; /* current .file # */
105 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
106 extern int sym_lineno; /* sgi next label # for each stmt */
107 extern int set_noreorder; /* # of nested .set noreorder's */
108 extern int set_nomacro; /* # of nested .set nomacro's */
109 extern int set_noat; /* # of nested .set noat's */
110 extern int set_volatile; /* # of nested .set volatile's */
111 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
112 extern int mips_dbx_regno[]; /* Map register # to debug register # */
113 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
114 extern enum cmp_type branch_type; /* what type of branch to use */
115 extern enum processor_type mips_arch; /* which cpu to codegen for */
116 extern enum processor_type mips_tune; /* which cpu to schedule for */
117 extern int mips_isa; /* architectural level */
118 extern int mips_abi; /* which ABI to use */
119 extern int mips16_hard_float; /* mips16 without -msoft-float */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern const struct mips_cpu_info mips_cpu_info_table[];
126 extern const struct mips_cpu_info *mips_arch_info;
127 extern const struct mips_cpu_info *mips_tune_info;
128
129 /* Macros to silence warnings about numbers being signed in traditional
130 C and unsigned in ISO C when compiled on 32-bit hosts. */
131
132 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
133 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
134 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
135
136 \f
137 /* Run-time compilation parameters selecting different hardware subsets. */
138
139 /* Macros used in the machine description to test the flags. */
140
141 /* Bits for real switches */
142 #define MASK_INT64 0x00000001 /* ints are 64 bits */
143 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
144 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
145 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
146 multiply-add operations. */
147 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
148 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
149 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
150 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
151 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
152 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
153 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
154 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
155 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
156 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
157 #define MASK_EMBEDDED_DATA 0x00004000 /* Reduce RAM usage, not fast code */
158 #define MASK_BIG_ENDIAN 0x00008000 /* Generate big endian code */
159 #define MASK_SINGLE_FLOAT 0x00010000 /* Only single precision FPU. */
160 #define MASK_MAD 0x00020000 /* Generate mad/madu as on 4650. */
161 #define MASK_4300_MUL_FIX 0x00040000 /* Work-around early Vr4300 CPU bug */
162 #define MASK_MIPS16 0x00080000 /* Generate mips16 code */
163 #define MASK_NO_CHECK_ZERO_DIV \
164 0x00100000 /* divide by zero checking */
165 #define MASK_BRANCHLIKELY 0x00200000 /* Generate Branch Likely
166 instructions. */
167 #define MASK_UNINIT_CONST_IN_RODATA \
168 0x00400000 /* Store uninitialized
169 consts in rodata */
170 #define MASK_FIX_R4000 0x00800000 /* Work around R4000 errata. */
171 #define MASK_FIX_R4400 0x01000000 /* Work around R4400 errata. */
172 #define MASK_FIX_SB1 0x02000000 /* Work around SB-1 errata. */
173 #define MASK_FIX_VR4120 0x04000000 /* Work around VR4120 errata. */
174 #define MASK_VR4130_ALIGN 0x08000000 /* Perform VR4130 alignment opts. */
175 #define MASK_FP_EXCEPTIONS 0x10000000 /* FP exceptions are enabled. */
176
177 /* Debug switches, not documented */
178 #define MASK_DEBUG 0 /* unused */
179 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
180 #define MASK_DEBUG_D 0 /* don't do define_split's */
181
182 /* Dummy switches used only in specs */
183 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
184
185 /* r4000 64 bit sizes */
186 #define TARGET_INT64 (target_flags & MASK_INT64)
187 #define TARGET_LONG64 (target_flags & MASK_LONG64)
188 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
189 #define TARGET_64BIT (target_flags & MASK_64BIT)
190
191 /* Mips vs. GNU linker */
192 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
193
194 /* Mips vs. GNU assembler */
195 #define TARGET_GAS (target_flags & MASK_GAS)
196 #define TARGET_MIPS_AS (!TARGET_GAS)
197
198 /* Debug Modes */
199 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
200 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
201 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
202
203 /* Reg. Naming in .s ($21 vs. $a0) */
204 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
205
206 /* call memcpy instead of inline code */
207 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
208
209 /* .abicalls, etc from Pyramid V.4 */
210 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
211 #define TARGET_XGOT (target_flags & MASK_XGOT)
212
213 /* software floating point */
214 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
215 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
216
217 /* always call through a register */
218 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
219
220 /* for embedded systems, optimize for
221 reduced RAM space instead of for
222 fastest code. */
223 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
224
225 /* always store uninitialized const
226 variables in rodata, requires
227 TARGET_EMBEDDED_DATA. */
228 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
229
230 /* generate big endian code. */
231 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
232
233 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
234 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
235
236 #define TARGET_MAD (target_flags & MASK_MAD)
237
238 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
239
240 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
241
242 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
243
244 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
245
246 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
247
248 /* Work around R4000 errata. */
249 #define TARGET_FIX_R4000 (target_flags & MASK_FIX_R4000)
250
251 /* Work around R4400 errata. */
252 #define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400)
253 #define TARGET_FIX_VR4120 (target_flags & MASK_FIX_VR4120)
254 #define TARGET_VR4130_ALIGN (target_flags & MASK_VR4130_ALIGN)
255
256 #define TARGET_FP_EXCEPTIONS (target_flags & MASK_FP_EXCEPTIONS)
257
258 /* True if we should use NewABI-style relocation operators for
259 symbolic addresses. This is never true for mips16 code,
260 which has its own conventions. */
261
262 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
263
264
265 /* True if the call patterns should be split into a jalr followed by
266 an instruction to restore $gp. This is only ever true for SVR4 PIC,
267 in which $gp is call-clobbered. It is only safe to split the load
268 from the call when every use of $gp is explicit. */
269
270 #define TARGET_SPLIT_CALLS \
271 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
272
273 /* True if we can optimize sibling calls. For simplicity, we only
274 handle cases in which call_insn_operand will reject invalid
275 sibcall addresses. There are two cases in which this isn't true:
276
277 - TARGET_MIPS16. call_insn_operand accepts constant addresses
278 but there is no direct jump instruction. It isn't worth
279 using sibling calls in this case anyway; they would usually
280 be longer than normal calls.
281
282 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
283 accepts global constants, but "jr $25" is the only allowed
284 sibcall. */
285
286 #define TARGET_SIBCALLS \
287 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
288
289 /* True if .gpword or .gpdword should be used for switch tables.
290 There are some problems with using these directives with the
291 native IRIX tools:
292
293 - It has been reported that some versions of the native n32
294 assembler mishandle .gpword, complaining that symbols are
295 global when they are in fact local.
296
297 - The native assemblers don't understand .gpdword.
298
299 - Although GAS does understand .gpdword, the native linker
300 mishandles the relocations GAS generates (R_MIPS_GPREL32
301 followed by R_MIPS_64).
302
303 We therefore disable GP-relative switch tables for n32 and n64
304 on IRIX targets. */
305 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
306
307 /* Generate mips16 code */
308 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
309
310 /* Generic ISA defines. */
311 #define ISA_MIPS1 (mips_isa == 1)
312 #define ISA_MIPS2 (mips_isa == 2)
313 #define ISA_MIPS3 (mips_isa == 3)
314 #define ISA_MIPS4 (mips_isa == 4)
315 #define ISA_MIPS32 (mips_isa == 32)
316 #define ISA_MIPS32R2 (mips_isa == 33)
317 #define ISA_MIPS64 (mips_isa == 64)
318
319 /* Architecture target defines. */
320 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
321 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
322 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
323 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
324 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
325 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
326 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
327 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
328 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
329
330 /* Scheduling target defines. */
331 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
332 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
333 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
334 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
335 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
336 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
337 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
338 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
339 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
340 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
341 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
342 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
343
344 /* True if the pre-reload scheduler should try to create chains of
345 multiply-add or multiply-subtract instructions. For example,
346 suppose we have:
347
348 t1 = a * b
349 t2 = t1 + c * d
350 t3 = e * f
351 t4 = t3 - g * h
352
353 t1 will have a higher priority than t2 and t3 will have a higher
354 priority than t4. However, before reload, there is no dependence
355 between t1 and t3, and they can often have similar priorities.
356 The scheduler will then tend to prefer:
357
358 t1 = a * b
359 t3 = e * f
360 t2 = t1 + c * d
361 t4 = t3 - g * h
362
363 which stops us from making full use of macc/madd-style instructions.
364 This sort of situation occurs frequently in Fourier transforms and
365 in unrolled loops.
366
367 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
368 queue so that chained multiply-add and multiply-subtract instructions
369 appear ahead of any other instruction that is likely to clobber lo.
370 In the example above, if t2 and t3 become ready at the same time,
371 the code ensures that t2 is scheduled first.
372
373 Multiply-accumulate instructions are a bigger win for some targets
374 than others, so this macro is defined on an opt-in basis. */
375 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
376 || TUNE_MIPS4120 \
377 || TUNE_MIPS4130)
378
379 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
380 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
381
382 /* IRIX specific stuff. */
383 #define TARGET_IRIX 0
384 #define TARGET_IRIX5 0
385 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
386
387 /* Define preprocessor macros for the -march and -mtune options.
388 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
389 processor. If INFO's canonical name is "foo", define PREFIX to
390 be "foo", and define an additional macro PREFIX_FOO. */
391 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
392 do \
393 { \
394 char *macro, *p; \
395 \
396 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
397 for (p = macro; *p != 0; p++) \
398 *p = TOUPPER (*p); \
399 \
400 builtin_define (macro); \
401 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
402 free (macro); \
403 } \
404 while (0)
405
406 /* Target CPU builtins. */
407 #define TARGET_CPU_CPP_BUILTINS() \
408 do \
409 { \
410 builtin_assert ("cpu=mips"); \
411 builtin_define ("__mips__"); \
412 builtin_define ("_mips"); \
413 \
414 /* We do this here because __mips is defined below \
415 and so we can't use builtin_define_std. */ \
416 if (!flag_iso) \
417 builtin_define ("mips"); \
418 \
419 /* Treat _R3000 and _R4000 like register-size defines, \
420 which is how they've historically been used. */ \
421 if (TARGET_64BIT) \
422 { \
423 builtin_define ("__mips64"); \
424 builtin_define_std ("R4000"); \
425 builtin_define ("_R4000"); \
426 } \
427 else \
428 { \
429 builtin_define_std ("R3000"); \
430 builtin_define ("_R3000"); \
431 } \
432 if (TARGET_FLOAT64) \
433 builtin_define ("__mips_fpr=64"); \
434 else \
435 builtin_define ("__mips_fpr=32"); \
436 \
437 if (TARGET_MIPS16) \
438 builtin_define ("__mips16"); \
439 \
440 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
441 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
442 \
443 if (ISA_MIPS1) \
444 { \
445 builtin_define ("__mips=1"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
447 } \
448 else if (ISA_MIPS2) \
449 { \
450 builtin_define ("__mips=2"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
452 } \
453 else if (ISA_MIPS3) \
454 { \
455 builtin_define ("__mips=3"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
457 } \
458 else if (ISA_MIPS4) \
459 { \
460 builtin_define ("__mips=4"); \
461 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
462 } \
463 else if (ISA_MIPS32) \
464 { \
465 builtin_define ("__mips=32"); \
466 builtin_define ("__mips_isa_rev=1"); \
467 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
468 } \
469 else if (ISA_MIPS32R2) \
470 { \
471 builtin_define ("__mips=32"); \
472 builtin_define ("__mips_isa_rev=2"); \
473 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
474 } \
475 else if (ISA_MIPS64) \
476 { \
477 builtin_define ("__mips=64"); \
478 builtin_define ("__mips_isa_rev=1"); \
479 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
480 } \
481 \
482 if (TARGET_HARD_FLOAT) \
483 builtin_define ("__mips_hard_float"); \
484 else if (TARGET_SOFT_FLOAT) \
485 builtin_define ("__mips_soft_float"); \
486 \
487 if (TARGET_SINGLE_FLOAT) \
488 builtin_define ("__mips_single_float"); \
489 \
490 if (TARGET_BIG_ENDIAN) \
491 { \
492 builtin_define_std ("MIPSEB"); \
493 builtin_define ("_MIPSEB"); \
494 } \
495 else \
496 { \
497 builtin_define_std ("MIPSEL"); \
498 builtin_define ("_MIPSEL"); \
499 } \
500 \
501 /* Macros dependent on the C dialect. */ \
502 if (preprocessing_asm_p ()) \
503 { \
504 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
505 builtin_define ("_LANGUAGE_ASSEMBLY"); \
506 } \
507 else if (c_dialect_cxx ()) \
508 { \
509 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
510 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
511 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
512 } \
513 else \
514 { \
515 builtin_define_std ("LANGUAGE_C"); \
516 builtin_define ("_LANGUAGE_C"); \
517 } \
518 if (c_dialect_objc ()) \
519 { \
520 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
521 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
522 /* Bizarre, but needed at least for Irix. */ \
523 builtin_define_std ("LANGUAGE_C"); \
524 builtin_define ("_LANGUAGE_C"); \
525 } \
526 \
527 if (mips_abi == ABI_EABI) \
528 builtin_define ("__mips_eabi"); \
529 \
530 } while (0)
531
532
533
534 /* Macro to define tables used to set the flags.
535 This is a list in braces of pairs in braces,
536 each pair being { "NAME", VALUE }
537 where VALUE is the bits to set or minus the bits to clear.
538 An empty string NAME is used to identify the default VALUE. */
539
540 #define TARGET_SWITCHES \
541 { \
542 SUBTARGET_TARGET_SWITCHES \
543 {"int64", MASK_INT64 | MASK_LONG64, \
544 N_("Use 64-bit int type")}, \
545 {"long64", MASK_LONG64, \
546 N_("Use 64-bit long type")}, \
547 {"long32", -(MASK_LONG64 | MASK_INT64), \
548 N_("Use 32-bit long type")}, \
549 {"split-addresses", MASK_SPLIT_ADDR, \
550 N_("Optimize lui/addiu address loads")}, \
551 {"no-split-addresses", -MASK_SPLIT_ADDR, \
552 N_("Don't optimize lui/addiu address loads")}, \
553 {"mips-as", -MASK_GAS, \
554 N_("Use MIPS as")}, \
555 {"gas", MASK_GAS, \
556 N_("Use GNU as")}, \
557 {"rnames", MASK_NAME_REGS, \
558 N_("Use symbolic register names")}, \
559 {"no-rnames", -MASK_NAME_REGS, \
560 N_("Don't use symbolic register names")}, \
561 {"gpOPT", 0, \
562 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
563 {"gpopt", 0, \
564 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
565 {"no-gpOPT", 0, \
566 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
567 {"no-gpopt", 0, \
568 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
569 {"stats", 0, \
570 N_("Output compiler statistics (now ignored)")}, \
571 {"no-stats", 0, \
572 N_("Don't output compiler statistics")}, \
573 {"memcpy", MASK_MEMCPY, \
574 N_("Don't optimize block moves")}, \
575 {"no-memcpy", -MASK_MEMCPY, \
576 N_("Optimize block moves")}, \
577 {"mips-tfile", MASK_MIPS_TFILE, \
578 N_("Use mips-tfile asm postpass")}, \
579 {"no-mips-tfile", -MASK_MIPS_TFILE, \
580 N_("Don't use mips-tfile asm postpass")}, \
581 {"soft-float", MASK_SOFT_FLOAT, \
582 N_("Use software floating point")}, \
583 {"hard-float", -MASK_SOFT_FLOAT, \
584 N_("Use hardware floating point")}, \
585 {"fp64", MASK_FLOAT64, \
586 N_("Use 64-bit FP registers")}, \
587 {"fp32", -MASK_FLOAT64, \
588 N_("Use 32-bit FP registers")}, \
589 {"gp64", MASK_64BIT, \
590 N_("Use 64-bit general registers")}, \
591 {"gp32", -MASK_64BIT, \
592 N_("Use 32-bit general registers")}, \
593 {"abicalls", MASK_ABICALLS, \
594 N_("Use Irix PIC")}, \
595 {"no-abicalls", -MASK_ABICALLS, \
596 N_("Don't use Irix PIC")}, \
597 {"long-calls", MASK_LONG_CALLS, \
598 N_("Use indirect calls")}, \
599 {"no-long-calls", -MASK_LONG_CALLS, \
600 N_("Don't use indirect calls")}, \
601 {"embedded-data", MASK_EMBEDDED_DATA, \
602 N_("Use ROM instead of RAM")}, \
603 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
604 N_("Don't use ROM instead of RAM")}, \
605 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
606 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
607 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
608 N_("Don't put uninitialized constants in ROM")}, \
609 {"eb", MASK_BIG_ENDIAN, \
610 N_("Use big-endian byte order")}, \
611 {"el", -MASK_BIG_ENDIAN, \
612 N_("Use little-endian byte order")}, \
613 {"single-float", MASK_SINGLE_FLOAT, \
614 N_("Use single (32-bit) FP only")}, \
615 {"double-float", -MASK_SINGLE_FLOAT, \
616 N_("Don't use single (32-bit) FP only")}, \
617 {"mad", MASK_MAD, \
618 N_("Use multiply accumulate")}, \
619 {"no-mad", -MASK_MAD, \
620 N_("Don't use multiply accumulate")}, \
621 {"no-fused-madd", MASK_NO_FUSED_MADD, \
622 N_("Don't generate fused multiply/add instructions")}, \
623 {"fused-madd", -MASK_NO_FUSED_MADD, \
624 N_("Generate fused multiply/add instructions")}, \
625 {"vr4130-align", MASK_VR4130_ALIGN, \
626 N_("Perform VR4130-specific alignment optimizations")}, \
627 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
628 N_("Don't perform VR4130-specific alignment optimizations")}, \
629 {"fix4300", MASK_4300_MUL_FIX, \
630 N_("Work around early 4300 hardware bug")}, \
631 {"no-fix4300", -MASK_4300_MUL_FIX, \
632 N_("Don't work around early 4300 hardware bug")}, \
633 {"fix-sb1", MASK_FIX_SB1, \
634 N_("Work around errata for early SB-1 revision 2 cores")}, \
635 {"no-fix-sb1", -MASK_FIX_SB1, \
636 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
637 {"fix-r4000", MASK_FIX_R4000, \
638 N_("Work around R4000 errata")}, \
639 {"no-fix-r4000", -MASK_FIX_R4000, \
640 N_("Don't work around R4000 errata")}, \
641 {"fix-r4400", MASK_FIX_R4400, \
642 N_("Work around R4400 errata")}, \
643 {"no-fix-r4400", -MASK_FIX_R4400, \
644 N_("Don't work around R4400 errata")}, \
645 {"fix-vr4120", MASK_FIX_VR4120, \
646 N_("Work around certain VR4120 errata")}, \
647 {"no-fix-vr4120", -MASK_FIX_VR4120, \
648 N_("Don't work around certain VR4120 errata")}, \
649 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
650 N_("Trap on integer divide by zero")}, \
651 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
652 N_("Don't trap on integer divide by zero")}, \
653 { "branch-likely", MASK_BRANCHLIKELY, \
654 N_("Use Branch Likely instructions, overriding default for arch")}, \
655 { "no-branch-likely", -MASK_BRANCHLIKELY, \
656 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
657 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
658 N_("Use NewABI-style %reloc() assembly operators")}, \
659 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
660 N_("Use assembler macros instead of relocation operators")}, \
661 {"ips16", MASK_MIPS16, \
662 N_("Generate mips16 code") }, \
663 {"no-mips16", -MASK_MIPS16, \
664 N_("Generate normal-mode code") }, \
665 {"xgot", MASK_XGOT, \
666 N_("Lift restrictions on GOT size") }, \
667 {"no-xgot", -MASK_XGOT, \
668 N_("Do not lift restrictions on GOT size") }, \
669 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
670 N_("FP exceptions are enabled") }, \
671 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
672 N_("FP exceptions are not enabled") }, \
673 {"debug", MASK_DEBUG, \
674 NULL}, \
675 {"debugc", MASK_DEBUG_C, \
676 NULL}, \
677 {"debugd", MASK_DEBUG_D, \
678 NULL}, \
679 {"", (TARGET_DEFAULT \
680 | TARGET_CPU_DEFAULT \
681 | TARGET_ENDIAN_DEFAULT \
682 | TARGET_FP_EXCEPTIONS_DEFAULT), \
683 NULL}, \
684 }
685
686 /* Default target_flags if no switches are specified */
687
688 #ifndef TARGET_DEFAULT
689 #define TARGET_DEFAULT 0
690 #endif
691
692 #ifndef TARGET_CPU_DEFAULT
693 #define TARGET_CPU_DEFAULT 0
694 #endif
695
696 #ifndef TARGET_ENDIAN_DEFAULT
697 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
698 #endif
699
700 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
701 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
702 #endif
703
704 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
705 #ifndef MIPS_ISA_DEFAULT
706 #ifndef MIPS_CPU_STRING_DEFAULT
707 #define MIPS_CPU_STRING_DEFAULT "from-abi"
708 #endif
709 #endif
710
711 #ifdef IN_LIBGCC2
712 #undef TARGET_64BIT
713 /* Make this compile time constant for libgcc2 */
714 #ifdef __mips64
715 #define TARGET_64BIT 1
716 #else
717 #define TARGET_64BIT 0
718 #endif
719 #endif /* IN_LIBGCC2 */
720
721 #ifndef MULTILIB_ENDIAN_DEFAULT
722 #if TARGET_ENDIAN_DEFAULT == 0
723 #define MULTILIB_ENDIAN_DEFAULT "EL"
724 #else
725 #define MULTILIB_ENDIAN_DEFAULT "EB"
726 #endif
727 #endif
728
729 #ifndef MULTILIB_ISA_DEFAULT
730 # if MIPS_ISA_DEFAULT == 1
731 # define MULTILIB_ISA_DEFAULT "mips1"
732 # else
733 # if MIPS_ISA_DEFAULT == 2
734 # define MULTILIB_ISA_DEFAULT "mips2"
735 # else
736 # if MIPS_ISA_DEFAULT == 3
737 # define MULTILIB_ISA_DEFAULT "mips3"
738 # else
739 # if MIPS_ISA_DEFAULT == 4
740 # define MULTILIB_ISA_DEFAULT "mips4"
741 # else
742 # if MIPS_ISA_DEFAULT == 32
743 # define MULTILIB_ISA_DEFAULT "mips32"
744 # else
745 # if MIPS_ISA_DEFAULT == 33
746 # define MULTILIB_ISA_DEFAULT "mips32r2"
747 # else
748 # if MIPS_ISA_DEFAULT == 64
749 # define MULTILIB_ISA_DEFAULT "mips64"
750 # else
751 # define MULTILIB_ISA_DEFAULT "mips1"
752 # endif
753 # endif
754 # endif
755 # endif
756 # endif
757 # endif
758 # endif
759 #endif
760
761 #ifndef MULTILIB_DEFAULTS
762 #define MULTILIB_DEFAULTS \
763 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
764 #endif
765
766 /* We must pass -EL to the linker by default for little endian embedded
767 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
768 linker will default to using big-endian output files. The OUTPUT_FORMAT
769 line must be in the linker script, otherwise -EB/-EL will not work. */
770
771 #ifndef ENDIAN_SPEC
772 #if TARGET_ENDIAN_DEFAULT == 0
773 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
774 #else
775 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
776 #endif
777 #endif
778
779 #define TARGET_OPTIONS \
780 { \
781 SUBTARGET_TARGET_OPTIONS \
782 { "tune=", &mips_tune_string, \
783 N_("Specify CPU for scheduling purposes"), 0}, \
784 { "arch=", &mips_arch_string, \
785 N_("Specify CPU for code generation purposes"), 0}, \
786 { "abi=", &mips_abi_string, \
787 N_("Specify an ABI"), 0}, \
788 { "ips", &mips_isa_string, \
789 N_("Specify a Standard MIPS ISA"), 0}, \
790 { "no-flush-func", &mips_cache_flush_func, \
791 N_("Don't call any cache flush functions"), 0}, \
792 { "flush-func=", &mips_cache_flush_func, \
793 N_("Specify cache flush function"), 0}, \
794 }
795
796 /* This is meant to be redefined in the host dependent files. */
797 #define SUBTARGET_TARGET_OPTIONS
798
799 /* Support for a compile-time default CPU, et cetera. The rules are:
800 --with-arch is ignored if -march is specified or a -mips is specified
801 (other than -mips16).
802 --with-tune is ignored if -mtune is specified.
803 --with-abi is ignored if -mabi is specified.
804 --with-float is ignored if -mhard-float or -msoft-float are
805 specified. */
806 #define OPTION_DEFAULT_SPECS \
807 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
808 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
809 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
810 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
811
812
813 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
814 && !TARGET_SR71K \
815 && !TARGET_MIPS16)
816
817 /* Generate three-operand multiply instructions for SImode. */
818 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
819 || TARGET_MIPS5400 \
820 || TARGET_MIPS5500 \
821 || TARGET_MIPS7000 \
822 || TARGET_MIPS9000 \
823 || ISA_MIPS32 \
824 || ISA_MIPS32R2 \
825 || ISA_MIPS64) \
826 && !TARGET_MIPS16)
827
828 /* Generate three-operand multiply instructions for DImode. */
829 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
830 && !TARGET_MIPS16)
831
832 /* Macros to decide whether certain features are available or not,
833 depending on the instruction set architecture level. */
834
835 #define HAVE_SQRT_P() (!ISA_MIPS1)
836
837 /* True if the ABI can only work with 64-bit integer registers. We
838 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
839 otherwise floating-point registers must also be 64-bit. */
840 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
841
842 /* Likewise for 32-bit regs. */
843 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
844
845 /* True if symbols are 64 bits wide. At present, n64 is the only
846 ABI for which this is true. */
847 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
848
849 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
850 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
851 || ISA_MIPS4 \
852 || ISA_MIPS64)
853
854 /* ISA has branch likely instructions (eg. mips2). */
855 /* Disable branchlikely for tx39 until compare rewrite. They haven't
856 been generated up to this point. */
857 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
858
859 /* ISA has the conditional move instructions introduced in mips4. */
860 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
861 || ISA_MIPS32 \
862 || ISA_MIPS32R2 \
863 || ISA_MIPS64) \
864 && !TARGET_MIPS5500 \
865 && !TARGET_MIPS16)
866
867 /* ISA has just the integer condition move instructions (movn,movz) */
868 #define ISA_HAS_INT_CONDMOVE 0
869
870 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
871 branch on CC, and move (both FP and non-FP) on CC. */
872 #define ISA_HAS_8CC (ISA_MIPS4 \
873 || ISA_MIPS32 \
874 || ISA_MIPS32R2 \
875 || ISA_MIPS64)
876
877 /* This is a catch all for other mips4 instructions: indexed load, the
878 FP madd and msub instructions, and the FP recip and recip sqrt
879 instructions. */
880 #define ISA_HAS_FP4 ((ISA_MIPS4 \
881 || ISA_MIPS64) \
882 && !TARGET_MIPS16)
883
884 /* ISA has conditional trap instructions. */
885 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
886 && !TARGET_MIPS16)
887
888 /* ISA has integer multiply-accumulate instructions, madd and msub. */
889 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
890 || ISA_MIPS32R2 \
891 || ISA_MIPS64 \
892 ) && !TARGET_MIPS16)
893
894 /* ISA has floating-point nmadd and nmsub instructions. */
895 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
896 || ISA_MIPS64) \
897 && (!TARGET_MIPS5400 || TARGET_MAD) \
898 && ! TARGET_MIPS16)
899
900 /* ISA has count leading zeroes/ones instruction (not implemented). */
901 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
902 || ISA_MIPS32R2 \
903 || ISA_MIPS64 \
904 ) && !TARGET_MIPS16)
905
906 /* ISA has double-word count leading zeroes/ones instruction (not
907 implemented). */
908 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
909 && !TARGET_MIPS16)
910
911 /* ISA has three operand multiply instructions that put
912 the high part in an accumulator: mulhi or mulhiu. */
913 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
914 || TARGET_MIPS5500 \
915 || TARGET_SR71K \
916 )
917
918 /* ISA has three operand multiply instructions that
919 negates the result and puts the result in an accumulator. */
920 #define ISA_HAS_MULS (TARGET_MIPS5400 \
921 || TARGET_MIPS5500 \
922 || TARGET_SR71K \
923 )
924
925 /* ISA has three operand multiply instructions that subtracts the
926 result from a 4th operand and puts the result in an accumulator. */
927 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
928 || TARGET_MIPS5500 \
929 || TARGET_SR71K \
930 )
931 /* ISA has three operand multiply instructions that the result
932 from a 4th operand and puts the result in an accumulator. */
933 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
934 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
935 || TARGET_MIPS5400 \
936 || TARGET_MIPS5500 \
937 || TARGET_SR71K \
938 )
939
940 /* ISA has 32-bit rotate right instruction. */
941 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
942 && (ISA_MIPS32R2 \
943 || TARGET_MIPS5400 \
944 || TARGET_MIPS5500 \
945 || TARGET_SR71K \
946 ))
947
948 /* ISA has 64-bit rotate right instruction. */
949 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
950 && !TARGET_MIPS16 \
951 && (TARGET_MIPS5400 \
952 || TARGET_MIPS5500 \
953 || TARGET_SR71K \
954 ))
955
956 /* ISA has data prefetch instructions. This controls use of 'pref'. */
957 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
958 || ISA_MIPS32 \
959 || ISA_MIPS32R2 \
960 || ISA_MIPS64) \
961 && !TARGET_MIPS16)
962
963 /* ISA has data indexed prefetch instructions. This controls use of
964 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
965 (prefx is a cop1x instruction, so can only be used if FP is
966 enabled.) */
967 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
968 || ISA_MIPS64) \
969 && !TARGET_MIPS16)
970
971 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
972 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
973 also requires TARGET_DOUBLE_FLOAT. */
974 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
975
976 /* ISA includes the MIPS32r2 seb and seh instructions. */
977 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
978 && (ISA_MIPS32R2 \
979 ))
980
981 /* True if the result of a load is not available to the next instruction.
982 A nop will then be needed between instructions like "lw $4,..."
983 and "addiu $4,$4,1". */
984 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
985 && !TARGET_MIPS3900 \
986 && !TARGET_MIPS16)
987
988 /* Likewise mtc1 and mfc1. */
989 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
990
991 /* Likewise floating-point comparisons. */
992 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
993
994 /* True if mflo and mfhi can be immediately followed by instructions
995 which write to the HI and LO registers.
996
997 According to MIPS specifications, MIPS ISAs I, II, and III need
998 (at least) two instructions between the reads of HI/LO and
999 instructions which write them, and later ISAs do not. Contradicting
1000 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1001 the UM for the NEC Vr5000) document needing the instructions between
1002 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1003 MIPS64 and later ISAs to have the interlocks, plus any specific
1004 earlier-ISA CPUs for which CPU documentation declares that the
1005 instructions are really interlocked. */
1006 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1007 || ISA_MIPS32R2 \
1008 || ISA_MIPS64 \
1009 || TARGET_MIPS5500)
1010 \f
1011 /* Add -G xx support. */
1012
1013 #undef SWITCH_TAKES_ARG
1014 #define SWITCH_TAKES_ARG(CHAR) \
1015 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1016
1017 #define OVERRIDE_OPTIONS override_options ()
1018
1019 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1020
1021 /* Show we can debug even without a frame pointer. */
1022 #define CAN_DEBUG_WITHOUT_FP
1023 \f
1024 /* Tell collect what flags to pass to nm. */
1025 #ifndef NM_FLAGS
1026 #define NM_FLAGS "-Bn"
1027 #endif
1028
1029 \f
1030 /* Assembler specs. */
1031
1032 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1033 than gas. */
1034
1035 #define MIPS_AS_ASM_SPEC "\
1036 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1037 %{pipe: %e-pipe is not supported} \
1038 %{K} %(subtarget_mips_as_asm_spec)"
1039
1040 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1041 rather than gas. It may be overridden by subtargets. */
1042
1043 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1044 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1045 #endif
1046
1047 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1048 assembler. */
1049
1050 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1051
1052 #define SUBTARGET_TARGET_SWITCHES
1053
1054 #ifndef MIPS_ABI_DEFAULT
1055 #define MIPS_ABI_DEFAULT ABI_32
1056 #endif
1057
1058 /* Use the most portable ABI flag for the ASM specs. */
1059
1060 #if MIPS_ABI_DEFAULT == ABI_32
1061 #define MULTILIB_ABI_DEFAULT "mabi=32"
1062 #define ASM_ABI_DEFAULT_SPEC "-32"
1063 #endif
1064
1065 #if MIPS_ABI_DEFAULT == ABI_O64
1066 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1067 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1068 #endif
1069
1070 #if MIPS_ABI_DEFAULT == ABI_N32
1071 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1072 #define ASM_ABI_DEFAULT_SPEC "-n32"
1073 #endif
1074
1075 #if MIPS_ABI_DEFAULT == ABI_64
1076 #define MULTILIB_ABI_DEFAULT "mabi=64"
1077 #define ASM_ABI_DEFAULT_SPEC "-64"
1078 #endif
1079
1080 #if MIPS_ABI_DEFAULT == ABI_EABI
1081 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1082 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1083 #endif
1084
1085 /* Only ELF targets can switch the ABI. */
1086 #ifndef OBJECT_FORMAT_ELF
1087 #undef ASM_ABI_DEFAULT_SPEC
1088 #define ASM_ABI_DEFAULT_SPEC ""
1089 #endif
1090
1091 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1092 GAS_ASM_SPEC as the default, depending upon the value of
1093 TARGET_DEFAULT. */
1094
1095 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1096 /* GAS */
1097
1098 #define TARGET_ASM_SPEC "\
1099 %{mmips-as: %(mips_as_asm_spec)} \
1100 %{!mmips-as: %(gas_asm_spec)}"
1101
1102 #else /* not GAS */
1103
1104 #define TARGET_ASM_SPEC "\
1105 %{!mgas: %(mips_as_asm_spec)} \
1106 %{mgas: %(gas_asm_spec)}"
1107
1108 #endif /* not GAS */
1109
1110 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1111 to the assembler. It may be overridden by subtargets. */
1112 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1113 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1114 %{noasmopt:-O0} \
1115 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1116 #endif
1117
1118 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1119 the assembler. It may be overridden by subtargets. */
1120 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1121 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1122 %{g} %{g0} %{g1} %{g2} %{g3} \
1123 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1124 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1125 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1126 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1127 %(mdebug_asm_spec)"
1128 #endif
1129
1130 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1131 debugging info. */
1132 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1133 /* GAS */
1134 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1135 %{!gcoff*:-no-mdebug}"
1136 #else /* not GAS */
1137 #define MDEBUG_ASM_SPEC ""
1138 #endif /* not GAS */
1139
1140 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1141 overridden by subtargets. */
1142
1143 #ifndef SUBTARGET_ASM_SPEC
1144 #define SUBTARGET_ASM_SPEC ""
1145 #endif
1146
1147 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1148 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1149 whether we're using GAS. These options can only be used properly
1150 with GAS, and it is better to get an error from a non-GAS assembler
1151 than to silently generate bad code. */
1152
1153 #undef ASM_SPEC
1154 #define ASM_SPEC "\
1155 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1156 %{mips32} %{mips32r2} %{mips64} \
1157 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1158 %{mfix-vr4120} \
1159 %(subtarget_asm_optimizing_spec) \
1160 %(subtarget_asm_debugging_spec) \
1161 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1162 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1163 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1164 %(target_asm_spec) \
1165 %(subtarget_asm_spec)"
1166
1167 /* Extra switches sometimes passed to the linker. */
1168 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1169 will interpret it as a -b option. */
1170
1171 #ifndef LINK_SPEC
1172 #define LINK_SPEC "\
1173 %(endian_spec) \
1174 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1175 %{bestGnum} %{shared} %{non_shared}"
1176 #endif /* LINK_SPEC defined */
1177
1178
1179 /* Specs for the compiler proper */
1180
1181 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1182 overridden by subtargets. */
1183 #ifndef SUBTARGET_CC1_SPEC
1184 #define SUBTARGET_CC1_SPEC ""
1185 #endif
1186
1187 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1188
1189 #ifndef CC1_SPEC
1190 #define CC1_SPEC "\
1191 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1192 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1193 %{save-temps: } \
1194 %(subtarget_cc1_spec)"
1195 #endif
1196
1197 /* Preprocessor specs. */
1198
1199 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1200 overridden by subtargets. */
1201 #ifndef SUBTARGET_CPP_SPEC
1202 #define SUBTARGET_CPP_SPEC ""
1203 #endif
1204
1205 #define CPP_SPEC "%(subtarget_cpp_spec)"
1206
1207 /* This macro defines names of additional specifications to put in the specs
1208 that can be used in various specifications like CC1_SPEC. Its definition
1209 is an initializer with a subgrouping for each command option.
1210
1211 Each subgrouping contains a string constant, that defines the
1212 specification name, and a string constant that used by the GCC driver
1213 program.
1214
1215 Do not define this macro if it does not need to do anything. */
1216
1217 #define EXTRA_SPECS \
1218 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1219 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1220 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1221 { "gas_asm_spec", GAS_ASM_SPEC }, \
1222 { "target_asm_spec", TARGET_ASM_SPEC }, \
1223 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1224 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1225 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1226 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1227 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1228 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1229 { "endian_spec", ENDIAN_SPEC }, \
1230 SUBTARGET_EXTRA_SPECS
1231
1232 #ifndef SUBTARGET_EXTRA_SPECS
1233 #define SUBTARGET_EXTRA_SPECS
1234 #endif
1235
1236 /* If defined, this macro is an additional prefix to try after
1237 `STANDARD_EXEC_PREFIX'. */
1238
1239 #ifndef MD_EXEC_PREFIX
1240 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1241 #endif
1242
1243 #ifndef MD_STARTFILE_PREFIX
1244 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1245 #endif
1246
1247 \f
1248 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1249 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1250 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1251
1252 #ifndef PREFERRED_DEBUGGING_TYPE
1253 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1254 #endif
1255
1256 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1257
1258 /* By default, turn on GDB extensions. */
1259 #define DEFAULT_GDB_EXTENSIONS 1
1260
1261 /* If we are passing smuggling stabs through the MIPS ECOFF object
1262 format, put a comment in front of the .stab<x> operation so
1263 that the MIPS assembler does not choke. The mips-tfile program
1264 will correctly put the stab into the object file. */
1265
1266 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1267 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1268 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1269
1270 /* Local compiler-generated symbols must have a prefix that the assembler
1271 understands. By default, this is $, although some targets (e.g.,
1272 NetBSD-ELF) need to override this. */
1273
1274 #ifndef LOCAL_LABEL_PREFIX
1275 #define LOCAL_LABEL_PREFIX "$"
1276 #endif
1277
1278 /* By default on the mips, external symbols do not have an underscore
1279 prepended, but some targets (e.g., NetBSD) require this. */
1280
1281 #ifndef USER_LABEL_PREFIX
1282 #define USER_LABEL_PREFIX ""
1283 #endif
1284
1285 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1286 since the length can run past this up to a continuation point. */
1287 #undef DBX_CONTIN_LENGTH
1288 #define DBX_CONTIN_LENGTH 1500
1289
1290 /* How to renumber registers for dbx and gdb. */
1291 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1292
1293 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1294 #define DWARF_FRAME_REGNUM(REG) (REG)
1295
1296 /* The DWARF 2 CFA column which tracks the return address. */
1297 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1298
1299 /* The DWARF 2 CFA column which tracks the return address from a
1300 signal handler context. */
1301 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1302
1303 /* Before the prologue, RA lives in r31. */
1304 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1305
1306 /* Describe how we implement __builtin_eh_return. */
1307 #define EH_RETURN_DATA_REGNO(N) \
1308 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1309
1310 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1311
1312 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1313 The default for this in 64-bit mode is 8, which causes problems with
1314 SFmode register saves. */
1315 #define DWARF_CIE_DATA_ALIGNMENT 4
1316
1317 /* Correct the offset of automatic variables and arguments. Note that
1318 the MIPS debug format wants all automatic variables and arguments
1319 to be in terms of the virtual frame pointer (stack pointer before
1320 any adjustment in the function), while the MIPS 3.0 linker wants
1321 the frame pointer to be the stack pointer after the initial
1322 adjustment. */
1323
1324 #define DEBUGGER_AUTO_OFFSET(X) \
1325 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1326 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1327 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1328 \f
1329 /* Target machine storage layout */
1330
1331 #define BITS_BIG_ENDIAN 0
1332 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1333 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1334
1335 /* Define this to set the endianness to use in libgcc2.c, which can
1336 not depend on target_flags. */
1337 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1338 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1339 #else
1340 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1341 #endif
1342
1343 #define MAX_BITS_PER_WORD 64
1344
1345 /* Width of a word, in units (bytes). */
1346 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1347 #define MIN_UNITS_PER_WORD 4
1348
1349 /* For MIPS, width of a floating point register. */
1350 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1351
1352 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1353 the next available register. */
1354 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1355
1356 /* The largest size of value that can be held in floating-point
1357 registers and moved with a single instruction. */
1358 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1359
1360 /* The largest size of value that can be held in floating-point
1361 registers. */
1362 #define UNITS_PER_FPVALUE \
1363 (TARGET_SOFT_FLOAT ? 0 \
1364 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1365 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1366
1367 /* The number of bytes in a double. */
1368 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1369
1370 /* Set the sizes of the core types. */
1371 #define SHORT_TYPE_SIZE 16
1372 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1373 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1374 #define LONG_LONG_TYPE_SIZE 64
1375
1376 #define FLOAT_TYPE_SIZE 32
1377 #define DOUBLE_TYPE_SIZE 64
1378 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1379
1380 /* long double is not a fixed mode, but the idea is that, if we
1381 support long double, we also want a 128-bit integer type. */
1382 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1383
1384 #ifdef IN_LIBGCC2
1385 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1386 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1387 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1388 # else
1389 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1390 # endif
1391 #endif
1392
1393 /* Width in bits of a pointer. */
1394 #ifndef POINTER_SIZE
1395 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1396 #endif
1397
1398 #define POINTERS_EXTEND_UNSIGNED 0
1399
1400 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1401 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1402 || TARGET_NEWABI \
1403 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1404
1405
1406 /* Allocation boundary (in *bits*) for the code of a function. */
1407 #define FUNCTION_BOUNDARY 32
1408
1409 /* Alignment of field after `int : 0' in a structure. */
1410 #define EMPTY_FIELD_BOUNDARY 32
1411
1412 /* Every structure's size must be a multiple of this. */
1413 /* 8 is observed right on a DECstation and on riscos 4.02. */
1414 #define STRUCTURE_SIZE_BOUNDARY 8
1415
1416 /* There is no point aligning anything to a rounder boundary than this. */
1417 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1418
1419 /* All accesses must be aligned. */
1420 #define STRICT_ALIGNMENT 1
1421
1422 /* Define this if you wish to imitate the way many other C compilers
1423 handle alignment of bitfields and the structures that contain
1424 them.
1425
1426 The behavior is that the type written for a bit-field (`int',
1427 `short', or other integer type) imposes an alignment for the
1428 entire structure, as if the structure really did contain an
1429 ordinary field of that type. In addition, the bit-field is placed
1430 within the structure so that it would fit within such a field,
1431 not crossing a boundary for it.
1432
1433 Thus, on most machines, a bit-field whose type is written as `int'
1434 would not cross a four-byte boundary, and would force four-byte
1435 alignment for the whole structure. (The alignment used may not
1436 be four bytes; it is controlled by the other alignment
1437 parameters.)
1438
1439 If the macro is defined, its definition should be a C expression;
1440 a nonzero value for the expression enables this behavior. */
1441
1442 #define PCC_BITFIELD_TYPE_MATTERS 1
1443
1444 /* If defined, a C expression to compute the alignment given to a
1445 constant that is being placed in memory. CONSTANT is the constant
1446 and ALIGN is the alignment that the object would ordinarily have.
1447 The value of this macro is used instead of that alignment to align
1448 the object.
1449
1450 If this macro is not defined, then ALIGN is used.
1451
1452 The typical use of this macro is to increase alignment for string
1453 constants to be word aligned so that `strcpy' calls that copy
1454 constants can be done inline. */
1455
1456 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1457 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1458 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1459
1460 /* If defined, a C expression to compute the alignment for a static
1461 variable. TYPE is the data type, and ALIGN is the alignment that
1462 the object would ordinarily have. The value of this macro is used
1463 instead of that alignment to align the object.
1464
1465 If this macro is not defined, then ALIGN is used.
1466
1467 One use of this macro is to increase alignment of medium-size
1468 data to make it all fit in fewer cache lines. Another is to
1469 cause character arrays to be word-aligned so that `strcpy' calls
1470 that copy constants to character arrays can be done inline. */
1471
1472 #undef DATA_ALIGNMENT
1473 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1474 ((((ALIGN) < BITS_PER_WORD) \
1475 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1476 || TREE_CODE (TYPE) == UNION_TYPE \
1477 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1478
1479
1480 #define PAD_VARARGS_DOWN \
1481 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1482
1483 /* Define if operations between registers always perform the operation
1484 on the full register even if a narrower mode is specified. */
1485 #define WORD_REGISTER_OPERATIONS
1486
1487 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1488 moves. All other references are zero extended. */
1489 #define LOAD_EXTEND_OP(MODE) \
1490 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1491 ? SIGN_EXTEND : ZERO_EXTEND)
1492
1493 /* Define this macro if it is advisable to hold scalars in registers
1494 in a wider mode than that declared by the program. In such cases,
1495 the value is constrained to be within the bounds of the declared
1496 type, but kept valid in the wider mode. The signedness of the
1497 extension may differ from that of the type. */
1498
1499 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1500 if (GET_MODE_CLASS (MODE) == MODE_INT \
1501 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1502 { \
1503 if ((MODE) == SImode) \
1504 (UNSIGNEDP) = 0; \
1505 (MODE) = Pmode; \
1506 }
1507
1508 /* Define if loading short immediate values into registers sign extends. */
1509 #define SHORT_IMMEDIATES_SIGN_EXTEND
1510 \f
1511 /* Standard register usage. */
1512
1513 /* Number of hardware registers. We have:
1514
1515 - 32 integer registers
1516 - 32 floating point registers
1517 - 8 condition code registers
1518 - 2 accumulator registers (hi and lo)
1519 - 32 registers each for coprocessors 0, 2 and 3
1520 - 3 fake registers:
1521 - ARG_POINTER_REGNUM
1522 - FRAME_POINTER_REGNUM
1523 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1524 - 3 dummy entries that were used at various times in the past. */
1525
1526 #define FIRST_PSEUDO_REGISTER 176
1527
1528 /* By default, fix the kernel registers ($26 and $27), the global
1529 pointer ($28) and the stack pointer ($29). This can change
1530 depending on the command-line options.
1531
1532 Regarding coprocessor registers: without evidence to the contrary,
1533 it's best to assume that each coprocessor register has a unique
1534 use. This can be overridden, in, e.g., override_options() or
1535 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1536 for a particular target. */
1537
1538 #define FIXED_REGISTERS \
1539 { \
1540 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1544 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1545 /* COP0 registers */ \
1546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1548 /* COP2 registers */ \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 /* COP3 registers */ \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1554 }
1555
1556
1557 /* Set up this array for o32 by default.
1558
1559 Note that we don't mark $31 as a call-clobbered register. The idea is
1560 that it's really the call instructions themselves which clobber $31.
1561 We don't care what the called function does with it afterwards.
1562
1563 This approach makes it easier to implement sibcalls. Unlike normal
1564 calls, sibcalls don't clobber $31, so the register reaches the
1565 called function in tact. EPILOGUE_USES says that $31 is useful
1566 to the called function. */
1567
1568 #define CALL_USED_REGISTERS \
1569 { \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 /* COP0 registers */ \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 /* COP2 registers */ \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1581 /* COP3 registers */ \
1582 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1584 }
1585
1586
1587 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1588
1589 #define CALL_REALLY_USED_REGISTERS \
1590 { /* General registers. */ \
1591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1592 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1593 /* Floating-point registers. */ \
1594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1595 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 /* Others. */ \
1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1598 /* COP0 registers */ \
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1601 /* COP2 registers */ \
1602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1603 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1604 /* COP3 registers */ \
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1607 }
1608
1609 /* Internal macros to classify a register number as to whether it's a
1610 general purpose register, a floating point register, a
1611 multiply/divide register, or a status register. */
1612
1613 #define GP_REG_FIRST 0
1614 #define GP_REG_LAST 31
1615 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1616 #define GP_DBX_FIRST 0
1617
1618 #define FP_REG_FIRST 32
1619 #define FP_REG_LAST 63
1620 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1621 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1622
1623 #define MD_REG_FIRST 64
1624 #define MD_REG_LAST 65
1625 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1626 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1627
1628 #define ST_REG_FIRST 67
1629 #define ST_REG_LAST 74
1630 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1631
1632
1633 /* FIXME: renumber. */
1634 #define COP0_REG_FIRST 80
1635 #define COP0_REG_LAST 111
1636 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1637
1638 #define COP2_REG_FIRST 112
1639 #define COP2_REG_LAST 143
1640 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1641
1642 #define COP3_REG_FIRST 144
1643 #define COP3_REG_LAST 175
1644 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1645 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1646 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1647
1648 #define AT_REGNUM (GP_REG_FIRST + 1)
1649 #define HI_REGNUM (MD_REG_FIRST + 0)
1650 #define LO_REGNUM (MD_REG_FIRST + 1)
1651
1652 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1653 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1654 should be used instead. */
1655 #define FPSW_REGNUM ST_REG_FIRST
1656
1657 #define GP_REG_P(REGNO) \
1658 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1659 #define M16_REG_P(REGNO) \
1660 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1661 #define FP_REG_P(REGNO) \
1662 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1663 #define MD_REG_P(REGNO) \
1664 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1665 #define ST_REG_P(REGNO) \
1666 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1667 #define COP0_REG_P(REGNO) \
1668 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1669 #define COP2_REG_P(REGNO) \
1670 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1671 #define COP3_REG_P(REGNO) \
1672 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1673 #define ALL_COP_REG_P(REGNO) \
1674 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1675
1676 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1677
1678 /* Return coprocessor number from register number. */
1679
1680 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1681 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1682 : COP3_REG_P (REGNO) ? '3' : '?')
1683
1684
1685 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1686
1687 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1688 array built in override_options. Because machmodes.h is not yet
1689 included before this file is processed, the MODE bound can't be
1690 expressed here. */
1691
1692 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1693
1694 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1695 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1696
1697 /* Value is 1 if it is a good idea to tie two pseudo registers
1698 when one has mode MODE1 and one has mode MODE2.
1699 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1700 for any hard reg, then this must be 0 for correct output. */
1701 #define MODES_TIEABLE_P(MODE1, MODE2) \
1702 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1703 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1704 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1705 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1706
1707 /* Register to use for pushing function arguments. */
1708 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1709
1710 /* These two registers don't really exist: they get eliminated to either
1711 the stack or hard frame pointer. */
1712 #define ARG_POINTER_REGNUM 77
1713 #define FRAME_POINTER_REGNUM 78
1714
1715 /* $30 is not available on the mips16, so we use $17 as the frame
1716 pointer. */
1717 #define HARD_FRAME_POINTER_REGNUM \
1718 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1719
1720 /* Value should be nonzero if functions must have frame pointers.
1721 Zero means the frame pointer need not be set up (and parms
1722 may be accessed via the stack pointer) in functions that seem suitable.
1723 This is computed in `reload', in reload1.c. */
1724 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1725
1726 /* Register in which static-chain is passed to a function. */
1727 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1728
1729 /* Registers used as temporaries in prologue/epilogue code. If we're
1730 generating mips16 code, these registers must come from the core set
1731 of 8. The prologue register mustn't conflict with any incoming
1732 arguments, the static chain pointer, or the frame pointer. The
1733 epilogue temporary mustn't conflict with the return registers, the
1734 frame pointer, the EH stack adjustment, or the EH data registers. */
1735
1736 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1737 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1738
1739 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1740 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1741
1742 /* Define this macro if it is as good or better to call a constant
1743 function address than to call an address kept in a register. */
1744 #define NO_FUNCTION_CSE 1
1745
1746 /* The ABI-defined global pointer. Sometimes we use a different
1747 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1748 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1749
1750 /* We normally use $28 as the global pointer. However, when generating
1751 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1752 register instead. They can then avoid saving and restoring $28
1753 and perhaps avoid using a frame at all.
1754
1755 When a leaf function uses something other than $28, mips_expand_prologue
1756 will modify pic_offset_table_rtx in place. Take the register number
1757 from there after reload. */
1758 #define PIC_OFFSET_TABLE_REGNUM \
1759 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1760
1761 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1762 \f
1763 /* Define the classes of registers for register constraints in the
1764 machine description. Also define ranges of constants.
1765
1766 One of the classes must always be named ALL_REGS and include all hard regs.
1767 If there is more than one class, another class must be named NO_REGS
1768 and contain no registers.
1769
1770 The name GENERAL_REGS must be the name of a class (or an alias for
1771 another name such as ALL_REGS). This is the class of registers
1772 that is allowed by "g" or "r" in a register constraint.
1773 Also, registers outside this class are allocated only when
1774 instructions express preferences for them.
1775
1776 The classes must be numbered in nondecreasing order; that is,
1777 a larger-numbered class must never be contained completely
1778 in a smaller-numbered class.
1779
1780 For any two classes, it is very desirable that there be another
1781 class that represents their union. */
1782
1783 enum reg_class
1784 {
1785 NO_REGS, /* no registers in set */
1786 M16_NA_REGS, /* mips16 regs not used to pass args */
1787 M16_REGS, /* mips16 directly accessible registers */
1788 T_REG, /* mips16 T register ($24) */
1789 M16_T_REGS, /* mips16 registers plus T register */
1790 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1791 LEA_REGS, /* Every GPR except $25 */
1792 GR_REGS, /* integer registers */
1793 FP_REGS, /* floating point registers */
1794 HI_REG, /* hi register */
1795 LO_REG, /* lo register */
1796 MD_REGS, /* multiply/divide registers (hi/lo) */
1797 COP0_REGS, /* generic coprocessor classes */
1798 COP2_REGS,
1799 COP3_REGS,
1800 HI_AND_GR_REGS, /* union classes */
1801 LO_AND_GR_REGS,
1802 HI_AND_FP_REGS,
1803 COP0_AND_GR_REGS,
1804 COP2_AND_GR_REGS,
1805 COP3_AND_GR_REGS,
1806 ALL_COP_REGS,
1807 ALL_COP_AND_GR_REGS,
1808 ST_REGS, /* status registers (fp status) */
1809 ALL_REGS, /* all registers */
1810 LIM_REG_CLASSES /* max value + 1 */
1811 };
1812
1813 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1814
1815 #define GENERAL_REGS GR_REGS
1816
1817 /* An initializer containing the names of the register classes as C
1818 string constants. These names are used in writing some of the
1819 debugging dumps. */
1820
1821 #define REG_CLASS_NAMES \
1822 { \
1823 "NO_REGS", \
1824 "M16_NA_REGS", \
1825 "M16_REGS", \
1826 "T_REG", \
1827 "M16_T_REGS", \
1828 "PIC_FN_ADDR_REG", \
1829 "LEA_REGS", \
1830 "GR_REGS", \
1831 "FP_REGS", \
1832 "HI_REG", \
1833 "LO_REG", \
1834 "MD_REGS", \
1835 /* coprocessor registers */ \
1836 "COP0_REGS", \
1837 "COP2_REGS", \
1838 "COP3_REGS", \
1839 "HI_AND_GR_REGS", \
1840 "LO_AND_GR_REGS", \
1841 "HI_AND_FP_REGS", \
1842 "COP0_AND_GR_REGS", \
1843 "COP2_AND_GR_REGS", \
1844 "COP3_AND_GR_REGS", \
1845 "ALL_COP_REGS", \
1846 "ALL_COP_AND_GR_REGS", \
1847 "ST_REGS", \
1848 "ALL_REGS" \
1849 }
1850
1851 /* An initializer containing the contents of the register classes,
1852 as integers which are bit masks. The Nth integer specifies the
1853 contents of class N. The way the integer MASK is interpreted is
1854 that register R is in the class if `MASK & (1 << R)' is 1.
1855
1856 When the machine has more than 32 registers, an integer does not
1857 suffice. Then the integers are replaced by sub-initializers,
1858 braced groupings containing several integers. Each
1859 sub-initializer must be suitable as an initializer for the type
1860 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1861
1862 #define REG_CLASS_CONTENTS \
1863 { \
1864 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1865 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1866 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1867 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1868 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1869 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1870 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1871 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1872 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1873 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1874 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1875 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1876 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1877 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1878 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1879 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1880 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1881 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1882 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1883 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1884 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1885 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1886 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1887 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1888 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1889 }
1890
1891
1892 /* A C expression whose value is a register class containing hard
1893 register REGNO. In general there is more that one such class;
1894 choose a class which is "minimal", meaning that no smaller class
1895 also contains the register. */
1896
1897 extern const enum reg_class mips_regno_to_class[];
1898
1899 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1900
1901 /* A macro whose definition is the name of the class to which a
1902 valid base register must belong. A base register is one used in
1903 an address which is the register value plus a displacement. */
1904
1905 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1906
1907 /* A macro whose definition is the name of the class to which a
1908 valid index register must belong. An index register is one used
1909 in an address where its value is either multiplied by a scale
1910 factor or added to another register (as well as added to a
1911 displacement). */
1912
1913 #define INDEX_REG_CLASS NO_REGS
1914
1915 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1916 registers explicitly used in the rtl to be used as spill registers
1917 but prevents the compiler from extending the lifetime of these
1918 registers. */
1919
1920 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1921
1922 /* This macro is used later on in the file. */
1923 #define GR_REG_CLASS_P(CLASS) \
1924 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1925 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1926 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1927
1928 /* This macro is also used later on in the file. */
1929 #define COP_REG_CLASS_P(CLASS) \
1930 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1931
1932 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1933 is the default value (allocate the registers in numeric order). We
1934 define it just so that we can override it for the mips16 target in
1935 ORDER_REGS_FOR_LOCAL_ALLOC. */
1936
1937 #define REG_ALLOC_ORDER \
1938 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1939 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1940 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1941 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1942 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1943 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1944 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1945 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1946 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1947 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1948 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1949 }
1950
1951 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1952 to be rearranged based on a particular function. On the mips16, we
1953 want to allocate $24 (T_REG) before other registers for
1954 instructions for which it is possible. */
1955
1956 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1957
1958 /* REGISTER AND CONSTANT CLASSES */
1959
1960 /* Get reg_class from a letter such as appears in the machine
1961 description.
1962
1963 DEFINED REGISTER CLASSES:
1964
1965 'd' General (aka integer) registers
1966 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1967 'y' General registers (in both mips16 and non mips16 mode)
1968 'e' Effective address registers (general registers except $25)
1969 't' mips16 temporary register ($24)
1970 'f' Floating point registers
1971 'h' Hi register
1972 'l' Lo register
1973 'x' Multiply/divide registers
1974 'z' FP Status register
1975 'B' Cop0 register
1976 'C' Cop2 register
1977 'D' Cop3 register
1978 'b' All registers */
1979
1980 extern enum reg_class mips_char_to_class[256];
1981
1982 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1983
1984 /* True if VALUE is a signed 16-bit number. */
1985
1986 #define SMALL_OPERAND(VALUE) \
1987 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1988
1989 /* True if VALUE is an unsigned 16-bit number. */
1990
1991 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1992 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1993
1994 /* True if VALUE can be loaded into a register using LUI. */
1995
1996 #define LUI_OPERAND(VALUE) \
1997 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1998 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1999
2000 /* Return a value X with the low 16 bits clear, and such that
2001 VALUE - X is a signed 16-bit value. */
2002
2003 #define CONST_HIGH_PART(VALUE) \
2004 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2005
2006 #define CONST_LOW_PART(VALUE) \
2007 ((VALUE) - CONST_HIGH_PART (VALUE))
2008
2009 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2010 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2011 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2012
2013 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2014 string can be used to stand for particular ranges of immediate
2015 operands. This macro defines what the ranges are. C is the
2016 letter, and VALUE is a constant value. Return 1 if VALUE is
2017 in the range specified by C. */
2018
2019 /* For MIPS:
2020
2021 `I' is used for the range of constants an arithmetic insn can
2022 actually contain (16 bits signed integers).
2023
2024 `J' is used for the range which is just zero (ie, $r0).
2025
2026 `K' is used for the range of constants a logical insn can actually
2027 contain (16 bit zero-extended integers).
2028
2029 `L' is used for the range of constants that be loaded with lui
2030 (ie, the bottom 16 bits are zero).
2031
2032 `M' is used for the range of constants that take two words to load
2033 (ie, not matched by `I', `K', and `L').
2034
2035 `N' is used for negative 16 bit constants other than -65536.
2036
2037 `O' is a 15 bit signed integer.
2038
2039 `P' is used for positive 16 bit constants. */
2040
2041 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2042 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2043 : (C) == 'J' ? ((VALUE) == 0) \
2044 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2045 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2046 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2047 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2048 && !LUI_OPERAND (VALUE)) \
2049 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2050 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2051 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2052 : 0)
2053
2054 /* Similar, but for floating constants, and defining letters G and H.
2055 Here VALUE is the CONST_DOUBLE rtx itself. */
2056
2057 /* For Mips
2058
2059 'G' : Floating point 0 */
2060
2061 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2062 ((C) == 'G' \
2063 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2064
2065 /* Letters in the range `Q' through `U' may be defined in a
2066 machine-dependent fashion to stand for arbitrary operand types.
2067 The machine description macro `EXTRA_CONSTRAINT' is passed the
2068 operand as its first argument and the constraint letter as its
2069 second operand.
2070
2071 `Q' is for signed 16-bit constants.
2072 `R' is for single-instruction memory references. Note that this
2073 constraint has often been used in linux and glibc code.
2074 `S' is for legitimate constant call addresses.
2075 `T' is for constant move_operands that cannot be safely loaded into $25.
2076 `U' is for constant move_operands that can be safely loaded into $25.
2077 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2078 This is true for all non-mips16 references (although it can sometimes
2079 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2080 stack and constant-pool references. */
2081
2082 #define EXTRA_CONSTRAINT(OP,CODE) \
2083 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2084 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2085 && mips_fetch_insns (OP) == 1) \
2086 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2087 && call_insn_operand (OP, VOIDmode)) \
2088 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2089 && move_operand (OP, VOIDmode) \
2090 && mips_dangerous_for_la25_p (OP)) \
2091 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2092 && move_operand (OP, VOIDmode) \
2093 && !mips_dangerous_for_la25_p (OP)) \
2094 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2095 && memory_operand (OP, VOIDmode) \
2096 && (!TARGET_MIPS16 \
2097 || (!stack_operand (OP, VOIDmode) \
2098 && !CONSTANT_P (XEXP (OP, 0))))) \
2099 : FALSE)
2100
2101 /* Say which of the above are memory constraints. */
2102 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2103
2104 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2105 mips_preferred_reload_class (X, CLASS)
2106
2107 /* Certain machines have the property that some registers cannot be
2108 copied to some other registers without using memory. Define this
2109 macro on those machines to be a C expression that is nonzero if
2110 objects of mode MODE in registers of CLASS1 can only be copied to
2111 registers of class CLASS2 by storing a register of CLASS1 into
2112 memory and loading that memory location into a register of CLASS2.
2113
2114 Do not define this macro if its value would always be zero. */
2115 #if 0
2116 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2117 ((!TARGET_DEBUG_H_MODE \
2118 && GET_MODE_CLASS (MODE) == MODE_INT \
2119 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2120 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2121 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2122 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2123 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2124 #endif
2125 /* The HI and LO registers can only be reloaded via the general
2126 registers. Condition code registers can only be loaded to the
2127 general registers, and from the floating point registers. */
2128
2129 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2130 mips_secondary_reload_class (CLASS, MODE, X, 1)
2131 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2132 mips_secondary_reload_class (CLASS, MODE, X, 0)
2133
2134 /* Return the maximum number of consecutive registers
2135 needed to represent mode MODE in a register of class CLASS. */
2136
2137 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2138
2139 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2140 mips_cannot_change_mode_class (FROM, TO, CLASS)
2141 \f
2142 /* Stack layout; function entry, exit and calling. */
2143
2144 #define STACK_GROWS_DOWNWARD
2145
2146 /* The offset of the first local variable from the beginning of the frame.
2147 See compute_frame_size for details about the frame layout. */
2148 #define STARTING_FRAME_OFFSET \
2149 (current_function_outgoing_args_size \
2150 + (TARGET_ABICALLS && !TARGET_NEWABI \
2151 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2152
2153 #define RETURN_ADDR_RTX mips_return_addr
2154
2155 /* Since the mips16 ISA mode is encoded in the least-significant bit
2156 of the address, mask it off return addresses for purposes of
2157 finding exception handling regions. */
2158
2159 #define MASK_RETURN_ADDR GEN_INT (-2)
2160
2161
2162 /* Similarly, don't use the least-significant bit to tell pointers to
2163 code from vtable index. */
2164
2165 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2166
2167 /* The eliminations to $17 are only used for mips16 code. See the
2168 definition of HARD_FRAME_POINTER_REGNUM. */
2169
2170 #define ELIMINABLE_REGS \
2171 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2172 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2173 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2174 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2175 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2176 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2177
2178 /* We can always eliminate to the hard frame pointer. We can eliminate
2179 to the stack pointer unless a frame pointer is needed.
2180
2181 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2182 reload may be unable to compute the address of a local variable,
2183 since there is no way to add a large constant to the stack pointer
2184 without using a temporary register. */
2185 #define CAN_ELIMINATE(FROM, TO) \
2186 ((TO) == HARD_FRAME_POINTER_REGNUM \
2187 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2188 && (!TARGET_MIPS16 \
2189 || compute_frame_size (get_frame_size ()) < 32768)))
2190
2191 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2192 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2193
2194 /* Allocate stack space for arguments at the beginning of each function. */
2195 #define ACCUMULATE_OUTGOING_ARGS 1
2196
2197 /* The argument pointer always points to the first argument. */
2198 #define FIRST_PARM_OFFSET(FNDECL) 0
2199
2200 /* o32 and o64 reserve stack space for all argument registers. */
2201 #define REG_PARM_STACK_SPACE(FNDECL) \
2202 (TARGET_OLDABI \
2203 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2204 : 0)
2205
2206 /* Define this if it is the responsibility of the caller to
2207 allocate the area reserved for arguments passed in registers.
2208 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2209 of this macro is to determine whether the space is included in
2210 `current_function_outgoing_args_size'. */
2211 #define OUTGOING_REG_PARM_STACK_SPACE
2212
2213 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2214 \f
2215 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2216
2217 /* Symbolic macros for the registers used to return integer and floating
2218 point values. */
2219
2220 #define GP_RETURN (GP_REG_FIRST + 2)
2221 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2222
2223 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2224
2225 /* Symbolic macros for the first/last argument registers. */
2226
2227 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2228 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2229 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2230 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2231
2232 #define LIBCALL_VALUE(MODE) \
2233 mips_function_value (NULL_TREE, NULL, (MODE))
2234
2235 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2236 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2237
2238 /* 1 if N is a possible register number for a function value.
2239 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2240 Currently, R2 and F0 are only implemented here (C has no complex type) */
2241
2242 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2243 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2244 && (N) == FP_RETURN + 2))
2245
2246 /* 1 if N is a possible register number for function argument passing.
2247 We have no FP argument registers when soft-float. When FP registers
2248 are 32 bits, we can't directly reference the odd numbered ones. */
2249
2250 #define FUNCTION_ARG_REGNO_P(N) \
2251 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2252 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2253 && !fixed_regs[N])
2254 \f
2255 /* This structure has to cope with two different argument allocation
2256 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2257 first N words go in registers and the rest go on the stack. If I < N,
2258 the Ith word might go in Ith integer argument register or the
2259 Ith floating-point one. For these ABIs, we only need to remember
2260 the number of words passed so far.
2261
2262 The EABI instead allocates the integer and floating-point arguments
2263 separately. The first N words of FP arguments go in FP registers,
2264 the rest go on the stack. Likewise, the first N words of the other
2265 arguments go in integer registers, and the rest go on the stack. We
2266 need to maintain three counts: the number of integer registers used,
2267 the number of floating-point registers used, and the number of words
2268 passed on the stack.
2269
2270 We could keep separate information for the two ABIs (a word count for
2271 the standard ABIs, and three separate counts for the EABI). But it
2272 seems simpler to view the standard ABIs as forms of EABI that do not
2273 allocate floating-point registers.
2274
2275 So for the standard ABIs, the first N words are allocated to integer
2276 registers, and function_arg decides on an argument-by-argument basis
2277 whether that argument should really go in an integer register, or in
2278 a floating-point one. */
2279
2280 typedef struct mips_args {
2281 /* Always true for varargs functions. Otherwise true if at least
2282 one argument has been passed in an integer register. */
2283 int gp_reg_found;
2284
2285 /* The number of arguments seen so far. */
2286 unsigned int arg_number;
2287
2288 /* For EABI, the number of integer registers used so far. For other
2289 ABIs, the number of words passed in registers (whether integer
2290 or floating-point). */
2291 unsigned int num_gprs;
2292
2293 /* For EABI, the number of floating-point registers used so far. */
2294 unsigned int num_fprs;
2295
2296 /* The number of words passed on the stack. */
2297 unsigned int stack_words;
2298
2299 /* On the mips16, we need to keep track of which floating point
2300 arguments were passed in general registers, but would have been
2301 passed in the FP regs if this were a 32 bit function, so that we
2302 can move them to the FP regs if we wind up calling a 32 bit
2303 function. We record this information in fp_code, encoded in base
2304 four. A zero digit means no floating point argument, a one digit
2305 means an SFmode argument, and a two digit means a DFmode argument,
2306 and a three digit is not used. The low order digit is the first
2307 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2308 an SFmode argument. ??? A more sophisticated approach will be
2309 needed if MIPS_ABI != ABI_32. */
2310 int fp_code;
2311
2312 /* True if the function has a prototype. */
2313 int prototype;
2314 } CUMULATIVE_ARGS;
2315
2316 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2317 for a call to a function whose data type is FNTYPE.
2318 For a library call, FNTYPE is 0. */
2319
2320 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2321 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2322
2323 /* Update the data in CUM to advance over an argument
2324 of mode MODE and data type TYPE.
2325 (TYPE is null for libcalls where that information may not be available.) */
2326
2327 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2328 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2329
2330 /* Determine where to put an argument to a function.
2331 Value is zero to push the argument on the stack,
2332 or a hard register in which to store the argument.
2333
2334 MODE is the argument's machine mode.
2335 TYPE is the data type of the argument (as a tree).
2336 This is null for libcalls where that information may
2337 not be available.
2338 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2339 the preceding args and about the function being called.
2340 NAMED is nonzero if this argument is a named parameter
2341 (otherwise it is an extra parameter matching an ellipsis). */
2342
2343 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2344 function_arg( &CUM, MODE, TYPE, NAMED)
2345
2346 /* For an arg passed partly in registers and partly in memory,
2347 this is the number of registers used.
2348 For args passed entirely in registers or entirely in memory, zero. */
2349
2350 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2351 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2352
2353 /* If defined, a C expression that gives the alignment boundary, in
2354 bits, of an argument with the specified mode and type. If it is
2355 not defined, `PARM_BOUNDARY' is used for all arguments. */
2356
2357 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2358 (((TYPE) != 0) \
2359 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2360 ? PARM_BOUNDARY \
2361 : TYPE_ALIGN(TYPE)) \
2362 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2363 ? PARM_BOUNDARY \
2364 : GET_MODE_ALIGNMENT(MODE)))
2365
2366 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2367 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2368
2369 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2370 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2371
2372 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2373 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2374
2375 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2376 (mips_abi == ABI_EABI && (NAMED) \
2377 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2378
2379 /* Modified version of the macro in expr.h. Only return true if
2380 the type has a variable size or if the front end requires it
2381 to be passed by reference. */
2382 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2383 ((TYPE) != 0 \
2384 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2385 || TREE_ADDRESSABLE (TYPE)))
2386
2387 /* True if using EABI and varargs can be passed in floating-point
2388 registers. Under these conditions, we need a more complex form
2389 of va_list, which tracks GPR, FPR and stack arguments separately. */
2390 #define EABI_FLOAT_VARARGS_P \
2391 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2392
2393 \f
2394 /* Say that the epilogue uses the return address register. Note that
2395 in the case of sibcalls, the values "used by the epilogue" are
2396 considered live at the start of the called function. */
2397 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2398
2399 /* Treat LOC as a byte offset from the stack pointer and round it up
2400 to the next fully-aligned offset. */
2401 #define MIPS_STACK_ALIGN(LOC) \
2402 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2403 ? ((LOC) + 7) & ~7 \
2404 : ((LOC) + 15) & ~15)
2405
2406 \f
2407 /* Implement `va_start' for varargs and stdarg. */
2408 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2409 mips_va_start (valist, nextarg)
2410
2411 /* Implement `va_arg'. */
2412 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2413 mips_va_arg (valist, type)
2414 \f
2415 /* Output assembler code to FILE to increment profiler label # LABELNO
2416 for profiling a function entry. */
2417
2418 #define FUNCTION_PROFILER(FILE, LABELNO) \
2419 { \
2420 if (TARGET_MIPS16) \
2421 sorry ("mips16 function profiling"); \
2422 fprintf (FILE, "\t.set\tnoat\n"); \
2423 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2424 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2425 if (!TARGET_NEWABI) \
2426 { \
2427 fprintf (FILE, \
2428 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2429 TARGET_64BIT ? "dsubu" : "subu", \
2430 reg_names[STACK_POINTER_REGNUM], \
2431 reg_names[STACK_POINTER_REGNUM], \
2432 Pmode == DImode ? 16 : 8); \
2433 } \
2434 fprintf (FILE, "\tjal\t_mcount\n"); \
2435 fprintf (FILE, "\t.set\tat\n"); \
2436 }
2437
2438 /* Define this macro if the code for function profiling should come
2439 before the function prologue. Normally, the profiling code comes
2440 after. */
2441
2442 /* #define PROFILE_BEFORE_PROLOGUE */
2443
2444 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2445 the stack pointer does not matter. The value is tested only in
2446 functions that have frame pointers.
2447 No definition is equivalent to always zero. */
2448
2449 #define EXIT_IGNORE_STACK 1
2450
2451 \f
2452 /* A C statement to output, on the stream FILE, assembler code for a
2453 block of data that contains the constant parts of a trampoline.
2454 This code should not include a label--the label is taken care of
2455 automatically. */
2456
2457 #define TRAMPOLINE_TEMPLATE(STREAM) \
2458 { \
2459 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2460 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2461 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2462 if (ptr_mode == DImode) \
2463 { \
2464 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2465 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2466 } \
2467 else \
2468 { \
2469 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2470 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2471 } \
2472 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2473 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2474 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2475 if (ptr_mode == DImode) \
2476 { \
2477 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2478 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2479 } \
2480 else \
2481 { \
2482 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2483 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2484 } \
2485 }
2486
2487 /* A C expression for the size in bytes of the trampoline, as an
2488 integer. */
2489
2490 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2491
2492 /* Alignment required for trampolines, in bits. */
2493
2494 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2495
2496 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2497 program and data caches. */
2498
2499 #ifndef CACHE_FLUSH_FUNC
2500 #define CACHE_FLUSH_FUNC "_flush_cache"
2501 #endif
2502
2503 /* A C statement to initialize the variable parts of a trampoline.
2504 ADDR is an RTX for the address of the trampoline; FNADDR is an
2505 RTX for the address of the nested function; STATIC_CHAIN is an
2506 RTX for the static chain value that should be passed to the
2507 function when it is called. */
2508
2509 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2510 { \
2511 rtx func_addr, chain_addr; \
2512 \
2513 func_addr = plus_constant (ADDR, 32); \
2514 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2515 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2516 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2517 \
2518 /* Flush both caches. We need to flush the data cache in case \
2519 the system has a write-back cache. */ \
2520 /* ??? Should check the return value for errors. */ \
2521 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2522 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2523 0, VOIDmode, 3, ADDR, Pmode, \
2524 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2525 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2526 }
2527 \f
2528 /* Addressing modes, and classification of registers for them. */
2529
2530 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2531 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2532 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2533
2534 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2535 and check its validity for a certain class.
2536 We have two alternate definitions for each of them.
2537 The usual definition accepts all pseudo regs; the other rejects them all.
2538 The symbol REG_OK_STRICT causes the latter definition to be used.
2539
2540 Most source files want to accept pseudo regs in the hope that
2541 they will get allocated to the class that the insn wants them to be in.
2542 Some source files that are used after register allocation
2543 need to be strict. */
2544
2545 #ifndef REG_OK_STRICT
2546 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2547 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2548 #else
2549 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2550 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2551 #endif
2552
2553 #define REG_OK_FOR_INDEX_P(X) 0
2554
2555 \f
2556 /* Maximum number of registers that can appear in a valid memory address. */
2557
2558 #define MAX_REGS_PER_ADDRESS 1
2559
2560 #ifdef REG_OK_STRICT
2561 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2562 { \
2563 if (mips_legitimate_address_p (MODE, X, 1)) \
2564 goto ADDR; \
2565 }
2566 #else
2567 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2568 { \
2569 if (mips_legitimate_address_p (MODE, X, 0)) \
2570 goto ADDR; \
2571 }
2572 #endif
2573
2574 /* Check for constness inline but use mips_legitimate_address_p
2575 to check whether a constant really is an address. */
2576
2577 #define CONSTANT_ADDRESS_P(X) \
2578 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2579
2580 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2581
2582 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2583 do { \
2584 if (mips_legitimize_address (&(X), MODE)) \
2585 goto WIN; \
2586 } while (0)
2587
2588
2589 /* A C statement or compound statement with a conditional `goto
2590 LABEL;' executed if memory address X (an RTX) can have different
2591 meanings depending on the machine mode of the memory reference it
2592 is used for.
2593
2594 Autoincrement and autodecrement addresses typically have
2595 mode-dependent effects because the amount of the increment or
2596 decrement is the size of the operand being addressed. Some
2597 machines have other mode-dependent addresses. Many RISC machines
2598 have no mode-dependent addresses.
2599
2600 You may assume that ADDR is a valid address for the machine. */
2601
2602 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2603
2604 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2605 'the start of the function that this code is output in'. */
2606
2607 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2608 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2609 asm_fprintf ((FILE), "%U%s", \
2610 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2611 else \
2612 asm_fprintf ((FILE), "%U%s", (NAME))
2613 \f
2614 /* Specify the machine mode that this machine uses
2615 for the index in the tablejump instruction.
2616 ??? Using HImode in mips16 mode can cause overflow. */
2617 #define CASE_VECTOR_MODE \
2618 (TARGET_MIPS16 ? HImode : ptr_mode)
2619
2620 /* Define as C expression which evaluates to nonzero if the tablejump
2621 instruction expects the table to contain offsets from the address of the
2622 table.
2623 Do not define this if the table should contain absolute addresses. */
2624 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2625
2626 /* Define this as 1 if `char' should by default be signed; else as 0. */
2627 #ifndef DEFAULT_SIGNED_CHAR
2628 #define DEFAULT_SIGNED_CHAR 1
2629 #endif
2630
2631 /* Max number of bytes we can move from memory to memory
2632 in one reasonably fast instruction. */
2633 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2634 #define MAX_MOVE_MAX 8
2635
2636 /* Define this macro as a C expression which is nonzero if
2637 accessing less than a word of memory (i.e. a `char' or a
2638 `short') is no faster than accessing a word of memory, i.e., if
2639 such access require more than one instruction or if there is no
2640 difference in cost between byte and (aligned) word loads.
2641
2642 On RISC machines, it tends to generate better code to define
2643 this as 1, since it avoids making a QI or HI mode register. */
2644 #define SLOW_BYTE_ACCESS 1
2645
2646 /* Define this to be nonzero if shift instructions ignore all but the low-order
2647 few bits. */
2648 #define SHIFT_COUNT_TRUNCATED 1
2649
2650 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2651 is done just by pretending it is already truncated. */
2652 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2653 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2654
2655
2656 /* Specify the machine mode that pointers have.
2657 After generation of rtl, the compiler makes no further distinction
2658 between pointers and any other objects of this machine mode. */
2659
2660 #ifndef Pmode
2661 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2662 #endif
2663
2664 /* Give call MEMs SImode since it is the "most permissive" mode
2665 for both 32-bit and 64-bit targets. */
2666
2667 #define FUNCTION_MODE SImode
2668
2669 \f
2670 /* The cost of loading values from the constant pool. It should be
2671 larger than the cost of any constant we want to synthesize in-line. */
2672
2673 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2674
2675 /* A C expression for the cost of moving data from a register in
2676 class FROM to one in class TO. The classes are expressed using
2677 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2678 the default; other values are interpreted relative to that.
2679
2680 It is not required that the cost always equal 2 when FROM is the
2681 same as TO; on some machines it is expensive to move between
2682 registers if they are not general registers.
2683
2684 If reload sees an insn consisting of a single `set' between two
2685 hard registers, and if `REGISTER_MOVE_COST' applied to their
2686 classes returns a value of 2, reload does not check to ensure
2687 that the constraints of the insn are met. Setting a cost of
2688 other than 2 will allow reload to verify that the constraints are
2689 met. You should do this if the `movM' pattern's constraints do
2690 not allow such copying. */
2691
2692 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2693 mips_register_move_cost (MODE, FROM, TO)
2694
2695 /* ??? Fix this to be right for the R8000. */
2696 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2697 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2698 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2699
2700 /* Define if copies to/from condition code registers should be avoided.
2701
2702 This is needed for the MIPS because reload_outcc is not complete;
2703 it needs to handle cases where the source is a general or another
2704 condition code register. */
2705 #define AVOID_CCMODE_COPIES
2706
2707 /* A C expression for the cost of a branch instruction. A value of
2708 1 is the default; other values are interpreted relative to that. */
2709
2710 /* ??? Fix this to be right for the R8000. */
2711 #define BRANCH_COST \
2712 ((! TARGET_MIPS16 \
2713 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2714 ? 2 : 1)
2715
2716 /* If defined, modifies the length assigned to instruction INSN as a
2717 function of the context in which it is used. LENGTH is an lvalue
2718 that contains the initially computed length of the insn and should
2719 be updated with the correct length of the insn. */
2720 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2721 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2722
2723 \f
2724 /* Optionally define this if you have added predicates to
2725 `MACHINE.c'. This macro is called within an initializer of an
2726 array of structures. The first field in the structure is the
2727 name of a predicate and the second field is an array of rtl
2728 codes. For each predicate, list all rtl codes that can be in
2729 expressions matched by the predicate. The list should have a
2730 trailing comma. Here is an example of two entries in the list
2731 for a typical RISC machine:
2732
2733 #define PREDICATE_CODES \
2734 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2735 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2736
2737 Defining this macro does not affect the generated code (however,
2738 incorrect definitions that omit an rtl code that may be matched
2739 by the predicate can cause the compiler to malfunction).
2740 Instead, it allows the table built by `genrecog' to be more
2741 compact and efficient, thus speeding up the compiler. The most
2742 important predicates to include in the list specified by this
2743 macro are thoses used in the most insn patterns. */
2744
2745 #define PREDICATE_CODES \
2746 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2747 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2748 {"general_symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2749 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2750 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2751 {"const_arith_operand", { CONST_INT }}, \
2752 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2753 UNSPEC_VOLATILE }}, \
2754 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2755 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2756 {"small_int", { CONST_INT }}, \
2757 {"const_float_1_operand", { CONST_DOUBLE }}, \
2758 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2759 {"equality_op", { EQ, NE }}, \
2760 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2761 LTU, LEU }}, \
2762 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2763 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2764 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2765 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2766 SYMBOL_REF, LABEL_REF, SUBREG, \
2767 REG, MEM}}, \
2768 {"stack_operand", { MEM }}, \
2769 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2770 CONST_DOUBLE, CONST }}, \
2771 {"fcc_register_operand", { REG, SUBREG }}, \
2772 {"hilo_operand", { REG }}, \
2773 {"macc_msac_operand", { PLUS, MINUS }}, \
2774 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2775
2776 /* A list of predicates that do special things with modes, and so
2777 should not elicit warnings for VOIDmode match_operand. */
2778
2779 #define SPECIAL_MODE_PREDICATES \
2780 "pc_or_label_operand",
2781 \f
2782 /* Control the assembler format that we output. */
2783
2784 /* Output to assembler file text saying following lines
2785 may contain character constants, extra white space, comments, etc. */
2786
2787 #ifndef ASM_APP_ON
2788 #define ASM_APP_ON " #APP\n"
2789 #endif
2790
2791 /* Output to assembler file text saying following lines
2792 no longer contain unusual constructs. */
2793
2794 #ifndef ASM_APP_OFF
2795 #define ASM_APP_OFF " #NO_APP\n"
2796 #endif
2797
2798 /* How to refer to registers in assembler output.
2799 This sequence is indexed by compiler's hard-register-number (see above).
2800
2801 In order to support the two different conventions for register names,
2802 we use the name of a table set up in mips.c, which is overwritten
2803 if -mrnames is used. */
2804
2805 #define REGISTER_NAMES \
2806 { \
2807 &mips_reg_names[ 0][0], \
2808 &mips_reg_names[ 1][0], \
2809 &mips_reg_names[ 2][0], \
2810 &mips_reg_names[ 3][0], \
2811 &mips_reg_names[ 4][0], \
2812 &mips_reg_names[ 5][0], \
2813 &mips_reg_names[ 6][0], \
2814 &mips_reg_names[ 7][0], \
2815 &mips_reg_names[ 8][0], \
2816 &mips_reg_names[ 9][0], \
2817 &mips_reg_names[10][0], \
2818 &mips_reg_names[11][0], \
2819 &mips_reg_names[12][0], \
2820 &mips_reg_names[13][0], \
2821 &mips_reg_names[14][0], \
2822 &mips_reg_names[15][0], \
2823 &mips_reg_names[16][0], \
2824 &mips_reg_names[17][0], \
2825 &mips_reg_names[18][0], \
2826 &mips_reg_names[19][0], \
2827 &mips_reg_names[20][0], \
2828 &mips_reg_names[21][0], \
2829 &mips_reg_names[22][0], \
2830 &mips_reg_names[23][0], \
2831 &mips_reg_names[24][0], \
2832 &mips_reg_names[25][0], \
2833 &mips_reg_names[26][0], \
2834 &mips_reg_names[27][0], \
2835 &mips_reg_names[28][0], \
2836 &mips_reg_names[29][0], \
2837 &mips_reg_names[30][0], \
2838 &mips_reg_names[31][0], \
2839 &mips_reg_names[32][0], \
2840 &mips_reg_names[33][0], \
2841 &mips_reg_names[34][0], \
2842 &mips_reg_names[35][0], \
2843 &mips_reg_names[36][0], \
2844 &mips_reg_names[37][0], \
2845 &mips_reg_names[38][0], \
2846 &mips_reg_names[39][0], \
2847 &mips_reg_names[40][0], \
2848 &mips_reg_names[41][0], \
2849 &mips_reg_names[42][0], \
2850 &mips_reg_names[43][0], \
2851 &mips_reg_names[44][0], \
2852 &mips_reg_names[45][0], \
2853 &mips_reg_names[46][0], \
2854 &mips_reg_names[47][0], \
2855 &mips_reg_names[48][0], \
2856 &mips_reg_names[49][0], \
2857 &mips_reg_names[50][0], \
2858 &mips_reg_names[51][0], \
2859 &mips_reg_names[52][0], \
2860 &mips_reg_names[53][0], \
2861 &mips_reg_names[54][0], \
2862 &mips_reg_names[55][0], \
2863 &mips_reg_names[56][0], \
2864 &mips_reg_names[57][0], \
2865 &mips_reg_names[58][0], \
2866 &mips_reg_names[59][0], \
2867 &mips_reg_names[60][0], \
2868 &mips_reg_names[61][0], \
2869 &mips_reg_names[62][0], \
2870 &mips_reg_names[63][0], \
2871 &mips_reg_names[64][0], \
2872 &mips_reg_names[65][0], \
2873 &mips_reg_names[66][0], \
2874 &mips_reg_names[67][0], \
2875 &mips_reg_names[68][0], \
2876 &mips_reg_names[69][0], \
2877 &mips_reg_names[70][0], \
2878 &mips_reg_names[71][0], \
2879 &mips_reg_names[72][0], \
2880 &mips_reg_names[73][0], \
2881 &mips_reg_names[74][0], \
2882 &mips_reg_names[75][0], \
2883 &mips_reg_names[76][0], \
2884 &mips_reg_names[77][0], \
2885 &mips_reg_names[78][0], \
2886 &mips_reg_names[79][0], \
2887 &mips_reg_names[80][0], \
2888 &mips_reg_names[81][0], \
2889 &mips_reg_names[82][0], \
2890 &mips_reg_names[83][0], \
2891 &mips_reg_names[84][0], \
2892 &mips_reg_names[85][0], \
2893 &mips_reg_names[86][0], \
2894 &mips_reg_names[87][0], \
2895 &mips_reg_names[88][0], \
2896 &mips_reg_names[89][0], \
2897 &mips_reg_names[90][0], \
2898 &mips_reg_names[91][0], \
2899 &mips_reg_names[92][0], \
2900 &mips_reg_names[93][0], \
2901 &mips_reg_names[94][0], \
2902 &mips_reg_names[95][0], \
2903 &mips_reg_names[96][0], \
2904 &mips_reg_names[97][0], \
2905 &mips_reg_names[98][0], \
2906 &mips_reg_names[99][0], \
2907 &mips_reg_names[100][0], \
2908 &mips_reg_names[101][0], \
2909 &mips_reg_names[102][0], \
2910 &mips_reg_names[103][0], \
2911 &mips_reg_names[104][0], \
2912 &mips_reg_names[105][0], \
2913 &mips_reg_names[106][0], \
2914 &mips_reg_names[107][0], \
2915 &mips_reg_names[108][0], \
2916 &mips_reg_names[109][0], \
2917 &mips_reg_names[110][0], \
2918 &mips_reg_names[111][0], \
2919 &mips_reg_names[112][0], \
2920 &mips_reg_names[113][0], \
2921 &mips_reg_names[114][0], \
2922 &mips_reg_names[115][0], \
2923 &mips_reg_names[116][0], \
2924 &mips_reg_names[117][0], \
2925 &mips_reg_names[118][0], \
2926 &mips_reg_names[119][0], \
2927 &mips_reg_names[120][0], \
2928 &mips_reg_names[121][0], \
2929 &mips_reg_names[122][0], \
2930 &mips_reg_names[123][0], \
2931 &mips_reg_names[124][0], \
2932 &mips_reg_names[125][0], \
2933 &mips_reg_names[126][0], \
2934 &mips_reg_names[127][0], \
2935 &mips_reg_names[128][0], \
2936 &mips_reg_names[129][0], \
2937 &mips_reg_names[130][0], \
2938 &mips_reg_names[131][0], \
2939 &mips_reg_names[132][0], \
2940 &mips_reg_names[133][0], \
2941 &mips_reg_names[134][0], \
2942 &mips_reg_names[135][0], \
2943 &mips_reg_names[136][0], \
2944 &mips_reg_names[137][0], \
2945 &mips_reg_names[138][0], \
2946 &mips_reg_names[139][0], \
2947 &mips_reg_names[140][0], \
2948 &mips_reg_names[141][0], \
2949 &mips_reg_names[142][0], \
2950 &mips_reg_names[143][0], \
2951 &mips_reg_names[144][0], \
2952 &mips_reg_names[145][0], \
2953 &mips_reg_names[146][0], \
2954 &mips_reg_names[147][0], \
2955 &mips_reg_names[148][0], \
2956 &mips_reg_names[149][0], \
2957 &mips_reg_names[150][0], \
2958 &mips_reg_names[151][0], \
2959 &mips_reg_names[152][0], \
2960 &mips_reg_names[153][0], \
2961 &mips_reg_names[154][0], \
2962 &mips_reg_names[155][0], \
2963 &mips_reg_names[156][0], \
2964 &mips_reg_names[157][0], \
2965 &mips_reg_names[158][0], \
2966 &mips_reg_names[159][0], \
2967 &mips_reg_names[160][0], \
2968 &mips_reg_names[161][0], \
2969 &mips_reg_names[162][0], \
2970 &mips_reg_names[163][0], \
2971 &mips_reg_names[164][0], \
2972 &mips_reg_names[165][0], \
2973 &mips_reg_names[166][0], \
2974 &mips_reg_names[167][0], \
2975 &mips_reg_names[168][0], \
2976 &mips_reg_names[169][0], \
2977 &mips_reg_names[170][0], \
2978 &mips_reg_names[171][0], \
2979 &mips_reg_names[172][0], \
2980 &mips_reg_names[173][0], \
2981 &mips_reg_names[174][0], \
2982 &mips_reg_names[175][0] \
2983 }
2984
2985 /* If defined, a C initializer for an array of structures
2986 containing a name and a register number. This macro defines
2987 additional names for hard registers, thus allowing the `asm'
2988 option in declarations to refer to registers using alternate
2989 names.
2990
2991 We define both names for the integer registers here. */
2992
2993 #define ADDITIONAL_REGISTER_NAMES \
2994 { \
2995 { "$0", 0 + GP_REG_FIRST }, \
2996 { "$1", 1 + GP_REG_FIRST }, \
2997 { "$2", 2 + GP_REG_FIRST }, \
2998 { "$3", 3 + GP_REG_FIRST }, \
2999 { "$4", 4 + GP_REG_FIRST }, \
3000 { "$5", 5 + GP_REG_FIRST }, \
3001 { "$6", 6 + GP_REG_FIRST }, \
3002 { "$7", 7 + GP_REG_FIRST }, \
3003 { "$8", 8 + GP_REG_FIRST }, \
3004 { "$9", 9 + GP_REG_FIRST }, \
3005 { "$10", 10 + GP_REG_FIRST }, \
3006 { "$11", 11 + GP_REG_FIRST }, \
3007 { "$12", 12 + GP_REG_FIRST }, \
3008 { "$13", 13 + GP_REG_FIRST }, \
3009 { "$14", 14 + GP_REG_FIRST }, \
3010 { "$15", 15 + GP_REG_FIRST }, \
3011 { "$16", 16 + GP_REG_FIRST }, \
3012 { "$17", 17 + GP_REG_FIRST }, \
3013 { "$18", 18 + GP_REG_FIRST }, \
3014 { "$19", 19 + GP_REG_FIRST }, \
3015 { "$20", 20 + GP_REG_FIRST }, \
3016 { "$21", 21 + GP_REG_FIRST }, \
3017 { "$22", 22 + GP_REG_FIRST }, \
3018 { "$23", 23 + GP_REG_FIRST }, \
3019 { "$24", 24 + GP_REG_FIRST }, \
3020 { "$25", 25 + GP_REG_FIRST }, \
3021 { "$26", 26 + GP_REG_FIRST }, \
3022 { "$27", 27 + GP_REG_FIRST }, \
3023 { "$28", 28 + GP_REG_FIRST }, \
3024 { "$29", 29 + GP_REG_FIRST }, \
3025 { "$30", 30 + GP_REG_FIRST }, \
3026 { "$31", 31 + GP_REG_FIRST }, \
3027 { "$sp", 29 + GP_REG_FIRST }, \
3028 { "$fp", 30 + GP_REG_FIRST }, \
3029 { "at", 1 + GP_REG_FIRST }, \
3030 { "v0", 2 + GP_REG_FIRST }, \
3031 { "v1", 3 + GP_REG_FIRST }, \
3032 { "a0", 4 + GP_REG_FIRST }, \
3033 { "a1", 5 + GP_REG_FIRST }, \
3034 { "a2", 6 + GP_REG_FIRST }, \
3035 { "a3", 7 + GP_REG_FIRST }, \
3036 { "t0", 8 + GP_REG_FIRST }, \
3037 { "t1", 9 + GP_REG_FIRST }, \
3038 { "t2", 10 + GP_REG_FIRST }, \
3039 { "t3", 11 + GP_REG_FIRST }, \
3040 { "t4", 12 + GP_REG_FIRST }, \
3041 { "t5", 13 + GP_REG_FIRST }, \
3042 { "t6", 14 + GP_REG_FIRST }, \
3043 { "t7", 15 + GP_REG_FIRST }, \
3044 { "s0", 16 + GP_REG_FIRST }, \
3045 { "s1", 17 + GP_REG_FIRST }, \
3046 { "s2", 18 + GP_REG_FIRST }, \
3047 { "s3", 19 + GP_REG_FIRST }, \
3048 { "s4", 20 + GP_REG_FIRST }, \
3049 { "s5", 21 + GP_REG_FIRST }, \
3050 { "s6", 22 + GP_REG_FIRST }, \
3051 { "s7", 23 + GP_REG_FIRST }, \
3052 { "t8", 24 + GP_REG_FIRST }, \
3053 { "t9", 25 + GP_REG_FIRST }, \
3054 { "k0", 26 + GP_REG_FIRST }, \
3055 { "k1", 27 + GP_REG_FIRST }, \
3056 { "gp", 28 + GP_REG_FIRST }, \
3057 { "sp", 29 + GP_REG_FIRST }, \
3058 { "fp", 30 + GP_REG_FIRST }, \
3059 { "ra", 31 + GP_REG_FIRST }, \
3060 { "$sp", 29 + GP_REG_FIRST }, \
3061 { "$fp", 30 + GP_REG_FIRST } \
3062 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3063 }
3064
3065 /* This is meant to be redefined in the host dependent files. It is a
3066 set of alternative names and regnums for mips coprocessors. */
3067
3068 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3069
3070 /* A C compound statement to output to stdio stream STREAM the
3071 assembler syntax for an instruction operand X. X is an RTL
3072 expression.
3073
3074 CODE is a value that can be used to specify one of several ways
3075 of printing the operand. It is used when identical operands
3076 must be printed differently depending on the context. CODE
3077 comes from the `%' specification that was used to request
3078 printing of the operand. If the specification was just `%DIGIT'
3079 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3080 is the ASCII code for LTR.
3081
3082 If X is a register, this macro should print the register's name.
3083 The names can be found in an array `reg_names' whose type is
3084 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3085
3086 When the machine description has a specification `%PUNCT' (a `%'
3087 followed by a punctuation character), this macro is called with
3088 a null pointer for X and the punctuation character for CODE.
3089
3090 See mips.c for the MIPS specific codes. */
3091
3092 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3093
3094 /* A C expression which evaluates to true if CODE is a valid
3095 punctuation character for use in the `PRINT_OPERAND' macro. If
3096 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3097 punctuation characters (except for the standard one, `%') are
3098 used in this way. */
3099
3100 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3101
3102 /* A C compound statement to output to stdio stream STREAM the
3103 assembler syntax for an instruction operand that is a memory
3104 reference whose address is ADDR. ADDR is an RTL expression. */
3105
3106 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3107
3108
3109 /* A C statement, to be executed after all slot-filler instructions
3110 have been output. If necessary, call `dbr_sequence_length' to
3111 determine the number of slots filled in a sequence (zero if not
3112 currently outputting a sequence), to decide how many no-ops to
3113 output, or whatever.
3114
3115 Don't define this macro if it has nothing to do, but it is
3116 helpful in reading assembly output if the extent of the delay
3117 sequence is made explicit (e.g. with white space).
3118
3119 Note that output routines for instructions with delay slots must
3120 be prepared to deal with not being output as part of a sequence
3121 (i.e. when the scheduling pass is not run, or when no slot
3122 fillers could be found.) The variable `final_sequence' is null
3123 when not processing a sequence, otherwise it contains the
3124 `sequence' rtx being output. */
3125
3126 #define DBR_OUTPUT_SEQEND(STREAM) \
3127 do \
3128 { \
3129 if (set_nomacro > 0 && --set_nomacro == 0) \
3130 fputs ("\t.set\tmacro\n", STREAM); \
3131 \
3132 if (set_noreorder > 0 && --set_noreorder == 0) \
3133 fputs ("\t.set\treorder\n", STREAM); \
3134 \
3135 fputs ("\n", STREAM); \
3136 } \
3137 while (0)
3138
3139
3140 /* How to tell the debugger about changes of source files. */
3141
3142 #ifndef SET_FILE_NUMBER
3143 #define SET_FILE_NUMBER() ++num_source_filenames
3144 #endif
3145
3146 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3147 mips_output_filename (STREAM, NAME)
3148
3149 /* This is defined so that it can be overridden in iris6.h. */
3150 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3151 do \
3152 { \
3153 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3154 output_quoted_string (STREAM, NAME); \
3155 fputs ("\n", STREAM); \
3156 } \
3157 while (0)
3158
3159 /* This is how to output a note the debugger telling it the line number
3160 to which the following sequence of instructions corresponds.
3161 Silicon graphics puts a label after each .loc. */
3162
3163 #ifndef LABEL_AFTER_LOC
3164 #define LABEL_AFTER_LOC(STREAM)
3165 #endif
3166
3167 #ifndef ASM_OUTPUT_SOURCE_LINE
3168 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3169 mips_output_lineno (STREAM, LINE)
3170 #endif
3171
3172 /* The MIPS implementation uses some labels for its own purpose. The
3173 following lists what labels are created, and are all formed by the
3174 pattern $L[a-z].*. The machine independent portion of GCC creates
3175 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3176
3177 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3178 $Lb[0-9]+ Begin blocks for MIPS debug support
3179 $Lc[0-9]+ Label for use in s<xx> operation.
3180 $Le[0-9]+ End blocks for MIPS debug support */
3181
3182 #undef ASM_DECLARE_OBJECT_NAME
3183 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3184 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3185
3186 /* Globalizing directive for a label. */
3187 #define GLOBAL_ASM_OP "\t.globl\t"
3188
3189 /* This says how to define a global common symbol. */
3190
3191 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
3192
3193 /* This says how to define a local common symbol (ie, not visible to
3194 linker). */
3195
3196 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3197 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3198
3199
3200 /* This says how to output an external. It would be possible not to
3201 output anything and let undefined symbol become external. However
3202 the assembler uses length information on externals to allocate in
3203 data/sdata bss/sbss, thereby saving exec time. */
3204
3205 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3206 mips_output_external(STREAM,DECL,NAME)
3207
3208 /* This is how to declare a function name. The actual work of
3209 emitting the label is moved to function_prologue, so that we can
3210 get the line number correctly emitted before the .ent directive,
3211 and after any .file directives. Define as empty so that the function
3212 is not declared before the .ent directive elsewhere. */
3213
3214 #undef ASM_DECLARE_FUNCTION_NAME
3215 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3216
3217 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3218 #define FUNCTION_NAME_ALREADY_DECLARED 0
3219 #endif
3220
3221 /* This is how to store into the string LABEL
3222 the symbol_ref name of an internal numbered label where
3223 PREFIX is the class of label and NUM is the number within the class.
3224 This is suitable for output with `assemble_name'. */
3225
3226 #undef ASM_GENERATE_INTERNAL_LABEL
3227 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3228 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3229
3230 /* This is how to output an element of a case-vector that is absolute. */
3231
3232 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3233 fprintf (STREAM, "\t%s\t%sL%d\n", \
3234 ptr_mode == DImode ? ".dword" : ".word", \
3235 LOCAL_LABEL_PREFIX, \
3236 VALUE)
3237
3238 /* This is how to output an element of a case-vector. We can make the
3239 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
3240 is supported. */
3241
3242 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3243 do { \
3244 if (TARGET_MIPS16) \
3245 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3246 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3247 else if (TARGET_GPWORD) \
3248 fprintf (STREAM, "\t%s\t%sL%d\n", \
3249 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3250 LOCAL_LABEL_PREFIX, VALUE); \
3251 else \
3252 fprintf (STREAM, "\t%s\t%sL%d\n", \
3253 ptr_mode == DImode ? ".dword" : ".word", \
3254 LOCAL_LABEL_PREFIX, VALUE); \
3255 } while (0)
3256
3257 /* When generating mips16 code we want to put the jump table in the .text
3258 section. In all other cases, we want to put the jump table in the .rdata
3259 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
3260 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
3261 to the .text section if appropriate. */
3262 #undef ASM_OUTPUT_CASE_LABEL
3263 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3264 do { \
3265 if (TARGET_MIPS16) \
3266 function_section (current_function_decl); \
3267 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3268 } while (0)
3269
3270 /* This is how to output an assembler line
3271 that says to advance the location counter
3272 to a multiple of 2**LOG bytes. */
3273
3274 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3275 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3276
3277 /* This is how to output an assembler line to advance the location
3278 counter by SIZE bytes. */
3279
3280 #undef ASM_OUTPUT_SKIP
3281 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3282 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3283
3284 /* This is how to output a string. */
3285 #undef ASM_OUTPUT_ASCII
3286 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3287 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3288
3289 /* Output #ident as a in the read-only data section. */
3290 #undef ASM_OUTPUT_IDENT
3291 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3292 { \
3293 const char *p = STRING; \
3294 int size = strlen (p) + 1; \
3295 readonly_data_section (); \
3296 assemble_string (p, size); \
3297 }
3298 \f
3299 /* Default to -G 8 */
3300 #ifndef MIPS_DEFAULT_GVALUE
3301 #define MIPS_DEFAULT_GVALUE 8
3302 #endif
3303
3304 /* Define the strings to put out for each section in the object file. */
3305 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3306 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3307 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3308
3309 #undef READONLY_DATA_SECTION_ASM_OP
3310 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3311
3312 /* Given a decl node or constant node, choose the section to output it in
3313 and select that section. */
3314
3315 #undef TARGET_ASM_SELECT_SECTION
3316 #define TARGET_ASM_SELECT_SECTION mips_select_section
3317 \f
3318 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3319 do \
3320 { \
3321 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3322 TARGET_64BIT ? "dsubu" : "subu", \
3323 reg_names[STACK_POINTER_REGNUM], \
3324 reg_names[STACK_POINTER_REGNUM], \
3325 TARGET_64BIT ? "sd" : "sw", \
3326 reg_names[REGNO], \
3327 reg_names[STACK_POINTER_REGNUM]); \
3328 } \
3329 while (0)
3330
3331 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3332 do \
3333 { \
3334 if (! set_noreorder) \
3335 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3336 \
3337 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3338 TARGET_64BIT ? "ld" : "lw", \
3339 reg_names[REGNO], \
3340 reg_names[STACK_POINTER_REGNUM], \
3341 TARGET_64BIT ? "daddu" : "addu", \
3342 reg_names[STACK_POINTER_REGNUM], \
3343 reg_names[STACK_POINTER_REGNUM]); \
3344 \
3345 if (! set_noreorder) \
3346 fprintf (STREAM, "\t.set\treorder\n"); \
3347 } \
3348 while (0)
3349
3350 /* How to start an assembler comment.
3351 The leading space is important (the mips native assembler requires it). */
3352 #ifndef ASM_COMMENT_START
3353 #define ASM_COMMENT_START " #"
3354 #endif
3355 \f
3356 /* Default definitions for size_t and ptrdiff_t. We must override the
3357 definitions from ../svr4.h on mips-*-linux-gnu. */
3358
3359 #undef SIZE_TYPE
3360 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3361
3362 #undef PTRDIFF_TYPE
3363 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3364
3365 /* See mips_expand_prologue's use of loadgp for when this should be
3366 true. */
3367
3368 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3369 \f
3370 /* Generate calls to memcpy, etc., not bcopy, etc. */
3371 #define TARGET_MEM_FUNCTIONS
3372
3373 #ifndef __mips16
3374 /* Since the bits of the _init and _fini function is spread across
3375 many object files, each potentially with its own GP, we must assume
3376 we need to load our GP. We don't preserve $gp or $ra, since each
3377 init/fini chunk is supposed to initialize $gp, and crti/crtn
3378 already take care of preserving $ra and, when appropriate, $gp. */
3379 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3380 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3381 asm (SECTION_OP "\n\
3382 .set noreorder\n\
3383 bal 1f\n\
3384 nop\n\
3385 1: .cpload $31\n\
3386 .set reorder\n\
3387 jal " USER_LABEL_PREFIX #FUNC "\n\
3388 " TEXT_SECTION_ASM_OP);
3389 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3390 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3391 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3392 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3393 asm (SECTION_OP "\n\
3394 .set noreorder\n\
3395 bal 1f\n\
3396 nop\n\
3397 1: .set reorder\n\
3398 .cpsetup $31, $2, 1b\n\
3399 jal " USER_LABEL_PREFIX #FUNC "\n\
3400 " TEXT_SECTION_ASM_OP);
3401 #endif
3402 #endif
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