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* Makefile.in (cse.o): Depend on TARGET_H.
[official-gcc.git] / gcc / config / arm / arm.h
blobc2afa4dc21122cf020aa7cbd58714db3473dfdd5
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 if (TARGET_ARM) \
34 builtin_define ("__arm__"); \
35 else \
36 builtin_define ("__thumb__"); \
37 \
38 if (TARGET_BIG_END) \
39 { \
40 builtin_define ("__ARMEB__"); \
41 if (TARGET_THUMB) \
42 builtin_define ("__THUMBEB__"); \
43 if (TARGET_LITTLE_WORDS) \
44 builtin_define ("__ARMWEL__"); \
45 } \
46 else \
47 { \
48 builtin_define ("__ARMEL__"); \
49 if (TARGET_THUMB) \
50 builtin_define ("__THUMBEL__"); \
51 } \
52 \
53 if (TARGET_APCS_32) \
54 builtin_define ("__APCS_32__"); \
55 else \
56 builtin_define ("__APCS_26__"); \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
62 FPA. */ \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
64 builtin_define ("__VFP_FP__"); \
65 \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (TARGET_INTERWORK) \
69 builtin_define ("__THUMB_INTERWORK__"); \
70 \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
73 } while (0)
74
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 /* Configure didn't specify. */
100 #define TARGET_CPU_generic 0x8000
101
102 typedef enum arm_cond_code
103 {
104 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
105 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
106 }
107 arm_cc;
108
109 extern arm_cc arm_current_cc;
110
111 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
112
113 extern int arm_target_label;
114 extern int arm_ccfsm_state;
115 extern GTY(()) rtx arm_target_insn;
116 /* Run-time compilation parameters selecting different hardware subsets. */
117 extern int target_flags;
118 /* The floating point instruction architecture, can be 2 or 3 */
119 extern const char * target_fp_name;
120 /* Define the information needed to generate branch insns. This is
121 stored from the compare operation. */
122 extern GTY(()) rtx arm_compare_op0;
123 extern GTY(()) rtx arm_compare_op1;
124 /* The label of the current constant pool. */
125 extern rtx pool_vector_label;
126 /* Set to 1 when a return insn is output, this means that the epilogue
127 is not needed. */
128 extern int return_used_this_function;
129 /* Used to produce AOF syntax assembler. */
130 extern GTY(()) rtx aof_pic_label;
131 \f
132 /* Just in case configure has failed to define anything. */
133 #ifndef TARGET_CPU_DEFAULT
134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
135 #endif
136
137 /* If the configuration file doesn't specify the cpu, the subtarget may
138 override it. If it doesn't, then default to an ARM6. */
139 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
140 #undef TARGET_CPU_DEFAULT
141
142 #ifdef SUBTARGET_CPU_DEFAULT
143 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
144 #else
145 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
146 #endif
147 #endif
148
149 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
150 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
151 #else
152 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
153 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
154 #else
155 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
156 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
157 #else
158 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
159 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
160 #else
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
162 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
163 #else
164 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
165 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
166 #else
167 Unrecognized value in TARGET_CPU_DEFAULT.
168 #endif
169 #endif
170 #endif
171 #endif
172 #endif
173 #endif
174
175 #undef CPP_SPEC
176 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
177 %{mapcs-32:%{mapcs-26: \
178 %e-mapcs-26 and -mapcs-32 may not be used together}} \
179 %{msoft-float:%{mhard-float: \
180 %e-msoft-float and -mhard_float may not be used together}} \
181 %{mbig-endian:%{mlittle-endian: \
182 %e-mbig-endian and -mlittle-endian may not be used together}}"
183
184 /* Set the architecture define -- if -march= is set, then it overrides
185 the -mcpu= setting. */
186 #define CPP_CPU_ARCH_SPEC "\
187 %{march=arm2:-D__ARM_ARCH_2__} \
188 %{march=arm250:-D__ARM_ARCH_2__} \
189 %{march=arm3:-D__ARM_ARCH_2__} \
190 %{march=arm6:-D__ARM_ARCH_3__} \
191 %{march=arm600:-D__ARM_ARCH_3__} \
192 %{march=arm610:-D__ARM_ARCH_3__} \
193 %{march=arm7:-D__ARM_ARCH_3__} \
194 %{march=arm700:-D__ARM_ARCH_3__} \
195 %{march=arm710:-D__ARM_ARCH_3__} \
196 %{march=arm720:-D__ARM_ARCH_3__} \
197 %{march=arm7100:-D__ARM_ARCH_3__} \
198 %{march=arm7500:-D__ARM_ARCH_3__} \
199 %{march=arm7500fe:-D__ARM_ARCH_3__} \
200 %{march=arm7m:-D__ARM_ARCH_3M__} \
201 %{march=arm7dm:-D__ARM_ARCH_3M__} \
202 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
203 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
204 %{march=arm8:-D__ARM_ARCH_4__} \
205 %{march=arm810:-D__ARM_ARCH_4__} \
206 %{march=arm9:-D__ARM_ARCH_4T__} \
207 %{march=arm920:-D__ARM_ARCH_4__} \
208 %{march=arm920t:-D__ARM_ARCH_4T__} \
209 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
210 %{march=strongarm:-D__ARM_ARCH_4__} \
211 %{march=strongarm110:-D__ARM_ARCH_4__} \
212 %{march=strongarm1100:-D__ARM_ARCH_4__} \
213 %{march=xscale:-D__ARM_ARCH_5TE__} \
214 %{march=xscale:-D__XSCALE__} \
215 %{march=armv2:-D__ARM_ARCH_2__} \
216 %{march=armv2a:-D__ARM_ARCH_2__} \
217 %{march=armv3:-D__ARM_ARCH_3__} \
218 %{march=armv3m:-D__ARM_ARCH_3M__} \
219 %{march=armv4:-D__ARM_ARCH_4__} \
220 %{march=armv4t:-D__ARM_ARCH_4T__} \
221 %{march=armv5:-D__ARM_ARCH_5__} \
222 %{march=armv5t:-D__ARM_ARCH_5T__} \
223 %{march=armv5e:-D__ARM_ARCH_5E__} \
224 %{march=armv5te:-D__ARM_ARCH_5TE__} \
225 %{!march=*: \
226 %{mcpu=arm2:-D__ARM_ARCH_2__} \
227 %{mcpu=arm250:-D__ARM_ARCH_2__} \
228 %{mcpu=arm3:-D__ARM_ARCH_2__} \
229 %{mcpu=arm6:-D__ARM_ARCH_3__} \
230 %{mcpu=arm600:-D__ARM_ARCH_3__} \
231 %{mcpu=arm610:-D__ARM_ARCH_3__} \
232 %{mcpu=arm7:-D__ARM_ARCH_3__} \
233 %{mcpu=arm700:-D__ARM_ARCH_3__} \
234 %{mcpu=arm710:-D__ARM_ARCH_3__} \
235 %{mcpu=arm720:-D__ARM_ARCH_3__} \
236 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
237 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
238 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
239 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
240 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
241 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
242 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
243 %{mcpu=arm8:-D__ARM_ARCH_4__} \
244 %{mcpu=arm810:-D__ARM_ARCH_4__} \
245 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
246 %{mcpu=arm920:-D__ARM_ARCH_4__} \
247 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
248 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
249 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
250 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
251 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
252 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
253 %{mcpu=xscale:-D__XSCALE__} \
254 %{!mcpu*:%(cpp_cpu_arch_default)}} \
255 "
256
257 #ifndef CC1_SPEC
258 #define CC1_SPEC ""
259 #endif
260
261 /* This macro defines names of additional specifications to put in the specs
262 that can be used in various specifications like CC1_SPEC. Its definition
263 is an initializer with a subgrouping for each command option.
264
265 Each subgrouping contains a string constant, that defines the
266 specification name, and a string constant that used by the GNU CC driver
267 program.
268
269 Do not define this macro if it does not need to do anything. */
270 #define EXTRA_SPECS \
271 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
272 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
273 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
274 SUBTARGET_EXTRA_SPECS
275
276 #ifndef SUBTARGET_EXTRA_SPECS
277 #define SUBTARGET_EXTRA_SPECS
278 #endif
279
280 #ifndef SUBTARGET_CPP_SPEC
281 #define SUBTARGET_CPP_SPEC ""
282 #endif
283 \f
284 /* Run-time Target Specification. */
285 #ifndef TARGET_VERSION
286 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
287 #endif
288
289 /* Nonzero if the function prologue (and epilogue) should obey
290 the ARM Procedure Call Standard. */
291 #define ARM_FLAG_APCS_FRAME (1 << 0)
292
293 /* Nonzero if the function prologue should output the function name to enable
294 the post mortem debugger to print a backtrace (very useful on RISCOS,
295 unused on RISCiX). Specifying this flag also enables
296 -fno-omit-frame-pointer.
297 XXX Must still be implemented in the prologue. */
298 #define ARM_FLAG_POKE (1 << 1)
299
300 /* Nonzero if floating point instructions are emulated by the FPE, in which
301 case instruction scheduling becomes very uninteresting. */
302 #define ARM_FLAG_FPE (1 << 2)
303
304 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
305 that assume restoration of the condition flags when returning from a
306 branch and link (ie a function). */
307 #define ARM_FLAG_APCS_32 (1 << 3)
308
309 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
310
311 /* Nonzero if stack checking should be performed on entry to each function
312 which allocates temporary variables on the stack. */
313 #define ARM_FLAG_APCS_STACK (1 << 4)
314
315 /* Nonzero if floating point parameters should be passed to functions in
316 floating point registers. */
317 #define ARM_FLAG_APCS_FLOAT (1 << 5)
318
319 /* Nonzero if re-entrant, position independent code should be generated.
320 This is equivalent to -fpic. */
321 #define ARM_FLAG_APCS_REENT (1 << 6)
322
323 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
324 be loaded using either LDRH or LDRB instructions. */
325 #define ARM_FLAG_MMU_TRAPS (1 << 7)
326
327 /* Nonzero if all floating point instructions are missing (and there is no
328 emulator either). Generate function calls for all ops in this case. */
329 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
330
331 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
332 #define ARM_FLAG_BIG_END (1 << 9)
333
334 /* Nonzero if we should compile for Thumb interworking. */
335 #define ARM_FLAG_INTERWORK (1 << 10)
336
337 /* Nonzero if we should have little-endian words even when compiling for
338 big-endian (for backwards compatibility with older versions of GCC). */
339 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
340
341 /* Nonzero if we need to protect the prolog from scheduling */
342 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
343
344 /* Nonzero if a call to abort should be generated if a noreturn
345 function tries to return. */
346 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
347
348 /* Nonzero if function prologues should not load the PIC register. */
349 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
350
351 /* Nonzero if all call instructions should be indirect. */
352 #define ARM_FLAG_LONG_CALLS (1 << 15)
353
354 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
355 #define ARM_FLAG_THUMB (1 << 16)
356
357 /* Set if a TPCS style stack frame should be generated, for non-leaf
358 functions, even if they do not need one. */
359 #define THUMB_FLAG_BACKTRACE (1 << 17)
360
361 /* Set if a TPCS style stack frame should be generated, for leaf
362 functions, even if they do not need one. */
363 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
364
365 /* Set if externally visible functions should assume that they
366 might be called in ARM mode, from a non-thumb aware code. */
367 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
368
369 /* Set if calls via function pointers should assume that their
370 destination is non-Thumb aware. */
371 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
372
373 /* Nonzero means target uses VFP FP. */
374 #define ARM_FLAG_VFP (1 << 21)
375
376 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
377 #define ARM_FLAG_ATPCS (1 << 22)
378
379 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
380 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
381 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
382 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
383 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
384 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
385 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
386 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
387 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
388 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
389 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
390 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
391 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
392 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
393 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
394 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
395 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
396 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
397 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
398 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
399 #define TARGET_ARM (! TARGET_THUMB)
400 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
401 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
402 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
403 #define TARGET_BACKTRACE (leaf_function_p () \
404 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
405 : (target_flags & THUMB_FLAG_BACKTRACE))
406
407 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
408 #ifndef SUBTARGET_SWITCHES
409 #define SUBTARGET_SWITCHES
410 #endif
411
412 #define TARGET_SWITCHES \
413 { \
414 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
415 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
416 N_("Generate APCS conformant stack frames") }, \
417 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
418 {"poke-function-name", ARM_FLAG_POKE, \
419 N_("Store function names in object code") }, \
420 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
421 {"fpe", ARM_FLAG_FPE, "" }, \
422 {"apcs-32", ARM_FLAG_APCS_32, \
423 N_("Use the 32-bit version of the APCS") }, \
424 {"apcs-26", -ARM_FLAG_APCS_32, \
425 N_("Use the 26-bit version of the APCS") }, \
426 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
427 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
428 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
429 N_("Pass FP arguments in FP registers") }, \
430 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
431 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
432 N_("Generate re-entrant, PIC code") }, \
433 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
434 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
435 N_("The MMU will trap on unaligned accesses") }, \
436 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
437 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
438 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
439 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
440 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
441 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
442 N_("Use library calls to perform FP operations") }, \
443 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
444 N_("Use hardware floating point instructions") }, \
445 {"big-endian", ARM_FLAG_BIG_END, \
446 N_("Assume target CPU is configured as big endian") }, \
447 {"little-endian", -ARM_FLAG_BIG_END, \
448 N_("Assume target CPU is configured as little endian") }, \
449 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
450 N_("Assume big endian bytes, little endian words") }, \
451 {"thumb-interwork", ARM_FLAG_INTERWORK, \
452 N_("Support calls between Thumb and ARM instruction sets") }, \
453 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
454 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
455 N_("Generate a call to abort if a noreturn function returns")}, \
456 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
457 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
458 N_("Do not move instructions into a function's prologue") }, \
459 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
460 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
461 N_("Do not load the PIC register in function prologues") }, \
462 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
463 {"long-calls", ARM_FLAG_LONG_CALLS, \
464 N_("Generate call insns as indirect calls, if necessary") }, \
465 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
466 {"thumb", ARM_FLAG_THUMB, \
467 N_("Compile for the Thumb not the ARM") }, \
468 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
469 {"arm", -ARM_FLAG_THUMB, "" }, \
470 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
471 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
472 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
473 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
474 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
475 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
476 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
477 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
478 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
479 "" }, \
480 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
481 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
482 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
483 "" }, \
484 SUBTARGET_SWITCHES \
485 {"", TARGET_DEFAULT, "" } \
486 }
487
488 #define TARGET_OPTIONS \
489 { \
490 {"cpu=", & arm_select[0].string, \
491 N_("Specify the name of the target CPU") }, \
492 {"arch=", & arm_select[1].string, \
493 N_("Specify the name of the target architecture") }, \
494 {"tune=", & arm_select[2].string, "" }, \
495 {"fpe=", & target_fp_name, "" }, \
496 {"fp=", & target_fp_name, \
497 N_("Specify the version of the floating point emulator") }, \
498 {"structure-size-boundary=", & structure_size_string, \
499 N_("Specify the minimum bit alignment of structures") }, \
500 {"pic-register=", & arm_pic_register_string, \
501 N_("Specify the register to be used for PIC addressing") } \
502 }
503
504 struct arm_cpu_select
505 {
506 const char * string;
507 const char * name;
508 const struct processors * processors;
509 };
510
511 /* This is a magic array. If the user specifies a command line switch
512 which matches one of the entries in TARGET_OPTIONS then the corresponding
513 string pointer will be set to the value specified by the user. */
514 extern struct arm_cpu_select arm_select[];
515
516 enum prog_mode_type
517 {
518 prog_mode26,
519 prog_mode32
520 };
521
522 /* Recast the program mode class to be the prog_mode attribute */
523 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
524
525 extern enum prog_mode_type arm_prgmode;
526
527 /* What sort of floating point unit do we have? Hardware or software.
528 If software, is it issue 2 or issue 3? */
529 enum floating_point_type
530 {
531 FP_HARD,
532 FP_SOFT2,
533 FP_SOFT3
534 };
535
536 /* Recast the floating point class to be the floating point attribute. */
537 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
538
539 /* What type of floating point to tune for */
540 extern enum floating_point_type arm_fpu;
541
542 /* What type of floating point instructions are available */
543 extern enum floating_point_type arm_fpu_arch;
544
545 /* Default floating point architecture. Override in sub-target if
546 necessary. */
547 #ifndef FP_DEFAULT
548 #define FP_DEFAULT FP_SOFT2
549 #endif
550
551 /* Nonzero if the processor has a fast multiply insn, and one that does
552 a 64-bit multiply of two 32-bit values. */
553 extern int arm_fast_multiply;
554
555 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
556 extern int arm_arch4;
557
558 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
559 extern int arm_arch5;
560
561 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
562 extern int arm_arch5e;
563
564 /* Nonzero if this chip can benefit from load scheduling. */
565 extern int arm_ld_sched;
566
567 /* Nonzero if generating thumb code. */
568 extern int thumb_code;
569
570 /* Nonzero if this chip is a StrongARM. */
571 extern int arm_is_strong;
572
573 /* Nonzero if this chip is an XScale. */
574 extern int arm_is_xscale;
575
576 /* Nonzero if this chip is an ARM6 or an ARM7. */
577 extern int arm_is_6_or_7;
578
579 #ifndef TARGET_DEFAULT
580 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
581 #endif
582
583 /* The frame pointer register used in gcc has nothing to do with debugging;
584 that is controlled by the APCS-FRAME option. */
585 #define CAN_DEBUG_WITHOUT_FP
586
587 #undef TARGET_MEM_FUNCTIONS
588 #define TARGET_MEM_FUNCTIONS 1
589
590 #define OVERRIDE_OPTIONS arm_override_options ()
591
592 /* Nonzero if PIC code requires explicit qualifiers to generate
593 PLT and GOT relocs rather than the assembler doing so implicitly.
594 Subtargets can override these if required. */
595 #ifndef NEED_GOT_RELOC
596 #define NEED_GOT_RELOC 0
597 #endif
598 #ifndef NEED_PLT_RELOC
599 #define NEED_PLT_RELOC 0
600 #endif
601
602 /* Nonzero if we need to refer to the GOT with a PC-relative
603 offset. In other words, generate
604
605 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
606
607 rather than
608
609 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
610
611 The default is true, which matches NetBSD. Subtargets can
612 override this if required. */
613 #ifndef GOT_PCREL
614 #define GOT_PCREL 1
615 #endif
616 \f
617 /* Target machine storage Layout. */
618
619
620 /* Define this macro if it is advisable to hold scalars in registers
621 in a wider mode than that declared by the program. In such cases,
622 the value is constrained to be within the bounds of the declared
623 type, but kept valid in the wider mode. The signedness of the
624 extension may differ from that of the type. */
625
626 /* It is far faster to zero extend chars than to sign extend them */
627
628 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
629 if (GET_MODE_CLASS (MODE) == MODE_INT \
630 && GET_MODE_SIZE (MODE) < 4) \
631 { \
632 if (MODE == QImode) \
633 UNSIGNEDP = 1; \
634 else if (MODE == HImode) \
635 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
636 (MODE) = SImode; \
637 }
638
639 /* Define this macro if the promotion described by `PROMOTE_MODE'
640 should also be done for outgoing function arguments. */
641 /* This is required to ensure that push insns always push a word. */
642 #define PROMOTE_FUNCTION_ARGS
643
644 /* Define this if most significant bit is lowest numbered
645 in instructions that operate on numbered bit-fields. */
646 #define BITS_BIG_ENDIAN 0
647
648 /* Define this if most significant byte of a word is the lowest numbered.
649 Most ARM processors are run in little endian mode, so that is the default.
650 If you want to have it run-time selectable, change the definition in a
651 cover file to be TARGET_BIG_ENDIAN. */
652 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
653
654 /* Define this if most significant word of a multiword number is the lowest
655 numbered.
656 This is always false, even when in big-endian mode. */
657 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
658
659 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
660 on processor pre-defineds when compiling libgcc2.c. */
661 #if defined(__ARMEB__) && !defined(__ARMWEL__)
662 #define LIBGCC2_WORDS_BIG_ENDIAN 1
663 #else
664 #define LIBGCC2_WORDS_BIG_ENDIAN 0
665 #endif
666
667 /* Define this if most significant word of doubles is the lowest numbered.
668 The rules are different based on whether or not we use FPA-format or
669 VFP-format doubles. */
670 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
671
672 #define UNITS_PER_WORD 4
673
674 #define PARM_BOUNDARY 32
675
676 #define STACK_BOUNDARY 32
677
678 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
679
680 #define FUNCTION_BOUNDARY 32
681
682 /* The lowest bit is used to indicate Thumb-mode functions, so the
683 vbit must go into the delta field of pointers to member
684 functions. */
685 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
686
687 #define EMPTY_FIELD_BOUNDARY 32
688
689 #define BIGGEST_ALIGNMENT 32
690
691 /* Make strings word-aligned so strcpy from constants will be faster. */
692 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
693
694 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
695 ((TREE_CODE (EXP) == STRING_CST \
696 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
697 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
698
699 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
700 value set in previous versions of this toolchain was 8, which produces more
701 compact structures. The command line option -mstructure_size_boundary=<n>
702 can be used to change this value. For compatibility with the ARM SDK
703 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
704 0020D) page 2-20 says "Structures are aligned on word boundaries". */
705 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
706 extern int arm_structure_size_boundary;
707
708 /* This is the value used to initialize arm_structure_size_boundary. If a
709 particular arm target wants to change the default value it should change
710 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
711 for an example of this. */
712 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
713 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
714 #endif
715
716 /* Used when parsing command line option -mstructure_size_boundary. */
717 extern const char * structure_size_string;
718
719 /* Nonzero if move instructions will actually fail to work
720 when given unaligned data. */
721 #define STRICT_ALIGNMENT 1
722 \f
723 /* Standard register usage. */
724
725 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
726 (S - saved over call).
727
728 r0 * argument word/integer result
729 r1-r3 argument word
730
731 r4-r8 S register variable
732 r9 S (rfp) register variable (real frame pointer)
733
734 r10 F S (sl) stack limit (used by -mapcs-stack-check)
735 r11 F S (fp) argument pointer
736 r12 (ip) temp workspace
737 r13 F S (sp) lower end of current stack frame
738 r14 (lr) link address/workspace
739 r15 F (pc) program counter
740
741 f0 floating point result
742 f1-f3 floating point scratch
743
744 f4-f7 S floating point variable
745
746 cc This is NOT a real register, but is used internally
747 to represent things that use or set the condition
748 codes.
749 sfp This isn't either. It is used during rtl generation
750 since the offset between the frame pointer and the
751 auto's isn't known until after register allocation.
752 afp Nor this, we only need this because of non-local
753 goto. Without it fp appears to be used and the
754 elimination code won't get rid of sfp. It tracks
755 fp exactly at all times.
756
757 *: See CONDITIONAL_REGISTER_USAGE */
758
759 /* The stack backtrace structure is as follows:
760 fp points to here: | save code pointer | [fp]
761 | return link value | [fp, #-4]
762 | return sp value | [fp, #-8]
763 | return fp value | [fp, #-12]
764 [| saved r10 value |]
765 [| saved r9 value |]
766 [| saved r8 value |]
767 [| saved r7 value |]
768 [| saved r6 value |]
769 [| saved r5 value |]
770 [| saved r4 value |]
771 [| saved r3 value |]
772 [| saved r2 value |]
773 [| saved r1 value |]
774 [| saved r0 value |]
775 [| saved f7 value |] three words
776 [| saved f6 value |] three words
777 [| saved f5 value |] three words
778 [| saved f4 value |] three words
779 r0-r3 are not normally saved in a C function. */
780
781 /* 1 for registers that have pervasive standard uses
782 and are not available for the register allocator. */
783 #define FIXED_REGISTERS \
784 { \
785 0,0,0,0,0,0,0,0, \
786 0,0,0,0,0,1,0,1, \
787 0,0,0,0,0,0,0,0, \
788 1,1,1 \
789 }
790
791 /* 1 for registers not available across function calls.
792 These must include the FIXED_REGISTERS and also any
793 registers that can be used without being saved.
794 The latter must include the registers where values are returned
795 and the register where structure-value addresses are passed.
796 Aside from that, you can include as many other registers as you like.
797 The CC is not preserved over function calls on the ARM 6, so it is
798 easier to assume this for all. SFP is preserved, since FP is. */
799 #define CALL_USED_REGISTERS \
800 { \
801 1,1,1,1,0,0,0,0, \
802 0,0,0,0,1,1,1,1, \
803 1,1,1,1,0,0,0,0, \
804 1,1,1 \
805 }
806
807 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
808 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
809 #endif
810
811 #define CONDITIONAL_REGISTER_USAGE \
812 { \
813 int regno; \
814 \
815 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
816 { \
817 for (regno = FIRST_ARM_FP_REGNUM; \
818 regno <= LAST_ARM_FP_REGNUM; ++regno) \
819 fixed_regs[regno] = call_used_regs[regno] = 1; \
820 } \
821 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
822 { \
823 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
824 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
825 } \
826 else if (TARGET_APCS_STACK) \
827 { \
828 fixed_regs[10] = 1; \
829 call_used_regs[10] = 1; \
830 } \
831 if (TARGET_APCS_FRAME) \
832 { \
833 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
834 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
835 } \
836 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
837 }
838
839 /* These are a couple of extensions to the formats accecpted
840 by asm_fprintf:
841 %@ prints out ASM_COMMENT_START
842 %r prints out REGISTER_PREFIX reg_names[arg] */
843 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
844 case '@': \
845 fputs (ASM_COMMENT_START, FILE); \
846 break; \
847 \
848 case 'r': \
849 fputs (REGISTER_PREFIX, FILE); \
850 fputs (reg_names [va_arg (ARGS, int)], FILE); \
851 break;
852
853 /* Round X up to the nearest word. */
854 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
855
856 /* Convert fron bytes to ints. */
857 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
858
859 /* The number of (integer) registers required to hold a quantity of type MODE. */
860 #define ARM_NUM_REGS(MODE) \
861 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
862
863 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
864 #define ARM_NUM_REGS2(MODE, TYPE) \
865 ARM_NUM_INTS ((MODE) == BLKmode ? \
866 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
867
868 /* The number of (integer) argument register available. */
869 #define NUM_ARG_REGS 4
870
871 /* Return the regiser number of the N'th (integer) argument. */
872 #define ARG_REGISTER(N) (N - 1)
873
874 #if 0 /* FIXME: The ARM backend has special code to handle structure
875 returns, and will reserve its own hidden first argument. So
876 if this macro is enabled a *second* hidden argument will be
877 reserved, which will break binary compatibility with old
878 toolchains and also thunk handling. One day this should be
879 fixed. */
880 /* RTX for structure returns. NULL means use a hidden first argument. */
881 #define STRUCT_VALUE 0
882 #else
883 /* Register in which address to store a structure value
884 is passed to a function. */
885 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
886 #endif
887
888 /* Specify the registers used for certain standard purposes.
889 The values of these macros are register numbers. */
890
891 /* The number of the last argument register. */
892 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
893
894 /* The number of the last "lo" register (thumb). */
895 #define LAST_LO_REGNUM 7
896
897 /* The register that holds the return address in exception handlers. */
898 #define EXCEPTION_LR_REGNUM 2
899
900 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
901 as an invisible last argument (possible since varargs don't exist in
902 Pascal), so the following is not true. */
903 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
904
905 /* Define this to be where the real frame pointer is if it is not possible to
906 work out the offset between the frame pointer and the automatic variables
907 until after register allocation has taken place. FRAME_POINTER_REGNUM
908 should point to a special register that we will make sure is eliminated.
909
910 For the Thumb we have another problem. The TPCS defines the frame pointer
911 as r11, and GCC belives that it is always possible to use the frame pointer
912 as base register for addressing purposes. (See comments in
913 find_reloads_address()). But - the Thumb does not allow high registers,
914 including r11, to be used as base address registers. Hence our problem.
915
916 The solution used here, and in the old thumb port is to use r7 instead of
917 r11 as the hard frame pointer and to have special code to generate
918 backtrace structures on the stack (if required to do so via a command line
919 option) using r11. This is the only 'user visable' use of r11 as a frame
920 pointer. */
921 #define ARM_HARD_FRAME_POINTER_REGNUM 11
922 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
923
924 #define HARD_FRAME_POINTER_REGNUM \
925 (TARGET_ARM \
926 ? ARM_HARD_FRAME_POINTER_REGNUM \
927 : THUMB_HARD_FRAME_POINTER_REGNUM)
928
929 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
930
931 /* Register to use for pushing function arguments. */
932 #define STACK_POINTER_REGNUM SP_REGNUM
933
934 /* ARM floating pointer registers. */
935 #define FIRST_ARM_FP_REGNUM 16
936 #define LAST_ARM_FP_REGNUM 23
937
938 /* Base register for access to local variables of the function. */
939 #define FRAME_POINTER_REGNUM 25
940
941 /* Base register for access to arguments of the function. */
942 #define ARG_POINTER_REGNUM 26
943
944 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
945 #define FIRST_PSEUDO_REGISTER 27
946
947 /* Value should be nonzero if functions must have frame pointers.
948 Zero means the frame pointer need not be set up (and parms may be accessed
949 via the stack pointer) in functions that seem suitable.
950 If we have to have a frame pointer we might as well make use of it.
951 APCS says that the frame pointer does not need to be pushed in leaf
952 functions, or simple tail call functions. */
953 #define FRAME_POINTER_REQUIRED \
954 (current_function_has_nonlocal_label \
955 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
956
957 /* Return number of consecutive hard regs needed starting at reg REGNO
958 to hold something of mode MODE.
959 This is ordinarily the length in words of a value of mode MODE
960 but can be less for certain modes in special long registers.
961
962 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
963 mode. */
964 #define HARD_REGNO_NREGS(REGNO, MODE) \
965 ((TARGET_ARM \
966 && REGNO >= FIRST_ARM_FP_REGNUM \
967 && REGNO != FRAME_POINTER_REGNUM \
968 && REGNO != ARG_POINTER_REGNUM) \
969 ? 1 : ARM_NUM_REGS (MODE))
970
971 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
972 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
973 arm_hard_regno_mode_ok ((REGNO), (MODE))
974
975 /* Value is 1 if it is a good idea to tie two pseudo registers
976 when one has mode MODE1 and one has mode MODE2.
977 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
978 for any hard reg, then this must be 0 for correct output. */
979 #define MODES_TIEABLE_P(MODE1, MODE2) \
980 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
981
982 /* The order in which register should be allocated. It is good to use ip
983 since no saving is required (though calls clobber it) and it never contains
984 function parameters. It is quite good to use lr since other calls may
985 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
986 least likely to contain a function parameter; in addition results are
987 returned in r0. */
988 #define REG_ALLOC_ORDER \
989 { \
990 3, 2, 1, 0, 12, 14, 4, 5, \
991 6, 7, 8, 10, 9, 11, 13, 15, \
992 16, 17, 18, 19, 20, 21, 22, 23, \
993 24, 25, 26 \
994 }
995
996 /* Interrupt functions can only use registers that have already been
997 saved by the prologue, even if they would normally be
998 call-clobbered. */
999 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1000 (! IS_INTERRUPT (cfun->machine->func_type) || \
1001 regs_ever_live[DST])
1002 \f
1003 /* Register and constant classes. */
1004
1005 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1006 Now that the Thumb is involved it has become more complicated. */
1007 enum reg_class
1008 {
1009 NO_REGS,
1010 FPU_REGS,
1011 LO_REGS,
1012 STACK_REG,
1013 BASE_REGS,
1014 HI_REGS,
1015 CC_REG,
1016 GENERAL_REGS,
1017 ALL_REGS,
1018 LIM_REG_CLASSES
1019 };
1020
1021 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1022
1023 /* Give names of register classes as strings for dump file. */
1024 #define REG_CLASS_NAMES \
1025 { \
1026 "NO_REGS", \
1027 "FPU_REGS", \
1028 "LO_REGS", \
1029 "STACK_REG", \
1030 "BASE_REGS", \
1031 "HI_REGS", \
1032 "CC_REG", \
1033 "GENERAL_REGS", \
1034 "ALL_REGS", \
1035 }
1036
1037 /* Define which registers fit in which classes.
1038 This is an initializer for a vector of HARD_REG_SET
1039 of length N_REG_CLASSES. */
1040 #define REG_CLASS_CONTENTS \
1041 { \
1042 { 0x0000000 }, /* NO_REGS */ \
1043 { 0x0FF0000 }, /* FPU_REGS */ \
1044 { 0x00000FF }, /* LO_REGS */ \
1045 { 0x0002000 }, /* STACK_REG */ \
1046 { 0x00020FF }, /* BASE_REGS */ \
1047 { 0x000FF00 }, /* HI_REGS */ \
1048 { 0x1000000 }, /* CC_REG */ \
1049 { 0x200FFFF }, /* GENERAL_REGS */ \
1050 { 0x2FFFFFF } /* ALL_REGS */ \
1051 }
1052
1053 /* The same information, inverted:
1054 Return the class number of the smallest class containing
1055 reg number REGNO. This could be a conditional expression
1056 or could index an array. */
1057 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1058
1059 /* The class value for index registers, and the one for base regs. */
1060 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1061 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1062
1063 /* For the Thumb the high registers cannot be used as base registers
1064 when addressing quanitities in QI or HI mode; if we don't know the
1065 mode, then we must be conservative. After reload we must also be
1066 conservative, since we can't support SP+reg addressing, and we
1067 can't fix up any bad substitutions. */
1068 #define MODE_BASE_REG_CLASS(MODE) \
1069 (TARGET_ARM ? GENERAL_REGS : \
1070 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1071
1072 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1073 registers explicitly used in the rtl to be used as spill registers
1074 but prevents the compiler from extending the lifetime of these
1075 registers. */
1076 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1077
1078 /* Get reg_class from a letter such as appears in the machine description.
1079 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1080 ARM, but several more letters for the Thumb. */
1081 #define REG_CLASS_FROM_LETTER(C) \
1082 ( (C) == 'f' ? FPU_REGS \
1083 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1084 : TARGET_ARM ? NO_REGS \
1085 : (C) == 'h' ? HI_REGS \
1086 : (C) == 'b' ? BASE_REGS \
1087 : (C) == 'k' ? STACK_REG \
1088 : (C) == 'c' ? CC_REG \
1089 : NO_REGS)
1090
1091 /* The letters I, J, K, L and M in a register constraint string
1092 can be used to stand for particular ranges of immediate operands.
1093 This macro defines what the ranges are.
1094 C is the letter, and VALUE is a constant value.
1095 Return 1 if VALUE is in the range specified by C.
1096 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1097 J: valid indexing constants.
1098 K: ~value ok in rhs argument of data operand.
1099 L: -value ok in rhs argument of data operand.
1100 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1101 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1102 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1103 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1104 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1105 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1106 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1107 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1108 : 0)
1109
1110 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1111 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1112 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1113 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1114 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1115 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1116 && ((VAL) & 3) == 0) : \
1117 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1118 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1119 : 0)
1120
1121 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1122 (TARGET_ARM ? \
1123 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1124
1125 /* Constant letter 'G' for the FPU immediate constants.
1126 'H' means the same constant negated. */
1127 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1128 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1129 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1130
1131 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1132 (TARGET_ARM ? \
1133 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1134
1135 /* For the ARM, `Q' means that this is a memory operand that is just
1136 an offset from a register.
1137 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1138 address. This means that the symbol is in the text segment and can be
1139 accessed without using a load. */
1140
1141 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1142 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1143 (C) == 'R' ? (GET_CODE (OP) == MEM \
1144 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1145 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1146 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1147 : 0)
1148
1149 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1150 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1151 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1152
1153 #define EXTRA_CONSTRAINT(X, C) \
1154 (TARGET_ARM ? \
1155 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1156
1157 /* Given an rtx X being reloaded into a reg required to be
1158 in class CLASS, return the class of reg to actually use.
1159 In general this is just CLASS, but for the Thumb we prefer
1160 a LO_REGS class or a subset. */
1161 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1162 (TARGET_ARM ? (CLASS) : \
1163 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1164
1165 /* Must leave BASE_REGS reloads alone */
1166 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1167 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1168 ? ((true_regnum (X) == -1 ? LO_REGS \
1169 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1170 : NO_REGS)) \
1171 : NO_REGS)
1172
1173 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1174 ((CLASS) != LO_REGS \
1175 ? ((true_regnum (X) == -1 ? LO_REGS \
1176 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1177 : NO_REGS)) \
1178 : NO_REGS)
1179
1180 /* Return the register class of a scratch register needed to copy IN into
1181 or out of a register in CLASS in MODE. If it can be done directly,
1182 NO_REGS is returned. */
1183 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1184 (TARGET_ARM ? \
1185 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1186 ? GENERAL_REGS : NO_REGS) \
1187 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1188
1189 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1190 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1191 (TARGET_ARM ? \
1192 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1193 && (GET_CODE (X) == MEM \
1194 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1195 && true_regnum (X) == -1))) \
1196 ? GENERAL_REGS : NO_REGS) \
1197 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1198
1199 /* Try a machine-dependent way of reloading an illegitimate address
1200 operand. If we find one, push the reload and jump to WIN. This
1201 macro is used in only one place: `find_reloads_address' in reload.c.
1202
1203 For the ARM, we wish to handle large displacements off a base
1204 register by splitting the addend across a MOV and the mem insn.
1205 This can cut the number of reloads needed. */
1206 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1207 do \
1208 { \
1209 if (GET_CODE (X) == PLUS \
1210 && GET_CODE (XEXP (X, 0)) == REG \
1211 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1212 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1213 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1214 { \
1215 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1216 HOST_WIDE_INT low, high; \
1217 \
1218 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1219 low = ((val & 0xf) ^ 0x8) - 0x8; \
1220 else if (MODE == SImode \
1221 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1222 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1223 /* Need to be careful, -4096 is not a valid offset. */ \
1224 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1225 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1226 /* Need to be careful, -256 is not a valid offset. */ \
1227 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1228 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1229 && TARGET_HARD_FLOAT) \
1230 /* Need to be careful, -1024 is not a valid offset. */ \
1231 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1232 else \
1233 break; \
1234 \
1235 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1236 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1237 - (unsigned HOST_WIDE_INT) 0x80000000); \
1238 /* Check for overflow or zero */ \
1239 if (low == 0 || high == 0 || (high + low != val)) \
1240 break; \
1241 \
1242 /* Reload the high part into a base reg; leave the low part \
1243 in the mem. */ \
1244 X = gen_rtx_PLUS (GET_MODE (X), \
1245 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1246 GEN_INT (high)), \
1247 GEN_INT (low)); \
1248 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1249 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1250 VOIDmode, 0, 0, OPNUM, TYPE); \
1251 goto WIN; \
1252 } \
1253 } \
1254 while (0)
1255
1256 /* ??? If an HImode FP+large_offset address is converted to an HImode
1257 SP+large_offset address, then reload won't know how to fix it. It sees
1258 only that SP isn't valid for HImode, and so reloads the SP into an index
1259 register, but the resulting address is still invalid because the offset
1260 is too big. We fix it here instead by reloading the entire address. */
1261 /* We could probably achieve better results by defining PROMOTE_MODE to help
1262 cope with the variances between the Thumb's signed and unsigned byte and
1263 halfword load instructions. */
1264 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1265 { \
1266 if (GET_CODE (X) == PLUS \
1267 && GET_MODE_SIZE (MODE) < 4 \
1268 && GET_CODE (XEXP (X, 0)) == REG \
1269 && XEXP (X, 0) == stack_pointer_rtx \
1270 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1271 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1272 { \
1273 rtx orig_X = X; \
1274 X = copy_rtx (X); \
1275 push_reload (orig_X, NULL_RTX, &X, NULL, \
1276 MODE_BASE_REG_CLASS (MODE), \
1277 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1278 goto WIN; \
1279 } \
1280 }
1281
1282 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1283 if (TARGET_ARM) \
1284 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1285 else \
1286 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1287
1288 /* Return the maximum number of consecutive registers
1289 needed to represent mode MODE in a register of class CLASS.
1290 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1291 #define CLASS_MAX_NREGS(CLASS, MODE) \
1292 ((CLASS) == FPU_REGS ? 1 : ARM_NUM_REGS (MODE))
1293
1294 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1295 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1296 (TARGET_ARM ? \
1297 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1298 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1299 : \
1300 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1301 \f
1302 /* Stack layout; function entry, exit and calling. */
1303
1304 /* Define this if pushing a word on the stack
1305 makes the stack pointer a smaller address. */
1306 #define STACK_GROWS_DOWNWARD 1
1307
1308 /* Define this if the nominal address of the stack frame
1309 is at the high-address end of the local variables;
1310 that is, each additional local variable allocated
1311 goes at a more negative offset in the frame. */
1312 #define FRAME_GROWS_DOWNWARD 1
1313
1314 /* Offset within stack frame to start allocating local variables at.
1315 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1316 first local allocated. Otherwise, it is the offset to the BEGINNING
1317 of the first local allocated. */
1318 #define STARTING_FRAME_OFFSET 0
1319
1320 /* If we generate an insn to push BYTES bytes,
1321 this says how many the stack pointer really advances by. */
1322 /* The push insns do not do this rounding implicitly.
1323 So don't define this. */
1324 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1325
1326 /* Define this if the maximum size of all the outgoing args is to be
1327 accumulated and pushed during the prologue. The amount can be
1328 found in the variable current_function_outgoing_args_size. */
1329 #define ACCUMULATE_OUTGOING_ARGS 1
1330
1331 /* Offset of first parameter from the argument pointer register value. */
1332 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1333
1334 /* Value is the number of byte of arguments automatically
1335 popped when returning from a subroutine call.
1336 FUNDECL is the declaration node of the function (as a tree),
1337 FUNTYPE is the data type of the function (as a tree),
1338 or for a library call it is an identifier node for the subroutine name.
1339 SIZE is the number of bytes of arguments passed on the stack.
1340
1341 On the ARM, the caller does not pop any of its arguments that were passed
1342 on the stack. */
1343 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1344
1345 /* Define how to find the value returned by a library function
1346 assuming the value has mode MODE. */
1347 #define LIBCALL_VALUE(MODE) \
1348 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1349 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1350 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1351
1352 /* Define how to find the value returned by a function.
1353 VALTYPE is the data type of the value (as a tree).
1354 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1355 otherwise, FUNC is 0. */
1356 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1357 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1358
1359 /* 1 if N is a possible register number for a function value.
1360 On the ARM, only r0 and f0 can return results. */
1361 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1362 ((REGNO) == ARG_REGISTER (1) \
1363 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1364
1365 /* How large values are returned */
1366 /* A C expression which can inhibit the returning of certain function values
1367 in registers, based on the type of value. */
1368 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1369
1370 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1371 values must be in memory. On the ARM, they need only do so if larger
1372 than a word, or if they contain elements offset from zero in the struct. */
1373 #define DEFAULT_PCC_STRUCT_RETURN 0
1374
1375 /* Flags for the call/call_value rtl operations set up by function_arg. */
1376 #define CALL_NORMAL 0x00000000 /* No special processing. */
1377 #define CALL_LONG 0x00000001 /* Always call indirect. */
1378 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1379
1380 /* These bits describe the different types of function supported
1381 by the ARM backend. They are exclusive. ie a function cannot be both a
1382 normal function and an interworked function, for example. Knowing the
1383 type of a function is important for determining its prologue and
1384 epilogue sequences.
1385 Note value 7 is currently unassigned. Also note that the interrupt
1386 function types all have bit 2 set, so that they can be tested for easily.
1387 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1388 machine_function structure is initialized (to zero) func_type will
1389 default to unknown. This will force the first use of arm_current_func_type
1390 to call arm_compute_func_type. */
1391 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1392 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1393 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1394 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1395 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1396 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1397 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1398
1399 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1400
1401 /* In addition functions can have several type modifiers,
1402 outlined by these bit masks: */
1403 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1404 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1405 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1406 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1407
1408 /* Some macros to test these flags. */
1409 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1410 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1411 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1412 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1413 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1414
1415 /* A C structure for machine-specific, per-function data.
1416 This is added to the cfun structure. */
1417 typedef struct machine_function GTY(())
1418 {
1419 /* Additionsl stack adjustment in __builtin_eh_throw. */
1420 rtx eh_epilogue_sp_ofs;
1421 /* Records if LR has to be saved for far jumps. */
1422 int far_jump_used;
1423 /* Records if ARG_POINTER was ever live. */
1424 int arg_pointer_live;
1425 /* Records if the save of LR has been eliminated. */
1426 int lr_save_eliminated;
1427 /* The size of the stack frame. Only valid after reload. */
1428 int frame_size;
1429 /* Records the type of the current function. */
1430 unsigned long func_type;
1431 /* Record if the function has a variable argument list. */
1432 int uses_anonymous_args;
1433 }
1434 machine_function;
1435
1436 /* A C type for declaring a variable that is used as the first argument of
1437 `FUNCTION_ARG' and other related values. For some target machines, the
1438 type `int' suffices and can hold the number of bytes of argument so far. */
1439 typedef struct
1440 {
1441 /* This is the number of registers of arguments scanned so far. */
1442 int nregs;
1443 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1444 int call_cookie;
1445 } CUMULATIVE_ARGS;
1446
1447 /* Define where to put the arguments to a function.
1448 Value is zero to push the argument on the stack,
1449 or a hard register in which to store the argument.
1450
1451 MODE is the argument's machine mode.
1452 TYPE is the data type of the argument (as a tree).
1453 This is null for libcalls where that information may
1454 not be available.
1455 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1456 the preceding args and about the function being called.
1457 NAMED is nonzero if this argument is a named parameter
1458 (otherwise it is an extra parameter matching an ellipsis).
1459
1460 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1461 other arguments are passed on the stack. If (NAMED == 0) (which happens
1462 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1463 passed in the stack (function_prologue will indeed make it pass in the
1464 stack if necessary). */
1465 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1466 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1467
1468 /* For an arg passed partly in registers and partly in memory,
1469 this is the number of registers used.
1470 For args passed entirely in registers or entirely in memory, zero. */
1471 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1472 ( NUM_ARG_REGS > (CUM).nregs \
1473 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1474 ? NUM_ARG_REGS - (CUM).nregs : 0)
1475
1476 /* A C expression that indicates when an argument must be passed by
1477 reference. If nonzero for an argument, a copy of that argument is
1478 made in memory and a pointer to the argument is passed instead of
1479 the argument itself. The pointer is passed in whatever way is
1480 appropriate for passing a pointer to that type. */
1481 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1482 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1483
1484 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1485 for a call to a function whose data type is FNTYPE.
1486 For a library call, FNTYPE is 0.
1487 On the ARM, the offset starts at 0. */
1488 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1489 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1490
1491 /* Update the data in CUM to advance over an argument
1492 of mode MODE and data type TYPE.
1493 (TYPE is null for libcalls where that information may not be available.) */
1494 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1495 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1496
1497 /* 1 if N is a possible register number for function argument passing.
1498 On the ARM, r0-r3 are used to pass args. */
1499 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1500
1501 /* Implement `va_arg'. */
1502 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1503 arm_va_arg (valist, type)
1504
1505 \f
1506 /* Perform any actions needed for a function that is receiving a variable
1507 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1508 of the current parameter. PRETEND_SIZE is a variable that should be set to
1509 the amount of stack that must be pushed by the prolog to pretend that our
1510 caller pushed it.
1511
1512 Normally, this macro will push all remaining incoming registers on the
1513 stack and set PRETEND_SIZE to the length of the registers pushed.
1514
1515 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1516 named arg and all anonymous args onto the stack.
1517 XXX I know the prologue shouldn't be pushing registers, but it is faster
1518 that way. */
1519 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1520 { \
1521 cfun->machine->uses_anonymous_args = 1; \
1522 if ((CUM).nregs < NUM_ARG_REGS) \
1523 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1524 }
1525
1526 /* If your target environment doesn't prefix user functions with an
1527 underscore, you may wish to re-define this to prevent any conflicts.
1528 e.g. AOF may prefix mcount with an underscore. */
1529 #ifndef ARM_MCOUNT_NAME
1530 #define ARM_MCOUNT_NAME "*mcount"
1531 #endif
1532
1533 /* Call the function profiler with a given profile label. The Acorn
1534 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1535 On the ARM the full profile code will look like:
1536 .data
1537 LP1
1538 .word 0
1539 .text
1540 mov ip, lr
1541 bl mcount
1542 .word LP1
1543
1544 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1545 will output the .text section.
1546
1547 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1548 ``prof'' doesn't seem to mind about this!
1549
1550 Note - this version of the code is designed to work in both ARM and
1551 Thumb modes. */
1552 #ifndef ARM_FUNCTION_PROFILER
1553 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1554 { \
1555 char temp[20]; \
1556 rtx sym; \
1557 \
1558 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1559 IP_REGNUM, LR_REGNUM); \
1560 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1561 fputc ('\n', STREAM); \
1562 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1563 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1564 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1565 }
1566 #endif
1567
1568 #ifdef THUMB_FUNCTION_PROFILER
1569 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1570 if (TARGET_ARM) \
1571 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1572 else \
1573 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1574 #else
1575 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1576 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1577 #endif
1578
1579 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1580 the stack pointer does not matter. The value is tested only in
1581 functions that have frame pointers.
1582 No definition is equivalent to always zero.
1583
1584 On the ARM, the function epilogue recovers the stack pointer from the
1585 frame. */
1586 #define EXIT_IGNORE_STACK 1
1587
1588 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1589
1590 /* Determine if the epilogue should be output as RTL.
1591 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1592 #define USE_RETURN_INSN(ISCOND) \
1593 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1594
1595 /* Definitions for register eliminations.
1596
1597 This is an array of structures. Each structure initializes one pair
1598 of eliminable registers. The "from" register number is given first,
1599 followed by "to". Eliminations of the same "from" register are listed
1600 in order of preference.
1601
1602 We have two registers that can be eliminated on the ARM. First, the
1603 arg pointer register can often be eliminated in favor of the stack
1604 pointer register. Secondly, the pseudo frame pointer register can always
1605 be eliminated; it is replaced with either the stack or the real frame
1606 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1607 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1608
1609 #define ELIMINABLE_REGS \
1610 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1611 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1612 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1613 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1614 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1615 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1616 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1617
1618 /* Given FROM and TO register numbers, say whether this elimination is
1619 allowed. Frame pointer elimination is automatically handled.
1620
1621 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1622 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1623 pointer, we must eliminate FRAME_POINTER_REGNUM into
1624 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1625 ARG_POINTER_REGNUM. */
1626 #define CAN_ELIMINATE(FROM, TO) \
1627 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1628 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1629 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1630 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1631 1)
1632
1633 #define THUMB_REG_PUSHED_P(reg) \
1634 (regs_ever_live [reg] \
1635 && (! call_used_regs [reg] \
1636 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1637 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1638
1639 /* Define the offset between two registers, one to be eliminated, and the
1640 other its replacement, at the start of a routine. */
1641 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1642 do \
1643 { \
1644 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1645 } \
1646 while (0)
1647
1648 /* Note: This macro must match the code in thumb_function_prologue(). */
1649 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1650 { \
1651 (OFFSET) = 0; \
1652 if ((FROM) == ARG_POINTER_REGNUM) \
1653 { \
1654 int count_regs = 0; \
1655 int regno; \
1656 for (regno = 8; regno < 13; regno ++) \
1657 if (THUMB_REG_PUSHED_P (regno)) \
1658 count_regs ++; \
1659 if (count_regs) \
1660 (OFFSET) += 4 * count_regs; \
1661 count_regs = 0; \
1662 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1663 if (THUMB_REG_PUSHED_P (regno)) \
1664 count_regs ++; \
1665 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1666 (OFFSET) += 4 * (count_regs + 1); \
1667 if (TARGET_BACKTRACE) \
1668 { \
1669 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1670 (OFFSET) += 20; \
1671 else \
1672 (OFFSET) += 16; \
1673 } \
1674 } \
1675 if ((TO) == STACK_POINTER_REGNUM) \
1676 { \
1677 (OFFSET) += current_function_outgoing_args_size; \
1678 (OFFSET) += thumb_get_frame_size (); \
1679 } \
1680 }
1681
1682 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1683 if (TARGET_ARM) \
1684 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1685 else \
1686 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1687
1688 /* Special case handling of the location of arguments passed on the stack. */
1689 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1690
1691 /* Initialize data used by insn expanders. This is called from insn_emit,
1692 once for every function before code is generated. */
1693 #define INIT_EXPANDERS arm_init_expanders ()
1694
1695 /* Output assembler code for a block containing the constant parts
1696 of a trampoline, leaving space for the variable parts.
1697
1698 On the ARM, (if r8 is the static chain regnum, and remembering that
1699 referencing pc adds an offset of 8) the trampoline looks like:
1700 ldr r8, [pc, #0]
1701 ldr pc, [pc]
1702 .word static chain value
1703 .word function's address
1704 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1705 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1706 { \
1707 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1708 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1709 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1710 PC_REGNUM, PC_REGNUM); \
1711 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1712 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1713 }
1714
1715 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1716 Why - because it is easier. This code will always be branched to via
1717 a BX instruction and since the compiler magically generates the address
1718 of the function the linker has no opportunity to ensure that the
1719 bottom bit is set. Thus the processor will be in ARM mode when it
1720 reaches this code. So we duplicate the ARM trampoline code and add
1721 a switch into Thumb mode as well. */
1722 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1723 { \
1724 fprintf (FILE, "\t.code 32\n"); \
1725 fprintf (FILE, ".Ltrampoline_start:\n"); \
1726 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1727 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1728 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1729 IP_REGNUM, PC_REGNUM); \
1730 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1731 IP_REGNUM, IP_REGNUM); \
1732 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1733 fprintf (FILE, "\t.word\t0\n"); \
1734 fprintf (FILE, "\t.word\t0\n"); \
1735 fprintf (FILE, "\t.code 16\n"); \
1736 }
1737
1738 #define TRAMPOLINE_TEMPLATE(FILE) \
1739 if (TARGET_ARM) \
1740 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1741 else \
1742 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1743
1744 /* Length in units of the trampoline for entering a nested function. */
1745 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1746
1747 /* Alignment required for a trampoline in bits. */
1748 #define TRAMPOLINE_ALIGNMENT 32
1749
1750 /* Emit RTL insns to initialize the variable parts of a trampoline.
1751 FNADDR is an RTX for the address of the function's pure code.
1752 CXT is an RTX for the static chain value for the function. */
1753 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1754 { \
1755 emit_move_insn \
1756 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1757 emit_move_insn \
1758 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1759 }
1760
1761 \f
1762 /* Addressing modes, and classification of registers for them. */
1763 #define HAVE_POST_INCREMENT 1
1764 #define HAVE_PRE_INCREMENT TARGET_ARM
1765 #define HAVE_POST_DECREMENT TARGET_ARM
1766 #define HAVE_PRE_DECREMENT TARGET_ARM
1767 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
1768 #define HAVE_POST_MODIFY_DISP TARGET_ARM
1769 #define HAVE_PRE_MODIFY_REG TARGET_ARM
1770 #define HAVE_POST_MODIFY_REG TARGET_ARM
1771
1772 /* Macros to check register numbers against specific register classes. */
1773
1774 /* These assume that REGNO is a hard or pseudo reg number.
1775 They give nonzero only if REGNO is a hard reg of the suitable class
1776 or a pseudo reg currently allocated to a suitable hard reg.
1777 Since they use reg_renumber, they are safe only once reg_renumber
1778 has been allocated, which happens in local-alloc.c. */
1779 #define TEST_REGNO(R, TEST, VALUE) \
1780 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1781
1782 /* On the ARM, don't allow the pc to be used. */
1783 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1784 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1785 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1786 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1787
1788 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1789 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1790 || (GET_MODE_SIZE (MODE) >= 4 \
1791 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1792
1793 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1794 (TARGET_THUMB \
1795 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1796 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1797
1798 /* For ARM code, we don't care about the mode, but for Thumb, the index
1799 must be suitable for use in a QImode load. */
1800 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1801 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1802
1803 /* Maximum number of registers that can appear in a valid memory address.
1804 Shifts in addresses can't be by a register. */
1805 #define MAX_REGS_PER_ADDRESS 2
1806
1807 /* Recognize any constant value that is a valid address. */
1808 /* XXX We can address any constant, eventually... */
1809
1810 #ifdef AOF_ASSEMBLER
1811
1812 #define CONSTANT_ADDRESS_P(X) \
1813 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1814
1815 #else
1816
1817 #define CONSTANT_ADDRESS_P(X) \
1818 (GET_CODE (X) == SYMBOL_REF \
1819 && (CONSTANT_POOL_ADDRESS_P (X) \
1820 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1821
1822 #endif /* AOF_ASSEMBLER */
1823
1824 /* Nonzero if the constant value X is a legitimate general operand.
1825 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1826
1827 On the ARM, allow any integer (invalid ones are removed later by insn
1828 patterns), nice doubles and symbol_refs which refer to the function's
1829 constant pool XXX.
1830
1831 When generating pic allow anything. */
1832 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1833
1834 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1835 ( GET_CODE (X) == CONST_INT \
1836 || GET_CODE (X) == CONST_DOUBLE \
1837 || CONSTANT_ADDRESS_P (X) \
1838 || flag_pic)
1839
1840 #define LEGITIMATE_CONSTANT_P(X) \
1841 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1842
1843 /* Special characters prefixed to function names
1844 in order to encode attribute like information.
1845 Note, '@' and '*' have already been taken. */
1846 #define SHORT_CALL_FLAG_CHAR '^'
1847 #define LONG_CALL_FLAG_CHAR '#'
1848
1849 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1850 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1851
1852 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1853 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1854
1855 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1856 #define SUBTARGET_NAME_ENCODING_LENGTHS
1857 #endif
1858
1859 /* This is a C fragement for the inside of a switch statement.
1860 Each case label should return the number of characters to
1861 be stripped from the start of a function's name, if that
1862 name starts with the indicated character. */
1863 #define ARM_NAME_ENCODING_LENGTHS \
1864 case SHORT_CALL_FLAG_CHAR: return 1; \
1865 case LONG_CALL_FLAG_CHAR: return 1; \
1866 case '*': return 1; \
1867 SUBTARGET_NAME_ENCODING_LENGTHS
1868
1869 /* This is how to output a reference to a user-level label named NAME.
1870 `assemble_name' uses this. */
1871 #undef ASM_OUTPUT_LABELREF
1872 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1873 arm_asm_output_labelref (FILE, NAME)
1874
1875 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1876 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1877
1878 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1879 and check its validity for a certain class.
1880 We have two alternate definitions for each of them.
1881 The usual definition accepts all pseudo regs; the other rejects
1882 them unless they have been allocated suitable hard regs.
1883 The symbol REG_OK_STRICT causes the latter definition to be used. */
1884 #ifndef REG_OK_STRICT
1885
1886 #define ARM_REG_OK_FOR_BASE_P(X) \
1887 (REGNO (X) <= LAST_ARM_REGNUM \
1888 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1889 || REGNO (X) == FRAME_POINTER_REGNUM \
1890 || REGNO (X) == ARG_POINTER_REGNUM)
1891
1892 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1893 (REGNO (X) <= LAST_LO_REGNUM \
1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1895 || (GET_MODE_SIZE (MODE) >= 4 \
1896 && (REGNO (X) == STACK_POINTER_REGNUM \
1897 || (X) == hard_frame_pointer_rtx \
1898 || (X) == arg_pointer_rtx)))
1899
1900 #define REG_STRICT_P 0
1901
1902 #else /* REG_OK_STRICT */
1903
1904 #define ARM_REG_OK_FOR_BASE_P(X) \
1905 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1906
1907 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1908 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1909
1910 #define REG_STRICT_P 1
1911
1912 #endif /* REG_OK_STRICT */
1913
1914 /* Now define some helpers in terms of the above. */
1915
1916 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1917 (TARGET_THUMB \
1918 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1919 : ARM_REG_OK_FOR_BASE_P (X))
1920
1921 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1922
1923 /* For Thumb, a valid index register is anything that can be used in
1924 a byte load instruction. */
1925 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1926
1927 /* Nonzero if X is a hard reg that can be used as an index
1928 or if it is a pseudo reg. On the Thumb, the stack pointer
1929 is not suitable. */
1930 #define REG_OK_FOR_INDEX_P(X) \
1931 (TARGET_THUMB \
1932 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1933 : ARM_REG_OK_FOR_INDEX_P (X))
1934
1935 \f
1936 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1937 that is a valid memory address for an instruction.
1938 The MODE argument is the machine mode for the MEM expression
1939 that wants to use this address. */
1940
1941 #define ARM_BASE_REGISTER_RTX_P(X) \
1942 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
1943
1944 #define ARM_INDEX_REGISTER_RTX_P(X) \
1945 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
1946
1947 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
1948 { \
1949 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
1950 goto WIN; \
1951 }
1952
1953 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
1954 { \
1955 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
1956 goto WIN; \
1957 }
1958
1959 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1960 if (TARGET_ARM) \
1961 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
1962 else /* if (TARGET_THUMB) */ \
1963 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
1964
1965 \f
1966 /* Try machine-dependent ways of modifying an illegitimate address
1967 to be legitimate. If we find one, return the new, valid address.
1968 This macro is used in only one place: `memory_address' in explow.c.
1969
1970 OLDX is the address as it was before break_out_memory_refs was called.
1971 In some cases it is useful to look at this to decide what needs to be done.
1972
1973 MODE and WIN are passed so that this macro can use
1974 GO_IF_LEGITIMATE_ADDRESS.
1975
1976 It is always safe for this macro to do nothing. It exists to recognize
1977 opportunities to optimize the output.
1978
1979 On the ARM, try to convert [REG, #BIGCONST]
1980 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1981 where VALIDCONST == 0 in case of TImode. */
1982 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1983 { \
1984 if (GET_CODE (X) == PLUS) \
1985 { \
1986 rtx xop0 = XEXP (X, 0); \
1987 rtx xop1 = XEXP (X, 1); \
1988 \
1989 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1990 xop0 = force_reg (SImode, xop0); \
1991 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1992 xop1 = force_reg (SImode, xop1); \
1993 if (ARM_BASE_REGISTER_RTX_P (xop0) \
1994 && GET_CODE (xop1) == CONST_INT) \
1995 { \
1996 HOST_WIDE_INT n, low_n; \
1997 rtx base_reg, val; \
1998 n = INTVAL (xop1); \
1999 \
2000 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2001 { \
2002 low_n = n & 0x0f; \
2003 n &= ~0x0f; \
2004 if (low_n > 4) \
2005 { \
2006 n += 16; \
2007 low_n -= 16; \
2008 } \
2009 } \
2010 else \
2011 { \
2012 low_n = ((MODE) == TImode ? 0 \
2013 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2014 n -= low_n; \
2015 } \
2016 base_reg = gen_reg_rtx (SImode); \
2017 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2018 GEN_INT (n)), NULL_RTX); \
2019 emit_move_insn (base_reg, val); \
2020 (X) = (low_n == 0 ? base_reg \
2021 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2022 } \
2023 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2024 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2025 } \
2026 else if (GET_CODE (X) == MINUS) \
2027 { \
2028 rtx xop0 = XEXP (X, 0); \
2029 rtx xop1 = XEXP (X, 1); \
2030 \
2031 if (CONSTANT_P (xop0)) \
2032 xop0 = force_reg (SImode, xop0); \
2033 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2034 xop1 = force_reg (SImode, xop1); \
2035 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2036 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2037 } \
2038 if (flag_pic) \
2039 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2040 if (memory_address_p (MODE, X)) \
2041 goto WIN; \
2042 }
2043
2044 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2045 if (flag_pic) \
2046 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2047
2048 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2049 if (TARGET_ARM) \
2050 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2051 else \
2052 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2053
2054 /* Go to LABEL if ADDR (a legitimate address expression)
2055 has an effect that depends on the machine mode it is used for. */
2056 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2057 { \
2058 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2059 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2060 goto LABEL; \
2061 }
2062
2063 /* Nothing helpful to do for the Thumb */
2064 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2065 if (TARGET_ARM) \
2066 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2067 \f
2068
2069 /* Specify the machine mode that this machine uses
2070 for the index in the tablejump instruction. */
2071 #define CASE_VECTOR_MODE Pmode
2072
2073 /* Define as C expression which evaluates to nonzero if the tablejump
2074 instruction expects the table to contain offsets from the address of the
2075 table.
2076 Do not define this if the table should contain absolute addresses. */
2077 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2078
2079 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2080 unsigned is probably best, but may break some code. */
2081 #ifndef DEFAULT_SIGNED_CHAR
2082 #define DEFAULT_SIGNED_CHAR 0
2083 #endif
2084
2085 /* Don't cse the address of the function being compiled. */
2086 #define NO_RECURSIVE_FUNCTION_CSE 1
2087
2088 /* Max number of bytes we can move from memory to memory
2089 in one reasonably fast instruction. */
2090 #define MOVE_MAX 4
2091
2092 #undef MOVE_RATIO
2093 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2094
2095 /* Define if operations between registers always perform the operation
2096 on the full register even if a narrower mode is specified. */
2097 #define WORD_REGISTER_OPERATIONS
2098
2099 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2100 will either zero-extend or sign-extend. The value of this macro should
2101 be the code that says which one of the two operations is implicitly
2102 done, NIL if none. */
2103 #define LOAD_EXTEND_OP(MODE) \
2104 (TARGET_THUMB ? ZERO_EXTEND : \
2105 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2106 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2107
2108 /* Nonzero if access to memory by bytes is slow and undesirable. */
2109 #define SLOW_BYTE_ACCESS 0
2110
2111 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2112
2113 /* Immediate shift counts are truncated by the output routines (or was it
2114 the assembler?). Shift counts in a register are truncated by ARM. Note
2115 that the native compiler puts too large (> 32) immediate shift counts
2116 into a register and shifts by the register, letting the ARM decide what
2117 to do instead of doing that itself. */
2118 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2119 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2120 On the arm, Y in a register is used modulo 256 for the shift. Only for
2121 rotates is modulo 32 used. */
2122 /* #define SHIFT_COUNT_TRUNCATED 1 */
2123
2124 /* All integers have the same format so truncation is easy. */
2125 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2126
2127 /* Calling from registers is a massive pain. */
2128 #define NO_FUNCTION_CSE 1
2129
2130 /* Chars and shorts should be passed as ints. */
2131 #define PROMOTE_PROTOTYPES 1
2132
2133 /* The machine modes of pointers and functions */
2134 #define Pmode SImode
2135 #define FUNCTION_MODE Pmode
2136
2137 #define ARM_FRAME_RTX(X) \
2138 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2139 || (X) == arg_pointer_rtx)
2140
2141 /* Moves to and from memory are quite expensive */
2142 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2143 (TARGET_ARM ? 10 : \
2144 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2145 * (CLASS == LO_REGS ? 1 : 2)))
2146
2147 /* All address computations that can be done are free, but rtx cost returns
2148 the same for practically all of them. So we weight the different types
2149 of address here in the order (most pref first):
2150 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2151 #define ARM_ADDRESS_COST(X) \
2152 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2153 || GET_CODE (X) == SYMBOL_REF) \
2154 ? 0 \
2155 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2156 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2157 ? 10 \
2158 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2159 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2160 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2161 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2162 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2163 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2164 ? 1 : 0)) \
2165 : 4)))))
2166
2167 #define THUMB_ADDRESS_COST(X) \
2168 ((GET_CODE (X) == REG \
2169 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2170 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2171 ? 1 : 2)
2172
2173 #define ADDRESS_COST(X) \
2174 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2175
2176 /* Try to generate sequences that don't involve branches, we can then use
2177 conditional instructions */
2178 #define BRANCH_COST \
2179 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2180 \f
2181 /* Position Independent Code. */
2182 /* We decide which register to use based on the compilation options and
2183 the assembler in use; this is more general than the APCS restriction of
2184 using sb (r9) all the time. */
2185 extern int arm_pic_register;
2186
2187 /* Used when parsing command line option -mpic-register=. */
2188 extern const char * arm_pic_register_string;
2189
2190 /* The register number of the register used to address a table of static
2191 data addresses in memory. */
2192 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2193
2194 #define FINALIZE_PIC arm_finalize_pic (1)
2195
2196 /* We can't directly access anything that contains a symbol,
2197 nor can we indirect via the constant pool. */
2198 #define LEGITIMATE_PIC_OPERAND_P(X) \
2199 (!(symbol_mentioned_p (X) \
2200 || label_mentioned_p (X) \
2201 || (GET_CODE (X) == SYMBOL_REF \
2202 && CONSTANT_POOL_ADDRESS_P (X) \
2203 && (symbol_mentioned_p (get_pool_constant (X)) \
2204 || label_mentioned_p (get_pool_constant (X))))))
2205
2206 /* We need to know when we are making a constant pool; this determines
2207 whether data needs to be in the GOT or can be referenced via a GOT
2208 offset. */
2209 extern int making_const_table;
2210 \f
2211 /* Handle pragmas for compatibility with Intel's compilers. */
2212 #define REGISTER_TARGET_PRAGMAS() do { \
2213 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2214 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2215 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2216 } while (0)
2217
2218 /* Condition code information. */
2219 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2220 return the mode to be used for the comparison. */
2221
2222 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2223
2224 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2225
2226 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2227 do \
2228 { \
2229 if (GET_CODE (OP1) == CONST_INT \
2230 && ! (const_ok_for_arm (INTVAL (OP1)) \
2231 || (const_ok_for_arm (- INTVAL (OP1))))) \
2232 { \
2233 rtx const_op = OP1; \
2234 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2235 OP1 = const_op; \
2236 } \
2237 } \
2238 while (0)
2239
2240 #define STORE_FLAG_VALUE 1
2241
2242 \f
2243
2244 /* Gcc puts the pool in the wrong place for ARM, since we can only
2245 load addresses a limited distance around the pc. We do some
2246 special munging to move the constant pool values to the correct
2247 point in the code. */
2248 #define MACHINE_DEPENDENT_REORG(INSN) \
2249 arm_reorg (INSN); \
2250
2251 #undef ASM_APP_OFF
2252 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2253
2254 /* Output a push or a pop instruction (only used when profiling). */
2255 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2256 if (TARGET_ARM) \
2257 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2258 STACK_POINTER_REGNUM, REGNO); \
2259 else \
2260 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2261
2262
2263 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2264 if (TARGET_ARM) \
2265 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2266 STACK_POINTER_REGNUM, REGNO); \
2267 else \
2268 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2269
2270 /* This is how to output a label which precedes a jumptable. Since
2271 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2272 #undef ASM_OUTPUT_CASE_LABEL
2273 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2274 do \
2275 { \
2276 if (TARGET_THUMB) \
2277 ASM_OUTPUT_ALIGN (FILE, 2); \
2278 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2279 } \
2280 while (0)
2281
2282 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2283 do \
2284 { \
2285 if (TARGET_THUMB) \
2286 { \
2287 if (is_called_in_ARM_mode (DECL)) \
2288 fprintf (STREAM, "\t.code 32\n") ; \
2289 else \
2290 fprintf (STREAM, "\t.thumb_func\n") ; \
2291 } \
2292 if (TARGET_POKE_FUNCTION_NAME) \
2293 arm_poke_function_name (STREAM, (char *) NAME); \
2294 } \
2295 while (0)
2296
2297 /* For aliases of functions we use .thumb_set instead. */
2298 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2299 do \
2300 { \
2301 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2302 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2303 \
2304 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2305 { \
2306 fprintf (FILE, "\t.thumb_set "); \
2307 assemble_name (FILE, LABEL1); \
2308 fprintf (FILE, ","); \
2309 assemble_name (FILE, LABEL2); \
2310 fprintf (FILE, "\n"); \
2311 } \
2312 else \
2313 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2314 } \
2315 while (0)
2316
2317 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2318 /* To support -falign-* switches we need to use .p2align so
2319 that alignment directives in code sections will be padded
2320 with no-op instructions, rather than zeroes. */
2321 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2322 if ((LOG) != 0) \
2323 { \
2324 if ((MAX_SKIP) == 0) \
2325 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2326 else \
2327 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2328 (LOG), (MAX_SKIP)); \
2329 }
2330 #endif
2331 \f
2332 /* Only perform branch elimination (by making instructions conditional) if
2333 we're optimising. Otherwise it's of no use anyway. */
2334 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2335 if (TARGET_ARM && optimize) \
2336 arm_final_prescan_insn (INSN); \
2337 else if (TARGET_THUMB) \
2338 thumb_final_prescan_insn (INSN)
2339
2340 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2341 (CODE == '@' || CODE == '|' \
2342 || (TARGET_ARM && (CODE == '?')) \
2343 || (TARGET_THUMB && (CODE == '_')))
2344
2345 /* Output an operand of an instruction. */
2346 #define PRINT_OPERAND(STREAM, X, CODE) \
2347 arm_print_operand (STREAM, X, CODE)
2348
2349 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2350 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2351 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2352 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2353 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2354 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2355 : 0))))
2356
2357 /* Output the address of an operand. */
2358 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2359 { \
2360 int is_minus = GET_CODE (X) == MINUS; \
2361 \
2362 if (GET_CODE (X) == REG) \
2363 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2364 else if (GET_CODE (X) == PLUS || is_minus) \
2365 { \
2366 rtx base = XEXP (X, 0); \
2367 rtx index = XEXP (X, 1); \
2368 HOST_WIDE_INT offset = 0; \
2369 if (GET_CODE (base) != REG) \
2370 { \
2371 /* Ensure that BASE is a register */ \
2372 /* (one of them must be). */ \
2373 rtx temp = base; \
2374 base = index; \
2375 index = temp; \
2376 } \
2377 switch (GET_CODE (index)) \
2378 { \
2379 case CONST_INT: \
2380 offset = INTVAL (index); \
2381 if (is_minus) \
2382 offset = -offset; \
2383 asm_fprintf (STREAM, "[%r, #%d]", \
2384 REGNO (base), offset); \
2385 break; \
2386 \
2387 case REG: \
2388 asm_fprintf (STREAM, "[%r, %s%r]", \
2389 REGNO (base), is_minus ? "-" : "", \
2390 REGNO (index)); \
2391 break; \
2392 \
2393 case MULT: \
2394 case ASHIFTRT: \
2395 case LSHIFTRT: \
2396 case ASHIFT: \
2397 case ROTATERT: \
2398 { \
2399 asm_fprintf (STREAM, "[%r, %s%r", \
2400 REGNO (base), is_minus ? "-" : "", \
2401 REGNO (XEXP (index, 0))); \
2402 arm_print_operand (STREAM, index, 'S'); \
2403 fputs ("]", STREAM); \
2404 break; \
2405 } \
2406 \
2407 default: \
2408 abort(); \
2409 } \
2410 } \
2411 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2412 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2413 { \
2414 extern enum machine_mode output_memory_reference_mode; \
2415 \
2416 if (GET_CODE (XEXP (X, 0)) != REG) \
2417 abort (); \
2418 \
2419 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2420 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2421 REGNO (XEXP (X, 0)), \
2422 GET_CODE (X) == PRE_DEC ? "-" : "", \
2423 GET_MODE_SIZE (output_memory_reference_mode)); \
2424 else \
2425 asm_fprintf (STREAM, "[%r], #%s%d", \
2426 REGNO (XEXP (X, 0)), \
2427 GET_CODE (X) == POST_DEC ? "-" : "", \
2428 GET_MODE_SIZE (output_memory_reference_mode)); \
2429 } \
2430 else if (GET_CODE (X) == PRE_MODIFY) \
2431 { \
2432 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2433 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2434 asm_fprintf (STREAM, "#%d]!", \
2435 INTVAL (XEXP (XEXP (X, 1), 1))); \
2436 else \
2437 asm_fprintf (STREAM, "%r]!", \
2438 REGNO (XEXP (XEXP (X, 1), 1))); \
2439 } \
2440 else if (GET_CODE (X) == POST_MODIFY) \
2441 { \
2442 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2443 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2444 asm_fprintf (STREAM, "#%d", \
2445 INTVAL (XEXP (XEXP (X, 1), 1))); \
2446 else \
2447 asm_fprintf (STREAM, "%r", \
2448 REGNO (XEXP (XEXP (X, 1), 1))); \
2449 } \
2450 else output_addr_const (STREAM, X); \
2451 }
2452
2453 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2454 { \
2455 if (GET_CODE (X) == REG) \
2456 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2457 else if (GET_CODE (X) == POST_INC) \
2458 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2459 else if (GET_CODE (X) == PLUS) \
2460 { \
2461 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2462 asm_fprintf (STREAM, "[%r, #%d]", \
2463 REGNO (XEXP (X, 0)), \
2464 (int) INTVAL (XEXP (X, 1))); \
2465 else \
2466 asm_fprintf (STREAM, "[%r, %r]", \
2467 REGNO (XEXP (X, 0)), \
2468 REGNO (XEXP (X, 1))); \
2469 } \
2470 else \
2471 output_addr_const (STREAM, X); \
2472 }
2473
2474 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2475 if (TARGET_ARM) \
2476 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2477 else \
2478 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2479
2480 /* A C expression whose value is RTL representing the value of the return
2481 address for the frame COUNT steps up from the current frame. */
2482
2483 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2484 arm_return_addr (COUNT, FRAME)
2485
2486 /* Mask of the bits in the PC that contain the real return address
2487 when running in 26-bit mode. */
2488 #define RETURN_ADDR_MASK26 (0x03fffffc)
2489
2490 /* Pick up the return address upon entry to a procedure. Used for
2491 dwarf2 unwind information. This also enables the table driven
2492 mechanism. */
2493 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2494 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2495
2496 /* Used to mask out junk bits from the return address, such as
2497 processor state, interrupt status, condition codes and the like. */
2498 #define MASK_RETURN_ADDR \
2499 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2500 in 26 bit mode, the condition codes must be masked out of the \
2501 return address. This does not apply to ARM6 and later processors \
2502 when running in 32 bit mode. */ \
2503 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2504 : (arm_arch4 || TARGET_THUMB) ? \
2505 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2506 : arm_gen_return_addr_mask ())
2507
2508 \f
2509 /* Define the codes that are matched by predicates in arm.c */
2510 #define PREDICATE_CODES \
2511 {"s_register_operand", {SUBREG, REG}}, \
2512 {"arm_hard_register_operand", {REG}}, \
2513 {"f_register_operand", {SUBREG, REG}}, \
2514 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2515 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2516 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2517 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2518 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2519 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2520 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2521 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2522 {"offsettable_memory_operand", {MEM}}, \
2523 {"bad_signed_byte_operand", {MEM}}, \
2524 {"alignable_memory_operand", {MEM}}, \
2525 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2526 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2527 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2528 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2529 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2530 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2531 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2532 {"load_multiple_operation", {PARALLEL}}, \
2533 {"store_multiple_operation", {PARALLEL}}, \
2534 {"equality_operator", {EQ, NE}}, \
2535 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2536 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2537 UNGE, UNGT}}, \
2538 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2539 {"const_shift_operand", {CONST_INT}}, \
2540 {"multi_register_push", {PARALLEL}}, \
2541 {"cc_register", {REG}}, \
2542 {"logical_binary_operator", {AND, IOR, XOR}}, \
2543 {"dominant_cc_register", {REG}},
2544
2545 /* Define this if you have special predicates that know special things
2546 about modes. Genrecog will warn about certain forms of
2547 match_operand without a mode; if the operand predicate is listed in
2548 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2549 #define SPECIAL_MODE_PREDICATES \
2550 "cc_register", "dominant_cc_register",
2551
2552 enum arm_builtins
2553 {
2554 ARM_BUILTIN_CLZ,
2555 ARM_BUILTIN_MAX
2556 };
2557 #endif /* ! GCC_ARM_H */
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