| blob | 557fb09878c0c2f4c7827a55e4953ebf77878b71 |
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-6, 1997 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
37 /* MIPS external variables defined in mips.c. */
39 /* comparison type */
45 CMP_MAX /* max comparison type */
46 };
48 /* types of delay slot */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 };
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
62 PROCESSOR_DEFAULT,
63 PROCESSOR_R3000,
64 PROCESSOR_R3900,
65 PROCESSOR_R6000,
66 PROCESSOR_R4000,
67 PROCESSOR_R4100,
68 PROCESSOR_R4300,
69 PROCESSOR_R4600,
70 PROCESSOR_R4650,
71 PROCESSOR_R5000,
72 PROCESSOR_R8000
73 };
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. This is only used by the Irix 6 port currently. */
81 ABI_32,
82 ABI_N32,
83 ABI_64,
84 ABI_EABI
85 };
87 #ifndef MIPS_ABI_DEFAULT
88 /* We define this away so that there is no extra runtime cost if the target
89 doesn't support multiple ABIs. */
90 #define mips_abi ABI_32
91 #else
93 #endif
95 /* Whether to emit abicalls code sequences or not. */
98 MIPS_ABICALLS_NO,
99 MIPS_ABICALLS_YES
100 };
102 /* Recast the abicalls class to be the abicalls attribute. */
103 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
105 /* Which type of block move to do (whether or not the last store is
106 split out so it can fill a branch delay slot). */
111 BLOCK_MOVE_LAST /* generate just the last store */
112 };
154 /* Functions within mips.c that we reference. */
209 /* Recognition functions that return if a condition is true. */
230 /* Functions to change what output section we are using. */
237 /* Stubs for half-pic support if not OSF/1 reference platform. */
239 #ifndef HALF_PIC_P
240 #define HALF_PIC_P() 0
241 #define HALF_PIC_NUMBER_PTRS 0
242 #define HALF_PIC_NUMBER_REFS 0
243 #define HALF_PIC_ENCODE(DECL)
244 #define HALF_PIC_DECLARE(NAME)
246 #define HALF_PIC_ADDRESS_P(X) 0
247 #define HALF_PIC_PTR(X) X
248 #define HALF_PIC_FINISH(STREAM)
249 #endif
251 \f
252 /* Run-time compilation parameters selecting different hardware subsets. */
254 /* Macros used in the machine description to test the flags. */
256 /* Bits for real switches */
279 /* Dummy switches used only in spec's*/
282 /* Debug switches, not documented */
294 /* r4000 64 bit sizes */
295 #define TARGET_INT64 (target_flags & MASK_INT64)
296 #define TARGET_LONG64 (target_flags & MASK_LONG64)
297 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
298 #define TARGET_64BIT (target_flags & MASK_64BIT)
300 /* Mips vs. GNU linker */
301 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
303 /* generate mips 3900 insns */
304 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
306 /* Mips vs. GNU assembler */
307 #define TARGET_GAS (target_flags & MASK_GAS)
308 #define TARGET_UNIX_ASM (!TARGET_GAS)
309 #define TARGET_MIPS_AS TARGET_UNIX_ASM
311 /* Debug Mode */
312 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
313 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
314 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
315 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
316 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
317 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
318 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
319 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
320 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
321 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
323 /* Reg. Naming in .s ($21 vs. $a0) */
324 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
326 /* Optimize for Sdata/Sbss */
327 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
329 /* print program statistics */
330 #define TARGET_STATS (target_flags & MASK_STATS)
332 /* call memcpy instead of inline code */
333 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
335 /* .abicalls, etc from Pyramid V.4 */
336 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
338 /* OSF pic references to externs */
339 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
341 /* software floating point */
342 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
343 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
345 /* always call through a register */
346 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
348 /* generate embedded PIC code;
349 requires gas. */
350 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
352 /* for embedded systems, optimize for
353 reduced RAM space instead of for
354 fastest code. */
355 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
357 /* generate big endian code. */
358 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
360 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
361 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
363 #define TARGET_MAD (target_flags & MASK_MAD)
365 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
367 /* This is true if we must enable the assembly language file switching
368 code. */
370 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
372 /* We must disable the function end stabs when doing the file switching trick,
373 because the Lscope stabs end up in the wrong place, making it impossible
374 to debug the resulting code. */
375 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
377 /* Macro to define tables used to set the flags.
378 This is a list in braces of pairs in braces,
379 each pair being { "NAME", VALUE }
380 where VALUE is the bits to set or minus the bits to clear.
381 An empty string NAME is used to identify the default VALUE. */
383 #define TARGET_SWITCHES \
384 { \
440 | TARGET_CPU_DEFAULT \
441 | TARGET_ENDIAN_DEFAULT)} \
442 }
444 /* Default target_flags if no switches are specified */
446 #ifndef TARGET_DEFAULT
447 #define TARGET_DEFAULT 0
448 #endif
450 #ifndef TARGET_CPU_DEFAULT
451 #define TARGET_CPU_DEFAULT 0
452 #endif
454 #ifndef TARGET_ENDIAN_DEFAULT
455 #ifndef DECSTATION
456 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
457 #else
458 #define TARGET_ENDIAN_DEFAULT 0
459 #endif
460 #endif
462 #ifndef MULTILIB_DEFAULTS
463 #if TARGET_ENDIAN_DEFAULT == 0
465 #else
467 #endif
468 #endif
470 /* We must pass -EL to the linker by default for little endian embedded
471 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
472 linker will default to using big-endian output files. The OUTPUT_FORMAT
473 line must be in the linker script, otherwise -EB/-EL will not work. */
475 #ifndef LINKER_ENDIAN_SPEC
476 #if TARGET_ENDIAN_DEFAULT == 0
478 #else
480 #endif
481 #endif
483 /* This macro is similar to `TARGET_SWITCHES' but defines names of
484 command options that have values. Its definition is an
485 initializer with a subgrouping for each command option.
487 Each subgrouping contains a string constant, that defines the
488 fixed part of the option name, and the address of a variable.
489 The variable, type `char *', is set to the variable part of the
490 given option if the fixed part matches. The actual option name
491 is made by appending `-m' to the specified name.
493 Here is an example which defines `-mshort-data-NUMBER'. If the
494 given option is `-mshort-data-512', the variable `m88k_short_data'
495 will be set to the string `"512"'.
497 extern char *m88k_short_data;
498 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
500 #define TARGET_OPTIONS \
501 { \
502 SUBTARGET_TARGET_OPTIONS \
505 }
507 /* This is meant to be redefined in the host dependent files. */
508 #define SUBTARGET_TARGET_OPTIONS
510 #define GENERATE_BRANCHLIKELY (TARGET_MIPS3900 || (mips_isa >= 2))
511 #define GENERATE_MULT3 (TARGET_MIPS3900)
512 #define GENERATE_MADD (TARGET_MIPS3900)
516 /* Macros to decide whether certain features are available or not,
517 depending on the instruction set architecture level. */
519 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
520 #define HAVE_SQRT_P() (mips_isa >= 2)
522 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
523 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
524 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
525 target_flags, and -mgp64 sets MASK_64BIT.
527 Setting MASK_64BIT in target_flags will cause gcc to assume that
528 registers are 64 bits wide. int, long and void * will be 32 bit;
529 this may be changed with -mint64 or -mlong64.
531 The gen* programs link code that refers to MASK_64BIT. They don't
532 actually use the information in target_flags; they just refer to
533 it. */
534 \f
535 /* Switch Recognition by gcc.c. Add -G xx support */
537 #ifdef SWITCH_TAKES_ARG
538 #undef SWITCH_TAKES_ARG
539 #endif
541 #define SWITCH_TAKES_ARG(CHAR) \
544 /* Sometimes certain combinations of command options do not make sense
545 on a particular target machine. You can define a macro
546 `OVERRIDE_OPTIONS' to take account of this. This macro, if
547 defined, is executed once just after all the command options have
548 been parsed.
550 On the MIPS, it is used to handle -G. We also use it to set up all
551 of the tables referenced in the other macros. */
553 #define OVERRIDE_OPTIONS override_options ()
555 /* Zero or more C statements that may conditionally modify two
556 variables `fixed_regs' and `call_used_regs' (both of type `char
557 []') after they have been initialized from the two preceding
558 macros.
560 This is necessary in case the fixed or call-clobbered registers
561 depend on target flags.
563 You need not define this macro if it has no work to do.
565 If the usage of an entire class of registers depends on the target
566 flags, you may indicate this to GCC by using this macro to modify
567 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
568 the classes which should not be used by GCC. Also define the macro
569 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
570 letter for a class that shouldn't be used.
572 (However, if this class is not included in `GENERAL_REGS' and all
573 of the insn patterns whose constraints permit this class are
574 controlled by target switches, then GCC will automatically avoid
575 using these registers when the target switches are opposed to
576 them.) */
578 #define CONDITIONAL_REGISTER_USAGE \
579 do \
580 { \
581 if (!TARGET_HARD_FLOAT) \
582 { \
583 int regno; \
584 \
585 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
586 fixed_regs[regno] = call_used_regs[regno] = 1; \
587 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
588 fixed_regs[regno] = call_used_regs[regno] = 1; \
589 } \
590 else if (mips_isa < 4) \
591 { \
592 int regno; \
593 \
594 /* We only have a single condition code register. We \
595 implement this by hiding all the condition code registers, \
597 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
598 fixed_regs[regno] = call_used_regs[regno] = 1; \
599 } \
600 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
601 } \
602 while (0)
604 /* This is meant to be redefined in the host dependent files. */
605 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
607 /* Show we can debug even without a frame pointer. */
608 #define CAN_DEBUG_WITHOUT_FP
609 \f
610 /* Complain about missing specs and predefines that should be defined in each
611 of the target tm files to override the defaults. This is mostly a place-
612 holder until I can get each of the files updated [mm]. */
614 #if defined(OSF_OS) \
615 || defined(DECSTATION) \
616 || defined(SGI_TARGET) \
617 || defined(MIPS_NEWS) \
618 || defined(MIPS_SYSV) \
619 || defined(MIPS_SVR4) \
620 || defined(MIPS_BSD43)
622 #ifndef CPP_PREDEFINES
624 #endif
626 #ifndef LIB_SPEC
628 #endif
630 #ifndef STARTFILE_SPEC
632 #endif
634 #ifndef MACHINE_TYPE
636 #endif
637 #endif
639 /* Tell collect what flags to pass to nm. */
640 #ifndef NM_FLAGS
642 #endif
644 \f
645 /* Names to predefine in the preprocessor for this target machine. */
647 #ifndef CPP_PREDEFINES
649 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
650 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
651 #endif
653 /* Assembler specs. */
655 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
656 than gas. */
659 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
660 %{pipe: %e-pipe is not supported.} \
661 %{K} %(subtarget_mips_as_asm_spec)"
663 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
664 rather than gas. It may be overridden by subtargets. */
666 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
668 #endif
670 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
671 assembler. */
675 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
676 GAS_ASM_SPEC as the default, depending upon the value of
677 TARGET_DEFAULT. */
679 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
680 /* GAS */
683 %{mmips-as: %(mips_as_asm_spec)} \
684 %{!mmips-as: %(gas_asm_spec)}"
689 %{!mgas: %(mips_as_asm_spec)} \
690 %{mgas: %(gas_asm_spec)}"
694 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
695 to the assembler. It may be overridden by subtargets. */
696 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
698 %{noasmopt:-O0} \
699 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
700 #endif
702 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
703 the assembler. It may be overridden by subtargets. */
704 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
706 %{g} %{g0} %{g1} %{g2} %{g3} \
707 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
708 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
709 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
710 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
711 #endif
713 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
714 overridden by subtargets. */
716 #ifndef SUBTARGET_ASM_SPEC
718 #endif
720 /* ASM_SPEC is the set of arguments to pass to the assembler. */
723 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
724 %(subtarget_asm_optimizing_spec) \
725 %(subtarget_asm_debugging_spec) \
726 %{membedded-pic} \
727 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
728 %(target_asm_spec) \
729 %(subtarget_asm_spec)"
731 /* Specify to run a post-processor, mips-tfile after the assembler
732 has run to stuff the mips debug information into the object file.
733 This is needed because the $#!%^ MIPS assembler provides no way
734 of specifying such information in the assembly file. If we are
735 cross compiling, disable mips-tfile unless the user specifies
736 -mmips-tfile. */
738 #ifndef ASM_FINAL_SPEC
739 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
740 /* GAS */
742 %{mmips-as: %{!mno-mips-tfile: \
744 %{K: -I %b.o~} \
745 %{!K: %{save-temps: -I %b.o~}} \
746 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
747 %{.s:%i} %{!.s:%g.s}}}"
749 #else
750 /* not GAS */
752 %{!mgas: %{!mno-mips-tfile: \
754 %{K: -I %b.o~} \
755 %{!K: %{save-temps: -I %b.o~}} \
756 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
757 %{.s:%i} %{!.s:%g.s}}}"
759 #endif
762 /* Redefinition of libraries used. Mips doesn't support normal
763 UNIX style profiling via calling _mcount. It does offer
764 profiling that samples the PC, so do what we can... */
766 #ifndef LIB_SPEC
768 #endif
770 /* Extra switches sometimes passed to the linker. */
771 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
772 will interpret it as a -b option. */
774 #ifndef LINK_SPEC
776 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
777 %{bestGnum} %{shared} %{non_shared} \
778 %(linker_endian_spec)"
781 /* Specs for the compiler proper */
783 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
784 overridden by subtargets. */
785 #ifndef SUBTARGET_CC1_SPEC
787 #endif
789 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
791 #ifndef CC1_SPEC
793 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
794 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
795 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
796 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
797 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
798 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
799 %{m4650:-mcpu=r4650} \
800 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
801 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
802 %{pic-none: -mno-half-pic} \
803 %{pic-lib: -mhalf-pic} \
804 %{pic-extern: -mhalf-pic} \
805 %{pic-calls: -mhalf-pic} \
806 %{save-temps: } \
807 %(subtarget_cc1_spec) "
808 #endif
810 /* Preprocessor specs. */
812 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
813 be overridden by subtargets. */
815 #ifndef SUBTARGET_CPP_SIZE_SPEC
819 #endif
821 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
822 overridden by subtargets. */
823 #ifndef SUBTARGET_CPP_SPEC
825 #endif
827 /* If we're using 64bit longs, then we have to define __LONG_MAX__
828 correctly. Similarly for 64bit ints and __INT_MAX__. */
829 #ifndef LONG_MAX_SPEC
830 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
832 #else
834 #endif
835 #endif
837 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
839 #ifndef CPP_SPEC
841 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
842 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
843 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
844 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
845 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
846 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
847 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
848 %(subtarget_cpp_size_spec) \
849 %{mips3:-U__mips -D__mips=3 -D__mips64} \
850 %{mips4:-U__mips -D__mips=4 -D__mips64} \
851 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
852 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
853 %{m4650:%{!msoft-float:-D__mips_single_float}} \
854 %{msoft-float:-D__mips_soft_float} \
855 %{mabi=eabi:-D__mips_eabi} \
856 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
857 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
858 %(long_max_spec) \
859 %(subtarget_cpp_spec) "
860 #endif
862 /* This macro defines names of additional specifications to put in the specs
863 that can be used in various specifications like CC1_SPEC. Its definition
864 is an initializer with a subgrouping for each command option.
866 Each subgrouping contains a string constant, that defines the
867 specification name, and a string constant that used by the GNU CC driver
868 program.
870 Do not define this macro if it does not need to do anything. */
872 #define EXTRA_SPECS \
885 SUBTARGET_EXTRA_SPECS
887 #ifndef SUBTARGET_EXTRA_SPECS
888 #define SUBTARGET_EXTRA_SPECS
889 #endif
891 /* If defined, this macro is an additional prefix to try after
892 `STANDARD_EXEC_PREFIX'. */
894 #ifndef MD_EXEC_PREFIX
896 #endif
898 #ifndef MD_STARTFILE_PREFIX
900 #endif
902 \f
903 /* Print subsidiary information on the compiler version in use. */
907 #ifndef MACHINE_TYPE
909 #endif
911 #ifndef TARGET_VERSION_INTERNAL
912 #define TARGET_VERSION_INTERNAL(STREAM) \
914 #endif
916 #ifndef TARGET_VERSION
917 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
918 #endif
920 \f
926 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
927 #endif
929 /* By default, turn on GDB extensions. */
930 #define DEFAULT_GDB_EXTENSIONS 1
932 /* If we are passing smuggling stabs through the MIPS ECOFF object
933 format, put a comment in front of the .stab<x> operation so
934 that the MIPS assembler does not choke. The mips-tfile program
935 will correctly put the stab into the object file. */
941 /* Local compiler-generated symbols must have a prefix that the assembler
942 understands. By default, this is $, although some targets (e.g.,
943 NetBSD-ELF) need to override this. */
945 #ifndef LOCAL_LABEL_PREFIX
947 #endif
949 /* By default on the mips, external symbols do not have an underscore
950 prepended, but some targets (e.g., NetBSD) require this. */
952 #ifndef USER_LABEL_PREFIX
954 #endif
956 /* Forward references to tags are allowed. */
957 #define SDB_ALLOW_FORWARD_REFERENCES
959 /* Unknown tags are also allowed. */
960 #define SDB_ALLOW_UNKNOWN_REFERENCES
962 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
963 since the length can run past this up to a continuation point. */
964 #define DBX_CONTIN_LENGTH 1500
966 /* How to renumber registers for dbx and gdb. */
967 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
969 /* The mapping from gcc register number to DWARF 2 CFA column number.
970 This mapping does not allow for tracking register 0, since SGI's broken
971 dwarf reader thinks column 0 is used for the frame address, but since
972 register 0 is fixed this is not a problem. */
973 #define DWARF_FRAME_REGNUM(REG) \
974 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
976 /* The DWARF 2 CFA column which tracks the return address. */
977 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
979 /* Before the prologue, RA lives in r31. */
980 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
982 /* Overrides for the COFF debug format. */
983 #define PUT_SDB_SCL(a) \
984 do { \
985 extern FILE *asm_out_text_file; \
987 } while (0)
989 #define PUT_SDB_INT_VAL(a) \
990 do { \
991 extern FILE *asm_out_text_file; \
993 } while (0)
995 #define PUT_SDB_VAL(a) \
996 do { \
997 extern FILE *asm_out_text_file; \
999 output_addr_const (asm_out_text_file, (a)); \
1001 } while (0)
1003 #define PUT_SDB_DEF(a) \
1004 do { \
1005 extern FILE *asm_out_text_file; \
1008 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1010 } while (0)
1012 #define PUT_SDB_PLAIN_DEF(a) \
1013 do { \
1014 extern FILE *asm_out_text_file; \
1017 } while (0)
1019 #define PUT_SDB_ENDEF \
1020 do { \
1021 extern FILE *asm_out_text_file; \
1023 } while (0)
1025 #define PUT_SDB_TYPE(a) \
1026 do { \
1027 extern FILE *asm_out_text_file; \
1029 } while (0)
1031 #define PUT_SDB_SIZE(a) \
1032 do { \
1033 extern FILE *asm_out_text_file; \
1035 } while (0)
1037 #define PUT_SDB_DIM(a) \
1038 do { \
1039 extern FILE *asm_out_text_file; \
1041 } while (0)
1043 #ifndef PUT_SDB_START_DIM
1044 #define PUT_SDB_START_DIM \
1045 do { \
1046 extern FILE *asm_out_text_file; \
1048 } while (0)
1049 #endif
1051 #ifndef PUT_SDB_NEXT_DIM
1052 #define PUT_SDB_NEXT_DIM(a) \
1053 do { \
1054 extern FILE *asm_out_text_file; \
1056 } while (0)
1057 #endif
1059 #ifndef PUT_SDB_LAST_DIM
1060 #define PUT_SDB_LAST_DIM(a) \
1061 do { \
1062 extern FILE *asm_out_text_file; \
1064 } while (0)
1065 #endif
1067 #define PUT_SDB_TAG(a) \
1068 do { \
1069 extern FILE *asm_out_text_file; \
1071 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1073 } while (0)
1075 /* For block start and end, we create labels, so that
1076 later we can figure out where the correct offset is.
1077 The normal .ent/.end serve well enough for functions,
1078 so those are just commented out. */
1080 #define PUT_SDB_BLOCK_START(LINE) \
1081 do { \
1082 extern FILE *asm_out_text_file; \
1083 fprintf (asm_out_text_file, \
1085 LOCAL_LABEL_PREFIX, \
1086 sdb_label_count, \
1088 LOCAL_LABEL_PREFIX, \
1089 sdb_label_count, \
1090 (LINE)); \
1091 sdb_label_count++; \
1092 } while (0)
1094 #define PUT_SDB_BLOCK_END(LINE) \
1095 do { \
1096 extern FILE *asm_out_text_file; \
1097 fprintf (asm_out_text_file, \
1099 LOCAL_LABEL_PREFIX, \
1100 sdb_label_count, \
1102 LOCAL_LABEL_PREFIX, \
1103 sdb_label_count, \
1104 (LINE)); \
1105 sdb_label_count++; \
1106 } while (0)
1108 #define PUT_SDB_FUNCTION_START(LINE)
1110 #define PUT_SDB_FUNCTION_END(LINE) \
1111 do { \
1112 extern FILE *asm_out_text_file; \
1113 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1114 } while (0)
1116 #define PUT_SDB_EPILOGUE_END(NAME)
1118 #define PUT_SDB_SRC_FILE(FILENAME) \
1119 do { \
1120 extern FILE *asm_out_text_file; \
1121 output_file_directive (asm_out_text_file, (FILENAME)); \
1122 } while (0)
1124 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1127 /* Correct the offset of automatic variables and arguments. Note that
1128 the MIPS debug format wants all automatic variables and arguments
1129 to be in terms of the virtual frame pointer (stack pointer before
1130 any adjustment in the function), while the MIPS 3.0 linker wants
1131 the frame pointer to be the stack pointer after the initial
1132 adjustment. */
1134 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
1135 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
1138 /* Tell collect that the object format is ECOFF */
1139 #ifndef OBJECT_FORMAT_ROSE
1142 #endif
1145 MIPS systems define USE_COLLECT2, so
1146 assemble_constructor does nothing anyway. */
1148 /* Don't use the default definitions, because we don't have gld.
1149 Also, we don't want stabs when generating ECOFF output.
1150 Instead we depend on collect to handle these. */
1152 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1153 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1156 \f
1157 /* Target machine storage layout */
1159 /* Define in order to support both big and little endian float formats
1160 in the same gcc binary. */
1161 #define REAL_ARITHMETIC
1163 /* Define this if most significant bit is lowest numbered
1164 in instructions that operate on numbered bit-fields.
1165 */
1166 #define BITS_BIG_ENDIAN 0
1168 /* Define this if most significant byte of a word is the lowest numbered. */
1169 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1171 /* Define this if most significant word of a multiword number is the lowest. */
1172 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1174 /* Define this to set the endianness to use in libgcc2.c, which can
1175 not depend on target_flags. */
1176 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1177 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1178 #else
1179 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1180 #endif
1182 /* Number of bits in an addressable storage unit */
1183 #define BITS_PER_UNIT 8
1185 /* Width in bits of a "word", which is the contents of a machine register.
1186 Note that this is not necessarily the width of data type `int';
1187 if using 16-bit ints on a 68000, this would still be 32.
1188 But on a machine with 16-bit registers, this would be 16. */
1189 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1190 #define MAX_BITS_PER_WORD 64
1192 /* Width of a word, in units (bytes). */
1193 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1194 #define MIN_UNITS_PER_WORD 4
1196 /* For MIPS, width of a floating point register. */
1197 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1199 /* A C expression for the size in bits of the type `int' on the
1200 target machine. If you don't define this, the default is one
1201 word. */
1202 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1203 #define MAX_INT_TYPE_SIZE 64
1205 /* Tell the preprocessor the maximum size of wchar_t. */
1206 #ifndef MAX_WCHAR_TYPE_SIZE
1207 #ifndef WCHAR_TYPE_SIZE
1208 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1209 #endif
1210 #endif
1212 /* A C expression for the size in bits of the type `short' on the
1213 target machine. If you don't define this, the default is half a
1214 word. (If this would be less than one storage unit, it is
1215 rounded up to one unit.) */
1216 #define SHORT_TYPE_SIZE 16
1218 /* A C expression for the size in bits of the type `long' on the
1219 target machine. If you don't define this, the default is one
1220 word. */
1221 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1222 #define MAX_LONG_TYPE_SIZE 64
1224 /* A C expression for the size in bits of the type `long long' on the
1225 target machine. If you don't define this, the default is two
1226 words. */
1227 #define LONG_LONG_TYPE_SIZE 64
1229 /* A C expression for the size in bits of the type `char' on the
1230 target machine. If you don't define this, the default is one
1231 quarter of a word. (If this would be less than one storage unit,
1232 it is rounded up to one unit.) */
1233 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1235 /* A C expression for the size in bits of the type `float' on the
1236 target machine. If you don't define this, the default is one
1237 word. */
1238 #define FLOAT_TYPE_SIZE 32
1240 /* A C expression for the size in bits of the type `double' on the
1241 target machine. If you don't define this, the default is two
1242 words. */
1243 #define DOUBLE_TYPE_SIZE 64
1245 /* A C expression for the size in bits of the type `long double' on
1246 the target machine. If you don't define this, the default is two
1247 words. */
1248 #define LONG_DOUBLE_TYPE_SIZE 64
1250 /* Width in bits of a pointer.
1251 See also the macro `Pmode' defined below. */
1252 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1254 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1255 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1257 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1258 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1260 /* Allocation boundary (in *bits*) for the code of a function. */
1261 #define FUNCTION_BOUNDARY 32
1263 /* Alignment of field after `int : 0' in a structure. */
1264 #define EMPTY_FIELD_BOUNDARY 32
1266 /* Every structure's size must be a multiple of this. */
1267 /* 8 is observed right on a DECstation and on riscos 4.02. */
1268 #define STRUCTURE_SIZE_BOUNDARY 8
1270 /* There is no point aligning anything to a rounder boundary than this. */
1271 #define BIGGEST_ALIGNMENT 64
1273 /* Set this nonzero if move instructions will actually fail to work
1274 when given unaligned data. */
1275 #define STRICT_ALIGNMENT 1
1277 /* Define this if you wish to imitate the way many other C compilers
1278 handle alignment of bitfields and the structures that contain
1279 them.
1281 The behavior is that the type written for a bitfield (`int',
1282 `short', or other integer type) imposes an alignment for the
1283 entire structure, as if the structure really did contain an
1284 ordinary field of that type. In addition, the bitfield is placed
1285 within the structure so that it would fit within such a field,
1286 not crossing a boundary for it.
1288 Thus, on most machines, a bitfield whose type is written as `int'
1289 would not cross a four-byte boundary, and would force four-byte
1290 alignment for the whole structure. (The alignment used may not
1291 be four bytes; it is controlled by the other alignment
1292 parameters.)
1294 If the macro is defined, its definition should be a C expression;
1295 a nonzero value for the expression enables this behavior. */
1297 #define PCC_BITFIELD_TYPE_MATTERS 1
1299 /* If defined, a C expression to compute the alignment given to a
1300 constant that is being placed in memory. CONSTANT is the constant
1301 and ALIGN is the alignment that the object would ordinarily have.
1302 The value of this macro is used instead of that alignment to align
1303 the object.
1305 If this macro is not defined, then ALIGN is used.
1307 The typical use of this macro is to increase alignment for string
1308 constants to be word aligned so that `strcpy' calls that copy
1309 constants can be done inline. */
1311 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1312 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1313 && (ALIGN) < BITS_PER_WORD \
1314 ? BITS_PER_WORD \
1315 : (ALIGN))
1317 /* If defined, a C expression to compute the alignment for a static
1318 variable. TYPE is the data type, and ALIGN is the alignment that
1319 the object would ordinarily have. The value of this macro is used
1320 instead of that alignment to align the object.
1322 If this macro is not defined, then ALIGN is used.
1324 One use of this macro is to increase alignment of medium-size
1325 data to make it all fit in fewer cache lines. Another is to
1326 cause character arrays to be word-aligned so that `strcpy' calls
1327 that copy constants to character arrays can be done inline. */
1329 #undef DATA_ALIGNMENT
1330 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1331 ((((ALIGN) < BITS_PER_WORD) \
1332 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1333 || TREE_CODE (TYPE) == UNION_TYPE \
1334 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1336 /* Define this macro if an argument declared as `char' or `short' in a
1337 prototype should actually be passed as an `int'. In addition to
1338 avoiding errors in certain cases of mismatch, it also makes for
1339 better code on certain machines. */
1341 #define PROMOTE_PROTOTYPES
1343 /* Define if operations between registers always perform the operation
1344 on the full register even if a narrower mode is specified. */
1345 #define WORD_REGISTER_OPERATIONS
1347 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1348 will either zero-extend or sign-extend. The value of this macro should
1349 be the code that says which one of the two operations is implicitly
1350 done, NIL if none. */
1351 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1352 \f
1353 /* Standard register usage. */
1355 /* Number of actual hardware registers.
1356 The hardware registers are assigned numbers for the compiler
1357 from 0 to just below FIRST_PSEUDO_REGISTER.
1358 All registers that the compiler knows about must be given numbers,
1359 even those that are not normally considered general registers.
1361 On the Mips, we have 32 integer registers, 32 floating point
1362 registers, 8 condition code registers, and the special registers
1363 hi, lo, hilo, and rap. The 8 condition code registers are only
1364 used if mips_isa >= 4. The hilo register is only used in 64 bit
1365 mode. It represents a 64 bit value stored as two 32 bit values in
1366 the hi and lo registers; this is the result of the mult
1367 instruction. rap is a pointer to the stack where the return
1368 address reg ($31) was stored. This is needed for C++ exception
1369 handling. */
1371 #define FIRST_PSEUDO_REGISTER 76
1373 /* 1 for registers that have pervasive standard uses
1374 and are not available for the register allocator.
1376 On the MIPS, see conventions, page D-2 */
1378 #define FIXED_REGISTERS \
1379 { \
1380 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1381 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1382 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1383 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1384 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1385 }
1388 /* 1 for registers not available across function calls.
1389 These must include the FIXED_REGISTERS and also any
1390 registers that can be used without being saved.
1391 The latter must include the registers where values are returned
1392 and the register where structure-value addresses are passed.
1393 Aside from that, you can include as many other registers as you like. */
1395 #define CALL_USED_REGISTERS \
1396 { \
1397 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1398 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1399 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1400 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1401 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1402 }
1405 /* Internal macros to classify a register number as to whether it's a
1406 general purpose register, a floating point register, a
1407 multiply/divide register, or a status register. */
1409 #define GP_REG_FIRST 0
1410 #define GP_REG_LAST 31
1411 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1412 #define GP_DBX_FIRST 0
1414 #define FP_REG_FIRST 32
1415 #define FP_REG_LAST 63
1416 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1417 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1419 #define MD_REG_FIRST 64
1420 #define MD_REG_LAST 66
1421 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1423 #define ST_REG_FIRST 67
1424 #define ST_REG_LAST 74
1425 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1427 #define RAP_REG_NUM 75
1429 #define AT_REGNUM (GP_REG_FIRST + 1)
1430 #define HI_REGNUM (MD_REG_FIRST + 0)
1431 #define LO_REGNUM (MD_REG_FIRST + 1)
1432 #define HILO_REGNUM (MD_REG_FIRST + 2)
1434 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1435 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1436 should be used instead. */
1437 #define FPSW_REGNUM ST_REG_FIRST
1439 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1440 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1441 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1442 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1444 /* Return number of consecutive hard regs needed starting at reg REGNO
1445 to hold something of mode MODE.
1446 This is ordinarily the length in words of a value of mode MODE
1447 but can be less for certain modes in special long registers.
1449 On the MIPS, all general registers are one word long. Except on
1450 the R4000 with the FR bit set, the floating point uses register
1451 pairs, with the second register not being allocable. */
1453 #define HARD_REGNO_NREGS(REGNO, MODE) \
1454 (! FP_REG_P (REGNO) \
1455 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1456 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1458 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1459 MODE. In 32 bit mode, require that DImode and DFmode be in even
1460 registers. For DImode, this makes some of the insns easier to
1461 write, since you don't have to worry about a DImode value in
1462 registers 3 & 4, producing a result in 4 & 5.
1464 To make the code simpler HARD_REGNO_MODE_OK now just references an
1465 array built in override_options. Because machmodes.h is not yet
1466 included before this file is processed, the MODE bound can't be
1467 expressed here. */
1471 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1472 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1474 /* Value is 1 if it is a good idea to tie two pseudo registers
1475 when one has mode MODE1 and one has mode MODE2.
1476 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1477 for any hard reg, then this must be 0 for correct output. */
1478 #define MODES_TIEABLE_P(MODE1, MODE2) \
1479 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1480 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1481 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1482 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1484 /* MIPS pc is not overloaded on a register. */
1485 /* #define PC_REGNUM xx */
1487 /* Register to use for pushing function arguments. */
1488 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1490 /* Offset from the stack pointer to the first available location. Use
1491 the default value zero. */
1492 /* #define STACK_POINTER_OFFSET 0 */
1494 /* Base register for access to local variables of the function. */
1495 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 30)
1497 /* Value should be nonzero if functions must have frame pointers.
1498 Zero means the frame pointer need not be set up (and parms
1499 may be accessed via the stack pointer) in functions that seem suitable.
1500 This is computed in `reload', in reload1.c. */
1501 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1503 /* Base register for access to arguments of the function. */
1504 #define ARG_POINTER_REGNUM GP_REG_FIRST
1506 /* Fake register that holds the address on the stack of the
1507 current function's return address. */
1508 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1510 /* Register in which static-chain is passed to a function. */
1511 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1513 /* If the structure value address is passed in a register, then
1514 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1515 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1517 /* If the structure value address is not passed in a register, define
1518 `STRUCT_VALUE' as an expression returning an RTX for the place
1519 where the address is passed. If it returns 0, the address is
1520 passed as an "invisible" first argument. */
1521 #define STRUCT_VALUE 0
1523 /* Mips registers used in prologue/epilogue code when the stack frame
1524 is larger than 32K bytes. These registers must come from the
1525 scratch register set, and not used for passing and returning
1526 arguments and any other information used in the calling sequence
1527 (such as pic). Must start at 12, since t0/t3 are parameter passing
1528 registers in the 64 bit ABI. */
1530 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1531 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1533 /* Define this macro if it is as good or better to call a constant
1534 function address than to call an address kept in a register. */
1535 #define NO_FUNCTION_CSE 1
1537 /* Define this macro if it is as good or better for a function to
1538 call itself with an explicit address than to call an address
1539 kept in a register. */
1540 #define NO_RECURSIVE_FUNCTION_CSE 1
1542 /* The register number of the register used to address a table of
1543 static data addresses in memory. In some cases this register is
1544 defined by a processor's "application binary interface" (ABI).
1545 When this macro is defined, RTL is generated for this register
1546 once, as with the stack pointer and frame pointer registers. If
1547 this macro is not defined, it is up to the machine-dependent
1548 files to allocate such a register (if necessary). */
1549 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1551 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1553 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1554 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1555 isn't always called for static inline functions. */
1556 #define INIT_EXPANDERS embedded_pic_fnaddr_rtx = NULL;
1557 \f
1558 /* Define the classes of registers for register constraints in the
1559 machine description. Also define ranges of constants.
1561 One of the classes must always be named ALL_REGS and include all hard regs.
1562 If there is more than one class, another class must be named NO_REGS
1563 and contain no registers.
1565 The name GENERAL_REGS must be the name of a class (or an alias for
1566 another name such as ALL_REGS). This is the class of registers
1567 that is allowed by "g" or "r" in a register constraint.
1568 Also, registers outside this class are allocated only when
1569 instructions express preferences for them.
1571 The classes must be numbered in nondecreasing order; that is,
1572 a larger-numbered class must never be contained completely
1573 in a smaller-numbered class.
1575 For any two classes, it is very desirable that there be another
1576 class that represents their union. */
1578 enum reg_class
1579 {
1589 LIM_REG_CLASSES /* max value + 1 */
1590 };
1592 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1594 #define GENERAL_REGS GR_REGS
1596 /* An initializer containing the names of the register classes as C
1597 string constants. These names are used in writing some of the
1598 debugging dumps. */
1600 #define REG_CLASS_NAMES \
1601 { \
1611 }
1613 /* An initializer containing the contents of the register classes,
1614 as integers which are bit masks. The Nth integer specifies the
1615 contents of class N. The way the integer MASK is interpreted is
1616 that register R is in the class if `MASK & (1 << R)' is 1.
1618 When the machine has more than 32 registers, an integer does not
1619 suffice. Then the integers are replaced by sub-initializers,
1620 braced groupings containing several integers. Each
1621 sub-initializer must be suitable as an initializer for the type
1622 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1624 #define REG_CLASS_CONTENTS \
1625 { \
1635 }
1638 /* A C expression whose value is a register class containing hard
1639 register REGNO. In general there is more that one such class;
1640 choose a class which is "minimal", meaning that no smaller class
1641 also contains the register. */
1645 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1647 /* A macro whose definition is the name of the class to which a
1648 valid base register must belong. A base register is one used in
1649 an address which is the register value plus a displacement. */
1651 #define BASE_REG_CLASS GR_REGS
1653 /* A macro whose definition is the name of the class to which a
1654 valid index register must belong. An index register is one used
1655 in an address where its value is either multiplied by a scale
1656 factor or added to another register (as well as added to a
1657 displacement). */
1659 #define INDEX_REG_CLASS NO_REGS
1662 /* REGISTER AND CONSTANT CLASSES */
1664 /* Get reg_class from a letter such as appears in the machine
1665 description.
1667 DEFINED REGISTER CLASSES:
1669 'd' General (aka integer) registers
1670 'f' Floating point registers
1671 'h' Hi register
1672 'l' Lo register
1673 'x' Multiply/divide registers
1674 'a' HILO_REG
1675 'z' FP Status register
1676 'b' All registers */
1680 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1682 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1683 string can be used to stand for particular ranges of immediate
1684 operands. This macro defines what the ranges are. C is the
1685 letter, and VALUE is a constant value. Return 1 if VALUE is
1686 in the range specified by C. */
1688 /* For MIPS:
1690 `I' is used for the range of constants an arithmetic insn can
1691 actually contain (16 bits signed integers).
1693 `J' is used for the range which is just zero (ie, $r0).
1695 `K' is used for the range of constants a logical insn can actually
1696 contain (16 bit zero-extended integers).
1698 `L' is used for the range of constants that be loaded with lui
1699 (ie, the bottom 16 bits are zero).
1701 `M' is used for the range of constants that take two words to load
1702 (ie, not matched by `I', `K', and `L').
1704 `N' is used for negative 16 bit constants.
1706 `O' is an exact power of 2 (not yet used in the md file).
1708 `P' is used for positive 16 bit constants. */
1710 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1711 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1713 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1718 && (((VALUE) & ~2147483647) == 0 \
1719 || ((VALUE) & ~2147483647) == ~2147483647)) \
1721 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1722 && (((VALUE) & 0x0000ffff) != 0 \
1723 || (((VALUE) & ~2147483647) != 0 \
1724 && ((VALUE) & ~2147483647) != ~2147483647))) \
1728 : 0)
1730 /* Similar, but for floating constants, and defining letters G and H.
1731 Here VALUE is the CONST_DOUBLE rtx itself. */
1733 /* For Mips
1735 'G' : Floating point 0 */
1737 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1739 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1741 /* Letters in the range `Q' through `U' may be defined in a
1742 machine-dependent fashion to stand for arbitrary operand types.
1743 The machine description macro `EXTRA_CONSTRAINT' is passed the
1744 operand as its first argument and the constraint letter as its
1745 second operand.
1747 `Q' is for memory references which take more than 1 instruction.
1748 `R' is for memory references which take 1 word for the instruction.
1749 `S' is for references to extern items which are PIC for OSF/rose. */
1751 #define EXTRA_CONSTRAINT(OP,CODE) \
1752 ((GET_CODE (OP) != MEM) ? FALSE \
1756 && HALF_PIC_ADDRESS_P (OP)) \
1757 : FALSE)
1759 /* Given an rtx X being reloaded into a reg required to be
1760 in class CLASS, return the class of reg to actually use.
1761 In general this is just CLASS; but on some machines
1762 in some cases it is preferable to use a more restrictive class. */
1764 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1765 ((CLASS) != ALL_REGS \
1766 ? (CLASS) \
1767 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1768 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1769 ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1770 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1771 || GET_MODE (X) == VOIDmode) \
1772 ? GR_REGS \
1773 : (CLASS))))
1775 /* Certain machines have the property that some registers cannot be
1776 copied to some other registers without using memory. Define this
1777 macro on those machines to be a C expression that is non-zero if
1778 objects of mode MODE in registers of CLASS1 can only be copied to
1779 registers of class CLASS2 by storing a register of CLASS1 into
1780 memory and loading that memory location into a register of CLASS2.
1782 Do not define this macro if its value would always be zero. */
1784 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1785 ((!TARGET_DEBUG_H_MODE \
1786 && GET_MODE_CLASS (MODE) == MODE_INT \
1787 && ((CLASS1 == FP_REGS && CLASS2 == GR_REGS) \
1788 || (CLASS1 == GR_REGS && CLASS2 == FP_REGS))) \
1789 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1790 && ((CLASS1 == GR_REGS && CLASS2 == FP_REGS) \
1791 || (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
1793 /* The HI and LO registers can only be reloaded via the general
1794 registers. Condition code registers can only be loaded to the
1795 general registers, and from the floating point registers. */
1797 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1798 mips_secondary_reload_class (CLASS, MODE, X, 1)
1799 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1800 mips_secondary_reload_class (CLASS, MODE, X, 0)
1802 /* Not declared above, with the other functions, because enum
1803 reg_class is not declared yet. */
1806 /* Return the maximum number of consecutive registers
1807 needed to represent mode MODE in a register of class CLASS. */
1809 #define CLASS_UNITS(mode, size) \
1810 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1812 #define CLASS_MAX_NREGS(CLASS, MODE) \
1813 ((CLASS) == FP_REGS \
1814 ? (TARGET_FLOAT64 \
1815 ? CLASS_UNITS (MODE, 8) \
1816 : 2 * CLASS_UNITS (MODE, 8)) \
1817 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1819 /* If defined, this is a C expression whose value should be
1820 nonzero if the insn INSN has the effect of mysteriously
1821 clobbering the contents of hard register number REGNO. By
1822 "mysterious" we mean that the insn's RTL expression doesn't
1823 describe such an effect.
1825 If this macro is not defined, it means that no insn clobbers
1826 registers mysteriously. This is the usual situation; all else
1827 being equal, it is best for the RTL expression to show all the
1828 activity. */
1830 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1832 \f
1833 /* Stack layout; function entry, exit and calling. */
1835 /* Define this if pushing a word on the stack
1836 makes the stack pointer a smaller address. */
1837 #define STACK_GROWS_DOWNWARD
1839 /* Define this if the nominal address of the stack frame
1840 is at the high-address end of the local variables;
1841 that is, each additional local variable allocated
1842 goes at a more negative offset in the frame. */
1843 /* #define FRAME_GROWS_DOWNWARD */
1845 /* Offset within stack frame to start allocating local variables at.
1846 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1847 first local allocated. Otherwise, it is the offset to the BEGINNING
1848 of the first local allocated. */
1849 #define STARTING_FRAME_OFFSET \
1850 (current_function_outgoing_args_size \
1851 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1853 /* Offset from the stack pointer register to an item dynamically
1854 allocated on the stack, e.g., by `alloca'.
1856 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1857 length of the outgoing arguments. The default is correct for most
1858 machines. See `function.c' for details.
1860 The MIPS ABI states that functions which dynamically allocate the
1861 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
1862 we are trying to create a second frame pointer to the function, so
1863 allocate some stack space to make it happy.
1865 However, the linker currently complains about linking any code that
1866 dynamically allocates stack space, and there seems to be a bug in
1867 STACK_DYNAMIC_OFFSET, so don't define this right now. */
1869 #if 0
1870 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1871 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
1872 ? 4*UNITS_PER_WORD \
1873 : current_function_outgoing_args_size)
1874 #endif
1876 /* The return address for the current frame is in r31 is this is a leaf
1877 function. Otherwise, it is on the stack. It is at a variable offset
1878 from sp/fp/ap, so we define a fake hard register rap which is a
1879 poiner to the return address on the stack. This always gets eliminated
1880 during reload to be either the frame pointer or the stack pointer plus
1881 an offset. */
1883 /* ??? This definition fails for leaf functions. There is currently no
1884 general solution for this problem. */
1886 /* ??? There appears to be no way to get the return address of any previous
1887 frame except by disassembling instructions in the prologue/epilogue.
1888 So currently we support only the current frame. */
1890 #define RETURN_ADDR_RTX(count, frame) \
1891 ((count == 0) \
1892 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
1893 : (rtx) 0)
1895 /* Structure to be filled in by compute_frame_size with register
1896 save masks, and offsets for the current function. */
1898 struct mips_frame_info
1899 {
1915 };
1919 /* If defined, this macro specifies a table of register pairs used to
1920 eliminate unneeded registers that point into the stack frame. If
1921 it is not defined, the only elimination attempted by the compiler
1922 is to replace references to the frame pointer with references to
1923 the stack pointer.
1925 The definition of this macro is a list of structure
1926 initializations, each of which specifies an original and
1927 replacement register.
1929 On some machines, the position of the argument pointer is not
1930 known until the compilation is completed. In such a case, a
1931 separate hard register must be used for the argument pointer.
1932 This register can be eliminated by replacing it with either the
1933 frame pointer or the argument pointer, depending on whether or not
1934 the frame pointer has been eliminated.
1936 In this case, you might specify:
1937 #define ELIMINABLE_REGS \
1938 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1939 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1940 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1942 Note that the elimination of the argument pointer with the stack
1943 pointer is specified first since that is the preferred elimination. */
1945 #define ELIMINABLE_REGS \
1946 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1947 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1948 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1949 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1950 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1952 /* A C expression that returns non-zero if the compiler is allowed to
1953 try to replace register number FROM-REG with register number
1954 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
1955 defined, and will usually be the constant 1, since most of the
1956 cases preventing register elimination are things that the compiler
1957 already knows about. */
1959 #define CAN_ELIMINATE(FROM, TO) \
1960 (!frame_pointer_needed \
1961 || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1962 || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1963 && (TO) == FRAME_POINTER_REGNUM))
1965 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1966 specifies the initial difference between the specified pair of
1967 registers. This macro must be defined if `ELIMINABLE_REGS' is
1968 defined. */
1970 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1971 { compute_frame_size (get_frame_size ()); \
1972 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1973 (OFFSET) = 0; \
1974 else if ((FROM) == ARG_POINTER_REGNUM \
1975 && ((TO) == FRAME_POINTER_REGNUM \
1976 || (TO) == STACK_POINTER_REGNUM)) \
1977 (OFFSET) = (current_frame_info.total_size \
1978 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
1979 ? current_function_pretend_args_size \
1980 : 0)); \
1981 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1982 && ((TO) == FRAME_POINTER_REGNUM \
1983 || (TO) == STACK_POINTER_REGNUM)) \
1984 (OFFSET) = current_frame_info.gp_sp_offset \
1985 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
1986 * (BYTES_BIG_ENDIAN != 0)); \
1987 else \
1988 abort (); \
1989 }
1991 /* If we generate an insn to push BYTES bytes,
1992 this says how many the stack pointer really advances by.
1993 On the vax, sp@- in a byte insn really pushes a word. */
1995 /* #define PUSH_ROUNDING(BYTES) 0 */
1997 /* If defined, the maximum amount of space required for outgoing
1998 arguments will be computed and placed into the variable
1999 `current_function_outgoing_args_size'. No space will be pushed
2000 onto the stack for each call; instead, the function prologue
2001 should increase the stack frame size by this amount.
2003 It is not proper to define both `PUSH_ROUNDING' and
2004 `ACCUMULATE_OUTGOING_ARGS'. */
2005 #define ACCUMULATE_OUTGOING_ARGS
2007 /* Offset from the argument pointer register to the first argument's
2008 address. On some machines it may depend on the data type of the
2009 function.
2011 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2012 the first argument's address.
2014 On the MIPS, we must skip the first argument position if we are
2015 returning a structure or a union, to account for its address being
2016 passed in $4. However, at the current time, this produces a compiler
2017 that can't bootstrap, so comment it out for now. */
2019 #if 0
2020 #define FIRST_PARM_OFFSET(FNDECL) \
2021 (FNDECL != 0 \
2022 && TREE_TYPE (FNDECL) != 0 \
2023 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2024 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2025 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2026 ? UNITS_PER_WORD \
2027 : 0)
2028 #else
2029 #define FIRST_PARM_OFFSET(FNDECL) 0
2030 #endif
2032 /* When a parameter is passed in a register, stack space is still
2033 allocated for it. For the MIPS, stack space must be allocated, cf
2034 Asm Lang Prog Guide page 7-8.
2036 BEWARE that some space is also allocated for non existing arguments
2037 in register. In case an argument list is of form GF used registers
2038 are a0 (a2,a3), but we should push over a1... */
2040 #define REG_PARM_STACK_SPACE(FNDECL) \
2041 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2043 /* Define this if it is the responsibility of the caller to
2044 allocate the area reserved for arguments passed in registers.
2045 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2046 of this macro is to determine whether the space is included in
2047 `current_function_outgoing_args_size'. */
2048 #define OUTGOING_REG_PARM_STACK_SPACE
2050 /* Align stack frames on 64 bits (Double Word ). */
2051 #define STACK_BOUNDARY 64
2053 /* Make sure 4 words are always allocated on the stack. */
2055 #ifndef STACK_ARGS_ADJUST
2056 #define STACK_ARGS_ADJUST(SIZE) \
2057 { \
2058 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2059 SIZE.constant = 4 * UNITS_PER_WORD; \
2060 }
2061 #endif
2063 \f
2064 /* A C expression that should indicate the number of bytes of its
2065 own arguments that a function function pops on returning, or 0
2066 if the function pops no arguments and the caller must therefore
2067 pop them all after the function returns.
2069 FUNDECL is the declaration node of the function (as a tree).
2071 FUNTYPE is a C variable whose value is a tree node that
2072 describes the function in question. Normally it is a node of
2073 type `FUNCTION_TYPE' that describes the data type of the function.
2074 From this it is possible to obtain the data types of the value
2075 and arguments (if known).
2077 When a call to a library function is being considered, FUNTYPE
2078 will contain an identifier node for the library function. Thus,
2079 if you need to distinguish among various library functions, you
2080 can do so by their names. Note that "library function" in this
2081 context means a function used to perform arithmetic, whose name
2082 is known specially in the compiler and was not mentioned in the
2083 C code being compiled.
2085 STACK-SIZE is the number of bytes of arguments passed on the
2086 stack. If a variable number of bytes is passed, it is zero, and
2087 argument popping will always be the responsibility of the
2088 calling function. */
2090 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2093 /* Symbolic macros for the registers used to return integer and floating
2094 point values. */
2096 #define GP_RETURN (GP_REG_FIRST + 2)
2097 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2099 /* Symbolic macros for the first/last argument registers. */
2101 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2102 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2103 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2104 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2106 #define MAX_ARGS_IN_REGISTERS 4
2108 /* Define how to find the value returned by a library function
2109 assuming the value has mode MODE. */
2111 #define LIBCALL_VALUE(MODE) \
2112 gen_rtx (REG, MODE, \
2113 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2114 && (! TARGET_SINGLE_FLOAT \
2115 || GET_MODE_SIZE (MODE) <= 4)) \
2116 ? FP_RETURN \
2117 : GP_RETURN))
2119 /* Define how to find the value returned by a function.
2120 VALTYPE is the data type of the value (as a tree).
2121 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2122 otherwise, FUNC is 0. */
2124 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2127 /* 1 if N is a possible register number for a function value.
2128 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2129 Currently, R2 and F0 are only implemented here (C has no complex type) */
2131 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2133 /* 1 if N is a possible register number for function argument passing.
2134 We have no FP argument registers when soft-float. When FP registers
2135 are 32 bits, we can't directly reference the odd numbered ones. */
2137 #define FUNCTION_ARG_REGNO_P(N) \
2138 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2139 || (! TARGET_SOFT_FLOAT \
2140 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2141 && (TARGET_FLOAT64 || (0 == (N) % 2))))
2143 /* A C expression which can inhibit the returning of certain function
2144 values in registers, based on the type of value. A nonzero value says
2145 to return the function value in memory, just as large structures are
2146 always returned. Here TYPE will be a C expression of type
2147 `tree', representing the data type of the value.
2149 Note that values of mode `BLKmode' must be explicitly
2150 handled by this macro. Also, the option `-fpcc-struct-return'
2151 takes effect regardless of this macro. On most systems, it is
2152 possible to leave the macro undefined; this causes a default
2153 definition to be used, whose value is the constant 1 for BLKmode
2154 values, and 0 otherwise.
2156 GCC normally converts 1 byte structures into chars, 2 byte
2157 structs into shorts, and 4 byte structs into ints, and returns
2158 them this way. Defining the following macro overrides this,
2159 to give us MIPS cc compatibility. */
2161 #define RETURN_IN_MEMORY(TYPE) \
2162 (TYPE_MODE (TYPE) == BLKmode)
2163 \f
2164 /* A code distinguishing the floating point format of the target
2165 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2166 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2168 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2170 \f
2171 /* Define a data type for recording info about an argument list
2172 during the scan of that argument list. This data type should
2173 hold all necessary information about the function itself
2174 and about the args processed so far, enough to enable macros
2175 such as FUNCTION_ARG to determine where the next arg should go.
2176 */
2185 /* Adjustments made to args pass in regs. */
2186 /* ??? The size is doubled to work around a
2187 bug in the code that sets the adjustments
2188 in function_arg. */
2192 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2193 for a call to a function whose data type is FNTYPE.
2194 For a library call, FNTYPE is 0.
2196 */
2198 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2199 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2201 /* Update the data in CUM to advance over an argument
2202 of mode MODE and data type TYPE.
2203 (TYPE is null for libcalls where that information may not be available.) */
2205 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2206 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2208 /* Determine where to put an argument to a function.
2209 Value is zero to push the argument on the stack,
2210 or a hard register in which to store the argument.
2212 MODE is the argument's machine mode.
2213 TYPE is the data type of the argument (as a tree).
2214 This is null for libcalls where that information may
2215 not be available.
2216 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2217 the preceding args and about the function being called.
2218 NAMED is nonzero if this argument is a named parameter
2219 (otherwise it is an extra parameter matching an ellipsis). */
2221 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2222 function_arg( &CUM, MODE, TYPE, NAMED)
2224 /* For an arg passed partly in registers and partly in memory,
2225 this is the number of registers used.
2226 For args passed entirely in registers or entirely in memory, zero. */
2228 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2229 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2231 /* If defined, a C expression that gives the alignment boundary, in
2232 bits, of an argument with the specified mode and type. If it is
2233 not defined, `PARM_BOUNDARY' is used for all arguments. */
2235 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2236 (((TYPE) != 0) \
2237 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2238 ? PARM_BOUNDARY \
2239 : TYPE_ALIGN(TYPE)) \
2240 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2241 ? PARM_BOUNDARY \
2242 : GET_MODE_ALIGNMENT(MODE)))
2244 \f
2245 /* This macro generates the assembly code for function entry.
2246 FILE is a stdio stream to output the code to.
2247 SIZE is an int: how many units of temporary storage to allocate.
2248 Refer to the array `regs_ever_live' to determine which registers
2249 to save; `regs_ever_live[I]' is nonzero if register number I
2250 is ever used in the function. This macro is responsible for
2251 knowing which registers should not be saved even if used. */
2253 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2255 /* This macro generates the assembly code for function exit,
2256 on machines that need it. If FUNCTION_EPILOGUE is not defined
2257 then individual return instructions are generated for each
2258 return statement. Args are same as for FUNCTION_PROLOGUE. */
2260 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2262 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2264 #define MUST_SAVE_REGISTER(regno) \
2265 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2266 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
2267 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2269 /* ALIGN FRAMES on double word boundaries */
2271 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2273 \f
2274 /* Output assembler code to FILE to increment profiler label # LABELNO
2275 for profiling a function entry. */
2277 #define FUNCTION_PROFILER(FILE, LABELNO) \
2278 { \
2282 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2284 fprintf (FILE, \
2287 reg_names[STACK_POINTER_REGNUM], \
2288 reg_names[STACK_POINTER_REGNUM], \
2289 TARGET_LONG64 ? 16 : 8); \
2292 }
2294 /* Define this macro if the code for function profiling should come
2295 before the function prologue. Normally, the profiling code comes
2296 after. */
2298 /* #define PROFILE_BEFORE_PROLOGUE */
2300 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2301 the stack pointer does not matter. The value is tested only in
2302 functions that have frame pointers.
2303 No definition is equivalent to always zero. */
2305 #define EXIT_IGNORE_STACK 1
2307 \f
2308 /* A C statement to output, on the stream FILE, assembler code for a
2309 block of data that contains the constant parts of a trampoline.
2310 This code should not include a label--the label is taken care of
2311 automatically. */
2313 #define TRAMPOLINE_TEMPLATE(STREAM) \
2314 { \
2318 if (TARGET_LONG64) \
2319 { \
2322 } \
2323 else \
2324 { \
2327 } \
2331 if (TARGET_LONG64) \
2332 { \
2335 } \
2336 else \
2337 { \
2340 } \
2341 }
2343 /* A C expression for the size in bytes of the trampoline, as an
2344 integer. */
2346 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2348 /* Alignment required for trampolines, in bits. */
2350 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2352 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2353 program and data caches. */
2355 #ifndef CACHE_FLUSH_FUNC
2357 #endif
2359 /* A C statement to initialize the variable parts of a trampoline.
2360 ADDR is an RTX for the address of the trampoline; FNADDR is an
2361 RTX for the address of the nested function; STATIC_CHAIN is an
2362 RTX for the static chain value that should be passed to the
2363 function when it is called. */
2365 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2366 { \
2367 rtx addr = ADDR; \
2368 if (TARGET_LONG64) \
2369 { \
2370 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2371 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2372 } \
2373 else \
2374 { \
2375 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2376 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2377 } \
2378 \
2379 /* Flush both caches. We need to flush the data cache in case \
2382 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2383 0, VOIDmode, 3, addr, Pmode, \
2384 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2385 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2386 }
2387 \f
2388 /* Addressing modes, and classification of registers for them. */
2390 /* #define HAVE_POST_INCREMENT */
2391 /* #define HAVE_POST_DECREMENT */
2393 /* #define HAVE_PRE_DECREMENT */
2394 /* #define HAVE_PRE_INCREMENT */
2396 /* These assume that REGNO is a hard or pseudo reg number.
2397 They give nonzero only if REGNO is a hard reg of the suitable class
2398 or a pseudo reg currently allocated to a suitable hard reg.
2399 These definitions are NOT overridden anywhere. */
2401 #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
2402 GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
2404 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
2405 (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
2407 #define REGNO_OK_FOR_INDEX_P(regno) 0
2408 #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
2410 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2411 and check its validity for a certain class.
2412 We have two alternate definitions for each of them.
2413 The usual definition accepts all pseudo regs; the other rejects them all.
2414 The symbol REG_OK_STRICT causes the latter definition to be used.
2416 Most source files want to accept pseudo regs in the hope that
2417 they will get allocated to the class that the insn wants them to be in.
2418 Some source files that are used after register allocation
2419 need to be strict. */
2421 #ifndef REG_OK_STRICT
2423 #define REG_OK_STRICT_P 0
2424 #define REG_OK_FOR_INDEX_P(X) 0
2425 #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
2427 #else
2429 #define REG_OK_STRICT_P 1
2430 #define REG_OK_FOR_INDEX_P(X) 0
2431 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2433 #endif
2435 \f
2436 /* Maximum number of registers that can appear in a valid memory address. */
2438 #define MAX_REGS_PER_ADDRESS 1
2440 /* A C compound statement with a conditional `goto LABEL;' executed
2441 if X (an RTX) is a legitimate memory address on the target
2442 machine for a memory operand of mode MODE.
2444 It usually pays to define several simpler macros to serve as
2445 subroutines for this one. Otherwise it may be too complicated
2446 to understand.
2448 This macro must exist in two variants: a strict variant and a
2449 non-strict one. The strict variant is used in the reload pass.
2450 It must be defined so that any pseudo-register that has not been
2451 allocated a hard register is considered a memory reference. In
2452 contexts where some kind of register is required, a
2453 pseudo-register with no hard register must be rejected.
2455 The non-strict variant is used in other passes. It must be
2456 defined to accept all pseudo-registers in every context where
2457 some kind of register is required.
2459 Compiler source files that want to use the strict variant of
2460 this macro define the macro `REG_OK_STRICT'. You should use an
2461 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2462 in that case and the non-strict variant otherwise.
2464 Typically among the subroutines used to define
2465 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2466 acceptable registers for various purposes (one for base
2467 registers, one for index registers, and so on). Then only these
2468 subroutine macros need have two variants; the higher levels of
2469 macros may be the same whether strict or not.
2471 Normally, constant addresses which are the sum of a `symbol_ref'
2472 and an integer are stored inside a `const' RTX to mark them as
2473 constant. Therefore, there is no need to recognize such sums
2474 specifically as legitimate addresses. Normally you would simply
2475 recognize any `const' as legitimate.
2477 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2478 constant sums that are not marked with `const'. It assumes
2479 that a naked `plus' indicates indexing. If so, then you *must*
2480 reject such naked constant sums as illegitimate addresses, so
2481 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2483 On some machines, whether a symbolic address is legitimate
2484 depends on the section that the address refers to. On these
2485 machines, define the macro `ENCODE_SECTION_INFO' to store the
2486 information into the `symbol_ref', and then check for it here.
2487 When you see a `const', you will have to look inside it to find
2488 the `symbol_ref' in order to determine the section. */
2490 #if 1
2491 #define GO_PRINTF(x) trace(x)
2492 #define GO_PRINTF2(x,y) trace(x,y)
2493 #define GO_DEBUG_RTX(x) debug_rtx(x)
2495 #else
2496 #define GO_PRINTF(x)
2497 #define GO_PRINTF2(x,y)
2498 #define GO_DEBUG_RTX(x)
2499 #endif
2501 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2502 { \
2503 register rtx xinsn = (X); \
2504 \
2505 if (TARGET_DEBUG_B_MODE) \
2506 { \
2509 GO_DEBUG_RTX (xinsn); \
2510 } \
2511 \
2512 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
2513 goto ADDR; \
2514 \
2515 if (CONSTANT_ADDRESS_P (xinsn) \
2516 && ! (mips_split_addresses && mips_check_split (xinsn, MODE))) \
2517 goto ADDR; \
2518 \
2519 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2520 { \
2521 register rtx xlow0 = XEXP (xinsn, 0); \
2522 register rtx xlow1 = XEXP (xinsn, 1); \
2523 \
2524 if (GET_CODE (xlow0) == REG && REG_OK_FOR_BASE_P (xlow0) \
2525 && mips_check_split (xlow1, MODE)) \
2526 goto ADDR; \
2527 } \
2528 \
2529 if (GET_CODE (xinsn) == PLUS) \
2530 { \
2531 register rtx xplus0 = XEXP (xinsn, 0); \
2532 register rtx xplus1 = XEXP (xinsn, 1); \
2533 register enum rtx_code code0 = GET_CODE (xplus0); \
2534 register enum rtx_code code1 = GET_CODE (xplus1); \
2535 \
2536 if (code0 != REG && code1 == REG) \
2537 { \
2538 xplus0 = XEXP (xinsn, 1); \
2539 xplus1 = XEXP (xinsn, 0); \
2540 code0 = GET_CODE (xplus0); \
2541 code1 = GET_CODE (xplus1); \
2542 } \
2543 \
2544 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
2545 { \
2546 if (code1 == CONST_INT \
2547 && INTVAL (xplus1) >= -32768 \
2548 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2549 goto ADDR; \
2550 \
2551 /* For some code sequences, you actually get better code by \
2552 pretending that the MIPS supports an address mode of a \
2553 constant address + a register, even though the real \
2554 machine doesn't support it. This is because the \
2555 assembler can use $r1 to load just the high 16 bits, add \
2556 in the register, and fold the low 16 bits into the memory \
2557 reference, whereas the compiler generates a 4 instruction \
2558 sequence. On the other hand, CSE is not as effective. \
2559 It would be a win to generate the lui directly, but the \
2560 MIPS assembler does not have syntax to generate the \
2562 \
2564 /* Reject combining an embedded PIC text segment reference \
2565 with a register. That requires an additional \
2567 /* ??? Reject combining an address with a register for the MIPS \
2569 if (!TARGET_DEBUG_A_MODE \
2570 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2571 && CONSTANT_ADDRESS_P (xplus1) \
2572 && ! mips_split_addresses \
2573 && (!TARGET_EMBEDDED_PIC \
2574 || code1 != CONST \
2575 || GET_CODE (XEXP (xplus1, 0)) != MINUS)) \
2576 goto ADDR; \
2577 } \
2578 } \
2579 \
2580 if (TARGET_DEBUG_B_MODE) \
2582 }
2585 /* A C expression that is 1 if the RTX X is a constant which is a
2586 valid address. This is defined to be the same as `CONSTANT_P (X)',
2587 but rejecting CONST_DOUBLE. */
2588 /* When pic, we must reject addresses of the form symbol+large int.
2589 This is because an instruction `sw $4,s+70000' needs to be converted
2590 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2591 assembler would use $at as a temp to load in the large offset. In this
2592 case $at is already in use. We convert such problem addresses to
2593 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2594 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2595 #define CONSTANT_ADDRESS_P(X) \
2596 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2597 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2598 || (GET_CODE (X) == CONST \
2599 && ! (flag_pic && pic_address_needs_scratch (X)) \
2600 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2601 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2603 /* Define this, so that when PIC, reload won't try to reload invalid
2604 addresses which require two reload registers. */
2606 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2608 /* Nonzero if the constant value X is a legitimate general operand.
2609 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2611 At present, GAS doesn't understand li.[sd], so don't allow it
2612 to be generated at present. Also, the MIPS assembler does not
2613 grok li.d Infinity. */
2615 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2616 #define LEGITIMATE_CONSTANT_P(X) \
2617 ((GET_CODE (X) != CONST_DOUBLE \
2618 || mips_const_double_ok (X, GET_MODE (X))) \
2619 && ! (GET_CODE (X) == CONST \
2620 && mips_abi != ABI_32 && mips_abi != ABI_EABI))
2622 /* A C compound statement that attempts to replace X with a valid
2623 memory address for an operand of mode MODE. WIN will be a C
2624 statement label elsewhere in the code; the macro definition may
2625 use
2627 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2629 to avoid further processing if the address has become legitimate.
2631 X will always be the result of a call to `break_out_memory_refs',
2632 and OLDX will be the operand that was given to that function to
2633 produce X.
2635 The code generated by this macro should not alter the
2636 substructure of X. If it transforms X into a more legitimate
2637 form, it should assign X (which will always be a C variable) a
2638 new value.
2640 It is not necessary for this macro to come up with a legitimate
2641 address. The compiler has standard ways of doing so in all
2642 cases. In fact, it is safe for this macro to do nothing. But
2643 often a machine-dependent strategy can generate better code.
2645 For the MIPS, transform:
2647 memory(X + <large int>)
2649 into:
2651 Y = <large int> & ~0x7fff;
2652 Z = X + Y
2653 memory (Z + (<large int> & 0x7fff));
2655 This is for CSE to find several similar references, and only use one Z.
2657 When PIC, convert addresses of the form memory (symbol+large int) to
2658 memory (reg+large int). */
2661 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2662 { \
2663 register rtx xinsn = (X); \
2664 \
2665 if (TARGET_DEBUG_B_MODE) \
2666 { \
2668 GO_DEBUG_RTX (xinsn); \
2669 } \
2670 \
2671 if (mips_split_addresses && mips_check_split (X, MODE)) \
2672 { \
2674 X = gen_rtx (LO_SUM, Pmode, \
2675 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2676 goto WIN; \
2677 } \
2678 \
2679 if (GET_CODE (xinsn) == CONST \
2680 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2682 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2683 { \
2684 rtx ptr_reg = gen_reg_rtx (Pmode); \
2685 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2686 \
2687 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2688 \
2689 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2690 if (SMALL_INT (constant)) \
2691 goto WIN; \
2692 /* Otherwise we fall through so the code below will fix the \
2694 xinsn = X; \
2695 } \
2696 \
2697 if (GET_CODE (xinsn) == PLUS) \
2698 { \
2699 register rtx xplus0 = XEXP (xinsn, 0); \
2700 register rtx xplus1 = XEXP (xinsn, 1); \
2701 register enum rtx_code code0 = GET_CODE (xplus0); \
2702 register enum rtx_code code1 = GET_CODE (xplus1); \
2703 \
2704 if (code0 != REG && code1 == REG) \
2705 { \
2706 xplus0 = XEXP (xinsn, 1); \
2707 xplus1 = XEXP (xinsn, 0); \
2708 code0 = GET_CODE (xplus0); \
2709 code1 = GET_CODE (xplus1); \
2710 } \
2711 \
2712 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
2713 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2714 { \
2715 rtx int_reg = gen_reg_rtx (Pmode); \
2716 rtx ptr_reg = gen_reg_rtx (Pmode); \
2717 \
2718 emit_move_insn (int_reg, \
2719 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2720 \
2721 emit_insn (gen_rtx (SET, VOIDmode, \
2722 ptr_reg, \
2723 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2724 \
2725 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2726 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2727 goto WIN; \
2728 } \
2729 } \
2730 \
2731 if (TARGET_DEBUG_B_MODE) \
2733 }
2736 /* A C statement or compound statement with a conditional `goto
2737 LABEL;' executed if memory address X (an RTX) can have different
2738 meanings depending on the machine mode of the memory reference it
2739 is used for.
2741 Autoincrement and autodecrement addresses typically have
2742 mode-dependent effects because the amount of the increment or
2743 decrement is the size of the operand being addressed. Some
2744 machines have other mode-dependent addresses. Many RISC machines
2745 have no mode-dependent addresses.
2747 You may assume that ADDR is a valid address for the machine. */
2749 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2752 /* Define this macro if references to a symbol must be treated
2753 differently depending on something about the variable or
2754 function named by the symbol (such as what section it is in).
2756 The macro definition, if any, is executed immediately after the
2757 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2758 The value of the rtl will be a `mem' whose address is a
2759 `symbol_ref'.
2761 The usual thing for this macro to do is to a flag in the
2762 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2763 name string in the `symbol_ref' (if one bit is not enough
2764 information).
2766 The best way to modify the name string is by adding text to the
2767 beginning, with suitable punctuation to prevent any ambiguity.
2768 Allocate the new name in `saveable_obstack'. You will have to
2769 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2770 and output the name accordingly.
2772 You can also check the information stored in the `symbol_ref' in
2773 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2774 `PRINT_OPERAND_ADDRESS'. */
2776 #define ENCODE_SECTION_INFO(DECL) \
2777 do \
2778 { \
2779 if (TARGET_EMBEDDED_PIC) \
2780 { \
2781 if (TREE_CODE (DECL) == VAR_DECL) \
2782 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2783 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
2784 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
2785 else if (TREE_CODE (DECL) == STRING_CST \
2786 && ! flag_writable_strings) \
2787 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
2788 else \
2789 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
2790 } \
2791 \
2792 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
2793 { \
2794 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2795 \
2796 if (size > 0 && size <= mips_section_threshold) \
2797 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2798 } \
2799 \
2800 else if (HALF_PIC_P ()) \
2801 HALF_PIC_ENCODE (DECL); \
2802 } \
2803 while (0)
2805 \f
2806 /* Specify the machine mode that this machine uses
2807 for the index in the tablejump instruction. */
2808 #define CASE_VECTOR_MODE (TARGET_LONG64 ? DImode : SImode)
2810 /* Define this if the tablejump instruction expects the table
2811 to contain offsets from the address of the table.
2812 Do not define this if the table should contain absolute addresses. */
2813 /* #define CASE_VECTOR_PC_RELATIVE */
2815 /* Specify the tree operation to be used to convert reals to integers. */
2816 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2818 /* This is the kind of divide that is easiest to do in the general case. */
2819 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2821 /* Define this as 1 if `char' should by default be signed; else as 0. */
2822 #ifndef DEFAULT_SIGNED_CHAR
2823 #define DEFAULT_SIGNED_CHAR 1
2824 #endif
2826 /* Max number of bytes we can move from memory to memory
2827 in one reasonably fast instruction. */
2828 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2829 #define MAX_MOVE_MAX 8
2831 /* Define this macro as a C expression which is nonzero if
2832 accessing less than a word of memory (i.e. a `char' or a
2833 `short') is no faster than accessing a word of memory, i.e., if
2834 such access require more than one instruction or if there is no
2835 difference in cost between byte and (aligned) word loads.
2837 On RISC machines, it tends to generate better code to define
2838 this as 1, since it avoids making a QI or HI mode register. */
2839 #define SLOW_BYTE_ACCESS 1
2841 /* We assume that the store-condition-codes instructions store 0 for false
2842 and some other value for true. This is the value stored for true. */
2844 #define STORE_FLAG_VALUE 1
2846 /* Define this if zero-extension is slow (more than one real instruction). */
2847 #define SLOW_ZERO_EXTEND
2849 /* Define this to be nonzero if shift instructions ignore all but the low-order
2850 few bits. */
2851 #define SHIFT_COUNT_TRUNCATED 1
2853 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2854 is done just by pretending it is already truncated. */
2855 /* In 64 bit mode, 32 bit instructions require that register values be properly
2856 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
2857 converts a value >32 bits to a value <32 bits. */
2858 /* ??? This results in inefficient code for 64 bit to 32 conversions.
2859 Something needs to be done about this. Perhaps not use any 32 bit
2860 instructions? Perhaps use PROMOTE_MODE? */
2861 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2862 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2864 /* Specify the machine mode that pointers have.
2865 After generation of rtl, the compiler makes no further distinction
2866 between pointers and any other objects of this machine mode. */
2868 #define Pmode (TARGET_LONG64 ? DImode : SImode)
2870 /* A function address in a call instruction
2871 is a word address (for indexing purposes)
2872 so give the MEM rtx a words's mode. */
2874 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
2876 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2877 memset, instead of the BSD functions bcopy and bzero. */
2879 #if defined(MIPS_SYSV) || defined(OSF_OS)
2880 #define TARGET_MEM_FUNCTIONS
2881 #endif
2883 \f
2884 /* A part of a C `switch' statement that describes the relative
2885 costs of constant RTL expressions. It must contain `case'
2886 labels for expression codes `const_int', `const', `symbol_ref',
2887 `label_ref' and `const_double'. Each case must ultimately reach
2888 a `return' statement to return the relative cost of the use of
2889 that kind of constant value in an expression. The cost may
2890 depend on the precise value of the constant, which is available
2891 for examination in X.
2893 CODE is the expression code--redundant, since it can be obtained
2894 with `GET_CODE (X)'. */
2896 #define CONST_COSTS(X,CODE,OUTER_CODE) \
2897 case CONST_INT: \
2898 /* Always return 0, since we don't have different sized \
2899 instructions, hence different costs according to Richard \
2901 return 0; \
2902 \
2903 case LABEL_REF: \
2904 return COSTS_N_INSNS (2); \
2905 \
2906 case CONST: \
2907 { \
2908 rtx offset = const0_rtx; \
2909 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
2910 \
2911 if (GET_CODE (symref) == LABEL_REF) \
2912 return COSTS_N_INSNS (2); \
2913 \
2914 if (GET_CODE (symref) != SYMBOL_REF) \
2915 return COSTS_N_INSNS (4); \
2916 \
2918 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
2919 return COSTS_N_INSNS (2); \
2920 \
2921 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2922 } \
2923 \
2924 case SYMBOL_REF: \
2925 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2926 \
2927 case CONST_DOUBLE: \
2928 { \
2929 rtx high, low; \
2930 split_double (X, &high, &low); \
2931 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
2932 || low == CONST0_RTX (GET_MODE (low))) \
2933 ? 2 : 4); \
2934 }
2936 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2937 This can be used, for example, to indicate how costly a multiply
2938 instruction is. In writing this macro, you can use the construct
2939 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2941 This macro is optional; do not define it if the default cost
2942 assumptions are adequate for the target machine.
2944 If -mdebugd is used, change the multiply cost to 2, so multiply by
2945 a constant isn't converted to a series of shifts. This helps
2946 strength reduction, and also makes it easier to identify what the
2947 compiler is doing. */
2949 /* ??? Fix this to be right for the R8000. */
2950 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2951 case MEM: \
2952 { \
2953 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2954 if (simple_memory_operand (X, GET_MODE (X))) \
2955 return COSTS_N_INSNS (num_words); \
2956 \
2957 return COSTS_N_INSNS (2*num_words); \
2958 } \
2959 \
2960 case FFS: \
2961 return COSTS_N_INSNS (6); \
2962 \
2963 case NOT: \
2964 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
2965 \
2966 case AND: \
2967 case IOR: \
2968 case XOR: \
2969 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2970 return COSTS_N_INSNS (2); \
2971 \
2972 return COSTS_N_INSNS (1); \
2973 \
2974 case ASHIFT: \
2975 case ASHIFTRT: \
2976 case LSHIFTRT: \
2977 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2978 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
2979 \
2980 return COSTS_N_INSNS (1); \
2981 \
2982 case ABS: \
2983 { \
2984 enum machine_mode xmode = GET_MODE (X); \
2985 if (xmode == SFmode || xmode == DFmode) \
2986 return COSTS_N_INSNS (1); \
2987 \
2988 return COSTS_N_INSNS (4); \
2989 } \
2990 \
2991 case PLUS: \
2992 case MINUS: \
2993 { \
2994 enum machine_mode xmode = GET_MODE (X); \
2995 if (xmode == SFmode || xmode == DFmode) \
2996 { \
2997 if (mips_cpu == PROCESSOR_R3000 \
2998 || mips_cpu == PROCESSOR_R3900) \
2999 return COSTS_N_INSNS (2); \
3000 else if (mips_cpu == PROCESSOR_R6000) \
3001 return COSTS_N_INSNS (3); \
3002 else \
3003 return COSTS_N_INSNS (6); \
3004 } \
3005 \
3006 if (xmode == DImode && !TARGET_64BIT) \
3007 return COSTS_N_INSNS (4); \
3008 \
3009 return COSTS_N_INSNS (1); \
3010 } \
3011 \
3012 case NEG: \
3013 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 4 : 1); \
3014 \
3015 case MULT: \
3016 { \
3017 enum machine_mode xmode = GET_MODE (X); \
3018 if (xmode == SFmode) \
3019 { \
3020 if (mips_cpu == PROCESSOR_R3000 \
3021 || mips_cpu == PROCESSOR_R3900 \
3022 || mips_cpu == PROCESSOR_R5000) \
3023 return COSTS_N_INSNS (4); \
3024 else if (mips_cpu == PROCESSOR_R6000) \
3025 return COSTS_N_INSNS (5); \
3026 else \
3027 return COSTS_N_INSNS (7); \
3028 } \
3029 \
3030 if (xmode == DFmode) \
3031 { \
3032 if (mips_cpu == PROCESSOR_R3000 \
3033 || mips_cpu == PROCESSOR_R3900 \
3034 || mips_cpu == PROCESSOR_R5000) \
3035 return COSTS_N_INSNS (5); \
3036 else if (mips_cpu == PROCESSOR_R6000) \
3037 return COSTS_N_INSNS (6); \
3038 else \
3039 return COSTS_N_INSNS (8); \
3040 } \
3041 \
3042 if (mips_cpu == PROCESSOR_R3000) \
3043 return COSTS_N_INSNS (12); \
3044 else if (mips_cpu == PROCESSOR_R3900) \
3045 return COSTS_N_INSNS (2); \
3046 else if (mips_cpu == PROCESSOR_R6000) \
3047 return COSTS_N_INSNS (17); \
3048 else if (mips_cpu == PROCESSOR_R5000) \
3049 return COSTS_N_INSNS (5); \
3050 else \
3051 return COSTS_N_INSNS (10); \
3052 } \
3053 \
3054 case DIV: \
3055 case MOD: \
3056 { \
3057 enum machine_mode xmode = GET_MODE (X); \
3058 if (xmode == SFmode) \
3059 { \
3060 if (mips_cpu == PROCESSOR_R3000 \
3061 || mips_cpu == PROCESSOR_R3900) \
3062 return COSTS_N_INSNS (12); \
3063 else if (mips_cpu == PROCESSOR_R6000) \
3064 return COSTS_N_INSNS (15); \
3065 else \
3066 return COSTS_N_INSNS (23); \
3067 } \
3068 \
3069 if (xmode == DFmode) \
3070 { \
3071 if (mips_cpu == PROCESSOR_R3000 \
3072 || mips_cpu == PROCESSOR_R3900) \
3073 return COSTS_N_INSNS (19); \
3074 else if (mips_cpu == PROCESSOR_R6000) \
3075 return COSTS_N_INSNS (16); \
3076 else \
3077 return COSTS_N_INSNS (36); \
3078 } \
3079 } \
3081 \
3082 case UDIV: \
3083 case UMOD: \
3084 if (mips_cpu == PROCESSOR_R3000 \
3085 || mips_cpu == PROCESSOR_R3900) \
3086 return COSTS_N_INSNS (35); \
3087 else if (mips_cpu == PROCESSOR_R6000) \
3088 return COSTS_N_INSNS (38); \
3089 else if (mips_cpu == PROCESSOR_R5000) \
3090 return COSTS_N_INSNS (36); \
3091 else \
3092 return COSTS_N_INSNS (69); \
3093 \
3094 case SIGN_EXTEND: \
3095 /* A sign extend from SImode to DImode in 64 bit mode is often \
3096 zero instructions, because the result can often be used \
3098 if (TARGET_64BIT && GET_MODE (X) == DImode \
3099 && GET_MODE (XEXP (X, 0)) == SImode) \
3100 return COSTS_N_INSNS (1); \
3101 else \
3102 return COSTS_N_INSNS (2); \
3103 \
3104 case ZERO_EXTEND: \
3105 if (TARGET_64BIT && GET_MODE (X) == DImode \
3106 && GET_MODE (XEXP (X, 0)) == SImode) \
3107 return COSTS_N_INSNS (2); \
3108 else \
3109 return COSTS_N_INSNS (1);
3111 /* An expression giving the cost of an addressing mode that
3112 contains ADDRESS. If not defined, the cost is computed from the
3113 form of the ADDRESS expression and the `CONST_COSTS' values.
3115 For most CISC machines, the default cost is a good approximation
3116 of the true cost of the addressing mode. However, on RISC
3117 machines, all instructions normally have the same length and
3118 execution time. Hence all addresses will have equal costs.
3120 In cases where more than one form of an address is known, the
3121 form with the lowest cost will be used. If multiple forms have
3122 the same, lowest, cost, the one that is the most complex will be
3123 used.
3125 For example, suppose an address that is equal to the sum of a
3126 register and a constant is used twice in the same basic block.
3127 When this macro is not defined, the address will be computed in
3128 a register and memory references will be indirect through that
3129 register. On machines where the cost of the addressing mode
3130 containing the sum is no higher than that of a simple indirect
3131 reference, this will produce an additional instruction and
3132 possibly require an additional register. Proper specification
3133 of this macro eliminates this overhead for such machines.
3135 Similar use of this macro is made in strength reduction of loops.
3137 ADDRESS need not be valid as an address. In such a case, the
3138 cost is not relevant and can be any value; invalid addresses
3139 need not be assigned a different cost.
3141 On machines where an address involving more than one register is
3142 as cheap as an address computation involving only one register,
3143 defining `ADDRESS_COST' to reflect this can cause two registers
3144 to be live over a region of code where only one would have been
3145 if `ADDRESS_COST' were not defined in that manner. This effect
3146 should be considered in the definition of this macro.
3147 Equivalent costs should probably only be given to addresses with
3148 different numbers of registers on machines with lots of registers.
3150 This macro will normally either not be defined or be defined as
3151 a constant. */
3153 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3155 /* A C expression for the cost of moving data from a register in
3156 class FROM to one in class TO. The classes are expressed using
3157 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3158 the default; other values are interpreted relative to that.
3160 It is not required that the cost always equal 2 when FROM is the
3161 same as TO; on some machines it is expensive to move between
3162 registers if they are not general registers.
3164 If reload sees an insn consisting of a single `set' between two
3165 hard registers, and if `REGISTER_MOVE_COST' applied to their
3166 classes returns a value of 2, reload does not check to ensure
3167 that the constraints of the insn are met. Setting a cost of
3168 other than 2 will allow reload to verify that the constraints are
3169 met. You should do this if the `movM' pattern's constraints do
3170 not allow such copying. */
3172 #define REGISTER_MOVE_COST(FROM, TO) \
3173 ((FROM) == GR_REGS && (TO) == GR_REGS ? 2 \
3174 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3175 : (FROM) == GR_REGS && (TO) == FP_REGS ? 4 \
3176 : (FROM) == FP_REGS && (TO) == GR_REGS ? 4 \
3177 : (((FROM) == HI_REG || (FROM) == LO_REG \
3178 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3179 && (TO) == GR_REGS) ? 6 \
3180 : (((TO) == HI_REG || (TO) == LO_REG \
3181 || (TO) == MD_REGS || (FROM) == HILO_REG) \
3182 && (FROM) == GR_REGS) ? 6 \
3183 : (FROM) == ST_REGS && (TO) == GR_REGS ? 4 \
3184 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3185 : 12)
3187 /* ??? Fix this to be right for the R8000. */
3188 #define MEMORY_MOVE_COST(MODE) \
3189 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3191 /* A C expression for the cost of a branch instruction. A value of
3192 1 is the default; other values are interpreted relative to that. */
3194 /* ??? Fix this to be right for the R8000. */
3195 #define BRANCH_COST \
3196 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
3198 /* A C statement (sans semicolon) to update the integer variable COST
3199 based on the relationship between INSN that is dependent on
3200 DEP_INSN through the dependence LINK. The default is to make no
3201 adjustment to COST. On the MIPS, ignore the cost of anti- and
3202 output-dependencies. */
3204 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3205 if (REG_NOTE_KIND (LINK) != 0) \
3207 \f
3208 /* Optionally define this if you have added predicates to
3209 `MACHINE.c'. This macro is called within an initializer of an
3210 array of structures. The first field in the structure is the
3211 name of a predicate and the second field is an array of rtl
3212 codes. For each predicate, list all rtl codes that can be in
3213 expressions matched by the predicate. The list should have a
3214 trailing comma. Here is an example of two entries in the list
3215 for a typical RISC machine:
3217 #define PREDICATE_CODES \
3218 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3219 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3221 Defining this macro does not affect the generated code (however,
3222 incorrect definitions that omit an rtl code that may be matched
3223 by the predicate can cause the compiler to malfunction).
3224 Instead, it allows the table built by `genrecog' to be more
3225 compact and efficient, thus speeding up the compiler. The most
3226 important predicates to include in the list specified by this
3227 macro are thoses used in the most insn patterns. */
3229 #define PREDICATE_CODES \
3241 LTU, LEU }}, \
3245 SYMBOL_REF, LABEL_REF, SUBREG, \
3246 REG, MEM}}, \
3248 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3249 MEM, SIGN_EXTEND }}, \
3252 SIGN_EXTEND }}, \
3254 SIGN_EXTEND }}, \
3256 SIGN_EXTEND }}, \
3258 SYMBOL_REF, LABEL_REF, SUBREG, \
3259 REG, SIGN_EXTEND }}, \
3262 \f
3263 /* If defined, a C statement to be executed just prior to the
3264 output of assembler code for INSN, to modify the extracted
3265 operands so they will be output differently.
3267 Here the argument OPVEC is the vector containing the operands
3268 extracted from INSN, and NOPERANDS is the number of elements of
3269 the vector which contain meaningful data for this insn. The
3270 contents of this vector are what will be used to convert the
3271 insn template into assembler code, so you can change the
3272 assembler output by changing the contents of the vector.
3274 We use it to check if the current insn needs a nop in front of it
3275 because of load delays, and also to update the delay slot
3276 statistics. */
3278 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3279 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3281 \f
3282 /* Control the assembler format that we output. */
3284 /* Output at beginning of assembler file.
3285 If we are optimizing to use the global pointer, create a temporary
3286 file to hold all of the text stuff, and write it out to the end.
3287 This is needed because the MIPS assembler is evidently one pass,
3288 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3289 declaration when the code is processed, it generates a two
3290 instruction sequence. */
3292 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3294 /* Output to assembler file text saying following lines
3295 may contain character constants, extra white space, comments, etc. */
3299 /* Output to assembler file text saying following lines
3300 no longer contain unusual constructs. */
3304 /* How to refer to registers in assembler output.
3305 This sequence is indexed by compiler's hard-register-number (see above).
3307 In order to support the two different conventions for register names,
3308 we use the name of a table set up in mips.c, which is overwritten
3309 if -mrnames is used. */
3311 #define REGISTER_NAMES \
3312 { \
3313 &mips_reg_names[ 0][0], \
3314 &mips_reg_names[ 1][0], \
3315 &mips_reg_names[ 2][0], \
3316 &mips_reg_names[ 3][0], \
3317 &mips_reg_names[ 4][0], \
3318 &mips_reg_names[ 5][0], \
3319 &mips_reg_names[ 6][0], \
3320 &mips_reg_names[ 7][0], \
3321 &mips_reg_names[ 8][0], \
3322 &mips_reg_names[ 9][0], \
3323 &mips_reg_names[10][0], \
3324 &mips_reg_names[11][0], \
3325 &mips_reg_names[12][0], \
3326 &mips_reg_names[13][0], \
3327 &mips_reg_names[14][0], \
3328 &mips_reg_names[15][0], \
3329 &mips_reg_names[16][0], \
3330 &mips_reg_names[17][0], \
3331 &mips_reg_names[18][0], \
3332 &mips_reg_names[19][0], \
3333 &mips_reg_names[20][0], \
3334 &mips_reg_names[21][0], \
3335 &mips_reg_names[22][0], \
3336 &mips_reg_names[23][0], \
3337 &mips_reg_names[24][0], \
3338 &mips_reg_names[25][0], \
3339 &mips_reg_names[26][0], \
3340 &mips_reg_names[27][0], \
3341 &mips_reg_names[28][0], \
3342 &mips_reg_names[29][0], \
3343 &mips_reg_names[30][0], \
3344 &mips_reg_names[31][0], \
3345 &mips_reg_names[32][0], \
3346 &mips_reg_names[33][0], \
3347 &mips_reg_names[34][0], \
3348 &mips_reg_names[35][0], \
3349 &mips_reg_names[36][0], \
3350 &mips_reg_names[37][0], \
3351 &mips_reg_names[38][0], \
3352 &mips_reg_names[39][0], \
3353 &mips_reg_names[40][0], \
3354 &mips_reg_names[41][0], \
3355 &mips_reg_names[42][0], \
3356 &mips_reg_names[43][0], \
3357 &mips_reg_names[44][0], \
3358 &mips_reg_names[45][0], \
3359 &mips_reg_names[46][0], \
3360 &mips_reg_names[47][0], \
3361 &mips_reg_names[48][0], \
3362 &mips_reg_names[49][0], \
3363 &mips_reg_names[50][0], \
3364 &mips_reg_names[51][0], \
3365 &mips_reg_names[52][0], \
3366 &mips_reg_names[53][0], \
3367 &mips_reg_names[54][0], \
3368 &mips_reg_names[55][0], \
3369 &mips_reg_names[56][0], \
3370 &mips_reg_names[57][0], \
3371 &mips_reg_names[58][0], \
3372 &mips_reg_names[59][0], \
3373 &mips_reg_names[60][0], \
3374 &mips_reg_names[61][0], \
3375 &mips_reg_names[62][0], \
3376 &mips_reg_names[63][0], \
3377 &mips_reg_names[64][0], \
3378 &mips_reg_names[65][0], \
3379 &mips_reg_names[66][0], \
3380 &mips_reg_names[67][0], \
3381 &mips_reg_names[68][0], \
3382 &mips_reg_names[69][0], \
3383 &mips_reg_names[70][0], \
3384 &mips_reg_names[71][0], \
3385 &mips_reg_names[72][0], \
3386 &mips_reg_names[73][0], \
3387 &mips_reg_names[74][0], \
3388 &mips_reg_names[75][0], \
3389 }
3391 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3392 So define this for it. */
3393 #define DEBUG_REGISTER_NAMES \
3394 { \
3405 }
3407 /* If defined, a C initializer for an array of structures
3408 containing a name and a register number. This macro defines
3409 additional names for hard registers, thus allowing the `asm'
3410 option in declarations to refer to registers using alternate
3411 names.
3413 We define both names for the integer registers here. */
3415 #define ADDITIONAL_REGISTER_NAMES \
3416 { \
3484 }
3486 /* Define results of standard character escape sequences. */
3487 #define TARGET_BELL 007
3488 #define TARGET_BS 010
3489 #define TARGET_TAB 011
3490 #define TARGET_NEWLINE 012
3491 #define TARGET_VT 013
3492 #define TARGET_FF 014
3493 #define TARGET_CR 015
3495 /* A C compound statement to output to stdio stream STREAM the
3496 assembler syntax for an instruction operand X. X is an RTL
3497 expression.
3499 CODE is a value that can be used to specify one of several ways
3500 of printing the operand. It is used when identical operands
3501 must be printed differently depending on the context. CODE
3502 comes from the `%' specification that was used to request
3503 printing of the operand. If the specification was just `%DIGIT'
3504 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3505 is the ASCII code for LTR.
3507 If X is a register, this macro should print the register's name.
3508 The names can be found in an array `reg_names' whose type is
3509 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3511 When the machine description has a specification `%PUNCT' (a `%'
3512 followed by a punctuation character), this macro is called with
3513 a null pointer for X and the punctuation character for CODE.
3515 See mips.c for the MIPS specific codes. */
3517 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3519 /* A C expression which evaluates to true if CODE is a valid
3520 punctuation character for use in the `PRINT_OPERAND' macro. If
3521 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3522 punctuation characters (except for the standard one, `%') are
3523 used in this way. */
3525 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3527 /* A C compound statement to output to stdio stream STREAM the
3528 assembler syntax for an instruction operand that is a memory
3529 reference whose address is ADDR. ADDR is an RTL expression.
3531 On some machines, the syntax for a symbolic address depends on
3532 the section that the address refers to. On these machines,
3533 define the macro `ENCODE_SECTION_INFO' to store the information
3534 into the `symbol_ref', and then check for it here. */
3536 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3539 /* A C statement, to be executed after all slot-filler instructions
3540 have been output. If necessary, call `dbr_sequence_length' to
3541 determine the number of slots filled in a sequence (zero if not
3542 currently outputting a sequence), to decide how many no-ops to
3543 output, or whatever.
3545 Don't define this macro if it has nothing to do, but it is
3546 helpful in reading assembly output if the extent of the delay
3547 sequence is made explicit (e.g. with white space).
3549 Note that output routines for instructions with delay slots must
3550 be prepared to deal with not being output as part of a sequence
3551 (i.e. when the scheduling pass is not run, or when no slot
3552 fillers could be found.) The variable `final_sequence' is null
3553 when not processing a sequence, otherwise it contains the
3554 `sequence' rtx being output. */
3556 #define DBR_OUTPUT_SEQEND(STREAM) \
3557 do \
3558 { \
3559 if (set_nomacro > 0 && --set_nomacro == 0) \
3561 \
3562 if (set_noreorder > 0 && --set_noreorder == 0) \
3564 \
3565 dslots_jump_filled++; \
3567 } \
3568 while (0)
3571 /* How to tell the debugger about changes of source files. Note, the
3572 mips ECOFF format cannot deal with changes of files inside of
3573 functions, which means the output of parser generators like bison
3574 is generally not debuggable without using the -l switch. Lose,
3575 lose, lose. Silicon graphics seems to want all .file's hardwired
3576 to 1. */
3578 #ifndef SET_FILE_NUMBER
3579 #define SET_FILE_NUMBER() ++num_source_filenames
3580 #endif
3582 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3583 mips_output_filename (STREAM, NAME)
3585 /* This is defined so that it can be overridden in iris6.h. */
3586 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3587 do \
3588 { \
3590 output_quoted_string (STREAM, NAME); \
3592 } \
3593 while (0)
3595 /* This is how to output a note the debugger telling it the line number
3596 to which the following sequence of instructions corresponds.
3597 Silicon graphics puts a label after each .loc. */
3599 #ifndef LABEL_AFTER_LOC
3600 #define LABEL_AFTER_LOC(STREAM)
3601 #endif
3603 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3604 mips_output_lineno (STREAM, LINE)
3606 /* The MIPS implementation uses some labels for it's own purpose. The
3607 following lists what labels are created, and are all formed by the
3608 pattern $L[a-z].*. The machine independent portion of GCC creates
3609 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3611 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3612 $Lb[0-9]+ Begin blocks for MIPS debug support
3613 $Lc[0-9]+ Label for use in s<xx> operation.
3614 $Le[0-9]+ End blocks for MIPS debug support
3615 $Lp\..+ Half-pic labels. */
3617 /* This is how to output the definition of a user-level label named NAME,
3618 such as the label on a static function or variable NAME.
3620 If we are optimizing the gp, remember that this label has been put
3621 out, so we know not to emit an .extern for it in mips_asm_file_end.
3622 We use one of the common bits in the IDENTIFIER tree node for this,
3623 since those bits seem to be unused, and we don't have any method
3624 of getting the decl nodes from the name. */
3626 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3627 do { \
3628 assemble_name (STREAM, NAME); \
3630 } while (0)
3633 /* A C statement (sans semicolon) to output to the stdio stream
3634 STREAM any text necessary for declaring the name NAME of an
3635 initialized variable which is being defined. This macro must
3636 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3637 The argument DECL is the `VAR_DECL' tree node representing the
3638 variable.
3640 If this macro is not defined, then the variable name is defined
3641 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3643 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3644 do \
3645 { \
3647 HALF_PIC_DECLARE (NAME); \
3648 } \
3649 while (0)
3652 /* This is how to output a command to make the user-level label named NAME
3653 defined for reference from other files. */
3655 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3656 do { \
3658 assemble_name (STREAM, NAME); \
3660 } while (0)
3662 /* This says how to define a global common symbol. */
3664 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3667 /* This says how to define a local common symbol (ie, not visible to
3668 linker). */
3670 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3674 /* This says how to output an external. It would be possible not to
3675 output anything and let undefined symbol become external. However
3676 the assembler uses length information on externals to allocate in
3677 data/sdata bss/sbss, thereby saving exec time. */
3679 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3680 mips_output_external(STREAM,DECL,NAME)
3682 /* This says what to print at the end of the assembly file */
3683 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3686 /* This is how to declare a function name. The actual work of
3687 emitting the label is moved to function_prologue, so that we can
3688 get the line number correctly emitted before the .ent directive,
3689 and after any .file directives.
3691 Also, switch files if we are optimizing the global pointer. */
3693 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
3694 { \
3695 extern FILE *asm_out_text_file; \
3696 if (TARGET_GP_OPT) \
3697 { \
3698 STREAM = asm_out_text_file; \
3699 /* ??? text_section gets called too soon. If the previous \
3700 function is in a special section and we're not, we have \
3701 to switch back to the text section. We can't call \
3703 /* ??? See varasm.c. There are other things that get output \
3705 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
3707 } \
3708 \
3709 HALF_PIC_DECLARE (NAME); \
3710 }
3712 /* This is how to output an internal numbered label where
3713 PREFIX is the class of label and NUM is the number within the class. */
3715 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
3718 /* This is how to store into the string LABEL
3719 the symbol_ref name of an internal numbered label where
3720 PREFIX is the class of label and NUM is the number within the class.
3721 This is suitable for output with `assemble_name'. */
3723 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3726 /* This is how to output an assembler line defining a `double' constant. */
3728 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
3729 mips_output_double (STREAM, VALUE)
3732 /* This is how to output an assembler line defining a `float' constant. */
3734 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3735 mips_output_float (STREAM, VALUE)
3738 /* This is how to output an assembler line defining an `int' constant. */
3740 #define ASM_OUTPUT_INT(STREAM,VALUE) \
3741 do { \
3743 output_addr_const (STREAM, (VALUE)); \
3745 } while (0)
3747 /* Likewise for 64 bit, `char' and `short' constants. */
3749 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
3750 do { \
3751 if (TARGET_64BIT) \
3752 { \
3754 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
3755 /* We can't use 'X' for negative numbers, because then we won't \
3757 output_addr_const (STREAM, VALUE); \
3758 else \
3759 /* We must use 'X', because otherwise LONG_MIN will print as \
3763 } \
3764 else \
3765 { \
3766 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
3767 UNITS_PER_WORD, 1); \
3768 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
3769 UNITS_PER_WORD, 1); \
3770 } \
3771 } while (0)
3773 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3774 { \
3776 output_addr_const (STREAM, (VALUE)); \
3778 }
3780 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3781 { \
3783 output_addr_const (STREAM, (VALUE)); \
3785 }
3787 /* This is how to output an assembler line for a numeric constant byte. */
3789 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3792 /* This is how to output an element of a case-vector that is absolute. */
3794 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3797 LOCAL_LABEL_PREFIX, \
3798 VALUE)
3800 /* This is how to output an element of a case-vector that is relative.
3801 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3802 TARGET_EMBEDDED_PIC). */
3804 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3805 do { \
3806 if (TARGET_EMBEDDED_PIC) \
3809 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3810 else if (mips_abi == ABI_32) \
3813 LOCAL_LABEL_PREFIX, VALUE); \
3814 else \
3817 LOCAL_LABEL_PREFIX, VALUE); \
3818 } while (0)
3820 /* When generating embedded PIC code we want to put the jump table in
3821 the .text section. In all other cases, we want to put the jump
3822 table in the .rdata section. Unfortunately, we can't use
3823 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3824 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3825 section if appropriate. */
3826 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3827 do { \
3828 if (TARGET_EMBEDDED_PIC) \
3829 text_section (); \
3830 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
3831 } while (0)
3833 /* This is how to output an assembler line
3834 that says to advance the location counter
3835 to a multiple of 2**LOG bytes. */
3837 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3838 { \
3839 int mask = (1 << (LOG)) - 1; \
3841 }
3843 /* This is how to output an assembler line to to advance the location
3844 counter by SIZE bytes. */
3846 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3849 /* This is how to output a string. */
3850 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3851 do { \
3852 register int i, c, len = (LEN), cur_pos = 17; \
3853 register unsigned char *string = (unsigned char *)(STRING); \
3855 for (i = 0; i < len; i++) \
3856 { \
3857 register int c = string[i]; \
3858 \
3859 switch (c) \
3860 { \
3864 putc (c, (STREAM)); \
3865 cur_pos += 2; \
3866 break; \
3867 \
3868 case TARGET_NEWLINE: \
3870 if (i+1 < len \
3872 || c == TARGET_TAB)) \
3874 else \
3875 cur_pos += 2; \
3876 break; \
3877 \
3878 case TARGET_TAB: \
3880 cur_pos += 2; \
3881 break; \
3882 \
3883 case TARGET_FF: \
3885 cur_pos += 2; \
3886 break; \
3887 \
3888 case TARGET_BS: \
3890 cur_pos += 2; \
3891 break; \
3892 \
3893 case TARGET_CR: \
3895 cur_pos += 2; \
3896 break; \
3897 \
3898 default: \
3900 { \
3901 putc (c, (STREAM)); \
3902 cur_pos++; \
3903 } \
3904 else \
3905 { \
3907 cur_pos += 4; \
3908 } \
3909 } \
3910 \
3911 if (cur_pos > 72 && i+1 < len) \
3912 { \
3913 cur_pos = 17; \
3915 } \
3916 } \
3918 } while (0)
3920 /* Handle certain cpp directives used in header files on sysV. */
3921 #define SCCS_DIRECTIVE
3923 /* Output #ident as a in the read-only data section. */
3924 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3925 { \
3926 char *p = STRING; \
3927 int size = strlen (p) + 1; \
3928 rdata_section (); \
3929 assemble_string (p, size); \
3930 }
3931 \f
3932 /* Default to -G 8 */
3933 #ifndef MIPS_DEFAULT_GVALUE
3934 #define MIPS_DEFAULT_GVALUE 8
3935 #endif
3937 /* Define the strings to put out for each section in the object file. */
3942 #define READONLY_DATA_SECTION rdata_section
3943 #define SMALL_DATA_SECTION sdata_section
3945 /* What other sections we support other than the normal .data/.text. */
3947 #define EXTRA_SECTIONS in_sdata, in_rdata
3949 /* Define the additional functions to select our additional sections. */
3951 /* on the MIPS it is not a good idea to put constants in the text
3952 section, since this defeats the sdata/data mechanism. This is
3953 especially true when -O is used. In this case an effort is made to
3954 address with faster (gp) register relative addressing, which can
3955 only get at sdata and sbss items (there is no stext !!) However,
3956 if the constant is too large for sdata, and it's readonly, it
3957 will go into the .rdata section. */
3959 #define EXTRA_SECTION_FUNCTIONS \
3960 void \
3961 sdata_section () \
3962 { \
3963 if (in_section != in_sdata) \
3964 { \
3966 in_section = in_sdata; \
3967 } \
3968 } \
3969 \
3970 void \
3971 rdata_section () \
3972 { \
3973 if (in_section != in_rdata) \
3974 { \
3976 in_section = in_rdata; \
3977 } \
3978 }
3980 /* Given a decl node or constant node, choose the section to output it in
3981 and select that section. */
3983 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
3985 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
3987 \f
3988 /* Store in OUTPUT a string (made with alloca) containing
3989 an assembler-name for a local static variable named NAME.
3990 LABELNO is an integer which is different for each call. */
3992 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3993 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3996 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3997 do \
3998 { \
4001 reg_names[STACK_POINTER_REGNUM], \
4002 reg_names[STACK_POINTER_REGNUM], \
4004 reg_names[REGNO], \
4005 reg_names[STACK_POINTER_REGNUM]); \
4006 } \
4007 while (0)
4009 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4010 do \
4011 { \
4012 if (! set_noreorder) \
4014 \
4015 dslots_load_total++; \
4016 dslots_load_filled++; \
4019 reg_names[REGNO], \
4020 reg_names[STACK_POINTER_REGNUM], \
4022 reg_names[STACK_POINTER_REGNUM], \
4023 reg_names[STACK_POINTER_REGNUM]); \
4024 \
4025 if (! set_noreorder) \
4027 } \
4028 while (0)
4030 /* Define the parentheses used to group arithmetic operations
4031 in assembler code. */
4036 /* How to start an assembler comment.
4037 The leading space is important (the mips native assembler requires it). */
4038 #ifndef ASM_COMMENT_START
4040 #endif
4041 \f
4043 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4044 and mips-tdump.c to print them out.
4046 These must match the corresponding definitions in gdb/mipsread.c.
4047 Unfortunately, gcc and gdb do not currently share any directories. */
4049 #define CODE_MASK 0x8F300
4050 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4051 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4052 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4054 \f
4055 /* Default definitions for size_t and ptrdiff_t. */
4057 #ifndef SIZE_TYPE
4058 #define NO_BUILTIN_SIZE_TYPE
4060 #endif
4062 #ifndef PTRDIFF_TYPE
4063 #define NO_BUILTIN_PTRDIFF_TYPE
4065 #endif
4067 /* See mips_expand_prologue's use of loadgp for when this should be
4068 true. */
4070 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && mips_abi != ABI_32)