gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 88, 92-97, 1998 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_regnotes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #ifdef __STDC__
  79 #include <stdarg.h>
  80 #else
  81 #include <varargs.h>
  82 #endif
  83
  84 /* Must precede rtl.h for FFS.  */
  85 #include <stdio.h>
  86
  87 #include "rtl.h"
  88 #include "flags.h"
  89 #include "regs.h"
  90 #include "hard-reg-set.h"
  91 #include "expr.h"
  92 #include "basic-block.h"
  93 #include "insn-config.h"
  94 #include "insn-flags.h"
  95 #include "insn-codes.h"
  96 #include "insn-attr.h"
  97 #include "recog.h"
  98 #include "real.h"
  99
 100 /* It is not safe to use ordinary gen_lowpart in combine.
 101    Use gen_lowpart_for_combine instead.  See comments there.  */
 102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
 103
 104 /* Number of attempts to combine instructions in this function.  */
 105
 106 static int combine_attempts;
 107
 108 /* Number of attempts that got as far as substitution in this function.  */
 109
 110 static int combine_merges;
 111
 112 /* Number of instructions combined with added SETs in this function.  */
 113
 114 static int combine_extras;
 115
 116 /* Number of instructions combined in this function.  */
 117
 118 static int combine_successes;
 119
 120 /* Totals over entire compilation.  */
 121
 122 static int total_attempts, total_merges, total_extras, total_successes;
 123
 124 /* Define a default value for REVERSIBLE_CC_MODE.
 125    We can never assume that a condition code mode is safe to reverse unless
 126    the md tells us so.  */
 127 #ifndef REVERSIBLE_CC_MODE
 128 #define REVERSIBLE_CC_MODE(MODE) 0
 129 #endif
 130 \f
 131 /* Vector mapping INSN_UIDs to cuids.
 132    The cuids are like uids but increase monotonically always.
 133    Combine always uses cuids so that it can compare them.
 134    But actually renumbering the uids, which we used to do,
 135    proves to be a bad idea because it makes it hard to compare
 136    the dumps produced by earlier passes with those from later passes.  */
 137
 138 static int *uid_cuid;
 139 static int max_uid_cuid;
 140
 141 /* Get the cuid of an insn.  */
 142
 143 #define INSN_CUID(INSN) \
 144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 145
 146 /* Maximum register number, which is the size of the tables below.  */
 147
 148 static int combine_max_regno;
 149
 150 /* Record last point of death of (hard or pseudo) register n.  */
 151
 152 static rtx *reg_last_death;
 153
 154 /* Record last point of modification of (hard or pseudo) register n.  */
 155
 156 static rtx *reg_last_set;
 157
 158 /* Record the cuid of the last insn that invalidated memory
 159    (anything that writes memory, and subroutine calls, but not pushes).  */
 160
 161 static int mem_last_set;
 162
 163 /* Record the cuid of the last CALL_INSN
 164    so we can tell whether a potential combination crosses any calls.  */
 165
 166 static int last_call_cuid;
 167
 168 /* When `subst' is called, this is the insn that is being modified
 169    (by combining in a previous insn).  The PATTERN of this insn
 170    is still the old pattern partially modified and it should not be
 171    looked at, but this may be used to examine the successors of the insn
 172    to judge whether a simplification is valid.  */
 173
 174 static rtx subst_insn;
 175
 176 /* This is an insn that belongs before subst_insn, but is not currently
 177    on the insn chain.  */
 178
 179 static rtx subst_prev_insn;
 180
 181 /* This is the lowest CUID that `subst' is currently dealing with.
 182    get_last_value will not return a value if the register was set at or
 183    after this CUID.  If not for this mechanism, we could get confused if
 184    I2 or I1 in try_combine were an insn that used the old value of a register
 185    to obtain a new value.  In that case, we might erroneously get the
 186    new value of the register when we wanted the old one.  */
 187
 188 static int subst_low_cuid;
 189
 190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 191    must consider all these registers to be always live.  */
 192
 193 static HARD_REG_SET newpat_used_regs;
 194
 195 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 196    insn is the earlier than I2 or I3, combine should rescan starting at
 197    that location.  */
 198
 199 static rtx added_links_insn;
 200
 201 /* Basic block number of the block in which we are performing combines.  */
 202 static int this_basic_block;
 203 \f
 204 /* The next group of arrays allows the recording of the last value assigned
 205    to (hard or pseudo) register n.  We use this information to see if a
 206    operation being processed is redundant given a prior operation performed
 207    on the register.  For example, an `and' with a constant is redundant if
 208    all the zero bits are already known to be turned off.
 209
 210    We use an approach similar to that used by cse, but change it in the
 211    following ways:
 212
 213    (1) We do not want to reinitialize at each label.
 214    (2) It is useful, but not critical, to know the actual value assigned
 215        to a register.  Often just its form is helpful.
 216
 217    Therefore, we maintain the following arrays:
 218
 219    reg_last_set_value           the last value assigned
 220    reg_last_set_label           records the value of label_tick when the
 221                                 register was assigned
 222    reg_last_set_table_tick      records the value of label_tick when a
 223                                 value using the register is assigned
 224    reg_last_set_invalid         set to non-zero when it is not valid
 225                                 to use the value of this register in some
 226                                 register's value
 227
 228    To understand the usage of these tables, it is important to understand
 229    the distinction between the value in reg_last_set_value being valid
 230    and the register being validly contained in some other expression in the
 231    table.
 232
 233    Entry I in reg_last_set_value is valid if it is non-zero, and either
 234    reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
 235
 236    Register I may validly appear in any expression returned for the value
 237    of another register if reg_n_sets[i] is 1.  It may also appear in the
 238    value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
 239    reg_last_set_invalid[j] is zero.
 240
 241    If an expression is found in the table containing a register which may
 242    not validly appear in an expression, the register is replaced by
 243    something that won't match, (clobber (const_int 0)).
 244
 245    reg_last_set_invalid[i] is set non-zero when register I is being assigned
 246    to and reg_last_set_table_tick[i] == label_tick.  */
 247
 248 /* Record last value assigned to (hard or pseudo) register n.  */
 249
 250 static rtx *reg_last_set_value;
 251
 252 /* Record the value of label_tick when the value for register n is placed in
 253    reg_last_set_value[n].  */
 254
 255 static int *reg_last_set_label;
 256
 257 /* Record the value of label_tick when an expression involving register n
 258    is placed in reg_last_set_value.  */
 259
 260 static int *reg_last_set_table_tick;
 261
 262 /* Set non-zero if references to register n in expressions should not be
 263    used.  */
 264
 265 static char *reg_last_set_invalid;
 266
 267 /* Incremented for each label.  */
 268
 269 static int label_tick;
 270
 271 /* Some registers that are set more than once and used in more than one
 272    basic block are nevertheless always set in similar ways.  For example,
 273    a QImode register may be loaded from memory in two places on a machine
 274    where byte loads zero extend.
 275
 276    We record in the following array what we know about the nonzero
 277    bits of a register, specifically which bits are known to be zero.
 278
 279    If an entry is zero, it means that we don't know anything special.  */
 280
 281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
 282
 283 /* Mode used to compute significance in reg_nonzero_bits.  It is the largest
 284    integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 285
 286 static enum machine_mode nonzero_bits_mode;
 287
 288 /* Nonzero if we know that a register has some leading bits that are always
 289    equal to the sign bit.  */
 290
 291 static char *reg_sign_bit_copies;
 292
 293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
 294    It is zero while computing them and after combine has completed.  This
 295    former test prevents propagating values based on previously set values,
 296    which can be incorrect if a variable is modified in a loop.  */
 297
 298 static int nonzero_sign_valid;
 299
 300 /* These arrays are maintained in parallel with reg_last_set_value
 301    and are used to store the mode in which the register was last set,
 302    the bits that were known to be zero when it was last set, and the
 303    number of sign bits copies it was known to have when it was last set.  */
 304
 305 static enum machine_mode *reg_last_set_mode;
 306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
 307 static char *reg_last_set_sign_bit_copies;
 308 \f
 309 /* Record one modification to rtl structure
 310    to be undone by storing old_contents into *where.
 311    is_int is 1 if the contents are an int.  */
 312
 313 struct undo
 314 {
 315   struct undo *next;
 316   int is_int;
 317   union {rtx r; int i;} old_contents;
 318   union {rtx *r; int *i;} where;
 319 };
 320
 321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 322    num_undo says how many are currently recorded.
 323
 324    storage is nonzero if we must undo the allocation of new storage.
 325    The value of storage is what to pass to obfree.
 326
 327    other_insn is nonzero if we have modified some other insn in the process
 328    of working on subst_insn.  It must be verified too.
 329
 330    previous_undos is the value of undobuf.undos when we started processing
 331    this substitution.  This will prevent gen_rtx_combine from re-used a piece
 332    from the previous expression.  Doing so can produce circular rtl
 333    structures.  */
 334
 335 struct undobuf
 336 {
 337   char *storage;
 338   struct undo *undos;
 339   struct undo *frees;
 340   struct undo *previous_undos;
 341   rtx other_insn;
 342 };
 343
 344 static struct undobuf undobuf;
 345
 346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 347    insn.  The substitution can be undone by undo_all.  If INTO is already
 348    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 349    also call SUBST, we have to compute it before we put anything into
 350    the undo table.  */
 351
 352 #define SUBST(INTO, NEWVAL)  \
 353  do { rtx _new = (NEWVAL);                                      \
 354       struct undo *_buf;                                        \
 355                                                                 \
 356       if (undobuf.frees)                                        \
 357         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 358       else                                                      \
 359         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 360                                                                 \
 361       _buf->is_int = 0;                                         \
 362       _buf->where.r = &INTO;                                    \
 363       _buf->old_contents.r = INTO;                              \
 364       INTO = _new;                                              \
 365       if (_buf->old_contents.r == INTO)                         \
 366         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 367       else                                                      \
 368         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 369     } while (0)
 370
 371 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 372    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 373    not safe.  */
 374
 375 #define SUBST_INT(INTO, NEWVAL)  \
 376  do { struct undo *_buf;                                        \
 377                                                                 \
 378       if (undobuf.frees)                                        \
 379         _buf = undobuf.frees, undobuf.frees = _buf->next;       \
 380       else                                                      \
 381         _buf = (struct undo *) xmalloc (sizeof (struct undo));  \
 382                                                                 \
 383       _buf->is_int = 1;                                         \
 384       _buf->where.i = (int *) &INTO;                            \
 385       _buf->old_contents.i = INTO;                              \
 386       INTO = NEWVAL;                                            \
 387       if (_buf->old_contents.i == INTO)                         \
 388         _buf->next = undobuf.frees, undobuf.frees = _buf;       \
 389       else                                                      \
 390         _buf->next = undobuf.undos, undobuf.undos = _buf;       \
 391      } while (0)
 392
 393 /* Number of times the pseudo being substituted for
 394    was found and replaced.  */
 395
 396 static int n_occurrences;
 397
 398 static void init_reg_last_arrays        PROTO((void));
 399 static void setup_incoming_promotions   PROTO((void));
 400 static void set_nonzero_bits_and_sign_copies  PROTO((rtx, rtx));
 401 static int can_combine_p        PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
 402 static int combinable_i3pat     PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
 403 static rtx try_combine          PROTO((rtx, rtx, rtx));
 404 static void undo_all            PROTO((void));
 405 static rtx *find_split_point    PROTO((rtx *, rtx));
 406 static rtx subst                PROTO((rtx, rtx, rtx, int, int));
 407 static rtx simplify_rtx         PROTO((rtx, enum machine_mode, int, int));
 408 static rtx simplify_if_then_else  PROTO((rtx));
 409 static rtx simplify_set         PROTO((rtx));
 410 static rtx simplify_logical     PROTO((rtx, int));
 411 static rtx expand_compound_operation  PROTO((rtx));
 412 static rtx expand_field_assignment  PROTO((rtx));
 413 static rtx make_extraction      PROTO((enum machine_mode, rtx, int, rtx, int,
 414                                        int, int, int));
 415 static rtx extract_left_shift   PROTO((rtx, int));
 416 static rtx make_compound_operation  PROTO((rtx, enum rtx_code));
 417 static int get_pos_from_mask    PROTO((unsigned HOST_WIDE_INT, int *));
 418 static rtx force_to_mode        PROTO((rtx, enum machine_mode,
 419                                        unsigned HOST_WIDE_INT, rtx, int));
 420 static rtx if_then_else_cond    PROTO((rtx, rtx *, rtx *));
 421 static rtx known_cond           PROTO((rtx, enum rtx_code, rtx, rtx));
 422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
 423 static rtx make_field_assignment  PROTO((rtx));
 424 static rtx apply_distributive_law  PROTO((rtx));
 425 static rtx simplify_and_const_int  PROTO((rtx, enum machine_mode, rtx,
 426                                           unsigned HOST_WIDE_INT));
 427 static unsigned HOST_WIDE_INT nonzero_bits  PROTO((rtx, enum machine_mode));
 428 static int num_sign_bit_copies  PROTO((rtx, enum machine_mode));
 429 static int merge_outer_ops      PROTO((enum rtx_code *, HOST_WIDE_INT *,
 430                                        enum rtx_code, HOST_WIDE_INT,
 431                                        enum machine_mode, int *));
 432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
 433                                        rtx, int));
 434 static int recog_for_combine    PROTO((rtx *, rtx, rtx *, int *));
 435 static rtx gen_lowpart_for_combine  PROTO((enum machine_mode, rtx));
 436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
 437                                   ...));
 438 static rtx gen_binary           PROTO((enum rtx_code, enum machine_mode,
 439                                        rtx, rtx));
 440 static rtx gen_unary            PROTO((enum rtx_code, enum machine_mode,
 441                                        enum machine_mode, rtx));
 442 static enum rtx_code simplify_comparison  PROTO((enum rtx_code, rtx *, rtx *));
 443 static int reversible_comparison_p  PROTO((rtx));
 444 static void update_table_tick   PROTO((rtx));
 445 static void record_value_for_reg  PROTO((rtx, rtx, rtx));
 446 static void record_dead_and_set_regs_1  PROTO((rtx, rtx));
 447 static void record_dead_and_set_regs  PROTO((rtx));
 448 static int get_last_value_validate  PROTO((rtx *, rtx, int, int));
 449 static rtx get_last_value       PROTO((rtx));
 450 static int use_crosses_set_p    PROTO((rtx, int));
 451 static void reg_dead_at_p_1     PROTO((rtx, rtx));
 452 static int reg_dead_at_p        PROTO((rtx, rtx));
 453 static void move_deaths         PROTO((rtx, rtx, int, rtx, rtx *));
 454 static int reg_bitfield_target_p  PROTO((rtx, rtx));
 455 static void distribute_notes    PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
 456 static void distribute_links    PROTO((rtx));
 457 static void mark_used_regs_combine PROTO((rtx));
 458 static int insn_cuid            PROTO((rtx));
 459 \f
 460 /* Main entry point for combiner.  F is the first insn of the function.
 461    NREGS is the first unused pseudo-reg number.  */
 462
 463 void
 464 combine_instructions (f, nregs)
 465      rtx f;
 466      int nregs;
 467 {
 468   register rtx insn, next, prev;
 469   register int i;
 470   register rtx links, nextlinks;
 471
 472   combine_attempts = 0;
 473   combine_merges = 0;
 474   combine_extras = 0;
 475   combine_successes = 0;
 476   undobuf.undos = undobuf.previous_undos = 0;
 477
 478   combine_max_regno = nregs;
 479
 480   reg_nonzero_bits
 481     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 482   reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
 483
 484   bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 485   bzero (reg_sign_bit_copies, nregs * sizeof (char));
 486
 487   reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
 488   reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
 489   reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
 490   reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
 491   reg_last_set_label = (int *) alloca (nregs * sizeof (int));
 492   reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
 493   reg_last_set_mode
 494     = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
 495   reg_last_set_nonzero_bits
 496     = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
 497   reg_last_set_sign_bit_copies
 498     = (char *) alloca (nregs * sizeof (char));
 499
 500   init_reg_last_arrays ();
 501
 502   init_recog_no_volatile ();
 503
 504   /* Compute maximum uid value so uid_cuid can be allocated.  */
 505
 506   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 507     if (INSN_UID (insn) > i)
 508       i = INSN_UID (insn);
 509
 510   uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
 511   max_uid_cuid = i;
 512
 513   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 514
 515   /* Don't use reg_nonzero_bits when computing it.  This can cause problems
 516      when, for example, we have j <<= 1 in a loop.  */
 517
 518   nonzero_sign_valid = 0;
 519
 520   /* Compute the mapping from uids to cuids.
 521      Cuids are numbers assigned to insns, like uids,
 522      except that cuids increase monotonically through the code.
 523
 524      Scan all SETs and see if we can deduce anything about what
 525      bits are known to be zero for some registers and how many copies
 526      of the sign bit are known to exist for those registers.
 527
 528      Also set any known values so that we can use it while searching
 529      for what bits are known to be set.  */
 530
 531   label_tick = 1;
 532
 533   /* We need to initialize it here, because record_dead_and_set_regs may call
 534      get_last_value.  */
 535   subst_prev_insn = NULL_RTX;
 536
 537   setup_incoming_promotions ();
 538
 539   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 540     {
 541       uid_cuid[INSN_UID (insn)] = ++i;
 542       subst_low_cuid = i;
 543       subst_insn = insn;
 544
 545       if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 546         {
 547           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
 548           record_dead_and_set_regs (insn);
 549
 550 #ifdef AUTO_INC_DEC
 551           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 552             if (REG_NOTE_KIND (links) == REG_INC)
 553               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
 554 #endif
 555         }
 556
 557       if (GET_CODE (insn) == CODE_LABEL)
 558         label_tick++;
 559     }
 560
 561   nonzero_sign_valid = 1;
 562
 563   /* Now scan all the insns in forward order.  */
 564
 565   this_basic_block = -1;
 566   label_tick = 1;
 567   last_call_cuid = 0;
 568   mem_last_set = 0;
 569   init_reg_last_arrays ();
 570   setup_incoming_promotions ();
 571
 572   for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
 573     {
 574       next = 0;
 575
 576       /* If INSN starts a new basic block, update our basic block number.  */
 577       if (this_basic_block + 1 < n_basic_blocks
 578           && basic_block_head[this_basic_block + 1] == insn)
 579         this_basic_block++;
 580
 581       if (GET_CODE (insn) == CODE_LABEL)
 582         label_tick++;
 583
 584       else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
 585         {
 586           /* Try this insn with each insn it links back to.  */
 587
 588           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 589             if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
 590               goto retry;
 591
 592           /* Try each sequence of three linked insns ending with this one.  */
 593
 594           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 595             for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
 596                  nextlinks = XEXP (nextlinks, 1))
 597               if ((next = try_combine (insn, XEXP (links, 0),
 598                                        XEXP (nextlinks, 0))) != 0)
 599                 goto retry;
 600
 601 #ifdef HAVE_cc0
 602           /* Try to combine a jump insn that uses CC0
 603              with a preceding insn that sets CC0, and maybe with its
 604              logical predecessor as well.
 605              This is how we make decrement-and-branch insns.
 606              We need this special code because data flow connections
 607              via CC0 do not get entered in LOG_LINKS.  */
 608
 609           if (GET_CODE (insn) == JUMP_INSN
 610               && (prev = prev_nonnote_insn (insn)) != 0
 611               && GET_CODE (prev) == INSN
 612               && sets_cc0_p (PATTERN (prev)))
 613             {
 614               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 615                 goto retry;
 616
 617               for (nextlinks = LOG_LINKS (prev); nextlinks;
 618                    nextlinks = XEXP (nextlinks, 1))
 619                 if ((next = try_combine (insn, prev,
 620                                          XEXP (nextlinks, 0))) != 0)
 621                   goto retry;
 622             }
 623
 624           /* Do the same for an insn that explicitly references CC0.  */
 625           if (GET_CODE (insn) == INSN
 626               && (prev = prev_nonnote_insn (insn)) != 0
 627               && GET_CODE (prev) == INSN
 628               && sets_cc0_p (PATTERN (prev))
 629               && GET_CODE (PATTERN (insn)) == SET
 630               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 631             {
 632               if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
 633                 goto retry;
 634
 635               for (nextlinks = LOG_LINKS (prev); nextlinks;
 636                    nextlinks = XEXP (nextlinks, 1))
 637                 if ((next = try_combine (insn, prev,
 638                                          XEXP (nextlinks, 0))) != 0)
 639                   goto retry;
 640             }
 641
 642           /* Finally, see if any of the insns that this insn links to
 643              explicitly references CC0.  If so, try this insn, that insn,
 644              and its predecessor if it sets CC0.  */
 645           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 646             if (GET_CODE (XEXP (links, 0)) == INSN
 647                 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 648                 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 649                 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 650                 && GET_CODE (prev) == INSN
 651                 && sets_cc0_p (PATTERN (prev))
 652                 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
 653               goto retry;
 654 #endif
 655
 656           /* Try combining an insn with two different insns whose results it
 657              uses.  */
 658           for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 659             for (nextlinks = XEXP (links, 1); nextlinks;
 660                  nextlinks = XEXP (nextlinks, 1))
 661               if ((next = try_combine (insn, XEXP (links, 0),
 662                                        XEXP (nextlinks, 0))) != 0)
 663                 goto retry;
 664
 665           if (GET_CODE (insn) != NOTE)
 666             record_dead_and_set_regs (insn);
 667
 668         retry:
 669           ;
 670         }
 671     }
 672
 673   total_attempts += combine_attempts;
 674   total_merges += combine_merges;
 675   total_extras += combine_extras;
 676   total_successes += combine_successes;
 677
 678   nonzero_sign_valid = 0;
 679 }
 680
 681 /* Wipe the reg_last_xxx arrays in preparation for another pass.  */
 682
 683 static void
 684 init_reg_last_arrays ()
 685 {
 686   int nregs = combine_max_regno;
 687
 688   bzero ((char *) reg_last_death, nregs * sizeof (rtx));
 689   bzero ((char *) reg_last_set, nregs * sizeof (rtx));
 690   bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
 691   bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
 692   bzero ((char *) reg_last_set_label, nregs * sizeof (int));
 693   bzero (reg_last_set_invalid, nregs * sizeof (char));
 694   bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
 695   bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
 696   bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
 697 }
 698 \f
 699 /* Set up any promoted values for incoming argument registers.  */
 700
 701 static void
 702 setup_incoming_promotions ()
 703 {
 704 #ifdef PROMOTE_FUNCTION_ARGS
 705   int regno;
 706   rtx reg;
 707   enum machine_mode mode;
 708   int unsignedp;
 709   rtx first = get_insns ();
 710
 711   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 712     if (FUNCTION_ARG_REGNO_P (regno)
 713         && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
 714       record_value_for_reg (reg, first,
 715                             gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
 716                                      GET_MODE (reg),
 717                                      gen_rtx (CLOBBER, mode, const0_rtx)));
 718 #endif
 719 }
 720 \f
 721 /* Called via note_stores.  If X is a pseudo that is narrower than
 722    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
 723
 724    If we are setting only a portion of X and we can't figure out what
 725    portion, assume all bits will be used since we don't know what will
 726    be happening.
 727
 728    Similarly, set how many bits of X are known to be copies of the sign bit
 729    at all locations in the function.  This is the smallest number implied
 730    by any set of X.  */
 731
 732 static void
 733 set_nonzero_bits_and_sign_copies (x, set)
 734      rtx x;
 735      rtx set;
 736 {
 737   int num;
 738
 739   if (GET_CODE (x) == REG
 740       && REGNO (x) >= FIRST_PSEUDO_REGISTER
 741       /* If this register is undefined at the start of the file, we can't
 742          say what its contents were.  */
 743       && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
 744       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
 745     {
 746       if (set == 0 || GET_CODE (set) == CLOBBER)
 747         {
 748           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 749           reg_sign_bit_copies[REGNO (x)] = 1;
 750           return;
 751         }
 752
 753       /* If this is a complex assignment, see if we can convert it into a
 754          simple assignment.  */
 755       set = expand_field_assignment (set);
 756
 757       /* If this is a simple assignment, or we have a paradoxical SUBREG,
 758          set what we know about X.  */
 759
 760       if (SET_DEST (set) == x
 761           || (GET_CODE (SET_DEST (set)) == SUBREG
 762               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
 763                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
 764               && SUBREG_REG (SET_DEST (set)) == x))
 765         {
 766           rtx src = SET_SRC (set);
 767
 768 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
 769           /* If X is narrower than a word and SRC is a non-negative
 770              constant that would appear negative in the mode of X,
 771              sign-extend it for use in reg_nonzero_bits because some
 772              machines (maybe most) will actually do the sign-extension
 773              and this is the conservative approach.
 774
 775              ??? For 2.5, try to tighten up the MD files in this regard
 776              instead of this kludge.  */
 777
 778           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
 779               && GET_CODE (src) == CONST_INT
 780               && INTVAL (src) > 0
 781               && 0 != (INTVAL (src)
 782                        & ((HOST_WIDE_INT) 1
 783                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
 784             src = GEN_INT (INTVAL (src)
 785                            | ((HOST_WIDE_INT) (-1)
 786                               << GET_MODE_BITSIZE (GET_MODE (x))));
 787 #endif
 788
 789           reg_nonzero_bits[REGNO (x)]
 790             |= nonzero_bits (src, nonzero_bits_mode);
 791           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
 792           if (reg_sign_bit_copies[REGNO (x)] == 0
 793               || reg_sign_bit_copies[REGNO (x)] > num)
 794             reg_sign_bit_copies[REGNO (x)] = num;
 795         }
 796       else
 797         {
 798           reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
 799           reg_sign_bit_copies[REGNO (x)] = 1;
 800         }
 801     }
 802 }
 803 \f
 804 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
 805    insns that were previously combined into I3 or that will be combined
 806    into the merger of INSN and I3.
 807
 808    Return 0 if the combination is not allowed for any reason.
 809
 810    If the combination is allowed, *PDEST will be set to the single
 811    destination of INSN and *PSRC to the single source, and this function
 812    will return 1.  */
 813
 814 static int
 815 can_combine_p (insn, i3, pred, succ, pdest, psrc)
 816      rtx insn;
 817      rtx i3;
 818      rtx pred, succ;
 819      rtx *pdest, *psrc;
 820 {
 821   int i;
 822   rtx set = 0, src, dest;
 823   rtx p, link;
 824   int all_adjacent = (succ ? (next_active_insn (insn) == succ
 825                               && next_active_insn (succ) == i3)
 826                       : next_active_insn (insn) == i3);
 827
 828   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
 829      or a PARALLEL consisting of such a SET and CLOBBERs.
 830
 831      If INSN has CLOBBER parallel parts, ignore them for our processing.
 832      By definition, these happen during the execution of the insn.  When it
 833      is merged with another insn, all bets are off.  If they are, in fact,
 834      needed and aren't also supplied in I3, they may be added by
 835      recog_for_combine.  Otherwise, it won't match.
 836
 837      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
 838      note.
 839
 840      Get the source and destination of INSN.  If more than one, can't
 841      combine.  */
 842
 843   if (GET_CODE (PATTERN (insn)) == SET)
 844     set = PATTERN (insn);
 845   else if (GET_CODE (PATTERN (insn)) == PARALLEL
 846            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
 847     {
 848       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
 849         {
 850           rtx elt = XVECEXP (PATTERN (insn), 0, i);
 851
 852           switch (GET_CODE (elt))
 853             {
 854               /* We can ignore CLOBBERs.  */
 855             case CLOBBER:
 856               break;
 857
 858             case SET:
 859               /* Ignore SETs whose result isn't used but not those that
 860                  have side-effects.  */
 861               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
 862                   && ! side_effects_p (elt))
 863                 break;
 864
 865               /* If we have already found a SET, this is a second one and
 866                  so we cannot combine with this insn.  */
 867               if (set)
 868                 return 0;
 869
 870               set = elt;
 871               break;
 872
 873             default:
 874               /* Anything else means we can't combine.  */
 875               return 0;
 876             }
 877         }
 878
 879       if (set == 0
 880           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
 881              so don't do anything with it.  */
 882           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
 883         return 0;
 884     }
 885   else
 886     return 0;
 887
 888   if (set == 0)
 889     return 0;
 890
 891   set = expand_field_assignment (set);
 892   src = SET_SRC (set), dest = SET_DEST (set);
 893
 894   /* Don't eliminate a store in the stack pointer.  */
 895   if (dest == stack_pointer_rtx
 896       /* If we couldn't eliminate a field assignment, we can't combine.  */
 897       || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
 898       /* Don't combine with an insn that sets a register to itself if it has
 899          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
 900       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
 901       /* Can't merge a function call.  */
 902       || GET_CODE (src) == CALL
 903       /* Don't eliminate a function call argument.  */
 904       || (GET_CODE (i3) == CALL_INSN
 905           && (find_reg_fusage (i3, USE, dest)
 906               || (GET_CODE (dest) == REG
 907                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
 908                   && global_regs[REGNO (dest)])))
 909       /* Don't substitute into an incremented register.  */
 910       || FIND_REG_INC_NOTE (i3, dest)
 911       || (succ && FIND_REG_INC_NOTE (succ, dest))
 912       /* Don't combine the end of a libcall into anything.  */
 913       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
 914       /* Make sure that DEST is not used after SUCC but before I3.  */
 915       || (succ && ! all_adjacent
 916           && reg_used_between_p (dest, succ, i3))
 917       /* Make sure that the value that is to be substituted for the register
 918          does not use any registers whose values alter in between.  However,
 919          If the insns are adjacent, a use can't cross a set even though we
 920          think it might (this can happen for a sequence of insns each setting
 921          the same destination; reg_last_set of that register might point to
 922          a NOTE).  If INSN has a REG_EQUIV note, the register is always
 923          equivalent to the memory so the substitution is valid even if there
 924          are intervening stores.  Also, don't move a volatile asm or
 925          UNSPEC_VOLATILE across any other insns.  */
 926       || (! all_adjacent
 927           && (((GET_CODE (src) != MEM
 928                 || ! find_reg_note (insn, REG_EQUIV, src))
 929                && use_crosses_set_p (src, INSN_CUID (insn)))
 930               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
 931               || GET_CODE (src) == UNSPEC_VOLATILE))
 932       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
 933          better register allocation by not doing the combine.  */
 934       || find_reg_note (i3, REG_NO_CONFLICT, dest)
 935       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
 936       /* Don't combine across a CALL_INSN, because that would possibly
 937          change whether the life span of some REGs crosses calls or not,
 938          and it is a pain to update that information.
 939          Exception: if source is a constant, moving it later can't hurt.
 940          Accept that special case, because it helps -fforce-addr a lot.  */
 941       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
 942     return 0;
 943
 944   /* DEST must either be a REG or CC0.  */
 945   if (GET_CODE (dest) == REG)
 946     {
 947       /* If register alignment is being enforced for multi-word items in all
 948          cases except for parameters, it is possible to have a register copy
 949          insn referencing a hard register that is not allowed to contain the
 950          mode being copied and which would not be valid as an operand of most
 951          insns.  Eliminate this problem by not combining with such an insn.
 952
 953          Also, on some machines we don't want to extend the life of a hard
 954          register.
 955
 956          This is the same test done in can_combine except that we don't test
 957          if SRC is a CALL operation to permit a hard register with
 958          SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
 959          into account.  */
 960
 961       if (GET_CODE (src) == REG
 962           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
 963                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
 964               /* Don't extend the life of a hard register unless it is
 965                  user variable (if we have few registers) or it can't
 966                  fit into the desired register (meaning something special
 967                  is going on).
 968                  Also avoid substituting a return register into I3, because
 969                  reload can't handle a conflict with constraints of other
 970                  inputs.  */
 971               || (REGNO (src) < FIRST_PSEUDO_REGISTER
 972                   && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
 973                       || (SMALL_REGISTER_CLASSES
 974                           && ((! all_adjacent && ! REG_USERVAR_P (src))
 975                               || (FUNCTION_VALUE_REGNO_P (REGNO (src))
 976                                   && ! REG_USERVAR_P (src))))))))
 977         return 0;
 978     }
 979   else if (GET_CODE (dest) != CC0)
 980     return 0;
 981
 982   /* Don't substitute for a register intended as a clobberable operand.
 983      Similarly, don't substitute an expression containing a register that
 984      will be clobbered in I3.  */
 985   if (GET_CODE (PATTERN (i3)) == PARALLEL)
 986     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
 987       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
 988           && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
 989                                        src)
 990               || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
 991         return 0;
 992
 993   /* If INSN contains anything volatile, or is an `asm' (whether volatile
 994      or not), reject, unless nothing volatile comes between it and I3,
 995      with the exception of SUCC.  */
 996
 997   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
 998     for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
 999       if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1000           && p != succ && volatile_refs_p (PATTERN (p)))
1001         return 0;
1002
1003   /* If there are any volatile insns between INSN and I3, reject, because
1004      they might affect machine state.  */
1005
1006   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1007     if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1008         && p != succ && volatile_insn_p (PATTERN (p)))
1009       return 0;
1010
1011   /* If INSN or I2 contains an autoincrement or autodecrement,
1012      make sure that register is not used between there and I3,
1013      and not already used in I3 either.
1014      Also insist that I3 not be a jump; if it were one
1015      and the incremented register were spilled, we would lose.  */
1016
1017 #ifdef AUTO_INC_DEC
1018   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1019     if (REG_NOTE_KIND (link) == REG_INC
1020         && (GET_CODE (i3) == JUMP_INSN
1021             || reg_used_between_p (XEXP (link, 0), insn, i3)
1022             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1023       return 0;
1024 #endif
1025
1026 #ifdef HAVE_cc0
1027   /* Don't combine an insn that follows a CC0-setting insn.
1028      An insn that uses CC0 must not be separated from the one that sets it.
1029      We do, however, allow I2 to follow a CC0-setting insn if that insn
1030      is passed as I1; in that case it will be deleted also.
1031      We also allow combining in this case if all the insns are adjacent
1032      because that would leave the two CC0 insns adjacent as well.
1033      It would be more logical to test whether CC0 occurs inside I1 or I2,
1034      but that would be much slower, and this ought to be equivalent.  */
1035
1036   p = prev_nonnote_insn (insn);
1037   if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1038       && ! all_adjacent)
1039     return 0;
1040 #endif
1041
1042   /* If we get here, we have passed all the tests and the combination is
1043      to be allowed.  */
1044
1045   *pdest = dest;
1046   *psrc = src;
1047
1048   return 1;
1049 }
1050 \f
1051 /* Check if PAT is an insn - or a part of it - used to set up an
1052    argument for a function in a hard register.  */
1053
1054 static int
1055 sets_function_arg_p (pat)
1056      rtx pat;
1057 {
1058   int i;
1059   rtx inner_dest;
1060
1061   switch (GET_CODE (pat))
1062     {
1063     case INSN:
1064       return sets_function_arg_p (PATTERN (pat));
1065
1066     case PARALLEL:
1067       for (i = XVECLEN (pat, 0); --i >= 0;)
1068         if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1069           return 1;
1070
1071       break;
1072
1073     case SET:
1074       inner_dest = SET_DEST (pat);
1075       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1076              || GET_CODE (inner_dest) == SUBREG
1077              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1078         inner_dest = XEXP (inner_dest, 0);
1079
1080       return (GET_CODE (inner_dest) == REG
1081               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1082               && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1083     }
1084
1085   return 0;
1086 }
1087
1088 /* LOC is the location within I3 that contains its pattern or the component
1089    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1090
1091    One problem is if I3 modifies its output, as opposed to replacing it
1092    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1093    so would produce an insn that is not equivalent to the original insns.
1094
1095    Consider:
1096
1097          (set (reg:DI 101) (reg:DI 100))
1098          (set (subreg:SI (reg:DI 101) 0) <foo>)
1099
1100    This is NOT equivalent to:
1101
1102          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1103                     (set (reg:DI 101) (reg:DI 100))])
1104
1105    Not only does this modify 100 (in which case it might still be valid
1106    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1107
1108    We can also run into a problem if I2 sets a register that I1
1109    uses and I1 gets directly substituted into I3 (not via I2).  In that
1110    case, we would be getting the wrong value of I2DEST into I3, so we
1111    must reject the combination.  This case occurs when I2 and I1 both
1112    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1113    If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1114    of a SET must prevent combination from occurring.
1115
1116    On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1117    if the destination of a SET is a hard register that isn't a user
1118    variable.
1119
1120    Before doing the above check, we first try to expand a field assignment
1121    into a set of logical operations.
1122
1123    If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1124    we place a register that is both set and used within I3.  If more than one
1125    such register is detected, we fail.
1126
1127    Return 1 if the combination is valid, zero otherwise.  */
1128
1129 static int
1130 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1131      rtx i3;
1132      rtx *loc;
1133      rtx i2dest;
1134      rtx i1dest;
1135      int i1_not_in_src;
1136      rtx *pi3dest_killed;
1137 {
1138   rtx x = *loc;
1139
1140   if (GET_CODE (x) == SET)
1141     {
1142       rtx set = expand_field_assignment (x);
1143       rtx dest = SET_DEST (set);
1144       rtx src = SET_SRC (set);
1145       rtx inner_dest = dest, inner_src = src;
1146
1147       SUBST (*loc, set);
1148
1149       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1150              || GET_CODE (inner_dest) == SUBREG
1151              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1152         inner_dest = XEXP (inner_dest, 0);
1153
1154   /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1155      was added.  */
1156 #if 0
1157       while (GET_CODE (inner_src) == STRICT_LOW_PART
1158              || GET_CODE (inner_src) == SUBREG
1159              || GET_CODE (inner_src) == ZERO_EXTRACT)
1160         inner_src = XEXP (inner_src, 0);
1161
1162       /* If it is better that two different modes keep two different pseudos,
1163          avoid combining them.  This avoids producing the following pattern
1164          on a 386:
1165           (set (subreg:SI (reg/v:QI 21) 0)
1166                (lshiftrt:SI (reg/v:SI 20)
1167                    (const_int 24)))
1168          If that were made, reload could not handle the pair of
1169          reg 20/21, since it would try to get any GENERAL_REGS
1170          but some of them don't handle QImode.  */
1171
1172       if (rtx_equal_p (inner_src, i2dest)
1173           && GET_CODE (inner_dest) == REG
1174           && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1175         return 0;
1176 #endif
1177
1178       /* Check for the case where I3 modifies its output, as
1179          discussed above.  */
1180       if ((inner_dest != dest
1181            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1182                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1183
1184           /* This is the same test done in can_combine_p except that we
1185              allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1186              CALL operation. Moreover, we can't test all_adjacent; we don't
1187              have to, since this instruction will stay in place, thus we are
1188              not considering increasing the lifetime of INNER_DEST.
1189
1190              Also, if this insn sets a function argument, combining it with
1191              something that might need a spill could clobber a previous
1192              function argument; the all_adjacent test in can_combine_p also
1193              checks this; here, we do a more specific test for this case.  */
1194
1195           || (GET_CODE (inner_dest) == REG
1196               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1197               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1198                                         GET_MODE (inner_dest))
1199                  || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1200                      && ! REG_USERVAR_P (inner_dest)
1201                      && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1202                          || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1203                              && i3 != 0
1204                              && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1205           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1206         return 0;
1207
1208       /* If DEST is used in I3, it is being killed in this insn,
1209          so record that for later.
1210          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1211          STACK_POINTER_REGNUM, since these are always considered to be
1212          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1213       if (pi3dest_killed && GET_CODE (dest) == REG
1214           && reg_referenced_p (dest, PATTERN (i3))
1215           && REGNO (dest) != FRAME_POINTER_REGNUM
1216 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1217           && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1218 #endif
1219 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1220           && (REGNO (dest) != ARG_POINTER_REGNUM
1221               || ! fixed_regs [REGNO (dest)])
1222 #endif
1223           && REGNO (dest) != STACK_POINTER_REGNUM)
1224         {
1225           if (*pi3dest_killed)
1226             return 0;
1227
1228           *pi3dest_killed = dest;
1229         }
1230     }
1231
1232   else if (GET_CODE (x) == PARALLEL)
1233     {
1234       int i;
1235
1236       for (i = 0; i < XVECLEN (x, 0); i++)
1237         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1238                                 i1_not_in_src, pi3dest_killed))
1239           return 0;
1240     }
1241
1242   return 1;
1243 }
1244 \f
1245 /* Try to combine the insns I1 and I2 into I3.
1246    Here I1 and I2 appear earlier than I3.
1247    I1 can be zero; then we combine just I2 into I3.
1248
1249    It we are combining three insns and the resulting insn is not recognized,
1250    try splitting it into two insns.  If that happens, I2 and I3 are retained
1251    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1252    are pseudo-deleted.
1253
1254    Return 0 if the combination does not work.  Then nothing is changed.
1255    If we did the combination, return the insn at which combine should
1256    resume scanning.  */
1257
1258 static rtx
1259 try_combine (i3, i2, i1)
1260      register rtx i3, i2, i1;
1261 {
1262   /* New patterns for I3 and I3, respectively.  */
1263   rtx newpat, newi2pat = 0;
1264   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1265   int added_sets_1, added_sets_2;
1266   /* Total number of SETs to put into I3.  */
1267   int total_sets;
1268   /* Nonzero is I2's body now appears in I3.  */
1269   int i2_is_used;
1270   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1271   int insn_code_number, i2_code_number, other_code_number;
1272   /* Contains I3 if the destination of I3 is used in its source, which means
1273      that the old life of I3 is being killed.  If that usage is placed into
1274      I2 and not in I3, a REG_DEAD note must be made.  */
1275   rtx i3dest_killed = 0;
1276   /* SET_DEST and SET_SRC of I2 and I1.  */
1277   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1278   /* PATTERN (I2), or a copy of it in certain cases.  */
1279   rtx i2pat;
1280   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1281   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1282   int i1_feeds_i3 = 0;
1283   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1284   rtx new_i3_notes, new_i2_notes;
1285   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1286   int i3_subst_into_i2 = 0;
1287   /* Notes that I1, I2 or I3 is a MULT operation.  */
1288   int have_mult = 0;
1289   /* Number of clobbers of SCRATCH we had to add.  */
1290   int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1291
1292   int maxreg;
1293   rtx temp;
1294   register rtx link;
1295   int i;
1296
1297   /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1298      This can occur when flow deletes an insn that it has merged into an
1299      auto-increment address.  We also can't do anything if I3 has a
1300      REG_LIBCALL note since we don't want to disrupt the contiguity of a
1301      libcall.  */
1302
1303   if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1304       || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1305       || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1306       || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1307     return 0;
1308
1309   combine_attempts++;
1310
1311   undobuf.undos = undobuf.previous_undos = 0;
1312   undobuf.other_insn = 0;
1313
1314   /* Save the current high-water-mark so we can free storage if we didn't
1315      accept this combination.  */
1316   undobuf.storage = (char *) oballoc (0);
1317
1318   /* Reset the hard register usage information.  */
1319   CLEAR_HARD_REG_SET (newpat_used_regs);
1320
1321   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1322      code below, set I1 to be the earlier of the two insns.  */
1323   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1324     temp = i1, i1 = i2, i2 = temp;
1325
1326   added_links_insn = 0;
1327
1328   /* First check for one important special-case that the code below will
1329      not handle.  Namely, the case where I1 is zero, I2 has multiple sets,
1330      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1331      we may be able to replace that destination with the destination of I3.
1332      This occurs in the common code where we compute both a quotient and
1333      remainder into a structure, in which case we want to do the computation
1334      directly into the structure to avoid register-register copies.
1335
1336      We make very conservative checks below and only try to handle the
1337      most common cases of this.  For example, we only handle the case
1338      where I2 and I3 are adjacent to avoid making difficult register
1339      usage tests.  */
1340
1341   if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1342       && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1343       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1344       && (! SMALL_REGISTER_CLASSES
1345           || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1346               || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1347               || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1348       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1349       && GET_CODE (PATTERN (i2)) == PARALLEL
1350       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1351       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1352          below would need to check what is inside (and reg_overlap_mentioned_p
1353          doesn't support those codes anyway).  Don't allow those destinations;
1354          the resulting insn isn't likely to be recognized anyway.  */
1355       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1356       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1357       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1358                                     SET_DEST (PATTERN (i3)))
1359       && next_real_insn (i2) == i3)
1360     {
1361       rtx p2 = PATTERN (i2);
1362
1363       /* Make sure that the destination of I3,
1364          which we are going to substitute into one output of I2,
1365          is not used within another output of I2.  We must avoid making this:
1366          (parallel [(set (mem (reg 69)) ...)
1367                     (set (reg 69) ...)])
1368          which is not well-defined as to order of actions.
1369          (Besides, reload can't handle output reloads for this.)
1370
1371          The problem can also happen if the dest of I3 is a memory ref,
1372          if another dest in I2 is an indirect memory ref.  */
1373       for (i = 0; i < XVECLEN (p2, 0); i++)
1374         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1375              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1376             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1377                                         SET_DEST (XVECEXP (p2, 0, i))))
1378           break;
1379
1380       if (i == XVECLEN (p2, 0))
1381         for (i = 0; i < XVECLEN (p2, 0); i++)
1382           if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1383             {
1384               combine_merges++;
1385
1386               subst_insn = i3;
1387               subst_low_cuid = INSN_CUID (i2);
1388
1389               added_sets_2 = added_sets_1 = 0;
1390               i2dest = SET_SRC (PATTERN (i3));
1391
1392               /* Replace the dest in I2 with our dest and make the resulting
1393                  insn the new pattern for I3.  Then skip to where we
1394                  validate the pattern.  Everything was set up above.  */
1395               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1396                      SET_DEST (PATTERN (i3)));
1397
1398               newpat = p2;
1399               i3_subst_into_i2 = 1;
1400               goto validate_replacement;
1401             }
1402     }
1403
1404 #ifndef HAVE_cc0
1405   /* If we have no I1 and I2 looks like:
1406         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1407                    (set Y OP)])
1408      make up a dummy I1 that is
1409         (set Y OP)
1410      and change I2 to be
1411         (set (reg:CC X) (compare:CC Y (const_int 0)))
1412
1413      (We can ignore any trailing CLOBBERs.)
1414
1415      This undoes a previous combination and allows us to match a branch-and-
1416      decrement insn.  */
1417
1418   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1419       && XVECLEN (PATTERN (i2), 0) >= 2
1420       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1421       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1422           == MODE_CC)
1423       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1424       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1425       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1426       && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1427       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1428                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1429     {
1430       for (i =  XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1431         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1432           break;
1433
1434       if (i == 1)
1435         {
1436           /* We make I1 with the same INSN_UID as I2.  This gives it
1437              the same INSN_CUID for value tracking.  Our fake I1 will
1438              never appear in the insn stream so giving it the same INSN_UID
1439              as I2 will not cause a problem.  */
1440
1441           subst_prev_insn = i1
1442             = gen_rtx (INSN, VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1443                        XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, NULL_RTX);
1444
1445           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1446           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1447                  SET_DEST (PATTERN (i1)));
1448         }
1449     }
1450 #endif
1451
1452   /* Verify that I2 and I1 are valid for combining.  */
1453   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1454       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1455     {
1456       undo_all ();
1457       return 0;
1458     }
1459
1460   /* Record whether I2DEST is used in I2SRC and similarly for the other
1461      cases.  Knowing this will help in register status updating below.  */
1462   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1463   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1464   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1465
1466   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
1467      in I2SRC.  */
1468   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1469
1470   /* Ensure that I3's pattern can be the destination of combines.  */
1471   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1472                           i1 && i2dest_in_i1src && i1_feeds_i3,
1473                           &i3dest_killed))
1474     {
1475       undo_all ();
1476       return 0;
1477     }
1478
1479   /* See if any of the insns is a MULT operation.  Unless one is, we will
1480      reject a combination that is, since it must be slower.  Be conservative
1481      here.  */
1482   if (GET_CODE (i2src) == MULT
1483       || (i1 != 0 && GET_CODE (i1src) == MULT)
1484       || (GET_CODE (PATTERN (i3)) == SET
1485           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1486     have_mult = 1;
1487
1488   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1489      We used to do this EXCEPT in one case: I3 has a post-inc in an
1490      output operand.  However, that exception can give rise to insns like
1491         mov r3,(r3)+
1492      which is a famous insn on the PDP-11 where the value of r3 used as the
1493      source was model-dependent.  Avoid this sort of thing.  */
1494
1495 #if 0
1496   if (!(GET_CODE (PATTERN (i3)) == SET
1497         && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1498         && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1499         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1500             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1501     /* It's not the exception.  */
1502 #endif
1503 #ifdef AUTO_INC_DEC
1504     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1505       if (REG_NOTE_KIND (link) == REG_INC
1506           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1507               || (i1 != 0
1508                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1509         {
1510           undo_all ();
1511           return 0;
1512         }
1513 #endif
1514
1515   /* See if the SETs in I1 or I2 need to be kept around in the merged
1516      instruction: whenever the value set there is still needed past I3.
1517      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1518
1519      For the SET in I1, we have two cases:  If I1 and I2 independently
1520      feed into I3, the set in I1 needs to be kept around if I1DEST dies
1521      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
1522      in I1 needs to be kept around unless I1DEST dies or is set in either
1523      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
1524      I1DEST.  If so, we know I1 feeds into I2.  */
1525
1526   added_sets_2 = ! dead_or_set_p (i3, i2dest);
1527
1528   added_sets_1
1529     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1530                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1531
1532   /* If the set in I2 needs to be kept around, we must make a copy of
1533      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1534      PATTERN (I2), we are only substituting for the original I1DEST, not into
1535      an already-substituted copy.  This also prevents making self-referential
1536      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1537      I2DEST.  */
1538
1539   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1540            ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1541            : PATTERN (i2));
1542
1543   if (added_sets_2)
1544     i2pat = copy_rtx (i2pat);
1545
1546   combine_merges++;
1547
1548   /* Substitute in the latest insn for the regs set by the earlier ones.  */
1549
1550   maxreg = max_reg_num ();
1551
1552   subst_insn = i3;
1553
1554   /* It is possible that the source of I2 or I1 may be performing an
1555      unneeded operation, such as a ZERO_EXTEND of something that is known
1556      to have the high part zero.  Handle that case by letting subst look at
1557      the innermost one of them.
1558
1559      Another way to do this would be to have a function that tries to
1560      simplify a single insn instead of merging two or more insns.  We don't
1561      do this because of the potential of infinite loops and because
1562      of the potential extra memory required.  However, doing it the way
1563      we are is a bit of a kludge and doesn't catch all cases.
1564
1565      But only do this if -fexpensive-optimizations since it slows things down
1566      and doesn't usually win.  */
1567
1568   if (flag_expensive_optimizations)
1569     {
1570       /* Pass pc_rtx so no substitutions are done, just simplifications.
1571          The cases that we are interested in here do not involve the few
1572          cases were is_replaced is checked.  */
1573       if (i1)
1574         {
1575           subst_low_cuid = INSN_CUID (i1);
1576           i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1577         }
1578       else
1579         {
1580           subst_low_cuid = INSN_CUID (i2);
1581           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1582         }
1583
1584       undobuf.previous_undos = undobuf.undos;
1585     }
1586
1587 #ifndef HAVE_cc0
1588   /* Many machines that don't use CC0 have insns that can both perform an
1589      arithmetic operation and set the condition code.  These operations will
1590      be represented as a PARALLEL with the first element of the vector
1591      being a COMPARE of an arithmetic operation with the constant zero.
1592      The second element of the vector will set some pseudo to the result
1593      of the same arithmetic operation.  If we simplify the COMPARE, we won't
1594      match such a pattern and so will generate an extra insn.   Here we test
1595      for this case, where both the comparison and the operation result are
1596      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1597      I2SRC.  Later we will make the PARALLEL that contains I2.  */
1598
1599   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1600       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1601       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1602       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1603     {
1604       rtx *cc_use;
1605       enum machine_mode compare_mode;
1606
1607       newpat = PATTERN (i3);
1608       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1609
1610       i2_is_used = 1;
1611
1612 #ifdef EXTRA_CC_MODES
1613       /* See if a COMPARE with the operand we substituted in should be done
1614          with the mode that is currently being used.  If not, do the same
1615          processing we do in `subst' for a SET; namely, if the destination
1616          is used only once, try to replace it with a register of the proper
1617          mode and also replace the COMPARE.  */
1618       if (undobuf.other_insn == 0
1619           && (cc_use = find_single_use (SET_DEST (newpat), i3,
1620                                         &undobuf.other_insn))
1621           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1622                                               i2src, const0_rtx))
1623               != GET_MODE (SET_DEST (newpat))))
1624         {
1625           int regno = REGNO (SET_DEST (newpat));
1626           rtx new_dest = gen_rtx (REG, compare_mode, regno);
1627
1628           if (regno < FIRST_PSEUDO_REGISTER
1629               || (REG_N_SETS (regno) == 1 && ! added_sets_2
1630                   && ! REG_USERVAR_P (SET_DEST (newpat))))
1631             {
1632               if (regno >= FIRST_PSEUDO_REGISTER)
1633                 SUBST (regno_reg_rtx[regno], new_dest);
1634
1635               SUBST (SET_DEST (newpat), new_dest);
1636               SUBST (XEXP (*cc_use, 0), new_dest);
1637               SUBST (SET_SRC (newpat),
1638                      gen_rtx_combine (COMPARE, compare_mode,
1639                                       i2src, const0_rtx));
1640             }
1641           else
1642             undobuf.other_insn = 0;
1643         }
1644 #endif
1645     }
1646   else
1647 #endif
1648     {
1649       n_occurrences = 0;                /* `subst' counts here */
1650
1651       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1652          need to make a unique copy of I2SRC each time we substitute it
1653          to avoid self-referential rtl.  */
1654
1655       subst_low_cuid = INSN_CUID (i2);
1656       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1657                       ! i1_feeds_i3 && i1dest_in_i1src);
1658       undobuf.previous_undos = undobuf.undos;
1659
1660       /* Record whether i2's body now appears within i3's body.  */
1661       i2_is_used = n_occurrences;
1662     }
1663
1664   /* If we already got a failure, don't try to do more.  Otherwise,
1665      try to substitute in I1 if we have it.  */
1666
1667   if (i1 && GET_CODE (newpat) != CLOBBER)
1668     {
1669       /* Before we can do this substitution, we must redo the test done
1670          above (see detailed comments there) that ensures  that I1DEST
1671          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
1672
1673       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1674                               0, NULL_PTR))
1675         {
1676           undo_all ();
1677           return 0;
1678         }
1679
1680       n_occurrences = 0;
1681       subst_low_cuid = INSN_CUID (i1);
1682       newpat = subst (newpat, i1dest, i1src, 0, 0);
1683       undobuf.previous_undos = undobuf.undos;
1684     }
1685
1686   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
1687      to count all the ways that I2SRC and I1SRC can be used.  */
1688   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1689        && i2_is_used + added_sets_2 > 1)
1690       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1691           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1692               > 1))
1693       /* Fail if we tried to make a new register (we used to abort, but there's
1694          really no reason to).  */
1695       || max_reg_num () != maxreg
1696       /* Fail if we couldn't do something and have a CLOBBER.  */
1697       || GET_CODE (newpat) == CLOBBER
1698       /* Fail if this new pattern is a MULT and we didn't have one before
1699          at the outer level.  */
1700       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1701           && ! have_mult))
1702     {
1703       undo_all ();
1704       return 0;
1705     }
1706
1707   /* If the actions of the earlier insns must be kept
1708      in addition to substituting them into the latest one,
1709      we must make a new PARALLEL for the latest insn
1710      to hold additional the SETs.  */
1711
1712   if (added_sets_1 || added_sets_2)
1713     {
1714       combine_extras++;
1715
1716       if (GET_CODE (newpat) == PARALLEL)
1717         {
1718           rtvec old = XVEC (newpat, 0);
1719           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1720           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1721           bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1722                  sizeof (old->elem[0]) * old->num_elem);
1723         }
1724       else
1725         {
1726           rtx old = newpat;
1727           total_sets = 1 + added_sets_1 + added_sets_2;
1728           newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1729           XVECEXP (newpat, 0, 0) = old;
1730         }
1731
1732      if (added_sets_1)
1733        XVECEXP (newpat, 0, --total_sets)
1734          = (GET_CODE (PATTERN (i1)) == PARALLEL
1735             ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1736
1737      if (added_sets_2)
1738         {
1739           /* If there is no I1, use I2's body as is.  We used to also not do
1740              the subst call below if I2 was substituted into I3,
1741              but that could lose a simplification.  */
1742           if (i1 == 0)
1743             XVECEXP (newpat, 0, --total_sets) = i2pat;
1744           else
1745             /* See comment where i2pat is assigned.  */
1746             XVECEXP (newpat, 0, --total_sets)
1747               = subst (i2pat, i1dest, i1src, 0, 0);
1748         }
1749     }
1750
1751   /* We come here when we are replacing a destination in I2 with the
1752      destination of I3.  */
1753  validate_replacement:
1754
1755   /* Note which hard regs this insn has as inputs.  */
1756   mark_used_regs_combine (newpat);
1757
1758   /* Is the result of combination a valid instruction?  */
1759   insn_code_number
1760     = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1761
1762   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1763      the second SET's destination is a register that is unused.  In that case,
1764      we just need the first SET.   This can occur when simplifying a divmod
1765      insn.  We *must* test for this case here because the code below that
1766      splits two independent SETs doesn't handle this case correctly when it
1767      updates the register status.  Also check the case where the first
1768      SET's destination is unused.  That would not cause incorrect code, but
1769      does cause an unneeded insn to remain.  */
1770
1771   if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1772       && XVECLEN (newpat, 0) == 2
1773       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1774       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1775       && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1776       && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1777       && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1778       && asm_noperands (newpat) < 0)
1779     {
1780       newpat = XVECEXP (newpat, 0, 0);
1781       insn_code_number
1782         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1783     }
1784
1785   else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1786            && XVECLEN (newpat, 0) == 2
1787            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1788            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1789            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1790            && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1791            && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1792            && asm_noperands (newpat) < 0)
1793     {
1794       newpat = XVECEXP (newpat, 0, 1);
1795       insn_code_number
1796         = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1797     }
1798
1799   /* If we were combining three insns and the result is a simple SET
1800      with no ASM_OPERANDS that wasn't recognized, try to split it into two
1801      insns.  There are two ways to do this.  It can be split using a
1802      machine-specific method (like when you have an addition of a large
1803      constant) or by combine in the function find_split_point.  */
1804
1805   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1806       && asm_noperands (newpat) < 0)
1807     {
1808       rtx m_split, *split;
1809       rtx ni2dest = i2dest;
1810
1811       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
1812          use I2DEST as a scratch register will help.  In the latter case,
1813          convert I2DEST to the mode of the source of NEWPAT if we can.  */
1814
1815       m_split = split_insns (newpat, i3);
1816
1817       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1818          inputs of NEWPAT.  */
1819
1820       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1821          possible to try that as a scratch reg.  This would require adding
1822          more code to make it work though.  */
1823
1824       if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1825         {
1826           /* If I2DEST is a hard register or the only use of a pseudo,
1827              we can change its mode.  */
1828           if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1829               && GET_MODE (SET_DEST (newpat)) != VOIDmode
1830               && GET_CODE (i2dest) == REG
1831               && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1832                   || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1833                       && ! REG_USERVAR_P (i2dest))))
1834             ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1835                                REGNO (i2dest));
1836
1837           m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1838                                           gen_rtvec (2, newpat,
1839                                                      gen_rtx (CLOBBER,
1840                                                               VOIDmode,
1841                                                               ni2dest))),
1842                                  i3);
1843         }
1844
1845       if (m_split && GET_CODE (m_split) == SEQUENCE
1846           && XVECLEN (m_split, 0) == 2
1847           && (next_real_insn (i2) == i3
1848               || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1849                                       INSN_CUID (i2))))
1850         {
1851           rtx i2set, i3set;
1852           rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1853           newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1854
1855           i3set = single_set (XVECEXP (m_split, 0, 1));
1856           i2set = single_set (XVECEXP (m_split, 0, 0));
1857
1858           /* In case we changed the mode of I2DEST, replace it in the
1859              pseudo-register table here.  We can't do it above in case this
1860              code doesn't get executed and we do a split the other way.  */
1861
1862           if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1863             SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1864
1865           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1866                                               &i2_scratches);
1867
1868           /* If I2 or I3 has multiple SETs, we won't know how to track
1869              register status, so don't use these insns.  If I2's destination
1870              is used between I2 and I3, we also can't use these insns.  */
1871
1872           if (i2_code_number >= 0 && i2set && i3set
1873               && (next_real_insn (i2) == i3
1874                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1875             insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1876                                                   &i3_scratches);
1877           if (insn_code_number >= 0)
1878             newpat = newi3pat;
1879
1880           /* It is possible that both insns now set the destination of I3.
1881              If so, we must show an extra use of it.  */
1882
1883           if (insn_code_number >= 0)
1884             {
1885               rtx new_i3_dest = SET_DEST (i3set);
1886               rtx new_i2_dest = SET_DEST (i2set);
1887
1888               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1889                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1890                      || GET_CODE (new_i3_dest) == SUBREG)
1891                 new_i3_dest = XEXP (new_i3_dest, 0);
1892
1893               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1894                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1895                      || GET_CODE (new_i2_dest) == SUBREG)
1896                 new_i2_dest = XEXP (new_i2_dest, 0);
1897
1898               if (GET_CODE (new_i3_dest) == REG
1899                   && GET_CODE (new_i2_dest) == REG
1900                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1901                 REG_N_SETS (REGNO (new_i2_dest))++;
1902             }
1903         }
1904
1905       /* If we can split it and use I2DEST, go ahead and see if that
1906          helps things be recognized.  Verify that none of the registers
1907          are set between I2 and I3.  */
1908       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1909 #ifdef HAVE_cc0
1910           && GET_CODE (i2dest) == REG
1911 #endif
1912           /* We need I2DEST in the proper mode.  If it is a hard register
1913              or the only use of a pseudo, we can change its mode.  */
1914           && (GET_MODE (*split) == GET_MODE (i2dest)
1915               || GET_MODE (*split) == VOIDmode
1916               || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1917               || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1918                   && ! REG_USERVAR_P (i2dest)))
1919           && (next_real_insn (i2) == i3
1920               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1921           /* We can't overwrite I2DEST if its value is still used by
1922              NEWPAT.  */
1923           && ! reg_referenced_p (i2dest, newpat))
1924         {
1925           rtx newdest = i2dest;
1926           enum rtx_code split_code = GET_CODE (*split);
1927           enum machine_mode split_mode = GET_MODE (*split);
1928
1929           /* Get NEWDEST as a register in the proper mode.  We have already
1930              validated that we can do this.  */
1931           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1932             {
1933               newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1934
1935               if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1936                 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1937             }
1938
1939           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1940              an ASHIFT.  This can occur if it was inside a PLUS and hence
1941              appeared to be a memory address.  This is a kludge.  */
1942           if (split_code == MULT
1943               && GET_CODE (XEXP (*split, 1)) == CONST_INT
1944               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1945             {
1946               SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1947                                               XEXP (*split, 0), GEN_INT (i)));
1948               /* Update split_code because we may not have a multiply
1949                  anymore.  */
1950               split_code = GET_CODE (*split);
1951             }
1952
1953 #ifdef INSN_SCHEDULING
1954           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1955              be written as a ZERO_EXTEND.  */
1956           if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1957             SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1958                                             XEXP (*split, 0)));
1959 #endif
1960
1961           newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1962           SUBST (*split, newdest);
1963           i2_code_number
1964             = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1965
1966           /* If the split point was a MULT and we didn't have one before,
1967              don't use one now.  */
1968           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1969             insn_code_number
1970               = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1971         }
1972     }
1973
1974   /* Check for a case where we loaded from memory in a narrow mode and
1975      then sign extended it, but we need both registers.  In that case,
1976      we have a PARALLEL with both loads from the same memory location.
1977      We can split this into a load from memory followed by a register-register
1978      copy.  This saves at least one insn, more if register allocation can
1979      eliminate the copy.
1980
1981      We cannot do this if the destination of the second assignment is
1982      a register that we have already assumed is zero-extended.  Similarly
1983      for a SUBREG of such a register.  */
1984
1985   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1986            && GET_CODE (newpat) == PARALLEL
1987            && XVECLEN (newpat, 0) == 2
1988            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1989            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1990            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1991            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1992                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1993            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1994                                    INSN_CUID (i2))
1995            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1996            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1997            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1998                  (GET_CODE (temp) == REG
1999                   && reg_nonzero_bits[REGNO (temp)] != 0
2000                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2001                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2002                   && (reg_nonzero_bits[REGNO (temp)]
2003                       != GET_MODE_MASK (word_mode))))
2004            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2005                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2006                      (GET_CODE (temp) == REG
2007                       && reg_nonzero_bits[REGNO (temp)] != 0
2008                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2009                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2010                       && (reg_nonzero_bits[REGNO (temp)]
2011                           != GET_MODE_MASK (word_mode)))))
2012            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2013                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2014            && ! find_reg_note (i3, REG_UNUSED,
2015                                SET_DEST (XVECEXP (newpat, 0, 0))))
2016     {
2017       rtx ni2dest;
2018
2019       newi2pat = XVECEXP (newpat, 0, 0);
2020       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2021       newpat = XVECEXP (newpat, 0, 1);
2022       SUBST (SET_SRC (newpat),
2023              gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2024       i2_code_number
2025         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2026
2027       if (i2_code_number >= 0)
2028         insn_code_number
2029           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2030
2031       if (insn_code_number >= 0)
2032         {
2033           rtx insn;
2034           rtx link;
2035
2036           /* If we will be able to accept this, we have made a change to the
2037              destination of I3.  This can invalidate a LOG_LINKS pointing
2038              to I3.  No other part of combine.c makes such a transformation.
2039
2040              The new I3 will have a destination that was previously the
2041              destination of I1 or I2 and which was used in i2 or I3.  Call
2042              distribute_links to make a LOG_LINK from the next use of
2043              that destination.  */
2044
2045           PATTERN (i3) = newpat;
2046           distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2047
2048           /* I3 now uses what used to be its destination and which is
2049              now I2's destination.  That means we need a LOG_LINK from
2050              I3 to I2.  But we used to have one, so we still will.
2051
2052              However, some later insn might be using I2's dest and have
2053              a LOG_LINK pointing at I3.  We must remove this link.
2054              The simplest way to remove the link is to point it at I1,
2055              which we know will be a NOTE.  */
2056
2057           for (insn = NEXT_INSN (i3);
2058                insn && (this_basic_block == n_basic_blocks - 1
2059                         || insn != basic_block_head[this_basic_block + 1]);
2060                insn = NEXT_INSN (insn))
2061             {
2062               if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2063                   && reg_referenced_p (ni2dest, PATTERN (insn)))
2064                 {
2065                   for (link = LOG_LINKS (insn); link;
2066                        link = XEXP (link, 1))
2067                     if (XEXP (link, 0) == i3)
2068                       XEXP (link, 0) = i1;
2069
2070                   break;
2071                 }
2072             }
2073         }
2074     }
2075
2076   /* Similarly, check for a case where we have a PARALLEL of two independent
2077      SETs but we started with three insns.  In this case, we can do the sets
2078      as two separate insns.  This case occurs when some SET allows two
2079      other insns to combine, but the destination of that SET is still live.  */
2080
2081   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2082            && GET_CODE (newpat) == PARALLEL
2083            && XVECLEN (newpat, 0) == 2
2084            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2085            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2086            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2087            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2088            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2089            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2090            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2091                                    INSN_CUID (i2))
2092            /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
2093            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2094            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2095            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2096                                   XVECEXP (newpat, 0, 0))
2097            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2098                                   XVECEXP (newpat, 0, 1)))
2099     {
2100       /* Normally, it doesn't matter which of the two is done first,
2101          but it does if one references cc0.  In that case, it has to
2102          be first.  */
2103 #ifdef HAVE_cc0
2104       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2105         {
2106           newi2pat = XVECEXP (newpat, 0, 0);
2107           newpat = XVECEXP (newpat, 0, 1);
2108         }
2109       else
2110 #endif
2111         {
2112           newi2pat = XVECEXP (newpat, 0, 1);
2113           newpat = XVECEXP (newpat, 0, 0);
2114         }
2115
2116       i2_code_number
2117         = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2118
2119       if (i2_code_number >= 0)
2120         insn_code_number
2121           = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2122     }
2123
2124   /* If it still isn't recognized, fail and change things back the way they
2125      were.  */
2126   if ((insn_code_number < 0
2127        /* Is the result a reasonable ASM_OPERANDS?  */
2128        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2129     {
2130       undo_all ();
2131       return 0;
2132     }
2133
2134   /* If we had to change another insn, make sure it is valid also.  */
2135   if (undobuf.other_insn)
2136     {
2137       rtx other_pat = PATTERN (undobuf.other_insn);
2138       rtx new_other_notes;
2139       rtx note, next;
2140
2141       CLEAR_HARD_REG_SET (newpat_used_regs);
2142
2143       other_code_number
2144         = recog_for_combine (&other_pat, undobuf.other_insn,
2145                              &new_other_notes, &other_scratches);
2146
2147       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2148         {
2149           undo_all ();
2150           return 0;
2151         }
2152
2153       PATTERN (undobuf.other_insn) = other_pat;
2154
2155       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2156          are still valid.  Then add any non-duplicate notes added by
2157          recog_for_combine.  */
2158       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2159         {
2160           next = XEXP (note, 1);
2161
2162           if (REG_NOTE_KIND (note) == REG_UNUSED
2163               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2164             {
2165               if (GET_CODE (XEXP (note, 0)) == REG)
2166                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2167
2168               remove_note (undobuf.other_insn, note);
2169             }
2170         }
2171
2172       for (note = new_other_notes; note; note = XEXP (note, 1))
2173         if (GET_CODE (XEXP (note, 0)) == REG)
2174           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2175
2176       distribute_notes (new_other_notes, undobuf.other_insn,
2177                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2178     }
2179
2180   /* We now know that we can do this combination.  Merge the insns and
2181      update the status of registers and LOG_LINKS.  */
2182
2183   {
2184     rtx i3notes, i2notes, i1notes = 0;
2185     rtx i3links, i2links, i1links = 0;
2186     rtx midnotes = 0;
2187     register int regno;
2188     /* Compute which registers we expect to eliminate.  */
2189     rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2190                    ? 0 : i2dest);
2191     rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2192
2193     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2194        clear them.  */
2195     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2196     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2197     if (i1)
2198       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2199
2200     /* Ensure that we do not have something that should not be shared but
2201        occurs multiple times in the new insns.  Check this by first
2202        resetting all the `used' flags and then copying anything is shared.  */
2203
2204     reset_used_flags (i3notes);
2205     reset_used_flags (i2notes);
2206     reset_used_flags (i1notes);
2207     reset_used_flags (newpat);
2208     reset_used_flags (newi2pat);
2209     if (undobuf.other_insn)
2210       reset_used_flags (PATTERN (undobuf.other_insn));
2211
2212     i3notes = copy_rtx_if_shared (i3notes);
2213     i2notes = copy_rtx_if_shared (i2notes);
2214     i1notes = copy_rtx_if_shared (i1notes);
2215     newpat = copy_rtx_if_shared (newpat);
2216     newi2pat = copy_rtx_if_shared (newi2pat);
2217     if (undobuf.other_insn)
2218       reset_used_flags (PATTERN (undobuf.other_insn));
2219
2220     INSN_CODE (i3) = insn_code_number;
2221     PATTERN (i3) = newpat;
2222     if (undobuf.other_insn)
2223       INSN_CODE (undobuf.other_insn) = other_code_number;
2224
2225     /* We had one special case above where I2 had more than one set and
2226        we replaced a destination of one of those sets with the destination
2227        of I3.  In that case, we have to update LOG_LINKS of insns later
2228        in this basic block.  Note that this (expensive) case is rare.
2229
2230        Also, in this case, we must pretend that all REG_NOTEs for I2
2231        actually came from I3, so that REG_UNUSED notes from I2 will be
2232        properly handled.  */
2233
2234     if (i3_subst_into_i2)
2235       {
2236         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2237           if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2238               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2239               && ! find_reg_note (i2, REG_UNUSED,
2240                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2241             for (temp = NEXT_INSN (i2);
2242                  temp && (this_basic_block == n_basic_blocks - 1
2243                           || basic_block_head[this_basic_block] != temp);
2244                  temp = NEXT_INSN (temp))
2245               if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2246                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2247                   if (XEXP (link, 0) == i2)
2248                     XEXP (link, 0) = i3;
2249
2250         if (i3notes)
2251           {
2252             rtx link = i3notes;
2253             while (XEXP (link, 1))
2254               link = XEXP (link, 1);
2255             XEXP (link, 1) = i2notes;
2256           }
2257         else
2258           i3notes = i2notes;
2259         i2notes = 0;
2260       }
2261
2262     LOG_LINKS (i3) = 0;
2263     REG_NOTES (i3) = 0;
2264     LOG_LINKS (i2) = 0;
2265     REG_NOTES (i2) = 0;
2266
2267     if (newi2pat)
2268       {
2269         INSN_CODE (i2) = i2_code_number;
2270         PATTERN (i2) = newi2pat;
2271       }
2272     else
2273       {
2274         PUT_CODE (i2, NOTE);
2275         NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2276         NOTE_SOURCE_FILE (i2) = 0;
2277       }
2278
2279     if (i1)
2280       {
2281         LOG_LINKS (i1) = 0;
2282         REG_NOTES (i1) = 0;
2283         PUT_CODE (i1, NOTE);
2284         NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2285         NOTE_SOURCE_FILE (i1) = 0;
2286       }
2287
2288     /* Get death notes for everything that is now used in either I3 or
2289        I2 and used to die in a previous insn.  If we built two new
2290        patterns, move from I1 to I2 then I2 to I3 so that we get the
2291        proper movement on registers that I2 modifies.  */
2292
2293     if (newi2pat)
2294       {
2295         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2296         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2297       }
2298     else
2299       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2300                    i3, &midnotes);
2301
2302     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
2303     if (i3notes)
2304       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2305                         elim_i2, elim_i1);
2306     if (i2notes)
2307       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2308                         elim_i2, elim_i1);
2309     if (i1notes)
2310       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2311                         elim_i2, elim_i1);
2312     if (midnotes)
2313       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2314                         elim_i2, elim_i1);
2315
2316     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
2317        know these are REG_UNUSED and want them to go to the desired insn,
2318        so we always pass it as i3.  We have not counted the notes in
2319        reg_n_deaths yet, so we need to do so now.  */
2320
2321     if (newi2pat && new_i2_notes)
2322       {
2323         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2324           if (GET_CODE (XEXP (temp, 0)) == REG)
2325             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2326
2327         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2328       }
2329
2330     if (new_i3_notes)
2331       {
2332         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2333           if (GET_CODE (XEXP (temp, 0)) == REG)
2334             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2335
2336         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2337       }
2338
2339     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
2340        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
2341        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
2342        in that case, it might delete I2.  Similarly for I2 and I1.
2343        Show an additional death due to the REG_DEAD note we make here.  If
2344        we discard it in distribute_notes, we will decrement it again.  */
2345
2346     if (i3dest_killed)
2347       {
2348         if (GET_CODE (i3dest_killed) == REG)
2349           REG_N_DEATHS (REGNO (i3dest_killed))++;
2350
2351         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2352           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2353                                      NULL_RTX),
2354                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2355         else
2356           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2357                                      NULL_RTX),
2358                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2359                             elim_i2, elim_i1);
2360       }
2361
2362     if (i2dest_in_i2src)
2363       {
2364         if (GET_CODE (i2dest) == REG)
2365           REG_N_DEATHS (REGNO (i2dest))++;
2366
2367         if (newi2pat && reg_set_p (i2dest, newi2pat))
2368           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2369                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2370         else
2371           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2372                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2373                             NULL_RTX, NULL_RTX);
2374       }
2375
2376     if (i1dest_in_i1src)
2377       {
2378         if (GET_CODE (i1dest) == REG)
2379           REG_N_DEATHS (REGNO (i1dest))++;
2380
2381         if (newi2pat && reg_set_p (i1dest, newi2pat))
2382           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2383                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2384         else
2385           distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2386                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2387                             NULL_RTX, NULL_RTX);
2388       }
2389
2390     distribute_links (i3links);
2391     distribute_links (i2links);
2392     distribute_links (i1links);
2393
2394     if (GET_CODE (i2dest) == REG)
2395       {
2396         rtx link;
2397         rtx i2_insn = 0, i2_val = 0, set;
2398
2399         /* The insn that used to set this register doesn't exist, and
2400            this life of the register may not exist either.  See if one of
2401            I3's links points to an insn that sets I2DEST.  If it does,
2402            that is now the last known value for I2DEST. If we don't update
2403            this and I2 set the register to a value that depended on its old
2404            contents, we will get confused.  If this insn is used, thing
2405            will be set correctly in combine_instructions.  */
2406
2407         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2408           if ((set = single_set (XEXP (link, 0))) != 0
2409               && rtx_equal_p (i2dest, SET_DEST (set)))
2410             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2411
2412         record_value_for_reg (i2dest, i2_insn, i2_val);
2413
2414         /* If the reg formerly set in I2 died only once and that was in I3,
2415            zero its use count so it won't make `reload' do any work.  */
2416         if (! added_sets_2
2417             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2418             && ! i2dest_in_i2src)
2419           {
2420             regno = REGNO (i2dest);
2421             REG_N_SETS (regno)--;
2422             if (REG_N_SETS (regno) == 0
2423                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2424               REG_N_REFS (regno) = 0;
2425           }
2426       }
2427
2428     if (i1 && GET_CODE (i1dest) == REG)
2429       {
2430         rtx link;
2431         rtx i1_insn = 0, i1_val = 0, set;
2432
2433         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2434           if ((set = single_set (XEXP (link, 0))) != 0
2435               && rtx_equal_p (i1dest, SET_DEST (set)))
2436             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2437
2438         record_value_for_reg (i1dest, i1_insn, i1_val);
2439
2440         regno = REGNO (i1dest);
2441         if (! added_sets_1 && ! i1dest_in_i1src)
2442           {
2443             REG_N_SETS (regno)--;
2444             if (REG_N_SETS (regno) == 0
2445                 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2446               REG_N_REFS (regno) = 0;
2447           }
2448       }
2449
2450     /* Update reg_nonzero_bits et al for any changes that may have been made
2451        to this insn.  */
2452
2453     note_stores (newpat, set_nonzero_bits_and_sign_copies);
2454     if (newi2pat)
2455       note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2456
2457     /* If we added any (clobber (scratch)), add them to the max for a
2458        block.  This is a very pessimistic calculation, since we might
2459        have had them already and this might not be the worst block, but
2460        it's not worth doing any better.  */
2461     max_scratch += i3_scratches + i2_scratches + other_scratches;
2462
2463     /* If I3 is now an unconditional jump, ensure that it has a
2464        BARRIER following it since it may have initially been a
2465        conditional jump.  It may also be the last nonnote insn.  */
2466
2467     if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2468         && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2469             || GET_CODE (temp) != BARRIER))
2470       emit_barrier_after (i3);
2471   }
2472
2473   combine_successes++;
2474
2475   /* Clear this here, so that subsequent get_last_value calls are not
2476      affected.  */
2477   subst_prev_insn = NULL_RTX;
2478
2479   if (added_links_insn
2480       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2481       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2482     return added_links_insn;
2483   else
2484     return newi2pat ? i2 : i3;
2485 }
2486 \f
2487 /* Undo all the modifications recorded in undobuf.  */
2488
2489 static void
2490 undo_all ()
2491 {
2492   struct undo *undo, *next;
2493
2494   for (undo = undobuf.undos; undo; undo = next)
2495     {
2496       next = undo->next;
2497       if (undo->is_int)
2498         *undo->where.i = undo->old_contents.i;
2499       else
2500         *undo->where.r = undo->old_contents.r;
2501
2502       undo->next = undobuf.frees;
2503       undobuf.frees = undo;
2504     }
2505
2506   obfree (undobuf.storage);
2507   undobuf.undos = undobuf.previous_undos = 0;
2508
2509   /* Clear this here, so that subsequent get_last_value calls are not
2510      affected.  */
2511   subst_prev_insn = NULL_RTX;
2512 }
2513 \f
2514 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2515    where we have an arithmetic expression and return that point.  LOC will
2516    be inside INSN.
2517
2518    try_combine will call this function to see if an insn can be split into
2519    two insns.  */
2520
2521 static rtx *
2522 find_split_point (loc, insn)
2523      rtx *loc;
2524      rtx insn;
2525 {
2526   rtx x = *loc;
2527   enum rtx_code code = GET_CODE (x);
2528   rtx *split;
2529   int len = 0, pos, unsignedp;
2530   rtx inner;
2531
2532   /* First special-case some codes.  */
2533   switch (code)
2534     {
2535     case SUBREG:
2536 #ifdef INSN_SCHEDULING
2537       /* If we are making a paradoxical SUBREG invalid, it becomes a split
2538          point.  */
2539       if (GET_CODE (SUBREG_REG (x)) == MEM)
2540         return loc;
2541 #endif
2542       return find_split_point (&SUBREG_REG (x), insn);
2543
2544     case MEM:
2545 #ifdef HAVE_lo_sum
2546       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2547          using LO_SUM and HIGH.  */
2548       if (GET_CODE (XEXP (x, 0)) == CONST
2549           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2550         {
2551           SUBST (XEXP (x, 0),
2552                  gen_rtx_combine (LO_SUM, Pmode,
2553                                   gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2554                                   XEXP (x, 0)));
2555           return &XEXP (XEXP (x, 0), 0);
2556         }
2557 #endif
2558
2559       /* If we have a PLUS whose second operand is a constant and the
2560          address is not valid, perhaps will can split it up using
2561          the machine-specific way to split large constants.  We use
2562          the first pseudo-reg (one of the virtual regs) as a placeholder;
2563          it will not remain in the result.  */
2564       if (GET_CODE (XEXP (x, 0)) == PLUS
2565           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2566           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2567         {
2568           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2569           rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2570                                  subst_insn);
2571
2572           /* This should have produced two insns, each of which sets our
2573              placeholder.  If the source of the second is a valid address,
2574              we can make put both sources together and make a split point
2575              in the middle.  */
2576
2577           if (seq && XVECLEN (seq, 0) == 2
2578               && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2579               && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2580               && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2581               && ! reg_mentioned_p (reg,
2582                                     SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2583               && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2584               && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2585               && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2586               && memory_address_p (GET_MODE (x),
2587                                    SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2588             {
2589               rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2590               rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2591
2592               /* Replace the placeholder in SRC2 with SRC1.  If we can
2593                  find where in SRC2 it was placed, that can become our
2594                  split point and we can replace this address with SRC2.
2595                  Just try two obvious places.  */
2596
2597               src2 = replace_rtx (src2, reg, src1);
2598               split = 0;
2599               if (XEXP (src2, 0) == src1)
2600                 split = &XEXP (src2, 0);
2601               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2602                        && XEXP (XEXP (src2, 0), 0) == src1)
2603                 split = &XEXP (XEXP (src2, 0), 0);
2604
2605               if (split)
2606                 {
2607                   SUBST (XEXP (x, 0), src2);
2608                   return split;
2609                 }
2610             }
2611
2612           /* If that didn't work, perhaps the first operand is complex and
2613              needs to be computed separately, so make a split point there.
2614              This will occur on machines that just support REG + CONST
2615              and have a constant moved through some previous computation.  */
2616
2617           else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2618                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2619                          && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2620                              == 'o')))
2621             return &XEXP (XEXP (x, 0), 0);
2622         }
2623       break;
2624
2625     case SET:
2626 #ifdef HAVE_cc0
2627       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2628          ZERO_EXTRACT, the most likely reason why this doesn't match is that
2629          we need to put the operand into a register.  So split at that
2630          point.  */
2631
2632       if (SET_DEST (x) == cc0_rtx
2633           && GET_CODE (SET_SRC (x)) != COMPARE
2634           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2635           && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2636           && ! (GET_CODE (SET_SRC (x)) == SUBREG
2637                 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2638         return &SET_SRC (x);
2639 #endif
2640
2641       /* See if we can split SET_SRC as it stands.  */
2642       split = find_split_point (&SET_SRC (x), insn);
2643       if (split && split != &SET_SRC (x))
2644         return split;
2645
2646       /* See if we can split SET_DEST as it stands.  */
2647       split = find_split_point (&SET_DEST (x), insn);
2648       if (split && split != &SET_DEST (x))
2649         return split;
2650
2651       /* See if this is a bitfield assignment with everything constant.  If
2652          so, this is an IOR of an AND, so split it into that.  */
2653       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2654           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2655               <= HOST_BITS_PER_WIDE_INT)
2656           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2657           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2658           && GET_CODE (SET_SRC (x)) == CONST_INT
2659           && ((INTVAL (XEXP (SET_DEST (x), 1))
2660               + INTVAL (XEXP (SET_DEST (x), 2)))
2661               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2662           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2663         {
2664           int pos = INTVAL (XEXP (SET_DEST (x), 2));
2665           int len = INTVAL (XEXP (SET_DEST (x), 1));
2666           int src = INTVAL (SET_SRC (x));
2667           rtx dest = XEXP (SET_DEST (x), 0);
2668           enum machine_mode mode = GET_MODE (dest);
2669           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2670
2671           if (BITS_BIG_ENDIAN)
2672             pos = GET_MODE_BITSIZE (mode) - len - pos;
2673
2674           if (src == mask)
2675             SUBST (SET_SRC (x),
2676                    gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2677           else
2678             SUBST (SET_SRC (x),
2679                    gen_binary (IOR, mode,
2680                                gen_binary (AND, mode, dest,
2681                                            GEN_INT (~ (mask << pos)
2682                                                     & GET_MODE_MASK (mode))),
2683                                GEN_INT (src << pos)));
2684
2685           SUBST (SET_DEST (x), dest);
2686
2687           split = find_split_point (&SET_SRC (x), insn);
2688           if (split && split != &SET_SRC (x))
2689             return split;
2690         }
2691
2692       /* Otherwise, see if this is an operation that we can split into two.
2693          If so, try to split that.  */
2694       code = GET_CODE (SET_SRC (x));
2695
2696       switch (code)
2697         {
2698         case AND:
2699           /* If we are AND'ing with a large constant that is only a single
2700              bit and the result is only being used in a context where we
2701              need to know if it is zero or non-zero, replace it with a bit
2702              extraction.  This will avoid the large constant, which might
2703              have taken more than one insn to make.  If the constant were
2704              not a valid argument to the AND but took only one insn to make,
2705              this is no worse, but if it took more than one insn, it will
2706              be better.  */
2707
2708           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2709               && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2710               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2711               && GET_CODE (SET_DEST (x)) == REG
2712               && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2713               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2714               && XEXP (*split, 0) == SET_DEST (x)
2715               && XEXP (*split, 1) == const0_rtx)
2716             {
2717               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2718                                                 XEXP (SET_SRC (x), 0),
2719                                                 pos, NULL_RTX, 1, 1, 0, 0);
2720               if (extraction != 0)
2721                 {
2722                   SUBST (SET_SRC (x), extraction);
2723                   return find_split_point (loc, insn);
2724                 }
2725             }
2726           break;
2727
2728         case NE:
2729           /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2730              is known to be on, this can be converted into a NEG of a shift. */
2731           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2732               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2733               && 1 <= (pos = exact_log2
2734                        (nonzero_bits (XEXP (SET_SRC (x), 0),
2735                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
2736             {
2737               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2738
2739               SUBST (SET_SRC (x),
2740                      gen_rtx_combine (NEG, mode,
2741                                       gen_rtx_combine (LSHIFTRT, mode,
2742                                                        XEXP (SET_SRC (x), 0),
2743                                                        GEN_INT (pos))));
2744
2745               split = find_split_point (&SET_SRC (x), insn);
2746               if (split && split != &SET_SRC (x))
2747                 return split;
2748             }
2749           break;
2750
2751         case SIGN_EXTEND:
2752           inner = XEXP (SET_SRC (x), 0);
2753
2754           /* We can't optimize if either mode is a partial integer
2755              mode as we don't know how many bits are significant
2756              in those modes.  */
2757           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2758               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2759             break;
2760
2761           pos = 0;
2762           len = GET_MODE_BITSIZE (GET_MODE (inner));
2763           unsignedp = 0;
2764           break;
2765
2766         case SIGN_EXTRACT:
2767         case ZERO_EXTRACT:
2768           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2769               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2770             {
2771               inner = XEXP (SET_SRC (x), 0);
2772               len = INTVAL (XEXP (SET_SRC (x), 1));
2773               pos = INTVAL (XEXP (SET_SRC (x), 2));
2774
2775               if (BITS_BIG_ENDIAN)
2776                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2777               unsignedp = (code == ZERO_EXTRACT);
2778             }
2779           break;
2780
2781         default:
2782           break;
2783         }
2784
2785       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2786         {
2787           enum machine_mode mode = GET_MODE (SET_SRC (x));
2788
2789           /* For unsigned, we have a choice of a shift followed by an
2790              AND or two shifts.  Use two shifts for field sizes where the
2791              constant might be too large.  We assume here that we can
2792              always at least get 8-bit constants in an AND insn, which is
2793              true for every current RISC.  */
2794
2795           if (unsignedp && len <= 8)
2796             {
2797               SUBST (SET_SRC (x),
2798                      gen_rtx_combine
2799                      (AND, mode,
2800                       gen_rtx_combine (LSHIFTRT, mode,
2801                                        gen_lowpart_for_combine (mode, inner),
2802                                        GEN_INT (pos)),
2803                       GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2804
2805               split = find_split_point (&SET_SRC (x), insn);
2806               if (split && split != &SET_SRC (x))
2807                 return split;
2808             }
2809           else
2810             {
2811               SUBST (SET_SRC (x),
2812                      gen_rtx_combine
2813                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2814                       gen_rtx_combine (ASHIFT, mode,
2815                                        gen_lowpart_for_combine (mode, inner),
2816                                        GEN_INT (GET_MODE_BITSIZE (mode)
2817                                                 - len - pos)),
2818                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2819
2820               split = find_split_point (&SET_SRC (x), insn);
2821               if (split && split != &SET_SRC (x))
2822                 return split;
2823             }
2824         }
2825
2826       /* See if this is a simple operation with a constant as the second
2827          operand.  It might be that this constant is out of range and hence
2828          could be used as a split point.  */
2829       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2830            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2831            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2832           && CONSTANT_P (XEXP (SET_SRC (x), 1))
2833           && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2834               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2835                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2836                       == 'o'))))
2837         return &XEXP (SET_SRC (x), 1);
2838
2839       /* Finally, see if this is a simple operation with its first operand
2840          not in a register.  The operation might require this operand in a
2841          register, so return it as a split point.  We can always do this
2842          because if the first operand were another operation, we would have
2843          already found it as a split point.  */
2844       if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2845            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2846            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2847            || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2848           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2849         return &XEXP (SET_SRC (x), 0);
2850
2851       return 0;
2852
2853     case AND:
2854     case IOR:
2855       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2856          it is better to write this as (not (ior A B)) so we can split it.
2857          Similarly for IOR.  */
2858       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2859         {
2860           SUBST (*loc,
2861                  gen_rtx_combine (NOT, GET_MODE (x),
2862                                   gen_rtx_combine (code == IOR ? AND : IOR,
2863                                                    GET_MODE (x),
2864                                                    XEXP (XEXP (x, 0), 0),
2865                                                    XEXP (XEXP (x, 1), 0))));
2866           return find_split_point (loc, insn);
2867         }
2868
2869       /* Many RISC machines have a large set of logical insns.  If the
2870          second operand is a NOT, put it first so we will try to split the
2871          other operand first.  */
2872       if (GET_CODE (XEXP (x, 1)) == NOT)
2873         {
2874           rtx tem = XEXP (x, 0);
2875           SUBST (XEXP (x, 0), XEXP (x, 1));
2876           SUBST (XEXP (x, 1), tem);
2877         }
2878       break;
2879
2880     default:
2881       break;
2882     }
2883
2884   /* Otherwise, select our actions depending on our rtx class.  */
2885   switch (GET_RTX_CLASS (code))
2886     {
2887     case 'b':                   /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
2888     case '3':
2889       split = find_split_point (&XEXP (x, 2), insn);
2890       if (split)
2891         return split;
2892       /* ... fall through ...  */
2893     case '2':
2894     case 'c':
2895     case '<':
2896       split = find_split_point (&XEXP (x, 1), insn);
2897       if (split)
2898         return split;
2899       /* ... fall through ...  */
2900     case '1':
2901       /* Some machines have (and (shift ...) ...) insns.  If X is not
2902          an AND, but XEXP (X, 0) is, use it as our split point.  */
2903       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2904         return &XEXP (x, 0);
2905
2906       split = find_split_point (&XEXP (x, 0), insn);
2907       if (split)
2908         return split;
2909       return loc;
2910     }
2911
2912   /* Otherwise, we don't have a split point.  */
2913   return 0;
2914 }
2915 \f
2916 /* Throughout X, replace FROM with TO, and return the result.
2917    The result is TO if X is FROM;
2918    otherwise the result is X, but its contents may have been modified.
2919    If they were modified, a record was made in undobuf so that
2920    undo_all will (among other things) return X to its original state.
2921
2922    If the number of changes necessary is too much to record to undo,
2923    the excess changes are not made, so the result is invalid.
2924    The changes already made can still be undone.
2925    undobuf.num_undo is incremented for such changes, so by testing that
2926    the caller can tell whether the result is valid.
2927
2928    `n_occurrences' is incremented each time FROM is replaced.
2929
2930    IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2931
2932    UNIQUE_COPY is non-zero if each substitution must be unique.  We do this
2933    by copying if `n_occurrences' is non-zero.  */
2934
2935 static rtx
2936 subst (x, from, to, in_dest, unique_copy)
2937      register rtx x, from, to;
2938      int in_dest;
2939      int unique_copy;
2940 {
2941   register enum rtx_code code = GET_CODE (x);
2942   enum machine_mode op0_mode = VOIDmode;
2943   register char *fmt;
2944   register int len, i;
2945   rtx new;
2946
2947 /* Two expressions are equal if they are identical copies of a shared
2948    RTX or if they are both registers with the same register number
2949    and mode.  */
2950
2951 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
2952   ((X) == (Y)                                           \
2953    || (GET_CODE (X) == REG && GET_CODE (Y) == REG       \
2954        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2955
2956   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2957     {
2958       n_occurrences++;
2959       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2960     }
2961
2962   /* If X and FROM are the same register but different modes, they will
2963      not have been seen as equal above.  However, flow.c will make a
2964      LOG_LINKS entry for that case.  If we do nothing, we will try to
2965      rerecognize our original insn and, when it succeeds, we will
2966      delete the feeding insn, which is incorrect.
2967
2968      So force this insn not to match in this (rare) case.  */
2969   if (! in_dest && code == REG && GET_CODE (from) == REG
2970       && REGNO (x) == REGNO (from))
2971     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2972
2973   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2974      of which may contain things that can be combined.  */
2975   if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2976     return x;
2977
2978   /* It is possible to have a subexpression appear twice in the insn.
2979      Suppose that FROM is a register that appears within TO.
2980      Then, after that subexpression has been scanned once by `subst',
2981      the second time it is scanned, TO may be found.  If we were
2982      to scan TO here, we would find FROM within it and create a
2983      self-referent rtl structure which is completely wrong.  */
2984   if (COMBINE_RTX_EQUAL_P (x, to))
2985     return to;
2986
2987   len = GET_RTX_LENGTH (code);
2988   fmt = GET_RTX_FORMAT (code);
2989
2990   /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2991      set up to skip this common case.  All other cases where we want to
2992      suppress replacing something inside a SET_SRC are handled via the
2993      IN_DEST operand.  */
2994   if (code == SET
2995       && (GET_CODE (SET_DEST (x)) == REG
2996         || GET_CODE (SET_DEST (x)) == CC0
2997         || GET_CODE (SET_DEST (x)) == PC))
2998     fmt = "ie";
2999
3000   /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3001      constant.  */
3002   if (fmt[0] == 'e')
3003     op0_mode = GET_MODE (XEXP (x, 0));
3004
3005   for (i = 0; i < len; i++)
3006     {
3007       if (fmt[i] == 'E')
3008         {
3009           register int j;
3010           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3011             {
3012               if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3013                 {
3014                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3015                   n_occurrences++;
3016                 }
3017               else
3018                 {
3019                   new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3020
3021                   /* If this substitution failed, this whole thing fails.  */
3022                   if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3023                     return new;
3024                 }
3025
3026               SUBST (XVECEXP (x, i, j), new);
3027             }
3028         }
3029       else if (fmt[i] == 'e')
3030         {
3031           if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3032             {
3033               /* In general, don't install a subreg involving two modes not
3034                  tieable.  It can worsen register allocation, and can even
3035                  make invalid reload insns, since the reg inside may need to
3036                  be copied from in the outside mode, and that may be invalid
3037                  if it is an fp reg copied in integer mode.
3038
3039                  We allow two exceptions to this: It is valid if it is inside
3040                  another SUBREG and the mode of that SUBREG and the mode of
3041                  the inside of TO is tieable and it is valid if X is a SET
3042                  that copies FROM to CC0.  */
3043               if (GET_CODE (to) == SUBREG
3044                   && ! MODES_TIEABLE_P (GET_MODE (to),
3045                                         GET_MODE (SUBREG_REG (to)))
3046                   && ! (code == SUBREG
3047                         && MODES_TIEABLE_P (GET_MODE (x),
3048                                             GET_MODE (SUBREG_REG (to))))
3049 #ifdef HAVE_cc0
3050                   && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3051 #endif
3052                   )
3053                 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
3054
3055               new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3056               n_occurrences++;
3057             }
3058           else
3059             /* If we are in a SET_DEST, suppress most cases unless we
3060                have gone inside a MEM, in which case we want to
3061                simplify the address.  We assume here that things that
3062                are actually part of the destination have their inner
3063                parts in the first expression.  This is true for SUBREG,
3064                STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3065                things aside from REG and MEM that should appear in a
3066                SET_DEST.  */
3067             new = subst (XEXP (x, i), from, to,
3068                          (((in_dest
3069                             && (code == SUBREG || code == STRICT_LOW_PART
3070                                 || code == ZERO_EXTRACT))
3071                            || code == SET)
3072                           && i == 0), unique_copy);
3073
3074           /* If we found that we will have to reject this combination,
3075              indicate that by returning the CLOBBER ourselves, rather than
3076              an expression containing it.  This will speed things up as
3077              well as prevent accidents where two CLOBBERs are considered
3078              to be equal, thus producing an incorrect simplification.  */
3079
3080           if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3081             return new;
3082
3083           SUBST (XEXP (x, i), new);
3084         }
3085     }
3086
3087   /* Try to simplify X.  If the simplification changed the code, it is likely
3088      that further simplification will help, so loop, but limit the number
3089      of repetitions that will be performed.  */
3090
3091   for (i = 0; i < 4; i++)
3092     {
3093       /* If X is sufficiently simple, don't bother trying to do anything
3094          with it.  */
3095       if (code != CONST_INT && code != REG && code != CLOBBER)
3096         x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3097
3098       if (GET_CODE (x) == code)
3099         break;
3100
3101       code = GET_CODE (x);
3102
3103       /* We no longer know the original mode of operand 0 since we
3104          have changed the form of X)  */
3105       op0_mode = VOIDmode;
3106     }
3107
3108   return x;
3109 }
3110 \f
3111 /* Simplify X, a piece of RTL.  We just operate on the expression at the
3112    outer level; call `subst' to simplify recursively.  Return the new
3113    expression.
3114
3115    OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3116    will be the iteration even if an expression with a code different from
3117    X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */
3118
3119 static rtx
3120 simplify_rtx (x, op0_mode, last, in_dest)
3121      rtx x;
3122      enum machine_mode op0_mode;
3123      int last;
3124      int in_dest;
3125 {
3126   enum rtx_code code = GET_CODE (x);
3127   enum machine_mode mode = GET_MODE (x);
3128   rtx temp;
3129   int i;
3130
3131   /* If this is a commutative operation, put a constant last and a complex
3132      expression first.  We don't need to do this for comparisons here.  */
3133   if (GET_RTX_CLASS (code) == 'c'
3134       && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3135           || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3136               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3137           || (GET_CODE (XEXP (x, 0)) == SUBREG
3138               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3139               && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3140     {
3141       temp = XEXP (x, 0);
3142       SUBST (XEXP (x, 0), XEXP (x, 1));
3143       SUBST (XEXP (x, 1), temp);
3144     }
3145
3146   /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3147      sign extension of a PLUS with a constant, reverse the order of the sign
3148      extension and the addition. Note that this not the same as the original
3149      code, but overflow is undefined for signed values.  Also note that the
3150      PLUS will have been partially moved "inside" the sign-extension, so that
3151      the first operand of X will really look like:
3152          (ashiftrt (plus (ashift A C4) C5) C4).
3153      We convert this to
3154          (plus (ashiftrt (ashift A C4) C2) C4)
3155      and replace the first operand of X with that expression.  Later parts
3156      of this function may simplify the expression further.
3157
3158      For example, if we start with (mult (sign_extend (plus A C1)) C2),
3159      we swap the SIGN_EXTEND and PLUS.  Later code will apply the
3160      distributive law to produce (plus (mult (sign_extend X) C1) C3).
3161
3162      We do this to simplify address expressions.  */
3163
3164   if ((code == PLUS || code == MINUS || code == MULT)
3165       && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3166       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3167       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3168       && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3169       && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3170       && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3171       && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3172       && (temp = simplify_binary_operation (ASHIFTRT, mode,
3173                                             XEXP (XEXP (XEXP (x, 0), 0), 1),
3174                                             XEXP (XEXP (x, 0), 1))) != 0)
3175     {
3176       rtx new
3177         = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3178                                 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3179                                 INTVAL (XEXP (XEXP (x, 0), 1)));
3180
3181       new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3182                                   INTVAL (XEXP (XEXP (x, 0), 1)));
3183
3184       SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3185     }
3186
3187   /* If this is a simple operation applied to an IF_THEN_ELSE, try
3188      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
3189      things.  Check for cases where both arms are testing the same
3190      condition.
3191
3192      Don't do anything if all operands are very simple.  */
3193
3194   if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3195         || GET_RTX_CLASS (code) == '<')
3196        && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3197             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3198                   && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3199                       == 'o')))
3200            || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3201                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3202                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3203                          == 'o')))))
3204       || (GET_RTX_CLASS (code) == '1'
3205           && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3206                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3207                      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3208                          == 'o'))))))
3209     {
3210       rtx cond, true, false;
3211
3212       cond = if_then_else_cond (x, &true, &false);
3213       if (cond != 0
3214           /* If everything is a comparison, what we have is highly unlikely
3215              to be simpler, so don't use it.  */
3216           && ! (GET_RTX_CLASS (code) == '<'
3217                 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3218                     || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3219         {
3220           rtx cop1 = const0_rtx;
3221           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3222
3223           if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3224             return x;
3225
3226           /* Simplify the alternative arms; this may collapse the true and
3227              false arms to store-flag values.  */
3228           true = subst (true, pc_rtx, pc_rtx, 0, 0);
3229           false = subst (false, pc_rtx, pc_rtx, 0, 0);
3230
3231           /* Restarting if we generate a store-flag expression will cause
3232              us to loop.  Just drop through in this case.  */
3233
3234           /* If the result values are STORE_FLAG_VALUE and zero, we can
3235              just make the comparison operation.  */
3236           if (true == const_true_rtx && false == const0_rtx)
3237             x = gen_binary (cond_code, mode, cond, cop1);
3238           else if (true == const0_rtx && false == const_true_rtx)
3239             x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3240
3241           /* Likewise, we can make the negate of a comparison operation
3242              if the result values are - STORE_FLAG_VALUE and zero.  */
3243           else if (GET_CODE (true) == CONST_INT
3244                    && INTVAL (true) == - STORE_FLAG_VALUE
3245                    && false == const0_rtx)
3246             x = gen_unary (NEG, mode, mode,
3247                            gen_binary (cond_code, mode, cond, cop1));
3248           else if (GET_CODE (false) == CONST_INT
3249                    && INTVAL (false) == - STORE_FLAG_VALUE
3250                    && true == const0_rtx)
3251             x = gen_unary (NEG, mode, mode,
3252                            gen_binary (reverse_condition (cond_code),
3253                                        mode, cond, cop1));
3254           else
3255             return gen_rtx (IF_THEN_ELSE, mode,
3256                             gen_binary (cond_code, VOIDmode, cond, cop1),
3257                             true, false);
3258
3259           code = GET_CODE (x);
3260           op0_mode = VOIDmode;
3261         }
3262     }
3263
3264   /* Try to fold this expression in case we have constants that weren't
3265      present before.  */
3266   temp = 0;
3267   switch (GET_RTX_CLASS (code))
3268     {
3269     case '1':
3270       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3271       break;
3272     case '<':
3273       temp = simplify_relational_operation (code, op0_mode,
3274                                             XEXP (x, 0), XEXP (x, 1));
3275 #ifdef FLOAT_STORE_FLAG_VALUE
3276       if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3277         temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3278                 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3279 #endif
3280       break;
3281     case 'c':
3282     case '2':
3283       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3284       break;
3285     case 'b':
3286     case '3':
3287       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3288                                          XEXP (x, 1), XEXP (x, 2));
3289       break;
3290     }
3291
3292   if (temp)
3293     x = temp, code = GET_CODE (temp);
3294
3295   /* First see if we can apply the inverse distributive law.  */
3296   if (code == PLUS || code == MINUS
3297       || code == AND || code == IOR || code == XOR)
3298     {
3299       x = apply_distributive_law (x);
3300       code = GET_CODE (x);
3301     }
3302
3303   /* If CODE is an associative operation not otherwise handled, see if we
3304      can associate some operands.  This can win if they are constants or
3305      if they are logically related (i.e. (a & b) & a.  */
3306   if ((code == PLUS || code == MINUS
3307        || code == MULT || code == AND || code == IOR || code == XOR
3308        || code == DIV || code == UDIV
3309        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3310       && INTEGRAL_MODE_P (mode))
3311     {
3312       if (GET_CODE (XEXP (x, 0)) == code)
3313         {
3314           rtx other = XEXP (XEXP (x, 0), 0);
3315           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3316           rtx inner_op1 = XEXP (x, 1);
3317           rtx inner;
3318
3319           /* Make sure we pass the constant operand if any as the second
3320              one if this is a commutative operation.  */
3321           if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3322             {
3323               rtx tem = inner_op0;
3324               inner_op0 = inner_op1;
3325               inner_op1 = tem;
3326             }
3327           inner = simplify_binary_operation (code == MINUS ? PLUS
3328                                              : code == DIV ? MULT
3329                                              : code == UDIV ? MULT
3330                                              : code,
3331                                              mode, inner_op0, inner_op1);
3332
3333           /* For commutative operations, try the other pair if that one
3334              didn't simplify.  */
3335           if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3336             {
3337               other = XEXP (XEXP (x, 0), 1);
3338               inner = simplify_binary_operation (code, mode,
3339                                                  XEXP (XEXP (x, 0), 0),
3340                                                  XEXP (x, 1));
3341             }
3342
3343           if (inner)
3344             return gen_binary (code, mode, other, inner);
3345         }
3346     }
3347
3348   /* A little bit of algebraic simplification here.  */
3349   switch (code)
3350     {
3351     case MEM:
3352       /* Ensure that our address has any ASHIFTs converted to MULT in case
3353          address-recognizing predicates are called later.  */
3354       temp = make_compound_operation (XEXP (x, 0), MEM);
3355       SUBST (XEXP (x, 0), temp);
3356       break;
3357
3358     case SUBREG:
3359       /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3360          is paradoxical.  If we can't do that safely, then it becomes
3361          something nonsensical so that this combination won't take place.  */
3362
3363       if (GET_CODE (SUBREG_REG (x)) == MEM
3364           && (GET_MODE_SIZE (mode)
3365               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3366         {
3367           rtx inner = SUBREG_REG (x);
3368           int endian_offset = 0;
3369           /* Don't change the mode of the MEM
3370              if that would change the meaning of the address.  */
3371           if (MEM_VOLATILE_P (SUBREG_REG (x))
3372               || mode_dependent_address_p (XEXP (inner, 0)))
3373             return gen_rtx (CLOBBER, mode, const0_rtx);
3374
3375           if (BYTES_BIG_ENDIAN)
3376             {
3377               if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3378                 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3379               if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3380                 endian_offset -= (UNITS_PER_WORD
3381                                   - GET_MODE_SIZE (GET_MODE (inner)));
3382             }
3383           /* Note if the plus_constant doesn't make a valid address
3384              then this combination won't be accepted.  */
3385           x = gen_rtx (MEM, mode,
3386                        plus_constant (XEXP (inner, 0),
3387                                       (SUBREG_WORD (x) * UNITS_PER_WORD
3388                                        + endian_offset)));
3389           MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3390           RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3391           MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3392           return x;
3393         }
3394
3395       /* If we are in a SET_DEST, these other cases can't apply.  */
3396       if (in_dest)
3397         return x;
3398
3399       /* Changing mode twice with SUBREG => just change it once,
3400          or not at all if changing back to starting mode.  */
3401       if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3402         {
3403           if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3404               && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3405             return SUBREG_REG (SUBREG_REG (x));
3406
3407           SUBST_INT (SUBREG_WORD (x),
3408                      SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3409           SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3410         }
3411
3412       /* SUBREG of a hard register => just change the register number
3413          and/or mode.  If the hard register is not valid in that mode,
3414          suppress this combination.  If the hard register is the stack,
3415          frame, or argument pointer, leave this as a SUBREG.  */
3416
3417       if (GET_CODE (SUBREG_REG (x)) == REG
3418           && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3419           && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3420 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3421           && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3422 #endif
3423 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3424           && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3425 #endif
3426           && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3427         {
3428           if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3429                                   mode))
3430             return gen_rtx (REG, mode,
3431                             REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3432           else
3433             return gen_rtx (CLOBBER, mode, const0_rtx);
3434         }
3435
3436       /* For a constant, try to pick up the part we want.  Handle a full
3437          word and low-order part.  Only do this if we are narrowing
3438          the constant; if it is being widened, we have no idea what
3439          the extra bits will have been set to.  */
3440
3441       if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3442           && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3443           && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3444           && GET_MODE_CLASS (mode) == MODE_INT)
3445         {
3446           temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3447                                   0, op0_mode);
3448           if (temp)
3449             return temp;
3450         }
3451
3452       /* If we want a subreg of a constant, at offset 0,
3453          take the low bits.  On a little-endian machine, that's
3454          always valid.  On a big-endian machine, it's valid
3455          only if the constant's mode fits in one word.   Note that we
3456          cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode.  */
3457       if (CONSTANT_P (SUBREG_REG (x))
3458           && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3459               || ! WORDS_BIG_ENDIAN)
3460               ? SUBREG_WORD (x) == 0
3461               : (SUBREG_WORD (x)
3462                  == ((GET_MODE_SIZE (op0_mode)
3463                       - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3464                      / UNITS_PER_WORD)))
3465           && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3466           && (! WORDS_BIG_ENDIAN
3467               || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3468         return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3469
3470       /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3471          since we are saying that the high bits don't matter.  */
3472       if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3473           && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3474         return SUBREG_REG (x);
3475
3476       /* Note that we cannot do any narrowing for non-constants since
3477          we might have been counting on using the fact that some bits were
3478          zero.  We now do this in the SET.  */
3479
3480       break;
3481
3482     case NOT:
3483       /* (not (plus X -1)) can become (neg X).  */
3484       if (GET_CODE (XEXP (x, 0)) == PLUS
3485           && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3486         return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3487
3488       /* Similarly, (not (neg X)) is (plus X -1).  */
3489       if (GET_CODE (XEXP (x, 0)) == NEG)
3490         return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3491                                 constm1_rtx);
3492
3493       /* (not (xor X C)) for C constant is (xor X D) with D = ~ C.  */
3494       if (GET_CODE (XEXP (x, 0)) == XOR
3495           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3496           && (temp = simplify_unary_operation (NOT, mode,
3497                                                XEXP (XEXP (x, 0), 1),
3498                                                mode)) != 0)
3499         return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3500
3501       /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
3502          other than 1, but that is not valid.  We could do a similar
3503          simplification for (not (lshiftrt C X)) where C is just the sign bit,
3504          but this doesn't seem common enough to bother with.  */
3505       if (GET_CODE (XEXP (x, 0)) == ASHIFT
3506           && XEXP (XEXP (x, 0), 0) == const1_rtx)
3507         return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3508                         XEXP (XEXP (x, 0), 1));
3509
3510       if (GET_CODE (XEXP (x, 0)) == SUBREG
3511           && subreg_lowpart_p (XEXP (x, 0))
3512           && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3513               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3514           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3515           && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3516         {
3517           enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3518
3519           x = gen_rtx (ROTATE, inner_mode,
3520                        gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3521                        XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3522           return gen_lowpart_for_combine (mode, x);
3523         }
3524
3525       /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3526          reversing the comparison code if valid.  */
3527       if (STORE_FLAG_VALUE == -1
3528           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3529           && reversible_comparison_p (XEXP (x, 0)))
3530         return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3531                                 mode, XEXP (XEXP (x, 0), 0),
3532                                 XEXP (XEXP (x, 0), 1));
3533
3534       /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3535          is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3536          perform the above simplification.  */
3537
3538       if (STORE_FLAG_VALUE == -1
3539           && XEXP (x, 1) == const1_rtx
3540           && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3541           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3542           && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3543         return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3544
3545       /* Apply De Morgan's laws to reduce number of patterns for machines
3546          with negating logical insns (and-not, nand, etc.).  If result has
3547          only one NOT, put it first, since that is how the patterns are
3548          coded.  */
3549
3550       if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3551         {
3552          rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3553
3554          if (GET_CODE (in1) == NOT)
3555            in1 = XEXP (in1, 0);
3556          else
3557            in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3558
3559          if (GET_CODE (in2) == NOT)
3560            in2 = XEXP (in2, 0);
3561          else if (GET_CODE (in2) == CONST_INT
3562                   && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3563            in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3564          else
3565            in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3566
3567          if (GET_CODE (in2) == NOT)
3568            {
3569              rtx tem = in2;
3570              in2 = in1; in1 = tem;
3571            }
3572
3573          return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3574                                  mode, in1, in2);
3575        }
3576       break;
3577
3578     case NEG:
3579       /* (neg (plus X 1)) can become (not X).  */
3580       if (GET_CODE (XEXP (x, 0)) == PLUS
3581           && XEXP (XEXP (x, 0), 1) == const1_rtx)
3582         return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3583
3584       /* Similarly, (neg (not X)) is (plus X 1).  */
3585       if (GET_CODE (XEXP (x, 0)) == NOT)
3586         return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3587
3588       /* (neg (minus X Y)) can become (minus Y X).  */
3589       if (GET_CODE (XEXP (x, 0)) == MINUS
3590           && (! FLOAT_MODE_P (mode)
3591               /* x-y != -(y-x) with IEEE floating point.  */
3592               || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3593               || flag_fast_math))
3594         return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3595                            XEXP (XEXP (x, 0), 0));
3596
3597       /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
3598       if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3599           && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3600         return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3601
3602       /* NEG commutes with ASHIFT since it is multiplication.  Only do this
3603          if we can then eliminate the NEG (e.g.,
3604          if the operand is a constant).  */
3605
3606       if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3607         {
3608           temp = simplify_unary_operation (NEG, mode,
3609                                            XEXP (XEXP (x, 0), 0), mode);
3610           if (temp)
3611             {
3612               SUBST (XEXP (XEXP (x, 0), 0), temp);
3613               return XEXP (x, 0);
3614             }
3615         }
3616
3617       temp = expand_compound_operation (XEXP (x, 0));
3618
3619       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3620          replaced by (lshiftrt X C).  This will convert
3621          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
3622
3623       if (GET_CODE (temp) == ASHIFTRT
3624           && GET_CODE (XEXP (temp, 1)) == CONST_INT
3625           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3626         return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3627                                      INTVAL (XEXP (temp, 1)));
3628
3629       /* If X has only a single bit that might be nonzero, say, bit I, convert
3630          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3631          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
3632          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
3633          or a SUBREG of one since we'd be making the expression more
3634          complex if it was just a register.  */
3635
3636       if (GET_CODE (temp) != REG
3637           && ! (GET_CODE (temp) == SUBREG
3638                 && GET_CODE (SUBREG_REG (temp)) == REG)
3639           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3640         {
3641           rtx temp1 = simplify_shift_const
3642             (NULL_RTX, ASHIFTRT, mode,
3643              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3644                                    GET_MODE_BITSIZE (mode) - 1 - i),
3645              GET_MODE_BITSIZE (mode) - 1 - i);
3646
3647           /* If all we did was surround TEMP with the two shifts, we
3648              haven't improved anything, so don't use it.  Otherwise,
3649              we are better off with TEMP1.  */
3650           if (GET_CODE (temp1) != ASHIFTRT
3651               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3652               || XEXP (XEXP (temp1, 0), 0) != temp)
3653             return temp1;
3654         }
3655       break;
3656
3657     case TRUNCATE:
3658       /* We can't handle truncation to a partial integer mode here
3659          because we don't know the real bitsize of the partial
3660          integer mode.  */
3661       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3662         break;
3663
3664       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3665         SUBST (XEXP (x, 0),
3666                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3667                               GET_MODE_MASK (mode), NULL_RTX, 0));
3668
3669       /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
3670       if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3671            || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3672           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3673         return XEXP (XEXP (x, 0), 0);
3674
3675       /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3676          (OP:SI foo:SI) if OP is NEG or ABS.  */
3677       if ((GET_CODE (XEXP (x, 0)) == ABS
3678            || GET_CODE (XEXP (x, 0)) == NEG)
3679           && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3680               || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3681           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3682         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3683                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3684
3685       /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3686          (truncate:SI x).  */
3687       if (GET_CODE (XEXP (x, 0)) == SUBREG
3688           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3689           && subreg_lowpart_p (XEXP (x, 0)))
3690         return SUBREG_REG (XEXP (x, 0));
3691
3692       /* If we know that the value is already truncated, we can
3693          replace the TRUNCATE with a SUBREG.  */
3694       if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3695           && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3696               &~ GET_MODE_MASK (mode)) == 0)
3697         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3698
3699       /* A truncate of a comparison can be replaced with a subreg if
3700          STORE_FLAG_VALUE permits.  This is like the previous test,
3701          but it works even if the comparison is done in a mode larger
3702          than HOST_BITS_PER_WIDE_INT.  */
3703       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3704           && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3705           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3706         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3707
3708       /* Similarly, a truncate of a register whose value is a
3709          comparison can be replaced with a subreg if STORE_FLAG_VALUE
3710          permits.  */
3711       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3712           && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3713           && (temp = get_last_value (XEXP (x, 0)))
3714           && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3715         return gen_lowpart_for_combine (mode, XEXP (x, 0));
3716
3717       break;
3718
3719     case FLOAT_TRUNCATE:
3720       /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
3721       if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3722           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3723         return XEXP (XEXP (x, 0), 0);
3724
3725       /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3726          (OP:SF foo:SF) if OP is NEG or ABS.  */
3727       if ((GET_CODE (XEXP (x, 0)) == ABS
3728            || GET_CODE (XEXP (x, 0)) == NEG)
3729           && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3730           && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3731         return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3732                           XEXP (XEXP (XEXP (x, 0), 0), 0));
3733
3734       /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3735          is (float_truncate:SF x).  */
3736       if (GET_CODE (XEXP (x, 0)) == SUBREG
3737           && subreg_lowpart_p (XEXP (x, 0))
3738           && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3739         return SUBREG_REG (XEXP (x, 0));
3740       break;
3741
3742 #ifdef HAVE_cc0
3743     case COMPARE:
3744       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3745          using cc0, in which case we want to leave it as a COMPARE
3746          so we can distinguish it from a register-register-copy.  */
3747       if (XEXP (x, 1) == const0_rtx)
3748         return XEXP (x, 0);
3749
3750       /* In IEEE floating point, x-0 is not the same as x.  */
3751       if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3752            || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3753            || flag_fast_math)
3754           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3755         return XEXP (x, 0);
3756       break;
3757 #endif
3758
3759     case CONST:
3760       /* (const (const X)) can become (const X).  Do it this way rather than
3761          returning the inner CONST since CONST can be shared with a
3762          REG_EQUAL note.  */
3763       if (GET_CODE (XEXP (x, 0)) == CONST)
3764         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3765       break;
3766
3767 #ifdef HAVE_lo_sum
3768     case LO_SUM:
3769       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
3770          can add in an offset.  find_split_point will split this address up
3771          again if it doesn't match.  */
3772       if (GET_CODE (XEXP (x, 0)) == HIGH
3773           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3774         return XEXP (x, 1);
3775       break;
3776 #endif
3777
3778     case PLUS:
3779       /* If we have (plus (plus (A const) B)), associate it so that CONST is
3780          outermost.  That's because that's the way indexed addresses are
3781          supposed to appear.  This code used to check many more cases, but
3782          they are now checked elsewhere.  */
3783       if (GET_CODE (XEXP (x, 0)) == PLUS
3784           && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3785         return gen_binary (PLUS, mode,
3786                            gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3787                                        XEXP (x, 1)),
3788                            XEXP (XEXP (x, 0), 1));
3789
3790       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3791          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3792          bit-field and can be replaced by either a sign_extend or a
3793          sign_extract.  The `and' may be a zero_extend.  */
3794       if (GET_CODE (XEXP (x, 0)) == XOR
3795           && GET_CODE (XEXP (x, 1)) == CONST_INT
3796           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3797           && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3798           && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3799           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3800           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3801                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3802                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3803                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3804               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3805                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3806                       == i + 1))))
3807         return simplify_shift_const
3808           (NULL_RTX, ASHIFTRT, mode,
3809            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3810                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
3811                                  GET_MODE_BITSIZE (mode) - (i + 1)),
3812            GET_MODE_BITSIZE (mode) - (i + 1));
3813
3814       /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3815          C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3816          is 1.  This produces better code than the alternative immediately
3817          below.  */
3818       if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3819           && reversible_comparison_p (XEXP (x, 0))
3820           && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3821               || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3822         return
3823           gen_unary (NEG, mode, mode,
3824                      gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3825                                  mode, XEXP (XEXP (x, 0), 0),
3826                                  XEXP (XEXP (x, 0), 1)));
3827
3828       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3829          can become (ashiftrt (ashift (xor x 1) C) C) where C is
3830          the bitsize of the mode - 1.  This allows simplification of
3831          "a = (b & 8) == 0;"  */
3832       if (XEXP (x, 1) == constm1_rtx
3833           && GET_CODE (XEXP (x, 0)) != REG
3834           && ! (GET_CODE (XEXP (x,0)) == SUBREG
3835                 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3836           && nonzero_bits (XEXP (x, 0), mode) == 1)
3837         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3838            simplify_shift_const (NULL_RTX, ASHIFT, mode,
3839                                  gen_rtx_combine (XOR, mode,
3840                                                   XEXP (x, 0), const1_rtx),
3841                                  GET_MODE_BITSIZE (mode) - 1),
3842            GET_MODE_BITSIZE (mode) - 1);
3843
3844       /* If we are adding two things that have no bits in common, convert
3845          the addition into an IOR.  This will often be further simplified,
3846          for example in cases like ((a & 1) + (a & 2)), which can
3847          become a & 3.  */
3848
3849       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3850           && (nonzero_bits (XEXP (x, 0), mode)
3851               & nonzero_bits (XEXP (x, 1), mode)) == 0)
3852         return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3853       break;
3854
3855     case MINUS:
3856       /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3857          by reversing the comparison code if valid.  */
3858       if (STORE_FLAG_VALUE == 1
3859           && XEXP (x, 0) == const1_rtx
3860           && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3861           && reversible_comparison_p (XEXP (x, 1)))
3862         return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3863                            mode, XEXP (XEXP (x, 1), 0),
3864                                 XEXP (XEXP (x, 1), 1));
3865
3866       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3867          (and <foo> (const_int pow2-1))  */
3868       if (GET_CODE (XEXP (x, 1)) == AND
3869           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3870           && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3871           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3872         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3873                                        - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3874
3875       /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3876          integers.  */
3877       if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3878         return gen_binary (MINUS, mode,
3879                            gen_binary (MINUS, mode, XEXP (x, 0),
3880                                        XEXP (XEXP (x, 1), 0)),
3881                            XEXP (XEXP (x, 1), 1));
3882       break;
3883
3884     case MULT:
3885       /* If we have (mult (plus A B) C), apply the distributive law and then
3886          the inverse distributive law to see if things simplify.  This
3887          occurs mostly in addresses, often when unrolling loops.  */
3888
3889       if (GET_CODE (XEXP (x, 0)) == PLUS)
3890         {
3891           x = apply_distributive_law
3892             (gen_binary (PLUS, mode,
3893                          gen_binary (MULT, mode,
3894                                      XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3895                          gen_binary (MULT, mode,
3896                                      XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3897
3898           if (GET_CODE (x) != MULT)
3899             return x;
3900         }
3901       break;
3902
3903     case UDIV:
3904       /* If this is a divide by a power of two, treat it as a shift if
3905          its first operand is a shift.  */
3906       if (GET_CODE (XEXP (x, 1)) == CONST_INT
3907           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3908           && (GET_CODE (XEXP (x, 0)) == ASHIFT
3909               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3910               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3911               || GET_CODE (XEXP (x, 0)) == ROTATE
3912               || GET_CODE (XEXP (x, 0)) == ROTATERT))
3913         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3914       break;
3915
3916     case EQ:  case NE:
3917     case GT:  case GTU:  case GE:  case GEU:
3918     case LT:  case LTU:  case LE:  case LEU:
3919       /* If the first operand is a condition code, we can't do anything
3920          with it.  */
3921       if (GET_CODE (XEXP (x, 0)) == COMPARE
3922           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3923 #ifdef HAVE_cc0
3924               && XEXP (x, 0) != cc0_rtx
3925 #endif
3926                ))
3927         {
3928           rtx op0 = XEXP (x, 0);
3929           rtx op1 = XEXP (x, 1);
3930           enum rtx_code new_code;
3931
3932           if (GET_CODE (op0) == COMPARE)
3933             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3934
3935           /* Simplify our comparison, if possible.  */
3936           new_code = simplify_comparison (code, &op0, &op1);
3937
3938           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3939              if only the low-order bit is possibly nonzero in X (such as when
3940              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
3941              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
3942              known to be either 0 or -1, NE becomes a NEG and EQ becomes
3943              (plus X 1).
3944
3945              Remove any ZERO_EXTRACT we made when thinking this was a
3946              comparison.  It may now be simpler to use, e.g., an AND.  If a
3947              ZERO_EXTRACT is indeed appropriate, it will be placed back by
3948              the call to make_compound_operation in the SET case.  */
3949
3950           if (STORE_FLAG_VALUE == 1
3951               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3952               && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3953             return gen_lowpart_for_combine (mode,
3954                                             expand_compound_operation (op0));
3955
3956           else if (STORE_FLAG_VALUE == 1
3957                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3958                    && op1 == const0_rtx
3959                    && (num_sign_bit_copies (op0, mode)
3960                        == GET_MODE_BITSIZE (mode)))
3961             {
3962               op0 = expand_compound_operation (op0);
3963               return gen_unary (NEG, mode, mode,
3964                                 gen_lowpart_for_combine (mode, op0));
3965             }
3966
3967           else if (STORE_FLAG_VALUE == 1
3968                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3969                    && op1 == const0_rtx
3970                    && nonzero_bits (op0, mode) == 1)
3971             {
3972               op0 = expand_compound_operation (op0);
3973               return gen_binary (XOR, mode,
3974                                  gen_lowpart_for_combine (mode, op0),
3975                                  const1_rtx);
3976             }
3977
3978           else if (STORE_FLAG_VALUE == 1
3979                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3980                    && op1 == const0_rtx
3981                    && (num_sign_bit_copies (op0, mode)
3982                        == GET_MODE_BITSIZE (mode)))
3983             {
3984               op0 = expand_compound_operation (op0);
3985               return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3986             }
3987
3988           /* If STORE_FLAG_VALUE is -1, we have cases similar to
3989              those above.  */
3990           if (STORE_FLAG_VALUE == -1
3991               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3992               && op1 == const0_rtx
3993               && (num_sign_bit_copies (op0, mode)
3994                   == GET_MODE_BITSIZE (mode)))
3995             return gen_lowpart_for_combine (mode,
3996                                             expand_compound_operation (op0));
3997
3998           else if (STORE_FLAG_VALUE == -1
3999                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4000                    && op1 == const0_rtx
4001                    && nonzero_bits (op0, mode) == 1)
4002             {
4003               op0 = expand_compound_operation (op0);
4004               return gen_unary (NEG, mode, mode,
4005                                 gen_lowpart_for_combine (mode, op0));
4006             }
4007
4008           else if (STORE_FLAG_VALUE == -1
4009                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4010                    && op1 == const0_rtx
4011                    && (num_sign_bit_copies (op0, mode)
4012                        == GET_MODE_BITSIZE (mode)))
4013             {
4014               op0 = expand_compound_operation (op0);
4015               return gen_unary (NOT, mode, mode,
4016                                 gen_lowpart_for_combine (mode, op0));
4017             }
4018
4019           /* If X is 0/1, (eq X 0) is X-1.  */
4020           else if (STORE_FLAG_VALUE == -1
4021                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4022                    && op1 == const0_rtx
4023                    && nonzero_bits (op0, mode) == 1)
4024             {
4025               op0 = expand_compound_operation (op0);
4026               return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4027             }
4028
4029           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4030              one bit that might be nonzero, we can convert (ne x 0) to
4031              (ashift x c) where C puts the bit in the sign bit.  Remove any
4032              AND with STORE_FLAG_VALUE when we are done, since we are only
4033              going to test the sign bit.  */
4034           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4035               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4036               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4037                   == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4038               && op1 == const0_rtx
4039               && mode == GET_MODE (op0)
4040               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4041             {
4042               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4043                                         expand_compound_operation (op0),
4044                                         GET_MODE_BITSIZE (mode) - 1 - i);
4045               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4046                 return XEXP (x, 0);
4047               else
4048                 return x;
4049             }
4050
4051           /* If the code changed, return a whole new comparison.  */
4052           if (new_code != code)
4053             return gen_rtx_combine (new_code, mode, op0, op1);
4054
4055           /* Otherwise, keep this operation, but maybe change its operands.
4056              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4057           SUBST (XEXP (x, 0), op0);
4058           SUBST (XEXP (x, 1), op1);
4059         }
4060       break;
4061
4062     case IF_THEN_ELSE:
4063       return simplify_if_then_else (x);
4064
4065     case ZERO_EXTRACT:
4066     case SIGN_EXTRACT:
4067     case ZERO_EXTEND:
4068     case SIGN_EXTEND:
4069       /* If we are processing SET_DEST, we are done.  */
4070       if (in_dest)
4071         return x;
4072
4073       return expand_compound_operation (x);
4074
4075     case SET:
4076       return simplify_set (x);
4077
4078     case AND:
4079     case IOR:
4080     case XOR:
4081       return simplify_logical (x, last);
4082
4083     case ABS:
4084       /* (abs (neg <foo>)) -> (abs <foo>) */
4085       if (GET_CODE (XEXP (x, 0)) == NEG)
4086         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4087
4088       /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4089          do nothing.  */
4090       if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4091         break;
4092
4093       /* If operand is something known to be positive, ignore the ABS.  */
4094       if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4095           || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4096                <= HOST_BITS_PER_WIDE_INT)
4097               && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4098                    & ((HOST_WIDE_INT) 1
4099                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4100                   == 0)))
4101         return XEXP (x, 0);
4102
4103
4104       /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
4105       if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4106         return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4107
4108       break;
4109
4110     case FFS:
4111       /* (ffs (*_extend <X>)) = (ffs <X>) */
4112       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4113           || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4114         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4115       break;
4116
4117     case FLOAT:
4118       /* (float (sign_extend <X>)) = (float <X>).  */
4119       if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4120         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4121       break;
4122
4123     case ASHIFT:
4124     case LSHIFTRT:
4125     case ASHIFTRT:
4126     case ROTATE:
4127     case ROTATERT:
4128       /* If this is a shift by a constant amount, simplify it.  */
4129       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4130         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4131                                      INTVAL (XEXP (x, 1)));
4132
4133 #ifdef SHIFT_COUNT_TRUNCATED
4134       else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4135         SUBST (XEXP (x, 1),
4136                force_to_mode (XEXP (x, 1), GET_MODE (x),
4137                               ((HOST_WIDE_INT) 1
4138                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4139                               - 1,
4140                               NULL_RTX, 0));
4141 #endif
4142
4143       break;
4144
4145     default:
4146       break;
4147     }
4148
4149   return x;
4150 }
4151 \f
4152 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4153
4154 static rtx
4155 simplify_if_then_else (x)
4156      rtx x;
4157 {
4158   enum machine_mode mode = GET_MODE (x);
4159   rtx cond = XEXP (x, 0);
4160   rtx true = XEXP (x, 1);
4161   rtx false = XEXP (x, 2);
4162   enum rtx_code true_code = GET_CODE (cond);
4163   int comparison_p = GET_RTX_CLASS (true_code) == '<';
4164   rtx temp;
4165   int i;
4166
4167   /* Simplify storing of the truth value.  */
4168   if (comparison_p && true == const_true_rtx && false == const0_rtx)
4169     return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4170
4171   /* Also when the truth value has to be reversed.  */
4172   if (comparison_p && reversible_comparison_p (cond)
4173       && true == const0_rtx && false == const_true_rtx)
4174     return gen_binary (reverse_condition (true_code),
4175                        mode, XEXP (cond, 0), XEXP (cond, 1));
4176
4177   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4178      in it is being compared against certain values.  Get the true and false
4179      comparisons and see if that says anything about the value of each arm.  */
4180
4181   if (comparison_p && reversible_comparison_p (cond)
4182       && GET_CODE (XEXP (cond, 0)) == REG)
4183     {
4184       HOST_WIDE_INT nzb;
4185       rtx from = XEXP (cond, 0);
4186       enum rtx_code false_code = reverse_condition (true_code);
4187       rtx true_val = XEXP (cond, 1);
4188       rtx false_val = true_val;
4189       int swapped = 0;
4190
4191       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4192
4193       if (false_code == EQ)
4194         {
4195           swapped = 1, true_code = EQ, false_code = NE;
4196           temp = true, true = false, false = temp;
4197         }
4198
4199       /* If we are comparing against zero and the expression being tested has
4200          only a single bit that might be nonzero, that is its value when it is
4201          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4202
4203       if (true_code == EQ && true_val == const0_rtx
4204           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4205         false_code = EQ, false_val = GEN_INT (nzb);
4206       else if (true_code == EQ && true_val == const0_rtx
4207                && (num_sign_bit_copies (from, GET_MODE (from))
4208                    == GET_MODE_BITSIZE (GET_MODE (from))))
4209         false_code = EQ, false_val = constm1_rtx;
4210
4211       /* Now simplify an arm if we know the value of the register in the
4212          branch and it is used in the arm.  Be careful due to the potential
4213          of locally-shared RTL.  */
4214
4215       if (reg_mentioned_p (from, true))
4216         true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4217                       pc_rtx, pc_rtx, 0, 0);
4218       if (reg_mentioned_p (from, false))
4219         false = subst (known_cond (copy_rtx (false), false_code,
4220                                    from, false_val),
4221                        pc_rtx, pc_rtx, 0, 0);
4222
4223       SUBST (XEXP (x, 1), swapped ? false : true);
4224       SUBST (XEXP (x, 2), swapped ? true : false);
4225
4226       true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4227     }
4228
4229   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4230      reversed, do so to avoid needing two sets of patterns for
4231      subtract-and-branch insns.  Similarly if we have a constant in the true
4232      arm, the false arm is the same as the first operand of the comparison, or
4233      the false arm is more complicated than the true arm.  */
4234
4235   if (comparison_p && reversible_comparison_p (cond)
4236       && (true == pc_rtx
4237           || (CONSTANT_P (true)
4238               && GET_CODE (false) != CONST_INT && false != pc_rtx)
4239           || true == const0_rtx
4240           || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4241               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4242           || (GET_CODE (true) == SUBREG
4243               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4244               && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4245           || reg_mentioned_p (true, false)
4246           || rtx_equal_p (false, XEXP (cond, 0))))
4247     {
4248       true_code = reverse_condition (true_code);
4249       SUBST (XEXP (x, 0),
4250              gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4251                          XEXP (cond, 1)));
4252
4253       SUBST (XEXP (x, 1), false);
4254       SUBST (XEXP (x, 2), true);
4255
4256       temp = true, true = false, false = temp, cond = XEXP (x, 0);
4257
4258       /* It is possible that the conditional has been simplified out.  */
4259       true_code = GET_CODE (cond);
4260       comparison_p = GET_RTX_CLASS (true_code) == '<';
4261     }
4262
4263   /* If the two arms are identical, we don't need the comparison.  */
4264
4265   if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4266     return true;
4267
4268   /* Convert a == b ? b : a to "a".  */
4269   if (true_code == EQ && ! side_effects_p (cond)
4270       && rtx_equal_p (XEXP (cond, 0), false)
4271       && rtx_equal_p (XEXP (cond, 1), true))
4272     return false;
4273   else if (true_code == NE && ! side_effects_p (cond)
4274            && rtx_equal_p (XEXP (cond, 0), true)
4275            && rtx_equal_p (XEXP (cond, 1), false))
4276     return true;
4277
4278   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4279
4280   if (GET_MODE_CLASS (mode) == MODE_INT
4281       && GET_CODE (false) == NEG
4282       && rtx_equal_p (true, XEXP (false, 0))
4283       && comparison_p
4284       && rtx_equal_p (true, XEXP (cond, 0))
4285       && ! side_effects_p (true))
4286     switch (true_code)
4287       {
4288       case GT:
4289       case GE:
4290         return gen_unary (ABS, mode, mode, true);
4291       case LT:
4292       case LE:
4293         return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4294     default:
4295       break;
4296       }
4297
4298   /* Look for MIN or MAX.  */
4299
4300   if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4301       && comparison_p
4302       && rtx_equal_p (XEXP (cond, 0), true)
4303       && rtx_equal_p (XEXP (cond, 1), false)
4304       && ! side_effects_p (cond))
4305     switch (true_code)
4306       {
4307       case GE:
4308       case GT:
4309         return gen_binary (SMAX, mode, true, false);
4310       case LE:
4311       case LT:
4312         return gen_binary (SMIN, mode, true, false);
4313       case GEU:
4314       case GTU:
4315         return gen_binary (UMAX, mode, true, false);
4316       case LEU:
4317       case LTU:
4318         return gen_binary (UMIN, mode, true, false);
4319       default:
4320         break;
4321       }
4322
4323   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4324      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4325      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4326      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4327      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4328      neither 1 or -1, but it isn't worth checking for.  */
4329
4330   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4331       && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4332     {
4333       rtx t = make_compound_operation (true, SET);
4334       rtx f = make_compound_operation (false, SET);
4335       rtx cond_op0 = XEXP (cond, 0);
4336       rtx cond_op1 = XEXP (cond, 1);
4337       enum rtx_code op, extend_op = NIL;
4338       enum machine_mode m = mode;
4339       rtx z = 0, c1;
4340
4341       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4342            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4343            || GET_CODE (t) == ASHIFT
4344            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4345           && rtx_equal_p (XEXP (t, 0), f))
4346         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4347
4348       /* If an identity-zero op is commutative, check whether there
4349          would be a match if we swapped the operands.  */
4350       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4351                 || GET_CODE (t) == XOR)
4352                && rtx_equal_p (XEXP (t, 1), f))
4353         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4354       else if (GET_CODE (t) == SIGN_EXTEND
4355                && (GET_CODE (XEXP (t, 0)) == PLUS
4356                    || GET_CODE (XEXP (t, 0)) == MINUS
4357                    || GET_CODE (XEXP (t, 0)) == IOR
4358                    || GET_CODE (XEXP (t, 0)) == XOR
4359                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4360                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4361                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4362                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4363                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4364                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4365                && (num_sign_bit_copies (f, GET_MODE (f))
4366                    > (GET_MODE_BITSIZE (mode)
4367                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4368         {
4369           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4370           extend_op = SIGN_EXTEND;
4371           m = GET_MODE (XEXP (t, 0));
4372         }
4373       else if (GET_CODE (t) == SIGN_EXTEND
4374                && (GET_CODE (XEXP (t, 0)) == PLUS
4375                    || GET_CODE (XEXP (t, 0)) == IOR
4376                    || GET_CODE (XEXP (t, 0)) == XOR)
4377                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4378                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4379                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4380                && (num_sign_bit_copies (f, GET_MODE (f))
4381                    > (GET_MODE_BITSIZE (mode)
4382                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4383         {
4384           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4385           extend_op = SIGN_EXTEND;
4386           m = GET_MODE (XEXP (t, 0));
4387         }
4388       else if (GET_CODE (t) == ZERO_EXTEND
4389                && (GET_CODE (XEXP (t, 0)) == PLUS
4390                    || GET_CODE (XEXP (t, 0)) == MINUS
4391                    || GET_CODE (XEXP (t, 0)) == IOR
4392                    || GET_CODE (XEXP (t, 0)) == XOR
4393                    || GET_CODE (XEXP (t, 0)) == ASHIFT
4394                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4395                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4396                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4397                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4398                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4399                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4400                && ((nonzero_bits (f, GET_MODE (f))
4401                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4402                    == 0))
4403         {
4404           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4405           extend_op = ZERO_EXTEND;
4406           m = GET_MODE (XEXP (t, 0));
4407         }
4408       else if (GET_CODE (t) == ZERO_EXTEND
4409                && (GET_CODE (XEXP (t, 0)) == PLUS
4410                    || GET_CODE (XEXP (t, 0)) == IOR
4411                    || GET_CODE (XEXP (t, 0)) == XOR)
4412                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4413                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4414                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4415                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4416                && ((nonzero_bits (f, GET_MODE (f))
4417                     & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4418                    == 0))
4419         {
4420           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4421           extend_op = ZERO_EXTEND;
4422           m = GET_MODE (XEXP (t, 0));
4423         }
4424
4425       if (z)
4426         {
4427           temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4428                         pc_rtx, pc_rtx, 0, 0);
4429           temp = gen_binary (MULT, m, temp,
4430                              gen_binary (MULT, m, c1, const_true_rtx));
4431           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4432           temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4433
4434           if (extend_op != NIL)
4435             temp = gen_unary (extend_op, mode, m, temp);
4436
4437           return temp;
4438         }
4439     }
4440
4441   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4442      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4443      negation of a single bit, we can convert this operation to a shift.  We
4444      can actually do this more generally, but it doesn't seem worth it.  */
4445
4446   if (true_code == NE && XEXP (cond, 1) == const0_rtx
4447       && false == const0_rtx && GET_CODE (true) == CONST_INT
4448       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4449            && (i = exact_log2 (INTVAL (true))) >= 0)
4450           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4451                == GET_MODE_BITSIZE (mode))
4452               && (i = exact_log2 (- INTVAL (true))) >= 0)))
4453     return
4454       simplify_shift_const (NULL_RTX, ASHIFT, mode,
4455                             gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4456
4457   return x;
4458 }
4459 \f
4460 /* Simplify X, a SET expression.  Return the new expression.  */
4461
4462 static rtx
4463 simplify_set (x)
4464      rtx x;
4465 {
4466   rtx src = SET_SRC (x);
4467   rtx dest = SET_DEST (x);
4468   enum machine_mode mode
4469     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4470   rtx other_insn;
4471   rtx *cc_use;
4472
4473   /* (set (pc) (return)) gets written as (return).  */
4474   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4475     return src;
4476
4477   /* Now that we know for sure which bits of SRC we are using, see if we can
4478      simplify the expression for the object knowing that we only need the
4479      low-order bits.  */
4480
4481   if (GET_MODE_CLASS (mode) == MODE_INT)
4482     src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4483
4484   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4485      the comparison result and try to simplify it unless we already have used
4486      undobuf.other_insn.  */
4487   if ((GET_CODE (src) == COMPARE
4488 #ifdef HAVE_cc0
4489        || dest == cc0_rtx
4490 #endif
4491        )
4492       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4493       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4494       && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4495       && rtx_equal_p (XEXP (*cc_use, 0), dest))
4496     {
4497       enum rtx_code old_code = GET_CODE (*cc_use);
4498       enum rtx_code new_code;
4499       rtx op0, op1;
4500       int other_changed = 0;
4501       enum machine_mode compare_mode = GET_MODE (dest);
4502
4503       if (GET_CODE (src) == COMPARE)
4504         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4505       else
4506         op0 = src, op1 = const0_rtx;
4507
4508       /* Simplify our comparison, if possible.  */
4509       new_code = simplify_comparison (old_code, &op0, &op1);
4510
4511 #ifdef EXTRA_CC_MODES
4512       /* If this machine has CC modes other than CCmode, check to see if we
4513          need to use a different CC mode here.  */
4514       compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4515 #endif /* EXTRA_CC_MODES */
4516
4517 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4518       /* If the mode changed, we have to change SET_DEST, the mode in the
4519          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
4520          a hard register, just build new versions with the proper mode.  If it
4521          is a pseudo, we lose unless it is only time we set the pseudo, in
4522          which case we can safely change its mode.  */
4523       if (compare_mode != GET_MODE (dest))
4524         {
4525           int regno = REGNO (dest);
4526           rtx new_dest = gen_rtx (REG, compare_mode, regno);
4527
4528           if (regno < FIRST_PSEUDO_REGISTER
4529               || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4530             {
4531               if (regno >= FIRST_PSEUDO_REGISTER)
4532                 SUBST (regno_reg_rtx[regno], new_dest);
4533
4534               SUBST (SET_DEST (x), new_dest);
4535               SUBST (XEXP (*cc_use, 0), new_dest);
4536               other_changed = 1;
4537
4538               dest = new_dest;
4539             }
4540         }
4541 #endif
4542
4543       /* If the code changed, we have to build a new comparison in
4544          undobuf.other_insn.  */
4545       if (new_code != old_code)
4546         {
4547           unsigned HOST_WIDE_INT mask;
4548
4549           SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4550                                            dest, const0_rtx));
4551
4552           /* If the only change we made was to change an EQ into an NE or
4553              vice versa, OP0 has only one bit that might be nonzero, and OP1
4554              is zero, check if changing the user of the condition code will
4555              produce a valid insn.  If it won't, we can keep the original code
4556              in that insn by surrounding our operation with an XOR.  */
4557
4558           if (((old_code == NE && new_code == EQ)
4559                || (old_code == EQ && new_code == NE))
4560               && ! other_changed && op1 == const0_rtx
4561               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4562               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4563             {
4564               rtx pat = PATTERN (other_insn), note = 0;
4565               int scratches;
4566
4567               if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
4568                    && ! check_asm_operands (pat)))
4569                 {
4570                   PUT_CODE (*cc_use, old_code);
4571                   other_insn = 0;
4572
4573                   op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4574                 }
4575             }
4576
4577           other_changed = 1;
4578         }
4579
4580       if (other_changed)
4581         undobuf.other_insn = other_insn;
4582
4583 #ifdef HAVE_cc0
4584       /* If we are now comparing against zero, change our source if
4585          needed.  If we do not use cc0, we always have a COMPARE.  */
4586       if (op1 == const0_rtx && dest == cc0_rtx)
4587         {
4588           SUBST (SET_SRC (x), op0);
4589           src = op0;
4590         }
4591       else
4592 #endif
4593
4594       /* Otherwise, if we didn't previously have a COMPARE in the
4595          correct mode, we need one.  */
4596       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4597         {
4598           SUBST (SET_SRC (x),
4599                  gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4600           src = SET_SRC (x);
4601         }
4602       else
4603         {
4604           /* Otherwise, update the COMPARE if needed.  */
4605           SUBST (XEXP (src, 0), op0);
4606           SUBST (XEXP (src, 1), op1);
4607         }
4608     }
4609   else
4610     {
4611       /* Get SET_SRC in a form where we have placed back any
4612          compound expressions.  Then do the checks below.  */
4613       src = make_compound_operation (src, SET);
4614       SUBST (SET_SRC (x), src);
4615     }
4616
4617   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4618      and X being a REG or (subreg (reg)), we may be able to convert this to
4619      (set (subreg:m2 x) (op)).
4620
4621      We can always do this if M1 is narrower than M2 because that means that
4622      we only care about the low bits of the result.
4623
4624      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4625      perform a narrower operation that requested since the high-order bits will
4626      be undefined.  On machine where it is defined, this transformation is safe
4627      as long as M1 and M2 have the same number of words.  */
4628
4629   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4630       && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4631       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4632            / UNITS_PER_WORD)
4633           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4634                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4635 #ifndef WORD_REGISTER_OPERATIONS
4636       && (GET_MODE_SIZE (GET_MODE (src))
4637           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4638 #endif
4639 #ifdef CLASS_CANNOT_CHANGE_SIZE
4640       && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4641             && (TEST_HARD_REG_BIT
4642                 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4643                  REGNO (dest)))
4644             && (GET_MODE_SIZE (GET_MODE (src))
4645                 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4646 #endif
4647       && (GET_CODE (dest) == REG
4648           || (GET_CODE (dest) == SUBREG
4649               && GET_CODE (SUBREG_REG (dest)) == REG)))
4650     {
4651       SUBST (SET_DEST (x),
4652              gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4653                                       dest));
4654       SUBST (SET_SRC (x), SUBREG_REG (src));
4655
4656       src = SET_SRC (x), dest = SET_DEST (x);
4657     }
4658
4659 #ifdef LOAD_EXTEND_OP
4660   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4661      would require a paradoxical subreg.  Replace the subreg with a
4662      zero_extend to avoid the reload that would otherwise be required.  */
4663
4664   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4665       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4666       && SUBREG_WORD (src) == 0
4667       && (GET_MODE_SIZE (GET_MODE (src))
4668           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4669       && GET_CODE (SUBREG_REG (src)) == MEM)
4670     {
4671       SUBST (SET_SRC (x),
4672              gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4673                               GET_MODE (src), XEXP (src, 0)));
4674
4675       src = SET_SRC (x);
4676     }
4677 #endif
4678
4679   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4680      are comparing an item known to be 0 or -1 against 0, use a logical
4681      operation instead. Check for one of the arms being an IOR of the other
4682      arm with some value.  We compute three terms to be IOR'ed together.  In
4683      practice, at most two will be nonzero.  Then we do the IOR's.  */
4684
4685   if (GET_CODE (dest) != PC
4686       && GET_CODE (src) == IF_THEN_ELSE
4687       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4688       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4689       && XEXP (XEXP (src, 0), 1) == const0_rtx
4690       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4691 #ifdef HAVE_conditional_move
4692       && ! can_conditionally_move_p (GET_MODE (src))
4693 #endif
4694       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4695                                GET_MODE (XEXP (XEXP (src, 0), 0)))
4696           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4697       && ! side_effects_p (src))
4698     {
4699       rtx true = (GET_CODE (XEXP (src, 0)) == NE
4700                       ? XEXP (src, 1) : XEXP (src, 2));
4701       rtx false = (GET_CODE (XEXP (src, 0)) == NE
4702                    ? XEXP (src, 2) : XEXP (src, 1));
4703       rtx term1 = const0_rtx, term2, term3;
4704
4705       if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4706         term1 = false, true = XEXP (true, 1), false = const0_rtx;
4707       else if (GET_CODE (true) == IOR
4708                && rtx_equal_p (XEXP (true, 1), false))
4709         term1 = false, true = XEXP (true, 0), false = const0_rtx;
4710       else if (GET_CODE (false) == IOR
4711                && rtx_equal_p (XEXP (false, 0), true))
4712         term1 = true, false = XEXP (false, 1), true = const0_rtx;
4713       else if (GET_CODE (false) == IOR
4714                && rtx_equal_p (XEXP (false, 1), true))
4715         term1 = true, false = XEXP (false, 0), true = const0_rtx;
4716
4717       term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4718       term3 = gen_binary (AND, GET_MODE (src),
4719                           gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4720                                      XEXP (XEXP (src, 0), 0)),
4721                           false);
4722
4723       SUBST (SET_SRC (x),
4724              gen_binary (IOR, GET_MODE (src),
4725                          gen_binary (IOR, GET_MODE (src), term1, term2),
4726                          term3));
4727
4728       src = SET_SRC (x);
4729     }
4730
4731   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4732      whole thing fail.  */
4733   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4734     return src;
4735   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4736     return dest;
4737   else
4738     /* Convert this into a field assignment operation, if possible.  */
4739     return make_field_assignment (x);
4740 }
4741 \f
4742 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4743    result.  LAST is nonzero if this is the last retry.  */
4744
4745 static rtx
4746 simplify_logical (x, last)
4747      rtx x;
4748      int last;
4749 {
4750   enum machine_mode mode = GET_MODE (x);
4751   rtx op0 = XEXP (x, 0);
4752   rtx op1 = XEXP (x, 1);
4753
4754   switch (GET_CODE (x))
4755     {
4756     case AND:
4757       /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4758          insn (and may simplify more).  */
4759       if (GET_CODE (op0) == XOR
4760           && rtx_equal_p (XEXP (op0, 0), op1)
4761           && ! side_effects_p (op1))
4762         x = gen_binary (AND, mode,
4763                         gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4764
4765       if (GET_CODE (op0) == XOR
4766           && rtx_equal_p (XEXP (op0, 1), op1)
4767           && ! side_effects_p (op1))
4768         x = gen_binary (AND, mode,
4769                         gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4770
4771       /* Similarly for (~ (A ^ B)) & A.  */
4772       if (GET_CODE (op0) == NOT
4773           && GET_CODE (XEXP (op0, 0)) == XOR
4774           && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4775           && ! side_effects_p (op1))
4776         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4777
4778       if (GET_CODE (op0) == NOT
4779           && GET_CODE (XEXP (op0, 0)) == XOR
4780           && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4781           && ! side_effects_p (op1))
4782         x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4783
4784       if (GET_CODE (op1) == CONST_INT)
4785         {
4786           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4787
4788           /* If we have (ior (and (X C1) C2)) and the next restart would be
4789              the last, simplify this by making C1 as small as possible
4790              and then exit.  */
4791           if (last
4792               && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4793               && GET_CODE (XEXP (op0, 1)) == CONST_INT
4794               && GET_CODE (op1) == CONST_INT)
4795             return gen_binary (IOR, mode,
4796                                gen_binary (AND, mode, XEXP (op0, 0),
4797                                            GEN_INT (INTVAL (XEXP (op0, 1))
4798                                                     & ~ INTVAL (op1))), op1);
4799
4800           if (GET_CODE (x) != AND)
4801             return x;
4802
4803           if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4804               || GET_RTX_CLASS (GET_CODE (x)) == '2')
4805             op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4806         }
4807
4808       /* Convert (A | B) & A to A.  */
4809       if (GET_CODE (op0) == IOR
4810           && (rtx_equal_p (XEXP (op0, 0), op1)
4811               || rtx_equal_p (XEXP (op0, 1), op1))
4812           && ! side_effects_p (XEXP (op0, 0))
4813           && ! side_effects_p (XEXP (op0, 1)))
4814         return op1;
4815
4816       /* In the following group of tests (and those in case IOR below),
4817          we start with some combination of logical operations and apply
4818          the distributive law followed by the inverse distributive law.
4819          Most of the time, this results in no change.  However, if some of
4820          the operands are the same or inverses of each other, simplifications
4821          will result.
4822
4823          For example, (and (ior A B) (not B)) can occur as the result of
4824          expanding a bit field assignment.  When we apply the distributive
4825          law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4826          which then simplifies to (and (A (not B))).
4827
4828          If we have (and (ior A B) C), apply the distributive law and then
4829          the inverse distributive law to see if things simplify.  */
4830
4831       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4832         {
4833           x = apply_distributive_law
4834             (gen_binary (GET_CODE (op0), mode,
4835                          gen_binary (AND, mode, XEXP (op0, 0), op1),
4836                          gen_binary (AND, mode, XEXP (op0, 1), op1)));
4837           if (GET_CODE (x) != AND)
4838             return x;
4839         }
4840
4841       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4842         return apply_distributive_law
4843           (gen_binary (GET_CODE (op1), mode,
4844                        gen_binary (AND, mode, XEXP (op1, 0), op0),
4845                        gen_binary (AND, mode, XEXP (op1, 1), op0)));
4846
4847       /* Similarly, taking advantage of the fact that
4848          (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */
4849
4850       if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4851         return apply_distributive_law
4852           (gen_binary (XOR, mode,
4853                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4854                        gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4855
4856       else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4857         return apply_distributive_law
4858           (gen_binary (XOR, mode,
4859                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4860                        gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4861       break;
4862
4863     case IOR:
4864       /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
4865       if (GET_CODE (op1) == CONST_INT
4866           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4867           && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4868         return op1;
4869
4870       /* Convert (A & B) | A to A.  */
4871       if (GET_CODE (op0) == AND
4872           && (rtx_equal_p (XEXP (op0, 0), op1)
4873               || rtx_equal_p (XEXP (op0, 1), op1))
4874           && ! side_effects_p (XEXP (op0, 0))
4875           && ! side_effects_p (XEXP (op0, 1)))
4876         return op1;
4877
4878       /* If we have (ior (and A B) C), apply the distributive law and then
4879          the inverse distributive law to see if things simplify.  */
4880
4881       if (GET_CODE (op0) == AND)
4882         {
4883           x = apply_distributive_law
4884             (gen_binary (AND, mode,
4885                          gen_binary (IOR, mode, XEXP (op0, 0), op1),
4886                          gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4887
4888           if (GET_CODE (x) != IOR)
4889             return x;
4890         }
4891
4892       if (GET_CODE (op1) == AND)
4893         {
4894           x = apply_distributive_law
4895             (gen_binary (AND, mode,
4896                          gen_binary (IOR, mode, XEXP (op1, 0), op0),
4897                          gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4898
4899           if (GET_CODE (x) != IOR)
4900             return x;
4901         }
4902
4903       /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4904          mode size to (rotate A CX).  */
4905
4906       if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4907            || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4908           && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4909           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4910           && GET_CODE (XEXP (op1, 1)) == CONST_INT
4911           && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4912               == GET_MODE_BITSIZE (mode)))
4913         return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4914                         (GET_CODE (op0) == ASHIFT
4915                          ? XEXP (op0, 1) : XEXP (op1, 1)));
4916
4917       /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4918          a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
4919          does not affect any of the bits in OP1, it can really be done
4920          as a PLUS and we can associate.  We do this by seeing if OP1
4921          can be safely shifted left C bits.  */
4922       if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4923           && GET_CODE (XEXP (op0, 0)) == PLUS
4924           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4925           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4926           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4927         {
4928           int count = INTVAL (XEXP (op0, 1));
4929           HOST_WIDE_INT mask = INTVAL (op1) << count;
4930
4931           if (mask >> count == INTVAL (op1)
4932               && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4933             {
4934               SUBST (XEXP (XEXP (op0, 0), 1),
4935                      GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4936               return op0;
4937             }
4938         }
4939       break;
4940
4941     case XOR:
4942       /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4943          Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4944          (NOT y).  */
4945       {
4946         int num_negated = 0;
4947
4948         if (GET_CODE (op0) == NOT)
4949           num_negated++, op0 = XEXP (op0, 0);
4950         if (GET_CODE (op1) == NOT)
4951           num_negated++, op1 = XEXP (op1, 0);
4952
4953         if (num_negated == 2)
4954           {
4955             SUBST (XEXP (x, 0), op0);
4956             SUBST (XEXP (x, 1), op1);
4957           }
4958         else if (num_negated == 1)
4959           return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4960       }
4961
4962       /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
4963          correspond to a machine insn or result in further simplifications
4964          if B is a constant.  */
4965
4966       if (GET_CODE (op0) == AND
4967           && rtx_equal_p (XEXP (op0, 1), op1)
4968           && ! side_effects_p (op1))
4969         return gen_binary (AND, mode,
4970                            gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4971                            op1);
4972
4973       else if (GET_CODE (op0) == AND
4974                && rtx_equal_p (XEXP (op0, 0), op1)
4975                && ! side_effects_p (op1))
4976         return gen_binary (AND, mode,
4977                            gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4978                            op1);
4979
4980       /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4981          comparison if STORE_FLAG_VALUE is 1.  */
4982       if (STORE_FLAG_VALUE == 1
4983           && op1 == const1_rtx
4984           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4985           && reversible_comparison_p (op0))
4986         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4987                                 mode, XEXP (op0, 0), XEXP (op0, 1));
4988
4989       /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4990          is (lt foo (const_int 0)), so we can perform the above
4991          simplification if STORE_FLAG_VALUE is 1.  */
4992
4993       if (STORE_FLAG_VALUE == 1
4994           && op1 == const1_rtx
4995           && GET_CODE (op0) == LSHIFTRT
4996           && GET_CODE (XEXP (op0, 1)) == CONST_INT
4997           && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4998         return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4999
5000       /* (xor (comparison foo bar) (const_int sign-bit))
5001          when STORE_FLAG_VALUE is the sign bit.  */
5002       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5003           && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5004               == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5005           && op1 == const_true_rtx
5006           && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5007           && reversible_comparison_p (op0))
5008         return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5009                                 mode, XEXP (op0, 0), XEXP (op0, 1));
5010       break;
5011
5012     default:
5013       abort ();
5014     }
5015
5016   return x;
5017 }
5018 \f
5019 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5020    operations" because they can be replaced with two more basic operations.
5021    ZERO_EXTEND is also considered "compound" because it can be replaced with
5022    an AND operation, which is simpler, though only one operation.
5023
5024    The function expand_compound_operation is called with an rtx expression
5025    and will convert it to the appropriate shifts and AND operations,
5026    simplifying at each stage.
5027
5028    The function make_compound_operation is called to convert an expression
5029    consisting of shifts and ANDs into the equivalent compound expression.
5030    It is the inverse of this function, loosely speaking.  */
5031
5032 static rtx
5033 expand_compound_operation (x)
5034      rtx x;
5035 {
5036   int pos = 0, len;
5037   int unsignedp = 0;
5038   int modewidth;
5039   rtx tem;
5040
5041   switch (GET_CODE (x))
5042     {
5043     case ZERO_EXTEND:
5044       unsignedp = 1;
5045     case SIGN_EXTEND:
5046       /* We can't necessarily use a const_int for a multiword mode;
5047          it depends on implicitly extending the value.
5048          Since we don't know the right way to extend it,
5049          we can't tell whether the implicit way is right.
5050
5051          Even for a mode that is no wider than a const_int,
5052          we can't win, because we need to sign extend one of its bits through
5053          the rest of it, and we don't know which bit.  */
5054       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5055         return x;
5056
5057       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5058          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5059          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5060          reloaded. If not for that, MEM's would very rarely be safe.
5061
5062          Reject MODEs bigger than a word, because we might not be able
5063          to reference a two-register group starting with an arbitrary register
5064          (and currently gen_lowpart might crash for a SUBREG).  */
5065
5066       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5067         return x;
5068
5069       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5070       /* If the inner object has VOIDmode (the only way this can happen
5071          is if it is a ASM_OPERANDS), we can't do anything since we don't
5072          know how much masking to do.  */
5073       if (len == 0)
5074         return x;
5075
5076       break;
5077
5078     case ZERO_EXTRACT:
5079       unsignedp = 1;
5080     case SIGN_EXTRACT:
5081       /* If the operand is a CLOBBER, just return it.  */
5082       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5083         return XEXP (x, 0);
5084
5085       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5086           || GET_CODE (XEXP (x, 2)) != CONST_INT
5087           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5088         return x;
5089
5090       len = INTVAL (XEXP (x, 1));
5091       pos = INTVAL (XEXP (x, 2));
5092
5093       /* If this goes outside the object being extracted, replace the object
5094          with a (use (mem ...)) construct that only combine understands
5095          and is used only for this purpose.  */
5096       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5097         SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5098
5099       if (BITS_BIG_ENDIAN)
5100         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5101
5102       break;
5103
5104     default:
5105       return x;
5106     }
5107
5108   /* We can optimize some special cases of ZERO_EXTEND.  */
5109   if (GET_CODE (x) == ZERO_EXTEND)
5110     {
5111       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5112          know that the last value didn't have any inappropriate bits
5113          set.  */
5114       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5115           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5116           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5117           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5118               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5119         return XEXP (XEXP (x, 0), 0);
5120
5121       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5122       if (GET_CODE (XEXP (x, 0)) == SUBREG
5123           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5124           && subreg_lowpart_p (XEXP (x, 0))
5125           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5126           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5127               & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5128         return SUBREG_REG (XEXP (x, 0));
5129
5130       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5131          is a comparison and STORE_FLAG_VALUE permits.  This is like
5132          the first case, but it works even when GET_MODE (x) is larger
5133          than HOST_WIDE_INT.  */
5134       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5135           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5136           && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5137           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5138               <= HOST_BITS_PER_WIDE_INT)
5139           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5140               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5141         return XEXP (XEXP (x, 0), 0);
5142
5143       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5144       if (GET_CODE (XEXP (x, 0)) == SUBREG
5145           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5146           && subreg_lowpart_p (XEXP (x, 0))
5147           && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5148           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5149               <= HOST_BITS_PER_WIDE_INT)
5150           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5151               & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5152         return SUBREG_REG (XEXP (x, 0));
5153
5154       /* If sign extension is cheaper than zero extension, then use it
5155          if we know that no extraneous bits are set, and that the high
5156          bit is not set.  */
5157       if (flag_expensive_optimizations
5158           && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5159                && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5160                     & ~ (((unsigned HOST_WIDE_INT)
5161                           GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5162                          >> 1))
5163                    == 0))
5164               || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5165                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5166                       <= HOST_BITS_PER_WIDE_INT)
5167                   && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5168                        & ~ (((unsigned HOST_WIDE_INT)
5169                              GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5170                             >> 1))
5171                       == 0))))
5172         {
5173           rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5174
5175           if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5176             return expand_compound_operation (temp);
5177         }
5178     }
5179
5180   /* If we reach here, we want to return a pair of shifts.  The inner
5181      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5182      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5183      logical depending on the value of UNSIGNEDP.
5184
5185      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5186      converted into an AND of a shift.
5187
5188      We must check for the case where the left shift would have a negative
5189      count.  This can happen in a case like (x >> 31) & 255 on machines
5190      that can't shift by a constant.  On those machines, we would first
5191      combine the shift with the AND to produce a variable-position
5192      extraction.  Then the constant of 31 would be substituted in to produce
5193      a such a position.  */
5194
5195   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5196   if (modewidth >= pos - len)
5197     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5198                                 GET_MODE (x),
5199                                 simplify_shift_const (NULL_RTX, ASHIFT,
5200                                                       GET_MODE (x),
5201                                                       XEXP (x, 0),
5202                                                       modewidth - pos - len),
5203                                 modewidth - len);
5204
5205   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5206     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5207                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5208                                                         GET_MODE (x),
5209                                                         XEXP (x, 0), pos),
5210                                   ((HOST_WIDE_INT) 1 << len) - 1);
5211   else
5212     /* Any other cases we can't handle.  */
5213     return x;
5214
5215
5216   /* If we couldn't do this for some reason, return the original
5217      expression.  */
5218   if (GET_CODE (tem) == CLOBBER)
5219     return x;
5220
5221   return tem;
5222 }
5223 \f
5224 /* X is a SET which contains an assignment of one object into
5225    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5226    or certain SUBREGS). If possible, convert it into a series of
5227    logical operations.
5228
5229    We half-heartedly support variable positions, but do not at all
5230    support variable lengths.  */
5231
5232 static rtx
5233 expand_field_assignment (x)
5234      rtx x;
5235 {
5236   rtx inner;
5237   rtx pos;                      /* Always counts from low bit.  */
5238   int len;
5239   rtx mask;
5240   enum machine_mode compute_mode;
5241
5242   /* Loop until we find something we can't simplify.  */
5243   while (1)
5244     {
5245       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5246           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5247         {
5248           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5249           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5250           pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5251         }
5252       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5253                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5254         {
5255           inner = XEXP (SET_DEST (x), 0);
5256           len = INTVAL (XEXP (SET_DEST (x), 1));
5257           pos = XEXP (SET_DEST (x), 2);
5258
5259           /* If the position is constant and spans the width of INNER,
5260              surround INNER  with a USE to indicate this.  */
5261           if (GET_CODE (pos) == CONST_INT
5262               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5263             inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5264
5265           if (BITS_BIG_ENDIAN)
5266             {
5267               if (GET_CODE (pos) == CONST_INT)
5268                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5269                                - INTVAL (pos));
5270               else if (GET_CODE (pos) == MINUS
5271                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5272                        && (INTVAL (XEXP (pos, 1))
5273                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5274                 /* If position is ADJUST - X, new position is X.  */
5275                 pos = XEXP (pos, 0);
5276               else
5277                 pos = gen_binary (MINUS, GET_MODE (pos),
5278                                   GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5279                                            - len),
5280                                   pos);
5281             }
5282         }
5283
5284       /* A SUBREG between two modes that occupy the same numbers of words
5285          can be done by moving the SUBREG to the source.  */
5286       else if (GET_CODE (SET_DEST (x)) == SUBREG
5287                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5288                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5289                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5290                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5291         {
5292           x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5293                        gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5294                                                 SET_SRC (x)));
5295           continue;
5296         }
5297       else
5298         break;
5299
5300       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5301         inner = SUBREG_REG (inner);
5302
5303       compute_mode = GET_MODE (inner);
5304
5305       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5306       if (len < HOST_BITS_PER_WIDE_INT)
5307         mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5308       else
5309         break;
5310
5311       /* Now compute the equivalent expression.  Make a copy of INNER
5312          for the SET_DEST in case it is a MEM into which we will substitute;
5313          we don't want shared RTL in that case.  */
5314       x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5315                    gen_binary (IOR, compute_mode,
5316                                gen_binary (AND, compute_mode,
5317                                            gen_unary (NOT, compute_mode,
5318                                                       compute_mode,
5319                                                       gen_binary (ASHIFT,
5320                                                                   compute_mode,
5321                                                                   mask, pos)),
5322                                            inner),
5323                                gen_binary (ASHIFT, compute_mode,
5324                                            gen_binary (AND, compute_mode,
5325                                                        gen_lowpart_for_combine
5326                                                        (compute_mode,
5327                                                         SET_SRC (x)),
5328                                                        mask),
5329                                            pos)));
5330     }
5331
5332   return x;
5333 }
5334 \f
5335 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5336    it is an RTX that represents a variable starting position; otherwise,
5337    POS is the (constant) starting bit position (counted from the LSB).
5338
5339    INNER may be a USE.  This will occur when we started with a bitfield
5340    that went outside the boundary of the object in memory, which is
5341    allowed on most machines.  To isolate this case, we produce a USE
5342    whose mode is wide enough and surround the MEM with it.  The only
5343    code that understands the USE is this routine.  If it is not removed,
5344    it will cause the resulting insn not to match.
5345
5346    UNSIGNEDP is non-zero for an unsigned reference and zero for a
5347    signed reference.
5348
5349    IN_DEST is non-zero if this is a reference in the destination of a
5350    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If non-zero,
5351    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5352    be used.
5353
5354    IN_COMPARE is non-zero if we are in a COMPARE.  This means that a
5355    ZERO_EXTRACT should be built even for bits starting at bit 0.
5356
5357    MODE is the desired mode of the result (if IN_DEST == 0).
5358
5359    The result is an RTX for the extraction or NULL_RTX if the target
5360    can't handle it.  */
5361
5362 static rtx
5363 make_extraction (mode, inner, pos, pos_rtx, len,
5364                  unsignedp, in_dest, in_compare)
5365      enum machine_mode mode;
5366      rtx inner;
5367      int pos;
5368      rtx pos_rtx;
5369      int len;
5370      int unsignedp;
5371      int in_dest, in_compare;
5372 {
5373   /* This mode describes the size of the storage area
5374      to fetch the overall value from.  Within that, we
5375      ignore the POS lowest bits, etc.  */
5376   enum machine_mode is_mode = GET_MODE (inner);
5377   enum machine_mode inner_mode;
5378   enum machine_mode wanted_inner_mode = byte_mode;
5379   enum machine_mode wanted_inner_reg_mode = word_mode;
5380   enum machine_mode pos_mode = word_mode;
5381   enum machine_mode extraction_mode = word_mode;
5382   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5383   int spans_byte = 0;
5384   rtx new = 0;
5385   rtx orig_pos_rtx = pos_rtx;
5386   int orig_pos;
5387
5388   /* Get some information about INNER and get the innermost object.  */
5389   if (GET_CODE (inner) == USE)
5390     /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
5391     /* We don't need to adjust the position because we set up the USE
5392        to pretend that it was a full-word object.  */
5393     spans_byte = 1, inner = XEXP (inner, 0);
5394   else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5395     {
5396       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5397          consider just the QI as the memory to extract from.
5398          The subreg adds or removes high bits; its mode is
5399          irrelevant to the meaning of this extraction,
5400          since POS and LEN count from the lsb.  */
5401       if (GET_CODE (SUBREG_REG (inner)) == MEM)
5402         is_mode = GET_MODE (SUBREG_REG (inner));
5403       inner = SUBREG_REG (inner);
5404     }
5405
5406   inner_mode = GET_MODE (inner);
5407
5408   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5409     pos = INTVAL (pos_rtx), pos_rtx = 0;
5410
5411   /* See if this can be done without an extraction.  We never can if the
5412      width of the field is not the same as that of some integer mode. For
5413      registers, we can only avoid the extraction if the position is at the
5414      low-order bit and this is either not in the destination or we have the
5415      appropriate STRICT_LOW_PART operation available.
5416
5417      For MEM, we can avoid an extract if the field starts on an appropriate
5418      boundary and we can change the mode of the memory reference.  However,
5419      we cannot directly access the MEM if we have a USE and the underlying
5420      MEM is not TMODE.  This combination means that MEM was being used in a
5421      context where bits outside its mode were being referenced; that is only
5422      valid in bit-field insns.  */
5423
5424   if (tmode != BLKmode
5425       && ! (spans_byte && inner_mode != tmode)
5426       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5427            && GET_CODE (inner) != MEM
5428            && (! in_dest
5429                || (GET_CODE (inner) == REG
5430                    && (movstrict_optab->handlers[(int) tmode].insn_code
5431                        != CODE_FOR_nothing))))
5432           || (GET_CODE (inner) == MEM && pos_rtx == 0
5433               && (pos
5434                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5435                      : BITS_PER_UNIT)) == 0
5436               /* We can't do this if we are widening INNER_MODE (it
5437                  may not be aligned, for one thing).  */
5438               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5439               && (inner_mode == tmode
5440                   || (! mode_dependent_address_p (XEXP (inner, 0))
5441                       && ! MEM_VOLATILE_P (inner))))))
5442     {
5443       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5444          field.  If the original and current mode are the same, we need not
5445          adjust the offset.  Otherwise, we do if bytes big endian.
5446
5447          If INNER is not a MEM, get a piece consisting of just the field
5448          of interest (in this case POS % BITS_PER_WORD must be 0).  */
5449
5450       if (GET_CODE (inner) == MEM)
5451         {
5452           int offset;
5453           /* POS counts from lsb, but make OFFSET count in memory order.  */
5454           if (BYTES_BIG_ENDIAN)
5455             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5456           else
5457             offset = pos / BITS_PER_UNIT;
5458
5459           new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5460           RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5461           MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5462           MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5463         }
5464       else if (GET_CODE (inner) == REG)
5465         {
5466           /* We can't call gen_lowpart_for_combine here since we always want
5467              a SUBREG and it would sometimes return a new hard register.  */
5468           if (tmode != inner_mode)
5469             new = gen_rtx (SUBREG, tmode, inner,
5470                            (WORDS_BIG_ENDIAN
5471                             && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5472                             ? (((GET_MODE_SIZE (inner_mode)
5473                                  - GET_MODE_SIZE (tmode))
5474                                 / UNITS_PER_WORD)
5475                                - pos / BITS_PER_WORD)
5476                             : pos / BITS_PER_WORD));
5477           else
5478             new = inner;
5479         }
5480       else
5481         new = force_to_mode (inner, tmode,
5482                              len >= HOST_BITS_PER_WIDE_INT
5483                              ? GET_MODE_MASK (tmode)
5484                              : ((HOST_WIDE_INT) 1 << len) - 1,
5485                              NULL_RTX, 0);
5486
5487       /* If this extraction is going into the destination of a SET,
5488          make a STRICT_LOW_PART unless we made a MEM.  */
5489
5490       if (in_dest)
5491         return (GET_CODE (new) == MEM ? new
5492                 : (GET_CODE (new) != SUBREG
5493                    ? gen_rtx (CLOBBER, tmode, const0_rtx)
5494                    : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5495
5496       /* Otherwise, sign- or zero-extend unless we already are in the
5497          proper mode.  */
5498
5499       return (mode == tmode ? new
5500               : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5501                                  mode, new));
5502     }
5503
5504   /* Unless this is a COMPARE or we have a funny memory reference,
5505      don't do anything with zero-extending field extracts starting at
5506      the low-order bit since they are simple AND operations.  */
5507   if (pos_rtx == 0 && pos == 0 && ! in_dest
5508       && ! in_compare && ! spans_byte && unsignedp)
5509     return 0;
5510
5511   /* Unless we are allowed to span bytes, reject this if we would be
5512      spanning bytes or if the position is not a constant and the length
5513      is not 1.  In all other cases, we would only be going outside
5514      out object in cases when an original shift would have been
5515      undefined.  */
5516   if (! spans_byte
5517       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5518           || (pos_rtx != 0 && len != 1)))
5519     return 0;
5520
5521   /* Get the mode to use should INNER not be a MEM, the mode for the position,
5522      and the mode for the result.  */
5523 #ifdef HAVE_insv
5524   if (in_dest)
5525     {
5526       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5527       pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5528       extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5529     }
5530 #endif
5531
5532 #ifdef HAVE_extzv
5533   if (! in_dest && unsignedp)
5534     {
5535       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5536       pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5537       extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5538     }
5539 #endif
5540
5541 #ifdef HAVE_extv
5542   if (! in_dest && ! unsignedp)
5543     {
5544       wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5545       pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5546       extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5547     }
5548 #endif
5549
5550   /* Never narrow an object, since that might not be safe.  */
5551
5552   if (mode != VOIDmode
5553       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5554     extraction_mode = mode;
5555
5556   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5557       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5558     pos_mode = GET_MODE (pos_rtx);
5559
5560   /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5561      if we have to change the mode of memory and cannot, the desired mode is
5562      EXTRACTION_MODE.  */
5563   if (GET_CODE (inner) != MEM)
5564     wanted_inner_mode = wanted_inner_reg_mode;
5565   else if (inner_mode != wanted_inner_mode
5566            && (mode_dependent_address_p (XEXP (inner, 0))
5567                || MEM_VOLATILE_P (inner)))
5568     wanted_inner_mode = extraction_mode;
5569
5570   orig_pos = pos;
5571
5572   if (BITS_BIG_ENDIAN)
5573     {
5574       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5575          BITS_BIG_ENDIAN style.  If position is constant, compute new
5576          position.  Otherwise, build subtraction.
5577          Note that POS is relative to the mode of the original argument.
5578          If it's a MEM we need to recompute POS relative to that.
5579          However, if we're extracting from (or inserting into) a register,
5580          we want to recompute POS relative to wanted_inner_mode.  */
5581       int width = (GET_CODE (inner) == MEM
5582                    ? GET_MODE_BITSIZE (is_mode)
5583                    : GET_MODE_BITSIZE (wanted_inner_mode));
5584
5585       if (pos_rtx == 0)
5586         pos = width - len - pos;
5587       else
5588         pos_rtx
5589           = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5590                              GEN_INT (width - len), pos_rtx);
5591       /* POS may be less than 0 now, but we check for that below.
5592          Note that it can only be less than 0 if GET_CODE (inner) != MEM.  */
5593     }
5594
5595   /* If INNER has a wider mode, make it smaller.  If this is a constant
5596      extract, try to adjust the byte to point to the byte containing
5597      the value.  */
5598   if (wanted_inner_mode != VOIDmode
5599       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5600       && ((GET_CODE (inner) == MEM
5601            && (inner_mode == wanted_inner_mode
5602                || (! mode_dependent_address_p (XEXP (inner, 0))
5603                    && ! MEM_VOLATILE_P (inner))))))
5604     {
5605       int offset = 0;
5606
5607       /* The computations below will be correct if the machine is big
5608          endian in both bits and bytes or little endian in bits and bytes.
5609          If it is mixed, we must adjust.  */
5610
5611       /* If bytes are big endian and we had a paradoxical SUBREG, we must
5612          adjust OFFSET to compensate.  */
5613       if (BYTES_BIG_ENDIAN
5614           && ! spans_byte
5615           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5616         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5617
5618       /* If this is a constant position, we can move to the desired byte.  */
5619       if (pos_rtx == 0)
5620         {
5621           offset += pos / BITS_PER_UNIT;
5622           pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5623         }
5624
5625       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5626           && ! spans_byte
5627           && is_mode != wanted_inner_mode)
5628         offset = (GET_MODE_SIZE (is_mode)
5629                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
5630
5631       if (offset != 0 || inner_mode != wanted_inner_mode)
5632         {
5633           rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5634                                 plus_constant (XEXP (inner, 0), offset));
5635           RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5636           MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5637           MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5638           inner = newmem;
5639         }
5640     }
5641
5642   /* If INNER is not memory, we can always get it into the proper mode.  If we
5643      are changing its mode, POS must be a constant and smaller than the size
5644      of the new mode.  */
5645   else if (GET_CODE (inner) != MEM)
5646     {
5647       if (GET_MODE (inner) != wanted_inner_mode
5648           && (pos_rtx != 0
5649               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5650         return 0;
5651
5652       inner = force_to_mode (inner, wanted_inner_mode,
5653                              pos_rtx
5654                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5655                              ? GET_MODE_MASK (wanted_inner_mode)
5656                              : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5657                              NULL_RTX, 0);
5658     }
5659
5660   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
5661      have to zero extend.  Otherwise, we can just use a SUBREG.  */
5662   if (pos_rtx != 0
5663       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5664     pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5665   else if (pos_rtx != 0
5666            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5667     pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5668
5669   /* Make POS_RTX unless we already have it and it is correct.  If we don't
5670      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5671      be a CONST_INT.  */
5672   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5673     pos_rtx = orig_pos_rtx;
5674
5675   else if (pos_rtx == 0)
5676     pos_rtx = GEN_INT (pos);
5677
5678   /* Make the required operation.  See if we can use existing rtx.  */
5679   new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5680                          extraction_mode, inner, GEN_INT (len), pos_rtx);
5681   if (! in_dest)
5682     new = gen_lowpart_for_combine (mode, new);
5683
5684   return new;
5685 }
5686 \f
5687 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5688    with any other operations in X.  Return X without that shift if so.  */
5689
5690 static rtx
5691 extract_left_shift (x, count)
5692      rtx x;
5693      int count;
5694 {
5695   enum rtx_code code = GET_CODE (x);
5696   enum machine_mode mode = GET_MODE (x);
5697   rtx tem;
5698
5699   switch (code)
5700     {
5701     case ASHIFT:
5702       /* This is the shift itself.  If it is wide enough, we will return
5703          either the value being shifted if the shift count is equal to
5704          COUNT or a shift for the difference.  */
5705       if (GET_CODE (XEXP (x, 1)) == CONST_INT
5706           && INTVAL (XEXP (x, 1)) >= count)
5707         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5708                                      INTVAL (XEXP (x, 1)) - count);
5709       break;
5710
5711     case NEG:  case NOT:
5712       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5713         return gen_unary (code, mode, mode, tem);
5714
5715       break;
5716
5717     case PLUS:  case IOR:  case XOR:  case AND:
5718       /* If we can safely shift this constant and we find the inner shift,
5719          make a new operation.  */
5720       if (GET_CODE (XEXP (x,1)) == CONST_INT
5721           && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5722           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5723         return gen_binary (code, mode, tem,
5724                            GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5725
5726       break;
5727
5728     default:
5729       break;
5730     }
5731
5732   return 0;
5733 }
5734 \f
5735 /* Look at the expression rooted at X.  Look for expressions
5736    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5737    Form these expressions.
5738
5739    Return the new rtx, usually just X.
5740
5741    Also, for machines like the Vax that don't have logical shift insns,
5742    try to convert logical to arithmetic shift operations in cases where
5743    they are equivalent.  This undoes the canonicalizations to logical
5744    shifts done elsewhere.
5745
5746    We try, as much as possible, to re-use rtl expressions to save memory.
5747
5748    IN_CODE says what kind of expression we are processing.  Normally, it is
5749    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
5750    being kludges), it is MEM.  When processing the arguments of a comparison
5751    or a COMPARE against zero, it is COMPARE.  */
5752
5753 static rtx
5754 make_compound_operation (x, in_code)
5755      rtx x;
5756      enum rtx_code in_code;
5757 {
5758   enum rtx_code code = GET_CODE (x);
5759   enum machine_mode mode = GET_MODE (x);
5760   int mode_width = GET_MODE_BITSIZE (mode);
5761   rtx rhs, lhs;
5762   enum rtx_code next_code;
5763   int i;
5764   rtx new = 0;
5765   rtx tem;
5766   char *fmt;
5767
5768   /* Select the code to be used in recursive calls.  Once we are inside an
5769      address, we stay there.  If we have a comparison, set to COMPARE,
5770      but once inside, go back to our default of SET.  */
5771
5772   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5773                : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5774                   && XEXP (x, 1) == const0_rtx) ? COMPARE
5775                : in_code == COMPARE ? SET : in_code);
5776
5777   /* Process depending on the code of this operation.  If NEW is set
5778      non-zero, it will be returned.  */
5779
5780   switch (code)
5781     {
5782     case ASHIFT:
5783       /* Convert shifts by constants into multiplications if inside
5784          an address.  */
5785       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5786           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5787           && INTVAL (XEXP (x, 1)) >= 0)
5788         {
5789           new = make_compound_operation (XEXP (x, 0), next_code);
5790           new = gen_rtx_combine (MULT, mode, new,
5791                                  GEN_INT ((HOST_WIDE_INT) 1
5792                                           << INTVAL (XEXP (x, 1))));
5793         }
5794       break;
5795
5796     case AND:
5797       /* If the second operand is not a constant, we can't do anything
5798          with it.  */
5799       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5800         break;
5801
5802       /* If the constant is a power of two minus one and the first operand
5803          is a logical right shift, make an extraction.  */
5804       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5805           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5806         {
5807           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5808           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5809                                  0, in_code == COMPARE);
5810         }
5811
5812       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
5813       else if (GET_CODE (XEXP (x, 0)) == SUBREG
5814                && subreg_lowpart_p (XEXP (x, 0))
5815                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5816                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5817         {
5818           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5819                                          next_code);
5820           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5821                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5822                                  0, in_code == COMPARE);
5823         }
5824       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
5825       else if ((GET_CODE (XEXP (x, 0)) == XOR
5826                 || GET_CODE (XEXP (x, 0)) == IOR)
5827                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5828                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5829                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5830         {
5831           /* Apply the distributive law, and then try to make extractions.  */
5832           new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5833                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5834                                           XEXP (x, 1)),
5835                                  gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5836                                           XEXP (x, 1)));
5837           new = make_compound_operation (new, in_code);
5838         }
5839
5840       /* If we are have (and (rotate X C) M) and C is larger than the number
5841          of bits in M, this is an extraction.  */
5842
5843       else if (GET_CODE (XEXP (x, 0)) == ROTATE
5844                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5845                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5846                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5847         {
5848           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5849           new = make_extraction (mode, new,
5850                                  (GET_MODE_BITSIZE (mode)
5851                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
5852                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
5853         }
5854
5855       /* On machines without logical shifts, if the operand of the AND is
5856          a logical shift and our mask turns off all the propagated sign
5857          bits, we can replace the logical shift with an arithmetic shift.  */
5858       else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5859                && (lshr_optab->handlers[(int) mode].insn_code
5860                    == CODE_FOR_nothing)
5861                && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5862                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5863                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5864                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5865                && mode_width <= HOST_BITS_PER_WIDE_INT)
5866         {
5867           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5868
5869           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5870           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5871             SUBST (XEXP (x, 0),
5872                    gen_rtx_combine (ASHIFTRT, mode,
5873                                     make_compound_operation (XEXP (XEXP (x, 0), 0),
5874                                                              next_code),
5875                                     XEXP (XEXP (x, 0), 1)));
5876         }
5877
5878       /* If the constant is one less than a power of two, this might be
5879          representable by an extraction even if no shift is present.
5880          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5881          we are in a COMPARE.  */
5882       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5883         new = make_extraction (mode,
5884                                make_compound_operation (XEXP (x, 0),
5885                                                         next_code),
5886                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5887
5888       /* If we are in a comparison and this is an AND with a power of two,
5889          convert this into the appropriate bit extract.  */
5890       else if (in_code == COMPARE
5891                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5892         new = make_extraction (mode,
5893                                make_compound_operation (XEXP (x, 0),
5894                                                         next_code),
5895                                i, NULL_RTX, 1, 1, 0, 1);
5896
5897       break;
5898
5899     case LSHIFTRT:
5900       /* If the sign bit is known to be zero, replace this with an
5901          arithmetic shift.  */
5902       if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5903           && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5904           && mode_width <= HOST_BITS_PER_WIDE_INT
5905           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5906         {
5907           new = gen_rtx_combine (ASHIFTRT, mode,
5908                                  make_compound_operation (XEXP (x, 0),
5909                                                           next_code),
5910                                  XEXP (x, 1));
5911           break;
5912         }
5913
5914       /* ... fall through ...  */
5915
5916     case ASHIFTRT:
5917       lhs = XEXP (x, 0);
5918       rhs = XEXP (x, 1);
5919
5920       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5921          this is a SIGN_EXTRACT.  */
5922       if (GET_CODE (rhs) == CONST_INT
5923           && GET_CODE (lhs) == ASHIFT
5924           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5925           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5926         {
5927           new = make_compound_operation (XEXP (lhs, 0), next_code);
5928           new = make_extraction (mode, new,
5929                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5930                                  NULL_RTX, mode_width - INTVAL (rhs),
5931                                  code == LSHIFTRT, 0, in_code == COMPARE);
5932         }
5933
5934       /* See if we have operations between an ASHIFTRT and an ASHIFT.
5935          If so, try to merge the shifts into a SIGN_EXTEND.  We could
5936          also do this for some cases of SIGN_EXTRACT, but it doesn't
5937          seem worth the effort; the case checked for occurs on Alpha.  */
5938
5939       if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5940           && ! (GET_CODE (lhs) == SUBREG
5941                 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5942           && GET_CODE (rhs) == CONST_INT
5943           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5944           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5945         new = make_extraction (mode, make_compound_operation (new, next_code),
5946                                0, NULL_RTX, mode_width - INTVAL (rhs),
5947                                code == LSHIFTRT, 0, in_code == COMPARE);
5948
5949       break;
5950
5951     case SUBREG:
5952       /* Call ourselves recursively on the inner expression.  If we are
5953          narrowing the object and it has a different RTL code from
5954          what it originally did, do this SUBREG as a force_to_mode.  */
5955
5956       tem = make_compound_operation (SUBREG_REG (x), in_code);
5957       if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5958           && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5959           && subreg_lowpart_p (x))
5960         {
5961           rtx newer = force_to_mode (tem, mode,
5962                                      GET_MODE_MASK (mode), NULL_RTX, 0);
5963
5964           /* If we have something other than a SUBREG, we might have
5965              done an expansion, so rerun outselves.  */
5966           if (GET_CODE (newer) != SUBREG)
5967             newer = make_compound_operation (newer, in_code);
5968
5969           return newer;
5970         }
5971       break;
5972
5973     default:
5974       break;
5975     }
5976
5977   if (new)
5978     {
5979       x = gen_lowpart_for_combine (mode, new);
5980       code = GET_CODE (x);
5981     }
5982
5983   /* Now recursively process each operand of this operation.  */
5984   fmt = GET_RTX_FORMAT (code);
5985   for (i = 0; i < GET_RTX_LENGTH (code); i++)
5986     if (fmt[i] == 'e')
5987       {
5988         new = make_compound_operation (XEXP (x, i), next_code);
5989         SUBST (XEXP (x, i), new);
5990       }
5991
5992   return x;
5993 }
5994 \f
5995 /* Given M see if it is a value that would select a field of bits
5996     within an item, but not the entire word.  Return -1 if not.
5997     Otherwise, return the starting position of the field, where 0 is the
5998     low-order bit.
5999
6000    *PLEN is set to the length of the field.  */
6001
6002 static int
6003 get_pos_from_mask (m, plen)
6004      unsigned HOST_WIDE_INT m;
6005      int *plen;
6006 {
6007   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6008   int pos = exact_log2 (m & - m);
6009
6010   if (pos < 0)
6011     return -1;
6012
6013   /* Now shift off the low-order zero bits and see if we have a power of
6014      two minus 1.  */
6015   *plen = exact_log2 ((m >> pos) + 1);
6016
6017   if (*plen <= 0)
6018     return -1;
6019
6020   return pos;
6021 }
6022 \f
6023 /* See if X can be simplified knowing that we will only refer to it in
6024    MODE and will only refer to those bits that are nonzero in MASK.
6025    If other bits are being computed or if masking operations are done
6026    that select a superset of the bits in MASK, they can sometimes be
6027    ignored.
6028
6029    Return a possibly simplified expression, but always convert X to
6030    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6031
6032    Also, if REG is non-zero and X is a register equal in value to REG,
6033    replace X with REG.
6034
6035    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6036    are all off in X.  This is used when X will be complemented, by either
6037    NOT, NEG, or XOR.  */
6038
6039 static rtx
6040 force_to_mode (x, mode, mask, reg, just_select)
6041      rtx x;
6042      enum machine_mode mode;
6043      unsigned HOST_WIDE_INT mask;
6044      rtx reg;
6045      int just_select;
6046 {
6047   enum rtx_code code = GET_CODE (x);
6048   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6049   enum machine_mode op_mode;
6050   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6051   rtx op0, op1, temp;
6052
6053   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6054      code below will do the wrong thing since the mode of such an
6055      expression is VOIDmode.
6056
6057      Also do nothing if X is a CLOBBER; this can happen if X was
6058      the return value from a call to gen_lowpart_for_combine.  */
6059   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6060     return x;
6061
6062   /* We want to perform the operation is its present mode unless we know
6063      that the operation is valid in MODE, in which case we do the operation
6064      in MODE.  */
6065   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6066               && code_to_optab[(int) code] != 0
6067               && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6068                   != CODE_FOR_nothing))
6069              ? mode : GET_MODE (x));
6070
6071   /* It is not valid to do a right-shift in a narrower mode
6072      than the one it came in with.  */
6073   if ((code == LSHIFTRT || code == ASHIFTRT)
6074       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6075     op_mode = GET_MODE (x);
6076
6077   /* Truncate MASK to fit OP_MODE.  */
6078   if (op_mode)
6079     mask &= GET_MODE_MASK (op_mode);
6080
6081   /* When we have an arithmetic operation, or a shift whose count we
6082      do not know, we need to assume that all bit the up to the highest-order
6083      bit in MASK will be needed.  This is how we form such a mask.  */
6084   if (op_mode)
6085     fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6086                    ? GET_MODE_MASK (op_mode)
6087                    : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6088   else
6089     fuller_mask = ~ (HOST_WIDE_INT) 0;
6090
6091   /* Determine what bits of X are guaranteed to be (non)zero.  */
6092   nonzero = nonzero_bits (x, mode);
6093
6094   /* If none of the bits in X are needed, return a zero.  */
6095   if (! just_select && (nonzero & mask) == 0)
6096     return const0_rtx;
6097
6098   /* If X is a CONST_INT, return a new one.  Do this here since the
6099      test below will fail.  */
6100   if (GET_CODE (x) == CONST_INT)
6101     {
6102       HOST_WIDE_INT cval = INTVAL (x) & mask;
6103       int width = GET_MODE_BITSIZE (mode);
6104
6105       /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6106          number, sign extend it.  */
6107       if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6108           && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6109         cval |= (HOST_WIDE_INT) -1 << width;
6110
6111       return GEN_INT (cval);
6112     }
6113
6114   /* If X is narrower than MODE and we want all the bits in X's mode, just
6115      get X in the proper mode.  */
6116   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6117       && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6118     return gen_lowpart_for_combine (mode, x);
6119
6120   /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6121      MASK are already known to be zero in X, we need not do anything.  */
6122   if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6123     return x;
6124
6125   switch (code)
6126     {
6127     case CLOBBER:
6128       /* If X is a (clobber (const_int)), return it since we know we are
6129          generating something that won't match.  */
6130       return x;
6131
6132     case USE:
6133       /* X is a (use (mem ..)) that was made from a bit-field extraction that
6134          spanned the boundary of the MEM.  If we are now masking so it is
6135          within that boundary, we don't need the USE any more.  */
6136       if (! BITS_BIG_ENDIAN
6137           && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6138         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139       break;
6140
6141     case SIGN_EXTEND:
6142     case ZERO_EXTEND:
6143     case ZERO_EXTRACT:
6144     case SIGN_EXTRACT:
6145       x = expand_compound_operation (x);
6146       if (GET_CODE (x) != code)
6147         return force_to_mode (x, mode, mask, reg, next_select);
6148       break;
6149
6150     case REG:
6151       if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6152                        || rtx_equal_p (reg, get_last_value (x))))
6153         x = reg;
6154       break;
6155
6156     case SUBREG:
6157       if (subreg_lowpart_p (x)
6158           /* We can ignore the effect of this SUBREG if it narrows the mode or
6159              if the constant masks to zero all the bits the mode doesn't
6160              have.  */
6161           && ((GET_MODE_SIZE (GET_MODE (x))
6162                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6163               || (0 == (mask
6164                         & GET_MODE_MASK (GET_MODE (x))
6165                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6166         return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6167       break;
6168
6169     case AND:
6170       /* If this is an AND with a constant, convert it into an AND
6171          whose constant is the AND of that constant with MASK.  If it
6172          remains an AND of MASK, delete it since it is redundant.  */
6173
6174       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6175         {
6176           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6177                                       mask & INTVAL (XEXP (x, 1)));
6178
6179           /* If X is still an AND, see if it is an AND with a mask that
6180              is just some low-order bits.  If so, and it is MASK, we don't
6181              need it.  */
6182
6183           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6184               && INTVAL (XEXP (x, 1)) == mask)
6185             x = XEXP (x, 0);
6186
6187           /* If it remains an AND, try making another AND with the bits
6188              in the mode mask that aren't in MASK turned on.  If the
6189              constant in the AND is wide enough, this might make a
6190              cheaper constant.  */
6191
6192           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6193               && GET_MODE_MASK (GET_MODE (x)) != mask
6194               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6195             {
6196               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6197                                     | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6198               int width = GET_MODE_BITSIZE (GET_MODE (x));
6199               rtx y;
6200
6201               /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6202                  number, sign extend it.  */
6203               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6204                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6205                 cval |= (HOST_WIDE_INT) -1 << width;
6206
6207               y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6208               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6209                 x = y;
6210             }
6211
6212           break;
6213         }
6214
6215       goto binop;
6216
6217     case PLUS:
6218       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6219          low-order bits (as in an alignment operation) and FOO is already
6220          aligned to that boundary, mask C1 to that boundary as well.
6221          This may eliminate that PLUS and, later, the AND.  */
6222
6223       {
6224         int width = GET_MODE_BITSIZE (mode);
6225         unsigned HOST_WIDE_INT smask = mask;
6226
6227         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6228            number, sign extend it.  */
6229
6230         if (width < HOST_BITS_PER_WIDE_INT
6231             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6232           smask |= (HOST_WIDE_INT) -1 << width;
6233
6234         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6235             && exact_log2 (- smask) >= 0
6236             && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6237             && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6238           return force_to_mode (plus_constant (XEXP (x, 0),
6239                                                INTVAL (XEXP (x, 1)) & mask),
6240                                 mode, mask, reg, next_select);
6241       }
6242
6243       /* ... fall through ...  */
6244
6245     case MINUS:
6246     case MULT:
6247       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6248          most significant bit in MASK since carries from those bits will
6249          affect the bits we are interested in.  */
6250       mask = fuller_mask;
6251       goto binop;
6252
6253     case IOR:
6254     case XOR:
6255       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6256          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6257          operation which may be a bitfield extraction.  Ensure that the
6258          constant we form is not wider than the mode of X.  */
6259
6260       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6261           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6262           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6263           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6264           && GET_CODE (XEXP (x, 1)) == CONST_INT
6265           && ((INTVAL (XEXP (XEXP (x, 0), 1))
6266                + floor_log2 (INTVAL (XEXP (x, 1))))
6267               < GET_MODE_BITSIZE (GET_MODE (x)))
6268           && (INTVAL (XEXP (x, 1))
6269               & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6270         {
6271           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6272                               << INTVAL (XEXP (XEXP (x, 0), 1)));
6273           temp = gen_binary (GET_CODE (x), GET_MODE (x),
6274                              XEXP (XEXP (x, 0), 0), temp);
6275           x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6276                           XEXP (XEXP (x, 0), 1));
6277           return force_to_mode (x, mode, mask, reg, next_select);
6278         }
6279
6280     binop:
6281       /* For most binary operations, just propagate into the operation and
6282          change the mode if we have an operation of that mode.   */
6283
6284       op0 = gen_lowpart_for_combine (op_mode,
6285                                      force_to_mode (XEXP (x, 0), mode, mask,
6286                                                     reg, next_select));
6287       op1 = gen_lowpart_for_combine (op_mode,
6288                                      force_to_mode (XEXP (x, 1), mode, mask,
6289                                                     reg, next_select));
6290
6291       /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6292          MASK since OP1 might have been sign-extended but we never want
6293          to turn on extra bits, since combine might have previously relied
6294          on them being off.  */
6295       if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6296           && (INTVAL (op1) & mask) != 0)
6297         op1 = GEN_INT (INTVAL (op1) & mask);
6298
6299       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6300         x = gen_binary (code, op_mode, op0, op1);
6301       break;
6302
6303     case ASHIFT:
6304       /* For left shifts, do the same, but just for the first operand.
6305          However, we cannot do anything with shifts where we cannot
6306          guarantee that the counts are smaller than the size of the mode
6307          because such a count will have a different meaning in a
6308          wider mode.  */
6309
6310       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6311              && INTVAL (XEXP (x, 1)) >= 0
6312              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6313           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6314                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6315                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6316         break;
6317
6318       /* If the shift count is a constant and we can do arithmetic in
6319          the mode of the shift, refine which bits we need.  Otherwise, use the
6320          conservative form of the mask.  */
6321       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6322           && INTVAL (XEXP (x, 1)) >= 0
6323           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6324           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6325         mask >>= INTVAL (XEXP (x, 1));
6326       else
6327         mask = fuller_mask;
6328
6329       op0 = gen_lowpart_for_combine (op_mode,
6330                                      force_to_mode (XEXP (x, 0), op_mode,
6331                                                     mask, reg, next_select));
6332
6333       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6334         x =  gen_binary (code, op_mode, op0, XEXP (x, 1));
6335       break;
6336
6337     case LSHIFTRT:
6338       /* Here we can only do something if the shift count is a constant,
6339          this shift constant is valid for the host, and we can do arithmetic
6340          in OP_MODE.  */
6341
6342       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6343           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6344           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6345         {
6346           rtx inner = XEXP (x, 0);
6347
6348           /* Select the mask of the bits we need for the shift operand.  */
6349           mask <<= INTVAL (XEXP (x, 1));
6350
6351           /* We can only change the mode of the shift if we can do arithmetic
6352              in the mode of the shift and MASK is no wider than the width of
6353              OP_MODE.  */
6354           if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6355               || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6356             op_mode = GET_MODE (x);
6357
6358           inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6359
6360           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6361             x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6362         }
6363
6364       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6365          shift and AND produces only copies of the sign bit (C2 is one less
6366          than a power of two), we can do this with just a shift.  */
6367
6368       if (GET_CODE (x) == LSHIFTRT
6369           && GET_CODE (XEXP (x, 1)) == CONST_INT
6370           && ((INTVAL (XEXP (x, 1))
6371                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6372               >= GET_MODE_BITSIZE (GET_MODE (x)))
6373           && exact_log2 (mask + 1) >= 0
6374           && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6375               >= exact_log2 (mask + 1)))
6376         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6377                         GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6378                                  - exact_log2 (mask + 1)));
6379       break;
6380
6381     case ASHIFTRT:
6382       /* If we are just looking for the sign bit, we don't need this shift at
6383          all, even if it has a variable count.  */
6384       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6385           && (mask == ((HOST_WIDE_INT) 1
6386                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6387         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6388
6389       /* If this is a shift by a constant, get a mask that contains those bits
6390          that are not copies of the sign bit.  We then have two cases:  If
6391          MASK only includes those bits, this can be a logical shift, which may
6392          allow simplifications.  If MASK is a single-bit field not within
6393          those bits, we are requesting a copy of the sign bit and hence can
6394          shift the sign bit to the appropriate location.  */
6395
6396       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6397           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6398         {
6399           int i = -1;
6400
6401           /* If the considered data is wider then HOST_WIDE_INT, we can't
6402              represent a mask for all its bits in a single scalar.
6403              But we only care about the lower bits, so calculate these.  */
6404
6405           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6406             {
6407               nonzero = ~ (HOST_WIDE_INT) 0;
6408
6409               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6410                  is the number of bits a full-width mask would have set.
6411                  We need only shift if these are fewer than nonzero can
6412                  hold.  If not, we must keep all bits set in nonzero.  */
6413
6414               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6415                   < HOST_BITS_PER_WIDE_INT)
6416                 nonzero >>= INTVAL (XEXP (x, 1))
6417                             + HOST_BITS_PER_WIDE_INT
6418                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
6419             }
6420           else
6421             {
6422               nonzero = GET_MODE_MASK (GET_MODE (x));
6423               nonzero >>= INTVAL (XEXP (x, 1));
6424             }
6425
6426           if ((mask & ~ nonzero) == 0
6427               || (i = exact_log2 (mask)) >= 0)
6428             {
6429               x = simplify_shift_const
6430                 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6431                  i < 0 ? INTVAL (XEXP (x, 1))
6432                  : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6433
6434               if (GET_CODE (x) != ASHIFTRT)
6435                 return force_to_mode (x, mode, mask, reg, next_select);
6436             }
6437         }
6438
6439       /* If MASK is 1, convert this to a LSHIFTRT.  This can be done
6440          even if the shift count isn't a constant.  */
6441       if (mask == 1)
6442         x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6443
6444       /* If this is a sign-extension operation that just affects bits
6445          we don't care about, remove it.  Be sure the call above returned
6446          something that is still a shift.  */
6447
6448       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6449           && GET_CODE (XEXP (x, 1)) == CONST_INT
6450           && INTVAL (XEXP (x, 1)) >= 0
6451           && (INTVAL (XEXP (x, 1))
6452               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6453           && GET_CODE (XEXP (x, 0)) == ASHIFT
6454           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6455           && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6456         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6457                               reg, next_select);
6458
6459       break;
6460
6461     case ROTATE:
6462     case ROTATERT:
6463       /* If the shift count is constant and we can do computations
6464          in the mode of X, compute where the bits we care about are.
6465          Otherwise, we can't do anything.  Don't change the mode of
6466          the shift or propagate MODE into the shift, though.  */
6467       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6468           && INTVAL (XEXP (x, 1)) >= 0)
6469         {
6470           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6471                                             GET_MODE (x), GEN_INT (mask),
6472                                             XEXP (x, 1));
6473           if (temp && GET_CODE(temp) == CONST_INT)
6474             SUBST (XEXP (x, 0),
6475                    force_to_mode (XEXP (x, 0), GET_MODE (x),
6476                                   INTVAL (temp), reg, next_select));
6477         }
6478       break;
6479
6480     case NEG:
6481       /* If we just want the low-order bit, the NEG isn't needed since it
6482          won't change the low-order bit.    */
6483       if (mask == 1)
6484         return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6485
6486       /* We need any bits less significant than the most significant bit in
6487          MASK since carries from those bits will affect the bits we are
6488          interested in.  */
6489       mask = fuller_mask;
6490       goto unop;
6491
6492     case NOT:
6493       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6494          same as the XOR case above.  Ensure that the constant we form is not
6495          wider than the mode of X.  */
6496
6497       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6498           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6499           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6500           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6501               < GET_MODE_BITSIZE (GET_MODE (x)))
6502           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6503         {
6504           temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6505           temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6506           x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6507
6508           return force_to_mode (x, mode, mask, reg, next_select);
6509         }
6510
6511       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6512          use the full mask inside the NOT.  */
6513       mask = fuller_mask;
6514
6515     unop:
6516       op0 = gen_lowpart_for_combine (op_mode,
6517                                      force_to_mode (XEXP (x, 0), mode, mask,
6518                                                     reg, next_select));
6519       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6520         x = gen_unary (code, op_mode, op_mode, op0);
6521       break;
6522
6523     case NE:
6524       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6525          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6526          which is equal to STORE_FLAG_VALUE.  */
6527       if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6528           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6529           && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6530         return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6531
6532       break;
6533
6534     case IF_THEN_ELSE:
6535       /* We have no way of knowing if the IF_THEN_ELSE can itself be
6536          written in a narrower mode.  We play it safe and do not do so.  */
6537
6538       SUBST (XEXP (x, 1),
6539              gen_lowpart_for_combine (GET_MODE (x),
6540                                       force_to_mode (XEXP (x, 1), mode,
6541                                                      mask, reg, next_select)));
6542       SUBST (XEXP (x, 2),
6543              gen_lowpart_for_combine (GET_MODE (x),
6544                                       force_to_mode (XEXP (x, 2), mode,
6545                                                      mask, reg,next_select)));
6546       break;
6547
6548     default:
6549       break;
6550     }
6551
6552   /* Ensure we return a value of the proper mode.  */
6553   return gen_lowpart_for_combine (mode, x);
6554 }
6555 \f
6556 /* Return nonzero if X is an expression that has one of two values depending on
6557    whether some other value is zero or nonzero.  In that case, we return the
6558    value that is being tested, *PTRUE is set to the value if the rtx being
6559    returned has a nonzero value, and *PFALSE is set to the other alternative.
6560
6561    If we return zero, we set *PTRUE and *PFALSE to X.  */
6562
6563 static rtx
6564 if_then_else_cond (x, ptrue, pfalse)
6565      rtx x;
6566      rtx *ptrue, *pfalse;
6567 {
6568   enum machine_mode mode = GET_MODE (x);
6569   enum rtx_code code = GET_CODE (x);
6570   int size = GET_MODE_BITSIZE (mode);
6571   rtx cond0, cond1, true0, true1, false0, false1;
6572   unsigned HOST_WIDE_INT nz;
6573
6574   /* If this is a unary operation whose operand has one of two values, apply
6575      our opcode to compute those values.  */
6576   if (GET_RTX_CLASS (code) == '1'
6577       && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6578     {
6579       *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6580       *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6581       return cond0;
6582     }
6583
6584   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6585      make can't possibly match and would suppress other optimizations.  */
6586   else if (code == COMPARE)
6587     ;
6588
6589   /* If this is a binary operation, see if either side has only one of two
6590      values.  If either one does or if both do and they are conditional on
6591      the same value, compute the new true and false values.  */
6592   else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6593            || GET_RTX_CLASS (code) == '<')
6594     {
6595       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6596       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6597
6598       if ((cond0 != 0 || cond1 != 0)
6599           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6600         {
6601           /* If if_then_else_cond returned zero, then true/false are the
6602              same rtl.  We must copy one of them to prevent invalid rtl
6603              sharing.  */
6604           if (cond0 == 0)
6605             true0 = copy_rtx (true0);
6606           else if (cond1 == 0)
6607             true1 = copy_rtx (true1);
6608
6609           *ptrue = gen_binary (code, mode, true0, true1);
6610           *pfalse = gen_binary (code, mode, false0, false1);
6611           return cond0 ? cond0 : cond1;
6612         }
6613
6614       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6615          operands is zero when the other is non-zero, and vice-versa,
6616          and STORE_FLAG_VALUE is 1 or -1.  */
6617
6618       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6619           && (code == PLUS || code == IOR || code == XOR || code == MINUS
6620            || code == UMAX)
6621           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6622         {
6623           rtx op0 = XEXP (XEXP (x, 0), 1);
6624           rtx op1 = XEXP (XEXP (x, 1), 1);
6625
6626           cond0 = XEXP (XEXP (x, 0), 0);
6627           cond1 = XEXP (XEXP (x, 1), 0);
6628
6629           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6630               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6631               && reversible_comparison_p (cond1)
6632               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6633                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6634                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6635                   || ((swap_condition (GET_CODE (cond0))
6636                        == reverse_condition (GET_CODE (cond1)))
6637                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6638                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6639               && ! side_effects_p (x))
6640             {
6641               *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6642               *pfalse = gen_binary (MULT, mode,
6643                                     (code == MINUS
6644                                      ? gen_unary (NEG, mode, mode, op1) : op1),
6645                                     const_true_rtx);
6646               return cond0;
6647             }
6648         }
6649
6650       /* Similarly for MULT, AND and UMIN, execpt that for these the result
6651          is always zero.  */
6652       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6653           && (code == MULT || code == AND || code == UMIN)
6654           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6655         {
6656           cond0 = XEXP (XEXP (x, 0), 0);
6657           cond1 = XEXP (XEXP (x, 1), 0);
6658
6659           if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6660               && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6661               && reversible_comparison_p (cond1)
6662               && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6663                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6664                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6665                   || ((swap_condition (GET_CODE (cond0))
6666                        == reverse_condition (GET_CODE (cond1)))
6667                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6668                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6669               && ! side_effects_p (x))
6670             {
6671               *ptrue = *pfalse = const0_rtx;
6672               return cond0;
6673             }
6674         }
6675     }
6676
6677   else if (code == IF_THEN_ELSE)
6678     {
6679       /* If we have IF_THEN_ELSE already, extract the condition and
6680          canonicalize it if it is NE or EQ.  */
6681       cond0 = XEXP (x, 0);
6682       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6683       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6684         return XEXP (cond0, 0);
6685       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6686         {
6687           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6688           return XEXP (cond0, 0);
6689         }
6690       else
6691         return cond0;
6692     }
6693
6694   /* If X is a normal SUBREG with both inner and outer modes integral,
6695      we can narrow both the true and false values of the inner expression,
6696      if there is a condition.  */
6697   else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6698            && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6699            && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6700            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6701                                                &true0, &false0)))
6702     {
6703       *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6704       *pfalse
6705         = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6706
6707       return cond0;
6708     }
6709
6710   /* If X is a constant, this isn't special and will cause confusions
6711      if we treat it as such.  Likewise if it is equivalent to a constant.  */
6712   else if (CONSTANT_P (x)
6713            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6714     ;
6715
6716   /* If X is known to be either 0 or -1, those are the true and
6717      false values when testing X.  */
6718   else if (num_sign_bit_copies (x, mode) == size)
6719     {
6720       *ptrue = constm1_rtx, *pfalse = const0_rtx;
6721       return x;
6722     }
6723
6724   /* Likewise for 0 or a single bit.  */
6725   else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6726     {
6727       *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6728       return x;
6729     }
6730
6731   /* Otherwise fail; show no condition with true and false values the same.  */
6732   *ptrue = *pfalse = x;
6733   return 0;
6734 }
6735 \f
6736 /* Return the value of expression X given the fact that condition COND
6737    is known to be true when applied to REG as its first operand and VAL
6738    as its second.  X is known to not be shared and so can be modified in
6739    place.
6740
6741    We only handle the simplest cases, and specifically those cases that
6742    arise with IF_THEN_ELSE expressions.  */
6743
6744 static rtx
6745 known_cond (x, cond, reg, val)
6746      rtx x;
6747      enum rtx_code cond;
6748      rtx reg, val;
6749 {
6750   enum rtx_code code = GET_CODE (x);
6751   rtx temp;
6752   char *fmt;
6753   int i, j;
6754
6755   if (side_effects_p (x))
6756     return x;
6757
6758   if (cond == EQ && rtx_equal_p (x, reg))
6759     return val;
6760
6761   /* If X is (abs REG) and we know something about REG's relationship
6762      with zero, we may be able to simplify this.  */
6763
6764   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6765     switch (cond)
6766       {
6767       case GE:  case GT:  case EQ:
6768         return XEXP (x, 0);
6769       case LT:  case LE:
6770         return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6771                           XEXP (x, 0));
6772       default:
6773         break;
6774       }
6775
6776   /* The only other cases we handle are MIN, MAX, and comparisons if the
6777      operands are the same as REG and VAL.  */
6778
6779   else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6780     {
6781       if (rtx_equal_p (XEXP (x, 0), val))
6782         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6783
6784       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6785         {
6786           if (GET_RTX_CLASS (code) == '<')
6787             return (comparison_dominates_p (cond, code) ? const_true_rtx
6788                     : (comparison_dominates_p (cond,
6789                                                reverse_condition (code))
6790                        ? const0_rtx : x));
6791
6792           else if (code == SMAX || code == SMIN
6793                    || code == UMIN || code == UMAX)
6794             {
6795               int unsignedp = (code == UMIN || code == UMAX);
6796
6797               if (code == SMAX || code == UMAX)
6798                 cond = reverse_condition (cond);
6799
6800               switch (cond)
6801                 {
6802                 case GE:   case GT:
6803                   return unsignedp ? x : XEXP (x, 1);
6804                 case LE:   case LT:
6805                   return unsignedp ? x : XEXP (x, 0);
6806                 case GEU:  case GTU:
6807                   return unsignedp ? XEXP (x, 1) : x;
6808                 case LEU:  case LTU:
6809                   return unsignedp ? XEXP (x, 0) : x;
6810                 default:
6811                   break;
6812                 }
6813             }
6814         }
6815     }
6816
6817   fmt = GET_RTX_FORMAT (code);
6818   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6819     {
6820       if (fmt[i] == 'e')
6821         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6822       else if (fmt[i] == 'E')
6823         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6824           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6825                                                 cond, reg, val));
6826     }
6827
6828   return x;
6829 }
6830 \f
6831 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6832    assignment as a field assignment.  */
6833
6834 static int
6835 rtx_equal_for_field_assignment_p (x, y)
6836      rtx x;
6837      rtx y;
6838 {
6839   rtx last_x, last_y;
6840
6841   if (x == y || rtx_equal_p (x, y))
6842     return 1;
6843
6844   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6845     return 0;
6846
6847   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6848      Note that all SUBREGs of MEM are paradoxical; otherwise they
6849      would have been rewritten.  */
6850   if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6851       && GET_CODE (SUBREG_REG (y)) == MEM
6852       && rtx_equal_p (SUBREG_REG (y),
6853                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6854     return 1;
6855
6856   if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6857       && GET_CODE (SUBREG_REG (x)) == MEM
6858       && rtx_equal_p (SUBREG_REG (x),
6859                       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6860     return 1;
6861
6862   last_x = get_last_value (x);
6863   last_y = get_last_value (y);
6864
6865   return ((last_x != 0
6866            && GET_CODE (last_x) != CLOBBER
6867            && rtx_equal_for_field_assignment_p (last_x, y))
6868           || (last_y != 0
6869               && GET_CODE (last_y) != CLOBBER
6870               && rtx_equal_for_field_assignment_p (x, last_y))
6871           || (last_x != 0 && last_y != 0
6872               && GET_CODE (last_x) != CLOBBER
6873               && GET_CODE (last_y) != CLOBBER
6874               && rtx_equal_for_field_assignment_p (last_x, last_y)));
6875 }
6876 \f
6877 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6878    Return that assignment if so.
6879
6880    We only handle the most common cases.  */
6881
6882 static rtx
6883 make_field_assignment (x)
6884      rtx x;
6885 {
6886   rtx dest = SET_DEST (x);
6887   rtx src = SET_SRC (x);
6888   rtx assign;
6889   rtx rhs, lhs;
6890   HOST_WIDE_INT c1;
6891   int pos, len;
6892   rtx other;
6893   enum machine_mode mode;
6894
6895   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6896      a clear of a one-bit field.  We will have changed it to
6897      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
6898      for a SUBREG.  */
6899
6900   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6901       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6902       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6903       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6904     {
6905       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6906                                 1, 1, 1, 0);
6907       if (assign != 0)
6908         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6909       return x;
6910     }
6911
6912   else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6913            && subreg_lowpart_p (XEXP (src, 0))
6914            && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6915                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6916            && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6917            && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6918            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6919     {
6920       assign = make_extraction (VOIDmode, dest, 0,
6921                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6922                                 1, 1, 1, 0);
6923       if (assign != 0)
6924         return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6925       return x;
6926     }
6927
6928   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6929      one-bit field.  */
6930   else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6931            && XEXP (XEXP (src, 0), 0) == const1_rtx
6932            && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6933     {
6934       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6935                                 1, 1, 1, 0);
6936       if (assign != 0)
6937         return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6938       return x;
6939     }
6940
6941   /* The other case we handle is assignments into a constant-position
6942      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
6943      a mask that has all one bits except for a group of zero bits and
6944      OTHER is known to have zeros where C1 has ones, this is such an
6945      assignment.  Compute the position and length from C1.  Shift OTHER
6946      to the appropriate position, force it to the required mode, and
6947      make the extraction.  Check for the AND in both operands.  */
6948
6949   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6950     return x;
6951
6952   rhs = expand_compound_operation (XEXP (src, 0));
6953   lhs = expand_compound_operation (XEXP (src, 1));
6954
6955   if (GET_CODE (rhs) == AND
6956       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6957       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6958     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6959   else if (GET_CODE (lhs) == AND
6960            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6961            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6962     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6963   else
6964     return x;
6965
6966   pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6967   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6968       || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6969           && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6970     return x;
6971
6972   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6973   if (assign == 0)
6974     return x;
6975
6976   /* The mode to use for the source is the mode of the assignment, or of
6977      what is inside a possible STRICT_LOW_PART.  */
6978   mode = (GET_CODE (assign) == STRICT_LOW_PART
6979           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6980
6981   /* Shift OTHER right POS places and make it the source, restricting it
6982      to the proper length and mode.  */
6983
6984   src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6985                                              GET_MODE (src), other, pos),
6986                        mode,
6987                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6988                        ? GET_MODE_MASK (mode)
6989                        : ((HOST_WIDE_INT) 1 << len) - 1,
6990                        dest, 0);
6991
6992   return gen_rtx_combine (SET, VOIDmode, assign, src);
6993 }
6994 \f
6995 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6996    if so.  */
6997
6998 static rtx
6999 apply_distributive_law (x)
7000      rtx x;
7001 {
7002   enum rtx_code code = GET_CODE (x);
7003   rtx lhs, rhs, other;
7004   rtx tem;
7005   enum rtx_code inner_code;
7006
7007   /* Distributivity is not true for floating point.
7008      It can change the value.  So don't do it.
7009      -- rms and moshier@world.std.com.  */
7010   if (FLOAT_MODE_P (GET_MODE (x)))
7011     return x;
7012
7013   /* The outer operation can only be one of the following:  */
7014   if (code != IOR && code != AND && code != XOR
7015       && code != PLUS && code != MINUS)
7016     return x;
7017
7018   lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7019
7020   /* If either operand is a primitive we can't do anything, so get out
7021      fast.  */
7022   if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7023       || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7024     return x;
7025
7026   lhs = expand_compound_operation (lhs);
7027   rhs = expand_compound_operation (rhs);
7028   inner_code = GET_CODE (lhs);
7029   if (inner_code != GET_CODE (rhs))
7030     return x;
7031
7032   /* See if the inner and outer operations distribute.  */
7033   switch (inner_code)
7034     {
7035     case LSHIFTRT:
7036     case ASHIFTRT:
7037     case AND:
7038     case IOR:
7039       /* These all distribute except over PLUS.  */
7040       if (code == PLUS || code == MINUS)
7041         return x;
7042       break;
7043
7044     case MULT:
7045       if (code != PLUS && code != MINUS)
7046         return x;
7047       break;
7048
7049     case ASHIFT:
7050       /* This is also a multiply, so it distributes over everything.  */
7051       break;
7052
7053     case SUBREG:
7054       /* Non-paradoxical SUBREGs distributes over all operations, provided
7055          the inner modes and word numbers are the same, this is an extraction
7056          of a low-order part, we don't convert an fp operation to int or
7057          vice versa, and we would not be converting a single-word
7058          operation into a multi-word operation.  The latter test is not
7059          required, but it prevents generating unneeded multi-word operations.
7060          Some of the previous tests are redundant given the latter test, but
7061          are retained because they are required for correctness.
7062
7063          We produce the result slightly differently in this case.  */
7064
7065       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7066           || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7067           || ! subreg_lowpart_p (lhs)
7068           || (GET_MODE_CLASS (GET_MODE (lhs))
7069               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7070           || (GET_MODE_SIZE (GET_MODE (lhs))
7071               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7072           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7073         return x;
7074
7075       tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7076                         SUBREG_REG (lhs), SUBREG_REG (rhs));
7077       return gen_lowpart_for_combine (GET_MODE (x), tem);
7078
7079     default:
7080       return x;
7081     }
7082
7083   /* Set LHS and RHS to the inner operands (A and B in the example
7084      above) and set OTHER to the common operand (C in the example).
7085      These is only one way to do this unless the inner operation is
7086      commutative.  */
7087   if (GET_RTX_CLASS (inner_code) == 'c'
7088       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7089     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7090   else if (GET_RTX_CLASS (inner_code) == 'c'
7091            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7092     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7093   else if (GET_RTX_CLASS (inner_code) == 'c'
7094            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7095     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7096   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7097     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7098   else
7099     return x;
7100
7101   /* Form the new inner operation, seeing if it simplifies first.  */
7102   tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7103
7104   /* There is one exception to the general way of distributing:
7105      (a ^ b) | (a ^ c) -> (~a) & (b ^ c)  */
7106   if (code == XOR && inner_code == IOR)
7107     {
7108       inner_code = AND;
7109       other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7110     }
7111
7112   /* We may be able to continuing distributing the result, so call
7113      ourselves recursively on the inner operation before forming the
7114      outer operation, which we return.  */
7115   return gen_binary (inner_code, GET_MODE (x),
7116                      apply_distributive_law (tem), other);
7117 }
7118 \f
7119 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7120    in MODE.
7121
7122    Return an equivalent form, if different from X.  Otherwise, return X.  If
7123    X is zero, we are to always construct the equivalent form.  */
7124
7125 static rtx
7126 simplify_and_const_int (x, mode, varop, constop)
7127      rtx x;
7128      enum machine_mode mode;
7129      rtx varop;
7130      unsigned HOST_WIDE_INT constop;
7131 {
7132   unsigned HOST_WIDE_INT nonzero;
7133   int width = GET_MODE_BITSIZE (mode);
7134   int i;
7135
7136   /* Simplify VAROP knowing that we will be only looking at some of the
7137      bits in it.  */
7138   varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7139
7140   /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7141      CONST_INT, we are done.  */
7142   if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7143     return varop;
7144
7145   /* See what bits may be nonzero in VAROP.  Unlike the general case of
7146      a call to nonzero_bits, here we don't care about bits outside
7147      MODE.  */
7148
7149   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7150
7151   /* If this would be an entire word for the target, but is not for
7152      the host, then sign-extend on the host so that the number will look
7153      the same way on the host that it would on the target.
7154
7155      For example, when building a 64 bit alpha hosted 32 bit sparc
7156      targeted compiler, then we want the 32 bit unsigned value -1 to be
7157      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7158      The later confuses the sparc backend.  */
7159
7160   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7161       && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7162     nonzero |= ((HOST_WIDE_INT) (-1) << width);
7163
7164   /* Turn off all bits in the constant that are known to already be zero.
7165      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7166      which is tested below.  */
7167
7168   constop &= nonzero;
7169
7170   /* If we don't have any bits left, return zero.  */
7171   if (constop == 0)
7172     return const0_rtx;
7173
7174   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7175      a power of two, we can replace this with a ASHIFT.  */
7176   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7177       && (i = exact_log2 (constop)) >= 0)
7178     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7179
7180   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7181      or XOR, then try to apply the distributive law.  This may eliminate
7182      operations if either branch can be simplified because of the AND.
7183      It may also make some cases more complex, but those cases probably
7184      won't match a pattern either with or without this.  */
7185
7186   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7187     return
7188       gen_lowpart_for_combine
7189         (mode,
7190          apply_distributive_law
7191          (gen_binary (GET_CODE (varop), GET_MODE (varop),
7192                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7193                                               XEXP (varop, 0), constop),
7194                       simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7195                                               XEXP (varop, 1), constop))));
7196
7197   /* Get VAROP in MODE.  Try to get a SUBREG if not.  Don't make a new SUBREG
7198      if we already had one (just check for the simplest cases).  */
7199   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7200       && GET_MODE (XEXP (x, 0)) == mode
7201       && SUBREG_REG (XEXP (x, 0)) == varop)
7202     varop = XEXP (x, 0);
7203   else
7204     varop = gen_lowpart_for_combine (mode, varop);
7205
7206   /* If we can't make the SUBREG, try to return what we were given.  */
7207   if (GET_CODE (varop) == CLOBBER)
7208     return x ? x : varop;
7209
7210   /* If we are only masking insignificant bits, return VAROP.  */
7211   if (constop == nonzero)
7212     x = varop;
7213
7214   /* Otherwise, return an AND.  See how much, if any, of X we can use.  */
7215   else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7216     x = gen_binary (AND, mode, varop, GEN_INT (constop));
7217
7218   else
7219     {
7220       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7221           || INTVAL (XEXP (x, 1)) != constop)
7222         SUBST (XEXP (x, 1), GEN_INT (constop));
7223
7224       SUBST (XEXP (x, 0), varop);
7225     }
7226
7227   return x;
7228 }
7229 \f
7230 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7231    We don't let nonzero_bits recur into num_sign_bit_copies, because that
7232    is less useful.  We can't allow both, because that results in exponential
7233    run time recursion.  There is a nullstone testcase that triggered
7234    this.  This macro avoids accidental uses of num_sign_bit_copies.  */
7235 #define num_sign_bit_copies()
7236
7237 /* Given an expression, X, compute which bits in X can be non-zero.
7238    We don't care about bits outside of those defined in MODE.
7239
7240    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7241    a shift, AND, or zero_extract, we can do better.  */
7242
7243 static unsigned HOST_WIDE_INT
7244 nonzero_bits (x, mode)
7245      rtx x;
7246      enum machine_mode mode;
7247 {
7248   unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7249   unsigned HOST_WIDE_INT inner_nz;
7250   enum rtx_code code;
7251   int mode_width = GET_MODE_BITSIZE (mode);
7252   rtx tem;
7253
7254   /* For floating-point values, assume all bits are needed.  */
7255   if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7256     return nonzero;
7257
7258   /* If X is wider than MODE, use its mode instead.  */
7259   if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7260     {
7261       mode = GET_MODE (x);
7262       nonzero = GET_MODE_MASK (mode);
7263       mode_width = GET_MODE_BITSIZE (mode);
7264     }
7265
7266   if (mode_width > HOST_BITS_PER_WIDE_INT)
7267     /* Our only callers in this case look for single bit values.  So
7268        just return the mode mask.  Those tests will then be false.  */
7269     return nonzero;
7270
7271 #ifndef WORD_REGISTER_OPERATIONS
7272   /* If MODE is wider than X, but both are a single word for both the host
7273      and target machines, we can compute this from which bits of the
7274      object might be nonzero in its own mode, taking into account the fact
7275      that on many CISC machines, accessing an object in a wider mode
7276      causes the high-order bits to become undefined.  So they are
7277      not known to be zero.  */
7278
7279   if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7280       && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7281       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7282       && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7283     {
7284       nonzero &= nonzero_bits (x, GET_MODE (x));
7285       nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7286       return nonzero;
7287     }
7288 #endif
7289
7290   code = GET_CODE (x);
7291   switch (code)
7292     {
7293     case REG:
7294 #ifdef POINTERS_EXTEND_UNSIGNED
7295       /* If pointers extend unsigned and this is a pointer in Pmode, say that
7296          all the bits above ptr_mode are known to be zero.  */
7297       if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7298           && REGNO_POINTER_FLAG (REGNO (x)))
7299         nonzero &= GET_MODE_MASK (ptr_mode);
7300 #endif
7301
7302 #ifdef STACK_BOUNDARY
7303       /* If this is the stack pointer, we may know something about its
7304          alignment.  If PUSH_ROUNDING is defined, it is possible for the
7305          stack to be momentarily aligned only to that amount, so we pick
7306          the least alignment.  */
7307
7308       /* We can't check for arg_pointer_rtx here, because it is not
7309          guaranteed to have as much alignment as the stack pointer.
7310          In particular, in the Irix6 n64 ABI, the stack has 128 bit
7311          alignment but the argument pointer has only 64 bit alignment.  */
7312
7313       if (x == stack_pointer_rtx || x == frame_pointer_rtx
7314           || x == hard_frame_pointer_rtx
7315           || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7316               && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7317         {
7318           int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7319
7320 #ifdef PUSH_ROUNDING
7321           if (REGNO (x) == STACK_POINTER_REGNUM)
7322             sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7323 #endif
7324
7325           /* We must return here, otherwise we may get a worse result from
7326              one of the choices below.  There is nothing useful below as
7327              far as the stack pointer is concerned.  */
7328           return nonzero &= ~ (sp_alignment - 1);
7329         }
7330 #endif
7331
7332       /* If X is a register whose nonzero bits value is current, use it.
7333          Otherwise, if X is a register whose value we can find, use that
7334          value.  Otherwise, use the previously-computed global nonzero bits
7335          for this register.  */
7336
7337       if (reg_last_set_value[REGNO (x)] != 0
7338           && reg_last_set_mode[REGNO (x)] == mode
7339           && (REG_N_SETS (REGNO (x)) == 1
7340               || reg_last_set_label[REGNO (x)] == label_tick)
7341           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7342         return reg_last_set_nonzero_bits[REGNO (x)];
7343
7344       tem = get_last_value (x);
7345
7346       if (tem)
7347         {
7348 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7349           /* If X is narrower than MODE and TEM is a non-negative
7350              constant that would appear negative in the mode of X,
7351              sign-extend it for use in reg_nonzero_bits because some
7352              machines (maybe most) will actually do the sign-extension
7353              and this is the conservative approach.
7354
7355              ??? For 2.5, try to tighten up the MD files in this regard
7356              instead of this kludge.  */
7357
7358           if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7359               && GET_CODE (tem) == CONST_INT
7360               && INTVAL (tem) > 0
7361               && 0 != (INTVAL (tem)
7362                        & ((HOST_WIDE_INT) 1
7363                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7364             tem = GEN_INT (INTVAL (tem)
7365                            | ((HOST_WIDE_INT) (-1)
7366                               << GET_MODE_BITSIZE (GET_MODE (x))));
7367 #endif
7368           return nonzero_bits (tem, mode);
7369         }
7370       else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7371         return reg_nonzero_bits[REGNO (x)] & nonzero;
7372       else
7373         return nonzero;
7374
7375     case CONST_INT:
7376 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7377       /* If X is negative in MODE, sign-extend the value.  */
7378       if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7379           && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7380         return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7381 #endif
7382
7383       return INTVAL (x);
7384
7385     case MEM:
7386 #ifdef LOAD_EXTEND_OP
7387       /* In many, if not most, RISC machines, reading a byte from memory
7388          zeros the rest of the register.  Noticing that fact saves a lot
7389          of extra zero-extends.  */
7390       if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7391         nonzero &= GET_MODE_MASK (GET_MODE (x));
7392 #endif
7393       break;
7394
7395     case EQ:  case NE:
7396     case GT:  case GTU:
7397     case LT:  case LTU:
7398     case GE:  case GEU:
7399     case LE:  case LEU:
7400
7401       /* If this produces an integer result, we know which bits are set.
7402          Code here used to clear bits outside the mode of X, but that is
7403          now done above.  */
7404
7405       if (GET_MODE_CLASS (mode) == MODE_INT
7406           && mode_width <= HOST_BITS_PER_WIDE_INT)
7407         nonzero = STORE_FLAG_VALUE;
7408       break;
7409
7410     case NEG:
7411 #if 0
7412       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7413          and num_sign_bit_copies.  */
7414       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7415           == GET_MODE_BITSIZE (GET_MODE (x)))
7416         nonzero = 1;
7417 #endif
7418
7419       if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7420         nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7421       break;
7422
7423     case ABS:
7424 #if 0
7425       /* Disabled to avoid exponential mutual recursion between nonzero_bits
7426          and num_sign_bit_copies.  */
7427       if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7428           == GET_MODE_BITSIZE (GET_MODE (x)))
7429         nonzero = 1;
7430 #endif
7431       break;
7432
7433     case TRUNCATE:
7434       nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7435       break;
7436
7437     case ZERO_EXTEND:
7438       nonzero &= nonzero_bits (XEXP (x, 0), mode);
7439       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7440         nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7441       break;
7442
7443     case SIGN_EXTEND:
7444       /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7445          Otherwise, show all the bits in the outer mode but not the inner
7446          may be non-zero.  */
7447       inner_nz = nonzero_bits (XEXP (x, 0), mode);
7448       if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7449         {
7450           inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7451           if (inner_nz
7452               & (((HOST_WIDE_INT) 1
7453                   << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7454             inner_nz |= (GET_MODE_MASK (mode)
7455                           & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7456         }
7457
7458       nonzero &= inner_nz;
7459       break;
7460
7461     case AND:
7462       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7463                   & nonzero_bits (XEXP (x, 1), mode));
7464       break;
7465
7466     case XOR:   case IOR:
7467     case UMIN:  case UMAX:  case SMIN:  case SMAX:
7468       nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7469                   | nonzero_bits (XEXP (x, 1), mode));
7470       break;
7471
7472     case PLUS:  case MINUS:
7473     case MULT:
7474     case DIV:   case UDIV:
7475     case MOD:   case UMOD:
7476       /* We can apply the rules of arithmetic to compute the number of
7477          high- and low-order zero bits of these operations.  We start by
7478          computing the width (position of the highest-order non-zero bit)
7479          and the number of low-order zero bits for each value.  */
7480       {
7481         unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7482         unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7483         int width0 = floor_log2 (nz0) + 1;
7484         int width1 = floor_log2 (nz1) + 1;
7485         int low0 = floor_log2 (nz0 & -nz0);
7486         int low1 = floor_log2 (nz1 & -nz1);
7487         HOST_WIDE_INT op0_maybe_minusp
7488           = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7489         HOST_WIDE_INT op1_maybe_minusp
7490           = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7491         int result_width = mode_width;
7492         int result_low = 0;
7493
7494         switch (code)
7495           {
7496           case PLUS:
7497             result_width = MAX (width0, width1) + 1;
7498             result_low = MIN (low0, low1);
7499             break;
7500           case MINUS:
7501             result_low = MIN (low0, low1);
7502             break;
7503           case MULT:
7504             result_width = width0 + width1;
7505             result_low = low0 + low1;
7506             break;
7507           case DIV:
7508             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7509               result_width = width0;
7510             break;
7511           case UDIV:
7512             result_width = width0;
7513             break;
7514           case MOD:
7515             if (! op0_maybe_minusp && ! op1_maybe_minusp)
7516               result_width = MIN (width0, width1);
7517             result_low = MIN (low0, low1);
7518             break;
7519           case UMOD:
7520             result_width = MIN (width0, width1);
7521             result_low = MIN (low0, low1);
7522             break;
7523           default:
7524             abort ();
7525           }
7526
7527         if (result_width < mode_width)
7528           nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7529
7530         if (result_low > 0)
7531           nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7532       }
7533       break;
7534
7535     case ZERO_EXTRACT:
7536       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7537           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7538         nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7539       break;
7540
7541     case SUBREG:
7542       /* If this is a SUBREG formed for a promoted variable that has
7543          been zero-extended, we know that at least the high-order bits
7544          are zero, though others might be too.  */
7545
7546       if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7547         nonzero = (GET_MODE_MASK (GET_MODE (x))
7548                    & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7549
7550       /* If the inner mode is a single word for both the host and target
7551          machines, we can compute this from which bits of the inner
7552          object might be nonzero.  */
7553       if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7554           && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7555               <= HOST_BITS_PER_WIDE_INT))
7556         {
7557           nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7558
7559 #ifndef WORD_REGISTER_OPERATIONS
7560           /* On many CISC machines, accessing an object in a wider mode
7561              causes the high-order bits to become undefined.  So they are
7562              not known to be zero.  */
7563           if (GET_MODE_SIZE (GET_MODE (x))
7564               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7565             nonzero |= (GET_MODE_MASK (GET_MODE (x))
7566                         & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7567 #endif
7568         }
7569       break;
7570
7571     case ASHIFTRT:
7572     case LSHIFTRT:
7573     case ASHIFT:
7574     case ROTATE:
7575       /* The nonzero bits are in two classes: any bits within MODE
7576          that aren't in GET_MODE (x) are always significant.  The rest of the
7577          nonzero bits are those that are significant in the operand of
7578          the shift when shifted the appropriate number of bits.  This
7579          shows that high-order bits are cleared by the right shift and
7580          low-order bits by left shifts.  */
7581       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7582           && INTVAL (XEXP (x, 1)) >= 0
7583           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7584         {
7585           enum machine_mode inner_mode = GET_MODE (x);
7586           int width = GET_MODE_BITSIZE (inner_mode);
7587           int count = INTVAL (XEXP (x, 1));
7588           unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7589           unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7590           unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7591           unsigned HOST_WIDE_INT outer = 0;
7592
7593           if (mode_width > width)
7594             outer = (op_nonzero & nonzero & ~ mode_mask);
7595
7596           if (code == LSHIFTRT)
7597             inner >>= count;
7598           else if (code == ASHIFTRT)
7599             {
7600               inner >>= count;
7601
7602               /* If the sign bit may have been nonzero before the shift, we
7603                  need to mark all the places it could have been copied to
7604                  by the shift as possibly nonzero.  */
7605               if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7606                 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7607             }
7608           else if (code == ASHIFT)
7609             inner <<= count;
7610           else
7611             inner = ((inner << (count % width)
7612                       | (inner >> (width - (count % width)))) & mode_mask);
7613
7614           nonzero &= (outer | inner);
7615         }
7616       break;
7617
7618     case FFS:
7619       /* This is at most the number of bits in the mode.  */
7620       nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7621       break;
7622
7623     case IF_THEN_ELSE:
7624       nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7625                   | nonzero_bits (XEXP (x, 2), mode));
7626       break;
7627
7628     default:
7629       break;
7630     }
7631
7632   return nonzero;
7633 }
7634
7635 /* See the macro definition above.  */
7636 #undef num_sign_bit_copies
7637 \f
7638 /* Return the number of bits at the high-order end of X that are known to
7639    be equal to the sign bit.  X will be used in mode MODE; if MODE is
7640    VOIDmode, X will be used in its own mode.  The returned value  will always
7641    be between 1 and the number of bits in MODE.  */
7642
7643 static int
7644 num_sign_bit_copies (x, mode)
7645      rtx x;
7646      enum machine_mode mode;
7647 {
7648   enum rtx_code code = GET_CODE (x);
7649   int bitwidth;
7650   int num0, num1, result;
7651   unsigned HOST_WIDE_INT nonzero;
7652   rtx tem;
7653
7654   /* If we weren't given a mode, use the mode of X.  If the mode is still
7655      VOIDmode, we don't know anything.  Likewise if one of the modes is
7656      floating-point.  */
7657
7658   if (mode == VOIDmode)
7659     mode = GET_MODE (x);
7660
7661   if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7662     return 1;
7663
7664   bitwidth = GET_MODE_BITSIZE (mode);
7665
7666   /* For a smaller object, just ignore the high bits.  */
7667   if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7668     return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7669                     - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7670
7671   if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7672     {
7673 #ifndef WORD_REGISTER_OPERATIONS
7674   /* If this machine does not do all register operations on the entire
7675      register and MODE is wider than the mode of X, we can say nothing
7676      at all about the high-order bits.  */
7677       return 1;
7678 #else
7679       /* Likewise on machines that do, if the mode of the object is smaller
7680          than a word and loads of that size don't sign extend, we can say
7681          nothing about the high order bits.  */
7682       if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7683 #ifdef LOAD_EXTEND_OP
7684           && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7685 #endif
7686           )
7687         return 1;
7688 #endif
7689     }
7690
7691   switch (code)
7692     {
7693     case REG:
7694
7695 #ifdef POINTERS_EXTEND_UNSIGNED
7696       /* If pointers extend signed and this is a pointer in Pmode, say that
7697          all the bits above ptr_mode are known to be sign bit copies.  */
7698       if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7699           && REGNO_POINTER_FLAG (REGNO (x)))
7700         return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7701 #endif
7702
7703       if (reg_last_set_value[REGNO (x)] != 0
7704           && reg_last_set_mode[REGNO (x)] == mode
7705           && (REG_N_SETS (REGNO (x)) == 1
7706               || reg_last_set_label[REGNO (x)] == label_tick)
7707           && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7708         return reg_last_set_sign_bit_copies[REGNO (x)];
7709
7710       tem =  get_last_value (x);
7711       if (tem != 0)
7712         return num_sign_bit_copies (tem, mode);
7713
7714       if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7715         return reg_sign_bit_copies[REGNO (x)];
7716       break;
7717
7718     case MEM:
7719 #ifdef LOAD_EXTEND_OP
7720       /* Some RISC machines sign-extend all loads of smaller than a word.  */
7721       if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7722         return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7723 #endif
7724       break;
7725
7726     case CONST_INT:
7727       /* If the constant is negative, take its 1's complement and remask.
7728          Then see how many zero bits we have.  */
7729       nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7730       if (bitwidth <= HOST_BITS_PER_WIDE_INT
7731           && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7732         nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7733
7734       return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7735
7736     case SUBREG:
7737       /* If this is a SUBREG for a promoted object that is sign-extended
7738          and we are looking at it in a wider mode, we know that at least the
7739          high-order bits are known to be sign bit copies.  */
7740
7741       if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7742         return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7743                     num_sign_bit_copies (SUBREG_REG (x), mode));
7744
7745       /* For a smaller object, just ignore the high bits.  */
7746       if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7747         {
7748           num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7749           return MAX (1, (num0
7750                           - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7751                              - bitwidth)));
7752         }
7753
7754 #ifdef WORD_REGISTER_OPERATIONS
7755 #ifdef LOAD_EXTEND_OP
7756       /* For paradoxical SUBREGs on machines where all register operations
7757          affect the entire register, just look inside.  Note that we are
7758          passing MODE to the recursive call, so the number of sign bit copies
7759          will remain relative to that mode, not the inner mode.  */
7760
7761       /* This works only if loads sign extend.  Otherwise, if we get a
7762          reload for the inner part, it may be loaded from the stack, and
7763          then we lose all sign bit copies that existed before the store
7764          to the stack.  */
7765
7766       if ((GET_MODE_SIZE (GET_MODE (x))
7767            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7768           && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7769         return num_sign_bit_copies (SUBREG_REG (x), mode);
7770 #endif
7771 #endif
7772       break;
7773
7774     case SIGN_EXTRACT:
7775       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7776         return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7777       break;
7778
7779     case SIGN_EXTEND:
7780       return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7781               + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7782
7783     case TRUNCATE:
7784       /* For a smaller object, just ignore the high bits.  */
7785       num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7786       return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7787                               - bitwidth)));
7788
7789     case NOT:
7790       return num_sign_bit_copies (XEXP (x, 0), mode);
7791
7792     case ROTATE:       case ROTATERT:
7793       /* If we are rotating left by a number of bits less than the number
7794          of sign bit copies, we can just subtract that amount from the
7795          number.  */
7796       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7797           && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7798         {
7799           num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7800           return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7801                                  : bitwidth - INTVAL (XEXP (x, 1))));
7802         }
7803       break;
7804
7805     case NEG:
7806       /* In general, this subtracts one sign bit copy.  But if the value
7807          is known to be positive, the number of sign bit copies is the
7808          same as that of the input.  Finally, if the input has just one bit
7809          that might be nonzero, all the bits are copies of the sign bit.  */
7810       nonzero = nonzero_bits (XEXP (x, 0), mode);
7811       if (nonzero == 1)
7812         return bitwidth;
7813
7814       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7815       if (num0 > 1
7816           && bitwidth <= HOST_BITS_PER_WIDE_INT
7817           && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7818         num0--;
7819
7820       return num0;
7821
7822     case IOR:   case AND:   case XOR:
7823     case SMIN:  case SMAX:  case UMIN:  case UMAX:
7824       /* Logical operations will preserve the number of sign-bit copies.
7825          MIN and MAX operations always return one of the operands.  */
7826       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7827       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7828       return MIN (num0, num1);
7829
7830     case PLUS:  case MINUS:
7831       /* For addition and subtraction, we can have a 1-bit carry.  However,
7832          if we are subtracting 1 from a positive number, there will not
7833          be such a carry.  Furthermore, if the positive number is known to
7834          be 0 or 1, we know the result is either -1 or 0.  */
7835
7836       if (code == PLUS && XEXP (x, 1) == constm1_rtx
7837           && bitwidth <= HOST_BITS_PER_WIDE_INT)
7838         {
7839           nonzero = nonzero_bits (XEXP (x, 0), mode);
7840           if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7841             return (nonzero == 1 || nonzero == 0 ? bitwidth
7842                     : bitwidth - floor_log2 (nonzero) - 1);
7843         }
7844
7845       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7846       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7847       return MAX (1, MIN (num0, num1) - 1);
7848
7849     case MULT:
7850       /* The number of bits of the product is the sum of the number of
7851          bits of both terms.  However, unless one of the terms if known
7852          to be positive, we must allow for an additional bit since negating
7853          a negative number can remove one sign bit copy.  */
7854
7855       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7856       num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7857
7858       result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7859       if (result > 0
7860           && bitwidth <= HOST_BITS_PER_WIDE_INT
7861           && ((nonzero_bits (XEXP (x, 0), mode)
7862                & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7863           && ((nonzero_bits (XEXP (x, 1), mode)
7864               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7865         result--;
7866
7867       return MAX (1, result);
7868
7869     case UDIV:
7870       /* The result must be <= the first operand.  */
7871       return num_sign_bit_copies (XEXP (x, 0), mode);
7872
7873     case UMOD:
7874       /* The result must be <= the scond operand.  */
7875       return num_sign_bit_copies (XEXP (x, 1), mode);
7876
7877     case DIV:
7878       /* Similar to unsigned division, except that we have to worry about
7879          the case where the divisor is negative, in which case we have
7880          to add 1.  */
7881       result = num_sign_bit_copies (XEXP (x, 0), mode);
7882       if (result > 1
7883           && bitwidth <= HOST_BITS_PER_WIDE_INT
7884           && (nonzero_bits (XEXP (x, 1), mode)
7885               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7886         result --;
7887
7888       return result;
7889
7890     case MOD:
7891       result = num_sign_bit_copies (XEXP (x, 1), mode);
7892       if (result > 1
7893           && bitwidth <= HOST_BITS_PER_WIDE_INT
7894           && (nonzero_bits (XEXP (x, 1), mode)
7895               & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7896         result --;
7897
7898       return result;
7899
7900     case ASHIFTRT:
7901       /* Shifts by a constant add to the number of bits equal to the
7902          sign bit.  */
7903       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7904       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7905           && INTVAL (XEXP (x, 1)) > 0)
7906         num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7907
7908       return num0;
7909
7910     case ASHIFT:
7911       /* Left shifts destroy copies.  */
7912       if (GET_CODE (XEXP (x, 1)) != CONST_INT
7913           || INTVAL (XEXP (x, 1)) < 0
7914           || INTVAL (XEXP (x, 1)) >= bitwidth)
7915         return 1;
7916
7917       num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7918       return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7919
7920     case IF_THEN_ELSE:
7921       num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7922       num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7923       return MIN (num0, num1);
7924
7925     case EQ:  case NE:  case GE:  case GT:  case LE:  case LT:
7926     case GEU: case GTU: case LEU: case LTU:
7927       if (STORE_FLAG_VALUE == -1)
7928         return bitwidth;
7929       break;
7930
7931     default:
7932       break;
7933     }
7934
7935   /* If we haven't been able to figure it out by one of the above rules,
7936      see if some of the high-order bits are known to be zero.  If so,
7937      count those bits and return one less than that amount.  If we can't
7938      safely compute the mask for this mode, always return BITWIDTH.  */
7939
7940   if (bitwidth > HOST_BITS_PER_WIDE_INT)
7941     return 1;
7942
7943   nonzero = nonzero_bits (x, mode);
7944   return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7945           ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7946 }
7947 \f
7948 /* Return the number of "extended" bits there are in X, when interpreted
7949    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
7950    unsigned quantities, this is the number of high-order zero bits.
7951    For signed quantities, this is the number of copies of the sign bit
7952    minus 1.  In both case, this function returns the number of "spare"
7953    bits.  For example, if two quantities for which this function returns
7954    at least 1 are added, the addition is known not to overflow.
7955
7956    This function will always return 0 unless called during combine, which
7957    implies that it must be called from a define_split.  */
7958
7959 int
7960 extended_count (x, mode, unsignedp)
7961      rtx x;
7962      enum machine_mode mode;
7963      int unsignedp;
7964 {
7965   if (nonzero_sign_valid == 0)
7966     return 0;
7967
7968   return (unsignedp
7969           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7970              && (GET_MODE_BITSIZE (mode) - 1
7971                  - floor_log2 (nonzero_bits (x, mode))))
7972           : num_sign_bit_copies (x, mode) - 1);
7973 }
7974 \f
7975 /* This function is called from `simplify_shift_const' to merge two
7976    outer operations.  Specifically, we have already found that we need
7977    to perform operation *POP0 with constant *PCONST0 at the outermost
7978    position.  We would now like to also perform OP1 with constant CONST1
7979    (with *POP0 being done last).
7980
7981    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7982    the resulting operation.  *PCOMP_P is set to 1 if we would need to
7983    complement the innermost operand, otherwise it is unchanged.
7984
7985    MODE is the mode in which the operation will be done.  No bits outside
7986    the width of this mode matter.  It is assumed that the width of this mode
7987    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7988
7989    If *POP0 or OP1 are NIL, it means no operation is required.  Only NEG, PLUS,
7990    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
7991    result is simply *PCONST0.
7992
7993    If the resulting operation cannot be expressed as one operation, we
7994    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
7995
7996 static int
7997 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7998      enum rtx_code *pop0;
7999      HOST_WIDE_INT *pconst0;
8000      enum rtx_code op1;
8001      HOST_WIDE_INT const1;
8002      enum machine_mode mode;
8003      int *pcomp_p;
8004 {
8005   enum rtx_code op0 = *pop0;
8006   HOST_WIDE_INT const0 = *pconst0;
8007   int width = GET_MODE_BITSIZE (mode);
8008
8009   const0 &= GET_MODE_MASK (mode);
8010   const1 &= GET_MODE_MASK (mode);
8011
8012   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8013   if (op0 == AND)
8014     const1 &= const0;
8015
8016   /* If OP0 or OP1 is NIL, this is easy.  Similarly if they are the same or
8017      if OP0 is SET.  */
8018
8019   if (op1 == NIL || op0 == SET)
8020     return 1;
8021
8022   else if (op0 == NIL)
8023     op0 = op1, const0 = const1;
8024
8025   else if (op0 == op1)
8026     {
8027       switch (op0)
8028         {
8029         case AND:
8030           const0 &= const1;
8031           break;
8032         case IOR:
8033           const0 |= const1;
8034           break;
8035         case XOR:
8036           const0 ^= const1;
8037           break;
8038         case PLUS:
8039           const0 += const1;
8040           break;
8041         case NEG:
8042           op0 = NIL;
8043           break;
8044         default:
8045           break;
8046         }
8047     }
8048
8049   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8050   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8051     return 0;
8052
8053   /* If the two constants aren't the same, we can't do anything.  The
8054      remaining six cases can all be done.  */
8055   else if (const0 != const1)
8056     return 0;
8057
8058   else
8059     switch (op0)
8060       {
8061       case IOR:
8062         if (op1 == AND)
8063           /* (a & b) | b == b */
8064           op0 = SET;
8065         else /* op1 == XOR */
8066           /* (a ^ b) | b == a | b */
8067           ;
8068         break;
8069
8070       case XOR:
8071         if (op1 == AND)
8072           /* (a & b) ^ b == (~a) & b */
8073           op0 = AND, *pcomp_p = 1;
8074         else /* op1 == IOR */
8075           /* (a | b) ^ b == a & ~b */
8076           op0 = AND, *pconst0 = ~ const0;
8077         break;
8078
8079       case AND:
8080         if (op1 == IOR)
8081           /* (a | b) & b == b */
8082         op0 = SET;
8083         else /* op1 == XOR */
8084           /* (a ^ b) & b) == (~a) & b */
8085           *pcomp_p = 1;
8086         break;
8087       default:
8088         break;
8089       }
8090
8091   /* Check for NO-OP cases.  */
8092   const0 &= GET_MODE_MASK (mode);
8093   if (const0 == 0
8094       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8095     op0 = NIL;
8096   else if (const0 == 0 && op0 == AND)
8097     op0 = SET;
8098   else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8099     op0 = NIL;
8100
8101   /* If this would be an entire word for the target, but is not for
8102      the host, then sign-extend on the host so that the number will look
8103      the same way on the host that it would on the target.
8104
8105      For example, when building a 64 bit alpha hosted 32 bit sparc
8106      targeted compiler, then we want the 32 bit unsigned value -1 to be
8107      represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8108      The later confuses the sparc backend.  */
8109
8110   if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8111       && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8112     const0 |= ((HOST_WIDE_INT) (-1) << width);
8113
8114   *pop0 = op0;
8115   *pconst0 = const0;
8116
8117   return 1;
8118 }
8119 \f
8120 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8121    The result of the shift is RESULT_MODE.  X, if non-zero, is an expression
8122    that we started with.
8123
8124    The shift is normally computed in the widest mode we find in VAROP, as
8125    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8126    are ASHIFTRT and ROTATE, which are always done in their original mode,  */
8127
8128 static rtx
8129 simplify_shift_const (x, code, result_mode, varop, count)
8130      rtx x;
8131      enum rtx_code code;
8132      enum machine_mode result_mode;
8133      rtx varop;
8134      int count;
8135 {
8136   enum rtx_code orig_code = code;
8137   int orig_count = count;
8138   enum machine_mode mode = result_mode;
8139   enum machine_mode shift_mode, tmode;
8140   int mode_words
8141     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8142   /* We form (outer_op (code varop count) (outer_const)).  */
8143   enum rtx_code outer_op = NIL;
8144   HOST_WIDE_INT outer_const = 0;
8145   rtx const_rtx;
8146   int complement_p = 0;
8147   rtx new;
8148
8149   /* If we were given an invalid count, don't do anything except exactly
8150      what was requested.  */
8151
8152   if (count < 0 || count > GET_MODE_BITSIZE (mode))
8153     {
8154       if (x)
8155         return x;
8156
8157       return gen_rtx (code, mode, varop, GEN_INT (count));
8158     }
8159
8160   /* Unless one of the branches of the `if' in this loop does a `continue',
8161      we will `break' the loop after the `if'.  */
8162
8163   while (count != 0)
8164     {
8165       /* If we have an operand of (clobber (const_int 0)), just return that
8166          value.  */
8167       if (GET_CODE (varop) == CLOBBER)
8168         return varop;
8169
8170       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8171          here would cause an infinite loop.  */
8172       if (complement_p)
8173         break;
8174
8175       /* Convert ROTATERT to ROTATE.  */
8176       if (code == ROTATERT)
8177         code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8178
8179       /* We need to determine what mode we will do the shift in.  If the
8180          shift is a right shift or a ROTATE, we must always do it in the mode
8181          it was originally done in.  Otherwise, we can do it in MODE, the
8182          widest mode encountered.  */
8183       shift_mode
8184         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8185            ? result_mode : mode);
8186
8187       /* Handle cases where the count is greater than the size of the mode
8188          minus 1.  For ASHIFT, use the size minus one as the count (this can
8189          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8190          take the count modulo the size.  For other shifts, the result is
8191          zero.
8192
8193          Since these shifts are being produced by the compiler by combining
8194          multiple operations, each of which are defined, we know what the
8195          result is supposed to be.  */
8196
8197       if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8198         {
8199           if (code == ASHIFTRT)
8200             count = GET_MODE_BITSIZE (shift_mode) - 1;
8201           else if (code == ROTATE || code == ROTATERT)
8202             count %= GET_MODE_BITSIZE (shift_mode);
8203           else
8204             {
8205               /* We can't simply return zero because there may be an
8206                  outer op.  */
8207               varop = const0_rtx;
8208               count = 0;
8209               break;
8210             }
8211         }
8212
8213       /* Negative counts are invalid and should not have been made (a
8214          programmer-specified negative count should have been handled
8215          above).  */
8216       else if (count < 0)
8217         abort ();
8218
8219       /* An arithmetic right shift of a quantity known to be -1 or 0
8220          is a no-op.  */
8221       if (code == ASHIFTRT
8222           && (num_sign_bit_copies (varop, shift_mode)
8223               == GET_MODE_BITSIZE (shift_mode)))
8224         {
8225           count = 0;
8226           break;
8227         }
8228
8229       /* If we are doing an arithmetic right shift and discarding all but
8230          the sign bit copies, this is equivalent to doing a shift by the
8231          bitsize minus one.  Convert it into that shift because it will often
8232          allow other simplifications.  */
8233
8234       if (code == ASHIFTRT
8235           && (count + num_sign_bit_copies (varop, shift_mode)
8236               >= GET_MODE_BITSIZE (shift_mode)))
8237         count = GET_MODE_BITSIZE (shift_mode) - 1;
8238
8239       /* We simplify the tests below and elsewhere by converting
8240          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8241          `make_compound_operation' will convert it to a ASHIFTRT for
8242          those machines (such as Vax) that don't have a LSHIFTRT.  */
8243       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8244           && code == ASHIFTRT
8245           && ((nonzero_bits (varop, shift_mode)
8246                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8247               == 0))
8248         code = LSHIFTRT;
8249
8250       switch (GET_CODE (varop))
8251         {
8252         case SIGN_EXTEND:
8253         case ZERO_EXTEND:
8254         case SIGN_EXTRACT:
8255         case ZERO_EXTRACT:
8256           new = expand_compound_operation (varop);
8257           if (new != varop)
8258             {
8259               varop = new;
8260               continue;
8261             }
8262           break;
8263
8264         case MEM:
8265           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8266              minus the width of a smaller mode, we can do this with a
8267              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8268           if ((code == ASHIFTRT || code == LSHIFTRT)
8269               && ! mode_dependent_address_p (XEXP (varop, 0))
8270               && ! MEM_VOLATILE_P (varop)
8271               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8272                                          MODE_INT, 1)) != BLKmode)
8273             {
8274               if (BYTES_BIG_ENDIAN)
8275                 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8276               else
8277                 new = gen_rtx (MEM, tmode,
8278                                plus_constant (XEXP (varop, 0),
8279                                               count / BITS_PER_UNIT));
8280               RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8281               MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8282               MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8283               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8284                                        : ZERO_EXTEND, mode, new);
8285               count = 0;
8286               continue;
8287             }
8288           break;
8289
8290         case USE:
8291           /* Similar to the case above, except that we can only do this if
8292              the resulting mode is the same as that of the underlying
8293              MEM and adjust the address depending on the *bits* endianness
8294              because of the way that bit-field extract insns are defined.  */
8295           if ((code == ASHIFTRT || code == LSHIFTRT)
8296               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8297                                          MODE_INT, 1)) != BLKmode
8298               && tmode == GET_MODE (XEXP (varop, 0)))
8299             {
8300               if (BITS_BIG_ENDIAN)
8301                 new = XEXP (varop, 0);
8302               else
8303                 {
8304                   new = copy_rtx (XEXP (varop, 0));
8305                   SUBST (XEXP (new, 0),
8306                          plus_constant (XEXP (new, 0),
8307                                         count / BITS_PER_UNIT));
8308                 }
8309
8310               varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8311                                        : ZERO_EXTEND, mode, new);
8312               count = 0;
8313               continue;
8314             }
8315           break;
8316
8317         case SUBREG:
8318           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8319              the same number of words as what we've seen so far.  Then store
8320              the widest mode in MODE.  */
8321           if (subreg_lowpart_p (varop)
8322               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8323                   > GET_MODE_SIZE (GET_MODE (varop)))
8324               && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8325                     + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8326                   == mode_words))
8327             {
8328               varop = SUBREG_REG (varop);
8329               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8330                 mode = GET_MODE (varop);
8331               continue;
8332             }
8333           break;
8334
8335         case MULT:
8336           /* Some machines use MULT instead of ASHIFT because MULT
8337              is cheaper.  But it is still better on those machines to
8338              merge two shifts into one.  */
8339           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8340               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8341             {
8342               varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8343                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8344               continue;
8345             }
8346           break;
8347
8348         case UDIV:
8349           /* Similar, for when divides are cheaper.  */
8350           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8351               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8352             {
8353               varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8354                                   GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8355               continue;
8356             }
8357           break;
8358
8359         case ASHIFTRT:
8360           /* If we are extracting just the sign bit of an arithmetic right
8361              shift, that shift is not needed.  */
8362           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8363             {
8364               varop = XEXP (varop, 0);
8365               continue;
8366             }
8367
8368           /* ... fall through ...  */
8369
8370         case LSHIFTRT:
8371         case ASHIFT:
8372         case ROTATE:
8373           /* Here we have two nested shifts.  The result is usually the
8374              AND of a new shift with a mask.  We compute the result below.  */
8375           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8376               && INTVAL (XEXP (varop, 1)) >= 0
8377               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8378               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8379               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8380             {
8381               enum rtx_code first_code = GET_CODE (varop);
8382               int first_count = INTVAL (XEXP (varop, 1));
8383               unsigned HOST_WIDE_INT mask;
8384               rtx mask_rtx;
8385
8386               /* We have one common special case.  We can't do any merging if
8387                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8388                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8389                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8390                  we can convert it to
8391                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8392                  This simplifies certain SIGN_EXTEND operations.  */
8393               if (code == ASHIFT && first_code == ASHIFTRT
8394                   && (GET_MODE_BITSIZE (result_mode)
8395                       - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8396                 {
8397                   /* C3 has the low-order C1 bits zero.  */
8398
8399                   mask = (GET_MODE_MASK (mode)
8400                           & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8401
8402                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8403                                                   XEXP (varop, 0), mask);
8404                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8405                                                 varop, count);
8406                   count = first_count;
8407                   code = ASHIFTRT;
8408                   continue;
8409                 }
8410
8411               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8412                  than C1 high-order bits equal to the sign bit, we can convert
8413                  this to either an ASHIFT or a ASHIFTRT depending on the
8414                  two counts.
8415
8416                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8417
8418               if (code == ASHIFTRT && first_code == ASHIFT
8419                   && GET_MODE (varop) == shift_mode
8420                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8421                       > first_count))
8422                 {
8423                   count -= first_count;
8424                   if (count < 0)
8425                     count = - count, code = ASHIFT;
8426                   varop = XEXP (varop, 0);
8427                   continue;
8428                 }
8429
8430               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8431                  we can only do this if FIRST_CODE is also ASHIFTRT.
8432
8433                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8434                  ASHIFTRT.
8435
8436                  If the mode of this shift is not the mode of the outer shift,
8437                  we can't do this if either shift is a right shift or ROTATE.
8438
8439                  Finally, we can't do any of these if the mode is too wide
8440                  unless the codes are the same.
8441
8442                  Handle the case where the shift codes are the same
8443                  first.  */
8444
8445               if (code == first_code)
8446                 {
8447                   if (GET_MODE (varop) != result_mode
8448                       && (code == ASHIFTRT || code == LSHIFTRT
8449                           || code == ROTATE))
8450                     break;
8451
8452                   count += first_count;
8453                   varop = XEXP (varop, 0);
8454                   continue;
8455                 }
8456
8457               if (code == ASHIFTRT
8458                   || (code == ROTATE && first_code == ASHIFTRT)
8459                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8460                   || (GET_MODE (varop) != result_mode
8461                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8462                           || first_code == ROTATE
8463                           || code == ROTATE)))
8464                 break;
8465
8466               /* To compute the mask to apply after the shift, shift the
8467                  nonzero bits of the inner shift the same way the
8468                  outer shift will.  */
8469
8470               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8471
8472               mask_rtx
8473                 = simplify_binary_operation (code, result_mode, mask_rtx,
8474                                              GEN_INT (count));
8475
8476               /* Give up if we can't compute an outer operation to use.  */
8477               if (mask_rtx == 0
8478                   || GET_CODE (mask_rtx) != CONST_INT
8479                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8480                                         INTVAL (mask_rtx),
8481                                         result_mode, &complement_p))
8482                 break;
8483
8484               /* If the shifts are in the same direction, we add the
8485                  counts.  Otherwise, we subtract them.  */
8486               if ((code == ASHIFTRT || code == LSHIFTRT)
8487                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8488                 count += first_count;
8489               else
8490                 count -= first_count;
8491
8492               /* If COUNT is positive, the new shift is usually CODE,
8493                  except for the two exceptions below, in which case it is
8494                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8495                  always be used  */
8496               if (count > 0
8497                   && ((first_code == ROTATE && code == ASHIFT)
8498                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8499                 code = first_code;
8500               else if (count < 0)
8501                 code = first_code, count = - count;
8502
8503               varop = XEXP (varop, 0);
8504               continue;
8505             }
8506
8507           /* If we have (A << B << C) for any shift, we can convert this to
8508              (A << C << B).  This wins if A is a constant.  Only try this if
8509              B is not a constant.  */
8510
8511           else if (GET_CODE (varop) == code
8512                    && GET_CODE (XEXP (varop, 1)) != CONST_INT
8513                    && 0 != (new
8514                             = simplify_binary_operation (code, mode,
8515                                                          XEXP (varop, 0),
8516                                                          GEN_INT (count))))
8517             {
8518               varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8519               count = 0;
8520               continue;
8521             }
8522           break;
8523
8524         case NOT:
8525           /* Make this fit the case below.  */
8526           varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8527                                    GEN_INT (GET_MODE_MASK (mode)));
8528           continue;
8529
8530         case IOR:
8531         case AND:
8532         case XOR:
8533           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8534              with C the size of VAROP - 1 and the shift is logical if
8535              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8536              we have an (le X 0) operation.   If we have an arithmetic shift
8537              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8538              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8539
8540           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8541               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8542               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8543               && (code == LSHIFTRT || code == ASHIFTRT)
8544               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8545               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8546             {
8547               count = 0;
8548               varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8549                                        const0_rtx);
8550
8551               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8552                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8553
8554               continue;
8555             }
8556
8557           /* If we have (shift (logical)), move the logical to the outside
8558              to allow it to possibly combine with another logical and the
8559              shift to combine with another shift.  This also canonicalizes to
8560              what a ZERO_EXTRACT looks like.  Also, some machines have
8561              (and (shift)) insns.  */
8562
8563           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8564               && (new = simplify_binary_operation (code, result_mode,
8565                                                    XEXP (varop, 1),
8566                                                    GEN_INT (count))) != 0
8567               && GET_CODE(new) == CONST_INT
8568               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8569                                   INTVAL (new), result_mode, &complement_p))
8570             {
8571               varop = XEXP (varop, 0);
8572               continue;
8573             }
8574
8575           /* If we can't do that, try to simplify the shift in each arm of the
8576              logical expression, make a new logical expression, and apply
8577              the inverse distributive law.  */
8578           {
8579             rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8580                                             XEXP (varop, 0), count);
8581             rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8582                                             XEXP (varop, 1), count);
8583
8584             varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8585             varop = apply_distributive_law (varop);
8586
8587             count = 0;
8588           }
8589           break;
8590
8591         case EQ:
8592           /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8593              says that the sign bit can be tested, FOO has mode MODE, C is
8594              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8595              that may be nonzero.  */
8596           if (code == LSHIFTRT
8597               && XEXP (varop, 1) == const0_rtx
8598               && GET_MODE (XEXP (varop, 0)) == result_mode
8599               && count == GET_MODE_BITSIZE (result_mode) - 1
8600               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8601               && ((STORE_FLAG_VALUE
8602                    & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8603               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8604               && merge_outer_ops (&outer_op, &outer_const, XOR,
8605                                   (HOST_WIDE_INT) 1, result_mode,
8606                                   &complement_p))
8607             {
8608               varop = XEXP (varop, 0);
8609               count = 0;
8610               continue;
8611             }
8612           break;
8613
8614         case NEG:
8615           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8616              than the number of bits in the mode is equivalent to A.  */
8617           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8618               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8619             {
8620               varop = XEXP (varop, 0);
8621               count = 0;
8622               continue;
8623             }
8624
8625           /* NEG commutes with ASHIFT since it is multiplication.  Move the
8626              NEG outside to allow shifts to combine.  */
8627           if (code == ASHIFT
8628               && merge_outer_ops (&outer_op, &outer_const, NEG,
8629                                   (HOST_WIDE_INT) 0, result_mode,
8630                                   &complement_p))
8631             {
8632               varop = XEXP (varop, 0);
8633               continue;
8634             }
8635           break;
8636
8637         case PLUS:
8638           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8639              is one less than the number of bits in the mode is
8640              equivalent to (xor A 1).  */
8641           if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8642               && XEXP (varop, 1) == constm1_rtx
8643               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8644               && merge_outer_ops (&outer_op, &outer_const, XOR,
8645                                   (HOST_WIDE_INT) 1, result_mode,
8646                                   &complement_p))
8647             {
8648               count = 0;
8649               varop = XEXP (varop, 0);
8650               continue;
8651             }
8652
8653           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8654              that might be nonzero in BAR are those being shifted out and those
8655              bits are known zero in FOO, we can replace the PLUS with FOO.
8656              Similarly in the other operand order.  This code occurs when
8657              we are computing the size of a variable-size array.  */
8658
8659           if ((code == ASHIFTRT || code == LSHIFTRT)
8660               && count < HOST_BITS_PER_WIDE_INT
8661               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8662               && (nonzero_bits (XEXP (varop, 1), result_mode)
8663                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8664             {
8665               varop = XEXP (varop, 0);
8666               continue;
8667             }
8668           else if ((code == ASHIFTRT || code == LSHIFTRT)
8669                    && count < HOST_BITS_PER_WIDE_INT
8670                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8671                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8672                             >> count)
8673                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8674                             & nonzero_bits (XEXP (varop, 1),
8675                                                  result_mode)))
8676             {
8677               varop = XEXP (varop, 1);
8678               continue;
8679             }
8680
8681           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
8682           if (code == ASHIFT
8683               && GET_CODE (XEXP (varop, 1)) == CONST_INT
8684               && (new = simplify_binary_operation (ASHIFT, result_mode,
8685                                                    XEXP (varop, 1),
8686                                                    GEN_INT (count))) != 0
8687               && GET_CODE(new) == CONST_INT
8688               && merge_outer_ops (&outer_op, &outer_const, PLUS,
8689                                   INTVAL (new), result_mode, &complement_p))
8690             {
8691               varop = XEXP (varop, 0);
8692               continue;
8693             }
8694           break;
8695
8696         case MINUS:
8697           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8698              with C the size of VAROP - 1 and the shift is logical if
8699              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8700              we have a (gt X 0) operation.  If the shift is arithmetic with
8701              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8702              we have a (neg (gt X 0)) operation.  */
8703
8704           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8705               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8706               && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8707               && (code == LSHIFTRT || code == ASHIFTRT)
8708               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8709               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8710               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8711             {
8712               count = 0;
8713               varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8714                                        const0_rtx);
8715
8716               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8717                 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8718
8719               continue;
8720             }
8721           break;
8722
8723         default:
8724           break;
8725         }
8726
8727       break;
8728     }
8729
8730   /* We need to determine what mode to do the shift in.  If the shift is
8731      a right shift or ROTATE, we must always do it in the mode it was
8732      originally done in.  Otherwise, we can do it in MODE, the widest mode
8733      encountered.  The code we care about is that of the shift that will
8734      actually be done, not the shift that was originally requested.  */
8735   shift_mode
8736     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8737        ? result_mode : mode);
8738
8739   /* We have now finished analyzing the shift.  The result should be
8740      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
8741      OUTER_OP is non-NIL, it is an operation that needs to be applied
8742      to the result of the shift.  OUTER_CONST is the relevant constant,
8743      but we must turn off all bits turned off in the shift.
8744
8745      If we were passed a value for X, see if we can use any pieces of
8746      it.  If not, make new rtx.  */
8747
8748   if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8749       && GET_CODE (XEXP (x, 1)) == CONST_INT
8750       && INTVAL (XEXP (x, 1)) == count)
8751     const_rtx = XEXP (x, 1);
8752   else
8753     const_rtx = GEN_INT (count);
8754
8755   if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8756       && GET_MODE (XEXP (x, 0)) == shift_mode
8757       && SUBREG_REG (XEXP (x, 0)) == varop)
8758     varop = XEXP (x, 0);
8759   else if (GET_MODE (varop) != shift_mode)
8760     varop = gen_lowpart_for_combine (shift_mode, varop);
8761
8762   /* If we can't make the SUBREG, try to return what we were given.  */
8763   if (GET_CODE (varop) == CLOBBER)
8764     return x ? x : varop;
8765
8766   new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8767   if (new != 0)
8768     x = new;
8769   else
8770     {
8771       if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8772         x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8773
8774       SUBST (XEXP (x, 0), varop);
8775       SUBST (XEXP (x, 1), const_rtx);
8776     }
8777
8778   /* If we have an outer operation and we just made a shift, it is
8779      possible that we could have simplified the shift were it not
8780      for the outer operation.  So try to do the simplification
8781      recursively.  */
8782
8783   if (outer_op != NIL && GET_CODE (x) == code
8784       && GET_CODE (XEXP (x, 1)) == CONST_INT)
8785     x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8786                               INTVAL (XEXP (x, 1)));
8787
8788   /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8789      turn off all the bits that the shift would have turned off.  */
8790   if (orig_code == LSHIFTRT && result_mode != shift_mode)
8791     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8792                                 GET_MODE_MASK (result_mode) >> orig_count);
8793
8794   /* Do the remainder of the processing in RESULT_MODE.  */
8795   x = gen_lowpart_for_combine (result_mode, x);
8796
8797   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8798      operation.  */
8799   if (complement_p)
8800     x = gen_unary (NOT, result_mode, result_mode, x);
8801
8802   if (outer_op != NIL)
8803     {
8804       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8805         {
8806           int width = GET_MODE_BITSIZE (result_mode);
8807
8808           outer_const &= GET_MODE_MASK (result_mode);
8809
8810           /* If this would be an entire word for the target, but is not for
8811              the host, then sign-extend on the host so that the number will
8812              look the same way on the host that it would on the target.
8813
8814              For example, when building a 64 bit alpha hosted 32 bit sparc
8815              targeted compiler, then we want the 32 bit unsigned value -1 to be
8816              represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8817              The later confuses the sparc backend.  */
8818
8819           if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8820               && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8821             outer_const |= ((HOST_WIDE_INT) (-1) << width);
8822         }
8823
8824       if (outer_op == AND)
8825         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8826       else if (outer_op == SET)
8827         /* This means that we have determined that the result is
8828            equivalent to a constant.  This should be rare.  */
8829         x = GEN_INT (outer_const);
8830       else if (GET_RTX_CLASS (outer_op) == '1')
8831         x = gen_unary (outer_op, result_mode, result_mode, x);
8832       else
8833         x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8834     }
8835
8836   return x;
8837 }
8838 \f
8839 /* Like recog, but we receive the address of a pointer to a new pattern.
8840    We try to match the rtx that the pointer points to.
8841    If that fails, we may try to modify or replace the pattern,
8842    storing the replacement into the same pointer object.
8843
8844    Modifications include deletion or addition of CLOBBERs.
8845
8846    PNOTES is a pointer to a location where any REG_UNUSED notes added for
8847    the CLOBBERs are placed.
8848
8849    PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8850    we had to add.
8851
8852    The value is the final insn code from the pattern ultimately matched,
8853    or -1.  */
8854
8855 static int
8856 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8857      rtx *pnewpat;
8858      rtx insn;
8859      rtx *pnotes;
8860      int *padded_scratches;
8861 {
8862   register rtx pat = *pnewpat;
8863   int insn_code_number;
8864   int num_clobbers_to_add = 0;
8865   int i;
8866   rtx notes = 0;
8867
8868   *padded_scratches = 0;
8869
8870   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8871      we use to indicate that something didn't match.  If we find such a
8872      thing, force rejection.  */
8873   if (GET_CODE (pat) == PARALLEL)
8874     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8875       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8876           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8877         return -1;
8878
8879   /* Is the result of combination a valid instruction?  */
8880   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8881
8882   /* If it isn't, there is the possibility that we previously had an insn
8883      that clobbered some register as a side effect, but the combined
8884      insn doesn't need to do that.  So try once more without the clobbers
8885      unless this represents an ASM insn.  */
8886
8887   if (insn_code_number < 0 && ! check_asm_operands (pat)
8888       && GET_CODE (pat) == PARALLEL)
8889     {
8890       int pos;
8891
8892       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8893         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8894           {
8895             if (i != pos)
8896               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8897             pos++;
8898           }
8899
8900       SUBST_INT (XVECLEN (pat, 0), pos);
8901
8902       if (pos == 1)
8903         pat = XVECEXP (pat, 0, 0);
8904
8905       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8906     }
8907
8908   /* If we had any clobbers to add, make a new pattern than contains
8909      them.  Then check to make sure that all of them are dead.  */
8910   if (num_clobbers_to_add)
8911     {
8912       rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8913                             gen_rtvec (GET_CODE (pat) == PARALLEL
8914                                        ? XVECLEN (pat, 0) + num_clobbers_to_add
8915                                        : num_clobbers_to_add + 1));
8916
8917       if (GET_CODE (pat) == PARALLEL)
8918         for (i = 0; i < XVECLEN (pat, 0); i++)
8919           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8920       else
8921         XVECEXP (newpat, 0, 0) = pat;
8922
8923       add_clobbers (newpat, insn_code_number);
8924
8925       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8926            i < XVECLEN (newpat, 0); i++)
8927         {
8928           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8929               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8930             return -1;
8931           else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8932             (*padded_scratches)++;
8933           notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8934                            XEXP (XVECEXP (newpat, 0, i), 0), notes);
8935         }
8936       pat = newpat;
8937     }
8938
8939   *pnewpat = pat;
8940   *pnotes = notes;
8941
8942   return insn_code_number;
8943 }
8944 \f
8945 /* Like gen_lowpart but for use by combine.  In combine it is not possible
8946    to create any new pseudoregs.  However, it is safe to create
8947    invalid memory addresses, because combine will try to recognize
8948    them and all they will do is make the combine attempt fail.
8949
8950    If for some reason this cannot do its job, an rtx
8951    (clobber (const_int 0)) is returned.
8952    An insn containing that will not be recognized.  */
8953
8954 #undef gen_lowpart
8955
8956 static rtx
8957 gen_lowpart_for_combine (mode, x)
8958      enum machine_mode mode;
8959      register rtx x;
8960 {
8961   rtx result;
8962
8963   if (GET_MODE (x) == mode)
8964     return x;
8965
8966   /* We can only support MODE being wider than a word if X is a
8967      constant integer or has a mode the same size.  */
8968
8969   if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8970       && ! ((GET_MODE (x) == VOIDmode
8971              && (GET_CODE (x) == CONST_INT
8972                  || GET_CODE (x) == CONST_DOUBLE))
8973             || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8974     return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8975
8976   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
8977      won't know what to do.  So we will strip off the SUBREG here and
8978      process normally.  */
8979   if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8980     {
8981       x = SUBREG_REG (x);
8982       if (GET_MODE (x) == mode)
8983         return x;
8984     }
8985
8986   result = gen_lowpart_common (mode, x);
8987   if (result != 0
8988       && GET_CODE (result) == SUBREG
8989       && GET_CODE (SUBREG_REG (result)) == REG
8990       && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8991       && (GET_MODE_SIZE (GET_MODE (result))
8992           != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8993     REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8994
8995   if (result)
8996     return result;
8997
8998   if (GET_CODE (x) == MEM)
8999     {
9000       register int offset = 0;
9001       rtx new;
9002
9003       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9004          address.  */
9005       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9006         return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9007
9008       /* If we want to refer to something bigger than the original memref,
9009          generate a perverse subreg instead.  That will force a reload
9010          of the original memref X.  */
9011       if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9012         return gen_rtx (SUBREG, mode, x, 0);
9013
9014       if (WORDS_BIG_ENDIAN)
9015         offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9016                   - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9017       if (BYTES_BIG_ENDIAN)
9018         {
9019           /* Adjust the address so that the address-after-the-data is
9020              unchanged.  */
9021           offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9022                      - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9023         }
9024       new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
9025       RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9026       MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9027       MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9028       return new;
9029     }
9030
9031   /* If X is a comparison operator, rewrite it in a new mode.  This
9032      probably won't match, but may allow further simplifications.  */
9033   else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9034     return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9035
9036   /* If we couldn't simplify X any other way, just enclose it in a
9037      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9038      include an explicit SUBREG or we may simplify it further in combine.  */
9039   else
9040     {
9041       int word = 0;
9042
9043       if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9044         word = ((GET_MODE_SIZE (GET_MODE (x))
9045                  - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9046                 / UNITS_PER_WORD);
9047       return gen_rtx (SUBREG, mode, x, word);
9048     }
9049 }
9050 \f
9051 /* Make an rtx expression.  This is a subset of gen_rtx and only supports
9052    expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9053
9054    If the identical expression was previously in the insn (in the undobuf),
9055    it will be returned.  Only if it is not found will a new expression
9056    be made.  */
9057
9058 /*VARARGS2*/
9059 static rtx
9060 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9061 {
9062 #ifndef __STDC__
9063   enum rtx_code code;
9064   enum machine_mode mode;
9065 #endif
9066   va_list p;
9067   int n_args;
9068   rtx args[3];
9069   int i, j;
9070   char *fmt;
9071   rtx rt;
9072   struct undo *undo;
9073
9074   VA_START (p, mode);
9075
9076 #ifndef __STDC__
9077   code = va_arg (p, enum rtx_code);
9078   mode = va_arg (p, enum machine_mode);
9079 #endif
9080
9081   n_args = GET_RTX_LENGTH (code);
9082   fmt = GET_RTX_FORMAT (code);
9083
9084   if (n_args == 0 || n_args > 3)
9085     abort ();
9086
9087   /* Get each arg and verify that it is supposed to be an expression.  */
9088   for (j = 0; j < n_args; j++)
9089     {
9090       if (*fmt++ != 'e')
9091         abort ();
9092
9093       args[j] = va_arg (p, rtx);
9094     }
9095
9096   /* See if this is in undobuf.  Be sure we don't use objects that came
9097      from another insn; this could produce circular rtl structures.  */
9098
9099   for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9100     if (!undo->is_int
9101         && GET_CODE (undo->old_contents.r) == code
9102         && GET_MODE (undo->old_contents.r) == mode)
9103       {
9104         for (j = 0; j < n_args; j++)
9105           if (XEXP (undo->old_contents.r, j) != args[j])
9106             break;
9107
9108         if (j == n_args)
9109           return undo->old_contents.r;
9110       }
9111
9112   /* Otherwise make a new rtx.  We know we have 1, 2, or 3 args.
9113      Use rtx_alloc instead of gen_rtx because it's faster on RISC.  */
9114   rt = rtx_alloc (code);
9115   PUT_MODE (rt, mode);
9116   XEXP (rt, 0) = args[0];
9117   if (n_args > 1)
9118     {
9119       XEXP (rt, 1) = args[1];
9120       if (n_args > 2)
9121         XEXP (rt, 2) = args[2];
9122     }
9123   return rt;
9124 }
9125
9126 /* These routines make binary and unary operations by first seeing if they
9127    fold; if not, a new expression is allocated.  */
9128
9129 static rtx
9130 gen_binary (code, mode, op0, op1)
9131      enum rtx_code code;
9132      enum machine_mode mode;
9133      rtx op0, op1;
9134 {
9135   rtx result;
9136   rtx tem;
9137
9138   if (GET_RTX_CLASS (code) == 'c'
9139       && (GET_CODE (op0) == CONST_INT
9140           || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9141     tem = op0, op0 = op1, op1 = tem;
9142
9143   if (GET_RTX_CLASS (code) == '<')
9144     {
9145       enum machine_mode op_mode = GET_MODE (op0);
9146
9147       /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9148          just (REL_OP X Y).  */
9149       if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9150         {
9151           op1 = XEXP (op0, 1);
9152           op0 = XEXP (op0, 0);
9153           op_mode = GET_MODE (op0);
9154         }
9155
9156       if (op_mode == VOIDmode)
9157         op_mode = GET_MODE (op1);
9158       result = simplify_relational_operation (code, op_mode, op0, op1);
9159     }
9160   else
9161     result = simplify_binary_operation (code, mode, op0, op1);
9162
9163   if (result)
9164     return result;
9165
9166   /* Put complex operands first and constants second.  */
9167   if (GET_RTX_CLASS (code) == 'c'
9168       && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9169           || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9170               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9171           || (GET_CODE (op0) == SUBREG
9172               && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9173               && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9174     return gen_rtx_combine (code, mode, op1, op0);
9175
9176   return gen_rtx_combine (code, mode, op0, op1);
9177 }
9178
9179 static rtx
9180 gen_unary (code, mode, op0_mode, op0)
9181      enum rtx_code code;
9182      enum machine_mode mode, op0_mode;
9183      rtx op0;
9184 {
9185   rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9186
9187   if (result)
9188     return result;
9189
9190   return gen_rtx_combine (code, mode, op0);
9191 }
9192 \f
9193 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9194    comparison code that will be tested.
9195
9196    The result is a possibly different comparison code to use.  *POP0 and
9197    *POP1 may be updated.
9198
9199    It is possible that we might detect that a comparison is either always
9200    true or always false.  However, we do not perform general constant
9201    folding in combine, so this knowledge isn't useful.  Such tautologies
9202    should have been detected earlier.  Hence we ignore all such cases.  */
9203
9204 static enum rtx_code
9205 simplify_comparison (code, pop0, pop1)
9206      enum rtx_code code;
9207      rtx *pop0;
9208      rtx *pop1;
9209 {
9210   rtx op0 = *pop0;
9211   rtx op1 = *pop1;
9212   rtx tem, tem1;
9213   int i;
9214   enum machine_mode mode, tmode;
9215
9216   /* Try a few ways of applying the same transformation to both operands.  */
9217   while (1)
9218     {
9219 #ifndef WORD_REGISTER_OPERATIONS
9220       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9221          so check specially.  */
9222       if (code != GTU && code != GEU && code != LTU && code != LEU
9223           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9224           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9225           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9226           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9227           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9228           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9229               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9230           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9231           && GET_CODE (XEXP (op1, 1)) == CONST_INT
9232           && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9233           && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9234           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9235           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9236           && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9237           && (INTVAL (XEXP (op0, 1))
9238               == (GET_MODE_BITSIZE (GET_MODE (op0))
9239                   - (GET_MODE_BITSIZE
9240                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9241         {
9242           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9243           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9244         }
9245 #endif
9246
9247       /* If both operands are the same constant shift, see if we can ignore the
9248          shift.  We can if the shift is a rotate or if the bits shifted out of
9249          this shift are known to be zero for both inputs and if the type of
9250          comparison is compatible with the shift.  */
9251       if (GET_CODE (op0) == GET_CODE (op1)
9252           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9253           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9254               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9255                   && (code != GT && code != LT && code != GE && code != LE))
9256               || (GET_CODE (op0) == ASHIFTRT
9257                   && (code != GTU && code != LTU
9258                       && code != GEU && code != GEU)))
9259           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9260           && INTVAL (XEXP (op0, 1)) >= 0
9261           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9262           && XEXP (op0, 1) == XEXP (op1, 1))
9263         {
9264           enum machine_mode mode = GET_MODE (op0);
9265           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9266           int shift_count = INTVAL (XEXP (op0, 1));
9267
9268           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9269             mask &= (mask >> shift_count) << shift_count;
9270           else if (GET_CODE (op0) == ASHIFT)
9271             mask = (mask & (mask << shift_count)) >> shift_count;
9272
9273           if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9274               && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9275             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9276           else
9277             break;
9278         }
9279
9280       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9281          SUBREGs are of the same mode, and, in both cases, the AND would
9282          be redundant if the comparison was done in the narrower mode,
9283          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9284          and the operand's possibly nonzero bits are 0xffffff01; in that case
9285          if we only care about QImode, we don't need the AND).  This case
9286          occurs if the output mode of an scc insn is not SImode and
9287          STORE_FLAG_VALUE == 1 (e.g., the 386).
9288
9289          Similarly, check for a case where the AND's are ZERO_EXTEND
9290          operations from some narrower mode even though a SUBREG is not
9291          present.  */
9292
9293       else if  (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9294                 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9295                 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9296         {
9297           rtx inner_op0 = XEXP (op0, 0);
9298           rtx inner_op1 = XEXP (op1, 0);
9299           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9300           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9301           int changed = 0;
9302
9303           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9304               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9305                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9306               && (GET_MODE (SUBREG_REG (inner_op0))
9307                   == GET_MODE (SUBREG_REG (inner_op1)))
9308               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9309                   <= HOST_BITS_PER_WIDE_INT)
9310               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9311                                              GET_MODE (SUBREG_REG (op0)))))
9312               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9313                                              GET_MODE (SUBREG_REG (inner_op1))))))
9314             {
9315               op0 = SUBREG_REG (inner_op0);
9316               op1 = SUBREG_REG (inner_op1);
9317
9318               /* The resulting comparison is always unsigned since we masked
9319                  off the original sign bit.  */
9320               code = unsigned_condition (code);
9321
9322               changed = 1;
9323             }
9324
9325           else if (c0 == c1)
9326             for (tmode = GET_CLASS_NARROWEST_MODE
9327                  (GET_MODE_CLASS (GET_MODE (op0)));
9328                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9329               if (c0 == GET_MODE_MASK (tmode))
9330                 {
9331                   op0 = gen_lowpart_for_combine (tmode, inner_op0);
9332                   op1 = gen_lowpart_for_combine (tmode, inner_op1);
9333                   code = unsigned_condition (code);
9334                   changed = 1;
9335                   break;
9336                 }
9337
9338           if (! changed)
9339             break;
9340         }
9341
9342       /* If both operands are NOT, we can strip off the outer operation
9343          and adjust the comparison code for swapped operands; similarly for
9344          NEG, except that this must be an equality comparison.  */
9345       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9346                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9347                    && (code == EQ || code == NE)))
9348         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9349
9350       else
9351         break;
9352     }
9353
9354   /* If the first operand is a constant, swap the operands and adjust the
9355      comparison code appropriately, but don't do this if the second operand
9356      is already a constant integer.  */
9357   if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9358     {
9359       tem = op0, op0 = op1, op1 = tem;
9360       code = swap_condition (code);
9361     }
9362
9363   /* We now enter a loop during which we will try to simplify the comparison.
9364      For the most part, we only are concerned with comparisons with zero,
9365      but some things may really be comparisons with zero but not start
9366      out looking that way.  */
9367
9368   while (GET_CODE (op1) == CONST_INT)
9369     {
9370       enum machine_mode mode = GET_MODE (op0);
9371       int mode_width = GET_MODE_BITSIZE (mode);
9372       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9373       int equality_comparison_p;
9374       int sign_bit_comparison_p;
9375       int unsigned_comparison_p;
9376       HOST_WIDE_INT const_op;
9377
9378       /* We only want to handle integral modes.  This catches VOIDmode,
9379          CCmode, and the floating-point modes.  An exception is that we
9380          can handle VOIDmode if OP0 is a COMPARE or a comparison
9381          operation.  */
9382
9383       if (GET_MODE_CLASS (mode) != MODE_INT
9384           && ! (mode == VOIDmode
9385                 && (GET_CODE (op0) == COMPARE
9386                     || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9387         break;
9388
9389       /* Get the constant we are comparing against and turn off all bits
9390          not on in our mode.  */
9391       const_op = INTVAL (op1);
9392       if (mode_width <= HOST_BITS_PER_WIDE_INT)
9393         const_op &= mask;
9394
9395       /* If we are comparing against a constant power of two and the value
9396          being compared can only have that single bit nonzero (e.g., it was
9397          `and'ed with that bit), we can replace this with a comparison
9398          with zero.  */
9399       if (const_op
9400           && (code == EQ || code == NE || code == GE || code == GEU
9401               || code == LT || code == LTU)
9402           && mode_width <= HOST_BITS_PER_WIDE_INT
9403           && exact_log2 (const_op) >= 0
9404           && nonzero_bits (op0, mode) == const_op)
9405         {
9406           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9407           op1 = const0_rtx, const_op = 0;
9408         }
9409
9410       /* Similarly, if we are comparing a value known to be either -1 or
9411          0 with -1, change it to the opposite comparison against zero.  */
9412
9413       if (const_op == -1
9414           && (code == EQ || code == NE || code == GT || code == LE
9415               || code == GEU || code == LTU)
9416           && num_sign_bit_copies (op0, mode) == mode_width)
9417         {
9418           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9419           op1 = const0_rtx, const_op = 0;
9420         }
9421
9422       /* Do some canonicalizations based on the comparison code.  We prefer
9423          comparisons against zero and then prefer equality comparisons.
9424          If we can reduce the size of a constant, we will do that too.  */
9425
9426       switch (code)
9427         {
9428         case LT:
9429           /* < C is equivalent to <= (C - 1) */
9430           if (const_op > 0)
9431             {
9432               const_op -= 1;
9433               op1 = GEN_INT (const_op);
9434               code = LE;
9435               /* ... fall through to LE case below.  */
9436             }
9437           else
9438             break;
9439
9440         case LE:
9441           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9442           if (const_op < 0)
9443             {
9444               const_op += 1;
9445               op1 = GEN_INT (const_op);
9446               code = LT;
9447             }
9448
9449           /* If we are doing a <= 0 comparison on a value known to have
9450              a zero sign bit, we can replace this with == 0.  */
9451           else if (const_op == 0
9452                    && mode_width <= HOST_BITS_PER_WIDE_INT
9453                    && (nonzero_bits (op0, mode)
9454                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9455             code = EQ;
9456           break;
9457
9458         case GE:
9459           /* >= C is equivalent to > (C - 1).  */
9460           if (const_op > 0)
9461             {
9462               const_op -= 1;
9463               op1 = GEN_INT (const_op);
9464               code = GT;
9465               /* ... fall through to GT below.  */
9466             }
9467           else
9468             break;
9469
9470         case GT:
9471           /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9472           if (const_op < 0)
9473             {
9474               const_op += 1;
9475               op1 = GEN_INT (const_op);
9476               code = GE;
9477             }
9478
9479           /* If we are doing a > 0 comparison on a value known to have
9480              a zero sign bit, we can replace this with != 0.  */
9481           else if (const_op == 0
9482                    && mode_width <= HOST_BITS_PER_WIDE_INT
9483                    && (nonzero_bits (op0, mode)
9484                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9485             code = NE;
9486           break;
9487
9488         case LTU:
9489           /* < C is equivalent to <= (C - 1).  */
9490           if (const_op > 0)
9491             {
9492               const_op -= 1;
9493               op1 = GEN_INT (const_op);
9494               code = LEU;
9495               /* ... fall through ...  */
9496             }
9497
9498           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9499           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9500                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9501             {
9502               const_op = 0, op1 = const0_rtx;
9503               code = GE;
9504               break;
9505             }
9506           else
9507             break;
9508
9509         case LEU:
9510           /* unsigned <= 0 is equivalent to == 0 */
9511           if (const_op == 0)
9512             code = EQ;
9513
9514           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9515           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9516                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9517             {
9518               const_op = 0, op1 = const0_rtx;
9519               code = GE;
9520             }
9521           break;
9522
9523         case GEU:
9524           /* >= C is equivalent to < (C - 1).  */
9525           if (const_op > 1)
9526             {
9527               const_op -= 1;
9528               op1 = GEN_INT (const_op);
9529               code = GTU;
9530               /* ... fall through ...  */
9531             }
9532
9533           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9534           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9535                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9536             {
9537               const_op = 0, op1 = const0_rtx;
9538               code = LT;
9539               break;
9540             }
9541           else
9542             break;
9543
9544         case GTU:
9545           /* unsigned > 0 is equivalent to != 0 */
9546           if (const_op == 0)
9547             code = NE;
9548
9549           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9550           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9551                     && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9552             {
9553               const_op = 0, op1 = const0_rtx;
9554               code = LT;
9555             }
9556           break;
9557
9558         default:
9559           break;
9560         }
9561
9562       /* Compute some predicates to simplify code below.  */
9563
9564       equality_comparison_p = (code == EQ || code == NE);
9565       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9566       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9567                                || code == LEU);
9568
9569       /* If this is a sign bit comparison and we can do arithmetic in
9570          MODE, say that we will only be needing the sign bit of OP0.  */
9571       if (sign_bit_comparison_p
9572           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9573         op0 = force_to_mode (op0, mode,
9574                              ((HOST_WIDE_INT) 1
9575                               << (GET_MODE_BITSIZE (mode) - 1)),
9576                              NULL_RTX, 0);
9577
9578       /* Now try cases based on the opcode of OP0.  If none of the cases
9579          does a "continue", we exit this loop immediately after the
9580          switch.  */
9581
9582       switch (GET_CODE (op0))
9583         {
9584         case ZERO_EXTRACT:
9585           /* If we are extracting a single bit from a variable position in
9586              a constant that has only a single bit set and are comparing it
9587              with zero, we can convert this into an equality comparison
9588              between the position and the location of the single bit.  */
9589
9590           if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9591               && XEXP (op0, 1) == const1_rtx
9592               && equality_comparison_p && const_op == 0
9593               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9594             {
9595               if (BITS_BIG_ENDIAN)
9596 #ifdef HAVE_extzv
9597                 i = (GET_MODE_BITSIZE
9598                      (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9599 #else
9600                 i = BITS_PER_WORD - 1 - i;
9601 #endif
9602
9603               op0 = XEXP (op0, 2);
9604               op1 = GEN_INT (i);
9605               const_op = i;
9606
9607               /* Result is nonzero iff shift count is equal to I.  */
9608               code = reverse_condition (code);
9609               continue;
9610             }
9611
9612           /* ... fall through ...  */
9613
9614         case SIGN_EXTRACT:
9615           tem = expand_compound_operation (op0);
9616           if (tem != op0)
9617             {
9618               op0 = tem;
9619               continue;
9620             }
9621           break;
9622
9623         case NOT:
9624           /* If testing for equality, we can take the NOT of the constant.  */
9625           if (equality_comparison_p
9626               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9627             {
9628               op0 = XEXP (op0, 0);
9629               op1 = tem;
9630               continue;
9631             }
9632
9633           /* If just looking at the sign bit, reverse the sense of the
9634              comparison.  */
9635           if (sign_bit_comparison_p)
9636             {
9637               op0 = XEXP (op0, 0);
9638               code = (code == GE ? LT : GE);
9639               continue;
9640             }
9641           break;
9642
9643         case NEG:
9644           /* If testing for equality, we can take the NEG of the constant.  */
9645           if (equality_comparison_p
9646               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9647             {
9648               op0 = XEXP (op0, 0);
9649               op1 = tem;
9650               continue;
9651             }
9652
9653           /* The remaining cases only apply to comparisons with zero.  */
9654           if (const_op != 0)
9655             break;
9656
9657           /* When X is ABS or is known positive,
9658              (neg X) is < 0 if and only if X != 0.  */
9659
9660           if (sign_bit_comparison_p
9661               && (GET_CODE (XEXP (op0, 0)) == ABS
9662                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9663                       && (nonzero_bits (XEXP (op0, 0), mode)
9664                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9665             {
9666               op0 = XEXP (op0, 0);
9667               code = (code == LT ? NE : EQ);
9668               continue;
9669             }
9670
9671           /* If we have NEG of something whose two high-order bits are the
9672              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9673           if (num_sign_bit_copies (op0, mode) >= 2)
9674             {
9675               op0 = XEXP (op0, 0);
9676               code = swap_condition (code);
9677               continue;
9678             }
9679           break;
9680
9681         case ROTATE:
9682           /* If we are testing equality and our count is a constant, we
9683              can perform the inverse operation on our RHS.  */
9684           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9685               && (tem = simplify_binary_operation (ROTATERT, mode,
9686                                                    op1, XEXP (op0, 1))) != 0)
9687             {
9688               op0 = XEXP (op0, 0);
9689               op1 = tem;
9690               continue;
9691             }
9692
9693           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9694              a particular bit.  Convert it to an AND of a constant of that
9695              bit.  This will be converted into a ZERO_EXTRACT.  */
9696           if (const_op == 0 && sign_bit_comparison_p
9697               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9698               && mode_width <= HOST_BITS_PER_WIDE_INT)
9699             {
9700               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9701                                             ((HOST_WIDE_INT) 1
9702                                              << (mode_width - 1
9703                                                  - INTVAL (XEXP (op0, 1)))));
9704               code = (code == LT ? NE : EQ);
9705               continue;
9706             }
9707
9708           /* ... fall through ...  */
9709
9710         case ABS:
9711           /* ABS is ignorable inside an equality comparison with zero.  */
9712           if (const_op == 0 && equality_comparison_p)
9713             {
9714               op0 = XEXP (op0, 0);
9715               continue;
9716             }
9717           break;
9718
9719
9720         case SIGN_EXTEND:
9721           /* Can simplify (compare (zero/sign_extend FOO) CONST)
9722              to (compare FOO CONST) if CONST fits in FOO's mode and we
9723              are either testing inequality or have an unsigned comparison
9724              with ZERO_EXTEND or a signed comparison with SIGN_EXTEND.  */
9725           if (! unsigned_comparison_p
9726               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9727                   <= HOST_BITS_PER_WIDE_INT)
9728               && ((unsigned HOST_WIDE_INT) const_op
9729                   < (((HOST_WIDE_INT) 1
9730                       << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9731             {
9732               op0 = XEXP (op0, 0);
9733               continue;
9734             }
9735           break;
9736
9737         case SUBREG:
9738           /* Check for the case where we are comparing A - C1 with C2,
9739              both constants are smaller than 1/2 the maximum positive
9740              value in MODE, and the comparison is equality or unsigned.
9741              In that case, if A is either zero-extended to MODE or has
9742              sufficient sign bits so that the high-order bit in MODE
9743              is a copy of the sign in the inner mode, we can prove that it is
9744              safe to do the operation in the wider mode.  This simplifies
9745              many range checks.  */
9746
9747           if (mode_width <= HOST_BITS_PER_WIDE_INT
9748               && subreg_lowpart_p (op0)
9749               && GET_CODE (SUBREG_REG (op0)) == PLUS
9750               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9751               && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9752               && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9753                   < GET_MODE_MASK (mode) / 2)
9754               && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9755               && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9756                                       GET_MODE (SUBREG_REG (op0)))
9757                         & ~ GET_MODE_MASK (mode))
9758                   || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9759                                            GET_MODE (SUBREG_REG (op0)))
9760                       > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9761                          - GET_MODE_BITSIZE (mode)))))
9762             {
9763               op0 = SUBREG_REG (op0);
9764               continue;
9765             }
9766
9767           /* If the inner mode is narrower and we are extracting the low part,
9768              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
9769           if (subreg_lowpart_p (op0)
9770               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9771             /* Fall through */ ;
9772           else
9773             break;
9774
9775           /* ... fall through ...  */
9776
9777         case ZERO_EXTEND:
9778           if ((unsigned_comparison_p || equality_comparison_p)
9779               && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9780                   <= HOST_BITS_PER_WIDE_INT)
9781               && ((unsigned HOST_WIDE_INT) const_op
9782                   < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9783             {
9784               op0 = XEXP (op0, 0);
9785               continue;
9786             }
9787           break;
9788
9789         case PLUS:
9790           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
9791              this for equality comparisons due to pathological cases involving
9792              overflows.  */
9793           if (equality_comparison_p
9794               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9795                                                         op1, XEXP (op0, 1))))
9796             {
9797               op0 = XEXP (op0, 0);
9798               op1 = tem;
9799               continue;
9800             }
9801
9802           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
9803           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9804               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9805             {
9806               op0 = XEXP (XEXP (op0, 0), 0);
9807               code = (code == LT ? EQ : NE);
9808               continue;
9809             }
9810           break;
9811
9812         case MINUS:
9813           /* (eq (minus A B) C) -> (eq A (plus B C)) or
9814              (eq B (minus A C)), whichever simplifies.  We can only do
9815              this for equality comparisons due to pathological cases involving
9816              overflows.  */
9817           if (equality_comparison_p
9818               && 0 != (tem = simplify_binary_operation (PLUS, mode,
9819                                                         XEXP (op0, 1), op1)))
9820             {
9821               op0 = XEXP (op0, 0);
9822               op1 = tem;
9823               continue;
9824             }
9825
9826           if (equality_comparison_p
9827               && 0 != (tem = simplify_binary_operation (MINUS, mode,
9828                                                         XEXP (op0, 0), op1)))
9829             {
9830               op0 = XEXP (op0, 1);
9831               op1 = tem;
9832               continue;
9833             }
9834
9835           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9836              of bits in X minus 1, is one iff X > 0.  */
9837           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9838               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9839               && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9840               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9841             {
9842               op0 = XEXP (op0, 1);
9843               code = (code == GE ? LE : GT);
9844               continue;
9845             }
9846           break;
9847
9848         case XOR:
9849           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
9850              if C is zero or B is a constant.  */
9851           if (equality_comparison_p
9852               && 0 != (tem = simplify_binary_operation (XOR, mode,
9853                                                         XEXP (op0, 1), op1)))
9854             {
9855               op0 = XEXP (op0, 0);
9856               op1 = tem;
9857               continue;
9858             }
9859           break;
9860
9861         case EQ:  case NE:
9862         case LT:  case LTU:  case LE:  case LEU:
9863         case GT:  case GTU:  case GE:  case GEU:
9864           /* We can't do anything if OP0 is a condition code value, rather
9865              than an actual data value.  */
9866           if (const_op != 0
9867 #ifdef HAVE_cc0
9868               || XEXP (op0, 0) == cc0_rtx
9869 #endif
9870               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9871             break;
9872
9873           /* Get the two operands being compared.  */
9874           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9875             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9876           else
9877             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9878
9879           /* Check for the cases where we simply want the result of the
9880              earlier test or the opposite of that result.  */
9881           if (code == NE
9882               || (code == EQ && reversible_comparison_p (op0))
9883               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9884                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9885                   && (STORE_FLAG_VALUE
9886                       & (((HOST_WIDE_INT) 1
9887                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9888                   && (code == LT
9889                       || (code == GE && reversible_comparison_p (op0)))))
9890             {
9891               code = (code == LT || code == NE
9892                       ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9893               op0 = tem, op1 = tem1;
9894               continue;
9895             }
9896           break;
9897
9898         case IOR:
9899           /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9900              iff X <= 0.  */
9901           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9902               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9903               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9904             {
9905               op0 = XEXP (op0, 1);
9906               code = (code == GE ? GT : LE);
9907               continue;
9908             }
9909           break;
9910
9911         case AND:
9912           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
9913              will be converted to a ZERO_EXTRACT later.  */
9914           if (const_op == 0 && equality_comparison_p
9915               && GET_CODE (XEXP (op0, 0)) == ASHIFT
9916               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9917             {
9918               op0 = simplify_and_const_int
9919                 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9920                                              XEXP (op0, 1),
9921                                              XEXP (XEXP (op0, 0), 1)),
9922                  (HOST_WIDE_INT) 1);
9923               continue;
9924             }
9925
9926           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9927              zero and X is a comparison and C1 and C2 describe only bits set
9928              in STORE_FLAG_VALUE, we can compare with X.  */
9929           if (const_op == 0 && equality_comparison_p
9930               && mode_width <= HOST_BITS_PER_WIDE_INT
9931               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9932               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9933               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9934               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9935               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9936             {
9937               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9938                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
9939               if ((~ STORE_FLAG_VALUE & mask) == 0
9940                   && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9941                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9942                           && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9943                 {
9944                   op0 = XEXP (XEXP (op0, 0), 0);
9945                   continue;
9946                 }
9947             }
9948
9949           /* If we are doing an equality comparison of an AND of a bit equal
9950              to the sign bit, replace this with a LT or GE comparison of
9951              the underlying value.  */
9952           if (equality_comparison_p
9953               && const_op == 0
9954               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9955               && mode_width <= HOST_BITS_PER_WIDE_INT
9956               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9957                   == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9958             {
9959               op0 = XEXP (op0, 0);
9960               code = (code == EQ ? GE : LT);
9961               continue;
9962             }
9963
9964           /* If this AND operation is really a ZERO_EXTEND from a narrower
9965              mode, the constant fits within that mode, and this is either an
9966              equality or unsigned comparison, try to do this comparison in
9967              the narrower mode.  */
9968           if ((equality_comparison_p || unsigned_comparison_p)
9969               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9970               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9971                                    & GET_MODE_MASK (mode))
9972                                   + 1)) >= 0
9973               && const_op >> i == 0
9974               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9975             {
9976               op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9977               continue;
9978             }
9979           break;
9980
9981         case ASHIFT:
9982           /* If we have (compare (ashift FOO N) (const_int C)) and
9983              the high order N bits of FOO (N+1 if an inequality comparison)
9984              are known to be zero, we can do this by comparing FOO with C
9985              shifted right N bits so long as the low-order N bits of C are
9986              zero.  */
9987           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9988               && INTVAL (XEXP (op0, 1)) >= 0
9989               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9990                   < HOST_BITS_PER_WIDE_INT)
9991               && ((const_op
9992                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9993               && mode_width <= HOST_BITS_PER_WIDE_INT
9994               && (nonzero_bits (XEXP (op0, 0), mode)
9995                   & ~ (mask >> (INTVAL (XEXP (op0, 1))
9996                                 + ! equality_comparison_p))) == 0)
9997             {
9998               const_op >>= INTVAL (XEXP (op0, 1));
9999               op1 = GEN_INT (const_op);
10000               op0 = XEXP (op0, 0);
10001               continue;
10002             }
10003
10004           /* If we are doing a sign bit comparison, it means we are testing
10005              a particular bit.  Convert it to the appropriate AND.  */
10006           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10007               && mode_width <= HOST_BITS_PER_WIDE_INT)
10008             {
10009               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10010                                             ((HOST_WIDE_INT) 1
10011                                              << (mode_width - 1
10012                                                  - INTVAL (XEXP (op0, 1)))));
10013               code = (code == LT ? NE : EQ);
10014               continue;
10015             }
10016
10017           /* If this an equality comparison with zero and we are shifting
10018              the low bit to the sign bit, we can convert this to an AND of the
10019              low-order bit.  */
10020           if (const_op == 0 && equality_comparison_p
10021               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10022               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10023             {
10024               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10025                                             (HOST_WIDE_INT) 1);
10026               continue;
10027             }
10028           break;
10029
10030         case ASHIFTRT:
10031           /* If this is an equality comparison with zero, we can do this
10032              as a logical shift, which might be much simpler.  */
10033           if (equality_comparison_p && const_op == 0
10034               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10035             {
10036               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10037                                           XEXP (op0, 0),
10038                                           INTVAL (XEXP (op0, 1)));
10039               continue;
10040             }
10041
10042           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10043              do the comparison in a narrower mode.  */
10044           if (! unsigned_comparison_p
10045               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10046               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10047               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10048               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10049                                          MODE_INT, 1)) != BLKmode
10050               && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10051                   || ((unsigned HOST_WIDE_INT) - const_op
10052                       <= GET_MODE_MASK (tmode))))
10053             {
10054               op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10055               continue;
10056             }
10057
10058           /* ... fall through ...  */
10059         case LSHIFTRT:
10060           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10061              the low order N bits of FOO are known to be zero, we can do this
10062              by comparing FOO with C shifted left N bits so long as no
10063              overflow occurs.  */
10064           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10065               && INTVAL (XEXP (op0, 1)) >= 0
10066               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10067               && mode_width <= HOST_BITS_PER_WIDE_INT
10068               && (nonzero_bits (XEXP (op0, 0), mode)
10069                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10070               && (const_op == 0
10071                   || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10072                       < mode_width)))
10073             {
10074               const_op <<= INTVAL (XEXP (op0, 1));
10075               op1 = GEN_INT (const_op);
10076               op0 = XEXP (op0, 0);
10077               continue;
10078             }
10079
10080           /* If we are using this shift to extract just the sign bit, we
10081              can replace this with an LT or GE comparison.  */
10082           if (const_op == 0
10083               && (equality_comparison_p || sign_bit_comparison_p)
10084               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10085               && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10086             {
10087               op0 = XEXP (op0, 0);
10088               code = (code == NE || code == GT ? LT : GE);
10089               continue;
10090             }
10091           break;
10092
10093         default:
10094           break;
10095         }
10096
10097       break;
10098     }
10099
10100   /* Now make any compound operations involved in this comparison.  Then,
10101      check for an outmost SUBREG on OP0 that isn't doing anything or is
10102      paradoxical.  The latter case can only occur when it is known that the
10103      "extra" bits will be zero.  Therefore, it is safe to remove the SUBREG.
10104      We can never remove a SUBREG for a non-equality comparison because the
10105      sign bit is in a different place in the underlying object.  */
10106
10107   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10108   op1 = make_compound_operation (op1, SET);
10109
10110   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10111       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10112       && (code == NE || code == EQ)
10113       && ((GET_MODE_SIZE (GET_MODE (op0))
10114            > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10115     {
10116       op0 = SUBREG_REG (op0);
10117       op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10118     }
10119
10120   else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10121            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10122            && (code == NE || code == EQ)
10123            && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10124                <= HOST_BITS_PER_WIDE_INT)
10125            && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10126                & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10127            && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10128                                               op1),
10129                (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10130                 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10131     op0 = SUBREG_REG (op0), op1 = tem;
10132
10133   /* We now do the opposite procedure: Some machines don't have compare
10134      insns in all modes.  If OP0's mode is an integer mode smaller than a
10135      word and we can't do a compare in that mode, see if there is a larger
10136      mode for which we can do the compare.  There are a number of cases in
10137      which we can use the wider mode.  */
10138
10139   mode = GET_MODE (op0);
10140   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10141       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10142       && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10143     for (tmode = GET_MODE_WIDER_MODE (mode);
10144          (tmode != VOIDmode
10145           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10146          tmode = GET_MODE_WIDER_MODE (tmode))
10147       if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10148         {
10149           /* If the only nonzero bits in OP0 and OP1 are those in the
10150              narrower mode and this is an equality or unsigned comparison,
10151              we can use the wider mode.  Similarly for sign-extended
10152              values, in which case it is true for all comparisons.  */
10153           if (((code == EQ || code == NE
10154                 || code == GEU || code == GTU || code == LEU || code == LTU)
10155                && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10156                && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10157               || ((num_sign_bit_copies (op0, tmode)
10158                    > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10159                   && (num_sign_bit_copies (op1, tmode)
10160                       > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10161             {
10162               op0 = gen_lowpart_for_combine (tmode, op0);
10163               op1 = gen_lowpart_for_combine (tmode, op1);
10164               break;
10165             }
10166
10167           /* If this is a test for negative, we can make an explicit
10168              test of the sign bit.  */
10169
10170           if (op1 == const0_rtx && (code == LT || code == GE)
10171               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10172             {
10173               op0 = gen_binary (AND, tmode,
10174                                 gen_lowpart_for_combine (tmode, op0),
10175                                 GEN_INT ((HOST_WIDE_INT) 1
10176                                          << (GET_MODE_BITSIZE (mode) - 1)));
10177               code = (code == LT) ? NE : EQ;
10178               break;
10179             }
10180         }
10181
10182 #ifdef CANONICALIZE_COMPARISON
10183   /* If this machine only supports a subset of valid comparisons, see if we
10184      can convert an unsupported one into a supported one.  */
10185   CANONICALIZE_COMPARISON (code, op0, op1);
10186 #endif
10187
10188   *pop0 = op0;
10189   *pop1 = op1;
10190
10191   return code;
10192 }
10193 \f
10194 /* Return 1 if we know that X, a comparison operation, is not operating
10195    on a floating-point value or is EQ or NE, meaning that we can safely
10196    reverse it.  */
10197
10198 static int
10199 reversible_comparison_p (x)
10200      rtx x;
10201 {
10202   if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10203       || flag_fast_math
10204       || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10205     return 1;
10206
10207   switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10208     {
10209     case MODE_INT:
10210     case MODE_PARTIAL_INT:
10211     case MODE_COMPLEX_INT:
10212       return 1;
10213
10214     case MODE_CC:
10215       /* If the mode of the condition codes tells us that this is safe,
10216          we need look no further.  */
10217       if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10218         return 1;
10219
10220       /* Otherwise try and find where the condition codes were last set and
10221          use that.  */
10222       x = get_last_value (XEXP (x, 0));
10223       return (x && GET_CODE (x) == COMPARE
10224               && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10225
10226     default:
10227       return 0;
10228     }
10229 }
10230 \f
10231 /* Utility function for following routine.  Called when X is part of a value
10232    being stored into reg_last_set_value.  Sets reg_last_set_table_tick
10233    for each register mentioned.  Similar to mention_regs in cse.c  */
10234
10235 static void
10236 update_table_tick (x)
10237      rtx x;
10238 {
10239   register enum rtx_code code = GET_CODE (x);
10240   register char *fmt = GET_RTX_FORMAT (code);
10241   register int i;
10242
10243   if (code == REG)
10244     {
10245       int regno = REGNO (x);
10246       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10247                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10248
10249       for (i = regno; i < endregno; i++)
10250         reg_last_set_table_tick[i] = label_tick;
10251
10252       return;
10253     }
10254
10255   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10256     /* Note that we can't have an "E" in values stored; see
10257        get_last_value_validate.  */
10258     if (fmt[i] == 'e')
10259       update_table_tick (XEXP (x, i));
10260 }
10261
10262 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10263    are saying that the register is clobbered and we no longer know its
10264    value.  If INSN is zero, don't update reg_last_set; this is only permitted
10265    with VALUE also zero and is used to invalidate the register.  */
10266
10267 static void
10268 record_value_for_reg (reg, insn, value)
10269      rtx reg;
10270      rtx insn;
10271      rtx value;
10272 {
10273   int regno = REGNO (reg);
10274   int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10275                           ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10276   int i;
10277
10278   /* If VALUE contains REG and we have a previous value for REG, substitute
10279      the previous value.  */
10280   if (value && insn && reg_overlap_mentioned_p (reg, value))
10281     {
10282       rtx tem;
10283
10284       /* Set things up so get_last_value is allowed to see anything set up to
10285          our insn.  */
10286       subst_low_cuid = INSN_CUID (insn);
10287       tem = get_last_value (reg);
10288
10289       if (tem)
10290         value = replace_rtx (copy_rtx (value), reg, tem);
10291     }
10292
10293   /* For each register modified, show we don't know its value, that
10294      we don't know about its bitwise content, that its value has been
10295      updated, and that we don't know the location of the death of the
10296      register.  */
10297   for (i = regno; i < endregno; i ++)
10298     {
10299       if (insn)
10300         reg_last_set[i] = insn;
10301       reg_last_set_value[i] = 0;
10302       reg_last_set_mode[i] = 0;
10303       reg_last_set_nonzero_bits[i] = 0;
10304       reg_last_set_sign_bit_copies[i] = 0;
10305       reg_last_death[i] = 0;
10306     }
10307
10308   /* Mark registers that are being referenced in this value.  */
10309   if (value)
10310     update_table_tick (value);
10311
10312   /* Now update the status of each register being set.
10313      If someone is using this register in this block, set this register
10314      to invalid since we will get confused between the two lives in this
10315      basic block.  This makes using this register always invalid.  In cse, we
10316      scan the table to invalidate all entries using this register, but this
10317      is too much work for us.  */
10318
10319   for (i = regno; i < endregno; i++)
10320     {
10321       reg_last_set_label[i] = label_tick;
10322       if (value && reg_last_set_table_tick[i] == label_tick)
10323         reg_last_set_invalid[i] = 1;
10324       else
10325         reg_last_set_invalid[i] = 0;
10326     }
10327
10328   /* The value being assigned might refer to X (like in "x++;").  In that
10329      case, we must replace it with (clobber (const_int 0)) to prevent
10330      infinite loops.  */
10331   if (value && ! get_last_value_validate (&value, insn,
10332                                           reg_last_set_label[regno], 0))
10333     {
10334       value = copy_rtx (value);
10335       if (! get_last_value_validate (&value, insn,
10336                                      reg_last_set_label[regno], 1))
10337         value = 0;
10338     }
10339
10340   /* For the main register being modified, update the value, the mode, the
10341      nonzero bits, and the number of sign bit copies.  */
10342
10343   reg_last_set_value[regno] = value;
10344
10345   if (value)
10346     {
10347       subst_low_cuid = INSN_CUID (insn);
10348       reg_last_set_mode[regno] = GET_MODE (reg);
10349       reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10350       reg_last_set_sign_bit_copies[regno]
10351         = num_sign_bit_copies (value, GET_MODE (reg));
10352     }
10353 }
10354
10355 /* Used for communication between the following two routines.  */
10356 static rtx record_dead_insn;
10357
10358 /* Called via note_stores from record_dead_and_set_regs to handle one
10359    SET or CLOBBER in an insn.  */
10360
10361 static void
10362 record_dead_and_set_regs_1 (dest, setter)
10363      rtx dest, setter;
10364 {
10365   if (GET_CODE (dest) == SUBREG)
10366     dest = SUBREG_REG (dest);
10367
10368   if (GET_CODE (dest) == REG)
10369     {
10370       /* If we are setting the whole register, we know its value.  Otherwise
10371          show that we don't know the value.  We can handle SUBREG in
10372          some cases.  */
10373       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10374         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10375       else if (GET_CODE (setter) == SET
10376                && GET_CODE (SET_DEST (setter)) == SUBREG
10377                && SUBREG_REG (SET_DEST (setter)) == dest
10378                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10379                && subreg_lowpart_p (SET_DEST (setter)))
10380         record_value_for_reg (dest, record_dead_insn,
10381                               gen_lowpart_for_combine (GET_MODE (dest),
10382                                                        SET_SRC (setter)));
10383       else
10384         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10385     }
10386   else if (GET_CODE (dest) == MEM
10387            /* Ignore pushes, they clobber nothing.  */
10388            && ! push_operand (dest, GET_MODE (dest)))
10389     mem_last_set = INSN_CUID (record_dead_insn);
10390 }
10391
10392 /* Update the records of when each REG was most recently set or killed
10393    for the things done by INSN.  This is the last thing done in processing
10394    INSN in the combiner loop.
10395
10396    We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10397    reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10398    and also the similar information mem_last_set (which insn most recently
10399    modified memory) and last_call_cuid (which insn was the most recent
10400    subroutine call).  */
10401
10402 static void
10403 record_dead_and_set_regs (insn)
10404      rtx insn;
10405 {
10406   register rtx link;
10407   int i;
10408
10409   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10410     {
10411       if (REG_NOTE_KIND (link) == REG_DEAD
10412           && GET_CODE (XEXP (link, 0)) == REG)
10413         {
10414           int regno = REGNO (XEXP (link, 0));
10415           int endregno
10416             = regno + (regno < FIRST_PSEUDO_REGISTER
10417                        ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10418                        : 1);
10419
10420           for (i = regno; i < endregno; i++)
10421             reg_last_death[i] = insn;
10422         }
10423       else if (REG_NOTE_KIND (link) == REG_INC)
10424         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10425     }
10426
10427   if (GET_CODE (insn) == CALL_INSN)
10428     {
10429       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10430         if (call_used_regs[i])
10431           {
10432             reg_last_set_value[i] = 0;
10433             reg_last_set_mode[i] = 0;
10434             reg_last_set_nonzero_bits[i] = 0;
10435             reg_last_set_sign_bit_copies[i] = 0;
10436             reg_last_death[i] = 0;
10437           }
10438
10439       last_call_cuid = mem_last_set = INSN_CUID (insn);
10440     }
10441
10442   record_dead_insn = insn;
10443   note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10444 }
10445 \f
10446 /* Utility routine for the following function.  Verify that all the registers
10447    mentioned in *LOC are valid when *LOC was part of a value set when
10448    label_tick == TICK.  Return 0 if some are not.
10449
10450    If REPLACE is non-zero, replace the invalid reference with
10451    (clobber (const_int 0)) and return 1.  This replacement is useful because
10452    we often can get useful information about the form of a value (e.g., if
10453    it was produced by a shift that always produces -1 or 0) even though
10454    we don't know exactly what registers it was produced from.  */
10455
10456 static int
10457 get_last_value_validate (loc, insn, tick, replace)
10458      rtx *loc;
10459      rtx insn;
10460      int tick;
10461      int replace;
10462 {
10463   rtx x = *loc;
10464   char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10465   int len = GET_RTX_LENGTH (GET_CODE (x));
10466   int i;
10467
10468   if (GET_CODE (x) == REG)
10469     {
10470       int regno = REGNO (x);
10471       int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10472                               ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10473       int j;
10474
10475       for (j = regno; j < endregno; j++)
10476         if (reg_last_set_invalid[j]
10477             /* If this is a pseudo-register that was only set once, it is
10478                always valid.  */
10479             || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10480                 && reg_last_set_label[j] > tick))
10481           {
10482             if (replace)
10483               *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10484             return replace;
10485           }
10486
10487       return 1;
10488     }
10489   /* If this is a memory reference, make sure that there were
10490      no stores after it that might have clobbered the value.  We don't
10491      have alias info, so we assume any store invalidates it.  */
10492   else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10493            && INSN_CUID (insn) <= mem_last_set)
10494     {
10495       if (replace)
10496         *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10497       return replace;
10498     }
10499
10500   for (i = 0; i < len; i++)
10501     if ((fmt[i] == 'e'
10502          && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10503         /* Don't bother with these.  They shouldn't occur anyway.  */
10504         || fmt[i] == 'E')
10505       return 0;
10506
10507   /* If we haven't found a reason for it to be invalid, it is valid.  */
10508   return 1;
10509 }
10510
10511 /* Get the last value assigned to X, if known.  Some registers
10512    in the value may be replaced with (clobber (const_int 0)) if their value
10513    is known longer known reliably.  */
10514
10515 static rtx
10516 get_last_value (x)
10517      rtx x;
10518 {
10519   int regno;
10520   rtx value;
10521
10522   /* If this is a non-paradoxical SUBREG, get the value of its operand and
10523      then convert it to the desired mode.  If this is a paradoxical SUBREG,
10524      we cannot predict what values the "extra" bits might have.  */
10525   if (GET_CODE (x) == SUBREG
10526       && subreg_lowpart_p (x)
10527       && (GET_MODE_SIZE (GET_MODE (x))
10528           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10529       && (value = get_last_value (SUBREG_REG (x))) != 0)
10530     return gen_lowpart_for_combine (GET_MODE (x), value);
10531
10532   if (GET_CODE (x) != REG)
10533     return 0;
10534
10535   regno = REGNO (x);
10536   value = reg_last_set_value[regno];
10537
10538   /* If we don't have a value or if it isn't for this basic block,
10539      return 0.  */
10540
10541   if (value == 0
10542       || (REG_N_SETS (regno) != 1
10543           && reg_last_set_label[regno] != label_tick))
10544     return 0;
10545
10546   /* If the value was set in a later insn than the ones we are processing,
10547      we can't use it even if the register was only set once, but make a quick
10548      check to see if the previous insn set it to something.  This is commonly
10549      the case when the same pseudo is used by repeated insns.
10550
10551      This does not work if there exists an instruction which is temporarily
10552      not on the insn chain.  */
10553
10554   if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10555     {
10556       rtx insn, set;
10557
10558       /* We can not do anything useful in this case, because there is
10559          an instruction which is not on the insn chain.  */
10560       if (subst_prev_insn)
10561         return 0;
10562
10563       /* Skip over USE insns.  They are not useful here, and they may have
10564          been made by combine, in which case they do not have a INSN_CUID
10565          value.  We can't use prev_real_insn, because that would incorrectly
10566          take us backwards across labels.  Skip over BARRIERs also, since
10567          they could have been made by combine.  If we see one, we must be
10568          optimizing dead code, so it doesn't matter what we do.  */
10569       for (insn = prev_nonnote_insn (subst_insn);
10570            insn && ((GET_CODE (insn) == INSN
10571                      && GET_CODE (PATTERN (insn)) == USE)
10572                     || GET_CODE (insn) == BARRIER
10573                     || INSN_CUID (insn) >= subst_low_cuid);
10574            insn = prev_nonnote_insn (insn))
10575         ;
10576
10577       if (insn
10578           && (set = single_set (insn)) != 0
10579           && rtx_equal_p (SET_DEST (set), x))
10580         {
10581           value = SET_SRC (set);
10582
10583           /* Make sure that VALUE doesn't reference X.  Replace any
10584              explicit references with a CLOBBER.  If there are any remaining
10585              references (rare), don't use the value.  */
10586
10587           if (reg_mentioned_p (x, value))
10588             value = replace_rtx (copy_rtx (value), x,
10589                                  gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10590
10591           if (reg_overlap_mentioned_p (x, value))
10592             return 0;
10593         }
10594       else
10595         return 0;
10596     }
10597
10598   /* If the value has all its registers valid, return it.  */
10599   if (get_last_value_validate (&value, reg_last_set[regno],
10600                                reg_last_set_label[regno], 0))
10601     return value;
10602
10603   /* Otherwise, make a copy and replace any invalid register with
10604      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
10605
10606   value = copy_rtx (value);
10607   if (get_last_value_validate (&value, reg_last_set[regno],
10608                                reg_last_set_label[regno], 1))
10609     return value;
10610
10611   return 0;
10612 }
10613 \f
10614 /* Return nonzero if expression X refers to a REG or to memory
10615    that is set in an instruction more recent than FROM_CUID.  */
10616
10617 static int
10618 use_crosses_set_p (x, from_cuid)
10619      register rtx x;
10620      int from_cuid;
10621 {
10622   register char *fmt;
10623   register int i;
10624   register enum rtx_code code = GET_CODE (x);
10625
10626   if (code == REG)
10627     {
10628       register int regno = REGNO (x);
10629       int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10630                             ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10631
10632 #ifdef PUSH_ROUNDING
10633       /* Don't allow uses of the stack pointer to be moved,
10634          because we don't know whether the move crosses a push insn.  */
10635       if (regno == STACK_POINTER_REGNUM)
10636         return 1;
10637 #endif
10638       for (;regno < endreg; regno++)
10639         if (reg_last_set[regno]
10640             && INSN_CUID (reg_last_set[regno]) > from_cuid)
10641           return 1;
10642       return 0;
10643     }
10644
10645   if (code == MEM && mem_last_set > from_cuid)
10646     return 1;
10647
10648   fmt = GET_RTX_FORMAT (code);
10649
10650   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10651     {
10652       if (fmt[i] == 'E')
10653         {
10654           register int j;
10655           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10656             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10657               return 1;
10658         }
10659       else if (fmt[i] == 'e'
10660                && use_crosses_set_p (XEXP (x, i), from_cuid))
10661         return 1;
10662     }
10663   return 0;
10664 }
10665 \f
10666 /* Define three variables used for communication between the following
10667    routines.  */
10668
10669 static int reg_dead_regno, reg_dead_endregno;
10670 static int reg_dead_flag;
10671
10672 /* Function called via note_stores from reg_dead_at_p.
10673
10674    If DEST is within [reg_dead_regno, reg_dead_endregno), set
10675    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
10676
10677 static void
10678 reg_dead_at_p_1 (dest, x)
10679      rtx dest;
10680      rtx x;
10681 {
10682   int regno, endregno;
10683
10684   if (GET_CODE (dest) != REG)
10685     return;
10686
10687   regno = REGNO (dest);
10688   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10689                       ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10690
10691   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10692     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10693 }
10694
10695 /* Return non-zero if REG is known to be dead at INSN.
10696
10697    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
10698    referencing REG, it is dead.  If we hit a SET referencing REG, it is
10699    live.  Otherwise, see if it is live or dead at the start of the basic
10700    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
10701    must be assumed to be always live.  */
10702
10703 static int
10704 reg_dead_at_p (reg, insn)
10705      rtx reg;
10706      rtx insn;
10707 {
10708   int block, i;
10709
10710   /* Set variables for reg_dead_at_p_1.  */
10711   reg_dead_regno = REGNO (reg);
10712   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10713                                         ? HARD_REGNO_NREGS (reg_dead_regno,
10714                                                             GET_MODE (reg))
10715                                         : 1);
10716
10717   reg_dead_flag = 0;
10718
10719   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  */
10720   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10721     {
10722       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10723         if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10724           return 0;
10725     }
10726
10727   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10728      beginning of function.  */
10729   for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10730        insn = prev_nonnote_insn (insn))
10731     {
10732       note_stores (PATTERN (insn), reg_dead_at_p_1);
10733       if (reg_dead_flag)
10734         return reg_dead_flag == 1 ? 1 : 0;
10735
10736       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10737         return 1;
10738     }
10739
10740   /* Get the basic block number that we were in.  */
10741   if (insn == 0)
10742     block = 0;
10743   else
10744     {
10745       for (block = 0; block < n_basic_blocks; block++)
10746         if (insn == basic_block_head[block])
10747           break;
10748
10749       if (block == n_basic_blocks)
10750         return 0;
10751     }
10752
10753   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10754     if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10755       return 0;
10756
10757   return 1;
10758 }
10759 \f
10760 /* Note hard registers in X that are used.  This code is similar to
10761    that in flow.c, but much simpler since we don't care about pseudos.  */
10762
10763 static void
10764 mark_used_regs_combine (x)
10765      rtx x;
10766 {
10767   register RTX_CODE code = GET_CODE (x);
10768   register int regno;
10769   int i;
10770
10771   switch (code)
10772     {
10773     case LABEL_REF:
10774     case SYMBOL_REF:
10775     case CONST_INT:
10776     case CONST:
10777     case CONST_DOUBLE:
10778     case PC:
10779     case ADDR_VEC:
10780     case ADDR_DIFF_VEC:
10781     case ASM_INPUT:
10782 #ifdef HAVE_cc0
10783     /* CC0 must die in the insn after it is set, so we don't need to take
10784        special note of it here.  */
10785     case CC0:
10786 #endif
10787       return;
10788
10789     case CLOBBER:
10790       /* If we are clobbering a MEM, mark any hard registers inside the
10791          address as used.  */
10792       if (GET_CODE (XEXP (x, 0)) == MEM)
10793         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10794       return;
10795
10796     case REG:
10797       regno = REGNO (x);
10798       /* A hard reg in a wide mode may really be multiple registers.
10799          If so, mark all of them just like the first.  */
10800       if (regno < FIRST_PSEUDO_REGISTER)
10801         {
10802           /* None of this applies to the stack, frame or arg pointers */
10803           if (regno == STACK_POINTER_REGNUM
10804 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10805               || regno == HARD_FRAME_POINTER_REGNUM
10806 #endif
10807 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10808               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10809 #endif
10810               || regno == FRAME_POINTER_REGNUM)
10811             return;
10812
10813           i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10814           while (i-- > 0)
10815             SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10816         }
10817       return;
10818
10819     case SET:
10820       {
10821         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10822            the address.  */
10823         register rtx testreg = SET_DEST (x);
10824
10825         while (GET_CODE (testreg) == SUBREG
10826                || GET_CODE (testreg) == ZERO_EXTRACT
10827                || GET_CODE (testreg) == SIGN_EXTRACT
10828                || GET_CODE (testreg) == STRICT_LOW_PART)
10829           testreg = XEXP (testreg, 0);
10830
10831         if (GET_CODE (testreg) == MEM)
10832           mark_used_regs_combine (XEXP (testreg, 0));
10833
10834         mark_used_regs_combine (SET_SRC (x));
10835       }
10836       return;
10837
10838     default:
10839       break;
10840     }
10841
10842   /* Recursively scan the operands of this expression.  */
10843
10844   {
10845     register char *fmt = GET_RTX_FORMAT (code);
10846
10847     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10848       {
10849         if (fmt[i] == 'e')
10850           mark_used_regs_combine (XEXP (x, i));
10851         else if (fmt[i] == 'E')
10852           {
10853             register int j;
10854
10855             for (j = 0; j < XVECLEN (x, i); j++)
10856               mark_used_regs_combine (XVECEXP (x, i, j));
10857           }
10858       }
10859   }
10860 }
10861
10862 \f
10863 /* Remove register number REGNO from the dead registers list of INSN.
10864
10865    Return the note used to record the death, if there was one.  */
10866
10867 rtx
10868 remove_death (regno, insn)
10869      int regno;
10870      rtx insn;
10871 {
10872   register rtx note = find_regno_note (insn, REG_DEAD, regno);
10873
10874   if (note)
10875     {
10876       REG_N_DEATHS (regno)--;
10877       remove_note (insn, note);
10878     }
10879
10880   return note;
10881 }
10882
10883 /* For each register (hardware or pseudo) used within expression X, if its
10884    death is in an instruction with cuid between FROM_CUID (inclusive) and
10885    TO_INSN (exclusive), put a REG_DEAD note for that register in the
10886    list headed by PNOTES.
10887
10888    That said, don't move registers killed by maybe_kill_insn.
10889
10890    This is done when X is being merged by combination into TO_INSN.  These
10891    notes will then be distributed as needed.  */
10892
10893 static void
10894 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10895      rtx x;
10896      rtx maybe_kill_insn;
10897      int from_cuid;
10898      rtx to_insn;
10899      rtx *pnotes;
10900 {
10901   register char *fmt;
10902   register int len, i;
10903   register enum rtx_code code = GET_CODE (x);
10904
10905   if (code == REG)
10906     {
10907       register int regno = REGNO (x);
10908       register rtx where_dead = reg_last_death[regno];
10909       register rtx before_dead, after_dead;
10910
10911       /* Don't move the register if it gets killed in between from and to */
10912       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10913           && !reg_referenced_p (x, maybe_kill_insn))
10914         return;
10915
10916       /* WHERE_DEAD could be a USE insn made by combine, so first we
10917          make sure that we have insns with valid INSN_CUID values.  */
10918       before_dead = where_dead;
10919       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10920         before_dead = PREV_INSN (before_dead);
10921       after_dead = where_dead;
10922       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10923         after_dead = NEXT_INSN (after_dead);
10924
10925       if (before_dead && after_dead
10926           && INSN_CUID (before_dead) >= from_cuid
10927           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10928               || (where_dead != after_dead
10929                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10930         {
10931           rtx note = remove_death (regno, where_dead);
10932
10933           /* It is possible for the call above to return 0.  This can occur
10934              when reg_last_death points to I2 or I1 that we combined with.
10935              In that case make a new note.
10936
10937              We must also check for the case where X is a hard register
10938              and NOTE is a death note for a range of hard registers
10939              including X.  In that case, we must put REG_DEAD notes for
10940              the remaining registers in place of NOTE.  */
10941
10942           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10943               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10944                   > GET_MODE_SIZE (GET_MODE (x))))
10945             {
10946               int deadregno = REGNO (XEXP (note, 0));
10947               int deadend
10948                 = (deadregno + HARD_REGNO_NREGS (deadregno,
10949                                                  GET_MODE (XEXP (note, 0))));
10950               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10951               int i;
10952
10953               for (i = deadregno; i < deadend; i++)
10954                 if (i < regno || i >= ourend)
10955                   REG_NOTES (where_dead)
10956                     = gen_rtx (EXPR_LIST, REG_DEAD,
10957                                gen_rtx (REG, reg_raw_mode[i], i),
10958                                REG_NOTES (where_dead));
10959             }
10960           /* If we didn't find any note, or if we found a REG_DEAD note that
10961              covers only part of the given reg, and we have a multi-reg hard
10962              register, then to be safe we must check for REG_DEAD notes
10963              for each register other than the first.  They could have
10964              their own REG_DEAD notes lying around.  */
10965           else if ((note == 0
10966                     || (note != 0
10967                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10968                             < GET_MODE_SIZE (GET_MODE (x)))))
10969                    && regno < FIRST_PSEUDO_REGISTER
10970                    && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10971             {
10972               int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10973               int i, offset;
10974               rtx oldnotes = 0;
10975
10976               if (note)
10977                 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
10978               else
10979                 offset = 1;
10980
10981               for (i = regno + offset; i < ourend; i++)
10982                 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10983                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10984             }
10985
10986           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10987             {
10988               XEXP (note, 1) = *pnotes;
10989               *pnotes = note;
10990             }
10991           else
10992             *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10993
10994           REG_N_DEATHS (regno)++;
10995         }
10996
10997       return;
10998     }
10999
11000   else if (GET_CODE (x) == SET)
11001     {
11002       rtx dest = SET_DEST (x);
11003
11004       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11005
11006       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11007          that accesses one word of a multi-word item, some
11008          piece of everything register in the expression is used by
11009          this insn, so remove any old death.  */
11010
11011       if (GET_CODE (dest) == ZERO_EXTRACT
11012           || GET_CODE (dest) == STRICT_LOW_PART
11013           || (GET_CODE (dest) == SUBREG
11014               && (((GET_MODE_SIZE (GET_MODE (dest))
11015                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11016                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11017                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11018         {
11019           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11020           return;
11021         }
11022
11023       /* If this is some other SUBREG, we know it replaces the entire
11024          value, so use that as the destination.  */
11025       if (GET_CODE (dest) == SUBREG)
11026         dest = SUBREG_REG (dest);
11027
11028       /* If this is a MEM, adjust deaths of anything used in the address.
11029          For a REG (the only other possibility), the entire value is
11030          being replaced so the old value is not used in this insn.  */
11031
11032       if (GET_CODE (dest) == MEM)
11033         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11034                      to_insn, pnotes);
11035       return;
11036     }
11037
11038   else if (GET_CODE (x) == CLOBBER)
11039     return;
11040
11041   len = GET_RTX_LENGTH (code);
11042   fmt = GET_RTX_FORMAT (code);
11043
11044   for (i = 0; i < len; i++)
11045     {
11046       if (fmt[i] == 'E')
11047         {
11048           register int j;
11049           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11050             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11051                          to_insn, pnotes);
11052         }
11053       else if (fmt[i] == 'e')
11054         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11055     }
11056 }
11057 \f
11058 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11059    pattern of an insn.  X must be a REG.  */
11060
11061 static int
11062 reg_bitfield_target_p (x, body)
11063      rtx x;
11064      rtx body;
11065 {
11066   int i;
11067
11068   if (GET_CODE (body) == SET)
11069     {
11070       rtx dest = SET_DEST (body);
11071       rtx target;
11072       int regno, tregno, endregno, endtregno;
11073
11074       if (GET_CODE (dest) == ZERO_EXTRACT)
11075         target = XEXP (dest, 0);
11076       else if (GET_CODE (dest) == STRICT_LOW_PART)
11077         target = SUBREG_REG (XEXP (dest, 0));
11078       else
11079         return 0;
11080
11081       if (GET_CODE (target) == SUBREG)
11082         target = SUBREG_REG (target);
11083
11084       if (GET_CODE (target) != REG)
11085         return 0;
11086
11087       tregno = REGNO (target), regno = REGNO (x);
11088       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11089         return target == x;
11090
11091       endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11092       endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11093
11094       return endregno > tregno && regno < endtregno;
11095     }
11096
11097   else if (GET_CODE (body) == PARALLEL)
11098     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11099       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11100         return 1;
11101
11102   return 0;
11103 }
11104 \f
11105 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11106    as appropriate.  I3 and I2 are the insns resulting from the combination
11107    insns including FROM (I2 may be zero).
11108
11109    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11110    not need REG_DEAD notes because they are being substituted for.  This
11111    saves searching in the most common cases.
11112
11113    Each note in the list is either ignored or placed on some insns, depending
11114    on the type of note.  */
11115
11116 static void
11117 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11118      rtx notes;
11119      rtx from_insn;
11120      rtx i3, i2;
11121      rtx elim_i2, elim_i1;
11122 {
11123   rtx note, next_note;
11124   rtx tem;
11125
11126   for (note = notes; note; note = next_note)
11127     {
11128       rtx place = 0, place2 = 0;
11129
11130       /* If this NOTE references a pseudo register, ensure it references
11131          the latest copy of that register.  */
11132       if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11133           && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11134         XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11135
11136       next_note = XEXP (note, 1);
11137       switch (REG_NOTE_KIND (note))
11138         {
11139         case REG_BR_PROB:
11140         case REG_EXEC_COUNT:
11141           /* Doesn't matter much where we put this, as long as it's somewhere.
11142              It is preferable to keep these notes on branches, which is most
11143              likely to be i3.  */
11144           place = i3;
11145           break;
11146
11147         case REG_UNUSED:
11148           /* Any clobbers for i3 may still exist, and so we must process
11149              REG_UNUSED notes from that insn.
11150
11151              Any clobbers from i2 or i1 can only exist if they were added by
11152              recog_for_combine.  In that case, recog_for_combine created the
11153              necessary REG_UNUSED notes.  Trying to keep any original
11154              REG_UNUSED notes from these insns can cause incorrect output
11155              if it is for the same register as the original i3 dest.
11156              In that case, we will notice that the register is set in i3,
11157              and then add a REG_UNUSED note for the destination of i3, which
11158              is wrong.  However, it is possible to have REG_UNUSED notes from
11159              i2 or i1 for register which were both used and clobbered, so
11160              we keep notes from i2 or i1 if they will turn into REG_DEAD
11161              notes.  */
11162
11163           /* If this register is set or clobbered in I3, put the note there
11164              unless there is one already.  */
11165           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11166             {
11167               if (from_insn != i3)
11168                 break;
11169
11170               if (! (GET_CODE (XEXP (note, 0)) == REG
11171                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11172                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11173                 place = i3;
11174             }
11175           /* Otherwise, if this register is used by I3, then this register
11176              now dies here, so we must put a REG_DEAD note here unless there
11177              is one already.  */
11178           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11179                    && ! (GET_CODE (XEXP (note, 0)) == REG
11180                          ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11181                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11182             {
11183               PUT_REG_NOTE_KIND (note, REG_DEAD);
11184               place = i3;
11185             }
11186           break;
11187
11188         case REG_EQUAL:
11189         case REG_EQUIV:
11190         case REG_NONNEG:
11191           /* These notes say something about results of an insn.  We can
11192              only support them if they used to be on I3 in which case they
11193              remain on I3.  Otherwise they are ignored.
11194
11195              If the note refers to an expression that is not a constant, we
11196              must also ignore the note since we cannot tell whether the
11197              equivalence is still true.  It might be possible to do
11198              slightly better than this (we only have a problem if I2DEST
11199              or I1DEST is present in the expression), but it doesn't
11200              seem worth the trouble.  */
11201
11202           if (from_insn == i3
11203               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11204             place = i3;
11205           break;
11206
11207         case REG_INC:
11208         case REG_NO_CONFLICT:
11209         case REG_LABEL:
11210           /* These notes say something about how a register is used.  They must
11211              be present on any use of the register in I2 or I3.  */
11212           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11213             place = i3;
11214
11215           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11216             {
11217               if (place)
11218                 place2 = i2;
11219               else
11220                 place = i2;
11221             }
11222           break;
11223
11224         case REG_WAS_0:
11225           /* It is too much trouble to try to see if this note is still
11226              correct in all situations.  It is better to simply delete it.  */
11227           break;
11228
11229         case REG_RETVAL:
11230           /* If the insn previously containing this note still exists,
11231              put it back where it was.  Otherwise move it to the previous
11232              insn.  Adjust the corresponding REG_LIBCALL note.  */
11233           if (GET_CODE (from_insn) != NOTE)
11234             place = from_insn;
11235           else
11236             {
11237               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11238               place = prev_real_insn (from_insn);
11239               if (tem && place)
11240                 XEXP (tem, 0) = place;
11241             }
11242           break;
11243
11244         case REG_LIBCALL:
11245           /* This is handled similarly to REG_RETVAL.  */
11246           if (GET_CODE (from_insn) != NOTE)
11247             place = from_insn;
11248           else
11249             {
11250               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11251               place = next_real_insn (from_insn);
11252               if (tem && place)
11253                 XEXP (tem, 0) = place;
11254             }
11255           break;
11256
11257         case REG_DEAD:
11258           /* If the register is used as an input in I3, it dies there.
11259              Similarly for I2, if it is non-zero and adjacent to I3.
11260
11261              If the register is not used as an input in either I3 or I2
11262              and it is not one of the registers we were supposed to eliminate,
11263              there are two possibilities.  We might have a non-adjacent I2
11264              or we might have somehow eliminated an additional register
11265              from a computation.  For example, we might have had A & B where
11266              we discover that B will always be zero.  In this case we will
11267              eliminate the reference to A.
11268
11269              In both cases, we must search to see if we can find a previous
11270              use of A and put the death note there.  */
11271
11272           if (from_insn
11273               && GET_CODE (from_insn) == CALL_INSN
11274               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11275             place = from_insn;
11276           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11277             place = i3;
11278           else if (i2 != 0 && next_nonnote_insn (i2) == i3
11279                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11280             place = i2;
11281
11282           if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11283             break;
11284
11285           /* If the register is used in both I2 and I3 and it dies in I3,
11286              we might have added another reference to it.  If reg_n_refs
11287              was 2, bump it to 3.  This has to be correct since the
11288              register must have been set somewhere.  The reason this is
11289              done is because local-alloc.c treats 2 references as a
11290              special case.  */
11291
11292           if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11293               && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11294               && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11295             REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11296
11297           if (place == 0)
11298             {
11299               for (tem = prev_nonnote_insn (i3);
11300                    place == 0 && tem
11301                    && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11302                    tem = prev_nonnote_insn (tem))
11303                 {
11304                   /* If the register is being set at TEM, see if that is all
11305                      TEM is doing.  If so, delete TEM.  Otherwise, make this
11306                      into a REG_UNUSED note instead.  */
11307                   if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11308                     {
11309                       rtx set = single_set (tem);
11310                       rtx inner_dest = 0;
11311
11312                       if (set != 0)
11313                         for (inner_dest = SET_DEST (set);
11314                              GET_CODE (inner_dest) == STRICT_LOW_PART
11315                              || GET_CODE (inner_dest) == SUBREG
11316                              || GET_CODE (inner_dest) == ZERO_EXTRACT;
11317                              inner_dest = XEXP (inner_dest, 0))
11318                           ;
11319
11320                       /* Verify that it was the set, and not a clobber that
11321                          modified the register.  */
11322
11323                       if (set != 0 && ! side_effects_p (SET_SRC (set))
11324                           && rtx_equal_p (XEXP (note, 0), inner_dest))
11325                         {
11326                           /* Move the notes and links of TEM elsewhere.
11327                              This might delete other dead insns recursively.
11328                              First set the pattern to something that won't use
11329                              any register.  */
11330
11331                           PATTERN (tem) = pc_rtx;
11332
11333                           distribute_notes (REG_NOTES (tem), tem, tem,
11334                                             NULL_RTX, NULL_RTX, NULL_RTX);
11335                           distribute_links (LOG_LINKS (tem));
11336
11337                           PUT_CODE (tem, NOTE);
11338                           NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11339                           NOTE_SOURCE_FILE (tem) = 0;
11340                         }
11341                       /* If the register is both set and used here, put the
11342                          REG_DEAD note here, but place a REG_UNUSED note
11343                          here too unless there already is one.  */
11344                       else if (reg_referenced_p (XEXP (note, 0),
11345                                                  PATTERN (tem)))
11346                         {
11347                           place = tem;
11348
11349                           if (! find_regno_note (tem, REG_UNUSED,
11350                                                  REGNO (XEXP (note, 0))))
11351                             REG_NOTES (tem)
11352                               = gen_rtx (EXPR_LIST, REG_UNUSED, XEXP (note, 0),
11353                                          REG_NOTES (tem));
11354                         }
11355                       else
11356                         {
11357                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
11358
11359                           /*  If there isn't already a REG_UNUSED note, put one
11360                               here.  */
11361                           if (! find_regno_note (tem, REG_UNUSED,
11362                                                  REGNO (XEXP (note, 0))))
11363                             place = tem;
11364                           break;
11365                       }
11366                   }
11367                 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11368                          || (GET_CODE (tem) == CALL_INSN
11369                              && find_reg_fusage (tem, USE, XEXP (note, 0))))
11370                   {
11371                     place = tem;
11372
11373                     /* If we are doing a 3->2 combination, and we have a
11374                        register which formerly died in i3 and was not used
11375                        by i2, which now no longer dies in i3 and is used in
11376                        i2 but does not die in i2, and place is between i2
11377                        and i3, then we may need to move a link from place to
11378                        i2.  */
11379                     if (i2 && INSN_UID (place) <= max_uid_cuid
11380                         && INSN_CUID (place) > INSN_CUID (i2)
11381                         && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11382                         && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11383                       {
11384                         rtx links = LOG_LINKS (place);
11385                         LOG_LINKS (place) = 0;
11386                         distribute_links (links);
11387                       }
11388                     break;
11389                   }
11390                 }
11391
11392               /* If we haven't found an insn for the death note and it
11393                  is still a REG_DEAD note, but we have hit a CODE_LABEL,
11394                  insert a USE insn for the register at that label and
11395                  put the death node there.  This prevents problems with
11396                  call-state tracking in caller-save.c.  */
11397               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11398                 {
11399                   place
11400                     = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11401                                        tem);
11402
11403                   /* If this insn was emitted between blocks, then update
11404                      basic_block_head of the current block to include it.  */
11405                   if (basic_block_end[this_basic_block - 1] == tem)
11406                     basic_block_head[this_basic_block] = place;
11407                 }
11408             }
11409
11410           /* If the register is set or already dead at PLACE, we needn't do
11411              anything with this note if it is still a REG_DEAD note.
11412              We can here if it is set at all, not if is it totally replace,
11413              which is what `dead_or_set_p' checks, so also check for it being
11414              set partially.  */
11415
11416
11417           if (place && REG_NOTE_KIND (note) == REG_DEAD)
11418             {
11419               int regno = REGNO (XEXP (note, 0));
11420
11421               if (dead_or_set_p (place, XEXP (note, 0))
11422                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11423                 {
11424                   /* Unless the register previously died in PLACE, clear
11425                      reg_last_death.  [I no longer understand why this is
11426                      being done.] */
11427                   if (reg_last_death[regno] != place)
11428                     reg_last_death[regno] = 0;
11429                   place = 0;
11430                 }
11431               else
11432                 reg_last_death[regno] = place;
11433
11434               /* If this is a death note for a hard reg that is occupying
11435                  multiple registers, ensure that we are still using all
11436                  parts of the object.  If we find a piece of the object
11437                  that is unused, we must add a USE for that piece before
11438                  PLACE and put the appropriate REG_DEAD note on it.
11439
11440                  An alternative would be to put a REG_UNUSED for the pieces
11441                  on the insn that set the register, but that can't be done if
11442                  it is not in the same block.  It is simpler, though less
11443                  efficient, to add the USE insns.  */
11444
11445               if (place && regno < FIRST_PSEUDO_REGISTER
11446                   && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11447                 {
11448                   int endregno
11449                     = regno + HARD_REGNO_NREGS (regno,
11450                                                 GET_MODE (XEXP (note, 0)));
11451                   int all_used = 1;
11452                   int i;
11453
11454                   for (i = regno; i < endregno; i++)
11455                     if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11456                         && ! find_regno_fusage (place, USE, i))
11457                       {
11458                         rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11459                         rtx p;
11460
11461                         /* See if we already placed a USE note for this
11462                            register in front of PLACE.  */
11463                         for (p = place;
11464                              GET_CODE (PREV_INSN (p)) == INSN
11465                              && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11466                              p = PREV_INSN (p))
11467                           if (rtx_equal_p (piece,
11468                                            XEXP (PATTERN (PREV_INSN (p)), 0)))
11469                             {
11470                               p = 0;
11471                               break;
11472                             }
11473
11474                         if (p)
11475                           {
11476                             rtx use_insn
11477                               = emit_insn_before (gen_rtx (USE, VOIDmode,
11478                                                            piece),
11479                                                   p);
11480                             REG_NOTES (use_insn)
11481                               = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11482                                          REG_NOTES (use_insn));
11483                           }
11484
11485                         all_used = 0;
11486                       }
11487
11488                   /* Check for the case where the register dying partially
11489                      overlaps the register set by this insn.  */
11490                   if (all_used)
11491                     for (i = regno; i < endregno; i++)
11492                       if (dead_or_set_regno_p (place, i))
11493                           {
11494                             all_used = 0;
11495                             break;
11496                           }
11497
11498                   if (! all_used)
11499                     {
11500                       /* Put only REG_DEAD notes for pieces that are
11501                          still used and that are not already dead or set.  */
11502
11503                       for (i = regno; i < endregno; i++)
11504                         {
11505                           rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11506
11507                           if ((reg_referenced_p (piece, PATTERN (place))
11508                                || (GET_CODE (place) == CALL_INSN
11509                                    && find_reg_fusage (place, USE, piece)))
11510                               && ! dead_or_set_p (place, piece)
11511                               && ! reg_bitfield_target_p (piece,
11512                                                           PATTERN (place)))
11513                             REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11514                                                          piece,
11515                                                          REG_NOTES (place));
11516                         }
11517
11518                       place = 0;
11519                     }
11520                 }
11521             }
11522           break;
11523
11524         default:
11525           /* Any other notes should not be present at this point in the
11526              compilation.  */
11527           abort ();
11528         }
11529
11530       if (place)
11531         {
11532           XEXP (note, 1) = REG_NOTES (place);
11533           REG_NOTES (place) = note;
11534         }
11535       else if ((REG_NOTE_KIND (note) == REG_DEAD
11536                 || REG_NOTE_KIND (note) == REG_UNUSED)
11537                && GET_CODE (XEXP (note, 0)) == REG)
11538         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11539
11540       if (place2)
11541         {
11542           if ((REG_NOTE_KIND (note) == REG_DEAD
11543                || REG_NOTE_KIND (note) == REG_UNUSED)
11544               && GET_CODE (XEXP (note, 0)) == REG)
11545             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11546
11547           REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11548                                         XEXP (note, 0), REG_NOTES (place2));
11549         }
11550     }
11551 }
11552 \f
11553 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11554    I3, I2, and I1 to new locations.  This is also called in one case to
11555    add a link pointing at I3 when I3's destination is changed.  */
11556
11557 static void
11558 distribute_links (links)
11559      rtx links;
11560 {
11561   rtx link, next_link;
11562
11563   for (link = links; link; link = next_link)
11564     {
11565       rtx place = 0;
11566       rtx insn;
11567       rtx set, reg;
11568
11569       next_link = XEXP (link, 1);
11570
11571       /* If the insn that this link points to is a NOTE or isn't a single
11572          set, ignore it.  In the latter case, it isn't clear what we
11573          can do other than ignore the link, since we can't tell which
11574          register it was for.  Such links wouldn't be used by combine
11575          anyway.
11576
11577          It is not possible for the destination of the target of the link to
11578          have been changed by combine.  The only potential of this is if we
11579          replace I3, I2, and I1 by I3 and I2.  But in that case the
11580          destination of I2 also remains unchanged.  */
11581
11582       if (GET_CODE (XEXP (link, 0)) == NOTE
11583           || (set = single_set (XEXP (link, 0))) == 0)
11584         continue;
11585
11586       reg = SET_DEST (set);
11587       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11588              || GET_CODE (reg) == SIGN_EXTRACT
11589              || GET_CODE (reg) == STRICT_LOW_PART)
11590         reg = XEXP (reg, 0);
11591
11592       /* A LOG_LINK is defined as being placed on the first insn that uses
11593          a register and points to the insn that sets the register.  Start
11594          searching at the next insn after the target of the link and stop
11595          when we reach a set of the register or the end of the basic block.
11596
11597          Note that this correctly handles the link that used to point from
11598          I3 to I2.  Also note that not much searching is typically done here
11599          since most links don't point very far away.  */
11600
11601       for (insn = NEXT_INSN (XEXP (link, 0));
11602            (insn && (this_basic_block == n_basic_blocks - 1
11603                      || basic_block_head[this_basic_block + 1] != insn));
11604            insn = NEXT_INSN (insn))
11605         if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11606             && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11607           {
11608             if (reg_referenced_p (reg, PATTERN (insn)))
11609               place = insn;
11610             break;
11611           }
11612         else if (GET_CODE (insn) == CALL_INSN
11613               && find_reg_fusage (insn, USE, reg))
11614           {
11615             place = insn;
11616             break;
11617           }
11618
11619       /* If we found a place to put the link, place it there unless there
11620          is already a link to the same insn as LINK at that point.  */
11621
11622       if (place)
11623         {
11624           rtx link2;
11625
11626           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11627             if (XEXP (link2, 0) == XEXP (link, 0))
11628               break;
11629
11630           if (link2 == 0)
11631             {
11632               XEXP (link, 1) = LOG_LINKS (place);
11633               LOG_LINKS (place) = link;
11634
11635               /* Set added_links_insn to the earliest insn we added a
11636                  link to.  */
11637               if (added_links_insn == 0
11638                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
11639                 added_links_insn = place;
11640             }
11641         }
11642     }
11643 }
11644 \f
11645 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
11646
11647 static int
11648 insn_cuid (insn)
11649      rtx insn;
11650 {
11651   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11652          && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11653     insn = NEXT_INSN (insn);
11654
11655   if (INSN_UID (insn) > max_uid_cuid)
11656     abort ();
11657
11658   return INSN_CUID (insn);
11659 }
11660 \f
11661 void
11662 dump_combine_stats (file)
11663      FILE *file;
11664 {
11665   fprintf
11666     (file,
11667      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11668      combine_attempts, combine_merges, combine_extras, combine_successes);
11669 }
11670
11671 void
11672 dump_combine_total_stats (file)
11673      FILE *file;
11674 {
11675   fprintf
11676     (file,
11677      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11678      total_attempts, total_merges, total_extras, total_successes);
11679 }