1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (match_operand 0 "register_operand")
121 if (GET_CODE (op) == SUBREG)
122 op = SUBREG_REG (op);
127 return CA_REGNO_P (REGNO (op));
130 ;; Return 1 if op is a signed 5-bit constant integer.
131 (define_predicate "s5bit_cint_operand"
132 (and (match_code "const_int")
133 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
135 ;; Return 1 if op is a unsigned 3-bit constant integer.
136 (define_predicate "u3bit_cint_operand"
137 (and (match_code "const_int")
138 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
140 ;; Return 1 if op is a unsigned 5-bit constant integer.
141 (define_predicate "u5bit_cint_operand"
142 (and (match_code "const_int")
143 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
145 ;; Return 1 if op is a signed 8-bit constant integer.
146 ;; Integer multiplication complete more quickly
147 (define_predicate "s8bit_cint_operand"
148 (and (match_code "const_int")
149 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
151 ;; Return 1 if op is a unsigned 10-bit constant integer.
152 (define_predicate "u10bit_cint_operand"
153 (and (match_code "const_int")
154 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
156 ;; Return 1 if op is a constant integer that can fit in a D field.
157 (define_predicate "short_cint_operand"
158 (and (match_code "const_int")
159 (match_test "satisfies_constraint_I (op)")))
161 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
162 (define_predicate "u_short_cint_operand"
163 (and (match_code "const_int")
164 (match_test "satisfies_constraint_K (op)")))
166 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
167 (define_predicate "non_short_cint_operand"
168 (and (match_code "const_int")
169 (match_test "(unsigned HOST_WIDE_INT)
170 (INTVAL (op) + 0x8000) >= 0x10000")))
172 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
173 (define_predicate "exact_log2_cint_operand"
174 (and (match_code "const_int")
175 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
177 ;; Match op = 0 or op = 1.
178 (define_predicate "const_0_to_1_operand"
179 (and (match_code "const_int")
180 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
183 (define_predicate "const_0_to_3_operand"
184 (and (match_code "const_int")
185 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
187 ;; Match op = 2 or op = 3.
188 (define_predicate "const_2_to_3_operand"
189 (and (match_code "const_int")
190 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
193 (define_predicate "const_0_to_15_operand"
194 (and (match_code "const_int")
195 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
197 ;; Return 1 if op is a register that is not special.
198 (define_predicate "gpc_reg_operand"
199 (match_operand 0 "register_operand")
201 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
204 if (GET_CODE (op) == SUBREG)
205 op = SUBREG_REG (op);
210 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
213 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
216 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
219 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
220 ;; allow floating point or vector registers.
221 (define_predicate "int_reg_operand"
222 (match_operand 0 "register_operand")
224 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
227 if (GET_CODE (op) == SUBREG)
228 op = SUBREG_REG (op);
233 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
236 return INT_REGNO_P (REGNO (op));
239 ;; Like int_reg_operand, but only return true for base registers
240 (define_predicate "base_reg_operand"
241 (match_operand 0 "int_reg_operand")
243 if (GET_CODE (op) == SUBREG)
244 op = SUBREG_REG (op);
249 return (REGNO (op) != FIRST_GPR_REGNO);
252 ;; Return 1 if op is a HTM specific SPR register.
253 (define_predicate "htm_spr_reg_operand"
254 (match_operand 0 "register_operand")
259 if (GET_CODE (op) == SUBREG)
260 op = SUBREG_REG (op);
279 ;; Return 1 if op is a general purpose register that is an even register
280 ;; which suitable for a load/store quad operation
281 (define_predicate "quad_int_reg_operand"
282 (match_operand 0 "register_operand")
286 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
289 if (GET_CODE (op) == SUBREG)
290 op = SUBREG_REG (op);
296 if (r >= FIRST_PSEUDO_REGISTER)
299 return (INT_REGNO_P (r) && ((r & 1) == 0));
302 ;; Return 1 if op is a register that is a condition register field.
303 (define_predicate "cc_reg_operand"
304 (match_operand 0 "register_operand")
306 if (GET_CODE (op) == SUBREG)
307 op = SUBREG_REG (op);
312 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
315 return CR_REGNO_P (REGNO (op));
318 ;; Return 1 if op is a register that is a condition register field not cr0.
319 (define_predicate "cc_reg_not_cr0_operand"
320 (match_operand 0 "register_operand")
322 if (GET_CODE (op) == SUBREG)
323 op = SUBREG_REG (op);
328 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
331 return CR_REGNO_NOT_CR0_P (REGNO (op));
334 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
335 (define_predicate "cc_reg_not_micro_cr0_operand"
336 (match_operand 0 "register_operand")
338 if (GET_CODE (op) == SUBREG)
339 op = SUBREG_REG (op);
344 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
347 if (rs6000_gen_cell_microcode)
348 return CR_REGNO_NOT_CR0_P (REGNO (op));
350 return CR_REGNO_P (REGNO (op));
353 ;; Return 1 if op is a constant integer valid for D field
354 ;; or non-special register register.
355 (define_predicate "reg_or_short_operand"
356 (if_then_else (match_code "const_int")
357 (match_operand 0 "short_cint_operand")
358 (match_operand 0 "gpc_reg_operand")))
360 ;; Return 1 if op is a constant integer valid whose negation is valid for
361 ;; D field or non-special register register.
362 ;; Do not allow a constant zero because all patterns that call this
363 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
364 ;; or equal to const, which does not work for zero.
365 (define_predicate "reg_or_neg_short_operand"
366 (if_then_else (match_code "const_int")
367 (match_test "satisfies_constraint_P (op)
368 && INTVAL (op) != 0")
369 (match_operand 0 "gpc_reg_operand")))
371 ;; Return 1 if op is a constant integer valid for DS field
372 ;; or non-special register.
373 (define_predicate "reg_or_aligned_short_operand"
374 (if_then_else (match_code "const_int")
375 (and (match_operand 0 "short_cint_operand")
376 (match_test "!(INTVAL (op) & 3)"))
377 (match_operand 0 "gpc_reg_operand")))
379 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
380 ;; or non-special register.
381 (define_predicate "reg_or_u_short_operand"
382 (if_then_else (match_code "const_int")
383 (match_operand 0 "u_short_cint_operand")
384 (match_operand 0 "gpc_reg_operand")))
386 ;; Return 1 if op is any constant integer
387 ;; or non-special register.
388 (define_predicate "reg_or_cint_operand"
389 (ior (match_code "const_int")
390 (match_operand 0 "gpc_reg_operand")))
392 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
393 (define_predicate "add_cint_operand"
394 (and (match_code "const_int")
395 (match_test "(unsigned HOST_WIDE_INT)
396 (INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
397 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
399 ;; Return 1 if op is a constant integer valid for addition
400 ;; or non-special register.
401 (define_predicate "reg_or_add_cint_operand"
402 (if_then_else (match_code "const_int")
403 (match_operand 0 "add_cint_operand")
404 (match_operand 0 "gpc_reg_operand")))
406 ;; Return 1 if op is a constant integer valid for subtraction
407 ;; or non-special register.
408 (define_predicate "reg_or_sub_cint_operand"
409 (if_then_else (match_code "const_int")
410 (match_test "(unsigned HOST_WIDE_INT)
411 (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
412 < (unsigned HOST_WIDE_INT) 0x100000000ll")
413 (match_operand 0 "gpc_reg_operand")))
415 ;; Return 1 if op is any 32-bit unsigned constant integer
416 ;; or non-special register.
417 (define_predicate "reg_or_logical_cint_operand"
418 (if_then_else (match_code "const_int")
419 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
421 || ((INTVAL (op) & GET_MODE_MASK (mode)
422 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
423 (match_operand 0 "gpc_reg_operand")))
425 ;; Like reg_or_logical_cint_operand, but allow vsx registers
426 (define_predicate "vsx_reg_or_cint_operand"
427 (ior (match_operand 0 "vsx_register_operand")
428 (match_operand 0 "reg_or_logical_cint_operand")))
430 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
431 ;; with no more than one instruction per word.
432 (define_predicate "easy_fp_constant"
433 (match_code "const_double")
438 if (GET_MODE (op) != mode
439 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
442 /* Consider all constants with -msoft-float to be easy. */
443 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
444 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
448 /* The constant 0.0 is easy under VSX. */
449 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
450 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
453 if (DECIMAL_FLOAT_MODE_P (mode))
456 /* If we are using V.4 style PIC, consider all constants to be hard. */
457 if (flag_pic && DEFAULT_ABI == ABI_V4)
460 #ifdef TARGET_RELOCATABLE
461 /* Similarly if we are using -mrelocatable, consider all constants
463 if (TARGET_RELOCATABLE)
470 if (TARGET_E500_DOUBLE)
473 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
474 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
476 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
477 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
478 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
479 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
482 /* The constant 0.f is easy under VSX. */
483 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
486 /* Force constants to memory before reload to utilize
487 compress_float_constant.
488 Avoid this when flag_unsafe_math_optimizations is enabled
489 because RDIV division to reciprocal optimization is not able
490 to regenerate the division. */
491 if (TARGET_E500_DOUBLE
492 || (!reload_in_progress && !reload_completed
493 && !flag_unsafe_math_optimizations))
496 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
497 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
499 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
500 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
503 /* The constant 0.f is easy. */
504 if (op == CONST0_RTX (SFmode))
507 /* Force constants to memory before reload to utilize
508 compress_float_constant.
509 Avoid this when flag_unsafe_math_optimizations is enabled
510 because RDIV division to reciprocal optimization is not able
511 to regenerate the division. */
512 if (!reload_in_progress && !reload_completed
513 && !flag_unsafe_math_optimizations)
516 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
517 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
519 return num_insns_constant_wide (k[0]) == 1;
522 return (num_insns_constant (op, DImode) <= 2);
532 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
533 ;; vector register without using memory.
534 (define_predicate "easy_vector_constant"
535 (match_code "const_vector")
537 /* As the paired vectors are actually FPRs it seems that there is
538 no easy way to load a CONST_VECTOR without using memory. */
539 if (TARGET_PAIRED_FLOAT)
542 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
544 if (zero_constant (op, mode))
547 return easy_altivec_constant (op, mode);
550 if (SPE_VECTOR_MODE (mode))
553 if (zero_constant (op, mode))
555 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
558 /* Limit SPE vectors to 15 bits signed. These we can generate with:
563 I don't know how efficient it would be to allow bigger constants,
564 considering we'll have an extra 'ori' for every 'li'. I doubt 5
565 instructions is better than a 64-bit memory load, but I don't
566 have the e500 timing specs. */
567 if (mode == V2SImode)
569 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
570 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
571 return cst >= -0x7fff && cst <= 0x7fff
572 && cst2 >= -0x7fff && cst2 <= 0x7fff;
579 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
580 (define_predicate "easy_vector_constant_add_self"
581 (and (match_code "const_vector")
582 (and (match_test "TARGET_ALTIVEC")
583 (match_test "easy_altivec_constant (op, mode)")))
587 if (mode == V2DImode || mode == V2DFmode)
589 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
590 val = const_vector_elt_as_int (op, elt);
591 val = ((val & 0xff) ^ 0x80) - 0x80;
592 return EASY_VECTOR_15_ADD_SELF (val);
595 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
596 (define_predicate "easy_vector_constant_msb"
597 (and (match_code "const_vector")
598 (and (match_test "TARGET_ALTIVEC")
599 (match_test "easy_altivec_constant (op, mode)")))
603 if (mode == V2DImode || mode == V2DFmode)
605 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
606 val = const_vector_elt_as_int (op, elt);
607 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
610 ;; Return 1 if operand is constant zero (scalars and vectors).
611 (define_predicate "zero_constant"
612 (and (match_code "const_int,const_double,const_wide_int,const_vector")
613 (match_test "op == CONST0_RTX (mode)")))
615 ;; Return 1 if operand is 0.0.
616 (define_predicate "zero_fp_constant"
617 (and (match_code "const_double")
618 (match_test "SCALAR_FLOAT_MODE_P (mode)
619 && op == CONST0_RTX (mode)")))
621 ;; Return 1 if the operand is in volatile memory. Note that during the
622 ;; RTL generation phase, memory_operand does not return TRUE for volatile
623 ;; memory references. So this function allows us to recognize volatile
624 ;; references where it's safe.
625 (define_predicate "volatile_mem_operand"
626 (and (and (match_code "mem")
627 (match_test "MEM_VOLATILE_P (op)"))
628 (if_then_else (match_test "reload_completed")
629 (match_operand 0 "memory_operand")
630 (if_then_else (match_test "reload_in_progress")
631 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
632 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
634 ;; Return 1 if the operand is an offsettable memory operand.
635 (define_predicate "offsettable_mem_operand"
636 (and (match_operand 0 "memory_operand")
637 (match_test "offsettable_nonstrict_memref_p (op)")))
639 ;; Return 1 if the operand is suitable for load/store quad memory.
640 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
641 (define_predicate "quad_memory_operand"
647 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
650 else if (!memory_operand (op, mode))
653 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
656 else if (MEM_ALIGN (op) < 128)
662 if (int_reg_operand (addr, Pmode))
665 else if (GET_CODE (addr) != PLUS)
670 op0 = XEXP (addr, 0);
671 op1 = XEXP (addr, 1);
672 ret = (int_reg_operand (op0, Pmode)
673 && GET_CODE (op1) == CONST_INT
674 && IN_RANGE (INTVAL (op1), -32768, 32767)
675 && (INTVAL (op1) & 15) == 0);
679 if (TARGET_DEBUG_ADDR)
681 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
688 ;; Return 1 if the operand is an indexed or indirect memory operand.
689 (define_predicate "indexed_or_indirect_operand"
693 if (VECTOR_MEM_ALTIVEC_P (mode)
694 && GET_CODE (op) == AND
695 && GET_CODE (XEXP (op, 1)) == CONST_INT
696 && INTVAL (XEXP (op, 1)) == -16)
699 return indexed_or_indirect_address (op, mode);
702 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
703 ;; moves are supported.
704 (define_predicate "reg_or_indexed_operand"
705 (match_code "mem,reg")
708 return indexed_or_indirect_operand (op, mode);
709 else if (TARGET_DIRECT_MOVE)
710 return register_operand (op, mode);
715 ;; Return 1 if the operand is an indexed or indirect memory operand with an
716 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
717 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
718 ;; while VSX uses the full address and traps)
719 (define_predicate "altivec_indexed_or_indirect_operand"
723 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
724 && GET_CODE (op) == AND
725 && GET_CODE (XEXP (op, 1)) == CONST_INT
726 && INTVAL (XEXP (op, 1)) == -16)
727 return indexed_or_indirect_address (XEXP (op, 0), mode);
732 ;; Return 1 if the operand is an indexed or indirect address.
733 (define_special_predicate "indexed_or_indirect_address"
734 (and (match_test "REG_P (op)
735 || (GET_CODE (op) == PLUS
736 /* Omit testing REG_P (XEXP (op, 0)). */
737 && REG_P (XEXP (op, 1)))")
738 (match_operand 0 "address_operand")))
740 ;; Return 1 if the operand is an index-form address.
741 (define_special_predicate "indexed_address"
742 (match_test "(GET_CODE (op) == PLUS
743 && REG_P (XEXP (op, 0))
744 && REG_P (XEXP (op, 1)))"))
746 ;; Return 1 if the operand is a MEM with an update-form address. This may
747 ;; also include update-indexed form.
748 (define_special_predicate "update_address_mem"
749 (match_test "(MEM_P (op)
750 && (GET_CODE (XEXP (op, 0)) == PRE_INC
751 || GET_CODE (XEXP (op, 0)) == PRE_DEC
752 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
754 ;; Return 1 if the operand is a MEM with an indexed-form address.
755 (define_special_predicate "indexed_address_mem"
756 (match_test "(MEM_P (op)
757 && (indexed_address (XEXP (op, 0), mode)
758 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
759 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
761 ;; Used for the destination of the fix_truncdfsi2 expander.
762 ;; If stfiwx will be used, the result goes to memory; otherwise,
763 ;; we're going to emit a store and a load of a subreg, so the dest is a
765 (define_predicate "fix_trunc_dest_operand"
766 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
767 (match_operand 0 "memory_operand")
768 (match_operand 0 "gpc_reg_operand")))
770 ;; Return 1 if the operand is either a non-special register or can be used
771 ;; as the operand of a `mode' add insn.
772 (define_predicate "add_operand"
773 (if_then_else (match_code "const_int")
774 (match_test "satisfies_constraint_I (op)
775 || satisfies_constraint_L (op)")
776 (match_operand 0 "gpc_reg_operand")))
778 ;; Return 1 if OP is a constant but not a valid add_operand.
779 (define_predicate "non_add_cint_operand"
780 (and (match_code "const_int")
781 (match_test "!satisfies_constraint_I (op)
782 && !satisfies_constraint_L (op)")))
784 ;; Return 1 if the operand is a constant that can be used as the operand
786 (define_predicate "logical_const_operand"
787 (match_code "const_int")
791 opl = INTVAL (op) & GET_MODE_MASK (mode);
793 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
794 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
797 ;; Return 1 if the operand is a non-special register or a constant that
798 ;; can be used as the operand of an OR or XOR.
799 (define_predicate "logical_operand"
800 (ior (match_operand 0 "gpc_reg_operand")
801 (match_operand 0 "logical_const_operand")))
803 ;; Return 1 if op is a constant that is not a logical operand, but could
804 ;; be split into one.
805 (define_predicate "non_logical_cint_operand"
806 (and (match_code "const_int,const_wide_int")
807 (and (not (match_operand 0 "logical_operand"))
808 (match_operand 0 "reg_or_logical_cint_operand"))))
810 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
811 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
812 ;; transitions). Reject all ones and all zeros, since these should have
813 ;; been optimized away and confuse the making of MB and ME.
814 (define_predicate "mask_operand"
815 (match_code "const_int")
817 HOST_WIDE_INT c, lsb;
821 if (TARGET_POWERPC64)
823 /* Fail if the mask is not 32-bit. */
824 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
827 /* Fail if the mask wraps around because the upper 32-bits of the
828 mask will all be 1s, contrary to GCC's internal view. */
829 if ((c & 0x80000001) == 0x80000001)
833 /* We don't change the number of transitions by inverting,
834 so make sure we start with the LS bit zero. */
838 /* Reject all zeros or all ones. */
842 /* Find the first transition. */
845 /* Invert to look for a second transition. */
848 /* Erase first transition. */
851 /* Find the second transition (if any). */
854 /* Match if all the bits above are 1's (or c is zero). */
858 ;; Return 1 for the PowerPC64 rlwinm corner case.
859 (define_predicate "mask_operand_wrap"
860 (match_code "const_int")
862 HOST_WIDE_INT c, lsb;
866 if ((c & 0x80000001) != 0x80000001)
880 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
881 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
882 ;; transition). Reject all zeros, since zero should have been
883 ;; optimized away and confuses the making of MB and ME.
884 (define_predicate "mask64_operand"
885 (match_code "const_int")
887 HOST_WIDE_INT c, lsb;
891 /* Reject all zeros. */
895 /* We don't change the number of transitions by inverting,
896 so make sure we start with the LS bit zero. */
900 /* Find the first transition. */
903 /* Match if all the bits above are 1's (or c is zero). */
907 ;; Like mask64_operand, but allow up to three transitions. This
908 ;; predicate is used by insn patterns that generate two rldicl or
909 ;; rldicr machine insns.
910 (define_predicate "mask64_2_operand"
911 (match_code "const_int")
913 HOST_WIDE_INT c, lsb;
917 /* Disallow all zeros. */
921 /* We don't change the number of transitions by inverting,
922 so make sure we start with the LS bit zero. */
926 /* Find the first transition. */
929 /* Invert to look for a second transition. */
932 /* Erase first transition. */
935 /* Find the second transition. */
938 /* Invert to look for a third transition. */
941 /* Erase second transition. */
944 /* Find the third transition (if any). */
947 /* Match if all the bits above are 1's (or c is zero). */
951 ;; Match a mask_operand or a mask64_operand.
952 (define_predicate "any_mask_operand"
953 (ior (match_operand 0 "mask_operand")
954 (and (match_test "TARGET_POWERPC64 && mode == DImode")
955 (match_operand 0 "mask64_operand"))))
957 ;; Like and_operand, but also match constants that can be implemented
958 ;; with two rldicl or rldicr insns.
959 (define_predicate "and64_2_operand"
960 (ior (match_operand 0 "mask64_2_operand")
961 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
962 (match_operand 0 "gpc_reg_operand")
963 (match_operand 0 "logical_operand"))))
965 ;; Return 1 if the operand is either a non-special register or a
966 ;; constant that can be used as the operand of a logical AND.
967 (define_predicate "and_operand"
968 (ior (match_operand 0 "mask_operand")
969 (and (match_test "TARGET_POWERPC64 && mode == DImode")
970 (match_operand 0 "mask64_operand"))
971 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
972 (match_operand 0 "gpc_reg_operand")
973 (match_operand 0 "logical_operand"))))
975 ;; Return 1 if the operand is a constant that can be used as the operand
976 ;; of a logical AND, implemented with two rld* insns, and it cannot be done
977 ;; using just one insn.
978 (define_predicate "and_2rld_operand"
979 (and (match_operand 0 "and64_2_operand")
980 (not (match_operand 0 "and_operand"))))
982 ;; Return 1 if the operand is either a logical operand or a short cint operand.
983 (define_predicate "scc_eq_operand"
984 (ior (match_operand 0 "logical_operand")
985 (match_operand 0 "short_cint_operand")))
987 ;; Return 1 if the operand is a general non-special register or memory operand.
988 (define_predicate "reg_or_mem_operand"
989 (ior (match_operand 0 "memory_operand")
990 (ior (and (match_code "mem")
991 (match_test "macho_lo_sum_memory_operand (op, mode)"))
992 (ior (match_operand 0 "volatile_mem_operand")
993 (match_operand 0 "gpc_reg_operand")))))
995 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
996 (define_predicate "reg_or_none500mem_operand"
997 (if_then_else (match_code "mem")
998 (and (match_test "!TARGET_E500_DOUBLE")
999 (ior (match_operand 0 "memory_operand")
1000 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
1001 (match_operand 0 "volatile_mem_operand"))))
1002 (match_operand 0 "gpc_reg_operand")))
1004 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
1005 (define_predicate "zero_reg_mem_operand"
1006 (ior (match_operand 0 "zero_fp_constant")
1007 (match_operand 0 "reg_or_mem_operand")))
1009 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
1010 ;; data types inside of a vector that scalar instructions operate on
1011 (define_predicate "vsx_scalar_64bit"
1012 (match_code "const_int")
1014 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
1017 ;; Return 1 if the operand is a general register or memory operand without
1018 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
1020 (define_predicate "lwa_operand"
1021 (match_code "reg,subreg,mem")
1023 rtx inner, addr, offset;
1026 if (reload_completed && GET_CODE (inner) == SUBREG)
1027 inner = SUBREG_REG (inner);
1029 if (gpc_reg_operand (inner, mode))
1031 if (!memory_operand (inner, mode))
1033 if (!rs6000_gen_cell_microcode)
1036 addr = XEXP (inner, 0);
1037 if (GET_CODE (addr) == PRE_INC
1038 || GET_CODE (addr) == PRE_DEC
1039 || (GET_CODE (addr) == PRE_MODIFY
1040 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1042 if (GET_CODE (addr) == LO_SUM
1043 && GET_CODE (XEXP (addr, 0)) == REG
1044 && GET_CODE (XEXP (addr, 1)) == CONST)
1045 addr = XEXP (XEXP (addr, 1), 0);
1046 if (GET_CODE (addr) != PLUS)
1048 offset = XEXP (addr, 1);
1049 if (GET_CODE (offset) != CONST_INT)
1051 return INTVAL (offset) % 4 == 0;
1054 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1055 (define_predicate "symbol_ref_operand"
1056 (and (match_code "symbol_ref")
1057 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1058 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1060 ;; Return 1 if op is an operand that can be loaded via the GOT.
1061 ;; or non-special register register field no cr0
1062 (define_predicate "got_operand"
1063 (match_code "symbol_ref,const,label_ref"))
1065 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1066 ;; excluding labels involving addition.
1067 (define_predicate "got_no_const_operand"
1068 (match_code "symbol_ref,label_ref"))
1070 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1071 (define_predicate "rs6000_tls_symbol_ref"
1072 (and (match_code "symbol_ref")
1073 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1075 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1076 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1077 (define_predicate "call_operand"
1078 (if_then_else (match_code "reg")
1079 (match_test "REGNO (op) == LR_REGNO
1080 || REGNO (op) == CTR_REGNO
1081 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1082 (match_code "symbol_ref")))
1084 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1086 (define_predicate "current_file_function_operand"
1087 (and (match_code "symbol_ref")
1088 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1089 && ((SYMBOL_REF_LOCAL_P (op)
1090 && ((DEFAULT_ABI != ABI_AIX
1091 && DEFAULT_ABI != ABI_ELFv2)
1092 || !SYMBOL_REF_EXTERNAL_P (op)))
1093 || (op == XEXP (DECL_RTL (current_function_decl),
1096 ;; Return 1 if this operand is a valid input for a move insn.
1097 (define_predicate "input_operand"
1098 (match_code "symbol_ref,const,reg,subreg,mem,
1099 const_double,const_wide_int,const_vector,const_int")
1101 /* Memory is always valid. */
1102 if (memory_operand (op, mode))
1105 /* For floating-point, easy constants are valid. */
1106 if (SCALAR_FLOAT_MODE_P (mode)
1107 && easy_fp_constant (op, mode))
1110 /* Allow any integer constant. */
1111 if (GET_MODE_CLASS (mode) == MODE_INT
1112 && CONST_SCALAR_INT_P (op))
1115 /* Allow easy vector constants. */
1116 if (GET_CODE (op) == CONST_VECTOR
1117 && easy_vector_constant (op, mode))
1120 /* Do not allow invalid E500 subregs. */
1121 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1122 && GET_CODE (op) == SUBREG
1123 && invalid_e500_subreg (op, mode))
1126 /* For floating-point or multi-word mode, the only remaining valid type
1128 if (SCALAR_FLOAT_MODE_P (mode)
1129 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1130 return register_operand (op, mode);
1132 /* We don't allow moving the carry bit around. */
1133 if (ca_operand (op, mode))
1136 /* The only cases left are integral modes one word or smaller (we
1137 do not get called for MODE_CC values). These can be in any
1139 if (register_operand (op, mode))
1142 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1144 if (DEFAULT_ABI == ABI_V4
1145 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1146 && small_data_operand (op, Pmode))
1152 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1153 (define_predicate "splat_input_operand"
1154 (match_code "symbol_ref,const,reg,subreg,mem,
1155 const_double,const_wide_int,const_vector,const_int")
1159 if (! volatile_ok && MEM_VOLATILE_P (op))
1163 else if (mode == DImode)
1167 return memory_address_addr_space_p (mode, XEXP (op, 0),
1168 MEM_ADDR_SPACE (op));
1170 return input_operand (op, mode);
1173 ;; Return true if OP is a non-immediate operand and not an invalid
1174 ;; SUBREG operation on the e500.
1175 (define_predicate "rs6000_nonimmediate_operand"
1176 (match_code "reg,subreg,mem")
1178 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1179 && GET_CODE (op) == SUBREG
1180 && invalid_e500_subreg (op, mode))
1183 return nonimmediate_operand (op, mode);
1186 ;; Return true if operand is boolean operator.
1187 (define_predicate "boolean_operator"
1188 (match_code "and,ior,xor"))
1190 ;; Return true if operand is OR-form of boolean operator.
1191 (define_predicate "boolean_or_operator"
1192 (match_code "ior,xor"))
1194 ;; Return true if operand is an equality operator.
1195 (define_special_predicate "equality_operator"
1196 (match_code "eq,ne"))
1198 ;; Return true if operand is MIN or MAX operator.
1199 (define_predicate "min_max_operator"
1200 (match_code "smin,smax,umin,umax"))
1202 ;; Return 1 if OP is a comparison operation that is valid for a branch
1203 ;; instruction. We check the opcode against the mode of the CC value.
1204 ;; validate_condition_mode is an assertion.
1205 (define_predicate "branch_comparison_operator"
1206 (and (match_operand 0 "comparison_operator")
1207 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1208 (match_test "validate_condition_mode (GET_CODE (op),
1209 GET_MODE (XEXP (op, 0))),
1212 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1213 ;; If we're assuming that FP operations cannot generate user-visible traps,
1214 ;; then on e500 we can use the ordered-signaling instructions to implement
1215 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1216 (define_predicate "rs6000_cbranch_operator"
1217 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1218 (if_then_else (match_test "flag_trapping_math")
1219 (match_operand 0 "ordered_comparison_operator")
1220 (ior (match_operand 0 "ordered_comparison_operator")
1221 (match_code ("unlt,unle,ungt,unge"))))
1222 (match_operand 0 "comparison_operator")))
1224 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1225 ;; it must be a positive comparison.
1226 (define_predicate "scc_comparison_operator"
1227 (and (match_operand 0 "branch_comparison_operator")
1228 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1230 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1232 (define_predicate "scc_rev_comparison_operator"
1233 (and (match_operand 0 "branch_comparison_operator")
1234 (match_code "ne,le,ge,leu,geu,ordered")))
1236 ;; Return 1 if OP is a comparison operation that is valid for a branch
1237 ;; insn, which is true if the corresponding bit in the CC register is set.
1238 (define_predicate "branch_positive_comparison_operator"
1239 (and (match_operand 0 "branch_comparison_operator")
1240 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1242 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1243 (define_predicate "load_multiple_operation"
1244 (match_code "parallel")
1246 int count = XVECLEN (op, 0);
1247 unsigned int dest_regno;
1251 /* Perform a quick check so we don't blow up below. */
1253 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1254 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1255 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1258 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1259 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1261 for (i = 1; i < count; i++)
1263 rtx elt = XVECEXP (op, 0, i);
1265 if (GET_CODE (elt) != SET
1266 || GET_CODE (SET_DEST (elt)) != REG
1267 || GET_MODE (SET_DEST (elt)) != SImode
1268 || REGNO (SET_DEST (elt)) != dest_regno + i
1269 || GET_CODE (SET_SRC (elt)) != MEM
1270 || GET_MODE (SET_SRC (elt)) != SImode
1271 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1272 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1273 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1274 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1281 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1282 ;; The second vector element is a CLOBBER.
1283 (define_predicate "store_multiple_operation"
1284 (match_code "parallel")
1286 int count = XVECLEN (op, 0) - 1;
1287 unsigned int src_regno;
1291 /* Perform a quick check so we don't blow up below. */
1293 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1294 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1295 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1298 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1299 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1301 for (i = 1; i < count; i++)
1303 rtx elt = XVECEXP (op, 0, i + 1);
1305 if (GET_CODE (elt) != SET
1306 || GET_CODE (SET_SRC (elt)) != REG
1307 || GET_MODE (SET_SRC (elt)) != SImode
1308 || REGNO (SET_SRC (elt)) != src_regno + i
1309 || GET_CODE (SET_DEST (elt)) != MEM
1310 || GET_MODE (SET_DEST (elt)) != SImode
1311 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1312 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1313 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1314 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1321 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1323 (define_predicate "save_world_operation"
1324 (match_code "parallel")
1329 int count = XVECLEN (op, 0);
1335 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1336 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1339 for (i=1; i <= 18; i++)
1341 elt = XVECEXP (op, 0, index++);
1342 if (GET_CODE (elt) != SET
1343 || GET_CODE (SET_DEST (elt)) != MEM
1344 || ! memory_operand (SET_DEST (elt), DFmode)
1345 || GET_CODE (SET_SRC (elt)) != REG
1346 || GET_MODE (SET_SRC (elt)) != DFmode)
1350 for (i=1; i <= 12; i++)
1352 elt = XVECEXP (op, 0, index++);
1353 if (GET_CODE (elt) != SET
1354 || GET_CODE (SET_DEST (elt)) != MEM
1355 || GET_CODE (SET_SRC (elt)) != REG
1356 || GET_MODE (SET_SRC (elt)) != V4SImode)
1360 for (i=1; i <= 19; i++)
1362 elt = XVECEXP (op, 0, index++);
1363 if (GET_CODE (elt) != SET
1364 || GET_CODE (SET_DEST (elt)) != MEM
1365 || ! memory_operand (SET_DEST (elt), Pmode)
1366 || GET_CODE (SET_SRC (elt)) != REG
1367 || GET_MODE (SET_SRC (elt)) != Pmode)
1371 elt = XVECEXP (op, 0, index++);
1372 if (GET_CODE (elt) != SET
1373 || GET_CODE (SET_DEST (elt)) != MEM
1374 || ! memory_operand (SET_DEST (elt), Pmode)
1375 || GET_CODE (SET_SRC (elt)) != REG
1376 || REGNO (SET_SRC (elt)) != CR2_REGNO
1377 || GET_MODE (SET_SRC (elt)) != Pmode)
1380 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1381 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1386 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1388 (define_predicate "restore_world_operation"
1389 (match_code "parallel")
1394 int count = XVECLEN (op, 0);
1400 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1401 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1402 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1403 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1406 elt = XVECEXP (op, 0, index++);
1407 if (GET_CODE (elt) != SET
1408 || GET_CODE (SET_SRC (elt)) != MEM
1409 || ! memory_operand (SET_SRC (elt), Pmode)
1410 || GET_CODE (SET_DEST (elt)) != REG
1411 || REGNO (SET_DEST (elt)) != CR2_REGNO
1412 || GET_MODE (SET_DEST (elt)) != Pmode)
1415 for (i=1; i <= 19; i++)
1417 elt = XVECEXP (op, 0, index++);
1418 if (GET_CODE (elt) != SET
1419 || GET_CODE (SET_SRC (elt)) != MEM
1420 || ! memory_operand (SET_SRC (elt), Pmode)
1421 || GET_CODE (SET_DEST (elt)) != REG
1422 || GET_MODE (SET_DEST (elt)) != Pmode)
1426 for (i=1; i <= 12; i++)
1428 elt = XVECEXP (op, 0, index++);
1429 if (GET_CODE (elt) != SET
1430 || GET_CODE (SET_SRC (elt)) != MEM
1431 || GET_CODE (SET_DEST (elt)) != REG
1432 || GET_MODE (SET_DEST (elt)) != V4SImode)
1436 for (i=1; i <= 18; i++)
1438 elt = XVECEXP (op, 0, index++);
1439 if (GET_CODE (elt) != SET
1440 || GET_CODE (SET_SRC (elt)) != MEM
1441 || ! memory_operand (SET_SRC (elt), DFmode)
1442 || GET_CODE (SET_DEST (elt)) != REG
1443 || GET_MODE (SET_DEST (elt)) != DFmode)
1447 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1448 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1449 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1450 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1451 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1456 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1457 (define_predicate "vrsave_operation"
1458 (match_code "parallel")
1460 int count = XVECLEN (op, 0);
1461 unsigned int dest_regno, src_regno;
1465 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1466 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1467 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1468 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1471 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1472 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1474 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1477 for (i = 1; i < count; i++)
1479 rtx elt = XVECEXP (op, 0, i);
1481 if (GET_CODE (elt) != CLOBBER
1482 && GET_CODE (elt) != SET)
1489 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1490 (define_predicate "mfcr_operation"
1491 (match_code "parallel")
1493 int count = XVECLEN (op, 0);
1496 /* Perform a quick check so we don't blow up below. */
1498 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1499 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1500 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1503 for (i = 0; i < count; i++)
1505 rtx exp = XVECEXP (op, 0, i);
1510 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1512 if (GET_CODE (src_reg) != REG
1513 || GET_MODE (src_reg) != CCmode
1514 || ! CR_REGNO_P (REGNO (src_reg)))
1517 if (GET_CODE (exp) != SET
1518 || GET_CODE (SET_DEST (exp)) != REG
1519 || GET_MODE (SET_DEST (exp)) != SImode
1520 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1522 unspec = SET_SRC (exp);
1523 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1525 if (GET_CODE (unspec) != UNSPEC
1526 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1527 || XVECLEN (unspec, 0) != 2
1528 || XVECEXP (unspec, 0, 0) != src_reg
1529 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1530 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1536 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1537 (define_predicate "mtcrf_operation"
1538 (match_code "parallel")
1540 int count = XVECLEN (op, 0);
1544 /* Perform a quick check so we don't blow up below. */
1546 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1547 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1548 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1550 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1552 if (GET_CODE (src_reg) != REG
1553 || GET_MODE (src_reg) != SImode
1554 || ! INT_REGNO_P (REGNO (src_reg)))
1557 for (i = 0; i < count; i++)
1559 rtx exp = XVECEXP (op, 0, i);
1563 if (GET_CODE (exp) != SET
1564 || GET_CODE (SET_DEST (exp)) != REG
1565 || GET_MODE (SET_DEST (exp)) != CCmode
1566 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1568 unspec = SET_SRC (exp);
1569 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1571 if (GET_CODE (unspec) != UNSPEC
1572 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1573 || XVECLEN (unspec, 0) != 2
1574 || XVECEXP (unspec, 0, 0) != src_reg
1575 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1576 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1582 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1583 (define_predicate "crsave_operation"
1584 (match_code "parallel")
1586 int count = XVECLEN (op, 0);
1589 for (i = 1; i < count; i++)
1591 rtx exp = XVECEXP (op, 0, i);
1593 if (GET_CODE (exp) != USE
1594 || GET_CODE (XEXP (exp, 0)) != REG
1595 || GET_MODE (XEXP (exp, 0)) != CCmode
1596 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1602 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1603 (define_predicate "lmw_operation"
1604 (match_code "parallel")
1606 int count = XVECLEN (op, 0);
1607 unsigned int dest_regno;
1609 unsigned int base_regno;
1610 HOST_WIDE_INT offset;
1613 /* Perform a quick check so we don't blow up below. */
1615 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1616 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1617 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1620 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1621 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1624 || count != 32 - (int) dest_regno)
1627 if (legitimate_indirect_address_p (src_addr, 0))
1630 base_regno = REGNO (src_addr);
1631 if (base_regno == 0)
1634 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1636 offset = INTVAL (XEXP (src_addr, 1));
1637 base_regno = REGNO (XEXP (src_addr, 0));
1642 for (i = 0; i < count; i++)
1644 rtx elt = XVECEXP (op, 0, i);
1647 HOST_WIDE_INT newoffset;
1649 if (GET_CODE (elt) != SET
1650 || GET_CODE (SET_DEST (elt)) != REG
1651 || GET_MODE (SET_DEST (elt)) != SImode
1652 || REGNO (SET_DEST (elt)) != dest_regno + i
1653 || GET_CODE (SET_SRC (elt)) != MEM
1654 || GET_MODE (SET_SRC (elt)) != SImode)
1656 newaddr = XEXP (SET_SRC (elt), 0);
1657 if (legitimate_indirect_address_p (newaddr, 0))
1662 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1664 addr_reg = XEXP (newaddr, 0);
1665 newoffset = INTVAL (XEXP (newaddr, 1));
1669 if (REGNO (addr_reg) != base_regno
1670 || newoffset != offset + 4 * i)
1677 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1678 (define_predicate "stmw_operation"
1679 (match_code "parallel")
1681 int count = XVECLEN (op, 0);
1682 unsigned int src_regno;
1684 unsigned int base_regno;
1685 HOST_WIDE_INT offset;
1688 /* Perform a quick check so we don't blow up below. */
1690 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1691 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1692 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1695 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1696 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1699 || count != 32 - (int) src_regno)
1702 if (legitimate_indirect_address_p (dest_addr, 0))
1705 base_regno = REGNO (dest_addr);
1706 if (base_regno == 0)
1709 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1711 offset = INTVAL (XEXP (dest_addr, 1));
1712 base_regno = REGNO (XEXP (dest_addr, 0));
1717 for (i = 0; i < count; i++)
1719 rtx elt = XVECEXP (op, 0, i);
1722 HOST_WIDE_INT newoffset;
1724 if (GET_CODE (elt) != SET
1725 || GET_CODE (SET_SRC (elt)) != REG
1726 || GET_MODE (SET_SRC (elt)) != SImode
1727 || REGNO (SET_SRC (elt)) != src_regno + i
1728 || GET_CODE (SET_DEST (elt)) != MEM
1729 || GET_MODE (SET_DEST (elt)) != SImode)
1731 newaddr = XEXP (SET_DEST (elt), 0);
1732 if (legitimate_indirect_address_p (newaddr, 0))
1737 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1739 addr_reg = XEXP (newaddr, 0);
1740 newoffset = INTVAL (XEXP (newaddr, 1));
1744 if (REGNO (addr_reg) != base_regno
1745 || newoffset != offset + 4 * i)
1752 ;; Return 1 if OP is a stack tie operand.
1753 (define_predicate "tie_operand"
1754 (match_code "parallel")
1756 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1757 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1758 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1759 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1762 ;; Match a small code model toc reference (or medium and large
1763 ;; model toc references before reload).
1764 (define_predicate "small_toc_ref"
1765 (match_code "unspec,plus")
1767 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1770 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1773 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1774 ;; GPR registers on power8.
1775 (define_predicate "fusion_gpr_addis"
1776 (match_code "const_int,high,plus")
1778 HOST_WIDE_INT value;
1781 if (GET_CODE (op) == HIGH)
1784 if (CONST_INT_P (op))
1787 else if (GET_CODE (op) == PLUS
1788 && base_reg_operand (XEXP (op, 0), Pmode)
1789 && CONST_INT_P (XEXP (op, 1)))
1790 int_const = XEXP (op, 1);
1795 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1796 value are all 1's or 0's. */
1797 value = INTVAL (int_const);
1798 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1801 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1804 return (IN_RANGE (value >> 16, -32, 31));
1807 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1808 ;; and loads to GPR registers on power8.
1809 (define_predicate "fusion_gpr_mem_load"
1810 (match_code "mem,sign_extend,zero_extend")
1812 rtx addr, base, offset;
1814 /* Handle sign/zero extend. */
1815 if (GET_CODE (op) == ZERO_EXTEND
1816 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1819 mode = GET_MODE (op);
1833 if (!TARGET_POWERPC64)
1841 addr = XEXP (op, 0);
1842 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1845 base = XEXP (addr, 0);
1846 if (!base_reg_operand (base, GET_MODE (base)))
1849 offset = XEXP (addr, 1);
1851 if (GET_CODE (addr) == PLUS)
1852 return satisfies_constraint_I (offset);
1854 else if (GET_CODE (addr) == LO_SUM)
1856 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1857 return small_toc_ref (offset, GET_MODE (offset));
1859 else if (TARGET_ELF && !TARGET_POWERPC64)
1860 return CONSTANT_P (offset);
1866 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1867 ;; memory field with both the addis and the memory offset. Sign extension
1868 ;; is not handled here, since lha and lwa are not fused.
1869 (define_predicate "fusion_gpr_mem_combo"
1870 (match_code "mem,zero_extend")
1872 rtx addr, base, offset;
1874 /* Handle zero extend. */
1875 if (GET_CODE (op) == ZERO_EXTEND)
1878 mode = GET_MODE (op);
1892 if (!TARGET_POWERPC64)
1900 addr = XEXP (op, 0);
1901 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1904 base = XEXP (addr, 0);
1905 if (!fusion_gpr_addis (base, GET_MODE (base)))
1908 offset = XEXP (addr, 1);
1909 if (GET_CODE (addr) == PLUS)
1910 return satisfies_constraint_I (offset);
1912 else if (GET_CODE (addr) == LO_SUM)
1914 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1915 return small_toc_ref (offset, GET_MODE (offset));
1917 else if (TARGET_ELF && !TARGET_POWERPC64)
1918 return CONSTANT_P (offset);