1 /* Machine description patterns for PowerPC running Darwin (Mac OS X).
2 Copyright (C) 2004-2014 Free Software Foundation, Inc.
3 Contributed by Apple Computer Inc.
5 This file is part of GCC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 (define_insn "adddi3_high"
22 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
23 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
24 (high:DI (match_operand 2 "" ""))))]
25 "TARGET_MACHO && TARGET_64BIT"
26 "addis %0,%1,ha16(%2)"
27 [(set_attr "length" "4")])
29 (define_insn "movdf_low_si"
30 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
31 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
32 (match_operand 2 "" ""))))]
33 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
36 switch (which_alternative)
39 return \"lfd %0,lo16(%2)(%1)\";
42 if (TARGET_POWERPC64 && TARGET_32BIT)
43 /* Note, old assemblers didn't support relocation here. */
44 return \"ld %0,lo16(%2)(%1)\";
47 output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
48 output_asm_insn (\"lwz %L0,4(%0)\", operands);
49 return (\"lwz %0,0(%0)\");
56 [(set_attr "type" "load")
57 (set_attr "length" "4,12")])
60 (define_insn "movdf_low_di"
61 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
62 (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
63 (match_operand 2 "" ""))))]
64 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
67 switch (which_alternative)
70 return \"lfd %0,lo16(%2)(%1)\";
72 return \"ld %0,lo16(%2)(%1)\";
77 [(set_attr "type" "load")
78 (set_attr "length" "4,4")])
80 (define_insn "movdf_low_st_si"
81 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
82 (match_operand 2 "" "")))
83 (match_operand:DF 0 "gpc_reg_operand" "f"))]
84 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
85 "stfd %0,lo16(%2)(%1)"
86 [(set_attr "type" "store")
87 (set_attr "length" "4")])
89 (define_insn "movdf_low_st_di"
90 [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
91 (match_operand 2 "" "")))
92 (match_operand:DF 0 "gpc_reg_operand" "f"))]
93 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
94 "stfd %0,lo16(%2)(%1)"
95 [(set_attr "type" "store")
96 (set_attr "length" "4")])
98 (define_insn "movsf_low_si"
99 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
100 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
101 (match_operand 2 "" ""))))]
102 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
106 [(set_attr "type" "load")
107 (set_attr "length" "4")])
109 (define_insn "movsf_low_di"
110 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
111 (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
112 (match_operand 2 "" ""))))]
113 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
117 [(set_attr "type" "load")
118 (set_attr "length" "4")])
120 (define_insn "movsf_low_st_si"
121 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
122 (match_operand 2 "" "")))
123 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
124 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
128 [(set_attr "type" "store")
129 (set_attr "length" "4")])
131 (define_insn "movsf_low_st_di"
132 [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
133 (match_operand 2 "" "")))
134 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
135 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
139 [(set_attr "type" "store")
140 (set_attr "length" "4")])
142 ;; 64-bit MachO load/store support
143 (define_insn "movdi_low"
144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d")
145 (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
146 (match_operand 2 "" ""))))]
147 "TARGET_MACHO && TARGET_64BIT"
151 [(set_attr "type" "load")
152 (set_attr "length" "4")])
154 (define_insn "movsi_low_st"
155 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
156 (match_operand 2 "" "")))
157 (match_operand:SI 0 "gpc_reg_operand" "r"))]
158 "TARGET_MACHO && ! TARGET_64BIT"
159 "stw %0,lo16(%2)(%1)"
160 [(set_attr "type" "store")
161 (set_attr "length" "4")])
163 (define_insn "movdi_low_st"
164 [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
165 (match_operand 2 "" "")))
166 (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
167 "TARGET_MACHO && TARGET_64BIT"
170 stfd %0,lo16(%2)(%1)"
171 [(set_attr "type" "store")
172 (set_attr "length" "4")])
174 ;; Mach-O PIC trickery.
175 (define_expand "macho_high"
176 [(set (match_operand 0 "" "")
177 (high (match_operand 1 "" "")))]
181 emit_insn (gen_macho_high_di (operands[0], operands[1]));
183 emit_insn (gen_macho_high_si (operands[0], operands[1]));
188 (define_insn "macho_high_si"
189 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
190 (high:SI (match_operand 1 "" "")))]
191 "TARGET_MACHO && ! TARGET_64BIT"
195 (define_insn "macho_high_di"
196 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
197 (high:DI (match_operand 1 "" "")))]
198 "TARGET_MACHO && TARGET_64BIT"
201 (define_expand "macho_low"
202 [(set (match_operand 0 "" "")
203 (lo_sum (match_operand 1 "" "")
204 (match_operand 2 "" "")))]
208 emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
210 emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
215 (define_insn "macho_low_si"
216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
217 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
218 (match_operand 2 "" "")))]
219 "TARGET_MACHO && ! TARGET_64BIT"
222 addic %0,%1,lo16(%2)")
224 (define_insn "macho_low_di"
225 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
226 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
227 (match_operand 2 "" "")))]
228 "TARGET_MACHO && TARGET_64BIT"
231 addic %0,%1,lo16(%2)")
234 [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
235 (match_operand:DI 1 "short_cint_operand" "")))
236 (match_operand:V4SI 2 "register_operand" ""))
237 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
238 "TARGET_MACHO && TARGET_64BIT"
239 [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
240 (set (mem:V4SI (match_dup 3))
244 (define_expand "load_macho_picbase"
246 (unspec [(match_operand 0 "" "")]
248 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
251 emit_insn (gen_load_macho_picbase_si (operands[0]));
253 emit_insn (gen_load_macho_picbase_di (operands[0]));
258 (define_insn "load_macho_picbase_si"
260 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
261 (pc)] UNSPEC_LD_MPIC))]
262 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
265 machopic_should_output_picbase_label (); /* Update for new func. */
269 return "bcl 20,31,%0\\n%0:";
271 [(set_attr "type" "branch")
272 (set_attr "length" "4")])
274 (define_insn "load_macho_picbase_di"
276 (unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
277 (pc)] UNSPEC_LD_MPIC))]
278 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
281 machopic_should_output_picbase_label (); /* Update for new func. */
285 return "bcl 20,31,%0\\n%0:";
287 [(set_attr "type" "branch")
288 (set_attr "length" "4")])
290 (define_expand "macho_correct_pic"
291 [(set (match_operand 0 "" "")
292 (plus (match_operand 1 "" "")
293 (unspec [(match_operand 2 "" "")
294 (match_operand 3 "" "")]
295 UNSPEC_MPIC_CORRECT)))]
296 "DEFAULT_ABI == ABI_DARWIN"
299 emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
302 emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
308 (define_insn "macho_correct_pic_si"
309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
310 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
311 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
312 (match_operand:SI 3 "immediate_operand" "s")]
313 UNSPEC_MPIC_CORRECT)))]
314 "DEFAULT_ABI == ABI_DARWIN"
315 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
316 [(set_attr "length" "8")])
318 (define_insn "macho_correct_pic_di"
319 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
320 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
321 (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
322 (match_operand:DI 3 "immediate_operand" "s")]
324 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
325 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
326 [(set_attr "length" "8")])
328 (define_insn "*call_indirect_nonlocal_darwin64"
329 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
330 (match_operand 1 "" "g,g,g,g"))
331 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
332 (clobber (reg:SI 65))]
333 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
337 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
338 (set_attr "length" "4,4,8,8")])
340 (define_insn "*call_nonlocal_darwin64"
341 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
342 (match_operand 1 "" "g,g"))
343 (use (match_operand:SI 2 "immediate_operand" "O,n"))
344 (clobber (reg:SI 65))]
345 "(DEFAULT_ABI == ABI_DARWIN)
346 && (INTVAL (operands[2]) & CALL_LONG) == 0"
349 return output_call(insn, operands, 0, 2);
354 [(set_attr "type" "branch,branch")
355 (set_attr "length" "4,8")])
357 (define_insn "*call_value_indirect_nonlocal_darwin64"
358 [(set (match_operand 0 "" "")
359 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
360 (match_operand 2 "" "g,g,g,g")))
361 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
362 (clobber (reg:SI 65))]
363 "DEFAULT_ABI == ABI_DARWIN"
367 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
368 (set_attr "length" "4,4,8,8")])
370 (define_insn "*call_value_nonlocal_darwin64"
371 [(set (match_operand 0 "" "")
372 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
373 (match_operand 2 "" "g,g")))
374 (use (match_operand:SI 3 "immediate_operand" "O,n"))
375 (clobber (reg:SI 65))]
376 "(DEFAULT_ABI == ABI_DARWIN)
377 && (INTVAL (operands[3]) & CALL_LONG) == 0"
380 return output_call(insn, operands, 1, 3);
385 [(set_attr "type" "branch,branch")
386 (set_attr "length" "4,8")])
388 (define_expand "reload_macho_picbase"
390 (unspec [(match_operand 0 "" "")]
392 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
395 emit_insn (gen_reload_macho_picbase_si (operands[0]));
397 emit_insn (gen_reload_macho_picbase_di (operands[0]));
402 (define_insn "reload_macho_picbase_si"
404 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
405 (pc)] UNSPEC_RELD_MPIC))]
406 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
409 if (machopic_should_output_picbase_label ())
412 const char *cnam = machopic_get_function_picbase ();
413 snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
420 return "bcl 20,31,%0\\n%0:";
422 [(set_attr "type" "branch")
423 (set_attr "length" "4")])
425 (define_insn "reload_macho_picbase_di"
427 (unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
428 (pc)] UNSPEC_RELD_MPIC))]
429 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
432 if (machopic_should_output_picbase_label ())
435 const char *cnam = machopic_get_function_picbase ();
436 snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam);
443 return "bcl 20,31,%0\\n%0:";
445 [(set_attr "type" "branch")
446 (set_attr "length" "4")])
448 ;; We need to restore the PIC register, at the site of nonlocal label.
450 (define_insn_and_split "nonlocal_goto_receiver"
451 [(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
452 "TARGET_MACHO && flag_pic"
454 "&& reload_completed"
458 if (crtl->uses_pic_offset_table)
460 static unsigned n = 0;
461 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
462 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
466 ASM_GENERATE_INTERNAL_LABEL(tmplab, "Lnlgr", ++n);
467 tmplrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
469 emit_insn (gen_reload_macho_picbase (tmplrtx));
470 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
471 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplrtx));
474 /* Not using PIC reg, no reload needed. */
475 emit_note (NOTE_INSN_DELETED);