gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* Maximum register number, which is the size of the tables below.  */
 143
 144 static unsigned int combine_max_regno;
 145
 146 struct reg_stat {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 };
 254
 255 static struct reg_stat *reg_stat;
 256
 257 /* Record the cuid of the last insn that invalidated memory
 258    (anything that writes memory, and subroutine calls, but not pushes).  */
 259
 260 static int mem_last_set;
 261
 262 /* Record the cuid of the last CALL_INSN
 263    so we can tell whether a potential combination crosses any calls.  */
 264
 265 static int last_call_cuid;
 266
 267 /* When `subst' is called, this is the insn that is being modified
 268    (by combining in a previous insn).  The PATTERN of this insn
 269    is still the old pattern partially modified and it should not be
 270    looked at, but this may be used to examine the successors of the insn
 271    to judge whether a simplification is valid.  */
 272
 273 static rtx subst_insn;
 274
 275 /* This is the lowest CUID that `subst' is currently dealing with.
 276    get_last_value will not return a value if the register was set at or
 277    after this CUID.  If not for this mechanism, we could get confused if
 278    I2 or I1 in try_combine were an insn that used the old value of a register
 279    to obtain a new value.  In that case, we might erroneously get the
 280    new value of the register when we wanted the old one.  */
 281
 282 static int subst_low_cuid;
 283
 284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 285    must consider all these registers to be always live.  */
 286
 287 static HARD_REG_SET newpat_used_regs;
 288
 289 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 290    insn is the earlier than I2 or I3, combine should rescan starting at
 291    that location.  */
 292
 293 static rtx added_links_insn;
 294
 295 /* Basic block in which we are performing combines.  */
 296 static basic_block this_basic_block;
 297
 298 /* A bitmap indicating which blocks had registers go dead at entry.
 299    After combine, we'll need to re-do global life analysis with
 300    those blocks as starting points.  */
 301 static sbitmap refresh_blocks;
 302 \f
 303 /* The following array records the insn_rtx_cost for every insn
 304    in the instruction stream.  */
 305
 306 static int *uid_insn_cost;
 307
 308 /* Length of the currently allocated uid_insn_cost array.  */
 309
 310 static int last_insn_cost;
 311
 312 /* Incremented for each label.  */
 313
 314 static int label_tick;
 315
 316 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 317    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 318
 319 static enum machine_mode nonzero_bits_mode;
 320
 321 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 322    be safely used.  It is zero while computing them and after combine has
 323    completed.  This former test prevents propagating values based on
 324    previously set values, which can be incorrect if a variable is modified
 325    in a loop.  */
 326
 327 static int nonzero_sign_valid;
 328
 329 \f
 330 /* Record one modification to rtl structure
 331    to be undone by storing old_contents into *where.  */
 332
 333 struct undo
 334 {
 335   struct undo *next;
 336   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 337   union { rtx r; int i; enum machine_mode m; } old_contents;
 338   union { rtx *r; int *i; } where;
 339 };
 340
 341 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 342    num_undo says how many are currently recorded.
 343
 344    other_insn is nonzero if we have modified some other insn in the process
 345    of working on subst_insn.  It must be verified too.  */
 346
 347 struct undobuf
 348 {
 349   struct undo *undos;
 350   struct undo *frees;
 351   rtx other_insn;
 352 };
 353
 354 static struct undobuf undobuf;
 355
 356 /* Number of times the pseudo being substituted for
 357    was found and replaced.  */
 358
 359 static int n_occurrences;
 360
 361 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 362                                          enum machine_mode,
 363                                          unsigned HOST_WIDE_INT,
 364                                          unsigned HOST_WIDE_INT *);
 365 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 366                                                 enum machine_mode,
 367                                                 unsigned int, unsigned int *);
 368 static void do_SUBST (rtx *, rtx);
 369 static void do_SUBST_INT (int *, int);
 370 static void init_reg_last (void);
 371 static void setup_incoming_promotions (void);
 372 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 373 static int cant_combine_insn_p (rtx);
 374 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 375 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 376 static int contains_muldiv (rtx);
 377 static rtx try_combine (rtx, rtx, rtx, int *);
 378 static void undo_all (void);
 379 static void undo_commit (void);
 380 static rtx *find_split_point (rtx *, rtx);
 381 static rtx subst (rtx, rtx, rtx, int, int);
 382 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 383 static rtx simplify_if_then_else (rtx);
 384 static rtx simplify_set (rtx);
 385 static rtx simplify_logical (rtx);
 386 static rtx expand_compound_operation (rtx);
 387 static rtx expand_field_assignment (rtx);
 388 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 389                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 390 static rtx extract_left_shift (rtx, int);
 391 static rtx make_compound_operation (rtx, enum rtx_code);
 392 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 393                               unsigned HOST_WIDE_INT *);
 394 static rtx canon_reg_for_combine (rtx, rtx);
 395 static rtx force_to_mode (rtx, enum machine_mode,
 396                           unsigned HOST_WIDE_INT, int);
 397 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 398 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 399 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 400 static rtx make_field_assignment (rtx);
 401 static rtx apply_distributive_law (rtx);
 402 static rtx distribute_and_simplify_rtx (rtx, int);
 403 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 404                                      unsigned HOST_WIDE_INT);
 405 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 406                                    unsigned HOST_WIDE_INT);
 407 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 408                             HOST_WIDE_INT, enum machine_mode, int *);
 409 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 410 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 411                                  int);
 412 static int recog_for_combine (rtx *, rtx, rtx *);
 413 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 414 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 415 static void update_table_tick (rtx);
 416 static void record_value_for_reg (rtx, rtx, rtx);
 417 static void check_conversions (rtx, rtx);
 418 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 419 static void record_dead_and_set_regs (rtx);
 420 static int get_last_value_validate (rtx *, rtx, int, int);
 421 static rtx get_last_value (rtx);
 422 static int use_crosses_set_p (rtx, int);
 423 static void reg_dead_at_p_1 (rtx, rtx, void *);
 424 static int reg_dead_at_p (rtx, rtx);
 425 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 426 static int reg_bitfield_target_p (rtx, rtx);
 427 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 428 static void distribute_links (rtx);
 429 static void mark_used_regs_combine (rtx);
 430 static int insn_cuid (rtx);
 431 static void record_promoted_value (rtx, rtx);
 432 static int unmentioned_reg_p_1 (rtx *, void *);
 433 static bool unmentioned_reg_p (rtx, rtx);
 434 static void record_truncated_value (rtx);
 435 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 436 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 437 \f
 438
 439 /* It is not safe to use ordinary gen_lowpart in combine.
 440    See comments in gen_lowpart_for_combine.  */
 441 #undef RTL_HOOKS_GEN_LOWPART
 442 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 443
 444 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 445 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 446 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 447
 448 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 449 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 450
 451 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 452 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 453
 454 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 455 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 456
 457 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 458
 459 \f
 460 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 461    insn.  The substitution can be undone by undo_all.  If INTO is already
 462    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 463    also call SUBST, we have to compute it before we put anything into
 464    the undo table.  */
 465
 466 static void
 467 do_SUBST (rtx *into, rtx newval)
 468 {
 469   struct undo *buf;
 470   rtx oldval = *into;
 471
 472   if (oldval == newval)
 473     return;
 474
 475   /* We'd like to catch as many invalid transformations here as
 476      possible.  Unfortunately, there are way too many mode changes
 477      that are perfectly valid, so we'd waste too much effort for
 478      little gain doing the checks here.  Focus on catching invalid
 479      transformations involving integer constants.  */
 480   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 481       && GET_CODE (newval) == CONST_INT)
 482     {
 483       /* Sanity check that we're replacing oldval with a CONST_INT
 484          that is a valid sign-extension for the original mode.  */
 485       gcc_assert (INTVAL (newval)
 486                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 487
 488       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 489          CONST_INT is not valid, because after the replacement, the
 490          original mode would be gone.  Unfortunately, we can't tell
 491          when do_SUBST is called to replace the operand thereof, so we
 492          perform this test on oldval instead, checking whether an
 493          invalid replacement took place before we got here.  */
 494       gcc_assert (!(GET_CODE (oldval) == SUBREG
 495                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 496       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 497                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 498     }
 499
 500   if (undobuf.frees)
 501     buf = undobuf.frees, undobuf.frees = buf->next;
 502   else
 503     buf = XNEW (struct undo);
 504
 505   buf->kind = UNDO_RTX;
 506   buf->where.r = into;
 507   buf->old_contents.r = oldval;
 508   *into = newval;
 509
 510   buf->next = undobuf.undos, undobuf.undos = buf;
 511 }
 512
 513 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 514
 515 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 516    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 517    not safe.  */
 518
 519 static void
 520 do_SUBST_INT (int *into, int newval)
 521 {
 522   struct undo *buf;
 523   int oldval = *into;
 524
 525   if (oldval == newval)
 526     return;
 527
 528   if (undobuf.frees)
 529     buf = undobuf.frees, undobuf.frees = buf->next;
 530   else
 531     buf = XNEW (struct undo);
 532
 533   buf->kind = UNDO_INT;
 534   buf->where.i = into;
 535   buf->old_contents.i = oldval;
 536   *into = newval;
 537
 538   buf->next = undobuf.undos, undobuf.undos = buf;
 539 }
 540
 541 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 542
 543 /* Similar to SUBST, but just substitute the mode.  This is used when
 544    changing the mode of a pseudo-register, so that any other
 545    references to the entry in the regno_reg_rtx array will change as
 546    well.  */
 547
 548 static void
 549 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 550 {
 551   struct undo *buf;
 552   enum machine_mode oldval = GET_MODE (*into);
 553
 554   if (oldval == newval)
 555     return;
 556
 557   if (undobuf.frees)
 558     buf = undobuf.frees, undobuf.frees = buf->next;
 559   else
 560     buf = XNEW (struct undo);
 561
 562   buf->kind = UNDO_MODE;
 563   buf->where.r = into;
 564   buf->old_contents.m = oldval;
 565   PUT_MODE (*into, newval);
 566
 567   buf->next = undobuf.undos, undobuf.undos = buf;
 568 }
 569
 570 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 571 \f
 572 /* Subroutine of try_combine.  Determine whether the combine replacement
 573    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 574    that the original instruction sequence I1, I2 and I3.  Note that I1
 575    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 576    costs of all instructions can be estimated, and the replacements are
 577    more expensive than the original sequence.  */
 578
 579 static bool
 580 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 581 {
 582   int i1_cost, i2_cost, i3_cost;
 583   int new_i2_cost, new_i3_cost;
 584   int old_cost, new_cost;
 585
 586   /* Lookup the original insn_rtx_costs.  */
 587   i2_cost = INSN_UID (i2) <= last_insn_cost
 588             ? uid_insn_cost[INSN_UID (i2)] : 0;
 589   i3_cost = INSN_UID (i3) <= last_insn_cost
 590             ? uid_insn_cost[INSN_UID (i3)] : 0;
 591
 592   if (i1)
 593     {
 594       i1_cost = INSN_UID (i1) <= last_insn_cost
 595                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 596       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 597                  ? i1_cost + i2_cost + i3_cost : 0;
 598     }
 599   else
 600     {
 601       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 602       i1_cost = 0;
 603     }
 604
 605   /* Calculate the replacement insn_rtx_costs.  */
 606   new_i3_cost = insn_rtx_cost (newpat);
 607   if (newi2pat)
 608     {
 609       new_i2_cost = insn_rtx_cost (newi2pat);
 610       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 611                  ? new_i2_cost + new_i3_cost : 0;
 612     }
 613   else
 614     {
 615       new_cost = new_i3_cost;
 616       new_i2_cost = 0;
 617     }
 618
 619   if (undobuf.other_insn)
 620     {
 621       int old_other_cost, new_other_cost;
 622
 623       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 624                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 625       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 626       if (old_other_cost > 0 && new_other_cost > 0)
 627         {
 628           old_cost += old_other_cost;
 629           new_cost += new_other_cost;
 630         }
 631       else
 632         old_cost = 0;
 633     }
 634
 635   /* Disallow this recombination if both new_cost and old_cost are
 636      greater than zero, and new_cost is greater than old cost.  */
 637   if (old_cost > 0
 638       && new_cost > old_cost)
 639     {
 640       if (dump_file)
 641         {
 642           if (i1)
 643             {
 644               fprintf (dump_file,
 645                        "rejecting combination of insns %d, %d and %d\n",
 646                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 647               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 648                        i1_cost, i2_cost, i3_cost, old_cost);
 649             }
 650           else
 651             {
 652               fprintf (dump_file,
 653                        "rejecting combination of insns %d and %d\n",
 654                        INSN_UID (i2), INSN_UID (i3));
 655               fprintf (dump_file, "original costs %d + %d = %d\n",
 656                        i2_cost, i3_cost, old_cost);
 657             }
 658
 659           if (newi2pat)
 660             {
 661               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 662                        new_i2_cost, new_i3_cost, new_cost);
 663             }
 664           else
 665             fprintf (dump_file, "replacement cost %d\n", new_cost);
 666         }
 667
 668       return false;
 669     }
 670
 671   /* Update the uid_insn_cost array with the replacement costs.  */
 672   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 673   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 674   if (i1)
 675     uid_insn_cost[INSN_UID (i1)] = 0;
 676
 677   return true;
 678 }
 679 \f
 680 /* Main entry point for combiner.  F is the first insn of the function.
 681    NREGS is the first unused pseudo-reg number.
 682
 683    Return nonzero if the combiner has turned an indirect jump
 684    instruction into a direct jump.  */
 685 static int
 686 combine_instructions (rtx f, unsigned int nregs)
 687 {
 688   rtx insn, next;
 689 #ifdef HAVE_cc0
 690   rtx prev;
 691 #endif
 692   int i;
 693   unsigned int j = 0;
 694   rtx links, nextlinks;
 695   sbitmap_iterator sbi;
 696
 697   int new_direct_jump_p = 0;
 698
 699   combine_attempts = 0;
 700   combine_merges = 0;
 701   combine_extras = 0;
 702   combine_successes = 0;
 703
 704   combine_max_regno = nregs;
 705
 706   rtl_hooks = combine_rtl_hooks;
 707
 708   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 709
 710   init_recog_no_volatile ();
 711
 712   /* Compute maximum uid value so uid_cuid can be allocated.  */
 713
 714   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 715     if (INSN_UID (insn) > i)
 716       i = INSN_UID (insn);
 717
 718   uid_cuid = XNEWVEC (int, i + 1);
 719   max_uid_cuid = i;
 720
 721   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 722
 723   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 724      problems when, for example, we have j <<= 1 in a loop.  */
 725
 726   nonzero_sign_valid = 0;
 727
 728   /* Compute the mapping from uids to cuids.
 729      Cuids are numbers assigned to insns, like uids,
 730      except that cuids increase monotonically through the code.
 731
 732      Scan all SETs and see if we can deduce anything about what
 733      bits are known to be zero for some registers and how many copies
 734      of the sign bit are known to exist for those registers.
 735
 736      Also set any known values so that we can use it while searching
 737      for what bits are known to be set.  */
 738
 739   label_tick = 1;
 740
 741   setup_incoming_promotions ();
 742
 743   refresh_blocks = sbitmap_alloc (last_basic_block);
 744   sbitmap_zero (refresh_blocks);
 745
 746   /* Allocate array of current insn_rtx_costs.  */
 747   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 748   last_insn_cost = max_uid_cuid;
 749
 750   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 751     {
 752       uid_cuid[INSN_UID (insn)] = ++i;
 753       subst_low_cuid = i;
 754       subst_insn = insn;
 755
 756       if (INSN_P (insn))
 757         {
 758           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 759                        NULL);
 760           record_dead_and_set_regs (insn);
 761
 762 #ifdef AUTO_INC_DEC
 763           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 764             if (REG_NOTE_KIND (links) == REG_INC)
 765               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 766                                                 NULL);
 767 #endif
 768
 769           /* Record the current insn_rtx_cost of this instruction.  */
 770           if (NONJUMP_INSN_P (insn))
 771             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 772           if (dump_file)
 773             fprintf(dump_file, "insn_cost %d: %d\n",
 774                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 775         }
 776
 777       if (LABEL_P (insn))
 778         label_tick++;
 779     }
 780
 781   nonzero_sign_valid = 1;
 782
 783   /* Now scan all the insns in forward order.  */
 784
 785   label_tick = 1;
 786   last_call_cuid = 0;
 787   mem_last_set = 0;
 788   init_reg_last ();
 789   setup_incoming_promotions ();
 790
 791   FOR_EACH_BB (this_basic_block)
 792     {
 793       for (insn = BB_HEAD (this_basic_block);
 794            insn != NEXT_INSN (BB_END (this_basic_block));
 795            insn = next ? next : NEXT_INSN (insn))
 796         {
 797           next = 0;
 798
 799           if (LABEL_P (insn))
 800             label_tick++;
 801
 802           else if (INSN_P (insn))
 803             {
 804               /* See if we know about function return values before this
 805                  insn based upon SUBREG flags.  */
 806               check_conversions (insn, PATTERN (insn));
 807
 808               /* Try this insn with each insn it links back to.  */
 809
 810               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 811                 if ((next = try_combine (insn, XEXP (links, 0),
 812                                          NULL_RTX, &new_direct_jump_p)) != 0)
 813                   goto retry;
 814
 815               /* Try each sequence of three linked insns ending with this one.  */
 816
 817               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 818                 {
 819                   rtx link = XEXP (links, 0);
 820
 821                   /* If the linked insn has been replaced by a note, then there
 822                      is no point in pursuing this chain any further.  */
 823                   if (NOTE_P (link))
 824                     continue;
 825
 826                   for (nextlinks = LOG_LINKS (link);
 827                        nextlinks;
 828                        nextlinks = XEXP (nextlinks, 1))
 829                     if ((next = try_combine (insn, link,
 830                                              XEXP (nextlinks, 0),
 831                                              &new_direct_jump_p)) != 0)
 832                       goto retry;
 833                 }
 834
 835 #ifdef HAVE_cc0
 836               /* Try to combine a jump insn that uses CC0
 837                  with a preceding insn that sets CC0, and maybe with its
 838                  logical predecessor as well.
 839                  This is how we make decrement-and-branch insns.
 840                  We need this special code because data flow connections
 841                  via CC0 do not get entered in LOG_LINKS.  */
 842
 843               if (JUMP_P (insn)
 844                   && (prev = prev_nonnote_insn (insn)) != 0
 845                   && NONJUMP_INSN_P (prev)
 846                   && sets_cc0_p (PATTERN (prev)))
 847                 {
 848                   if ((next = try_combine (insn, prev,
 849                                            NULL_RTX, &new_direct_jump_p)) != 0)
 850                     goto retry;
 851
 852                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 853                        nextlinks = XEXP (nextlinks, 1))
 854                     if ((next = try_combine (insn, prev,
 855                                              XEXP (nextlinks, 0),
 856                                              &new_direct_jump_p)) != 0)
 857                       goto retry;
 858                 }
 859
 860               /* Do the same for an insn that explicitly references CC0.  */
 861               if (NONJUMP_INSN_P (insn)
 862                   && (prev = prev_nonnote_insn (insn)) != 0
 863                   && NONJUMP_INSN_P (prev)
 864                   && sets_cc0_p (PATTERN (prev))
 865                   && GET_CODE (PATTERN (insn)) == SET
 866                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 867                 {
 868                   if ((next = try_combine (insn, prev,
 869                                            NULL_RTX, &new_direct_jump_p)) != 0)
 870                     goto retry;
 871
 872                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 873                        nextlinks = XEXP (nextlinks, 1))
 874                     if ((next = try_combine (insn, prev,
 875                                              XEXP (nextlinks, 0),
 876                                              &new_direct_jump_p)) != 0)
 877                       goto retry;
 878                 }
 879
 880               /* Finally, see if any of the insns that this insn links to
 881                  explicitly references CC0.  If so, try this insn, that insn,
 882                  and its predecessor if it sets CC0.  */
 883               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 884                 if (NONJUMP_INSN_P (XEXP (links, 0))
 885                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 886                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 887                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 888                     && NONJUMP_INSN_P (prev)
 889                     && sets_cc0_p (PATTERN (prev))
 890                     && (next = try_combine (insn, XEXP (links, 0),
 891                                             prev, &new_direct_jump_p)) != 0)
 892                   goto retry;
 893 #endif
 894
 895               /* Try combining an insn with two different insns whose results it
 896                  uses.  */
 897               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 898                 for (nextlinks = XEXP (links, 1); nextlinks;
 899                      nextlinks = XEXP (nextlinks, 1))
 900                   if ((next = try_combine (insn, XEXP (links, 0),
 901                                            XEXP (nextlinks, 0),
 902                                            &new_direct_jump_p)) != 0)
 903                     goto retry;
 904
 905               /* Try this insn with each REG_EQUAL note it links back to.  */
 906               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 907                 {
 908                   rtx set, note;
 909                   rtx temp = XEXP (links, 0);
 910                   if ((set = single_set (temp)) != 0
 911                       && (note = find_reg_equal_equiv_note (temp)) != 0
 912                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 913                       /* Avoid using a register that may already been marked
 914                          dead by an earlier instruction.  */
 915                       && ! unmentioned_reg_p (note, SET_SRC (set))
 916                       && (GET_MODE (note) == VOIDmode
 917                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 918                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 919                     {
 920                       /* Temporarily replace the set's source with the
 921                          contents of the REG_EQUAL note.  The insn will
 922                          be deleted or recognized by try_combine.  */
 923                       rtx orig = SET_SRC (set);
 924                       SET_SRC (set) = note;
 925                       next = try_combine (insn, temp, NULL_RTX,
 926                                           &new_direct_jump_p);
 927                       if (next)
 928                         goto retry;
 929                       SET_SRC (set) = orig;
 930                     }
 931                 }
 932
 933               if (!NOTE_P (insn))
 934                 record_dead_and_set_regs (insn);
 935
 936             retry:
 937               ;
 938             }
 939         }
 940     }
 941   clear_bb_flags ();
 942
 943   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 944     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 945   new_direct_jump_p |= purge_all_dead_edges ();
 946   delete_noop_moves ();
 947
 948   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 949                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 950                                     | PROP_KILL_DEAD_CODE);
 951
 952   /* Clean up.  */
 953   sbitmap_free (refresh_blocks);
 954   free (uid_insn_cost);
 955   free (reg_stat);
 956   free (uid_cuid);
 957
 958   {
 959     struct undo *undo, *next;
 960     for (undo = undobuf.frees; undo; undo = next)
 961       {
 962         next = undo->next;
 963         free (undo);
 964       }
 965     undobuf.frees = 0;
 966   }
 967
 968   total_attempts += combine_attempts;
 969   total_merges += combine_merges;
 970   total_extras += combine_extras;
 971   total_successes += combine_successes;
 972
 973   nonzero_sign_valid = 0;
 974   rtl_hooks = general_rtl_hooks;
 975
 976   /* Make recognizer allow volatile MEMs again.  */
 977   init_recog ();
 978
 979   return new_direct_jump_p;
 980 }
 981
 982 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 983
 984 static void
 985 init_reg_last (void)
 986 {
 987   unsigned int i;
 988   for (i = 0; i < combine_max_regno; i++)
 989     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 990 }
 991 \f
 992 /* Set up any promoted values for incoming argument registers.  */
 993
 994 static void
 995 setup_incoming_promotions (void)
 996 {
 997   unsigned int regno;
 998   rtx reg;
 999   enum machine_mode mode;
1000   int unsignedp;
1001   rtx first = get_insns ();
1002
1003   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1004     {
1005       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1006         /* Check whether this register can hold an incoming pointer
1007            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1008            numbers, so translate if necessary due to register windows.  */
1009         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1010             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1011           {
1012             record_value_for_reg
1013               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1014                                            : SIGN_EXTEND),
1015                                           GET_MODE (reg),
1016                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1017           }
1018     }
1019 }
1020 \f
1021 /* Called via note_stores.  If X is a pseudo that is narrower than
1022    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1023
1024    If we are setting only a portion of X and we can't figure out what
1025    portion, assume all bits will be used since we don't know what will
1026    be happening.
1027
1028    Similarly, set how many bits of X are known to be copies of the sign bit
1029    at all locations in the function.  This is the smallest number implied
1030    by any set of X.  */
1031
1032 static void
1033 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1034                                   void *data ATTRIBUTE_UNUSED)
1035 {
1036   unsigned int num;
1037
1038   if (REG_P (x)
1039       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1040       /* If this register is undefined at the start of the file, we can't
1041          say what its contents were.  */
1042       && ! REGNO_REG_SET_P
1043          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1044       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1045     {
1046       if (set == 0 || GET_CODE (set) == CLOBBER)
1047         {
1048           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1049           reg_stat[REGNO (x)].sign_bit_copies = 1;
1050           return;
1051         }
1052
1053       /* If this is a complex assignment, see if we can convert it into a
1054          simple assignment.  */
1055       set = expand_field_assignment (set);
1056
1057       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1058          set what we know about X.  */
1059
1060       if (SET_DEST (set) == x
1061           || (GET_CODE (SET_DEST (set)) == SUBREG
1062               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1063                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1064               && SUBREG_REG (SET_DEST (set)) == x))
1065         {
1066           rtx src = SET_SRC (set);
1067
1068 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1069           /* If X is narrower than a word and SRC is a non-negative
1070              constant that would appear negative in the mode of X,
1071              sign-extend it for use in reg_stat[].nonzero_bits because some
1072              machines (maybe most) will actually do the sign-extension
1073              and this is the conservative approach.
1074
1075              ??? For 2.5, try to tighten up the MD files in this regard
1076              instead of this kludge.  */
1077
1078           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1079               && GET_CODE (src) == CONST_INT
1080               && INTVAL (src) > 0
1081               && 0 != (INTVAL (src)
1082                        & ((HOST_WIDE_INT) 1
1083                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1084             src = GEN_INT (INTVAL (src)
1085                            | ((HOST_WIDE_INT) (-1)
1086                               << GET_MODE_BITSIZE (GET_MODE (x))));
1087 #endif
1088
1089           /* Don't call nonzero_bits if it cannot change anything.  */
1090           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1091             reg_stat[REGNO (x)].nonzero_bits
1092               |= nonzero_bits (src, nonzero_bits_mode);
1093           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1094           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1095               || reg_stat[REGNO (x)].sign_bit_copies > num)
1096             reg_stat[REGNO (x)].sign_bit_copies = num;
1097         }
1098       else
1099         {
1100           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1101           reg_stat[REGNO (x)].sign_bit_copies = 1;
1102         }
1103     }
1104 }
1105 \f
1106 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1107    insns that were previously combined into I3 or that will be combined
1108    into the merger of INSN and I3.
1109
1110    Return 0 if the combination is not allowed for any reason.
1111
1112    If the combination is allowed, *PDEST will be set to the single
1113    destination of INSN and *PSRC to the single source, and this function
1114    will return 1.  */
1115
1116 static int
1117 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1118                rtx *pdest, rtx *psrc)
1119 {
1120   int i;
1121   rtx set = 0, src, dest;
1122   rtx p;
1123 #ifdef AUTO_INC_DEC
1124   rtx link;
1125 #endif
1126   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1127                               && next_active_insn (succ) == i3)
1128                       : next_active_insn (insn) == i3);
1129
1130   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1131      or a PARALLEL consisting of such a SET and CLOBBERs.
1132
1133      If INSN has CLOBBER parallel parts, ignore them for our processing.
1134      By definition, these happen during the execution of the insn.  When it
1135      is merged with another insn, all bets are off.  If they are, in fact,
1136      needed and aren't also supplied in I3, they may be added by
1137      recog_for_combine.  Otherwise, it won't match.
1138
1139      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1140      note.
1141
1142      Get the source and destination of INSN.  If more than one, can't
1143      combine.  */
1144
1145   if (GET_CODE (PATTERN (insn)) == SET)
1146     set = PATTERN (insn);
1147   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1148            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1149     {
1150       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1151         {
1152           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1153           rtx note;
1154
1155           switch (GET_CODE (elt))
1156             {
1157             /* This is important to combine floating point insns
1158                for the SH4 port.  */
1159             case USE:
1160               /* Combining an isolated USE doesn't make sense.
1161                  We depend here on combinable_i3pat to reject them.  */
1162               /* The code below this loop only verifies that the inputs of
1163                  the SET in INSN do not change.  We call reg_set_between_p
1164                  to verify that the REG in the USE does not change between
1165                  I3 and INSN.
1166                  If the USE in INSN was for a pseudo register, the matching
1167                  insn pattern will likely match any register; combining this
1168                  with any other USE would only be safe if we knew that the
1169                  used registers have identical values, or if there was
1170                  something to tell them apart, e.g. different modes.  For
1171                  now, we forgo such complicated tests and simply disallow
1172                  combining of USES of pseudo registers with any other USE.  */
1173               if (REG_P (XEXP (elt, 0))
1174                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1175                 {
1176                   rtx i3pat = PATTERN (i3);
1177                   int i = XVECLEN (i3pat, 0) - 1;
1178                   unsigned int regno = REGNO (XEXP (elt, 0));
1179
1180                   do
1181                     {
1182                       rtx i3elt = XVECEXP (i3pat, 0, i);
1183
1184                       if (GET_CODE (i3elt) == USE
1185                           && REG_P (XEXP (i3elt, 0))
1186                           && (REGNO (XEXP (i3elt, 0)) == regno
1187                               ? reg_set_between_p (XEXP (elt, 0),
1188                                                    PREV_INSN (insn), i3)
1189                               : regno >= FIRST_PSEUDO_REGISTER))
1190                         return 0;
1191                     }
1192                   while (--i >= 0);
1193                 }
1194               break;
1195
1196               /* We can ignore CLOBBERs.  */
1197             case CLOBBER:
1198               break;
1199
1200             case SET:
1201               /* Ignore SETs whose result isn't used but not those that
1202                  have side-effects.  */
1203               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1204                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1205                       || INTVAL (XEXP (note, 0)) <= 0)
1206                   && ! side_effects_p (elt))
1207                 break;
1208
1209               /* If we have already found a SET, this is a second one and
1210                  so we cannot combine with this insn.  */
1211               if (set)
1212                 return 0;
1213
1214               set = elt;
1215               break;
1216
1217             default:
1218               /* Anything else means we can't combine.  */
1219               return 0;
1220             }
1221         }
1222
1223       if (set == 0
1224           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1225              so don't do anything with it.  */
1226           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1227         return 0;
1228     }
1229   else
1230     return 0;
1231
1232   if (set == 0)
1233     return 0;
1234
1235   set = expand_field_assignment (set);
1236   src = SET_SRC (set), dest = SET_DEST (set);
1237
1238   /* Don't eliminate a store in the stack pointer.  */
1239   if (dest == stack_pointer_rtx
1240       /* Don't combine with an insn that sets a register to itself if it has
1241          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1242       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1243       /* Can't merge an ASM_OPERANDS.  */
1244       || GET_CODE (src) == ASM_OPERANDS
1245       /* Can't merge a function call.  */
1246       || GET_CODE (src) == CALL
1247       /* Don't eliminate a function call argument.  */
1248       || (CALL_P (i3)
1249           && (find_reg_fusage (i3, USE, dest)
1250               || (REG_P (dest)
1251                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1252                   && global_regs[REGNO (dest)])))
1253       /* Don't substitute into an incremented register.  */
1254       || FIND_REG_INC_NOTE (i3, dest)
1255       || (succ && FIND_REG_INC_NOTE (succ, dest))
1256       /* Don't substitute into a non-local goto, this confuses CFG.  */
1257       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1258 #if 0
1259       /* Don't combine the end of a libcall into anything.  */
1260       /* ??? This gives worse code, and appears to be unnecessary, since no
1261          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1262          use REG_RETVAL notes for noconflict blocks, but other code here
1263          makes sure that those insns don't disappear.  */
1264       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1265 #endif
1266       /* Make sure that DEST is not used after SUCC but before I3.  */
1267       || (succ && ! all_adjacent
1268           && reg_used_between_p (dest, succ, i3))
1269       /* Make sure that the value that is to be substituted for the register
1270          does not use any registers whose values alter in between.  However,
1271          If the insns are adjacent, a use can't cross a set even though we
1272          think it might (this can happen for a sequence of insns each setting
1273          the same destination; last_set of that register might point to
1274          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1275          equivalent to the memory so the substitution is valid even if there
1276          are intervening stores.  Also, don't move a volatile asm or
1277          UNSPEC_VOLATILE across any other insns.  */
1278       || (! all_adjacent
1279           && (((!MEM_P (src)
1280                 || ! find_reg_note (insn, REG_EQUIV, src))
1281                && use_crosses_set_p (src, INSN_CUID (insn)))
1282               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1283               || GET_CODE (src) == UNSPEC_VOLATILE))
1284       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1285          better register allocation by not doing the combine.  */
1286       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1287       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1288       /* Don't combine across a CALL_INSN, because that would possibly
1289          change whether the life span of some REGs crosses calls or not,
1290          and it is a pain to update that information.
1291          Exception: if source is a constant, moving it later can't hurt.
1292          Accept that special case, because it helps -fforce-addr a lot.  */
1293       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1294     return 0;
1295
1296   /* DEST must either be a REG or CC0.  */
1297   if (REG_P (dest))
1298     {
1299       /* If register alignment is being enforced for multi-word items in all
1300          cases except for parameters, it is possible to have a register copy
1301          insn referencing a hard register that is not allowed to contain the
1302          mode being copied and which would not be valid as an operand of most
1303          insns.  Eliminate this problem by not combining with such an insn.
1304
1305          Also, on some machines we don't want to extend the life of a hard
1306          register.  */
1307
1308       if (REG_P (src)
1309           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1310                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1311               /* Don't extend the life of a hard register unless it is
1312                  user variable (if we have few registers) or it can't
1313                  fit into the desired register (meaning something special
1314                  is going on).
1315                  Also avoid substituting a return register into I3, because
1316                  reload can't handle a conflict with constraints of other
1317                  inputs.  */
1318               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1319                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1320         return 0;
1321     }
1322   else if (GET_CODE (dest) != CC0)
1323     return 0;
1324
1325
1326   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1327     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1328       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1329         {
1330           /* Don't substitute for a register intended as a clobberable
1331              operand.  */
1332           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1333           if (rtx_equal_p (reg, dest))
1334             return 0;
1335
1336           /* If the clobber represents an earlyclobber operand, we must not
1337              substitute an expression containing the clobbered register.
1338              As we do not analyze the constraint strings here, we have to
1339              make the conservative assumption.  However, if the register is
1340              a fixed hard reg, the clobber cannot represent any operand;
1341              we leave it up to the machine description to either accept or
1342              reject use-and-clobber patterns.  */
1343           if (!REG_P (reg)
1344               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1345               || !fixed_regs[REGNO (reg)])
1346             if (reg_overlap_mentioned_p (reg, src))
1347               return 0;
1348         }
1349
1350   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1351      or not), reject, unless nothing volatile comes between it and I3 */
1352
1353   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1354     {
1355       /* Make sure succ doesn't contain a volatile reference.  */
1356       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1357         return 0;
1358
1359       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1360         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1361           return 0;
1362     }
1363
1364   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1365      to be an explicit register variable, and was chosen for a reason.  */
1366
1367   if (GET_CODE (src) == ASM_OPERANDS
1368       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1369     return 0;
1370
1371   /* If there are any volatile insns between INSN and I3, reject, because
1372      they might affect machine state.  */
1373
1374   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1375     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1376       return 0;
1377
1378   /* If INSN contains an autoincrement or autodecrement, make sure that
1379      register is not used between there and I3, and not already used in
1380      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1381      Also insist that I3 not be a jump; if it were one
1382      and the incremented register were spilled, we would lose.  */
1383
1384 #ifdef AUTO_INC_DEC
1385   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1386     if (REG_NOTE_KIND (link) == REG_INC
1387         && (JUMP_P (i3)
1388             || reg_used_between_p (XEXP (link, 0), insn, i3)
1389             || (pred != NULL_RTX
1390                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1391             || (succ != NULL_RTX
1392                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1393             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1394       return 0;
1395 #endif
1396
1397 #ifdef HAVE_cc0
1398   /* Don't combine an insn that follows a CC0-setting insn.
1399      An insn that uses CC0 must not be separated from the one that sets it.
1400      We do, however, allow I2 to follow a CC0-setting insn if that insn
1401      is passed as I1; in that case it will be deleted also.
1402      We also allow combining in this case if all the insns are adjacent
1403      because that would leave the two CC0 insns adjacent as well.
1404      It would be more logical to test whether CC0 occurs inside I1 or I2,
1405      but that would be much slower, and this ought to be equivalent.  */
1406
1407   p = prev_nonnote_insn (insn);
1408   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1409       && ! all_adjacent)
1410     return 0;
1411 #endif
1412
1413   /* If we get here, we have passed all the tests and the combination is
1414      to be allowed.  */
1415
1416   *pdest = dest;
1417   *psrc = src;
1418
1419   return 1;
1420 }
1421 \f
1422 /* LOC is the location within I3 that contains its pattern or the component
1423    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1424
1425    One problem is if I3 modifies its output, as opposed to replacing it
1426    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1427    so would produce an insn that is not equivalent to the original insns.
1428
1429    Consider:
1430
1431          (set (reg:DI 101) (reg:DI 100))
1432          (set (subreg:SI (reg:DI 101) 0) <foo>)
1433
1434    This is NOT equivalent to:
1435
1436          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1437                     (set (reg:DI 101) (reg:DI 100))])
1438
1439    Not only does this modify 100 (in which case it might still be valid
1440    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1441
1442    We can also run into a problem if I2 sets a register that I1
1443    uses and I1 gets directly substituted into I3 (not via I2).  In that
1444    case, we would be getting the wrong value of I2DEST into I3, so we
1445    must reject the combination.  This case occurs when I2 and I1 both
1446    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1447    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1448    of a SET must prevent combination from occurring.
1449
1450    Before doing the above check, we first try to expand a field assignment
1451    into a set of logical operations.
1452
1453    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1454    we place a register that is both set and used within I3.  If more than one
1455    such register is detected, we fail.
1456
1457    Return 1 if the combination is valid, zero otherwise.  */
1458
1459 static int
1460 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1461                   int i1_not_in_src, rtx *pi3dest_killed)
1462 {
1463   rtx x = *loc;
1464
1465   if (GET_CODE (x) == SET)
1466     {
1467       rtx set = x ;
1468       rtx dest = SET_DEST (set);
1469       rtx src = SET_SRC (set);
1470       rtx inner_dest = dest;
1471       rtx subdest;
1472
1473       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1474              || GET_CODE (inner_dest) == SUBREG
1475              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1476         inner_dest = XEXP (inner_dest, 0);
1477
1478       /* Check for the case where I3 modifies its output, as discussed
1479          above.  We don't want to prevent pseudos from being combined
1480          into the address of a MEM, so only prevent the combination if
1481          i1 or i2 set the same MEM.  */
1482       if ((inner_dest != dest &&
1483            (!MEM_P (inner_dest)
1484             || rtx_equal_p (i2dest, inner_dest)
1485             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1486            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1487                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1488
1489           /* This is the same test done in can_combine_p except we can't test
1490              all_adjacent; we don't have to, since this instruction will stay
1491              in place, thus we are not considering increasing the lifetime of
1492              INNER_DEST.
1493
1494              Also, if this insn sets a function argument, combining it with
1495              something that might need a spill could clobber a previous
1496              function argument; the all_adjacent test in can_combine_p also
1497              checks this; here, we do a more specific test for this case.  */
1498
1499           || (REG_P (inner_dest)
1500               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1501               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1502                                         GET_MODE (inner_dest))))
1503           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1504         return 0;
1505
1506       /* If DEST is used in I3, it is being killed in this insn, so
1507          record that for later.  We have to consider paradoxical
1508          subregs here, since they kill the whole register, but we
1509          ignore partial subregs, STRICT_LOW_PART, etc.
1510          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1511          STACK_POINTER_REGNUM, since these are always considered to be
1512          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1513       subdest = dest;
1514       if (GET_CODE (subdest) == SUBREG
1515           && (GET_MODE_SIZE (GET_MODE (subdest))
1516               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1517         subdest = SUBREG_REG (subdest);
1518       if (pi3dest_killed
1519           && REG_P (subdest)
1520           && reg_referenced_p (subdest, PATTERN (i3))
1521           && REGNO (subdest) != FRAME_POINTER_REGNUM
1522 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1523           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1524 #endif
1525 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526           && (REGNO (subdest) != ARG_POINTER_REGNUM
1527               || ! fixed_regs [REGNO (subdest)])
1528 #endif
1529           && REGNO (subdest) != STACK_POINTER_REGNUM)
1530         {
1531           if (*pi3dest_killed)
1532             return 0;
1533
1534           *pi3dest_killed = subdest;
1535         }
1536     }
1537
1538   else if (GET_CODE (x) == PARALLEL)
1539     {
1540       int i;
1541
1542       for (i = 0; i < XVECLEN (x, 0); i++)
1543         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1544                                 i1_not_in_src, pi3dest_killed))
1545           return 0;
1546     }
1547
1548   return 1;
1549 }
1550 \f
1551 /* Return 1 if X is an arithmetic expression that contains a multiplication
1552    and division.  We don't count multiplications by powers of two here.  */
1553
1554 static int
1555 contains_muldiv (rtx x)
1556 {
1557   switch (GET_CODE (x))
1558     {
1559     case MOD:  case DIV:  case UMOD:  case UDIV:
1560       return 1;
1561
1562     case MULT:
1563       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1564                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1565     default:
1566       if (BINARY_P (x))
1567         return contains_muldiv (XEXP (x, 0))
1568             || contains_muldiv (XEXP (x, 1));
1569
1570       if (UNARY_P (x))
1571         return contains_muldiv (XEXP (x, 0));
1572
1573       return 0;
1574     }
1575 }
1576 \f
1577 /* Determine whether INSN can be used in a combination.  Return nonzero if
1578    not.  This is used in try_combine to detect early some cases where we
1579    can't perform combinations.  */
1580
1581 static int
1582 cant_combine_insn_p (rtx insn)
1583 {
1584   rtx set;
1585   rtx src, dest;
1586
1587   /* If this isn't really an insn, we can't do anything.
1588      This can occur when flow deletes an insn that it has merged into an
1589      auto-increment address.  */
1590   if (! INSN_P (insn))
1591     return 1;
1592
1593   /* Never combine loads and stores involving hard regs that are likely
1594      to be spilled.  The register allocator can usually handle such
1595      reg-reg moves by tying.  If we allow the combiner to make
1596      substitutions of likely-spilled regs, reload might die.
1597      As an exception, we allow combinations involving fixed regs; these are
1598      not available to the register allocator so there's no risk involved.  */
1599
1600   set = single_set (insn);
1601   if (! set)
1602     return 0;
1603   src = SET_SRC (set);
1604   dest = SET_DEST (set);
1605   if (GET_CODE (src) == SUBREG)
1606     src = SUBREG_REG (src);
1607   if (GET_CODE (dest) == SUBREG)
1608     dest = SUBREG_REG (dest);
1609   if (REG_P (src) && REG_P (dest)
1610       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1611            && ! fixed_regs[REGNO (src)]
1612            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1613           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1614               && ! fixed_regs[REGNO (dest)]
1615               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1616     return 1;
1617
1618   return 0;
1619 }
1620
1621 struct likely_spilled_retval_info
1622 {
1623   unsigned regno, nregs;
1624   unsigned mask;
1625 };
1626
1627 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1628    hard registers that are known to be written to / clobbered in full.  */
1629 static void
1630 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1631 {
1632   struct likely_spilled_retval_info *info = data;
1633   unsigned regno, nregs;
1634   unsigned new_mask;
1635
1636   if (!REG_P (XEXP (set, 0)))
1637     return;
1638   regno = REGNO (x);
1639   if (regno >= info->regno + info->nregs)
1640     return;
1641   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1642   if (regno + nregs <= info->regno)
1643     return;
1644   new_mask = (2U << (nregs - 1)) - 1;
1645   if (regno < info->regno)
1646     new_mask >>= info->regno - regno;
1647   else
1648     new_mask <<= regno - info->regno;
1649   info->mask &= new_mask;
1650 }
1651
1652 /* Return nonzero iff part of the return value is live during INSN, and
1653    it is likely spilled.  This can happen when more than one insn is needed
1654    to copy the return value, e.g. when we consider to combine into the
1655    second copy insn for a complex value.  */
1656
1657 static int
1658 likely_spilled_retval_p (rtx insn)
1659 {
1660   rtx use = BB_END (this_basic_block);
1661   rtx reg, p;
1662   unsigned regno, nregs;
1663   /* We assume here that no machine mode needs more than
1664      32 hard registers when the value overlaps with a register
1665      for which FUNCTION_VALUE_REGNO_P is true.  */
1666   unsigned mask;
1667   struct likely_spilled_retval_info info;
1668
1669   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1670     return 0;
1671   reg = XEXP (PATTERN (use), 0);
1672   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1673     return 0;
1674   regno = REGNO (reg);
1675   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1676   if (nregs == 1)
1677     return 0;
1678   mask = (2U << (nregs - 1)) - 1;
1679
1680   /* Disregard parts of the return value that are set later.  */
1681   info.regno = regno;
1682   info.nregs = nregs;
1683   info.mask = mask;
1684   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1685     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1686   mask = info.mask;
1687
1688   /* Check if any of the (probably) live return value registers is
1689      likely spilled.  */
1690   nregs --;
1691   do
1692     {
1693       if ((mask & 1 << nregs)
1694           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1695         return 1;
1696     } while (nregs--);
1697   return 0;
1698 }
1699
1700 /* Adjust INSN after we made a change to its destination.
1701
1702    Changing the destination can invalidate notes that say something about
1703    the results of the insn and a LOG_LINK pointing to the insn.  */
1704
1705 static void
1706 adjust_for_new_dest (rtx insn)
1707 {
1708   rtx *loc;
1709
1710   /* For notes, be conservative and simply remove them.  */
1711   loc = &REG_NOTES (insn);
1712   while (*loc)
1713     {
1714       enum reg_note kind = REG_NOTE_KIND (*loc);
1715       if (kind == REG_EQUAL || kind == REG_EQUIV)
1716         *loc = XEXP (*loc, 1);
1717       else
1718         loc = &XEXP (*loc, 1);
1719     }
1720
1721   /* The new insn will have a destination that was previously the destination
1722      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1723      the next use of that destination.  */
1724   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1725 }
1726
1727 /* Return TRUE if combine can reuse reg X in mode MODE.
1728    ADDED_SETS is nonzero if the original set is still required.  */
1729 static bool
1730 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1731 {
1732   unsigned int regno;
1733
1734   if (!REG_P(x))
1735     return false;
1736
1737   regno = REGNO (x);
1738   /* Allow hard registers if the new mode is legal, and occupies no more
1739      registers than the old mode.  */
1740   if (regno < FIRST_PSEUDO_REGISTER)
1741     return (HARD_REGNO_MODE_OK (regno, mode)
1742             && (hard_regno_nregs[regno][GET_MODE (x)]
1743                 >= hard_regno_nregs[regno][mode]));
1744
1745   /* Or a pseudo that is only used once.  */
1746   return (REG_N_SETS (regno) == 1 && !added_sets
1747           && !REG_USERVAR_P (x));
1748 }
1749
1750
1751 /* Check whether X, the destination of a set, refers to part of
1752    the register specified by REG.  */
1753
1754 static bool
1755 reg_subword_p (rtx x, rtx reg)
1756 {
1757   /* Check that reg is an integer mode register.  */
1758   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1759     return false;
1760
1761   if (GET_CODE (x) == STRICT_LOW_PART
1762       || GET_CODE (x) == ZERO_EXTRACT)
1763     x = XEXP (x, 0);
1764
1765   return GET_CODE (x) == SUBREG
1766          && SUBREG_REG (x) == reg
1767          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1768 }
1769
1770
1771 /* Try to combine the insns I1 and I2 into I3.
1772    Here I1 and I2 appear earlier than I3.
1773    I1 can be zero; then we combine just I2 into I3.
1774
1775    If we are combining three insns and the resulting insn is not recognized,
1776    try splitting it into two insns.  If that happens, I2 and I3 are retained
1777    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1778    are pseudo-deleted.
1779
1780    Return 0 if the combination does not work.  Then nothing is changed.
1781    If we did the combination, return the insn at which combine should
1782    resume scanning.
1783
1784    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1785    new direct jump instruction.  */
1786
1787 static rtx
1788 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1789 {
1790   /* New patterns for I3 and I2, respectively.  */
1791   rtx newpat, newi2pat = 0;
1792   rtvec newpat_vec_with_clobbers = 0;
1793   int substed_i2 = 0, substed_i1 = 0;
1794   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1795   int added_sets_1, added_sets_2;
1796   /* Total number of SETs to put into I3.  */
1797   int total_sets;
1798   /* Nonzero if I2's body now appears in I3.  */
1799   int i2_is_used;
1800   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1801   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1802   /* Contains I3 if the destination of I3 is used in its source, which means
1803      that the old life of I3 is being killed.  If that usage is placed into
1804      I2 and not in I3, a REG_DEAD note must be made.  */
1805   rtx i3dest_killed = 0;
1806   /* SET_DEST and SET_SRC of I2 and I1.  */
1807   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1808   /* PATTERN (I2), or a copy of it in certain cases.  */
1809   rtx i2pat;
1810   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1811   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1812   int i2dest_killed = 0, i1dest_killed = 0;
1813   int i1_feeds_i3 = 0;
1814   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1815   rtx new_i3_notes, new_i2_notes;
1816   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1817   int i3_subst_into_i2 = 0;
1818   /* Notes that I1, I2 or I3 is a MULT operation.  */
1819   int have_mult = 0;
1820   int swap_i2i3 = 0;
1821
1822   int maxreg;
1823   rtx temp;
1824   rtx link;
1825   int i;
1826
1827   /* Exit early if one of the insns involved can't be used for
1828      combinations.  */
1829   if (cant_combine_insn_p (i3)
1830       || cant_combine_insn_p (i2)
1831       || (i1 && cant_combine_insn_p (i1))
1832       || likely_spilled_retval_p (i3)
1833       /* We also can't do anything if I3 has a
1834          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1835          libcall.  */
1836 #if 0
1837       /* ??? This gives worse code, and appears to be unnecessary, since no
1838          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1839       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1840 #endif
1841       )
1842     return 0;
1843
1844   combine_attempts++;
1845   undobuf.other_insn = 0;
1846
1847   /* Reset the hard register usage information.  */
1848   CLEAR_HARD_REG_SET (newpat_used_regs);
1849
1850   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1851      code below, set I1 to be the earlier of the two insns.  */
1852   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1853     temp = i1, i1 = i2, i2 = temp;
1854
1855   added_links_insn = 0;
1856
1857   /* First check for one important special-case that the code below will
1858      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1859      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1860      we may be able to replace that destination with the destination of I3.
1861      This occurs in the common code where we compute both a quotient and
1862      remainder into a structure, in which case we want to do the computation
1863      directly into the structure to avoid register-register copies.
1864
1865      Note that this case handles both multiple sets in I2 and also
1866      cases where I2 has a number of CLOBBER or PARALLELs.
1867
1868      We make very conservative checks below and only try to handle the
1869      most common cases of this.  For example, we only handle the case
1870      where I2 and I3 are adjacent to avoid making difficult register
1871      usage tests.  */
1872
1873   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1874       && REG_P (SET_SRC (PATTERN (i3)))
1875       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1876       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1877       && GET_CODE (PATTERN (i2)) == PARALLEL
1878       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1879       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1880          below would need to check what is inside (and reg_overlap_mentioned_p
1881          doesn't support those codes anyway).  Don't allow those destinations;
1882          the resulting insn isn't likely to be recognized anyway.  */
1883       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1884       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1885       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1886                                     SET_DEST (PATTERN (i3)))
1887       && next_real_insn (i2) == i3)
1888     {
1889       rtx p2 = PATTERN (i2);
1890
1891       /* Make sure that the destination of I3,
1892          which we are going to substitute into one output of I2,
1893          is not used within another output of I2.  We must avoid making this:
1894          (parallel [(set (mem (reg 69)) ...)
1895                     (set (reg 69) ...)])
1896          which is not well-defined as to order of actions.
1897          (Besides, reload can't handle output reloads for this.)
1898
1899          The problem can also happen if the dest of I3 is a memory ref,
1900          if another dest in I2 is an indirect memory ref.  */
1901       for (i = 0; i < XVECLEN (p2, 0); i++)
1902         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1903              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1904             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1905                                         SET_DEST (XVECEXP (p2, 0, i))))
1906           break;
1907
1908       if (i == XVECLEN (p2, 0))
1909         for (i = 0; i < XVECLEN (p2, 0); i++)
1910           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1911                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1912               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1913             {
1914               combine_merges++;
1915
1916               subst_insn = i3;
1917               subst_low_cuid = INSN_CUID (i2);
1918
1919               added_sets_2 = added_sets_1 = 0;
1920               i2dest = SET_SRC (PATTERN (i3));
1921               i2dest_killed = dead_or_set_p (i2, i2dest);
1922
1923               /* Replace the dest in I2 with our dest and make the resulting
1924                  insn the new pattern for I3.  Then skip to where we
1925                  validate the pattern.  Everything was set up above.  */
1926               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1927                      SET_DEST (PATTERN (i3)));
1928
1929               newpat = p2;
1930               i3_subst_into_i2 = 1;
1931               goto validate_replacement;
1932             }
1933     }
1934
1935   /* If I2 is setting a pseudo to a constant and I3 is setting some
1936      sub-part of it to another constant, merge them by making a new
1937      constant.  */
1938   if (i1 == 0
1939       && (temp = single_set (i2)) != 0
1940       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1941           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1942       && GET_CODE (PATTERN (i3)) == SET
1943       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1944           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1945       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1946     {
1947       rtx dest = SET_DEST (PATTERN (i3));
1948       int offset = -1;
1949       int width = 0;
1950
1951       if (GET_CODE (dest) == ZERO_EXTRACT)
1952         {
1953           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1954               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1955             {
1956               width = INTVAL (XEXP (dest, 1));
1957               offset = INTVAL (XEXP (dest, 2));
1958               dest = XEXP (dest, 0);
1959               if (BITS_BIG_ENDIAN)
1960                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1961             }
1962         }
1963       else
1964         {
1965           if (GET_CODE (dest) == STRICT_LOW_PART)
1966             dest = XEXP (dest, 0);
1967           width = GET_MODE_BITSIZE (GET_MODE (dest));
1968           offset = 0;
1969         }
1970
1971       if (offset >= 0)
1972         {
1973           /* If this is the low part, we're done.  */
1974           if (subreg_lowpart_p (dest))
1975             ;
1976           /* Handle the case where inner is twice the size of outer.  */
1977           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1978                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1979             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1980           /* Otherwise give up for now.  */
1981           else
1982             offset = -1;
1983         }
1984
1985       if (offset >= 0)
1986         {
1987           HOST_WIDE_INT mhi, ohi, ihi;
1988           HOST_WIDE_INT mlo, olo, ilo;
1989           rtx inner = SET_SRC (PATTERN (i3));
1990           rtx outer = SET_SRC (temp);
1991
1992           if (GET_CODE (outer) == CONST_INT)
1993             {
1994               olo = INTVAL (outer);
1995               ohi = olo < 0 ? -1 : 0;
1996             }
1997           else
1998             {
1999               olo = CONST_DOUBLE_LOW (outer);
2000               ohi = CONST_DOUBLE_HIGH (outer);
2001             }
2002
2003           if (GET_CODE (inner) == CONST_INT)
2004             {
2005               ilo = INTVAL (inner);
2006               ihi = ilo < 0 ? -1 : 0;
2007             }
2008           else
2009             {
2010               ilo = CONST_DOUBLE_LOW (inner);
2011               ihi = CONST_DOUBLE_HIGH (inner);
2012             }
2013
2014           if (width < HOST_BITS_PER_WIDE_INT)
2015             {
2016               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2017               mhi = 0;
2018             }
2019           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2020             {
2021               mhi = ((unsigned HOST_WIDE_INT) 1
2022                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2023               mlo = -1;
2024             }
2025           else
2026             {
2027               mlo = -1;
2028               mhi = -1;
2029             }
2030
2031           ilo &= mlo;
2032           ihi &= mhi;
2033
2034           if (offset >= HOST_BITS_PER_WIDE_INT)
2035             {
2036               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2037               mlo = 0;
2038               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2039               ilo = 0;
2040             }
2041           else if (offset > 0)
2042             {
2043               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2044                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2045               mlo = mlo << offset;
2046               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2047                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2048               ilo = ilo << offset;
2049             }
2050
2051           olo = (olo & ~mlo) | ilo;
2052           ohi = (ohi & ~mhi) | ihi;
2053
2054           combine_merges++;
2055           subst_insn = i3;
2056           subst_low_cuid = INSN_CUID (i2);
2057           added_sets_2 = added_sets_1 = 0;
2058           i2dest = SET_DEST (temp);
2059           i2dest_killed = dead_or_set_p (i2, i2dest);
2060
2061           SUBST (SET_SRC (temp),
2062                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2063
2064           newpat = PATTERN (i2);
2065           goto validate_replacement;
2066         }
2067     }
2068
2069 #ifndef HAVE_cc0
2070   /* If we have no I1 and I2 looks like:
2071         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2072                    (set Y OP)])
2073      make up a dummy I1 that is
2074         (set Y OP)
2075      and change I2 to be
2076         (set (reg:CC X) (compare:CC Y (const_int 0)))
2077
2078      (We can ignore any trailing CLOBBERs.)
2079
2080      This undoes a previous combination and allows us to match a branch-and-
2081      decrement insn.  */
2082
2083   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2084       && XVECLEN (PATTERN (i2), 0) >= 2
2085       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2086       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2087           == MODE_CC)
2088       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2089       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2090       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2091       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2092       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2093                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2094     {
2095       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2096         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2097           break;
2098
2099       if (i == 1)
2100         {
2101           /* We make I1 with the same INSN_UID as I2.  This gives it
2102              the same INSN_CUID for value tracking.  Our fake I1 will
2103              never appear in the insn stream so giving it the same INSN_UID
2104              as I2 will not cause a problem.  */
2105
2106           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2107                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2108                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2109                              NULL_RTX);
2110
2111           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2112           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2113                  SET_DEST (PATTERN (i1)));
2114         }
2115     }
2116 #endif
2117
2118   /* Verify that I2 and I1 are valid for combining.  */
2119   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2120       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2121     {
2122       undo_all ();
2123       return 0;
2124     }
2125
2126   /* Record whether I2DEST is used in I2SRC and similarly for the other
2127      cases.  Knowing this will help in register status updating below.  */
2128   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2129   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2130   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2131   i2dest_killed = dead_or_set_p (i2, i2dest);
2132   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2133
2134   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2135      in I2SRC.  */
2136   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2137
2138   /* Ensure that I3's pattern can be the destination of combines.  */
2139   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2140                           i1 && i2dest_in_i1src && i1_feeds_i3,
2141                           &i3dest_killed))
2142     {
2143       undo_all ();
2144       return 0;
2145     }
2146
2147   /* See if any of the insns is a MULT operation.  Unless one is, we will
2148      reject a combination that is, since it must be slower.  Be conservative
2149      here.  */
2150   if (GET_CODE (i2src) == MULT
2151       || (i1 != 0 && GET_CODE (i1src) == MULT)
2152       || (GET_CODE (PATTERN (i3)) == SET
2153           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2154     have_mult = 1;
2155
2156   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2157      We used to do this EXCEPT in one case: I3 has a post-inc in an
2158      output operand.  However, that exception can give rise to insns like
2159         mov r3,(r3)+
2160      which is a famous insn on the PDP-11 where the value of r3 used as the
2161      source was model-dependent.  Avoid this sort of thing.  */
2162
2163 #if 0
2164   if (!(GET_CODE (PATTERN (i3)) == SET
2165         && REG_P (SET_SRC (PATTERN (i3)))
2166         && MEM_P (SET_DEST (PATTERN (i3)))
2167         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2168             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2169     /* It's not the exception.  */
2170 #endif
2171 #ifdef AUTO_INC_DEC
2172     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2173       if (REG_NOTE_KIND (link) == REG_INC
2174           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2175               || (i1 != 0
2176                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2177         {
2178           undo_all ();
2179           return 0;
2180         }
2181 #endif
2182
2183   /* See if the SETs in I1 or I2 need to be kept around in the merged
2184      instruction: whenever the value set there is still needed past I3.
2185      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2186
2187      For the SET in I1, we have two cases:  If I1 and I2 independently
2188      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2189      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2190      in I1 needs to be kept around unless I1DEST dies or is set in either
2191      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2192      I1DEST.  If so, we know I1 feeds into I2.  */
2193
2194   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2195
2196   added_sets_1
2197     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2198                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2199
2200   /* If the set in I2 needs to be kept around, we must make a copy of
2201      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2202      PATTERN (I2), we are only substituting for the original I1DEST, not into
2203      an already-substituted copy.  This also prevents making self-referential
2204      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2205      I2DEST.  */
2206
2207   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2208            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2209            : PATTERN (i2));
2210
2211   if (added_sets_2)
2212     i2pat = copy_rtx (i2pat);
2213
2214   combine_merges++;
2215
2216   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2217
2218   maxreg = max_reg_num ();
2219
2220   subst_insn = i3;
2221
2222 #ifndef HAVE_cc0
2223   /* Many machines that don't use CC0 have insns that can both perform an
2224      arithmetic operation and set the condition code.  These operations will
2225      be represented as a PARALLEL with the first element of the vector
2226      being a COMPARE of an arithmetic operation with the constant zero.
2227      The second element of the vector will set some pseudo to the result
2228      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2229      match such a pattern and so will generate an extra insn.   Here we test
2230      for this case, where both the comparison and the operation result are
2231      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2232      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2233
2234   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2235       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2236       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2237       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2238     {
2239 #ifdef SELECT_CC_MODE
2240       rtx *cc_use;
2241       enum machine_mode compare_mode;
2242 #endif
2243
2244       newpat = PATTERN (i3);
2245       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2246
2247       i2_is_used = 1;
2248
2249 #ifdef SELECT_CC_MODE
2250       /* See if a COMPARE with the operand we substituted in should be done
2251          with the mode that is currently being used.  If not, do the same
2252          processing we do in `subst' for a SET; namely, if the destination
2253          is used only once, try to replace it with a register of the proper
2254          mode and also replace the COMPARE.  */
2255       if (undobuf.other_insn == 0
2256           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2257                                         &undobuf.other_insn))
2258           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2259                                               i2src, const0_rtx))
2260               != GET_MODE (SET_DEST (newpat))))
2261         {
2262           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2263                                    compare_mode))
2264             {
2265               unsigned int regno = REGNO (SET_DEST (newpat));
2266               rtx new_dest;
2267
2268               if (regno < FIRST_PSEUDO_REGISTER)
2269                 new_dest = gen_rtx_REG (compare_mode, regno);
2270               else
2271                 {
2272                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2273                   new_dest = regno_reg_rtx[regno];
2274                 }
2275
2276               SUBST (SET_DEST (newpat), new_dest);
2277               SUBST (XEXP (*cc_use, 0), new_dest);
2278               SUBST (SET_SRC (newpat),
2279                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2280             }
2281           else
2282             undobuf.other_insn = 0;
2283         }
2284 #endif
2285     }
2286   else
2287 #endif
2288     {
2289       /* It is possible that the source of I2 or I1 may be performing
2290          an unneeded operation, such as a ZERO_EXTEND of something
2291          that is known to have the high part zero.  Handle that case
2292          by letting subst look at the innermost one of them.
2293
2294          Another way to do this would be to have a function that tries
2295          to simplify a single insn instead of merging two or more
2296          insns.  We don't do this because of the potential of infinite
2297          loops and because of the potential extra memory required.
2298          However, doing it the way we are is a bit of a kludge and
2299          doesn't catch all cases.
2300
2301          But only do this if -fexpensive-optimizations since it slows
2302          things down and doesn't usually win.
2303
2304          This is not done in the COMPARE case above because the
2305          unmodified I2PAT is used in the PARALLEL and so a pattern
2306          with a modified I2SRC would not match.  */
2307
2308       if (flag_expensive_optimizations)
2309         {
2310           /* Pass pc_rtx so no substitutions are done, just
2311              simplifications.  */
2312           if (i1)
2313             {
2314               subst_low_cuid = INSN_CUID (i1);
2315               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2316             }
2317           else
2318             {
2319               subst_low_cuid = INSN_CUID (i2);
2320               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2321             }
2322         }
2323
2324       n_occurrences = 0;                /* `subst' counts here */
2325
2326       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2327          need to make a unique copy of I2SRC each time we substitute it
2328          to avoid self-referential rtl.  */
2329
2330       subst_low_cuid = INSN_CUID (i2);
2331       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2332                       ! i1_feeds_i3 && i1dest_in_i1src);
2333       substed_i2 = 1;
2334
2335       /* Record whether i2's body now appears within i3's body.  */
2336       i2_is_used = n_occurrences;
2337     }
2338
2339   /* If we already got a failure, don't try to do more.  Otherwise,
2340      try to substitute in I1 if we have it.  */
2341
2342   if (i1 && GET_CODE (newpat) != CLOBBER)
2343     {
2344       /* Before we can do this substitution, we must redo the test done
2345          above (see detailed comments there) that ensures  that I1DEST
2346          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2347
2348       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2349                               0, (rtx*) 0))
2350         {
2351           undo_all ();
2352           return 0;
2353         }
2354
2355       n_occurrences = 0;
2356       subst_low_cuid = INSN_CUID (i1);
2357       newpat = subst (newpat, i1dest, i1src, 0, 0);
2358       substed_i1 = 1;
2359     }
2360
2361   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2362      to count all the ways that I2SRC and I1SRC can be used.  */
2363   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2364        && i2_is_used + added_sets_2 > 1)
2365       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2366           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2367               > 1))
2368       /* Fail if we tried to make a new register.  */
2369       || max_reg_num () != maxreg
2370       /* Fail if we couldn't do something and have a CLOBBER.  */
2371       || GET_CODE (newpat) == CLOBBER
2372       /* Fail if this new pattern is a MULT and we didn't have one before
2373          at the outer level.  */
2374       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2375           && ! have_mult))
2376     {
2377       undo_all ();
2378       return 0;
2379     }
2380
2381   /* If the actions of the earlier insns must be kept
2382      in addition to substituting them into the latest one,
2383      we must make a new PARALLEL for the latest insn
2384      to hold additional the SETs.  */
2385
2386   if (added_sets_1 || added_sets_2)
2387     {
2388       combine_extras++;
2389
2390       if (GET_CODE (newpat) == PARALLEL)
2391         {
2392           rtvec old = XVEC (newpat, 0);
2393           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2394           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2395           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2396                   sizeof (old->elem[0]) * old->num_elem);
2397         }
2398       else
2399         {
2400           rtx old = newpat;
2401           total_sets = 1 + added_sets_1 + added_sets_2;
2402           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2403           XVECEXP (newpat, 0, 0) = old;
2404         }
2405
2406       if (added_sets_1)
2407         XVECEXP (newpat, 0, --total_sets)
2408           = (GET_CODE (PATTERN (i1)) == PARALLEL
2409              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2410
2411       if (added_sets_2)
2412         {
2413           /* If there is no I1, use I2's body as is.  We used to also not do
2414              the subst call below if I2 was substituted into I3,
2415              but that could lose a simplification.  */
2416           if (i1 == 0)
2417             XVECEXP (newpat, 0, --total_sets) = i2pat;
2418           else
2419             /* See comment where i2pat is assigned.  */
2420             XVECEXP (newpat, 0, --total_sets)
2421               = subst (i2pat, i1dest, i1src, 0, 0);
2422         }
2423     }
2424
2425   /* We come here when we are replacing a destination in I2 with the
2426      destination of I3.  */
2427  validate_replacement:
2428
2429   /* Note which hard regs this insn has as inputs.  */
2430   mark_used_regs_combine (newpat);
2431
2432   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2433      consider splitting this pattern, we might need these clobbers.  */
2434   if (i1 && GET_CODE (newpat) == PARALLEL
2435       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2436     {
2437       int len = XVECLEN (newpat, 0);
2438
2439       newpat_vec_with_clobbers = rtvec_alloc (len);
2440       for (i = 0; i < len; i++)
2441         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2442     }
2443
2444   /* Is the result of combination a valid instruction?  */
2445   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2446
2447   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2448      the second SET's destination is a register that is unused and isn't
2449      marked as an instruction that might trap in an EH region.  In that case,
2450      we just need the first SET.   This can occur when simplifying a divmod
2451      insn.  We *must* test for this case here because the code below that
2452      splits two independent SETs doesn't handle this case correctly when it
2453      updates the register status.
2454
2455      It's pointless doing this if we originally had two sets, one from
2456      i3, and one from i2.  Combining then splitting the parallel results
2457      in the original i2 again plus an invalid insn (which we delete).
2458      The net effect is only to move instructions around, which makes
2459      debug info less accurate.
2460
2461      Also check the case where the first SET's destination is unused.
2462      That would not cause incorrect code, but does cause an unneeded
2463      insn to remain.  */
2464
2465   if (insn_code_number < 0
2466       && !(added_sets_2 && i1 == 0)
2467       && GET_CODE (newpat) == PARALLEL
2468       && XVECLEN (newpat, 0) == 2
2469       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2470       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2471       && asm_noperands (newpat) < 0)
2472     {
2473       rtx set0 = XVECEXP (newpat, 0, 0);
2474       rtx set1 = XVECEXP (newpat, 0, 1);
2475       rtx note;
2476
2477       if (((REG_P (SET_DEST (set1))
2478             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2479            || (GET_CODE (SET_DEST (set1)) == SUBREG
2480                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2481           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2482               || INTVAL (XEXP (note, 0)) <= 0)
2483           && ! side_effects_p (SET_SRC (set1)))
2484         {
2485           newpat = set0;
2486           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2487         }
2488
2489       else if (((REG_P (SET_DEST (set0))
2490                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2491                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2492                     && find_reg_note (i3, REG_UNUSED,
2493                                       SUBREG_REG (SET_DEST (set0)))))
2494                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2495                    || INTVAL (XEXP (note, 0)) <= 0)
2496                && ! side_effects_p (SET_SRC (set0)))
2497         {
2498           newpat = set1;
2499           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2500
2501           if (insn_code_number >= 0)
2502             {
2503               /* If we will be able to accept this, we have made a
2504                  change to the destination of I3.  This requires us to
2505                  do a few adjustments.  */
2506
2507               PATTERN (i3) = newpat;
2508               adjust_for_new_dest (i3);
2509             }
2510         }
2511     }
2512
2513   /* If we were combining three insns and the result is a simple SET
2514      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2515      insns.  There are two ways to do this.  It can be split using a
2516      machine-specific method (like when you have an addition of a large
2517      constant) or by combine in the function find_split_point.  */
2518
2519   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2520       && asm_noperands (newpat) < 0)
2521     {
2522       rtx m_split, *split;
2523
2524       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2525          use I2DEST as a scratch register will help.  In the latter case,
2526          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2527
2528       m_split = split_insns (newpat, i3);
2529
2530       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2531          inputs of NEWPAT.  */
2532
2533       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2534          possible to try that as a scratch reg.  This would require adding
2535          more code to make it work though.  */
2536
2537       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2538         {
2539           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2540
2541           /* First try to split using the original register as a
2542              scratch register.  */
2543           m_split = split_insns (gen_rtx_PARALLEL
2544                                  (VOIDmode,
2545                                   gen_rtvec (2, newpat,
2546                                              gen_rtx_CLOBBER (VOIDmode,
2547                                                               i2dest))),
2548                                  i3);
2549
2550           /* If that didn't work, try changing the mode of I2DEST if
2551              we can.  */
2552           if (m_split == 0
2553               && new_mode != GET_MODE (i2dest)
2554               && new_mode != VOIDmode
2555               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2556             {
2557               enum machine_mode old_mode = GET_MODE (i2dest);
2558               rtx ni2dest;
2559
2560               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2561                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2562               else
2563                 {
2564                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2565                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2566                 }
2567
2568               m_split = split_insns (gen_rtx_PARALLEL
2569                                      (VOIDmode,
2570                                       gen_rtvec (2, newpat,
2571                                                  gen_rtx_CLOBBER (VOIDmode,
2572                                                                   ni2dest))),
2573                                      i3);
2574
2575               if (m_split == 0
2576                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2577                 {
2578                   struct undo *buf;
2579
2580                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2581                   buf = undobuf.undos;
2582                   undobuf.undos = buf->next;
2583                   buf->next = undobuf.frees;
2584                   undobuf.frees = buf;
2585                 }
2586             }
2587         }
2588
2589       /* If recog_for_combine has discarded clobbers, try to use them
2590          again for the split.  */
2591       if (m_split == 0 && newpat_vec_with_clobbers)
2592         m_split
2593           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2594                                            newpat_vec_with_clobbers), i3);
2595
2596       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2597         {
2598           m_split = PATTERN (m_split);
2599           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2600           if (insn_code_number >= 0)
2601             newpat = m_split;
2602         }
2603       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2604                && (next_real_insn (i2) == i3
2605                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2606         {
2607           rtx i2set, i3set;
2608           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2609           newi2pat = PATTERN (m_split);
2610
2611           i3set = single_set (NEXT_INSN (m_split));
2612           i2set = single_set (m_split);
2613
2614           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2615
2616           /* If I2 or I3 has multiple SETs, we won't know how to track
2617              register status, so don't use these insns.  If I2's destination
2618              is used between I2 and I3, we also can't use these insns.  */
2619
2620           if (i2_code_number >= 0 && i2set && i3set
2621               && (next_real_insn (i2) == i3
2622                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2623             insn_code_number = recog_for_combine (&newi3pat, i3,
2624                                                   &new_i3_notes);
2625           if (insn_code_number >= 0)
2626             newpat = newi3pat;
2627
2628           /* It is possible that both insns now set the destination of I3.
2629              If so, we must show an extra use of it.  */
2630
2631           if (insn_code_number >= 0)
2632             {
2633               rtx new_i3_dest = SET_DEST (i3set);
2634               rtx new_i2_dest = SET_DEST (i2set);
2635
2636               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2637                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2638                      || GET_CODE (new_i3_dest) == SUBREG)
2639                 new_i3_dest = XEXP (new_i3_dest, 0);
2640
2641               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2642                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2643                      || GET_CODE (new_i2_dest) == SUBREG)
2644                 new_i2_dest = XEXP (new_i2_dest, 0);
2645
2646               if (REG_P (new_i3_dest)
2647                   && REG_P (new_i2_dest)
2648                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2649                 REG_N_SETS (REGNO (new_i2_dest))++;
2650             }
2651         }
2652
2653       /* If we can split it and use I2DEST, go ahead and see if that
2654          helps things be recognized.  Verify that none of the registers
2655          are set between I2 and I3.  */
2656       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2657 #ifdef HAVE_cc0
2658           && REG_P (i2dest)
2659 #endif
2660           /* We need I2DEST in the proper mode.  If it is a hard register
2661              or the only use of a pseudo, we can change its mode.
2662              Make sure we don't change a hard register to have a mode that
2663              isn't valid for it, or change the number of registers.  */
2664           && (GET_MODE (*split) == GET_MODE (i2dest)
2665               || GET_MODE (*split) == VOIDmode
2666               || can_change_dest_mode (i2dest, added_sets_2,
2667                                        GET_MODE (*split)))
2668           && (next_real_insn (i2) == i3
2669               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2670           /* We can't overwrite I2DEST if its value is still used by
2671              NEWPAT.  */
2672           && ! reg_referenced_p (i2dest, newpat))
2673         {
2674           rtx newdest = i2dest;
2675           enum rtx_code split_code = GET_CODE (*split);
2676           enum machine_mode split_mode = GET_MODE (*split);
2677           bool subst_done = false;
2678           newi2pat = NULL_RTX;
2679
2680           /* Get NEWDEST as a register in the proper mode.  We have already
2681              validated that we can do this.  */
2682           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2683             {
2684               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2685                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2686               else
2687                 {
2688                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2689                   newdest = regno_reg_rtx[REGNO (i2dest)];
2690                 }
2691             }
2692
2693           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2694              an ASHIFT.  This can occur if it was inside a PLUS and hence
2695              appeared to be a memory address.  This is a kludge.  */
2696           if (split_code == MULT
2697               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2698               && INTVAL (XEXP (*split, 1)) > 0
2699               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2700             {
2701               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2702                                              XEXP (*split, 0), GEN_INT (i)));
2703               /* Update split_code because we may not have a multiply
2704                  anymore.  */
2705               split_code = GET_CODE (*split);
2706             }
2707
2708 #ifdef INSN_SCHEDULING
2709           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2710              be written as a ZERO_EXTEND.  */
2711           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2712             {
2713 #ifdef LOAD_EXTEND_OP
2714               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2715                  what it really is.  */
2716               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2717                   == SIGN_EXTEND)
2718                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2719                                                     SUBREG_REG (*split)));
2720               else
2721 #endif
2722                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2723                                                     SUBREG_REG (*split)));
2724             }
2725 #endif
2726
2727           /* Attempt to split binary operators using arithmetic identities.  */
2728           if (BINARY_P (SET_SRC (newpat))
2729               && split_mode == GET_MODE (SET_SRC (newpat))
2730               && ! side_effects_p (SET_SRC (newpat)))
2731             {
2732               rtx setsrc = SET_SRC (newpat);
2733               enum machine_mode mode = GET_MODE (setsrc);
2734               enum rtx_code code = GET_CODE (setsrc);
2735               rtx src_op0 = XEXP (setsrc, 0);
2736               rtx src_op1 = XEXP (setsrc, 1);
2737
2738               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2739               if (rtx_equal_p (src_op0, src_op1))
2740                 {
2741                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2742                   SUBST (XEXP (setsrc, 0), newdest);
2743                   SUBST (XEXP (setsrc, 1), newdest);
2744                   subst_done = true;
2745                 }
2746               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2747               else if ((code == PLUS || code == MULT)
2748                        && GET_CODE (src_op0) == code
2749                        && GET_CODE (XEXP (src_op0, 0)) == code
2750                        && (INTEGRAL_MODE_P (mode)
2751                            || (FLOAT_MODE_P (mode)
2752                                && flag_unsafe_math_optimizations)))
2753                 {
2754                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2755                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2756                   rtx r = XEXP (src_op0, 1);
2757                   rtx s = src_op1;
2758
2759                   /* Split both "((X op Y) op X) op Y" and
2760                      "((X op Y) op Y) op X" as "T op T" where T is
2761                      "X op Y".  */
2762                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2763                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2764                     {
2765                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2766                                               XEXP (src_op0, 0));
2767                       SUBST (XEXP (setsrc, 0), newdest);
2768                       SUBST (XEXP (setsrc, 1), newdest);
2769                       subst_done = true;
2770                     }
2771                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2772                      T is "X op Y".  */
2773                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2774                     {
2775                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2776                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2777                       SUBST (XEXP (setsrc, 0), newdest);
2778                       SUBST (XEXP (setsrc, 1), newdest);
2779                       subst_done = true;
2780                     }
2781                 }
2782             }
2783
2784           if (!subst_done)
2785             {
2786               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2787               SUBST (*split, newdest);
2788             }
2789
2790           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2791
2792           /* recog_for_combine might have added CLOBBERs to newi2pat.
2793              Make sure NEWPAT does not depend on the clobbered regs.  */
2794           if (GET_CODE (newi2pat) == PARALLEL)
2795             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2796               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2797                 {
2798                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2799                   if (reg_overlap_mentioned_p (reg, newpat))
2800                     {
2801                       undo_all ();
2802                       return 0;
2803                     }
2804                 }
2805
2806           /* If the split point was a MULT and we didn't have one before,
2807              don't use one now.  */
2808           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2809             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2810         }
2811     }
2812
2813   /* Check for a case where we loaded from memory in a narrow mode and
2814      then sign extended it, but we need both registers.  In that case,
2815      we have a PARALLEL with both loads from the same memory location.
2816      We can split this into a load from memory followed by a register-register
2817      copy.  This saves at least one insn, more if register allocation can
2818      eliminate the copy.
2819
2820      We cannot do this if the destination of the first assignment is a
2821      condition code register or cc0.  We eliminate this case by making sure
2822      the SET_DEST and SET_SRC have the same mode.
2823
2824      We cannot do this if the destination of the second assignment is
2825      a register that we have already assumed is zero-extended.  Similarly
2826      for a SUBREG of such a register.  */
2827
2828   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2829            && GET_CODE (newpat) == PARALLEL
2830            && XVECLEN (newpat, 0) == 2
2831            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2832            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2833            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2834                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2835            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2836            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2837                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2838            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2839                                    INSN_CUID (i2))
2840            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2841            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2842            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2843                  (REG_P (temp)
2844                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2845                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2846                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2847                   && (reg_stat[REGNO (temp)].nonzero_bits
2848                       != GET_MODE_MASK (word_mode))))
2849            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2850                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2851                      (REG_P (temp)
2852                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2853                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2854                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2855                       && (reg_stat[REGNO (temp)].nonzero_bits
2856                           != GET_MODE_MASK (word_mode)))))
2857            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2858                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2859            && ! find_reg_note (i3, REG_UNUSED,
2860                                SET_DEST (XVECEXP (newpat, 0, 0))))
2861     {
2862       rtx ni2dest;
2863
2864       newi2pat = XVECEXP (newpat, 0, 0);
2865       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2866       newpat = XVECEXP (newpat, 0, 1);
2867       SUBST (SET_SRC (newpat),
2868              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2869       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2870
2871       if (i2_code_number >= 0)
2872         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2873
2874       if (insn_code_number >= 0)
2875         swap_i2i3 = 1;
2876     }
2877
2878   /* Similarly, check for a case where we have a PARALLEL of two independent
2879      SETs but we started with three insns.  In this case, we can do the sets
2880      as two separate insns.  This case occurs when some SET allows two
2881      other insns to combine, but the destination of that SET is still live.  */
2882
2883   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2884            && GET_CODE (newpat) == PARALLEL
2885            && XVECLEN (newpat, 0) == 2
2886            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2887            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2888            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2889            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2890            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2891            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2892            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2893                                    INSN_CUID (i2))
2894            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2895                                   XVECEXP (newpat, 0, 0))
2896            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2897                                   XVECEXP (newpat, 0, 1))
2898            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2899                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2900 #ifdef HAVE_cc0
2901            /* We cannot split the parallel into two sets if both sets
2902               reference cc0.  */
2903            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2904                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2905 #endif
2906            )
2907     {
2908       /* Normally, it doesn't matter which of the two is done first,
2909          but it does if one references cc0.  In that case, it has to
2910          be first.  */
2911 #ifdef HAVE_cc0
2912       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2913         {
2914           newi2pat = XVECEXP (newpat, 0, 0);
2915           newpat = XVECEXP (newpat, 0, 1);
2916         }
2917       else
2918 #endif
2919         {
2920           newi2pat = XVECEXP (newpat, 0, 1);
2921           newpat = XVECEXP (newpat, 0, 0);
2922         }
2923
2924       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2925
2926       if (i2_code_number >= 0)
2927         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2928     }
2929
2930   /* If it still isn't recognized, fail and change things back the way they
2931      were.  */
2932   if ((insn_code_number < 0
2933        /* Is the result a reasonable ASM_OPERANDS?  */
2934        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2935     {
2936       undo_all ();
2937       return 0;
2938     }
2939
2940   /* If we had to change another insn, make sure it is valid also.  */
2941   if (undobuf.other_insn)
2942     {
2943       rtx other_pat = PATTERN (undobuf.other_insn);
2944       rtx new_other_notes;
2945       rtx note, next;
2946
2947       CLEAR_HARD_REG_SET (newpat_used_regs);
2948
2949       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2950                                              &new_other_notes);
2951
2952       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2953         {
2954           undo_all ();
2955           return 0;
2956         }
2957
2958       PATTERN (undobuf.other_insn) = other_pat;
2959
2960       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2961          are still valid.  Then add any non-duplicate notes added by
2962          recog_for_combine.  */
2963       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2964         {
2965           next = XEXP (note, 1);
2966
2967           if (REG_NOTE_KIND (note) == REG_UNUSED
2968               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2969             {
2970               if (REG_P (XEXP (note, 0)))
2971                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2972
2973               remove_note (undobuf.other_insn, note);
2974             }
2975         }
2976
2977       for (note = new_other_notes; note; note = XEXP (note, 1))
2978         if (REG_P (XEXP (note, 0)))
2979           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2980
2981       distribute_notes (new_other_notes, undobuf.other_insn,
2982                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2983     }
2984 #ifdef HAVE_cc0
2985   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2986      they are adjacent to each other or not.  */
2987   {
2988     rtx p = prev_nonnote_insn (i3);
2989     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2990         && sets_cc0_p (newi2pat))
2991       {
2992         undo_all ();
2993         return 0;
2994       }
2995   }
2996 #endif
2997
2998   /* Only allow this combination if insn_rtx_costs reports that the
2999      replacement instructions are cheaper than the originals.  */
3000   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3001     {
3002       undo_all ();
3003       return 0;
3004     }
3005
3006   /* We now know that we can do this combination.  Merge the insns and
3007      update the status of registers and LOG_LINKS.  */
3008
3009   if (swap_i2i3)
3010     {
3011       rtx insn;
3012       rtx link;
3013       rtx ni2dest;
3014
3015       /* I3 now uses what used to be its destination and which is now
3016          I2's destination.  This requires us to do a few adjustments.  */
3017       PATTERN (i3) = newpat;
3018       adjust_for_new_dest (i3);
3019
3020       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3021          so we still will.
3022
3023          However, some later insn might be using I2's dest and have
3024          a LOG_LINK pointing at I3.  We must remove this link.
3025          The simplest way to remove the link is to point it at I1,
3026          which we know will be a NOTE.  */
3027
3028       /* newi2pat is usually a SET here; however, recog_for_combine might
3029          have added some clobbers.  */
3030       if (GET_CODE (newi2pat) == PARALLEL)
3031         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3032       else
3033         ni2dest = SET_DEST (newi2pat);
3034
3035       for (insn = NEXT_INSN (i3);
3036            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3037                     || insn != BB_HEAD (this_basic_block->next_bb));
3038            insn = NEXT_INSN (insn))
3039         {
3040           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3041             {
3042               for (link = LOG_LINKS (insn); link;
3043                    link = XEXP (link, 1))
3044                 if (XEXP (link, 0) == i3)
3045                   XEXP (link, 0) = i1;
3046
3047               break;
3048             }
3049         }
3050     }
3051
3052   {
3053     rtx i3notes, i2notes, i1notes = 0;
3054     rtx i3links, i2links, i1links = 0;
3055     rtx midnotes = 0;
3056     unsigned int regno;
3057     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3058        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3059        same as i3dest, in which case newi2pat may be setting i1dest.  */
3060     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3061                    || i2dest_in_i2src || i2dest_in_i1src
3062                    || !i2dest_killed
3063                    ? 0 : i2dest);
3064     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3065                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3066                    || !i1dest_killed
3067                    ? 0 : i1dest);
3068
3069     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3070        clear them.  */
3071     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3072     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3073     if (i1)
3074       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3075
3076     /* Ensure that we do not have something that should not be shared but
3077        occurs multiple times in the new insns.  Check this by first
3078        resetting all the `used' flags and then copying anything is shared.  */
3079
3080     reset_used_flags (i3notes);
3081     reset_used_flags (i2notes);
3082     reset_used_flags (i1notes);
3083     reset_used_flags (newpat);
3084     reset_used_flags (newi2pat);
3085     if (undobuf.other_insn)
3086       reset_used_flags (PATTERN (undobuf.other_insn));
3087
3088     i3notes = copy_rtx_if_shared (i3notes);
3089     i2notes = copy_rtx_if_shared (i2notes);
3090     i1notes = copy_rtx_if_shared (i1notes);
3091     newpat = copy_rtx_if_shared (newpat);
3092     newi2pat = copy_rtx_if_shared (newi2pat);
3093     if (undobuf.other_insn)
3094       reset_used_flags (PATTERN (undobuf.other_insn));
3095
3096     INSN_CODE (i3) = insn_code_number;
3097     PATTERN (i3) = newpat;
3098
3099     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3100       {
3101         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3102
3103         reset_used_flags (call_usage);
3104         call_usage = copy_rtx (call_usage);
3105
3106         if (substed_i2)
3107           replace_rtx (call_usage, i2dest, i2src);
3108
3109         if (substed_i1)
3110           replace_rtx (call_usage, i1dest, i1src);
3111
3112         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3113       }
3114
3115     if (undobuf.other_insn)
3116       INSN_CODE (undobuf.other_insn) = other_code_number;
3117
3118     /* We had one special case above where I2 had more than one set and
3119        we replaced a destination of one of those sets with the destination
3120        of I3.  In that case, we have to update LOG_LINKS of insns later
3121        in this basic block.  Note that this (expensive) case is rare.
3122
3123        Also, in this case, we must pretend that all REG_NOTEs for I2
3124        actually came from I3, so that REG_UNUSED notes from I2 will be
3125        properly handled.  */
3126
3127     if (i3_subst_into_i2)
3128       {
3129         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3130           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3131                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3132               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3133               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3134               && ! find_reg_note (i2, REG_UNUSED,
3135                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3136             for (temp = NEXT_INSN (i2);
3137                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3138                           || BB_HEAD (this_basic_block) != temp);
3139                  temp = NEXT_INSN (temp))
3140               if (temp != i3 && INSN_P (temp))
3141                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3142                   if (XEXP (link, 0) == i2)
3143                     XEXP (link, 0) = i3;
3144
3145         if (i3notes)
3146           {
3147             rtx link = i3notes;
3148             while (XEXP (link, 1))
3149               link = XEXP (link, 1);
3150             XEXP (link, 1) = i2notes;
3151           }
3152         else
3153           i3notes = i2notes;
3154         i2notes = 0;
3155       }
3156
3157     LOG_LINKS (i3) = 0;
3158     REG_NOTES (i3) = 0;
3159     LOG_LINKS (i2) = 0;
3160     REG_NOTES (i2) = 0;
3161
3162     if (newi2pat)
3163       {
3164         INSN_CODE (i2) = i2_code_number;
3165         PATTERN (i2) = newi2pat;
3166       }
3167     else
3168       SET_INSN_DELETED (i2);
3169
3170     if (i1)
3171       {
3172         LOG_LINKS (i1) = 0;
3173         REG_NOTES (i1) = 0;
3174         SET_INSN_DELETED (i1);
3175       }
3176
3177     /* Get death notes for everything that is now used in either I3 or
3178        I2 and used to die in a previous insn.  If we built two new
3179        patterns, move from I1 to I2 then I2 to I3 so that we get the
3180        proper movement on registers that I2 modifies.  */
3181
3182     if (newi2pat)
3183       {
3184         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3185         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3186       }
3187     else
3188       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3189                    i3, &midnotes);
3190
3191     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3192     if (i3notes)
3193       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3194                         elim_i2, elim_i1);
3195     if (i2notes)
3196       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3197                         elim_i2, elim_i1);
3198     if (i1notes)
3199       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3200                         elim_i2, elim_i1);
3201     if (midnotes)
3202       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3203                         elim_i2, elim_i1);
3204
3205     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3206        know these are REG_UNUSED and want them to go to the desired insn,
3207        so we always pass it as i3.  We have not counted the notes in
3208        reg_n_deaths yet, so we need to do so now.  */
3209
3210     if (newi2pat && new_i2_notes)
3211       {
3212         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3213           if (REG_P (XEXP (temp, 0)))
3214             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3215
3216         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3217       }
3218
3219     if (new_i3_notes)
3220       {
3221         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3222           if (REG_P (XEXP (temp, 0)))
3223             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3224
3225         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3226       }
3227
3228     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3229        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3230        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3231        in that case, it might delete I2.  Similarly for I2 and I1.
3232        Show an additional death due to the REG_DEAD note we make here.  If
3233        we discard it in distribute_notes, we will decrement it again.  */
3234
3235     if (i3dest_killed)
3236       {
3237         if (REG_P (i3dest_killed))
3238           REG_N_DEATHS (REGNO (i3dest_killed))++;
3239
3240         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3241           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3242                                                NULL_RTX),
3243                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3244         else
3245           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3246                                                NULL_RTX),
3247                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3248                             elim_i2, elim_i1);
3249       }
3250
3251     if (i2dest_in_i2src)
3252       {
3253         if (REG_P (i2dest))
3254           REG_N_DEATHS (REGNO (i2dest))++;
3255
3256         if (newi2pat && reg_set_p (i2dest, newi2pat))
3257           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3258                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3259         else
3260           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3261                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3262                             NULL_RTX, NULL_RTX);
3263       }
3264
3265     if (i1dest_in_i1src)
3266       {
3267         if (REG_P (i1dest))
3268           REG_N_DEATHS (REGNO (i1dest))++;
3269
3270         if (newi2pat && reg_set_p (i1dest, newi2pat))
3271           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3272                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3273         else
3274           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3275                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3276                             NULL_RTX, NULL_RTX);
3277       }
3278
3279     distribute_links (i3links);
3280     distribute_links (i2links);
3281     distribute_links (i1links);
3282
3283     if (REG_P (i2dest))
3284       {
3285         rtx link;
3286         rtx i2_insn = 0, i2_val = 0, set;
3287
3288         /* The insn that used to set this register doesn't exist, and
3289            this life of the register may not exist either.  See if one of
3290            I3's links points to an insn that sets I2DEST.  If it does,
3291            that is now the last known value for I2DEST. If we don't update
3292            this and I2 set the register to a value that depended on its old
3293            contents, we will get confused.  If this insn is used, thing
3294            will be set correctly in combine_instructions.  */
3295
3296         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3297           if ((set = single_set (XEXP (link, 0))) != 0
3298               && rtx_equal_p (i2dest, SET_DEST (set)))
3299             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3300
3301         record_value_for_reg (i2dest, i2_insn, i2_val);
3302
3303         /* If the reg formerly set in I2 died only once and that was in I3,
3304            zero its use count so it won't make `reload' do any work.  */
3305         if (! added_sets_2
3306             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3307             && ! i2dest_in_i2src)
3308           {
3309             regno = REGNO (i2dest);
3310             REG_N_SETS (regno)--;
3311           }
3312       }
3313
3314     if (i1 && REG_P (i1dest))
3315       {
3316         rtx link;
3317         rtx i1_insn = 0, i1_val = 0, set;
3318
3319         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3320           if ((set = single_set (XEXP (link, 0))) != 0
3321               && rtx_equal_p (i1dest, SET_DEST (set)))
3322             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3323
3324         record_value_for_reg (i1dest, i1_insn, i1_val);
3325
3326         regno = REGNO (i1dest);
3327         if (! added_sets_1 && ! i1dest_in_i1src)
3328           REG_N_SETS (regno)--;
3329       }
3330
3331     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3332        been made to this insn.  The order of
3333        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3334        can affect nonzero_bits of newpat */
3335     if (newi2pat)
3336       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3337     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3338
3339     /* Set new_direct_jump_p if a new return or simple jump instruction
3340        has been created.
3341
3342        If I3 is now an unconditional jump, ensure that it has a
3343        BARRIER following it since it may have initially been a
3344        conditional jump.  It may also be the last nonnote insn.  */
3345
3346     if (returnjump_p (i3) || any_uncondjump_p (i3))
3347       {
3348         *new_direct_jump_p = 1;
3349         mark_jump_label (PATTERN (i3), i3, 0);
3350
3351         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3352             || !BARRIER_P (temp))
3353           emit_barrier_after (i3);
3354       }
3355
3356     if (undobuf.other_insn != NULL_RTX
3357         && (returnjump_p (undobuf.other_insn)
3358             || any_uncondjump_p (undobuf.other_insn)))
3359       {
3360         *new_direct_jump_p = 1;
3361
3362         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3363             || !BARRIER_P (temp))
3364           emit_barrier_after (undobuf.other_insn);
3365       }
3366
3367     /* An NOOP jump does not need barrier, but it does need cleaning up
3368        of CFG.  */
3369     if (GET_CODE (newpat) == SET
3370         && SET_SRC (newpat) == pc_rtx
3371         && SET_DEST (newpat) == pc_rtx)
3372       *new_direct_jump_p = 1;
3373   }
3374
3375   combine_successes++;
3376   undo_commit ();
3377
3378   if (added_links_insn
3379       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3380       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3381     return added_links_insn;
3382   else
3383     return newi2pat ? i2 : i3;
3384 }
3385 \f
3386 /* Undo all the modifications recorded in undobuf.  */
3387
3388 static void
3389 undo_all (void)
3390 {
3391   struct undo *undo, *next;
3392
3393   for (undo = undobuf.undos; undo; undo = next)
3394     {
3395       next = undo->next;
3396       switch (undo->kind)
3397         {
3398         case UNDO_RTX:
3399           *undo->where.r = undo->old_contents.r;
3400           break;
3401         case UNDO_INT:
3402           *undo->where.i = undo->old_contents.i;
3403           break;
3404         case UNDO_MODE:
3405           PUT_MODE (*undo->where.r, undo->old_contents.m);
3406           break;
3407         default:
3408           gcc_unreachable ();
3409         }
3410
3411       undo->next = undobuf.frees;
3412       undobuf.frees = undo;
3413     }
3414
3415   undobuf.undos = 0;
3416 }
3417
3418 /* We've committed to accepting the changes we made.  Move all
3419    of the undos to the free list.  */
3420
3421 static void
3422 undo_commit (void)
3423 {
3424   struct undo *undo, *next;
3425
3426   for (undo = undobuf.undos; undo; undo = next)
3427     {
3428       next = undo->next;
3429       undo->next = undobuf.frees;
3430       undobuf.frees = undo;
3431     }
3432   undobuf.undos = 0;
3433 }
3434
3435 \f
3436 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3437    where we have an arithmetic expression and return that point.  LOC will
3438    be inside INSN.
3439
3440    try_combine will call this function to see if an insn can be split into
3441    two insns.  */
3442
3443 static rtx *
3444 find_split_point (rtx *loc, rtx insn)
3445 {
3446   rtx x = *loc;
3447   enum rtx_code code = GET_CODE (x);
3448   rtx *split;
3449   unsigned HOST_WIDE_INT len = 0;
3450   HOST_WIDE_INT pos = 0;
3451   int unsignedp = 0;
3452   rtx inner = NULL_RTX;
3453
3454   /* First special-case some codes.  */
3455   switch (code)
3456     {
3457     case SUBREG:
3458 #ifdef INSN_SCHEDULING
3459       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3460          point.  */
3461       if (MEM_P (SUBREG_REG (x)))
3462         return loc;
3463 #endif
3464       return find_split_point (&SUBREG_REG (x), insn);
3465
3466     case MEM:
3467 #ifdef HAVE_lo_sum
3468       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3469          using LO_SUM and HIGH.  */
3470       if (GET_CODE (XEXP (x, 0)) == CONST
3471           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3472         {
3473           SUBST (XEXP (x, 0),
3474                  gen_rtx_LO_SUM (Pmode,
3475                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3476                                  XEXP (x, 0)));
3477           return &XEXP (XEXP (x, 0), 0);
3478         }
3479 #endif
3480
3481       /* If we have a PLUS whose second operand is a constant and the
3482          address is not valid, perhaps will can split it up using
3483          the machine-specific way to split large constants.  We use
3484          the first pseudo-reg (one of the virtual regs) as a placeholder;
3485          it will not remain in the result.  */
3486       if (GET_CODE (XEXP (x, 0)) == PLUS
3487           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3488           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3489         {
3490           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3491           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3492                                  subst_insn);
3493
3494           /* This should have produced two insns, each of which sets our
3495              placeholder.  If the source of the second is a valid address,
3496              we can make put both sources together and make a split point
3497              in the middle.  */
3498
3499           if (seq
3500               && NEXT_INSN (seq) != NULL_RTX
3501               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3502               && NONJUMP_INSN_P (seq)
3503               && GET_CODE (PATTERN (seq)) == SET
3504               && SET_DEST (PATTERN (seq)) == reg
3505               && ! reg_mentioned_p (reg,
3506                                     SET_SRC (PATTERN (seq)))
3507               && NONJUMP_INSN_P (NEXT_INSN (seq))
3508               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3509               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3510               && memory_address_p (GET_MODE (x),
3511                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3512             {
3513               rtx src1 = SET_SRC (PATTERN (seq));
3514               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3515
3516               /* Replace the placeholder in SRC2 with SRC1.  If we can
3517                  find where in SRC2 it was placed, that can become our
3518                  split point and we can replace this address with SRC2.
3519                  Just try two obvious places.  */
3520
3521               src2 = replace_rtx (src2, reg, src1);
3522               split = 0;
3523               if (XEXP (src2, 0) == src1)
3524                 split = &XEXP (src2, 0);
3525               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3526                        && XEXP (XEXP (src2, 0), 0) == src1)
3527                 split = &XEXP (XEXP (src2, 0), 0);
3528
3529               if (split)
3530                 {
3531                   SUBST (XEXP (x, 0), src2);
3532                   return split;
3533                 }
3534             }
3535
3536           /* If that didn't work, perhaps the first operand is complex and
3537              needs to be computed separately, so make a split point there.
3538              This will occur on machines that just support REG + CONST
3539              and have a constant moved through some previous computation.  */
3540
3541           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3542                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3543                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3544             return &XEXP (XEXP (x, 0), 0);
3545         }
3546       break;
3547
3548     case SET:
3549 #ifdef HAVE_cc0
3550       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3551          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3552          we need to put the operand into a register.  So split at that
3553          point.  */
3554
3555       if (SET_DEST (x) == cc0_rtx
3556           && GET_CODE (SET_SRC (x)) != COMPARE
3557           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3558           && !OBJECT_P (SET_SRC (x))
3559           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3560                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3561         return &SET_SRC (x);
3562 #endif
3563
3564       /* See if we can split SET_SRC as it stands.  */
3565       split = find_split_point (&SET_SRC (x), insn);
3566       if (split && split != &SET_SRC (x))
3567         return split;
3568
3569       /* See if we can split SET_DEST as it stands.  */
3570       split = find_split_point (&SET_DEST (x), insn);
3571       if (split && split != &SET_DEST (x))
3572         return split;
3573
3574       /* See if this is a bitfield assignment with everything constant.  If
3575          so, this is an IOR of an AND, so split it into that.  */
3576       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3577           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3578               <= HOST_BITS_PER_WIDE_INT)
3579           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3580           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3581           && GET_CODE (SET_SRC (x)) == CONST_INT
3582           && ((INTVAL (XEXP (SET_DEST (x), 1))
3583                + INTVAL (XEXP (SET_DEST (x), 2)))
3584               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3585           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3586         {
3587           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3588           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3589           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3590           rtx dest = XEXP (SET_DEST (x), 0);
3591           enum machine_mode mode = GET_MODE (dest);
3592           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3593           rtx or_mask;
3594
3595           if (BITS_BIG_ENDIAN)
3596             pos = GET_MODE_BITSIZE (mode) - len - pos;
3597
3598           or_mask = gen_int_mode (src << pos, mode);
3599           if (src == mask)
3600             SUBST (SET_SRC (x),
3601                    simplify_gen_binary (IOR, mode, dest, or_mask));
3602           else
3603             {
3604               rtx negmask = gen_int_mode (~(mask << pos), mode);
3605               SUBST (SET_SRC (x),
3606                      simplify_gen_binary (IOR, mode,
3607                                           simplify_gen_binary (AND, mode,
3608                                                                dest, negmask),
3609                                           or_mask));
3610             }
3611
3612           SUBST (SET_DEST (x), dest);
3613
3614           split = find_split_point (&SET_SRC (x), insn);
3615           if (split && split != &SET_SRC (x))
3616             return split;
3617         }
3618
3619       /* Otherwise, see if this is an operation that we can split into two.
3620          If so, try to split that.  */
3621       code = GET_CODE (SET_SRC (x));
3622
3623       switch (code)
3624         {
3625         case AND:
3626           /* If we are AND'ing with a large constant that is only a single
3627              bit and the result is only being used in a context where we
3628              need to know if it is zero or nonzero, replace it with a bit
3629              extraction.  This will avoid the large constant, which might
3630              have taken more than one insn to make.  If the constant were
3631              not a valid argument to the AND but took only one insn to make,
3632              this is no worse, but if it took more than one insn, it will
3633              be better.  */
3634
3635           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3636               && REG_P (XEXP (SET_SRC (x), 0))
3637               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3638               && REG_P (SET_DEST (x))
3639               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3640               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3641               && XEXP (*split, 0) == SET_DEST (x)
3642               && XEXP (*split, 1) == const0_rtx)
3643             {
3644               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3645                                                 XEXP (SET_SRC (x), 0),
3646                                                 pos, NULL_RTX, 1, 1, 0, 0);
3647               if (extraction != 0)
3648                 {
3649                   SUBST (SET_SRC (x), extraction);
3650                   return find_split_point (loc, insn);
3651                 }
3652             }
3653           break;
3654
3655         case NE:
3656           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3657              is known to be on, this can be converted into a NEG of a shift.  */
3658           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3659               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3660               && 1 <= (pos = exact_log2
3661                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3662                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3663             {
3664               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3665
3666               SUBST (SET_SRC (x),
3667                      gen_rtx_NEG (mode,
3668                                   gen_rtx_LSHIFTRT (mode,
3669                                                     XEXP (SET_SRC (x), 0),
3670                                                     GEN_INT (pos))));
3671
3672               split = find_split_point (&SET_SRC (x), insn);
3673               if (split && split != &SET_SRC (x))
3674                 return split;
3675             }
3676           break;
3677
3678         case SIGN_EXTEND:
3679           inner = XEXP (SET_SRC (x), 0);
3680
3681           /* We can't optimize if either mode is a partial integer
3682              mode as we don't know how many bits are significant
3683              in those modes.  */
3684           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3685               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3686             break;
3687
3688           pos = 0;
3689           len = GET_MODE_BITSIZE (GET_MODE (inner));
3690           unsignedp = 0;
3691           break;
3692
3693         case SIGN_EXTRACT:
3694         case ZERO_EXTRACT:
3695           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3696               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3697             {
3698               inner = XEXP (SET_SRC (x), 0);
3699               len = INTVAL (XEXP (SET_SRC (x), 1));
3700               pos = INTVAL (XEXP (SET_SRC (x), 2));
3701
3702               if (BITS_BIG_ENDIAN)
3703                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3704               unsignedp = (code == ZERO_EXTRACT);
3705             }
3706           break;
3707
3708         default:
3709           break;
3710         }
3711
3712       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3713         {
3714           enum machine_mode mode = GET_MODE (SET_SRC (x));
3715
3716           /* For unsigned, we have a choice of a shift followed by an
3717              AND or two shifts.  Use two shifts for field sizes where the
3718              constant might be too large.  We assume here that we can
3719              always at least get 8-bit constants in an AND insn, which is
3720              true for every current RISC.  */
3721
3722           if (unsignedp && len <= 8)
3723             {
3724               SUBST (SET_SRC (x),
3725                      gen_rtx_AND (mode,
3726                                   gen_rtx_LSHIFTRT
3727                                   (mode, gen_lowpart (mode, inner),
3728                                    GEN_INT (pos)),
3729                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3730
3731               split = find_split_point (&SET_SRC (x), insn);
3732               if (split && split != &SET_SRC (x))
3733                 return split;
3734             }
3735           else
3736             {
3737               SUBST (SET_SRC (x),
3738                      gen_rtx_fmt_ee
3739                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3740                       gen_rtx_ASHIFT (mode,
3741                                       gen_lowpart (mode, inner),
3742                                       GEN_INT (GET_MODE_BITSIZE (mode)
3743                                                - len - pos)),
3744                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3745
3746               split = find_split_point (&SET_SRC (x), insn);
3747               if (split && split != &SET_SRC (x))
3748                 return split;
3749             }
3750         }
3751
3752       /* See if this is a simple operation with a constant as the second
3753          operand.  It might be that this constant is out of range and hence
3754          could be used as a split point.  */
3755       if (BINARY_P (SET_SRC (x))
3756           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3757           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3758               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3759                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3760         return &XEXP (SET_SRC (x), 1);
3761
3762       /* Finally, see if this is a simple operation with its first operand
3763          not in a register.  The operation might require this operand in a
3764          register, so return it as a split point.  We can always do this
3765          because if the first operand were another operation, we would have
3766          already found it as a split point.  */
3767       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3768           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3769         return &XEXP (SET_SRC (x), 0);
3770
3771       return 0;
3772
3773     case AND:
3774     case IOR:
3775       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3776          it is better to write this as (not (ior A B)) so we can split it.
3777          Similarly for IOR.  */
3778       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3779         {
3780           SUBST (*loc,
3781                  gen_rtx_NOT (GET_MODE (x),
3782                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3783                                               GET_MODE (x),
3784                                               XEXP (XEXP (x, 0), 0),
3785                                               XEXP (XEXP (x, 1), 0))));
3786           return find_split_point (loc, insn);
3787         }
3788
3789       /* Many RISC machines have a large set of logical insns.  If the
3790          second operand is a NOT, put it first so we will try to split the
3791          other operand first.  */
3792       if (GET_CODE (XEXP (x, 1)) == NOT)
3793         {
3794           rtx tem = XEXP (x, 0);
3795           SUBST (XEXP (x, 0), XEXP (x, 1));
3796           SUBST (XEXP (x, 1), tem);
3797         }
3798       break;
3799
3800     default:
3801       break;
3802     }
3803
3804   /* Otherwise, select our actions depending on our rtx class.  */
3805   switch (GET_RTX_CLASS (code))
3806     {
3807     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3808     case RTX_TERNARY:
3809       split = find_split_point (&XEXP (x, 2), insn);
3810       if (split)
3811         return split;
3812       /* ... fall through ...  */
3813     case RTX_BIN_ARITH:
3814     case RTX_COMM_ARITH:
3815     case RTX_COMPARE:
3816     case RTX_COMM_COMPARE:
3817       split = find_split_point (&XEXP (x, 1), insn);
3818       if (split)
3819         return split;
3820       /* ... fall through ...  */
3821     case RTX_UNARY:
3822       /* Some machines have (and (shift ...) ...) insns.  If X is not
3823          an AND, but XEXP (X, 0) is, use it as our split point.  */
3824       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3825         return &XEXP (x, 0);
3826
3827       split = find_split_point (&XEXP (x, 0), insn);
3828       if (split)
3829         return split;
3830       return loc;
3831
3832     default:
3833       /* Otherwise, we don't have a split point.  */
3834       return 0;
3835     }
3836 }
3837 \f
3838 /* Throughout X, replace FROM with TO, and return the result.
3839    The result is TO if X is FROM;
3840    otherwise the result is X, but its contents may have been modified.
3841    If they were modified, a record was made in undobuf so that
3842    undo_all will (among other things) return X to its original state.
3843
3844    If the number of changes necessary is too much to record to undo,
3845    the excess changes are not made, so the result is invalid.
3846    The changes already made can still be undone.
3847    undobuf.num_undo is incremented for such changes, so by testing that
3848    the caller can tell whether the result is valid.
3849
3850    `n_occurrences' is incremented each time FROM is replaced.
3851
3852    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3853
3854    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3855    by copying if `n_occurrences' is nonzero.  */
3856
3857 static rtx
3858 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3859 {
3860   enum rtx_code code = GET_CODE (x);
3861   enum machine_mode op0_mode = VOIDmode;
3862   const char *fmt;
3863   int len, i;
3864   rtx new;
3865
3866 /* Two expressions are equal if they are identical copies of a shared
3867    RTX or if they are both registers with the same register number
3868    and mode.  */
3869
3870 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3871   ((X) == (Y)                                           \
3872    || (REG_P (X) && REG_P (Y)   \
3873        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3874
3875   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3876     {
3877       n_occurrences++;
3878       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3879     }
3880
3881   /* If X and FROM are the same register but different modes, they will
3882      not have been seen as equal above.  However, flow.c will make a
3883      LOG_LINKS entry for that case.  If we do nothing, we will try to
3884      rerecognize our original insn and, when it succeeds, we will
3885      delete the feeding insn, which is incorrect.
3886
3887      So force this insn not to match in this (rare) case.  */
3888   if (! in_dest && code == REG && REG_P (from)
3889       && REGNO (x) == REGNO (from))
3890     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3891
3892   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3893      of which may contain things that can be combined.  */
3894   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3895     return x;
3896
3897   /* It is possible to have a subexpression appear twice in the insn.
3898      Suppose that FROM is a register that appears within TO.
3899      Then, after that subexpression has been scanned once by `subst',
3900      the second time it is scanned, TO may be found.  If we were
3901      to scan TO here, we would find FROM within it and create a
3902      self-referent rtl structure which is completely wrong.  */
3903   if (COMBINE_RTX_EQUAL_P (x, to))
3904     return to;
3905
3906   /* Parallel asm_operands need special attention because all of the
3907      inputs are shared across the arms.  Furthermore, unsharing the
3908      rtl results in recognition failures.  Failure to handle this case
3909      specially can result in circular rtl.
3910
3911      Solve this by doing a normal pass across the first entry of the
3912      parallel, and only processing the SET_DESTs of the subsequent
3913      entries.  Ug.  */
3914
3915   if (code == PARALLEL
3916       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3917       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3918     {
3919       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3920
3921       /* If this substitution failed, this whole thing fails.  */
3922       if (GET_CODE (new) == CLOBBER
3923           && XEXP (new, 0) == const0_rtx)
3924         return new;
3925
3926       SUBST (XVECEXP (x, 0, 0), new);
3927
3928       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3929         {
3930           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3931
3932           if (!REG_P (dest)
3933               && GET_CODE (dest) != CC0
3934               && GET_CODE (dest) != PC)
3935             {
3936               new = subst (dest, from, to, 0, unique_copy);
3937
3938               /* If this substitution failed, this whole thing fails.  */
3939               if (GET_CODE (new) == CLOBBER
3940                   && XEXP (new, 0) == const0_rtx)
3941                 return new;
3942
3943               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3944             }
3945         }
3946     }
3947   else
3948     {
3949       len = GET_RTX_LENGTH (code);
3950       fmt = GET_RTX_FORMAT (code);
3951
3952       /* We don't need to process a SET_DEST that is a register, CC0,
3953          or PC, so set up to skip this common case.  All other cases
3954          where we want to suppress replacing something inside a
3955          SET_SRC are handled via the IN_DEST operand.  */
3956       if (code == SET
3957           && (REG_P (SET_DEST (x))
3958               || GET_CODE (SET_DEST (x)) == CC0
3959               || GET_CODE (SET_DEST (x)) == PC))
3960         fmt = "ie";
3961
3962       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3963          constant.  */
3964       if (fmt[0] == 'e')
3965         op0_mode = GET_MODE (XEXP (x, 0));
3966
3967       for (i = 0; i < len; i++)
3968         {
3969           if (fmt[i] == 'E')
3970             {
3971               int j;
3972               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3973                 {
3974                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3975                     {
3976                       new = (unique_copy && n_occurrences
3977                              ? copy_rtx (to) : to);
3978                       n_occurrences++;
3979                     }
3980                   else
3981                     {
3982                       new = subst (XVECEXP (x, i, j), from, to, 0,
3983                                    unique_copy);
3984
3985                       /* If this substitution failed, this whole thing
3986                          fails.  */
3987                       if (GET_CODE (new) == CLOBBER
3988                           && XEXP (new, 0) == const0_rtx)
3989                         return new;
3990                     }
3991
3992                   SUBST (XVECEXP (x, i, j), new);
3993                 }
3994             }
3995           else if (fmt[i] == 'e')
3996             {
3997               /* If this is a register being set, ignore it.  */
3998               new = XEXP (x, i);
3999               if (in_dest
4000                   && i == 0
4001                   && (((code == SUBREG || code == ZERO_EXTRACT)
4002                        && REG_P (new))
4003                       || code == STRICT_LOW_PART))
4004                 ;
4005
4006               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4007                 {
4008                   /* In general, don't install a subreg involving two
4009                      modes not tieable.  It can worsen register
4010                      allocation, and can even make invalid reload
4011                      insns, since the reg inside may need to be copied
4012                      from in the outside mode, and that may be invalid
4013                      if it is an fp reg copied in integer mode.
4014
4015                      We allow two exceptions to this: It is valid if
4016                      it is inside another SUBREG and the mode of that
4017                      SUBREG and the mode of the inside of TO is
4018                      tieable and it is valid if X is a SET that copies
4019                      FROM to CC0.  */
4020
4021                   if (GET_CODE (to) == SUBREG
4022                       && ! MODES_TIEABLE_P (GET_MODE (to),
4023                                             GET_MODE (SUBREG_REG (to)))
4024                       && ! (code == SUBREG
4025                             && MODES_TIEABLE_P (GET_MODE (x),
4026                                                 GET_MODE (SUBREG_REG (to))))
4027 #ifdef HAVE_cc0
4028                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4029 #endif
4030                       )
4031                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4032
4033 #ifdef CANNOT_CHANGE_MODE_CLASS
4034                   if (code == SUBREG
4035                       && REG_P (to)
4036                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4037                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4038                                                    GET_MODE (to),
4039                                                    GET_MODE (x)))
4040                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4041 #endif
4042
4043                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4044                   n_occurrences++;
4045                 }
4046               else
4047                 /* If we are in a SET_DEST, suppress most cases unless we
4048                    have gone inside a MEM, in which case we want to
4049                    simplify the address.  We assume here that things that
4050                    are actually part of the destination have their inner
4051                    parts in the first expression.  This is true for SUBREG,
4052                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4053                    things aside from REG and MEM that should appear in a
4054                    SET_DEST.  */
4055                 new = subst (XEXP (x, i), from, to,
4056                              (((in_dest
4057                                 && (code == SUBREG || code == STRICT_LOW_PART
4058                                     || code == ZERO_EXTRACT))
4059                                || code == SET)
4060                               && i == 0), unique_copy);
4061
4062               /* If we found that we will have to reject this combination,
4063                  indicate that by returning the CLOBBER ourselves, rather than
4064                  an expression containing it.  This will speed things up as
4065                  well as prevent accidents where two CLOBBERs are considered
4066                  to be equal, thus producing an incorrect simplification.  */
4067
4068               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4069                 return new;
4070
4071               if (GET_CODE (x) == SUBREG
4072                   && (GET_CODE (new) == CONST_INT
4073                       || GET_CODE (new) == CONST_DOUBLE))
4074                 {
4075                   enum machine_mode mode = GET_MODE (x);
4076
4077                   x = simplify_subreg (GET_MODE (x), new,
4078                                        GET_MODE (SUBREG_REG (x)),
4079                                        SUBREG_BYTE (x));
4080                   if (! x)
4081                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4082                 }
4083               else if (GET_CODE (new) == CONST_INT
4084                        && GET_CODE (x) == ZERO_EXTEND)
4085                 {
4086                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4087                                                 new, GET_MODE (XEXP (x, 0)));
4088                   gcc_assert (x);
4089                 }
4090               else
4091                 SUBST (XEXP (x, i), new);
4092             }
4093         }
4094     }
4095
4096   /* Try to simplify X.  If the simplification changed the code, it is likely
4097      that further simplification will help, so loop, but limit the number
4098      of repetitions that will be performed.  */
4099
4100   for (i = 0; i < 4; i++)
4101     {
4102       /* If X is sufficiently simple, don't bother trying to do anything
4103          with it.  */
4104       if (code != CONST_INT && code != REG && code != CLOBBER)
4105         x = combine_simplify_rtx (x, op0_mode, in_dest);
4106
4107       if (GET_CODE (x) == code)
4108         break;
4109
4110       code = GET_CODE (x);
4111
4112       /* We no longer know the original mode of operand 0 since we
4113          have changed the form of X)  */
4114       op0_mode = VOIDmode;
4115     }
4116
4117   return x;
4118 }
4119 \f
4120 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4121    outer level; call `subst' to simplify recursively.  Return the new
4122    expression.
4123
4124    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4125    if we are inside a SET_DEST.  */
4126
4127 static rtx
4128 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4129 {
4130   enum rtx_code code = GET_CODE (x);
4131   enum machine_mode mode = GET_MODE (x);
4132   rtx temp;
4133   int i;
4134
4135   /* If this is a commutative operation, put a constant last and a complex
4136      expression first.  We don't need to do this for comparisons here.  */
4137   if (COMMUTATIVE_ARITH_P (x)
4138       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4139     {
4140       temp = XEXP (x, 0);
4141       SUBST (XEXP (x, 0), XEXP (x, 1));
4142       SUBST (XEXP (x, 1), temp);
4143     }
4144
4145   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4146      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4147      things.  Check for cases where both arms are testing the same
4148      condition.
4149
4150      Don't do anything if all operands are very simple.  */
4151
4152   if ((BINARY_P (x)
4153        && ((!OBJECT_P (XEXP (x, 0))
4154             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4155                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4156            || (!OBJECT_P (XEXP (x, 1))
4157                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4158                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4159       || (UNARY_P (x)
4160           && (!OBJECT_P (XEXP (x, 0))
4161                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4162                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4163     {
4164       rtx cond, true_rtx, false_rtx;
4165
4166       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4167       if (cond != 0
4168           /* If everything is a comparison, what we have is highly unlikely
4169              to be simpler, so don't use it.  */
4170           && ! (COMPARISON_P (x)
4171                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4172         {
4173           rtx cop1 = const0_rtx;
4174           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4175
4176           if (cond_code == NE && COMPARISON_P (cond))
4177             return x;
4178
4179           /* Simplify the alternative arms; this may collapse the true and
4180              false arms to store-flag values.  Be careful to use copy_rtx
4181              here since true_rtx or false_rtx might share RTL with x as a
4182              result of the if_then_else_cond call above.  */
4183           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4184           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4185
4186           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4187              is unlikely to be simpler.  */
4188           if (general_operand (true_rtx, VOIDmode)
4189               && general_operand (false_rtx, VOIDmode))
4190             {
4191               enum rtx_code reversed;
4192
4193               /* Restarting if we generate a store-flag expression will cause
4194                  us to loop.  Just drop through in this case.  */
4195
4196               /* If the result values are STORE_FLAG_VALUE and zero, we can
4197                  just make the comparison operation.  */
4198               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4199                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4200                                              cond, cop1);
4201               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4202                        && ((reversed = reversed_comparison_code_parts
4203                                         (cond_code, cond, cop1, NULL))
4204                            != UNKNOWN))
4205                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4206                                              cond, cop1);
4207
4208               /* Likewise, we can make the negate of a comparison operation
4209                  if the result values are - STORE_FLAG_VALUE and zero.  */
4210               else if (GET_CODE (true_rtx) == CONST_INT
4211                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4212                        && false_rtx == const0_rtx)
4213                 x = simplify_gen_unary (NEG, mode,
4214                                         simplify_gen_relational (cond_code,
4215                                                                  mode, VOIDmode,
4216                                                                  cond, cop1),
4217                                         mode);
4218               else if (GET_CODE (false_rtx) == CONST_INT
4219                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4220                        && true_rtx == const0_rtx
4221                        && ((reversed = reversed_comparison_code_parts
4222                                         (cond_code, cond, cop1, NULL))
4223                            != UNKNOWN))
4224                 x = simplify_gen_unary (NEG, mode,
4225                                         simplify_gen_relational (reversed,
4226                                                                  mode, VOIDmode,
4227                                                                  cond, cop1),
4228                                         mode);
4229               else
4230                 return gen_rtx_IF_THEN_ELSE (mode,
4231                                              simplify_gen_relational (cond_code,
4232                                                                       mode,
4233                                                                       VOIDmode,
4234                                                                       cond,
4235                                                                       cop1),
4236                                              true_rtx, false_rtx);
4237
4238               code = GET_CODE (x);
4239               op0_mode = VOIDmode;
4240             }
4241         }
4242     }
4243
4244   /* Try to fold this expression in case we have constants that weren't
4245      present before.  */
4246   temp = 0;
4247   switch (GET_RTX_CLASS (code))
4248     {
4249     case RTX_UNARY:
4250       if (op0_mode == VOIDmode)
4251         op0_mode = GET_MODE (XEXP (x, 0));
4252       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4253       break;
4254     case RTX_COMPARE:
4255     case RTX_COMM_COMPARE:
4256       {
4257         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4258         if (cmp_mode == VOIDmode)
4259           {
4260             cmp_mode = GET_MODE (XEXP (x, 1));
4261             if (cmp_mode == VOIDmode)
4262               cmp_mode = op0_mode;
4263           }
4264         temp = simplify_relational_operation (code, mode, cmp_mode,
4265                                               XEXP (x, 0), XEXP (x, 1));
4266       }
4267       break;
4268     case RTX_COMM_ARITH:
4269     case RTX_BIN_ARITH:
4270       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4271       break;
4272     case RTX_BITFIELD_OPS:
4273     case RTX_TERNARY:
4274       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4275                                          XEXP (x, 1), XEXP (x, 2));
4276       break;
4277     default:
4278       break;
4279     }
4280
4281   if (temp)
4282     {
4283       x = temp;
4284       code = GET_CODE (temp);
4285       op0_mode = VOIDmode;
4286       mode = GET_MODE (temp);
4287     }
4288
4289   /* First see if we can apply the inverse distributive law.  */
4290   if (code == PLUS || code == MINUS
4291       || code == AND || code == IOR || code == XOR)
4292     {
4293       x = apply_distributive_law (x);
4294       code = GET_CODE (x);
4295       op0_mode = VOIDmode;
4296     }
4297
4298   /* If CODE is an associative operation not otherwise handled, see if we
4299      can associate some operands.  This can win if they are constants or
4300      if they are logically related (i.e. (a & b) & a).  */
4301   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4302        || code == AND || code == IOR || code == XOR
4303        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4304       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4305           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4306     {
4307       if (GET_CODE (XEXP (x, 0)) == code)
4308         {
4309           rtx other = XEXP (XEXP (x, 0), 0);
4310           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4311           rtx inner_op1 = XEXP (x, 1);
4312           rtx inner;
4313
4314           /* Make sure we pass the constant operand if any as the second
4315              one if this is a commutative operation.  */
4316           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4317             {
4318               rtx tem = inner_op0;
4319               inner_op0 = inner_op1;
4320               inner_op1 = tem;
4321             }
4322           inner = simplify_binary_operation (code == MINUS ? PLUS
4323                                              : code == DIV ? MULT
4324                                              : code,
4325                                              mode, inner_op0, inner_op1);
4326
4327           /* For commutative operations, try the other pair if that one
4328              didn't simplify.  */
4329           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4330             {
4331               other = XEXP (XEXP (x, 0), 1);
4332               inner = simplify_binary_operation (code, mode,
4333                                                  XEXP (XEXP (x, 0), 0),
4334                                                  XEXP (x, 1));
4335             }
4336
4337           if (inner)
4338             return simplify_gen_binary (code, mode, other, inner);
4339         }
4340     }
4341
4342   /* A little bit of algebraic simplification here.  */
4343   switch (code)
4344     {
4345     case MEM:
4346       /* Ensure that our address has any ASHIFTs converted to MULT in case
4347          address-recognizing predicates are called later.  */
4348       temp = make_compound_operation (XEXP (x, 0), MEM);
4349       SUBST (XEXP (x, 0), temp);
4350       break;
4351
4352     case SUBREG:
4353       if (op0_mode == VOIDmode)
4354         op0_mode = GET_MODE (SUBREG_REG (x));
4355
4356       /* See if this can be moved to simplify_subreg.  */
4357       if (CONSTANT_P (SUBREG_REG (x))
4358           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4359              /* Don't call gen_lowpart if the inner mode
4360                 is VOIDmode and we cannot simplify it, as SUBREG without
4361                 inner mode is invalid.  */
4362           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4363               || gen_lowpart_common (mode, SUBREG_REG (x))))
4364         return gen_lowpart (mode, SUBREG_REG (x));
4365
4366       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4367         break;
4368       {
4369         rtx temp;
4370         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4371                                 SUBREG_BYTE (x));
4372         if (temp)
4373           return temp;
4374       }
4375
4376       /* Don't change the mode of the MEM if that would change the meaning
4377          of the address.  */
4378       if (MEM_P (SUBREG_REG (x))
4379           && (MEM_VOLATILE_P (SUBREG_REG (x))
4380               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4381         return gen_rtx_CLOBBER (mode, const0_rtx);
4382
4383       /* Note that we cannot do any narrowing for non-constants since
4384          we might have been counting on using the fact that some bits were
4385          zero.  We now do this in the SET.  */
4386
4387       break;
4388
4389     case NEG:
4390       temp = expand_compound_operation (XEXP (x, 0));
4391
4392       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4393          replaced by (lshiftrt X C).  This will convert
4394          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4395
4396       if (GET_CODE (temp) == ASHIFTRT
4397           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4398           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4399         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4400                                      INTVAL (XEXP (temp, 1)));
4401
4402       /* If X has only a single bit that might be nonzero, say, bit I, convert
4403          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4404          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4405          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4406          or a SUBREG of one since we'd be making the expression more
4407          complex if it was just a register.  */
4408
4409       if (!REG_P (temp)
4410           && ! (GET_CODE (temp) == SUBREG
4411                 && REG_P (SUBREG_REG (temp)))
4412           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4413         {
4414           rtx temp1 = simplify_shift_const
4415             (NULL_RTX, ASHIFTRT, mode,
4416              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4417                                    GET_MODE_BITSIZE (mode) - 1 - i),
4418              GET_MODE_BITSIZE (mode) - 1 - i);
4419
4420           /* If all we did was surround TEMP with the two shifts, we
4421              haven't improved anything, so don't use it.  Otherwise,
4422              we are better off with TEMP1.  */
4423           if (GET_CODE (temp1) != ASHIFTRT
4424               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4425               || XEXP (XEXP (temp1, 0), 0) != temp)
4426             return temp1;
4427         }
4428       break;
4429
4430     case TRUNCATE:
4431       /* We can't handle truncation to a partial integer mode here
4432          because we don't know the real bitsize of the partial
4433          integer mode.  */
4434       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4435         break;
4436
4437       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4438           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4439                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4440         SUBST (XEXP (x, 0),
4441                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4442                               GET_MODE_MASK (mode), 0));
4443
4444       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4445          whose value is a comparison can be replaced with a subreg if
4446          STORE_FLAG_VALUE permits.  */
4447       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4448           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4449           && (temp = get_last_value (XEXP (x, 0)))
4450           && COMPARISON_P (temp))
4451         return gen_lowpart (mode, XEXP (x, 0));
4452       break;
4453
4454 #ifdef HAVE_cc0
4455     case COMPARE:
4456       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4457          using cc0, in which case we want to leave it as a COMPARE
4458          so we can distinguish it from a register-register-copy.  */
4459       if (XEXP (x, 1) == const0_rtx)
4460         return XEXP (x, 0);
4461
4462       /* x - 0 is the same as x unless x's mode has signed zeros and
4463          allows rounding towards -infinity.  Under those conditions,
4464          0 - 0 is -0.  */
4465       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4466             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4467           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4468         return XEXP (x, 0);
4469       break;
4470 #endif
4471
4472     case CONST:
4473       /* (const (const X)) can become (const X).  Do it this way rather than
4474          returning the inner CONST since CONST can be shared with a
4475          REG_EQUAL note.  */
4476       if (GET_CODE (XEXP (x, 0)) == CONST)
4477         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4478       break;
4479
4480 #ifdef HAVE_lo_sum
4481     case LO_SUM:
4482       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4483          can add in an offset.  find_split_point will split this address up
4484          again if it doesn't match.  */
4485       if (GET_CODE (XEXP (x, 0)) == HIGH
4486           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4487         return XEXP (x, 1);
4488       break;
4489 #endif
4490
4491     case PLUS:
4492       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4493          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4494          bit-field and can be replaced by either a sign_extend or a
4495          sign_extract.  The `and' may be a zero_extend and the two
4496          <c>, -<c> constants may be reversed.  */
4497       if (GET_CODE (XEXP (x, 0)) == XOR
4498           && GET_CODE (XEXP (x, 1)) == CONST_INT
4499           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4500           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4501           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4502               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4503           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4504           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4505                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4506                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4507                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4508               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4509                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4510                       == (unsigned int) i + 1))))
4511         return simplify_shift_const
4512           (NULL_RTX, ASHIFTRT, mode,
4513            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4514                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4515                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4516            GET_MODE_BITSIZE (mode) - (i + 1));
4517
4518       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4519          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4520          the bitsize of the mode - 1.  This allows simplification of
4521          "a = (b & 8) == 0;"  */
4522       if (XEXP (x, 1) == constm1_rtx
4523           && !REG_P (XEXP (x, 0))
4524           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4525                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4526           && nonzero_bits (XEXP (x, 0), mode) == 1)
4527         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4528            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4529                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4530                                  GET_MODE_BITSIZE (mode) - 1),
4531            GET_MODE_BITSIZE (mode) - 1);
4532
4533       /* If we are adding two things that have no bits in common, convert
4534          the addition into an IOR.  This will often be further simplified,
4535          for example in cases like ((a & 1) + (a & 2)), which can
4536          become a & 3.  */
4537
4538       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4539           && (nonzero_bits (XEXP (x, 0), mode)
4540               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4541         {
4542           /* Try to simplify the expression further.  */
4543           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4544           temp = combine_simplify_rtx (tor, mode, in_dest);
4545
4546           /* If we could, great.  If not, do not go ahead with the IOR
4547              replacement, since PLUS appears in many special purpose
4548              address arithmetic instructions.  */
4549           if (GET_CODE (temp) != CLOBBER && temp != tor)
4550             return temp;
4551         }
4552       break;
4553
4554     case MINUS:
4555       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4556          (and <foo> (const_int pow2-1))  */
4557       if (GET_CODE (XEXP (x, 1)) == AND
4558           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4559           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4560           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4561         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4562                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4563       break;
4564
4565     case MULT:
4566       /* If we have (mult (plus A B) C), apply the distributive law and then
4567          the inverse distributive law to see if things simplify.  This
4568          occurs mostly in addresses, often when unrolling loops.  */
4569
4570       if (GET_CODE (XEXP (x, 0)) == PLUS)
4571         {
4572           rtx result = distribute_and_simplify_rtx (x, 0);
4573           if (result)
4574             return result;
4575         }
4576
4577       /* Try simplify a*(b/c) as (a*b)/c.  */
4578       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4579           && GET_CODE (XEXP (x, 0)) == DIV)
4580         {
4581           rtx tem = simplify_binary_operation (MULT, mode,
4582                                                XEXP (XEXP (x, 0), 0),
4583                                                XEXP (x, 1));
4584           if (tem)
4585             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4586         }
4587       break;
4588
4589     case UDIV:
4590       /* If this is a divide by a power of two, treat it as a shift if
4591          its first operand is a shift.  */
4592       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4593           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4594           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4595               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4596               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4597               || GET_CODE (XEXP (x, 0)) == ROTATE
4598               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4599         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4600       break;
4601
4602     case EQ:  case NE:
4603     case GT:  case GTU:  case GE:  case GEU:
4604     case LT:  case LTU:  case LE:  case LEU:
4605     case UNEQ:  case LTGT:
4606     case UNGT:  case UNGE:
4607     case UNLT:  case UNLE:
4608     case UNORDERED: case ORDERED:
4609       /* If the first operand is a condition code, we can't do anything
4610          with it.  */
4611       if (GET_CODE (XEXP (x, 0)) == COMPARE
4612           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4613               && ! CC0_P (XEXP (x, 0))))
4614         {
4615           rtx op0 = XEXP (x, 0);
4616           rtx op1 = XEXP (x, 1);
4617           enum rtx_code new_code;
4618
4619           if (GET_CODE (op0) == COMPARE)
4620             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4621
4622           /* Simplify our comparison, if possible.  */
4623           new_code = simplify_comparison (code, &op0, &op1);
4624
4625           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4626              if only the low-order bit is possibly nonzero in X (such as when
4627              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4628              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4629              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4630              (plus X 1).
4631
4632              Remove any ZERO_EXTRACT we made when thinking this was a
4633              comparison.  It may now be simpler to use, e.g., an AND.  If a
4634              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4635              the call to make_compound_operation in the SET case.  */
4636
4637           if (STORE_FLAG_VALUE == 1
4638               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4639               && op1 == const0_rtx
4640               && mode == GET_MODE (op0)
4641               && nonzero_bits (op0, mode) == 1)
4642             return gen_lowpart (mode,
4643                                 expand_compound_operation (op0));
4644
4645           else if (STORE_FLAG_VALUE == 1
4646                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4647                    && op1 == const0_rtx
4648                    && mode == GET_MODE (op0)
4649                    && (num_sign_bit_copies (op0, mode)
4650                        == GET_MODE_BITSIZE (mode)))
4651             {
4652               op0 = expand_compound_operation (op0);
4653               return simplify_gen_unary (NEG, mode,
4654                                          gen_lowpart (mode, op0),
4655                                          mode);
4656             }
4657
4658           else if (STORE_FLAG_VALUE == 1
4659                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4660                    && op1 == const0_rtx
4661                    && mode == GET_MODE (op0)
4662                    && nonzero_bits (op0, mode) == 1)
4663             {
4664               op0 = expand_compound_operation (op0);
4665               return simplify_gen_binary (XOR, mode,
4666                                           gen_lowpart (mode, op0),
4667                                           const1_rtx);
4668             }
4669
4670           else if (STORE_FLAG_VALUE == 1
4671                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4672                    && op1 == const0_rtx
4673                    && mode == GET_MODE (op0)
4674                    && (num_sign_bit_copies (op0, mode)
4675                        == GET_MODE_BITSIZE (mode)))
4676             {
4677               op0 = expand_compound_operation (op0);
4678               return plus_constant (gen_lowpart (mode, op0), 1);
4679             }
4680
4681           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4682              those above.  */
4683           if (STORE_FLAG_VALUE == -1
4684               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4685               && op1 == const0_rtx
4686               && (num_sign_bit_copies (op0, mode)
4687                   == GET_MODE_BITSIZE (mode)))
4688             return gen_lowpart (mode,
4689                                 expand_compound_operation (op0));
4690
4691           else if (STORE_FLAG_VALUE == -1
4692                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4693                    && op1 == const0_rtx
4694                    && mode == GET_MODE (op0)
4695                    && nonzero_bits (op0, mode) == 1)
4696             {
4697               op0 = expand_compound_operation (op0);
4698               return simplify_gen_unary (NEG, mode,
4699                                          gen_lowpart (mode, op0),
4700                                          mode);
4701             }
4702
4703           else if (STORE_FLAG_VALUE == -1
4704                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4705                    && op1 == const0_rtx
4706                    && mode == GET_MODE (op0)
4707                    && (num_sign_bit_copies (op0, mode)
4708                        == GET_MODE_BITSIZE (mode)))
4709             {
4710               op0 = expand_compound_operation (op0);
4711               return simplify_gen_unary (NOT, mode,
4712                                          gen_lowpart (mode, op0),
4713                                          mode);
4714             }
4715
4716           /* If X is 0/1, (eq X 0) is X-1.  */
4717           else if (STORE_FLAG_VALUE == -1
4718                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4719                    && op1 == const0_rtx
4720                    && mode == GET_MODE (op0)
4721                    && nonzero_bits (op0, mode) == 1)
4722             {
4723               op0 = expand_compound_operation (op0);
4724               return plus_constant (gen_lowpart (mode, op0), -1);
4725             }
4726
4727           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4728              one bit that might be nonzero, we can convert (ne x 0) to
4729              (ashift x c) where C puts the bit in the sign bit.  Remove any
4730              AND with STORE_FLAG_VALUE when we are done, since we are only
4731              going to test the sign bit.  */
4732           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4733               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4734               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4735                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4736               && op1 == const0_rtx
4737               && mode == GET_MODE (op0)
4738               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4739             {
4740               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4741                                         expand_compound_operation (op0),
4742                                         GET_MODE_BITSIZE (mode) - 1 - i);
4743               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4744                 return XEXP (x, 0);
4745               else
4746                 return x;
4747             }
4748
4749           /* If the code changed, return a whole new comparison.  */
4750           if (new_code != code)
4751             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4752
4753           /* Otherwise, keep this operation, but maybe change its operands.
4754              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4755           SUBST (XEXP (x, 0), op0);
4756           SUBST (XEXP (x, 1), op1);
4757         }
4758       break;
4759
4760     case IF_THEN_ELSE:
4761       return simplify_if_then_else (x);
4762
4763     case ZERO_EXTRACT:
4764     case SIGN_EXTRACT:
4765     case ZERO_EXTEND:
4766     case SIGN_EXTEND:
4767       /* If we are processing SET_DEST, we are done.  */
4768       if (in_dest)
4769         return x;
4770
4771       return expand_compound_operation (x);
4772
4773     case SET:
4774       return simplify_set (x);
4775
4776     case AND:
4777     case IOR:
4778       return simplify_logical (x);
4779
4780     case ASHIFT:
4781     case LSHIFTRT:
4782     case ASHIFTRT:
4783     case ROTATE:
4784     case ROTATERT:
4785       /* If this is a shift by a constant amount, simplify it.  */
4786       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4787         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4788                                      INTVAL (XEXP (x, 1)));
4789
4790       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4791         SUBST (XEXP (x, 1),
4792                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4793                               ((HOST_WIDE_INT) 1
4794                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4795                               - 1,
4796                               0));
4797       break;
4798
4799     default:
4800       break;
4801     }
4802
4803   return x;
4804 }
4805 \f
4806 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4807
4808 static rtx
4809 simplify_if_then_else (rtx x)
4810 {
4811   enum machine_mode mode = GET_MODE (x);
4812   rtx cond = XEXP (x, 0);
4813   rtx true_rtx = XEXP (x, 1);
4814   rtx false_rtx = XEXP (x, 2);
4815   enum rtx_code true_code = GET_CODE (cond);
4816   int comparison_p = COMPARISON_P (cond);
4817   rtx temp;
4818   int i;
4819   enum rtx_code false_code;
4820   rtx reversed;
4821
4822   /* Simplify storing of the truth value.  */
4823   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4824     return simplify_gen_relational (true_code, mode, VOIDmode,
4825                                     XEXP (cond, 0), XEXP (cond, 1));
4826
4827   /* Also when the truth value has to be reversed.  */
4828   if (comparison_p
4829       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4830       && (reversed = reversed_comparison (cond, mode)))
4831     return reversed;
4832
4833   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4834      in it is being compared against certain values.  Get the true and false
4835      comparisons and see if that says anything about the value of each arm.  */
4836
4837   if (comparison_p
4838       && ((false_code = reversed_comparison_code (cond, NULL))
4839           != UNKNOWN)
4840       && REG_P (XEXP (cond, 0)))
4841     {
4842       HOST_WIDE_INT nzb;
4843       rtx from = XEXP (cond, 0);
4844       rtx true_val = XEXP (cond, 1);
4845       rtx false_val = true_val;
4846       int swapped = 0;
4847
4848       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4849
4850       if (false_code == EQ)
4851         {
4852           swapped = 1, true_code = EQ, false_code = NE;
4853           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4854         }
4855
4856       /* If we are comparing against zero and the expression being tested has
4857          only a single bit that might be nonzero, that is its value when it is
4858          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4859
4860       if (true_code == EQ && true_val == const0_rtx
4861           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4862         false_code = EQ, false_val = GEN_INT (nzb);
4863       else if (true_code == EQ && true_val == const0_rtx
4864                && (num_sign_bit_copies (from, GET_MODE (from))
4865                    == GET_MODE_BITSIZE (GET_MODE (from))))
4866         false_code = EQ, false_val = constm1_rtx;
4867
4868       /* Now simplify an arm if we know the value of the register in the
4869          branch and it is used in the arm.  Be careful due to the potential
4870          of locally-shared RTL.  */
4871
4872       if (reg_mentioned_p (from, true_rtx))
4873         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4874                                       from, true_val),
4875                       pc_rtx, pc_rtx, 0, 0);
4876       if (reg_mentioned_p (from, false_rtx))
4877         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4878                                    from, false_val),
4879                        pc_rtx, pc_rtx, 0, 0);
4880
4881       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4882       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4883
4884       true_rtx = XEXP (x, 1);
4885       false_rtx = XEXP (x, 2);
4886       true_code = GET_CODE (cond);
4887     }
4888
4889   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4890      reversed, do so to avoid needing two sets of patterns for
4891      subtract-and-branch insns.  Similarly if we have a constant in the true
4892      arm, the false arm is the same as the first operand of the comparison, or
4893      the false arm is more complicated than the true arm.  */
4894
4895   if (comparison_p
4896       && reversed_comparison_code (cond, NULL) != UNKNOWN
4897       && (true_rtx == pc_rtx
4898           || (CONSTANT_P (true_rtx)
4899               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4900           || true_rtx == const0_rtx
4901           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4902           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4903               && !OBJECT_P (false_rtx))
4904           || reg_mentioned_p (true_rtx, false_rtx)
4905           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4906     {
4907       true_code = reversed_comparison_code (cond, NULL);
4908       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4909       SUBST (XEXP (x, 1), false_rtx);
4910       SUBST (XEXP (x, 2), true_rtx);
4911
4912       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4913       cond = XEXP (x, 0);
4914
4915       /* It is possible that the conditional has been simplified out.  */
4916       true_code = GET_CODE (cond);
4917       comparison_p = COMPARISON_P (cond);
4918     }
4919
4920   /* If the two arms are identical, we don't need the comparison.  */
4921
4922   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4923     return true_rtx;
4924
4925   /* Convert a == b ? b : a to "a".  */
4926   if (true_code == EQ && ! side_effects_p (cond)
4927       && !HONOR_NANS (mode)
4928       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4929       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4930     return false_rtx;
4931   else if (true_code == NE && ! side_effects_p (cond)
4932            && !HONOR_NANS (mode)
4933            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4934            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4935     return true_rtx;
4936
4937   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4938
4939   if (GET_MODE_CLASS (mode) == MODE_INT
4940       && GET_CODE (false_rtx) == NEG
4941       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4942       && comparison_p
4943       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4944       && ! side_effects_p (true_rtx))
4945     switch (true_code)
4946       {
4947       case GT:
4948       case GE:
4949         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4950       case LT:
4951       case LE:
4952         return
4953           simplify_gen_unary (NEG, mode,
4954                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4955                               mode);
4956       default:
4957         break;
4958       }
4959
4960   /* Look for MIN or MAX.  */
4961
4962   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4963       && comparison_p
4964       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4965       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4966       && ! side_effects_p (cond))
4967     switch (true_code)
4968       {
4969       case GE:
4970       case GT:
4971         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4972       case LE:
4973       case LT:
4974         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4975       case GEU:
4976       case GTU:
4977         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4978       case LEU:
4979       case LTU:
4980         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4981       default:
4982         break;
4983       }
4984
4985   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4986      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4987      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4988      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4989      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4990      neither 1 or -1, but it isn't worth checking for.  */
4991
4992   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4993       && comparison_p
4994       && GET_MODE_CLASS (mode) == MODE_INT
4995       && ! side_effects_p (x))
4996     {
4997       rtx t = make_compound_operation (true_rtx, SET);
4998       rtx f = make_compound_operation (false_rtx, SET);
4999       rtx cond_op0 = XEXP (cond, 0);
5000       rtx cond_op1 = XEXP (cond, 1);
5001       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5002       enum machine_mode m = mode;
5003       rtx z = 0, c1 = NULL_RTX;
5004
5005       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5006            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5007            || GET_CODE (t) == ASHIFT
5008            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5009           && rtx_equal_p (XEXP (t, 0), f))
5010         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5011
5012       /* If an identity-zero op is commutative, check whether there
5013          would be a match if we swapped the operands.  */
5014       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5015                 || GET_CODE (t) == XOR)
5016                && rtx_equal_p (XEXP (t, 1), f))
5017         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5018       else if (GET_CODE (t) == SIGN_EXTEND
5019                && (GET_CODE (XEXP (t, 0)) == PLUS
5020                    || GET_CODE (XEXP (t, 0)) == MINUS
5021                    || GET_CODE (XEXP (t, 0)) == IOR
5022                    || GET_CODE (XEXP (t, 0)) == XOR
5023                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5024                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5025                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5026                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5027                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5028                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5029                && (num_sign_bit_copies (f, GET_MODE (f))
5030                    > (unsigned int)
5031                      (GET_MODE_BITSIZE (mode)
5032                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5033         {
5034           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5035           extend_op = SIGN_EXTEND;
5036           m = GET_MODE (XEXP (t, 0));
5037         }
5038       else if (GET_CODE (t) == SIGN_EXTEND
5039                && (GET_CODE (XEXP (t, 0)) == PLUS
5040                    || GET_CODE (XEXP (t, 0)) == IOR
5041                    || GET_CODE (XEXP (t, 0)) == XOR)
5042                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5043                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5044                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5045                && (num_sign_bit_copies (f, GET_MODE (f))
5046                    > (unsigned int)
5047                      (GET_MODE_BITSIZE (mode)
5048                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5049         {
5050           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5051           extend_op = SIGN_EXTEND;
5052           m = GET_MODE (XEXP (t, 0));
5053         }
5054       else if (GET_CODE (t) == ZERO_EXTEND
5055                && (GET_CODE (XEXP (t, 0)) == PLUS
5056                    || GET_CODE (XEXP (t, 0)) == MINUS
5057                    || GET_CODE (XEXP (t, 0)) == IOR
5058                    || GET_CODE (XEXP (t, 0)) == XOR
5059                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5060                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5061                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5062                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5063                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5064                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5065                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5066                && ((nonzero_bits (f, GET_MODE (f))
5067                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5068                    == 0))
5069         {
5070           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5071           extend_op = ZERO_EXTEND;
5072           m = GET_MODE (XEXP (t, 0));
5073         }
5074       else if (GET_CODE (t) == ZERO_EXTEND
5075                && (GET_CODE (XEXP (t, 0)) == PLUS
5076                    || GET_CODE (XEXP (t, 0)) == IOR
5077                    || GET_CODE (XEXP (t, 0)) == XOR)
5078                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5079                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5080                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5081                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5082                && ((nonzero_bits (f, GET_MODE (f))
5083                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5084                    == 0))
5085         {
5086           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5087           extend_op = ZERO_EXTEND;
5088           m = GET_MODE (XEXP (t, 0));
5089         }
5090
5091       if (z)
5092         {
5093           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5094                                                  cond_op0, cond_op1),
5095                         pc_rtx, pc_rtx, 0, 0);
5096           temp = simplify_gen_binary (MULT, m, temp,
5097                                       simplify_gen_binary (MULT, m, c1,
5098                                                            const_true_rtx));
5099           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5100           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5101
5102           if (extend_op != UNKNOWN)
5103             temp = simplify_gen_unary (extend_op, mode, temp, m);
5104
5105           return temp;
5106         }
5107     }
5108
5109   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5110      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5111      negation of a single bit, we can convert this operation to a shift.  We
5112      can actually do this more generally, but it doesn't seem worth it.  */
5113
5114   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5115       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5116       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5117            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5118           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5119                == GET_MODE_BITSIZE (mode))
5120               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5121     return
5122       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5123                             gen_lowpart (mode, XEXP (cond, 0)), i);
5124
5125   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5126   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5127       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5128       && GET_MODE (XEXP (cond, 0)) == mode
5129       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5130           == nonzero_bits (XEXP (cond, 0), mode)
5131       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5132     return XEXP (cond, 0);
5133
5134   return x;
5135 }
5136 \f
5137 /* Simplify X, a SET expression.  Return the new expression.  */
5138
5139 static rtx
5140 simplify_set (rtx x)
5141 {
5142   rtx src = SET_SRC (x);
5143   rtx dest = SET_DEST (x);
5144   enum machine_mode mode
5145     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5146   rtx other_insn;
5147   rtx *cc_use;
5148
5149   /* (set (pc) (return)) gets written as (return).  */
5150   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5151     return src;
5152
5153   /* Now that we know for sure which bits of SRC we are using, see if we can
5154      simplify the expression for the object knowing that we only need the
5155      low-order bits.  */
5156
5157   if (GET_MODE_CLASS (mode) == MODE_INT
5158       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5159     {
5160       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5161       SUBST (SET_SRC (x), src);
5162     }
5163
5164   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5165      the comparison result and try to simplify it unless we already have used
5166      undobuf.other_insn.  */
5167   if ((GET_MODE_CLASS (mode) == MODE_CC
5168        || GET_CODE (src) == COMPARE
5169        || CC0_P (dest))
5170       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5171       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5172       && COMPARISON_P (*cc_use)
5173       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5174     {
5175       enum rtx_code old_code = GET_CODE (*cc_use);
5176       enum rtx_code new_code;
5177       rtx op0, op1, tmp;
5178       int other_changed = 0;
5179       enum machine_mode compare_mode = GET_MODE (dest);
5180
5181       if (GET_CODE (src) == COMPARE)
5182         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5183       else
5184         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5185
5186       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5187                                            op0, op1);
5188       if (!tmp)
5189         new_code = old_code;
5190       else if (!CONSTANT_P (tmp))
5191         {
5192           new_code = GET_CODE (tmp);
5193           op0 = XEXP (tmp, 0);
5194           op1 = XEXP (tmp, 1);
5195         }
5196       else
5197         {
5198           rtx pat = PATTERN (other_insn);
5199           undobuf.other_insn = other_insn;
5200           SUBST (*cc_use, tmp);
5201
5202           /* Attempt to simplify CC user.  */
5203           if (GET_CODE (pat) == SET)
5204             {
5205               rtx new = simplify_rtx (SET_SRC (pat));
5206               if (new != NULL_RTX)
5207                 SUBST (SET_SRC (pat), new);
5208             }
5209
5210           /* Convert X into a no-op move.  */
5211           SUBST (SET_DEST (x), pc_rtx);
5212           SUBST (SET_SRC (x), pc_rtx);
5213           return x;
5214         }
5215
5216       /* Simplify our comparison, if possible.  */
5217       new_code = simplify_comparison (new_code, &op0, &op1);
5218
5219 #ifdef SELECT_CC_MODE
5220       /* If this machine has CC modes other than CCmode, check to see if we
5221          need to use a different CC mode here.  */
5222       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5223         compare_mode = GET_MODE (op0);
5224       else
5225         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5226
5227 #ifndef HAVE_cc0
5228       /* If the mode changed, we have to change SET_DEST, the mode in the
5229          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5230          a hard register, just build new versions with the proper mode.  If it
5231          is a pseudo, we lose unless it is only time we set the pseudo, in
5232          which case we can safely change its mode.  */
5233       if (compare_mode != GET_MODE (dest))
5234         {
5235           if (can_change_dest_mode (dest, 0, compare_mode))
5236             {
5237               unsigned int regno = REGNO (dest);
5238               rtx new_dest;
5239
5240               if (regno < FIRST_PSEUDO_REGISTER)
5241                 new_dest = gen_rtx_REG (compare_mode, regno);
5242               else
5243                 {
5244                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5245                   new_dest = regno_reg_rtx[regno];
5246                 }
5247
5248               SUBST (SET_DEST (x), new_dest);
5249               SUBST (XEXP (*cc_use, 0), new_dest);
5250               other_changed = 1;
5251
5252               dest = new_dest;
5253             }
5254         }
5255 #endif  /* cc0 */
5256 #endif  /* SELECT_CC_MODE */
5257
5258       /* If the code changed, we have to build a new comparison in
5259          undobuf.other_insn.  */
5260       if (new_code != old_code)
5261         {
5262           int other_changed_previously = other_changed;
5263           unsigned HOST_WIDE_INT mask;
5264
5265           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5266                                           dest, const0_rtx));
5267           other_changed = 1;
5268
5269           /* If the only change we made was to change an EQ into an NE or
5270              vice versa, OP0 has only one bit that might be nonzero, and OP1
5271              is zero, check if changing the user of the condition code will
5272              produce a valid insn.  If it won't, we can keep the original code
5273              in that insn by surrounding our operation with an XOR.  */
5274
5275           if (((old_code == NE && new_code == EQ)
5276                || (old_code == EQ && new_code == NE))
5277               && ! other_changed_previously && op1 == const0_rtx
5278               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5279               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5280             {
5281               rtx pat = PATTERN (other_insn), note = 0;
5282
5283               if ((recog_for_combine (&pat, other_insn, &note) < 0
5284                    && ! check_asm_operands (pat)))
5285                 {
5286                   PUT_CODE (*cc_use, old_code);
5287                   other_changed = 0;
5288
5289                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5290                                              op0, GEN_INT (mask));
5291                 }
5292             }
5293         }
5294
5295       if (other_changed)
5296         undobuf.other_insn = other_insn;
5297
5298 #ifdef HAVE_cc0
5299       /* If we are now comparing against zero, change our source if
5300          needed.  If we do not use cc0, we always have a COMPARE.  */
5301       if (op1 == const0_rtx && dest == cc0_rtx)
5302         {
5303           SUBST (SET_SRC (x), op0);
5304           src = op0;
5305         }
5306       else
5307 #endif
5308
5309       /* Otherwise, if we didn't previously have a COMPARE in the
5310          correct mode, we need one.  */
5311       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5312         {
5313           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5314           src = SET_SRC (x);
5315         }
5316       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5317         {
5318           SUBST(SET_SRC (x), op0);
5319           src = SET_SRC (x);
5320         }
5321       else
5322         {
5323           /* Otherwise, update the COMPARE if needed.  */
5324           SUBST (XEXP (src, 0), op0);
5325           SUBST (XEXP (src, 1), op1);
5326         }
5327     }
5328   else
5329     {
5330       /* Get SET_SRC in a form where we have placed back any
5331          compound expressions.  Then do the checks below.  */
5332       src = make_compound_operation (src, SET);
5333       SUBST (SET_SRC (x), src);
5334     }
5335
5336   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5337      and X being a REG or (subreg (reg)), we may be able to convert this to
5338      (set (subreg:m2 x) (op)).
5339
5340      We can always do this if M1 is narrower than M2 because that means that
5341      we only care about the low bits of the result.
5342
5343      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5344      perform a narrower operation than requested since the high-order bits will
5345      be undefined.  On machine where it is defined, this transformation is safe
5346      as long as M1 and M2 have the same number of words.  */
5347
5348   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5349       && !OBJECT_P (SUBREG_REG (src))
5350       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5351            / UNITS_PER_WORD)
5352           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5353                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5354 #ifndef WORD_REGISTER_OPERATIONS
5355       && (GET_MODE_SIZE (GET_MODE (src))
5356         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5357 #endif
5358 #ifdef CANNOT_CHANGE_MODE_CLASS
5359       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5360             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5361                                          GET_MODE (SUBREG_REG (src)),
5362                                          GET_MODE (src)))
5363 #endif
5364       && (REG_P (dest)
5365           || (GET_CODE (dest) == SUBREG
5366               && REG_P (SUBREG_REG (dest)))))
5367     {
5368       SUBST (SET_DEST (x),
5369              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5370                                       dest));
5371       SUBST (SET_SRC (x), SUBREG_REG (src));
5372
5373       src = SET_SRC (x), dest = SET_DEST (x);
5374     }
5375
5376 #ifdef HAVE_cc0
5377   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5378      in SRC.  */
5379   if (dest == cc0_rtx
5380       && GET_CODE (src) == SUBREG
5381       && subreg_lowpart_p (src)
5382       && (GET_MODE_BITSIZE (GET_MODE (src))
5383           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5384     {
5385       rtx inner = SUBREG_REG (src);
5386       enum machine_mode inner_mode = GET_MODE (inner);
5387
5388       /* Here we make sure that we don't have a sign bit on.  */
5389       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5390           && (nonzero_bits (inner, inner_mode)
5391               < ((unsigned HOST_WIDE_INT) 1
5392                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5393         {
5394           SUBST (SET_SRC (x), inner);
5395           src = SET_SRC (x);
5396         }
5397     }
5398 #endif
5399
5400 #ifdef LOAD_EXTEND_OP
5401   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5402      would require a paradoxical subreg.  Replace the subreg with a
5403      zero_extend to avoid the reload that would otherwise be required.  */
5404
5405   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5406       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5407       && SUBREG_BYTE (src) == 0
5408       && (GET_MODE_SIZE (GET_MODE (src))
5409           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5410       && MEM_P (SUBREG_REG (src)))
5411     {
5412       SUBST (SET_SRC (x),
5413              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5414                             GET_MODE (src), SUBREG_REG (src)));
5415
5416       src = SET_SRC (x);
5417     }
5418 #endif
5419
5420   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5421      are comparing an item known to be 0 or -1 against 0, use a logical
5422      operation instead. Check for one of the arms being an IOR of the other
5423      arm with some value.  We compute three terms to be IOR'ed together.  In
5424      practice, at most two will be nonzero.  Then we do the IOR's.  */
5425
5426   if (GET_CODE (dest) != PC
5427       && GET_CODE (src) == IF_THEN_ELSE
5428       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5429       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5430       && XEXP (XEXP (src, 0), 1) == const0_rtx
5431       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5432 #ifdef HAVE_conditional_move
5433       && ! can_conditionally_move_p (GET_MODE (src))
5434 #endif
5435       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5436                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5437           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5438       && ! side_effects_p (src))
5439     {
5440       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5441                       ? XEXP (src, 1) : XEXP (src, 2));
5442       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5443                    ? XEXP (src, 2) : XEXP (src, 1));
5444       rtx term1 = const0_rtx, term2, term3;
5445
5446       if (GET_CODE (true_rtx) == IOR
5447           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5448         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5449       else if (GET_CODE (true_rtx) == IOR
5450                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5451         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5452       else if (GET_CODE (false_rtx) == IOR
5453                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5454         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5455       else if (GET_CODE (false_rtx) == IOR
5456                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5457         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5458
5459       term2 = simplify_gen_binary (AND, GET_MODE (src),
5460                                    XEXP (XEXP (src, 0), 0), true_rtx);
5461       term3 = simplify_gen_binary (AND, GET_MODE (src),
5462                                    simplify_gen_unary (NOT, GET_MODE (src),
5463                                                        XEXP (XEXP (src, 0), 0),
5464                                                        GET_MODE (src)),
5465                                    false_rtx);
5466
5467       SUBST (SET_SRC (x),
5468              simplify_gen_binary (IOR, GET_MODE (src),
5469                                   simplify_gen_binary (IOR, GET_MODE (src),
5470                                                        term1, term2),
5471                                   term3));
5472
5473       src = SET_SRC (x);
5474     }
5475
5476   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5477      whole thing fail.  */
5478   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5479     return src;
5480   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5481     return dest;
5482   else
5483     /* Convert this into a field assignment operation, if possible.  */
5484     return make_field_assignment (x);
5485 }
5486 \f
5487 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5488    result.  */
5489
5490 static rtx
5491 simplify_logical (rtx x)
5492 {
5493   enum machine_mode mode = GET_MODE (x);
5494   rtx op0 = XEXP (x, 0);
5495   rtx op1 = XEXP (x, 1);
5496
5497   switch (GET_CODE (x))
5498     {
5499     case AND:
5500       /* We can call simplify_and_const_int only if we don't lose
5501          any (sign) bits when converting INTVAL (op1) to
5502          "unsigned HOST_WIDE_INT".  */
5503       if (GET_CODE (op1) == CONST_INT
5504           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5505               || INTVAL (op1) > 0))
5506         {
5507           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5508           if (GET_CODE (x) != AND)
5509             return x;
5510
5511           op0 = XEXP (x, 0);
5512           op1 = XEXP (x, 1);
5513         }
5514
5515       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5516          apply the distributive law and then the inverse distributive
5517          law to see if things simplify.  */
5518       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5519         {
5520           rtx result = distribute_and_simplify_rtx (x, 0);
5521           if (result)
5522             return result;
5523         }
5524       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5525         {
5526           rtx result = distribute_and_simplify_rtx (x, 1);
5527           if (result)
5528             return result;
5529         }
5530       break;
5531
5532     case IOR:
5533       /* If we have (ior (and A B) C), apply the distributive law and then
5534          the inverse distributive law to see if things simplify.  */
5535
5536       if (GET_CODE (op0) == AND)
5537         {
5538           rtx result = distribute_and_simplify_rtx (x, 0);
5539           if (result)
5540             return result;
5541         }
5542
5543       if (GET_CODE (op1) == AND)
5544         {
5545           rtx result = distribute_and_simplify_rtx (x, 1);
5546           if (result)
5547             return result;
5548         }
5549       break;
5550
5551     default:
5552       gcc_unreachable ();
5553     }
5554
5555   return x;
5556 }
5557 \f
5558 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5559    operations" because they can be replaced with two more basic operations.
5560    ZERO_EXTEND is also considered "compound" because it can be replaced with
5561    an AND operation, which is simpler, though only one operation.
5562
5563    The function expand_compound_operation is called with an rtx expression
5564    and will convert it to the appropriate shifts and AND operations,
5565    simplifying at each stage.
5566
5567    The function make_compound_operation is called to convert an expression
5568    consisting of shifts and ANDs into the equivalent compound expression.
5569    It is the inverse of this function, loosely speaking.  */
5570
5571 static rtx
5572 expand_compound_operation (rtx x)
5573 {
5574   unsigned HOST_WIDE_INT pos = 0, len;
5575   int unsignedp = 0;
5576   unsigned int modewidth;
5577   rtx tem;
5578
5579   switch (GET_CODE (x))
5580     {
5581     case ZERO_EXTEND:
5582       unsignedp = 1;
5583     case SIGN_EXTEND:
5584       /* We can't necessarily use a const_int for a multiword mode;
5585          it depends on implicitly extending the value.
5586          Since we don't know the right way to extend it,
5587          we can't tell whether the implicit way is right.
5588
5589          Even for a mode that is no wider than a const_int,
5590          we can't win, because we need to sign extend one of its bits through
5591          the rest of it, and we don't know which bit.  */
5592       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5593         return x;
5594
5595       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5596          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5597          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5598          reloaded. If not for that, MEM's would very rarely be safe.
5599
5600          Reject MODEs bigger than a word, because we might not be able
5601          to reference a two-register group starting with an arbitrary register
5602          (and currently gen_lowpart might crash for a SUBREG).  */
5603
5604       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5605         return x;
5606
5607       /* Reject MODEs that aren't scalar integers because turning vector
5608          or complex modes into shifts causes problems.  */
5609
5610       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5611         return x;
5612
5613       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5614       /* If the inner object has VOIDmode (the only way this can happen
5615          is if it is an ASM_OPERANDS), we can't do anything since we don't
5616          know how much masking to do.  */
5617       if (len == 0)
5618         return x;
5619
5620       break;
5621
5622     case ZERO_EXTRACT:
5623       unsignedp = 1;
5624
5625       /* ... fall through ...  */
5626
5627     case SIGN_EXTRACT:
5628       /* If the operand is a CLOBBER, just return it.  */
5629       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5630         return XEXP (x, 0);
5631
5632       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5633           || GET_CODE (XEXP (x, 2)) != CONST_INT
5634           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5635         return x;
5636
5637       /* Reject MODEs that aren't scalar integers because turning vector
5638          or complex modes into shifts causes problems.  */
5639
5640       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5641         return x;
5642
5643       len = INTVAL (XEXP (x, 1));
5644       pos = INTVAL (XEXP (x, 2));
5645
5646       /* This should stay within the object being extracted, fail otherwise.  */
5647       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5648         return x;
5649
5650       if (BITS_BIG_ENDIAN)
5651         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5652
5653       break;
5654
5655     default:
5656       return x;
5657     }
5658   /* Convert sign extension to zero extension, if we know that the high
5659      bit is not set, as this is easier to optimize.  It will be converted
5660      back to cheaper alternative in make_extraction.  */
5661   if (GET_CODE (x) == SIGN_EXTEND
5662       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5663           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5664                 & ~(((unsigned HOST_WIDE_INT)
5665                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5666                      >> 1))
5667                == 0)))
5668     {
5669       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5670       rtx temp2 = expand_compound_operation (temp);
5671
5672       /* Make sure this is a profitable operation.  */
5673       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5674        return temp2;
5675       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5676        return temp;
5677       else
5678        return x;
5679     }
5680
5681   /* We can optimize some special cases of ZERO_EXTEND.  */
5682   if (GET_CODE (x) == ZERO_EXTEND)
5683     {
5684       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5685          know that the last value didn't have any inappropriate bits
5686          set.  */
5687       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5688           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5689           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5690           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5691               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5692         return XEXP (XEXP (x, 0), 0);
5693
5694       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5695       if (GET_CODE (XEXP (x, 0)) == SUBREG
5696           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5697           && subreg_lowpart_p (XEXP (x, 0))
5698           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5699           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5700               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5701         return SUBREG_REG (XEXP (x, 0));
5702
5703       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5704          is a comparison and STORE_FLAG_VALUE permits.  This is like
5705          the first case, but it works even when GET_MODE (x) is larger
5706          than HOST_WIDE_INT.  */
5707       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5708           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5709           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5710           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5711               <= HOST_BITS_PER_WIDE_INT)
5712           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5713               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5714         return XEXP (XEXP (x, 0), 0);
5715
5716       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5717       if (GET_CODE (XEXP (x, 0)) == SUBREG
5718           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5719           && subreg_lowpart_p (XEXP (x, 0))
5720           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5721           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5722               <= HOST_BITS_PER_WIDE_INT)
5723           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5724               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5725         return SUBREG_REG (XEXP (x, 0));
5726
5727     }
5728
5729   /* If we reach here, we want to return a pair of shifts.  The inner
5730      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5731      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5732      logical depending on the value of UNSIGNEDP.
5733
5734      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5735      converted into an AND of a shift.
5736
5737      We must check for the case where the left shift would have a negative
5738      count.  This can happen in a case like (x >> 31) & 255 on machines
5739      that can't shift by a constant.  On those machines, we would first
5740      combine the shift with the AND to produce a variable-position
5741      extraction.  Then the constant of 31 would be substituted in to produce
5742      a such a position.  */
5743
5744   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5745   if (modewidth + len >= pos)
5746     {
5747       enum machine_mode mode = GET_MODE (x);
5748       tem = gen_lowpart (mode, XEXP (x, 0));
5749       if (!tem || GET_CODE (tem) == CLOBBER)
5750         return x;
5751       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5752                                   tem, modewidth - pos - len);
5753       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5754                                   mode, tem, modewidth - len);
5755     }
5756   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5757     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5758                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5759                                                         GET_MODE (x),
5760                                                         XEXP (x, 0), pos),
5761                                   ((HOST_WIDE_INT) 1 << len) - 1);
5762   else
5763     /* Any other cases we can't handle.  */
5764     return x;
5765
5766   /* If we couldn't do this for some reason, return the original
5767      expression.  */
5768   if (GET_CODE (tem) == CLOBBER)
5769     return x;
5770
5771   return tem;
5772 }
5773 \f
5774 /* X is a SET which contains an assignment of one object into
5775    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5776    or certain SUBREGS). If possible, convert it into a series of
5777    logical operations.
5778
5779    We half-heartedly support variable positions, but do not at all
5780    support variable lengths.  */
5781
5782 static rtx
5783 expand_field_assignment (rtx x)
5784 {
5785   rtx inner;
5786   rtx pos;                      /* Always counts from low bit.  */
5787   int len;
5788   rtx mask, cleared, masked;
5789   enum machine_mode compute_mode;
5790
5791   /* Loop until we find something we can't simplify.  */
5792   while (1)
5793     {
5794       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5795           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5796         {
5797           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5798           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5799           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5800         }
5801       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5802                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5803         {
5804           inner = XEXP (SET_DEST (x), 0);
5805           len = INTVAL (XEXP (SET_DEST (x), 1));
5806           pos = XEXP (SET_DEST (x), 2);
5807
5808           /* A constant position should stay within the width of INNER.  */
5809           if (GET_CODE (pos) == CONST_INT
5810               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5811             break;
5812
5813           if (BITS_BIG_ENDIAN)
5814             {
5815               if (GET_CODE (pos) == CONST_INT)
5816                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5817                                - INTVAL (pos));
5818               else if (GET_CODE (pos) == MINUS
5819                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5820                        && (INTVAL (XEXP (pos, 1))
5821                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5822                 /* If position is ADJUST - X, new position is X.  */
5823                 pos = XEXP (pos, 0);
5824               else
5825                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5826                                            GEN_INT (GET_MODE_BITSIZE (
5827                                                     GET_MODE (inner))
5828                                                     - len),
5829                                            pos);
5830             }
5831         }
5832
5833       /* A SUBREG between two modes that occupy the same numbers of words
5834          can be done by moving the SUBREG to the source.  */
5835       else if (GET_CODE (SET_DEST (x)) == SUBREG
5836                /* We need SUBREGs to compute nonzero_bits properly.  */
5837                && nonzero_sign_valid
5838                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5839                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5840                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5841                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5842         {
5843           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5844                            gen_lowpart
5845                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5846                             SET_SRC (x)));
5847           continue;
5848         }
5849       else
5850         break;
5851
5852       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5853         inner = SUBREG_REG (inner);
5854
5855       compute_mode = GET_MODE (inner);
5856
5857       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5858       if (! SCALAR_INT_MODE_P (compute_mode))
5859         {
5860           enum machine_mode imode;
5861
5862           /* Don't do anything for vector or complex integral types.  */
5863           if (! FLOAT_MODE_P (compute_mode))
5864             break;
5865
5866           /* Try to find an integral mode to pun with.  */
5867           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5868           if (imode == BLKmode)
5869             break;
5870
5871           compute_mode = imode;
5872           inner = gen_lowpart (imode, inner);
5873         }
5874
5875       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5876       if (len >= HOST_BITS_PER_WIDE_INT)
5877         break;
5878
5879       /* Now compute the equivalent expression.  Make a copy of INNER
5880          for the SET_DEST in case it is a MEM into which we will substitute;
5881          we don't want shared RTL in that case.  */
5882       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5883       cleared = simplify_gen_binary (AND, compute_mode,
5884                                      simplify_gen_unary (NOT, compute_mode,
5885                                        simplify_gen_binary (ASHIFT,
5886                                                             compute_mode,
5887                                                             mask, pos),
5888                                        compute_mode),
5889                                      inner);
5890       masked = simplify_gen_binary (ASHIFT, compute_mode,
5891                                     simplify_gen_binary (
5892                                       AND, compute_mode,
5893                                       gen_lowpart (compute_mode, SET_SRC (x)),
5894                                       mask),
5895                                     pos);
5896
5897       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5898                        simplify_gen_binary (IOR, compute_mode,
5899                                             cleared, masked));
5900     }
5901
5902   return x;
5903 }
5904 \f
5905 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5906    it is an RTX that represents a variable starting position; otherwise,
5907    POS is the (constant) starting bit position (counted from the LSB).
5908
5909    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5910    signed reference.
5911
5912    IN_DEST is nonzero if this is a reference in the destination of a
5913    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5914    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5915    be used.
5916
5917    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5918    ZERO_EXTRACT should be built even for bits starting at bit 0.
5919
5920    MODE is the desired mode of the result (if IN_DEST == 0).
5921
5922    The result is an RTX for the extraction or NULL_RTX if the target
5923    can't handle it.  */
5924
5925 static rtx
5926 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5927                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5928                  int in_dest, int in_compare)
5929 {
5930   /* This mode describes the size of the storage area
5931      to fetch the overall value from.  Within that, we
5932      ignore the POS lowest bits, etc.  */
5933   enum machine_mode is_mode = GET_MODE (inner);
5934   enum machine_mode inner_mode;
5935   enum machine_mode wanted_inner_mode;
5936   enum machine_mode wanted_inner_reg_mode = word_mode;
5937   enum machine_mode pos_mode = word_mode;
5938   enum machine_mode extraction_mode = word_mode;
5939   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5940   rtx new = 0;
5941   rtx orig_pos_rtx = pos_rtx;
5942   HOST_WIDE_INT orig_pos;
5943
5944   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5945     {
5946       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5947          consider just the QI as the memory to extract from.
5948          The subreg adds or removes high bits; its mode is
5949          irrelevant to the meaning of this extraction,
5950          since POS and LEN count from the lsb.  */
5951       if (MEM_P (SUBREG_REG (inner)))
5952         is_mode = GET_MODE (SUBREG_REG (inner));
5953       inner = SUBREG_REG (inner);
5954     }
5955   else if (GET_CODE (inner) == ASHIFT
5956            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5957            && pos_rtx == 0 && pos == 0
5958            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5959     {
5960       /* We're extracting the least significant bits of an rtx
5961          (ashift X (const_int C)), where LEN > C.  Extract the
5962          least significant (LEN - C) bits of X, giving an rtx
5963          whose mode is MODE, then shift it left C times.  */
5964       new = make_extraction (mode, XEXP (inner, 0),
5965                              0, 0, len - INTVAL (XEXP (inner, 1)),
5966                              unsignedp, in_dest, in_compare);
5967       if (new != 0)
5968         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5969     }
5970
5971   inner_mode = GET_MODE (inner);
5972
5973   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5974     pos = INTVAL (pos_rtx), pos_rtx = 0;
5975
5976   /* See if this can be done without an extraction.  We never can if the
5977      width of the field is not the same as that of some integer mode. For
5978      registers, we can only avoid the extraction if the position is at the
5979      low-order bit and this is either not in the destination or we have the
5980      appropriate STRICT_LOW_PART operation available.
5981
5982      For MEM, we can avoid an extract if the field starts on an appropriate
5983      boundary and we can change the mode of the memory reference.  */
5984
5985   if (tmode != BLKmode
5986       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5987            && !MEM_P (inner)
5988            && (inner_mode == tmode
5989                || !REG_P (inner)
5990                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5991                                          GET_MODE_BITSIZE (inner_mode))
5992                || reg_truncated_to_mode (tmode, inner))
5993            && (! in_dest
5994                || (REG_P (inner)
5995                    && have_insn_for (STRICT_LOW_PART, tmode))))
5996           || (MEM_P (inner) && pos_rtx == 0
5997               && (pos
5998                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5999                      : BITS_PER_UNIT)) == 0
6000               /* We can't do this if we are widening INNER_MODE (it
6001                  may not be aligned, for one thing).  */
6002               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6003               && (inner_mode == tmode
6004                   || (! mode_dependent_address_p (XEXP (inner, 0))
6005                       && ! MEM_VOLATILE_P (inner))))))
6006     {
6007       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6008          field.  If the original and current mode are the same, we need not
6009          adjust the offset.  Otherwise, we do if bytes big endian.
6010
6011          If INNER is not a MEM, get a piece consisting of just the field
6012          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6013
6014       if (MEM_P (inner))
6015         {
6016           HOST_WIDE_INT offset;
6017
6018           /* POS counts from lsb, but make OFFSET count in memory order.  */
6019           if (BYTES_BIG_ENDIAN)
6020             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6021           else
6022             offset = pos / BITS_PER_UNIT;
6023
6024           new = adjust_address_nv (inner, tmode, offset);
6025         }
6026       else if (REG_P (inner))
6027         {
6028           if (tmode != inner_mode)
6029             {
6030               /* We can't call gen_lowpart in a DEST since we
6031                  always want a SUBREG (see below) and it would sometimes
6032                  return a new hard register.  */
6033               if (pos || in_dest)
6034                 {
6035                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6036
6037                   if (WORDS_BIG_ENDIAN
6038                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6039                     final_word = ((GET_MODE_SIZE (inner_mode)
6040                                    - GET_MODE_SIZE (tmode))
6041                                   / UNITS_PER_WORD) - final_word;
6042
6043                   final_word *= UNITS_PER_WORD;
6044                   if (BYTES_BIG_ENDIAN &&
6045                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6046                     final_word += (GET_MODE_SIZE (inner_mode)
6047                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6048
6049                   /* Avoid creating invalid subregs, for example when
6050                      simplifying (x>>32)&255.  */
6051                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6052                     return NULL_RTX;
6053
6054                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6055                 }
6056               else
6057                 new = gen_lowpart (tmode, inner);
6058             }
6059           else
6060             new = inner;
6061         }
6062       else
6063         new = force_to_mode (inner, tmode,
6064                              len >= HOST_BITS_PER_WIDE_INT
6065                              ? ~(unsigned HOST_WIDE_INT) 0
6066                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6067                              0);
6068
6069       /* If this extraction is going into the destination of a SET,
6070          make a STRICT_LOW_PART unless we made a MEM.  */
6071
6072       if (in_dest)
6073         return (MEM_P (new) ? new
6074                 : (GET_CODE (new) != SUBREG
6075                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6076                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6077
6078       if (mode == tmode)
6079         return new;
6080
6081       if (GET_CODE (new) == CONST_INT)
6082         return gen_int_mode (INTVAL (new), mode);
6083
6084       /* If we know that no extraneous bits are set, and that the high
6085          bit is not set, convert the extraction to the cheaper of
6086          sign and zero extension, that are equivalent in these cases.  */
6087       if (flag_expensive_optimizations
6088           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6089               && ((nonzero_bits (new, tmode)
6090                    & ~(((unsigned HOST_WIDE_INT)
6091                         GET_MODE_MASK (tmode))
6092                        >> 1))
6093                   == 0)))
6094         {
6095           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6096           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6097
6098           /* Prefer ZERO_EXTENSION, since it gives more information to
6099              backends.  */
6100           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6101             return temp;
6102           return temp1;
6103         }
6104
6105       /* Otherwise, sign- or zero-extend unless we already are in the
6106          proper mode.  */
6107
6108       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6109                              mode, new));
6110     }
6111
6112   /* Unless this is a COMPARE or we have a funny memory reference,
6113      don't do anything with zero-extending field extracts starting at
6114      the low-order bit since they are simple AND operations.  */
6115   if (pos_rtx == 0 && pos == 0 && ! in_dest
6116       && ! in_compare && unsignedp)
6117     return 0;
6118
6119   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6120      if the position is not a constant and the length is not 1.  In all
6121      other cases, we would only be going outside our object in cases when
6122      an original shift would have been undefined.  */
6123   if (MEM_P (inner)
6124       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6125           || (pos_rtx != 0 && len != 1)))
6126     return 0;
6127
6128   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6129      and the mode for the result.  */
6130   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6131     {
6132       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6133       pos_mode = mode_for_extraction (EP_insv, 2);
6134       extraction_mode = mode_for_extraction (EP_insv, 3);
6135     }
6136
6137   if (! in_dest && unsignedp
6138       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6139     {
6140       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6141       pos_mode = mode_for_extraction (EP_extzv, 3);
6142       extraction_mode = mode_for_extraction (EP_extzv, 0);
6143     }
6144
6145   if (! in_dest && ! unsignedp
6146       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6147     {
6148       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6149       pos_mode = mode_for_extraction (EP_extv, 3);
6150       extraction_mode = mode_for_extraction (EP_extv, 0);
6151     }
6152
6153   /* Never narrow an object, since that might not be safe.  */
6154
6155   if (mode != VOIDmode
6156       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6157     extraction_mode = mode;
6158
6159   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6160       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6161     pos_mode = GET_MODE (pos_rtx);
6162
6163   /* If this is not from memory, the desired mode is the preferred mode
6164      for an extraction pattern's first input operand, or word_mode if there
6165      is none.  */
6166   if (!MEM_P (inner))
6167     wanted_inner_mode = wanted_inner_reg_mode;
6168   else
6169     {
6170       /* Be careful not to go beyond the extracted object and maintain the
6171          natural alignment of the memory.  */
6172       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6173       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6174              > GET_MODE_BITSIZE (wanted_inner_mode))
6175         {
6176           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6177           gcc_assert (wanted_inner_mode != VOIDmode);
6178         }
6179
6180       /* If we have to change the mode of memory and cannot, the desired mode
6181          is EXTRACTION_MODE.  */
6182       if (inner_mode != wanted_inner_mode
6183           && (mode_dependent_address_p (XEXP (inner, 0))
6184               || MEM_VOLATILE_P (inner)
6185               || pos_rtx))
6186         wanted_inner_mode = extraction_mode;
6187     }
6188
6189   orig_pos = pos;
6190
6191   if (BITS_BIG_ENDIAN)
6192     {
6193       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6194          BITS_BIG_ENDIAN style.  If position is constant, compute new
6195          position.  Otherwise, build subtraction.
6196          Note that POS is relative to the mode of the original argument.
6197          If it's a MEM we need to recompute POS relative to that.
6198          However, if we're extracting from (or inserting into) a register,
6199          we want to recompute POS relative to wanted_inner_mode.  */
6200       int width = (MEM_P (inner)
6201                    ? GET_MODE_BITSIZE (is_mode)
6202                    : GET_MODE_BITSIZE (wanted_inner_mode));
6203
6204       if (pos_rtx == 0)
6205         pos = width - len - pos;
6206       else
6207         pos_rtx
6208           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6209       /* POS may be less than 0 now, but we check for that below.
6210          Note that it can only be less than 0 if !MEM_P (inner).  */
6211     }
6212
6213   /* If INNER has a wider mode, and this is a constant extraction, try to
6214      make it smaller and adjust the byte to point to the byte containing
6215      the value.  */
6216   if (wanted_inner_mode != VOIDmode
6217       && inner_mode != wanted_inner_mode
6218       && ! pos_rtx
6219       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6220       && MEM_P (inner)
6221       && ! mode_dependent_address_p (XEXP (inner, 0))
6222       && ! MEM_VOLATILE_P (inner))
6223     {
6224       int offset = 0;
6225
6226       /* The computations below will be correct if the machine is big
6227          endian in both bits and bytes or little endian in bits and bytes.
6228          If it is mixed, we must adjust.  */
6229
6230       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6231          adjust OFFSET to compensate.  */
6232       if (BYTES_BIG_ENDIAN
6233           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6234         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6235
6236       /* We can now move to the desired byte.  */
6237       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6238                 * GET_MODE_SIZE (wanted_inner_mode);
6239       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6240
6241       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6242           && is_mode != wanted_inner_mode)
6243         offset = (GET_MODE_SIZE (is_mode)
6244                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6245
6246       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6247     }
6248
6249   /* If INNER is not memory, we can always get it into the proper mode.  If we
6250      are changing its mode, POS must be a constant and smaller than the size
6251      of the new mode.  */
6252   else if (!MEM_P (inner))
6253     {
6254       if (GET_MODE (inner) != wanted_inner_mode
6255           && (pos_rtx != 0
6256               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6257         return 0;
6258
6259       if (orig_pos < 0)
6260         return 0;
6261
6262       inner = force_to_mode (inner, wanted_inner_mode,
6263                              pos_rtx
6264                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6265                              ? ~(unsigned HOST_WIDE_INT) 0
6266                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6267                                 << orig_pos),
6268                              0);
6269     }
6270
6271   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6272      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6273   if (pos_rtx != 0
6274       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6275     {
6276       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6277
6278       /* If we know that no extraneous bits are set, and that the high
6279          bit is not set, convert extraction to cheaper one - either
6280          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6281          cases.  */
6282       if (flag_expensive_optimizations
6283           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6284               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6285                    & ~(((unsigned HOST_WIDE_INT)
6286                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6287                        >> 1))
6288                   == 0)))
6289         {
6290           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6291
6292           /* Prefer ZERO_EXTENSION, since it gives more information to
6293              backends.  */
6294           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6295             temp = temp1;
6296         }
6297       pos_rtx = temp;
6298     }
6299   else if (pos_rtx != 0
6300            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6301     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6302
6303   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6304      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6305      be a CONST_INT.  */
6306   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6307     pos_rtx = orig_pos_rtx;
6308
6309   else if (pos_rtx == 0)
6310     pos_rtx = GEN_INT (pos);
6311
6312   /* Make the required operation.  See if we can use existing rtx.  */
6313   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6314                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6315   if (! in_dest)
6316     new = gen_lowpart (mode, new);
6317
6318   return new;
6319 }
6320 \f
6321 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6322    with any other operations in X.  Return X without that shift if so.  */
6323
6324 static rtx
6325 extract_left_shift (rtx x, int count)
6326 {
6327   enum rtx_code code = GET_CODE (x);
6328   enum machine_mode mode = GET_MODE (x);
6329   rtx tem;
6330
6331   switch (code)
6332     {
6333     case ASHIFT:
6334       /* This is the shift itself.  If it is wide enough, we will return
6335          either the value being shifted if the shift count is equal to
6336          COUNT or a shift for the difference.  */
6337       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6338           && INTVAL (XEXP (x, 1)) >= count)
6339         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6340                                      INTVAL (XEXP (x, 1)) - count);
6341       break;
6342
6343     case NEG:  case NOT:
6344       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6345         return simplify_gen_unary (code, mode, tem, mode);
6346
6347       break;
6348
6349     case PLUS:  case IOR:  case XOR:  case AND:
6350       /* If we can safely shift this constant and we find the inner shift,
6351          make a new operation.  */
6352       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6353           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6354           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6355         return simplify_gen_binary (code, mode, tem,
6356                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6357
6358       break;
6359
6360     default:
6361       break;
6362     }
6363
6364   return 0;
6365 }
6366 \f
6367 /* Look at the expression rooted at X.  Look for expressions
6368    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6369    Form these expressions.
6370
6371    Return the new rtx, usually just X.
6372
6373    Also, for machines like the VAX that don't have logical shift insns,
6374    try to convert logical to arithmetic shift operations in cases where
6375    they are equivalent.  This undoes the canonicalizations to logical
6376    shifts done elsewhere.
6377
6378    We try, as much as possible, to re-use rtl expressions to save memory.
6379
6380    IN_CODE says what kind of expression we are processing.  Normally, it is
6381    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6382    being kludges), it is MEM.  When processing the arguments of a comparison
6383    or a COMPARE against zero, it is COMPARE.  */
6384
6385 static rtx
6386 make_compound_operation (rtx x, enum rtx_code in_code)
6387 {
6388   enum rtx_code code = GET_CODE (x);
6389   enum machine_mode mode = GET_MODE (x);
6390   int mode_width = GET_MODE_BITSIZE (mode);
6391   rtx rhs, lhs;
6392   enum rtx_code next_code;
6393   int i;
6394   rtx new = 0;
6395   rtx tem;
6396   const char *fmt;
6397
6398   /* Select the code to be used in recursive calls.  Once we are inside an
6399      address, we stay there.  If we have a comparison, set to COMPARE,
6400      but once inside, go back to our default of SET.  */
6401
6402   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6403                : ((code == COMPARE || COMPARISON_P (x))
6404                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6405                : in_code == COMPARE ? SET : in_code);
6406
6407   /* Process depending on the code of this operation.  If NEW is set
6408      nonzero, it will be returned.  */
6409
6410   switch (code)
6411     {
6412     case ASHIFT:
6413       /* Convert shifts by constants into multiplications if inside
6414          an address.  */
6415       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6416           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6417           && INTVAL (XEXP (x, 1)) >= 0)
6418         {
6419           new = make_compound_operation (XEXP (x, 0), next_code);
6420           new = gen_rtx_MULT (mode, new,
6421                               GEN_INT ((HOST_WIDE_INT) 1
6422                                        << INTVAL (XEXP (x, 1))));
6423         }
6424       break;
6425
6426     case AND:
6427       /* If the second operand is not a constant, we can't do anything
6428          with it.  */
6429       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6430         break;
6431
6432       /* If the constant is a power of two minus one and the first operand
6433          is a logical right shift, make an extraction.  */
6434       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6435           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6436         {
6437           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6438           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6439                                  0, in_code == COMPARE);
6440         }
6441
6442       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6443       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6444                && subreg_lowpart_p (XEXP (x, 0))
6445                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6446                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6447         {
6448           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6449                                          next_code);
6450           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6451                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6452                                  0, in_code == COMPARE);
6453         }
6454       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6455       else if ((GET_CODE (XEXP (x, 0)) == XOR
6456                 || GET_CODE (XEXP (x, 0)) == IOR)
6457                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6458                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6459                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6460         {
6461           /* Apply the distributive law, and then try to make extractions.  */
6462           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6463                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6464                                              XEXP (x, 1)),
6465                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6466                                              XEXP (x, 1)));
6467           new = make_compound_operation (new, in_code);
6468         }
6469
6470       /* If we are have (and (rotate X C) M) and C is larger than the number
6471          of bits in M, this is an extraction.  */
6472
6473       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6474                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6475                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6476                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6477         {
6478           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6479           new = make_extraction (mode, new,
6480                                  (GET_MODE_BITSIZE (mode)
6481                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6482                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6483         }
6484
6485       /* On machines without logical shifts, if the operand of the AND is
6486          a logical shift and our mask turns off all the propagated sign
6487          bits, we can replace the logical shift with an arithmetic shift.  */
6488       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6489                && !have_insn_for (LSHIFTRT, mode)
6490                && have_insn_for (ASHIFTRT, mode)
6491                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6492                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6493                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6494                && mode_width <= HOST_BITS_PER_WIDE_INT)
6495         {
6496           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6497
6498           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6499           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6500             SUBST (XEXP (x, 0),
6501                    gen_rtx_ASHIFTRT (mode,
6502                                      make_compound_operation
6503                                      (XEXP (XEXP (x, 0), 0), next_code),
6504                                      XEXP (XEXP (x, 0), 1)));
6505         }
6506
6507       /* If the constant is one less than a power of two, this might be
6508          representable by an extraction even if no shift is present.
6509          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6510          we are in a COMPARE.  */
6511       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6512         new = make_extraction (mode,
6513                                make_compound_operation (XEXP (x, 0),
6514                                                         next_code),
6515                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6516
6517       /* If we are in a comparison and this is an AND with a power of two,
6518          convert this into the appropriate bit extract.  */
6519       else if (in_code == COMPARE
6520                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6521         new = make_extraction (mode,
6522                                make_compound_operation (XEXP (x, 0),
6523                                                         next_code),
6524                                i, NULL_RTX, 1, 1, 0, 1);
6525
6526       break;
6527
6528     case LSHIFTRT:
6529       /* If the sign bit is known to be zero, replace this with an
6530          arithmetic shift.  */
6531       if (have_insn_for (ASHIFTRT, mode)
6532           && ! have_insn_for (LSHIFTRT, mode)
6533           && mode_width <= HOST_BITS_PER_WIDE_INT
6534           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6535         {
6536           new = gen_rtx_ASHIFTRT (mode,
6537                                   make_compound_operation (XEXP (x, 0),
6538                                                            next_code),
6539                                   XEXP (x, 1));
6540           break;
6541         }
6542
6543       /* ... fall through ...  */
6544
6545     case ASHIFTRT:
6546       lhs = XEXP (x, 0);
6547       rhs = XEXP (x, 1);
6548
6549       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6550          this is a SIGN_EXTRACT.  */
6551       if (GET_CODE (rhs) == CONST_INT
6552           && GET_CODE (lhs) == ASHIFT
6553           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6554           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6555         {
6556           new = make_compound_operation (XEXP (lhs, 0), next_code);
6557           new = make_extraction (mode, new,
6558                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6559                                  NULL_RTX, mode_width - INTVAL (rhs),
6560                                  code == LSHIFTRT, 0, in_code == COMPARE);
6561           break;
6562         }
6563
6564       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6565          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6566          also do this for some cases of SIGN_EXTRACT, but it doesn't
6567          seem worth the effort; the case checked for occurs on Alpha.  */
6568
6569       if (!OBJECT_P (lhs)
6570           && ! (GET_CODE (lhs) == SUBREG
6571                 && (OBJECT_P (SUBREG_REG (lhs))))
6572           && GET_CODE (rhs) == CONST_INT
6573           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6574           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6575         new = make_extraction (mode, make_compound_operation (new, next_code),
6576                                0, NULL_RTX, mode_width - INTVAL (rhs),
6577                                code == LSHIFTRT, 0, in_code == COMPARE);
6578
6579       break;
6580
6581     case SUBREG:
6582       /* Call ourselves recursively on the inner expression.  If we are
6583          narrowing the object and it has a different RTL code from
6584          what it originally did, do this SUBREG as a force_to_mode.  */
6585
6586       tem = make_compound_operation (SUBREG_REG (x), in_code);
6587
6588       {
6589         rtx simplified;
6590         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6591                                       SUBREG_BYTE (x));
6592
6593         if (simplified)
6594           tem = simplified;
6595
6596         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6597             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6598             && subreg_lowpart_p (x))
6599           {
6600             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6601                                        0);
6602
6603             /* If we have something other than a SUBREG, we might have
6604                done an expansion, so rerun ourselves.  */
6605             if (GET_CODE (newer) != SUBREG)
6606               newer = make_compound_operation (newer, in_code);
6607
6608             return newer;
6609           }
6610
6611         if (simplified)
6612           return tem;
6613       }
6614       break;
6615
6616     default:
6617       break;
6618     }
6619
6620   if (new)
6621     {
6622       x = gen_lowpart (mode, new);
6623       code = GET_CODE (x);
6624     }
6625
6626   /* Now recursively process each operand of this operation.  */
6627   fmt = GET_RTX_FORMAT (code);
6628   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6629     if (fmt[i] == 'e')
6630       {
6631         new = make_compound_operation (XEXP (x, i), next_code);
6632         SUBST (XEXP (x, i), new);
6633       }
6634
6635   /* If this is a commutative operation, the changes to the operands
6636      may have made it noncanonical.  */
6637   if (COMMUTATIVE_ARITH_P (x)
6638       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6639     {
6640       tem = XEXP (x, 0);
6641       SUBST (XEXP (x, 0), XEXP (x, 1));
6642       SUBST (XEXP (x, 1), tem);
6643     }
6644
6645   return x;
6646 }
6647 \f
6648 /* Given M see if it is a value that would select a field of bits
6649    within an item, but not the entire word.  Return -1 if not.
6650    Otherwise, return the starting position of the field, where 0 is the
6651    low-order bit.
6652
6653    *PLEN is set to the length of the field.  */
6654
6655 static int
6656 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6657 {
6658   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6659   int pos = exact_log2 (m & -m);
6660   int len = 0;
6661
6662   if (pos >= 0)
6663     /* Now shift off the low-order zero bits and see if we have a
6664        power of two minus 1.  */
6665     len = exact_log2 ((m >> pos) + 1);
6666
6667   if (len <= 0)
6668     pos = -1;
6669
6670   *plen = len;
6671   return pos;
6672 }
6673 \f
6674 /* If X refers to a register that equals REG in value, replace these
6675    references with REG.  */
6676 static rtx
6677 canon_reg_for_combine (rtx x, rtx reg)
6678 {
6679   rtx op0, op1, op2;
6680   const char *fmt;
6681   int i;
6682   bool copied;
6683
6684   enum rtx_code code = GET_CODE (x);
6685   switch (GET_RTX_CLASS (code))
6686     {
6687     case RTX_UNARY:
6688       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6689       if (op0 != XEXP (x, 0))
6690         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6691                                    GET_MODE (reg));
6692       break;
6693
6694     case RTX_BIN_ARITH:
6695     case RTX_COMM_ARITH:
6696       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6697       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6698       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6699         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6700       break;
6701
6702     case RTX_COMPARE:
6703     case RTX_COMM_COMPARE:
6704       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6705       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6706       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6707         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6708                                         GET_MODE (op0), op0, op1);
6709       break;
6710
6711     case RTX_TERNARY:
6712     case RTX_BITFIELD_OPS:
6713       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6714       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6715       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6716       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6717         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6718                                      GET_MODE (op0), op0, op1, op2);
6719
6720     case RTX_OBJ:
6721       if (REG_P (x))
6722         {
6723           if (rtx_equal_p (get_last_value (reg), x)
6724               || rtx_equal_p (reg, get_last_value (x)))
6725             return reg;
6726           else
6727             break;
6728         }
6729
6730       /* fall through */
6731
6732     default:
6733       fmt = GET_RTX_FORMAT (code);
6734       copied = false;
6735       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6736         if (fmt[i] == 'e')
6737           {
6738             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6739             if (op != XEXP (x, i))
6740               {
6741                 if (!copied)
6742                   {
6743                     copied = true;
6744                     x = copy_rtx (x);
6745                   }
6746                 XEXP (x, i) = op;
6747               }
6748           }
6749         else if (fmt[i] == 'E')
6750           {
6751             int j;
6752             for (j = 0; j < XVECLEN (x, i); j++)
6753               {
6754                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6755                 if (op != XVECEXP (x, i, j))
6756                   {
6757                     if (!copied)
6758                       {
6759                         copied = true;
6760                         x = copy_rtx (x);
6761                       }
6762                     XVECEXP (x, i, j) = op;
6763                   }
6764               }
6765           }
6766
6767       break;
6768     }
6769
6770   return x;
6771 }
6772
6773 /* Return X converted to MODE.  If the value is already truncated to
6774    MODE we can just return a subreg even though in the general case we
6775    would need an explicit truncation.  */
6776
6777 static rtx
6778 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6779 {
6780   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6781       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6782                                 GET_MODE_BITSIZE (GET_MODE (x)))
6783       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6784     return gen_lowpart (mode, x);
6785   else
6786     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6787 }
6788
6789 /* See if X can be simplified knowing that we will only refer to it in
6790    MODE and will only refer to those bits that are nonzero in MASK.
6791    If other bits are being computed or if masking operations are done
6792    that select a superset of the bits in MASK, they can sometimes be
6793    ignored.
6794
6795    Return a possibly simplified expression, but always convert X to
6796    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6797
6798    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6799    are all off in X.  This is used when X will be complemented, by either
6800    NOT, NEG, or XOR.  */
6801
6802 static rtx
6803 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6804                int just_select)
6805 {
6806   enum rtx_code code = GET_CODE (x);
6807   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6808   enum machine_mode op_mode;
6809   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6810   rtx op0, op1, temp;
6811
6812   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6813      code below will do the wrong thing since the mode of such an
6814      expression is VOIDmode.
6815
6816      Also do nothing if X is a CLOBBER; this can happen if X was
6817      the return value from a call to gen_lowpart.  */
6818   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6819     return x;
6820
6821   /* We want to perform the operation is its present mode unless we know
6822      that the operation is valid in MODE, in which case we do the operation
6823      in MODE.  */
6824   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6825               && have_insn_for (code, mode))
6826              ? mode : GET_MODE (x));
6827
6828   /* It is not valid to do a right-shift in a narrower mode
6829      than the one it came in with.  */
6830   if ((code == LSHIFTRT || code == ASHIFTRT)
6831       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6832     op_mode = GET_MODE (x);
6833
6834   /* Truncate MASK to fit OP_MODE.  */
6835   if (op_mode)
6836     mask &= GET_MODE_MASK (op_mode);
6837
6838   /* When we have an arithmetic operation, or a shift whose count we
6839      do not know, we need to assume that all bits up to the highest-order
6840      bit in MASK will be needed.  This is how we form such a mask.  */
6841   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6842     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6843   else
6844     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6845                    - 1);
6846
6847   /* Determine what bits of X are guaranteed to be (non)zero.  */
6848   nonzero = nonzero_bits (x, mode);
6849
6850   /* If none of the bits in X are needed, return a zero.  */
6851   if (! just_select && (nonzero & mask) == 0)
6852     x = const0_rtx;
6853
6854   /* If X is a CONST_INT, return a new one.  Do this here since the
6855      test below will fail.  */
6856   if (GET_CODE (x) == CONST_INT)
6857     {
6858       if (SCALAR_INT_MODE_P (mode))
6859         return gen_int_mode (INTVAL (x) & mask, mode);
6860       else
6861         {
6862           x = GEN_INT (INTVAL (x) & mask);
6863           return gen_lowpart_common (mode, x);
6864         }
6865     }
6866
6867   /* If X is narrower than MODE and we want all the bits in X's mode, just
6868      get X in the proper mode.  */
6869   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6870       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6871     return gen_lowpart (mode, x);
6872
6873   switch (code)
6874     {
6875     case CLOBBER:
6876       /* If X is a (clobber (const_int)), return it since we know we are
6877          generating something that won't match.  */
6878       return x;
6879
6880     case SIGN_EXTEND:
6881     case ZERO_EXTEND:
6882     case ZERO_EXTRACT:
6883     case SIGN_EXTRACT:
6884       x = expand_compound_operation (x);
6885       if (GET_CODE (x) != code)
6886         return force_to_mode (x, mode, mask, next_select);
6887       break;
6888
6889     case SUBREG:
6890       if (subreg_lowpart_p (x)
6891           /* We can ignore the effect of this SUBREG if it narrows the mode or
6892              if the constant masks to zero all the bits the mode doesn't
6893              have.  */
6894           && ((GET_MODE_SIZE (GET_MODE (x))
6895                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6896               || (0 == (mask
6897                         & GET_MODE_MASK (GET_MODE (x))
6898                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6899         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6900       break;
6901
6902     case AND:
6903       /* If this is an AND with a constant, convert it into an AND
6904          whose constant is the AND of that constant with MASK.  If it
6905          remains an AND of MASK, delete it since it is redundant.  */
6906
6907       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6908         {
6909           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6910                                       mask & INTVAL (XEXP (x, 1)));
6911
6912           /* If X is still an AND, see if it is an AND with a mask that
6913              is just some low-order bits.  If so, and it is MASK, we don't
6914              need it.  */
6915
6916           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6917               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6918                   == mask))
6919             x = XEXP (x, 0);
6920
6921           /* If it remains an AND, try making another AND with the bits
6922              in the mode mask that aren't in MASK turned on.  If the
6923              constant in the AND is wide enough, this might make a
6924              cheaper constant.  */
6925
6926           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6927               && GET_MODE_MASK (GET_MODE (x)) != mask
6928               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6929             {
6930               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6931                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6932               int width = GET_MODE_BITSIZE (GET_MODE (x));
6933               rtx y;
6934
6935               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6936                  number, sign extend it.  */
6937               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6938                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6939                 cval |= (HOST_WIDE_INT) -1 << width;
6940
6941               y = simplify_gen_binary (AND, GET_MODE (x),
6942                                        XEXP (x, 0), GEN_INT (cval));
6943               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6944                 x = y;
6945             }
6946
6947           break;
6948         }
6949
6950       goto binop;
6951
6952     case PLUS:
6953       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6954          low-order bits (as in an alignment operation) and FOO is already
6955          aligned to that boundary, mask C1 to that boundary as well.
6956          This may eliminate that PLUS and, later, the AND.  */
6957
6958       {
6959         unsigned int width = GET_MODE_BITSIZE (mode);
6960         unsigned HOST_WIDE_INT smask = mask;
6961
6962         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6963            number, sign extend it.  */
6964
6965         if (width < HOST_BITS_PER_WIDE_INT
6966             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6967           smask |= (HOST_WIDE_INT) -1 << width;
6968
6969         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6970             && exact_log2 (- smask) >= 0
6971             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6972             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6973           return force_to_mode (plus_constant (XEXP (x, 0),
6974                                                (INTVAL (XEXP (x, 1)) & smask)),
6975                                 mode, smask, next_select);
6976       }
6977
6978       /* ... fall through ...  */
6979
6980     case MULT:
6981       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6982          most significant bit in MASK since carries from those bits will
6983          affect the bits we are interested in.  */
6984       mask = fuller_mask;
6985       goto binop;
6986
6987     case MINUS:
6988       /* If X is (minus C Y) where C's least set bit is larger than any bit
6989          in the mask, then we may replace with (neg Y).  */
6990       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6991           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6992                                         & -INTVAL (XEXP (x, 0))))
6993               > mask))
6994         {
6995           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6996                                   GET_MODE (x));
6997           return force_to_mode (x, mode, mask, next_select);
6998         }
6999
7000       /* Similarly, if C contains every bit in the fuller_mask, then we may
7001          replace with (not Y).  */
7002       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7003           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7004               == INTVAL (XEXP (x, 0))))
7005         {
7006           x = simplify_gen_unary (NOT, GET_MODE (x),
7007                                   XEXP (x, 1), GET_MODE (x));
7008           return force_to_mode (x, mode, mask, next_select);
7009         }
7010
7011       mask = fuller_mask;
7012       goto binop;
7013
7014     case IOR:
7015     case XOR:
7016       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7017          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7018          operation which may be a bitfield extraction.  Ensure that the
7019          constant we form is not wider than the mode of X.  */
7020
7021       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7022           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7023           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7024           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7025           && GET_CODE (XEXP (x, 1)) == CONST_INT
7026           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7027                + floor_log2 (INTVAL (XEXP (x, 1))))
7028               < GET_MODE_BITSIZE (GET_MODE (x)))
7029           && (INTVAL (XEXP (x, 1))
7030               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7031         {
7032           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7033                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7034           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7035                                       XEXP (XEXP (x, 0), 0), temp);
7036           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7037                                    XEXP (XEXP (x, 0), 1));
7038           return force_to_mode (x, mode, mask, next_select);
7039         }
7040
7041     binop:
7042       /* For most binary operations, just propagate into the operation and
7043          change the mode if we have an operation of that mode.  */
7044
7045       op0 = gen_lowpart_or_truncate (op_mode,
7046                                      force_to_mode (XEXP (x, 0), mode, mask,
7047                                                     next_select));
7048       op1 = gen_lowpart_or_truncate (op_mode,
7049                                      force_to_mode (XEXP (x, 1), mode, mask,
7050                                         next_select));
7051
7052       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7053         x = simplify_gen_binary (code, op_mode, op0, op1);
7054       break;
7055
7056     case ASHIFT:
7057       /* For left shifts, do the same, but just for the first operand.
7058          However, we cannot do anything with shifts where we cannot
7059          guarantee that the counts are smaller than the size of the mode
7060          because such a count will have a different meaning in a
7061          wider mode.  */
7062
7063       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7064              && INTVAL (XEXP (x, 1)) >= 0
7065              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7066           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7067                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7068                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7069         break;
7070
7071       /* If the shift count is a constant and we can do arithmetic in
7072          the mode of the shift, refine which bits we need.  Otherwise, use the
7073          conservative form of the mask.  */
7074       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7075           && INTVAL (XEXP (x, 1)) >= 0
7076           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7077           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7078         mask >>= INTVAL (XEXP (x, 1));
7079       else
7080         mask = fuller_mask;
7081
7082       op0 = gen_lowpart_or_truncate (op_mode,
7083                                      force_to_mode (XEXP (x, 0), op_mode,
7084                                                     mask, next_select));
7085
7086       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7087         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7088       break;
7089
7090     case LSHIFTRT:
7091       /* Here we can only do something if the shift count is a constant,
7092          this shift constant is valid for the host, and we can do arithmetic
7093          in OP_MODE.  */
7094
7095       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7096           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7097           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7098         {
7099           rtx inner = XEXP (x, 0);
7100           unsigned HOST_WIDE_INT inner_mask;
7101
7102           /* Select the mask of the bits we need for the shift operand.  */
7103           inner_mask = mask << INTVAL (XEXP (x, 1));
7104
7105           /* We can only change the mode of the shift if we can do arithmetic
7106              in the mode of the shift and INNER_MASK is no wider than the
7107              width of X's mode.  */
7108           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7109             op_mode = GET_MODE (x);
7110
7111           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7112
7113           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7114             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7115         }
7116
7117       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7118          shift and AND produces only copies of the sign bit (C2 is one less
7119          than a power of two), we can do this with just a shift.  */
7120
7121       if (GET_CODE (x) == LSHIFTRT
7122           && GET_CODE (XEXP (x, 1)) == CONST_INT
7123           /* The shift puts one of the sign bit copies in the least significant
7124              bit.  */
7125           && ((INTVAL (XEXP (x, 1))
7126                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7127               >= GET_MODE_BITSIZE (GET_MODE (x)))
7128           && exact_log2 (mask + 1) >= 0
7129           /* Number of bits left after the shift must be more than the mask
7130              needs.  */
7131           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7132               <= GET_MODE_BITSIZE (GET_MODE (x)))
7133           /* Must be more sign bit copies than the mask needs.  */
7134           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7135               >= exact_log2 (mask + 1)))
7136         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7137                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7138                                           - exact_log2 (mask + 1)));
7139
7140       goto shiftrt;
7141
7142     case ASHIFTRT:
7143       /* If we are just looking for the sign bit, we don't need this shift at
7144          all, even if it has a variable count.  */
7145       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7146           && (mask == ((unsigned HOST_WIDE_INT) 1
7147                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7148         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7149
7150       /* If this is a shift by a constant, get a mask that contains those bits
7151          that are not copies of the sign bit.  We then have two cases:  If
7152          MASK only includes those bits, this can be a logical shift, which may
7153          allow simplifications.  If MASK is a single-bit field not within
7154          those bits, we are requesting a copy of the sign bit and hence can
7155          shift the sign bit to the appropriate location.  */
7156
7157       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7158           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7159         {
7160           int i;
7161
7162           /* If the considered data is wider than HOST_WIDE_INT, we can't
7163              represent a mask for all its bits in a single scalar.
7164              But we only care about the lower bits, so calculate these.  */
7165
7166           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7167             {
7168               nonzero = ~(HOST_WIDE_INT) 0;
7169
7170               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7171                  is the number of bits a full-width mask would have set.
7172                  We need only shift if these are fewer than nonzero can
7173                  hold.  If not, we must keep all bits set in nonzero.  */
7174
7175               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7176                   < HOST_BITS_PER_WIDE_INT)
7177                 nonzero >>= INTVAL (XEXP (x, 1))
7178                             + HOST_BITS_PER_WIDE_INT
7179                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7180             }
7181           else
7182             {
7183               nonzero = GET_MODE_MASK (GET_MODE (x));
7184               nonzero >>= INTVAL (XEXP (x, 1));
7185             }
7186
7187           if ((mask & ~nonzero) == 0)
7188             {
7189               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7190                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7191               if (GET_CODE (x) != ASHIFTRT)
7192                 return force_to_mode (x, mode, mask, next_select);
7193             }
7194
7195           else if ((i = exact_log2 (mask)) >= 0)
7196             {
7197               x = simplify_shift_const
7198                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7199                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7200
7201               if (GET_CODE (x) != ASHIFTRT)
7202                 return force_to_mode (x, mode, mask, next_select);
7203             }
7204         }
7205
7206       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7207          even if the shift count isn't a constant.  */
7208       if (mask == 1)
7209         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7210                                  XEXP (x, 0), XEXP (x, 1));
7211
7212     shiftrt:
7213
7214       /* If this is a zero- or sign-extension operation that just affects bits
7215          we don't care about, remove it.  Be sure the call above returned
7216          something that is still a shift.  */
7217
7218       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7219           && GET_CODE (XEXP (x, 1)) == CONST_INT
7220           && INTVAL (XEXP (x, 1)) >= 0
7221           && (INTVAL (XEXP (x, 1))
7222               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7223           && GET_CODE (XEXP (x, 0)) == ASHIFT
7224           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7225         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7226                               next_select);
7227
7228       break;
7229
7230     case ROTATE:
7231     case ROTATERT:
7232       /* If the shift count is constant and we can do computations
7233          in the mode of X, compute where the bits we care about are.
7234          Otherwise, we can't do anything.  Don't change the mode of
7235          the shift or propagate MODE into the shift, though.  */
7236       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7237           && INTVAL (XEXP (x, 1)) >= 0)
7238         {
7239           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7240                                             GET_MODE (x), GEN_INT (mask),
7241                                             XEXP (x, 1));
7242           if (temp && GET_CODE (temp) == CONST_INT)
7243             SUBST (XEXP (x, 0),
7244                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7245                                   INTVAL (temp), next_select));
7246         }
7247       break;
7248
7249     case NEG:
7250       /* If we just want the low-order bit, the NEG isn't needed since it
7251          won't change the low-order bit.  */
7252       if (mask == 1)
7253         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7254
7255       /* We need any bits less significant than the most significant bit in
7256          MASK since carries from those bits will affect the bits we are
7257          interested in.  */
7258       mask = fuller_mask;
7259       goto unop;
7260
7261     case NOT:
7262       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7263          same as the XOR case above.  Ensure that the constant we form is not
7264          wider than the mode of X.  */
7265
7266       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7267           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7268           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7269           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7270               < GET_MODE_BITSIZE (GET_MODE (x)))
7271           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7272         {
7273           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7274                                GET_MODE (x));
7275           temp = simplify_gen_binary (XOR, GET_MODE (x),
7276                                       XEXP (XEXP (x, 0), 0), temp);
7277           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7278                                    temp, XEXP (XEXP (x, 0), 1));
7279
7280           return force_to_mode (x, mode, mask, next_select);
7281         }
7282
7283       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7284          use the full mask inside the NOT.  */
7285       mask = fuller_mask;
7286
7287     unop:
7288       op0 = gen_lowpart_or_truncate (op_mode,
7289                                      force_to_mode (XEXP (x, 0), mode, mask,
7290                                                     next_select));
7291       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7292         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7293       break;
7294
7295     case NE:
7296       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7297          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7298          which is equal to STORE_FLAG_VALUE.  */
7299       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7300           && GET_MODE (XEXP (x, 0)) == mode
7301           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7302           && (nonzero_bits (XEXP (x, 0), mode)
7303               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7304         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7305
7306       break;
7307
7308     case IF_THEN_ELSE:
7309       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7310          written in a narrower mode.  We play it safe and do not do so.  */
7311
7312       SUBST (XEXP (x, 1),
7313              gen_lowpart_or_truncate (GET_MODE (x),
7314                                       force_to_mode (XEXP (x, 1), mode,
7315                                                      mask, next_select)));
7316       SUBST (XEXP (x, 2),
7317              gen_lowpart_or_truncate (GET_MODE (x),
7318                                       force_to_mode (XEXP (x, 2), mode,
7319                                                      mask, next_select)));
7320       break;
7321
7322     default:
7323       break;
7324     }
7325
7326   /* Ensure we return a value of the proper mode.  */
7327   return gen_lowpart_or_truncate (mode, x);
7328 }
7329 \f
7330 /* Return nonzero if X is an expression that has one of two values depending on
7331    whether some other value is zero or nonzero.  In that case, we return the
7332    value that is being tested, *PTRUE is set to the value if the rtx being
7333    returned has a nonzero value, and *PFALSE is set to the other alternative.
7334
7335    If we return zero, we set *PTRUE and *PFALSE to X.  */
7336
7337 static rtx
7338 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7339 {
7340   enum machine_mode mode = GET_MODE (x);
7341   enum rtx_code code = GET_CODE (x);
7342   rtx cond0, cond1, true0, true1, false0, false1;
7343   unsigned HOST_WIDE_INT nz;
7344
7345   /* If we are comparing a value against zero, we are done.  */
7346   if ((code == NE || code == EQ)
7347       && XEXP (x, 1) == const0_rtx)
7348     {
7349       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7350       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7351       return XEXP (x, 0);
7352     }
7353
7354   /* If this is a unary operation whose operand has one of two values, apply
7355      our opcode to compute those values.  */
7356   else if (UNARY_P (x)
7357            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7358     {
7359       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7360       *pfalse = simplify_gen_unary (code, mode, false0,
7361                                     GET_MODE (XEXP (x, 0)));
7362       return cond0;
7363     }
7364
7365   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7366      make can't possibly match and would suppress other optimizations.  */
7367   else if (code == COMPARE)
7368     ;
7369
7370   /* If this is a binary operation, see if either side has only one of two
7371      values.  If either one does or if both do and they are conditional on
7372      the same value, compute the new true and false values.  */
7373   else if (BINARY_P (x))
7374     {
7375       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7376       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7377
7378       if ((cond0 != 0 || cond1 != 0)
7379           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7380         {
7381           /* If if_then_else_cond returned zero, then true/false are the
7382              same rtl.  We must copy one of them to prevent invalid rtl
7383              sharing.  */
7384           if (cond0 == 0)
7385             true0 = copy_rtx (true0);
7386           else if (cond1 == 0)
7387             true1 = copy_rtx (true1);
7388
7389           if (COMPARISON_P (x))
7390             {
7391               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7392                                                 true0, true1);
7393               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7394                                                  false0, false1);
7395              }
7396           else
7397             {
7398               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7399               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7400             }
7401
7402           return cond0 ? cond0 : cond1;
7403         }
7404
7405       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7406          operands is zero when the other is nonzero, and vice-versa,
7407          and STORE_FLAG_VALUE is 1 or -1.  */
7408
7409       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7410           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7411               || code == UMAX)
7412           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7413         {
7414           rtx op0 = XEXP (XEXP (x, 0), 1);
7415           rtx op1 = XEXP (XEXP (x, 1), 1);
7416
7417           cond0 = XEXP (XEXP (x, 0), 0);
7418           cond1 = XEXP (XEXP (x, 1), 0);
7419
7420           if (COMPARISON_P (cond0)
7421               && COMPARISON_P (cond1)
7422               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7423                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7424                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7425                   || ((swap_condition (GET_CODE (cond0))
7426                        == reversed_comparison_code (cond1, NULL))
7427                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7428                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7429               && ! side_effects_p (x))
7430             {
7431               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7432               *pfalse = simplify_gen_binary (MULT, mode,
7433                                              (code == MINUS
7434                                               ? simplify_gen_unary (NEG, mode,
7435                                                                     op1, mode)
7436                                               : op1),
7437                                               const_true_rtx);
7438               return cond0;
7439             }
7440         }
7441
7442       /* Similarly for MULT, AND and UMIN, except that for these the result
7443          is always zero.  */
7444       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7445           && (code == MULT || code == AND || code == UMIN)
7446           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7447         {
7448           cond0 = XEXP (XEXP (x, 0), 0);
7449           cond1 = XEXP (XEXP (x, 1), 0);
7450
7451           if (COMPARISON_P (cond0)
7452               && COMPARISON_P (cond1)
7453               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7454                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7455                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7456                   || ((swap_condition (GET_CODE (cond0))
7457                        == reversed_comparison_code (cond1, NULL))
7458                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7459                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7460               && ! side_effects_p (x))
7461             {
7462               *ptrue = *pfalse = const0_rtx;
7463               return cond0;
7464             }
7465         }
7466     }
7467
7468   else if (code == IF_THEN_ELSE)
7469     {
7470       /* If we have IF_THEN_ELSE already, extract the condition and
7471          canonicalize it if it is NE or EQ.  */
7472       cond0 = XEXP (x, 0);
7473       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7474       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7475         return XEXP (cond0, 0);
7476       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7477         {
7478           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7479           return XEXP (cond0, 0);
7480         }
7481       else
7482         return cond0;
7483     }
7484
7485   /* If X is a SUBREG, we can narrow both the true and false values
7486      if the inner expression, if there is a condition.  */
7487   else if (code == SUBREG
7488            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7489                                                &true0, &false0)))
7490     {
7491       true0 = simplify_gen_subreg (mode, true0,
7492                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7493       false0 = simplify_gen_subreg (mode, false0,
7494                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7495       if (true0 && false0)
7496         {
7497           *ptrue = true0;
7498           *pfalse = false0;
7499           return cond0;
7500         }
7501     }
7502
7503   /* If X is a constant, this isn't special and will cause confusions
7504      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7505   else if (CONSTANT_P (x)
7506            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7507     ;
7508
7509   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7510      will be least confusing to the rest of the compiler.  */
7511   else if (mode == BImode)
7512     {
7513       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7514       return x;
7515     }
7516
7517   /* If X is known to be either 0 or -1, those are the true and
7518      false values when testing X.  */
7519   else if (x == constm1_rtx || x == const0_rtx
7520            || (mode != VOIDmode
7521                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7522     {
7523       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7524       return x;
7525     }
7526
7527   /* Likewise for 0 or a single bit.  */
7528   else if (SCALAR_INT_MODE_P (mode)
7529            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7530            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7531     {
7532       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7533       return x;
7534     }
7535
7536   /* Otherwise fail; show no condition with true and false values the same.  */
7537   *ptrue = *pfalse = x;
7538   return 0;
7539 }
7540 \f
7541 /* Return the value of expression X given the fact that condition COND
7542    is known to be true when applied to REG as its first operand and VAL
7543    as its second.  X is known to not be shared and so can be modified in
7544    place.
7545
7546    We only handle the simplest cases, and specifically those cases that
7547    arise with IF_THEN_ELSE expressions.  */
7548
7549 static rtx
7550 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7551 {
7552   enum rtx_code code = GET_CODE (x);
7553   rtx temp;
7554   const char *fmt;
7555   int i, j;
7556
7557   if (side_effects_p (x))
7558     return x;
7559
7560   /* If either operand of the condition is a floating point value,
7561      then we have to avoid collapsing an EQ comparison.  */
7562   if (cond == EQ
7563       && rtx_equal_p (x, reg)
7564       && ! FLOAT_MODE_P (GET_MODE (x))
7565       && ! FLOAT_MODE_P (GET_MODE (val)))
7566     return val;
7567
7568   if (cond == UNEQ && rtx_equal_p (x, reg))
7569     return val;
7570
7571   /* If X is (abs REG) and we know something about REG's relationship
7572      with zero, we may be able to simplify this.  */
7573
7574   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7575     switch (cond)
7576       {
7577       case GE:  case GT:  case EQ:
7578         return XEXP (x, 0);
7579       case LT:  case LE:
7580         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7581                                    XEXP (x, 0),
7582                                    GET_MODE (XEXP (x, 0)));
7583       default:
7584         break;
7585       }
7586
7587   /* The only other cases we handle are MIN, MAX, and comparisons if the
7588      operands are the same as REG and VAL.  */
7589
7590   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7591     {
7592       if (rtx_equal_p (XEXP (x, 0), val))
7593         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7594
7595       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7596         {
7597           if (COMPARISON_P (x))
7598             {
7599               if (comparison_dominates_p (cond, code))
7600                 return const_true_rtx;
7601
7602               code = reversed_comparison_code (x, NULL);
7603               if (code != UNKNOWN
7604                   && comparison_dominates_p (cond, code))
7605                 return const0_rtx;
7606               else
7607                 return x;
7608             }
7609           else if (code == SMAX || code == SMIN
7610                    || code == UMIN || code == UMAX)
7611             {
7612               int unsignedp = (code == UMIN || code == UMAX);
7613
7614               /* Do not reverse the condition when it is NE or EQ.
7615                  This is because we cannot conclude anything about
7616                  the value of 'SMAX (x, y)' when x is not equal to y,
7617                  but we can when x equals y.  */
7618               if ((code == SMAX || code == UMAX)
7619                   && ! (cond == EQ || cond == NE))
7620                 cond = reverse_condition (cond);
7621
7622               switch (cond)
7623                 {
7624                 case GE:   case GT:
7625                   return unsignedp ? x : XEXP (x, 1);
7626                 case LE:   case LT:
7627                   return unsignedp ? x : XEXP (x, 0);
7628                 case GEU:  case GTU:
7629                   return unsignedp ? XEXP (x, 1) : x;
7630                 case LEU:  case LTU:
7631                   return unsignedp ? XEXP (x, 0) : x;
7632                 default:
7633                   break;
7634                 }
7635             }
7636         }
7637     }
7638   else if (code == SUBREG)
7639     {
7640       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7641       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7642
7643       if (SUBREG_REG (x) != r)
7644         {
7645           /* We must simplify subreg here, before we lose track of the
7646              original inner_mode.  */
7647           new = simplify_subreg (GET_MODE (x), r,
7648                                  inner_mode, SUBREG_BYTE (x));
7649           if (new)
7650             return new;
7651           else
7652             SUBST (SUBREG_REG (x), r);
7653         }
7654
7655       return x;
7656     }
7657   /* We don't have to handle SIGN_EXTEND here, because even in the
7658      case of replacing something with a modeless CONST_INT, a
7659      CONST_INT is already (supposed to be) a valid sign extension for
7660      its narrower mode, which implies it's already properly
7661      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7662      story is different.  */
7663   else if (code == ZERO_EXTEND)
7664     {
7665       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7666       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7667
7668       if (XEXP (x, 0) != r)
7669         {
7670           /* We must simplify the zero_extend here, before we lose
7671              track of the original inner_mode.  */
7672           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7673                                           r, inner_mode);
7674           if (new)
7675             return new;
7676           else
7677             SUBST (XEXP (x, 0), r);
7678         }
7679
7680       return x;
7681     }
7682
7683   fmt = GET_RTX_FORMAT (code);
7684   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7685     {
7686       if (fmt[i] == 'e')
7687         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7688       else if (fmt[i] == 'E')
7689         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7690           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7691                                                 cond, reg, val));
7692     }
7693
7694   return x;
7695 }
7696 \f
7697 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7698    assignment as a field assignment.  */
7699
7700 static int
7701 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7702 {
7703   if (x == y || rtx_equal_p (x, y))
7704     return 1;
7705
7706   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7707     return 0;
7708
7709   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7710      Note that all SUBREGs of MEM are paradoxical; otherwise they
7711      would have been rewritten.  */
7712   if (MEM_P (x) && GET_CODE (y) == SUBREG
7713       && MEM_P (SUBREG_REG (y))
7714       && rtx_equal_p (SUBREG_REG (y),
7715                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7716     return 1;
7717
7718   if (MEM_P (y) && GET_CODE (x) == SUBREG
7719       && MEM_P (SUBREG_REG (x))
7720       && rtx_equal_p (SUBREG_REG (x),
7721                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7722     return 1;
7723
7724   /* We used to see if get_last_value of X and Y were the same but that's
7725      not correct.  In one direction, we'll cause the assignment to have
7726      the wrong destination and in the case, we'll import a register into this
7727      insn that might have already have been dead.   So fail if none of the
7728      above cases are true.  */
7729   return 0;
7730 }
7731 \f
7732 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7733    Return that assignment if so.
7734
7735    We only handle the most common cases.  */
7736
7737 static rtx
7738 make_field_assignment (rtx x)
7739 {
7740   rtx dest = SET_DEST (x);
7741   rtx src = SET_SRC (x);
7742   rtx assign;
7743   rtx rhs, lhs;
7744   HOST_WIDE_INT c1;
7745   HOST_WIDE_INT pos;
7746   unsigned HOST_WIDE_INT len;
7747   rtx other;
7748   enum machine_mode mode;
7749
7750   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7751      a clear of a one-bit field.  We will have changed it to
7752      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7753      for a SUBREG.  */
7754
7755   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7756       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7757       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7758       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7759     {
7760       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7761                                 1, 1, 1, 0);
7762       if (assign != 0)
7763         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7764       return x;
7765     }
7766
7767   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7768       && subreg_lowpart_p (XEXP (src, 0))
7769       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7770           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7771       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7772       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7773       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7774       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7775     {
7776       assign = make_extraction (VOIDmode, dest, 0,
7777                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7778                                 1, 1, 1, 0);
7779       if (assign != 0)
7780         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7781       return x;
7782     }
7783
7784   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7785      one-bit field.  */
7786   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7787       && XEXP (XEXP (src, 0), 0) == const1_rtx
7788       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7789     {
7790       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7791                                 1, 1, 1, 0);
7792       if (assign != 0)
7793         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7794       return x;
7795     }
7796
7797   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7798      SRC is an AND with all bits of that field set, then we can discard
7799      the AND.  */
7800   if (GET_CODE (dest) == ZERO_EXTRACT
7801       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7802       && GET_CODE (src) == AND
7803       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7804     {
7805       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7806       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7807       unsigned HOST_WIDE_INT ze_mask;
7808
7809       if (width >= HOST_BITS_PER_WIDE_INT)
7810         ze_mask = -1;
7811       else
7812         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7813
7814       /* Complete overlap.  We can remove the source AND.  */
7815       if ((and_mask & ze_mask) == ze_mask)
7816         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7817
7818       /* Partial overlap.  We can reduce the source AND.  */
7819       if ((and_mask & ze_mask) != and_mask)
7820         {
7821           mode = GET_MODE (src);
7822           src = gen_rtx_AND (mode, XEXP (src, 0),
7823                              gen_int_mode (and_mask & ze_mask, mode));
7824           return gen_rtx_SET (VOIDmode, dest, src);
7825         }
7826     }
7827
7828   /* The other case we handle is assignments into a constant-position
7829      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7830      a mask that has all one bits except for a group of zero bits and
7831      OTHER is known to have zeros where C1 has ones, this is such an
7832      assignment.  Compute the position and length from C1.  Shift OTHER
7833      to the appropriate position, force it to the required mode, and
7834      make the extraction.  Check for the AND in both operands.  */
7835
7836   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7837     return x;
7838
7839   rhs = expand_compound_operation (XEXP (src, 0));
7840   lhs = expand_compound_operation (XEXP (src, 1));
7841
7842   if (GET_CODE (rhs) == AND
7843       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7844       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7845     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7846   else if (GET_CODE (lhs) == AND
7847            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7848            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7849     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7850   else
7851     return x;
7852
7853   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7854   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7855       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7856       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7857     return x;
7858
7859   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7860   if (assign == 0)
7861     return x;
7862
7863   /* The mode to use for the source is the mode of the assignment, or of
7864      what is inside a possible STRICT_LOW_PART.  */
7865   mode = (GET_CODE (assign) == STRICT_LOW_PART
7866           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7867
7868   /* Shift OTHER right POS places and make it the source, restricting it
7869      to the proper length and mode.  */
7870
7871   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7872                                                      GET_MODE (src),
7873                                                      other, pos),
7874                                dest);
7875   src = force_to_mode (src, mode,
7876                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7877                        ? ~(unsigned HOST_WIDE_INT) 0
7878                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7879                        0);
7880
7881   /* If SRC is masked by an AND that does not make a difference in
7882      the value being stored, strip it.  */
7883   if (GET_CODE (assign) == ZERO_EXTRACT
7884       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7885       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7886       && GET_CODE (src) == AND
7887       && GET_CODE (XEXP (src, 1)) == CONST_INT
7888       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7889           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7890     src = XEXP (src, 0);
7891
7892   return gen_rtx_SET (VOIDmode, assign, src);
7893 }
7894 \f
7895 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7896    if so.  */
7897
7898 static rtx
7899 apply_distributive_law (rtx x)
7900 {
7901   enum rtx_code code = GET_CODE (x);
7902   enum rtx_code inner_code;
7903   rtx lhs, rhs, other;
7904   rtx tem;
7905
7906   /* Distributivity is not true for floating point as it can change the
7907      value.  So we don't do it unless -funsafe-math-optimizations.  */
7908   if (FLOAT_MODE_P (GET_MODE (x))
7909       && ! flag_unsafe_math_optimizations)
7910     return x;
7911
7912   /* The outer operation can only be one of the following:  */
7913   if (code != IOR && code != AND && code != XOR
7914       && code != PLUS && code != MINUS)
7915     return x;
7916
7917   lhs = XEXP (x, 0);
7918   rhs = XEXP (x, 1);
7919
7920   /* If either operand is a primitive we can't do anything, so get out
7921      fast.  */
7922   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7923     return x;
7924
7925   lhs = expand_compound_operation (lhs);
7926   rhs = expand_compound_operation (rhs);
7927   inner_code = GET_CODE (lhs);
7928   if (inner_code != GET_CODE (rhs))
7929     return x;
7930
7931   /* See if the inner and outer operations distribute.  */
7932   switch (inner_code)
7933     {
7934     case LSHIFTRT:
7935     case ASHIFTRT:
7936     case AND:
7937     case IOR:
7938       /* These all distribute except over PLUS.  */
7939       if (code == PLUS || code == MINUS)
7940         return x;
7941       break;
7942
7943     case MULT:
7944       if (code != PLUS && code != MINUS)
7945         return x;
7946       break;
7947
7948     case ASHIFT:
7949       /* This is also a multiply, so it distributes over everything.  */
7950       break;
7951
7952     case SUBREG:
7953       /* Non-paradoxical SUBREGs distributes over all operations,
7954          provided the inner modes and byte offsets are the same, this
7955          is an extraction of a low-order part, we don't convert an fp
7956          operation to int or vice versa, this is not a vector mode,
7957          and we would not be converting a single-word operation into a
7958          multi-word operation.  The latter test is not required, but
7959          it prevents generating unneeded multi-word operations.  Some
7960          of the previous tests are redundant given the latter test,
7961          but are retained because they are required for correctness.
7962
7963          We produce the result slightly differently in this case.  */
7964
7965       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7966           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7967           || ! subreg_lowpart_p (lhs)
7968           || (GET_MODE_CLASS (GET_MODE (lhs))
7969               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7970           || (GET_MODE_SIZE (GET_MODE (lhs))
7971               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7972           || VECTOR_MODE_P (GET_MODE (lhs))
7973           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7974           /* Result might need to be truncated.  Don't change mode if
7975              explicit truncation is needed.  */
7976           || !TRULY_NOOP_TRUNCATION
7977                (GET_MODE_BITSIZE (GET_MODE (x)),
7978                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7979         return x;
7980
7981       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7982                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7983       return gen_lowpart (GET_MODE (x), tem);
7984
7985     default:
7986       return x;
7987     }
7988
7989   /* Set LHS and RHS to the inner operands (A and B in the example
7990      above) and set OTHER to the common operand (C in the example).
7991      There is only one way to do this unless the inner operation is
7992      commutative.  */
7993   if (COMMUTATIVE_ARITH_P (lhs)
7994       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7995     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7996   else if (COMMUTATIVE_ARITH_P (lhs)
7997            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7998     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7999   else if (COMMUTATIVE_ARITH_P (lhs)
8000            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8001     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8002   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8003     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8004   else
8005     return x;
8006
8007   /* Form the new inner operation, seeing if it simplifies first.  */
8008   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8009
8010   /* There is one exception to the general way of distributing:
8011      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8012   if (code == XOR && inner_code == IOR)
8013     {
8014       inner_code = AND;
8015       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8016     }
8017
8018   /* We may be able to continuing distributing the result, so call
8019      ourselves recursively on the inner operation before forming the
8020      outer operation, which we return.  */
8021   return simplify_gen_binary (inner_code, GET_MODE (x),
8022                               apply_distributive_law (tem), other);
8023 }
8024
8025 /* See if X is of the form (* (+ A B) C), and if so convert to
8026    (+ (* A C) (* B C)) and try to simplify.
8027
8028    Most of the time, this results in no change.  However, if some of
8029    the operands are the same or inverses of each other, simplifications
8030    will result.
8031
8032    For example, (and (ior A B) (not B)) can occur as the result of
8033    expanding a bit field assignment.  When we apply the distributive
8034    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8035    which then simplifies to (and (A (not B))).
8036
8037    Note that no checks happen on the validity of applying the inverse
8038    distributive law.  This is pointless since we can do it in the
8039    few places where this routine is called.
8040
8041    N is the index of the term that is decomposed (the arithmetic operation,
8042    i.e. (+ A B) in the first example above).  !N is the index of the term that
8043    is distributed, i.e. of C in the first example above.  */
8044 static rtx
8045 distribute_and_simplify_rtx (rtx x, int n)
8046 {
8047   enum machine_mode mode;
8048   enum rtx_code outer_code, inner_code;
8049   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8050
8051   decomposed = XEXP (x, n);
8052   if (!ARITHMETIC_P (decomposed))
8053     return NULL_RTX;
8054
8055   mode = GET_MODE (x);
8056   outer_code = GET_CODE (x);
8057   distributed = XEXP (x, !n);
8058
8059   inner_code = GET_CODE (decomposed);
8060   inner_op0 = XEXP (decomposed, 0);
8061   inner_op1 = XEXP (decomposed, 1);
8062
8063   /* Special case (and (xor B C) (not A)), which is equivalent to
8064      (xor (ior A B) (ior A C))  */
8065   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8066     {
8067       distributed = XEXP (distributed, 0);
8068       outer_code = IOR;
8069     }
8070
8071   if (n == 0)
8072     {
8073       /* Distribute the second term.  */
8074       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8075       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8076     }
8077   else
8078     {
8079       /* Distribute the first term.  */
8080       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8081       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8082     }
8083
8084   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8085                                                      new_op0, new_op1));
8086   if (GET_CODE (tmp) != outer_code
8087       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8088     return tmp;
8089
8090   return NULL_RTX;
8091 }
8092 \f
8093 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8094    in MODE.  Return an equivalent form, if different from (and VAROP
8095    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8096
8097 static rtx
8098 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8099                           unsigned HOST_WIDE_INT constop)
8100 {
8101   unsigned HOST_WIDE_INT nonzero;
8102   unsigned HOST_WIDE_INT orig_constop;
8103   rtx orig_varop;
8104   int i;
8105
8106   orig_varop = varop;
8107   orig_constop = constop;
8108   if (GET_CODE (varop) == CLOBBER)
8109     return NULL_RTX;
8110
8111   /* Simplify VAROP knowing that we will be only looking at some of the
8112      bits in it.
8113
8114      Note by passing in CONSTOP, we guarantee that the bits not set in
8115      CONSTOP are not significant and will never be examined.  We must
8116      ensure that is the case by explicitly masking out those bits
8117      before returning.  */
8118   varop = force_to_mode (varop, mode, constop, 0);
8119
8120   /* If VAROP is a CLOBBER, we will fail so return it.  */
8121   if (GET_CODE (varop) == CLOBBER)
8122     return varop;
8123
8124   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8125      to VAROP and return the new constant.  */
8126   if (GET_CODE (varop) == CONST_INT)
8127     return gen_int_mode (INTVAL (varop) & constop, mode);
8128
8129   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8130      a call to nonzero_bits, here we don't care about bits outside
8131      MODE.  */
8132
8133   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8134
8135   /* Turn off all bits in the constant that are known to already be zero.
8136      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8137      which is tested below.  */
8138
8139   constop &= nonzero;
8140
8141   /* If we don't have any bits left, return zero.  */
8142   if (constop == 0)
8143     return const0_rtx;
8144
8145   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8146      a power of two, we can replace this with an ASHIFT.  */
8147   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8148       && (i = exact_log2 (constop)) >= 0)
8149     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8150
8151   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8152      or XOR, then try to apply the distributive law.  This may eliminate
8153      operations if either branch can be simplified because of the AND.
8154      It may also make some cases more complex, but those cases probably
8155      won't match a pattern either with or without this.  */
8156
8157   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8158     return
8159       gen_lowpart
8160         (mode,
8161          apply_distributive_law
8162          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8163                                simplify_and_const_int (NULL_RTX,
8164                                                        GET_MODE (varop),
8165                                                        XEXP (varop, 0),
8166                                                        constop),
8167                                simplify_and_const_int (NULL_RTX,
8168                                                        GET_MODE (varop),
8169                                                        XEXP (varop, 1),
8170                                                        constop))));
8171
8172   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8173      the AND and see if one of the operands simplifies to zero.  If so, we
8174      may eliminate it.  */
8175
8176   if (GET_CODE (varop) == PLUS
8177       && exact_log2 (constop + 1) >= 0)
8178     {
8179       rtx o0, o1;
8180
8181       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8182       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8183       if (o0 == const0_rtx)
8184         return o1;
8185       if (o1 == const0_rtx)
8186         return o0;
8187     }
8188
8189   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8190   varop = gen_lowpart (mode, varop);
8191   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8192     return NULL_RTX;
8193
8194   /* If we are only masking insignificant bits, return VAROP.  */
8195   if (constop == nonzero)
8196     return varop;
8197
8198   if (varop == orig_varop && constop == orig_constop)
8199     return NULL_RTX;
8200
8201   /* Otherwise, return an AND.  */
8202   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8203 }
8204
8205
8206 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8207    in MODE.
8208
8209    Return an equivalent form, if different from X.  Otherwise, return X.  If
8210    X is zero, we are to always construct the equivalent form.  */
8211
8212 static rtx
8213 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8214                         unsigned HOST_WIDE_INT constop)
8215 {
8216   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8217   if (tem)
8218     return tem;
8219
8220   if (!x)
8221     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8222                              gen_int_mode (constop, mode));
8223   if (GET_MODE (x) != mode)
8224     x = gen_lowpart (mode, x);
8225   return x;
8226 }
8227 \f
8228 /* Given a REG, X, compute which bits in X can be nonzero.
8229    We don't care about bits outside of those defined in MODE.
8230
8231    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8232    a shift, AND, or zero_extract, we can do better.  */
8233
8234 static rtx
8235 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8236                               rtx known_x ATTRIBUTE_UNUSED,
8237                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8238                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8239                               unsigned HOST_WIDE_INT *nonzero)
8240 {
8241   rtx tem;
8242
8243   /* If X is a register whose nonzero bits value is current, use it.
8244      Otherwise, if X is a register whose value we can find, use that
8245      value.  Otherwise, use the previously-computed global nonzero bits
8246      for this register.  */
8247
8248   if (reg_stat[REGNO (x)].last_set_value != 0
8249       && (reg_stat[REGNO (x)].last_set_mode == mode
8250           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8251               && GET_MODE_CLASS (mode) == MODE_INT))
8252       && (reg_stat[REGNO (x)].last_set_label == label_tick
8253           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8254               && REG_N_SETS (REGNO (x)) == 1
8255               && ! REGNO_REG_SET_P
8256                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8257                   REGNO (x))))
8258       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8259     {
8260       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8261       return NULL;
8262     }
8263
8264   tem = get_last_value (x);
8265
8266   if (tem)
8267     {
8268 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8269       /* If X is narrower than MODE and TEM is a non-negative
8270          constant that would appear negative in the mode of X,
8271          sign-extend it for use in reg_nonzero_bits because some
8272          machines (maybe most) will actually do the sign-extension
8273          and this is the conservative approach.
8274
8275          ??? For 2.5, try to tighten up the MD files in this regard
8276          instead of this kludge.  */
8277
8278       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8279           && GET_CODE (tem) == CONST_INT
8280           && INTVAL (tem) > 0
8281           && 0 != (INTVAL (tem)
8282                    & ((HOST_WIDE_INT) 1
8283                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8284         tem = GEN_INT (INTVAL (tem)
8285                        | ((HOST_WIDE_INT) (-1)
8286                           << GET_MODE_BITSIZE (GET_MODE (x))));
8287 #endif
8288       return tem;
8289     }
8290   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8291     {
8292       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8293
8294       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8295         /* We don't know anything about the upper bits.  */
8296         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8297       *nonzero &= mask;
8298     }
8299
8300   return NULL;
8301 }
8302
8303 /* Return the number of bits at the high-order end of X that are known to
8304    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8305    VOIDmode, X will be used in its own mode.  The returned value  will always
8306    be between 1 and the number of bits in MODE.  */
8307
8308 static rtx
8309 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8310                                      rtx known_x ATTRIBUTE_UNUSED,
8311                                      enum machine_mode known_mode
8312                                      ATTRIBUTE_UNUSED,
8313                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8314                                      unsigned int *result)
8315 {
8316   rtx tem;
8317
8318   if (reg_stat[REGNO (x)].last_set_value != 0
8319       && reg_stat[REGNO (x)].last_set_mode == mode
8320       && (reg_stat[REGNO (x)].last_set_label == label_tick
8321           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8322               && REG_N_SETS (REGNO (x)) == 1
8323               && ! REGNO_REG_SET_P
8324                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8325                   REGNO (x))))
8326       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8327     {
8328       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8329       return NULL;
8330     }
8331
8332   tem = get_last_value (x);
8333   if (tem != 0)
8334     return tem;
8335
8336   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8337       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8338     *result = reg_stat[REGNO (x)].sign_bit_copies;
8339
8340   return NULL;
8341 }
8342 \f
8343 /* Return the number of "extended" bits there are in X, when interpreted
8344    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8345    unsigned quantities, this is the number of high-order zero bits.
8346    For signed quantities, this is the number of copies of the sign bit
8347    minus 1.  In both case, this function returns the number of "spare"
8348    bits.  For example, if two quantities for which this function returns
8349    at least 1 are added, the addition is known not to overflow.
8350
8351    This function will always return 0 unless called during combine, which
8352    implies that it must be called from a define_split.  */
8353
8354 unsigned int
8355 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8356 {
8357   if (nonzero_sign_valid == 0)
8358     return 0;
8359
8360   return (unsignedp
8361           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8362              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8363                                - floor_log2 (nonzero_bits (x, mode)))
8364              : 0)
8365           : num_sign_bit_copies (x, mode) - 1);
8366 }
8367 \f
8368 /* This function is called from `simplify_shift_const' to merge two
8369    outer operations.  Specifically, we have already found that we need
8370    to perform operation *POP0 with constant *PCONST0 at the outermost
8371    position.  We would now like to also perform OP1 with constant CONST1
8372    (with *POP0 being done last).
8373
8374    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8375    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8376    complement the innermost operand, otherwise it is unchanged.
8377
8378    MODE is the mode in which the operation will be done.  No bits outside
8379    the width of this mode matter.  It is assumed that the width of this mode
8380    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8381
8382    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8383    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8384    result is simply *PCONST0.
8385
8386    If the resulting operation cannot be expressed as one operation, we
8387    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8388
8389 static int
8390 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8391 {
8392   enum rtx_code op0 = *pop0;
8393   HOST_WIDE_INT const0 = *pconst0;
8394
8395   const0 &= GET_MODE_MASK (mode);
8396   const1 &= GET_MODE_MASK (mode);
8397
8398   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8399   if (op0 == AND)
8400     const1 &= const0;
8401
8402   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8403      if OP0 is SET.  */
8404
8405   if (op1 == UNKNOWN || op0 == SET)
8406     return 1;
8407
8408   else if (op0 == UNKNOWN)
8409     op0 = op1, const0 = const1;
8410
8411   else if (op0 == op1)
8412     {
8413       switch (op0)
8414         {
8415         case AND:
8416           const0 &= const1;
8417           break;
8418         case IOR:
8419           const0 |= const1;
8420           break;
8421         case XOR:
8422           const0 ^= const1;
8423           break;
8424         case PLUS:
8425           const0 += const1;
8426           break;
8427         case NEG:
8428           op0 = UNKNOWN;
8429           break;
8430         default:
8431           break;
8432         }
8433     }
8434
8435   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8436   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8437     return 0;
8438
8439   /* If the two constants aren't the same, we can't do anything.  The
8440      remaining six cases can all be done.  */
8441   else if (const0 != const1)
8442     return 0;
8443
8444   else
8445     switch (op0)
8446       {
8447       case IOR:
8448         if (op1 == AND)
8449           /* (a & b) | b == b */
8450           op0 = SET;
8451         else /* op1 == XOR */
8452           /* (a ^ b) | b == a | b */
8453           {;}
8454         break;
8455
8456       case XOR:
8457         if (op1 == AND)
8458           /* (a & b) ^ b == (~a) & b */
8459           op0 = AND, *pcomp_p = 1;
8460         else /* op1 == IOR */
8461           /* (a | b) ^ b == a & ~b */
8462           op0 = AND, const0 = ~const0;
8463         break;
8464
8465       case AND:
8466         if (op1 == IOR)
8467           /* (a | b) & b == b */
8468         op0 = SET;
8469         else /* op1 == XOR */
8470           /* (a ^ b) & b) == (~a) & b */
8471           *pcomp_p = 1;
8472         break;
8473       default:
8474         break;
8475       }
8476
8477   /* Check for NO-OP cases.  */
8478   const0 &= GET_MODE_MASK (mode);
8479   if (const0 == 0
8480       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8481     op0 = UNKNOWN;
8482   else if (const0 == 0 && op0 == AND)
8483     op0 = SET;
8484   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8485            && op0 == AND)
8486     op0 = UNKNOWN;
8487
8488   /* ??? Slightly redundant with the above mask, but not entirely.
8489      Moving this above means we'd have to sign-extend the mode mask
8490      for the final test.  */
8491   const0 = trunc_int_for_mode (const0, mode);
8492
8493   *pop0 = op0;
8494   *pconst0 = const0;
8495
8496   return 1;
8497 }
8498 \f
8499 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8500    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8501    simplify it.  Otherwise, return a simplified value.
8502
8503    The shift is normally computed in the widest mode we find in VAROP, as
8504    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8505    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8506
8507 static rtx
8508 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8509                         rtx varop, int orig_count)
8510 {
8511   enum rtx_code orig_code = code;
8512   rtx orig_varop = varop;
8513   int count;
8514   enum machine_mode mode = result_mode;
8515   enum machine_mode shift_mode, tmode;
8516   unsigned int mode_words
8517     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8518   /* We form (outer_op (code varop count) (outer_const)).  */
8519   enum rtx_code outer_op = UNKNOWN;
8520   HOST_WIDE_INT outer_const = 0;
8521   int complement_p = 0;
8522   rtx new, x;
8523
8524   /* Make sure and truncate the "natural" shift on the way in.  We don't
8525      want to do this inside the loop as it makes it more difficult to
8526      combine shifts.  */
8527   if (SHIFT_COUNT_TRUNCATED)
8528     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8529
8530   /* If we were given an invalid count, don't do anything except exactly
8531      what was requested.  */
8532
8533   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8534     return NULL_RTX;
8535
8536   count = orig_count;
8537
8538   /* Unless one of the branches of the `if' in this loop does a `continue',
8539      we will `break' the loop after the `if'.  */
8540
8541   while (count != 0)
8542     {
8543       /* If we have an operand of (clobber (const_int 0)), fail.  */
8544       if (GET_CODE (varop) == CLOBBER)
8545         return NULL_RTX;
8546
8547       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8548          here would cause an infinite loop.  */
8549       if (complement_p)
8550         break;
8551
8552       /* Convert ROTATERT to ROTATE.  */
8553       if (code == ROTATERT)
8554         {
8555           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8556           code = ROTATE;
8557           if (VECTOR_MODE_P (result_mode))
8558             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8559           else
8560             count = bitsize - count;
8561         }
8562
8563       /* We need to determine what mode we will do the shift in.  If the
8564          shift is a right shift or a ROTATE, we must always do it in the mode
8565          it was originally done in.  Otherwise, we can do it in MODE, the
8566          widest mode encountered.  */
8567       shift_mode
8568         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8569            ? result_mode : mode);
8570
8571       /* Handle cases where the count is greater than the size of the mode
8572          minus 1.  For ASHIFT, use the size minus one as the count (this can
8573          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8574          take the count modulo the size.  For other shifts, the result is
8575          zero.
8576
8577          Since these shifts are being produced by the compiler by combining
8578          multiple operations, each of which are defined, we know what the
8579          result is supposed to be.  */
8580
8581       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8582         {
8583           if (code == ASHIFTRT)
8584             count = GET_MODE_BITSIZE (shift_mode) - 1;
8585           else if (code == ROTATE || code == ROTATERT)
8586             count %= GET_MODE_BITSIZE (shift_mode);
8587           else
8588             {
8589               /* We can't simply return zero because there may be an
8590                  outer op.  */
8591               varop = const0_rtx;
8592               count = 0;
8593               break;
8594             }
8595         }
8596
8597       /* An arithmetic right shift of a quantity known to be -1 or 0
8598          is a no-op.  */
8599       if (code == ASHIFTRT
8600           && (num_sign_bit_copies (varop, shift_mode)
8601               == GET_MODE_BITSIZE (shift_mode)))
8602         {
8603           count = 0;
8604           break;
8605         }
8606
8607       /* If we are doing an arithmetic right shift and discarding all but
8608          the sign bit copies, this is equivalent to doing a shift by the
8609          bitsize minus one.  Convert it into that shift because it will often
8610          allow other simplifications.  */
8611
8612       if (code == ASHIFTRT
8613           && (count + num_sign_bit_copies (varop, shift_mode)
8614               >= GET_MODE_BITSIZE (shift_mode)))
8615         count = GET_MODE_BITSIZE (shift_mode) - 1;
8616
8617       /* We simplify the tests below and elsewhere by converting
8618          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8619          `make_compound_operation' will convert it to an ASHIFTRT for
8620          those machines (such as VAX) that don't have an LSHIFTRT.  */
8621       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8622           && code == ASHIFTRT
8623           && ((nonzero_bits (varop, shift_mode)
8624                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8625               == 0))
8626         code = LSHIFTRT;
8627
8628       if (code == LSHIFTRT
8629           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8630           && !(nonzero_bits (varop, shift_mode) >> count))
8631         varop = const0_rtx;
8632       if (code == ASHIFT
8633           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8634           && !((nonzero_bits (varop, shift_mode) << count)
8635                & GET_MODE_MASK (shift_mode)))
8636         varop = const0_rtx;
8637
8638       switch (GET_CODE (varop))
8639         {
8640         case SIGN_EXTEND:
8641         case ZERO_EXTEND:
8642         case SIGN_EXTRACT:
8643         case ZERO_EXTRACT:
8644           new = expand_compound_operation (varop);
8645           if (new != varop)
8646             {
8647               varop = new;
8648               continue;
8649             }
8650           break;
8651
8652         case MEM:
8653           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8654              minus the width of a smaller mode, we can do this with a
8655              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8656           if ((code == ASHIFTRT || code == LSHIFTRT)
8657               && ! mode_dependent_address_p (XEXP (varop, 0))
8658               && ! MEM_VOLATILE_P (varop)
8659               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8660                                          MODE_INT, 1)) != BLKmode)
8661             {
8662               new = adjust_address_nv (varop, tmode,
8663                                        BYTES_BIG_ENDIAN ? 0
8664                                        : count / BITS_PER_UNIT);
8665
8666               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8667                                      : ZERO_EXTEND, mode, new);
8668               count = 0;
8669               continue;
8670             }
8671           break;
8672
8673         case SUBREG:
8674           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8675              the same number of words as what we've seen so far.  Then store
8676              the widest mode in MODE.  */
8677           if (subreg_lowpart_p (varop)
8678               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8679                   > GET_MODE_SIZE (GET_MODE (varop)))
8680               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8681                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8682                  == mode_words)
8683             {
8684               varop = SUBREG_REG (varop);
8685               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8686                 mode = GET_MODE (varop);
8687               continue;
8688             }
8689           break;
8690
8691         case MULT:
8692           /* Some machines use MULT instead of ASHIFT because MULT
8693              is cheaper.  But it is still better on those machines to
8694              merge two shifts into one.  */
8695           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8696               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8697             {
8698               varop
8699                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8700                                        XEXP (varop, 0),
8701                                        GEN_INT (exact_log2 (
8702                                                 INTVAL (XEXP (varop, 1)))));
8703               continue;
8704             }
8705           break;
8706
8707         case UDIV:
8708           /* Similar, for when divides are cheaper.  */
8709           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8710               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8711             {
8712               varop
8713                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8714                                        XEXP (varop, 0),
8715                                        GEN_INT (exact_log2 (
8716                                                 INTVAL (XEXP (varop, 1)))));
8717               continue;
8718             }
8719           break;
8720
8721         case ASHIFTRT:
8722           /* If we are extracting just the sign bit of an arithmetic
8723              right shift, that shift is not needed.  However, the sign
8724              bit of a wider mode may be different from what would be
8725              interpreted as the sign bit in a narrower mode, so, if
8726              the result is narrower, don't discard the shift.  */
8727           if (code == LSHIFTRT
8728               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8729               && (GET_MODE_BITSIZE (result_mode)
8730                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8731             {
8732               varop = XEXP (varop, 0);
8733               continue;
8734             }
8735
8736           /* ... fall through ...  */
8737
8738         case LSHIFTRT:
8739         case ASHIFT:
8740         case ROTATE:
8741           /* Here we have two nested shifts.  The result is usually the
8742              AND of a new shift with a mask.  We compute the result below.  */
8743           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8744               && INTVAL (XEXP (varop, 1)) >= 0
8745               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8746               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8747               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8748               && !VECTOR_MODE_P (result_mode))
8749             {
8750               enum rtx_code first_code = GET_CODE (varop);
8751               unsigned int first_count = INTVAL (XEXP (varop, 1));
8752               unsigned HOST_WIDE_INT mask;
8753               rtx mask_rtx;
8754
8755               /* We have one common special case.  We can't do any merging if
8756                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8757                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8758                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8759                  we can convert it to
8760                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8761                  This simplifies certain SIGN_EXTEND operations.  */
8762               if (code == ASHIFT && first_code == ASHIFTRT
8763                   && count == (GET_MODE_BITSIZE (result_mode)
8764                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8765                 {
8766                   /* C3 has the low-order C1 bits zero.  */
8767
8768                   mask = (GET_MODE_MASK (mode)
8769                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8770
8771                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8772                                                   XEXP (varop, 0), mask);
8773                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8774                                                 varop, count);
8775                   count = first_count;
8776                   code = ASHIFTRT;
8777                   continue;
8778                 }
8779
8780               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8781                  than C1 high-order bits equal to the sign bit, we can convert
8782                  this to either an ASHIFT or an ASHIFTRT depending on the
8783                  two counts.
8784
8785                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8786
8787               if (code == ASHIFTRT && first_code == ASHIFT
8788                   && GET_MODE (varop) == shift_mode
8789                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8790                       > first_count))
8791                 {
8792                   varop = XEXP (varop, 0);
8793                   count -= first_count;
8794                   if (count < 0)
8795                     {
8796                       count = -count;
8797                       code = ASHIFT;
8798                     }
8799
8800                   continue;
8801                 }
8802
8803               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8804                  we can only do this if FIRST_CODE is also ASHIFTRT.
8805
8806                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8807                  ASHIFTRT.
8808
8809                  If the mode of this shift is not the mode of the outer shift,
8810                  we can't do this if either shift is a right shift or ROTATE.
8811
8812                  Finally, we can't do any of these if the mode is too wide
8813                  unless the codes are the same.
8814
8815                  Handle the case where the shift codes are the same
8816                  first.  */
8817
8818               if (code == first_code)
8819                 {
8820                   if (GET_MODE (varop) != result_mode
8821                       && (code == ASHIFTRT || code == LSHIFTRT
8822                           || code == ROTATE))
8823                     break;
8824
8825                   count += first_count;
8826                   varop = XEXP (varop, 0);
8827                   continue;
8828                 }
8829
8830               if (code == ASHIFTRT
8831                   || (code == ROTATE && first_code == ASHIFTRT)
8832                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8833                   || (GET_MODE (varop) != result_mode
8834                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8835                           || first_code == ROTATE
8836                           || code == ROTATE)))
8837                 break;
8838
8839               /* To compute the mask to apply after the shift, shift the
8840                  nonzero bits of the inner shift the same way the
8841                  outer shift will.  */
8842
8843               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8844
8845               mask_rtx
8846                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8847                                                    GEN_INT (count));
8848
8849               /* Give up if we can't compute an outer operation to use.  */
8850               if (mask_rtx == 0
8851                   || GET_CODE (mask_rtx) != CONST_INT
8852                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8853                                         INTVAL (mask_rtx),
8854                                         result_mode, &complement_p))
8855                 break;
8856
8857               /* If the shifts are in the same direction, we add the
8858                  counts.  Otherwise, we subtract them.  */
8859               if ((code == ASHIFTRT || code == LSHIFTRT)
8860                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8861                 count += first_count;
8862               else
8863                 count -= first_count;
8864
8865               /* If COUNT is positive, the new shift is usually CODE,
8866                  except for the two exceptions below, in which case it is
8867                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8868                  always be used  */
8869               if (count > 0
8870                   && ((first_code == ROTATE && code == ASHIFT)
8871                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8872                 code = first_code;
8873               else if (count < 0)
8874                 code = first_code, count = -count;
8875
8876               varop = XEXP (varop, 0);
8877               continue;
8878             }
8879
8880           /* If we have (A << B << C) for any shift, we can convert this to
8881              (A << C << B).  This wins if A is a constant.  Only try this if
8882              B is not a constant.  */
8883
8884           else if (GET_CODE (varop) == code
8885                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8886                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8887             {
8888               rtx new = simplify_const_binary_operation (code, mode,
8889                                                          XEXP (varop, 0),
8890                                                          GEN_INT (count));
8891               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8892               count = 0;
8893               continue;
8894             }
8895           break;
8896
8897         case NOT:
8898           /* Make this fit the case below.  */
8899           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8900                                GEN_INT (GET_MODE_MASK (mode)));
8901           continue;
8902
8903         case IOR:
8904         case AND:
8905         case XOR:
8906           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8907              with C the size of VAROP - 1 and the shift is logical if
8908              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8909              we have an (le X 0) operation.   If we have an arithmetic shift
8910              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8911              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8912
8913           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8914               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8915               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8916               && (code == LSHIFTRT || code == ASHIFTRT)
8917               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8918               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8919             {
8920               count = 0;
8921               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8922                                   const0_rtx);
8923
8924               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8925                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8926
8927               continue;
8928             }
8929
8930           /* If we have (shift (logical)), move the logical to the outside
8931              to allow it to possibly combine with another logical and the
8932              shift to combine with another shift.  This also canonicalizes to
8933              what a ZERO_EXTRACT looks like.  Also, some machines have
8934              (and (shift)) insns.  */
8935
8936           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8937               /* We can't do this if we have (ashiftrt (xor))  and the
8938                  constant has its sign bit set in shift_mode.  */
8939               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8940                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8941                                               shift_mode))
8942               && (new = simplify_const_binary_operation (code, result_mode,
8943                                                          XEXP (varop, 1),
8944                                                          GEN_INT (count))) != 0
8945               && GET_CODE (new) == CONST_INT
8946               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8947                                   INTVAL (new), result_mode, &complement_p))
8948             {
8949               varop = XEXP (varop, 0);
8950               continue;
8951             }
8952
8953           /* If we can't do that, try to simplify the shift in each arm of the
8954              logical expression, make a new logical expression, and apply
8955              the inverse distributive law.  This also can't be done
8956              for some (ashiftrt (xor)).  */
8957           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8958              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8959                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8960                                              shift_mode)))
8961             {
8962               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8963                                               XEXP (varop, 0), count);
8964               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8965                                               XEXP (varop, 1), count);
8966
8967               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8968                                            lhs, rhs);
8969               varop = apply_distributive_law (varop);
8970
8971               count = 0;
8972               continue;
8973             }
8974           break;
8975
8976         case EQ:
8977           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8978              says that the sign bit can be tested, FOO has mode MODE, C is
8979              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8980              that may be nonzero.  */
8981           if (code == LSHIFTRT
8982               && XEXP (varop, 1) == const0_rtx
8983               && GET_MODE (XEXP (varop, 0)) == result_mode
8984               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8985               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8986               && STORE_FLAG_VALUE == -1
8987               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8988               && merge_outer_ops (&outer_op, &outer_const, XOR,
8989                                   (HOST_WIDE_INT) 1, result_mode,
8990                                   &complement_p))
8991             {
8992               varop = XEXP (varop, 0);
8993               count = 0;
8994               continue;
8995             }
8996           break;
8997
8998         case NEG:
8999           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9000              than the number of bits in the mode is equivalent to A.  */
9001           if (code == LSHIFTRT
9002               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9003               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9004             {
9005               varop = XEXP (varop, 0);
9006               count = 0;
9007               continue;
9008             }
9009
9010           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9011              NEG outside to allow shifts to combine.  */
9012           if (code == ASHIFT
9013               && merge_outer_ops (&outer_op, &outer_const, NEG,
9014                                   (HOST_WIDE_INT) 0, result_mode,
9015                                   &complement_p))
9016             {
9017               varop = XEXP (varop, 0);
9018               continue;
9019             }
9020           break;
9021
9022         case PLUS:
9023           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9024              is one less than the number of bits in the mode is
9025              equivalent to (xor A 1).  */
9026           if (code == LSHIFTRT
9027               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9028               && XEXP (varop, 1) == constm1_rtx
9029               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9030               && merge_outer_ops (&outer_op, &outer_const, XOR,
9031                                   (HOST_WIDE_INT) 1, result_mode,
9032                                   &complement_p))
9033             {
9034               count = 0;
9035               varop = XEXP (varop, 0);
9036               continue;
9037             }
9038
9039           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9040              that might be nonzero in BAR are those being shifted out and those
9041              bits are known zero in FOO, we can replace the PLUS with FOO.
9042              Similarly in the other operand order.  This code occurs when
9043              we are computing the size of a variable-size array.  */
9044
9045           if ((code == ASHIFTRT || code == LSHIFTRT)
9046               && count < HOST_BITS_PER_WIDE_INT
9047               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9048               && (nonzero_bits (XEXP (varop, 1), result_mode)
9049                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9050             {
9051               varop = XEXP (varop, 0);
9052               continue;
9053             }
9054           else if ((code == ASHIFTRT || code == LSHIFTRT)
9055                    && count < HOST_BITS_PER_WIDE_INT
9056                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9057                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9058                             >> count)
9059                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9060                             & nonzero_bits (XEXP (varop, 1),
9061                                                  result_mode)))
9062             {
9063               varop = XEXP (varop, 1);
9064               continue;
9065             }
9066
9067           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9068           if (code == ASHIFT
9069               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9070               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9071                                                          XEXP (varop, 1),
9072                                                          GEN_INT (count))) != 0
9073               && GET_CODE (new) == CONST_INT
9074               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9075                                   INTVAL (new), result_mode, &complement_p))
9076             {
9077               varop = XEXP (varop, 0);
9078               continue;
9079             }
9080
9081           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9082              signbit', and attempt to change the PLUS to an XOR and move it to
9083              the outer operation as is done above in the AND/IOR/XOR case
9084              leg for shift(logical). See details in logical handling above
9085              for reasoning in doing so.  */
9086           if (code == LSHIFTRT
9087               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9088               && mode_signbit_p (result_mode, XEXP (varop, 1))
9089               && (new = simplify_const_binary_operation (code, result_mode,
9090                                                          XEXP (varop, 1),
9091                                                          GEN_INT (count))) != 0
9092               && GET_CODE (new) == CONST_INT
9093               && merge_outer_ops (&outer_op, &outer_const, XOR,
9094                                   INTVAL (new), result_mode, &complement_p))
9095             {
9096               varop = XEXP (varop, 0);
9097               continue;
9098             }
9099
9100           break;
9101
9102         case MINUS:
9103           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9104              with C the size of VAROP - 1 and the shift is logical if
9105              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9106              we have a (gt X 0) operation.  If the shift is arithmetic with
9107              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9108              we have a (neg (gt X 0)) operation.  */
9109
9110           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9111               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9112               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9113               && (code == LSHIFTRT || code == ASHIFTRT)
9114               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9115               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9116               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9117             {
9118               count = 0;
9119               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9120                                   const0_rtx);
9121
9122               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9123                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9124
9125               continue;
9126             }
9127           break;
9128
9129         case TRUNCATE:
9130           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9131              if the truncate does not affect the value.  */
9132           if (code == LSHIFTRT
9133               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9134               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9135               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9136                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9137                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9138             {
9139               rtx varop_inner = XEXP (varop, 0);
9140
9141               varop_inner
9142                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9143                                     XEXP (varop_inner, 0),
9144                                     GEN_INT
9145                                     (count + INTVAL (XEXP (varop_inner, 1))));
9146               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9147               count = 0;
9148               continue;
9149             }
9150           break;
9151
9152         default:
9153           break;
9154         }
9155
9156       break;
9157     }
9158
9159   /* We need to determine what mode to do the shift in.  If the shift is
9160      a right shift or ROTATE, we must always do it in the mode it was
9161      originally done in.  Otherwise, we can do it in MODE, the widest mode
9162      encountered.  The code we care about is that of the shift that will
9163      actually be done, not the shift that was originally requested.  */
9164   shift_mode
9165     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9166        ? result_mode : mode);
9167
9168   /* We have now finished analyzing the shift.  The result should be
9169      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9170      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9171      to the result of the shift.  OUTER_CONST is the relevant constant,
9172      but we must turn off all bits turned off in the shift.  */
9173
9174   if (outer_op == UNKNOWN
9175       && orig_code == code && orig_count == count
9176       && varop == orig_varop
9177       && shift_mode == GET_MODE (varop))
9178     return NULL_RTX;
9179
9180   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9181   varop = gen_lowpart (shift_mode, varop);
9182   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9183     return NULL_RTX;
9184
9185   /* If we have an outer operation and we just made a shift, it is
9186      possible that we could have simplified the shift were it not
9187      for the outer operation.  So try to do the simplification
9188      recursively.  */
9189
9190   if (outer_op != UNKNOWN)
9191     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9192   else
9193     x = NULL_RTX;
9194
9195   if (x == NULL_RTX)
9196     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9197
9198   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9199      turn off all the bits that the shift would have turned off.  */
9200   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9201     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9202                                 GET_MODE_MASK (result_mode) >> orig_count);
9203
9204   /* Do the remainder of the processing in RESULT_MODE.  */
9205   x = gen_lowpart_or_truncate (result_mode, x);
9206
9207   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9208      operation.  */
9209   if (complement_p)
9210     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9211
9212   if (outer_op != UNKNOWN)
9213     {
9214       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9215         outer_const = trunc_int_for_mode (outer_const, result_mode);
9216
9217       if (outer_op == AND)
9218         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9219       else if (outer_op == SET)
9220         /* This means that we have determined that the result is
9221            equivalent to a constant.  This should be rare.  */
9222         x = GEN_INT (outer_const);
9223       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9224         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9225       else
9226         x = simplify_gen_binary (outer_op, result_mode, x,
9227                                  GEN_INT (outer_const));
9228     }
9229
9230   return x;
9231 }
9232
9233 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9234    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9235    return X or, if it is NULL, synthesize the expression with
9236    simplify_gen_binary.  Otherwise, return a simplified value.
9237
9238    The shift is normally computed in the widest mode we find in VAROP, as
9239    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9240    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9241
9242 static rtx
9243 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9244                       rtx varop, int count)
9245 {
9246   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9247   if (tem)
9248     return tem;
9249
9250   if (!x)
9251     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9252   if (GET_MODE (x) != result_mode)
9253     x = gen_lowpart (result_mode, x);
9254   return x;
9255 }
9256
9257 \f
9258 /* Like recog, but we receive the address of a pointer to a new pattern.
9259    We try to match the rtx that the pointer points to.
9260    If that fails, we may try to modify or replace the pattern,
9261    storing the replacement into the same pointer object.
9262
9263    Modifications include deletion or addition of CLOBBERs.
9264
9265    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9266    the CLOBBERs are placed.
9267
9268    The value is the final insn code from the pattern ultimately matched,
9269    or -1.  */
9270
9271 static int
9272 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9273 {
9274   rtx pat = *pnewpat;
9275   int insn_code_number;
9276   int num_clobbers_to_add = 0;
9277   int i;
9278   rtx notes = 0;
9279   rtx old_notes, old_pat;
9280
9281   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9282      we use to indicate that something didn't match.  If we find such a
9283      thing, force rejection.  */
9284   if (GET_CODE (pat) == PARALLEL)
9285     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9286       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9287           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9288         return -1;
9289
9290   old_pat = PATTERN (insn);
9291   old_notes = REG_NOTES (insn);
9292   PATTERN (insn) = pat;
9293   REG_NOTES (insn) = 0;
9294
9295   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9296
9297   /* If it isn't, there is the possibility that we previously had an insn
9298      that clobbered some register as a side effect, but the combined
9299      insn doesn't need to do that.  So try once more without the clobbers
9300      unless this represents an ASM insn.  */
9301
9302   if (insn_code_number < 0 && ! check_asm_operands (pat)
9303       && GET_CODE (pat) == PARALLEL)
9304     {
9305       int pos;
9306
9307       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9308         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9309           {
9310             if (i != pos)
9311               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9312             pos++;
9313           }
9314
9315       SUBST_INT (XVECLEN (pat, 0), pos);
9316
9317       if (pos == 1)
9318         pat = XVECEXP (pat, 0, 0);
9319
9320       PATTERN (insn) = pat;
9321       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9322     }
9323   PATTERN (insn) = old_pat;
9324   REG_NOTES (insn) = old_notes;
9325
9326   /* Recognize all noop sets, these will be killed by followup pass.  */
9327   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9328     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9329
9330   /* If we had any clobbers to add, make a new pattern than contains
9331      them.  Then check to make sure that all of them are dead.  */
9332   if (num_clobbers_to_add)
9333     {
9334       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9335                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9336                                                   ? (XVECLEN (pat, 0)
9337                                                      + num_clobbers_to_add)
9338                                                   : num_clobbers_to_add + 1));
9339
9340       if (GET_CODE (pat) == PARALLEL)
9341         for (i = 0; i < XVECLEN (pat, 0); i++)
9342           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9343       else
9344         XVECEXP (newpat, 0, 0) = pat;
9345
9346       add_clobbers (newpat, insn_code_number);
9347
9348       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9349            i < XVECLEN (newpat, 0); i++)
9350         {
9351           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9352               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9353             return -1;
9354           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9355                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9356         }
9357       pat = newpat;
9358     }
9359
9360   *pnewpat = pat;
9361   *pnotes = notes;
9362
9363   return insn_code_number;
9364 }
9365 \f
9366 /* Like gen_lowpart_general but for use by combine.  In combine it
9367    is not possible to create any new pseudoregs.  However, it is
9368    safe to create invalid memory addresses, because combine will
9369    try to recognize them and all they will do is make the combine
9370    attempt fail.
9371
9372    If for some reason this cannot do its job, an rtx
9373    (clobber (const_int 0)) is returned.
9374    An insn containing that will not be recognized.  */
9375
9376 static rtx
9377 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9378 {
9379   enum machine_mode imode = GET_MODE (x);
9380   unsigned int osize = GET_MODE_SIZE (omode);
9381   unsigned int isize = GET_MODE_SIZE (imode);
9382   rtx result;
9383
9384   if (omode == imode)
9385     return x;
9386
9387   /* Return identity if this is a CONST or symbolic reference.  */
9388   if (omode == Pmode
9389       && (GET_CODE (x) == CONST
9390           || GET_CODE (x) == SYMBOL_REF
9391           || GET_CODE (x) == LABEL_REF))
9392     return x;
9393
9394   /* We can only support MODE being wider than a word if X is a
9395      constant integer or has a mode the same size.  */
9396   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9397       && ! ((imode == VOIDmode
9398              && (GET_CODE (x) == CONST_INT
9399                  || GET_CODE (x) == CONST_DOUBLE))
9400             || isize == osize))
9401     goto fail;
9402
9403   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9404      won't know what to do.  So we will strip off the SUBREG here and
9405      process normally.  */
9406   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9407     {
9408       x = SUBREG_REG (x);
9409
9410       /* For use in case we fall down into the address adjustments
9411          further below, we need to adjust the known mode and size of
9412          x; imode and isize, since we just adjusted x.  */
9413       imode = GET_MODE (x);
9414
9415       if (imode == omode)
9416         return x;
9417
9418       isize = GET_MODE_SIZE (imode);
9419     }
9420
9421   result = gen_lowpart_common (omode, x);
9422
9423 #ifdef CANNOT_CHANGE_MODE_CLASS
9424   if (result != 0 && GET_CODE (result) == SUBREG)
9425     record_subregs_of_mode (result);
9426 #endif
9427
9428   if (result)
9429     return result;
9430
9431   if (MEM_P (x))
9432     {
9433       int offset = 0;
9434
9435       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9436          address.  */
9437       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9438         goto fail;
9439
9440       /* If we want to refer to something bigger than the original memref,
9441          generate a paradoxical subreg instead.  That will force a reload
9442          of the original memref X.  */
9443       if (isize < osize)
9444         return gen_rtx_SUBREG (omode, x, 0);
9445
9446       if (WORDS_BIG_ENDIAN)
9447         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9448
9449       /* Adjust the address so that the address-after-the-data is
9450          unchanged.  */
9451       if (BYTES_BIG_ENDIAN)
9452         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9453
9454       return adjust_address_nv (x, omode, offset);
9455     }
9456
9457   /* If X is a comparison operator, rewrite it in a new mode.  This
9458      probably won't match, but may allow further simplifications.  */
9459   else if (COMPARISON_P (x))
9460     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9461
9462   /* If we couldn't simplify X any other way, just enclose it in a
9463      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9464      include an explicit SUBREG or we may simplify it further in combine.  */
9465   else
9466     {
9467       int offset = 0;
9468       rtx res;
9469
9470       offset = subreg_lowpart_offset (omode, imode);
9471       if (imode == VOIDmode)
9472         {
9473           imode = int_mode_for_mode (omode);
9474           x = gen_lowpart_common (imode, x);
9475           if (x == NULL)
9476             goto fail;
9477         }
9478       res = simplify_gen_subreg (omode, x, imode, offset);
9479       if (res)
9480         return res;
9481     }
9482
9483  fail:
9484   return gen_rtx_CLOBBER (imode, const0_rtx);
9485 }
9486 \f
9487 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9488    comparison code that will be tested.
9489
9490    The result is a possibly different comparison code to use.  *POP0 and
9491    *POP1 may be updated.
9492
9493    It is possible that we might detect that a comparison is either always
9494    true or always false.  However, we do not perform general constant
9495    folding in combine, so this knowledge isn't useful.  Such tautologies
9496    should have been detected earlier.  Hence we ignore all such cases.  */
9497
9498 static enum rtx_code
9499 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9500 {
9501   rtx op0 = *pop0;
9502   rtx op1 = *pop1;
9503   rtx tem, tem1;
9504   int i;
9505   enum machine_mode mode, tmode;
9506
9507   /* Try a few ways of applying the same transformation to both operands.  */
9508   while (1)
9509     {
9510 #ifndef WORD_REGISTER_OPERATIONS
9511       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9512          so check specially.  */
9513       if (code != GTU && code != GEU && code != LTU && code != LEU
9514           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9515           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9516           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9517           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9518           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9519           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9520               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9521           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9522           && XEXP (op0, 1) == XEXP (op1, 1)
9523           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9524           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9525           && (INTVAL (XEXP (op0, 1))
9526               == (GET_MODE_BITSIZE (GET_MODE (op0))
9527                   - (GET_MODE_BITSIZE
9528                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9529         {
9530           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9531           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9532         }
9533 #endif
9534
9535       /* If both operands are the same constant shift, see if we can ignore the
9536          shift.  We can if the shift is a rotate or if the bits shifted out of
9537          this shift are known to be zero for both inputs and if the type of
9538          comparison is compatible with the shift.  */
9539       if (GET_CODE (op0) == GET_CODE (op1)
9540           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9541           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9542               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9543                   && (code != GT && code != LT && code != GE && code != LE))
9544               || (GET_CODE (op0) == ASHIFTRT
9545                   && (code != GTU && code != LTU
9546                       && code != GEU && code != LEU)))
9547           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9548           && INTVAL (XEXP (op0, 1)) >= 0
9549           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9550           && XEXP (op0, 1) == XEXP (op1, 1))
9551         {
9552           enum machine_mode mode = GET_MODE (op0);
9553           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9554           int shift_count = INTVAL (XEXP (op0, 1));
9555
9556           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9557             mask &= (mask >> shift_count) << shift_count;
9558           else if (GET_CODE (op0) == ASHIFT)
9559             mask = (mask & (mask << shift_count)) >> shift_count;
9560
9561           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9562               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9563             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9564           else
9565             break;
9566         }
9567
9568       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9569          SUBREGs are of the same mode, and, in both cases, the AND would
9570          be redundant if the comparison was done in the narrower mode,
9571          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9572          and the operand's possibly nonzero bits are 0xffffff01; in that case
9573          if we only care about QImode, we don't need the AND).  This case
9574          occurs if the output mode of an scc insn is not SImode and
9575          STORE_FLAG_VALUE == 1 (e.g., the 386).
9576
9577          Similarly, check for a case where the AND's are ZERO_EXTEND
9578          operations from some narrower mode even though a SUBREG is not
9579          present.  */
9580
9581       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9582                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9583                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9584         {
9585           rtx inner_op0 = XEXP (op0, 0);
9586           rtx inner_op1 = XEXP (op1, 0);
9587           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9588           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9589           int changed = 0;
9590
9591           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9592               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9593                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9594               && (GET_MODE (SUBREG_REG (inner_op0))
9595                   == GET_MODE (SUBREG_REG (inner_op1)))
9596               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9597                   <= HOST_BITS_PER_WIDE_INT)
9598               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9599                                              GET_MODE (SUBREG_REG (inner_op0)))))
9600               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9601                                              GET_MODE (SUBREG_REG (inner_op1))))))
9602             {
9603               op0 = SUBREG_REG (inner_op0);
9604               op1 = SUBREG_REG (inner_op1);
9605
9606               /* The resulting comparison is always unsigned since we masked
9607                  off the original sign bit.  */
9608               code = unsigned_condition (code);
9609
9610               changed = 1;
9611             }
9612
9613           else if (c0 == c1)
9614             for (tmode = GET_CLASS_NARROWEST_MODE
9615                  (GET_MODE_CLASS (GET_MODE (op0)));
9616                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9617               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9618                 {
9619                   op0 = gen_lowpart (tmode, inner_op0);
9620                   op1 = gen_lowpart (tmode, inner_op1);
9621                   code = unsigned_condition (code);
9622                   changed = 1;
9623                   break;
9624                 }
9625
9626           if (! changed)
9627             break;
9628         }
9629
9630       /* If both operands are NOT, we can strip off the outer operation
9631          and adjust the comparison code for swapped operands; similarly for
9632          NEG, except that this must be an equality comparison.  */
9633       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9634                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9635                    && (code == EQ || code == NE)))
9636         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9637
9638       else
9639         break;
9640     }
9641
9642   /* If the first operand is a constant, swap the operands and adjust the
9643      comparison code appropriately, but don't do this if the second operand
9644      is already a constant integer.  */
9645   if (swap_commutative_operands_p (op0, op1))
9646     {
9647       tem = op0, op0 = op1, op1 = tem;
9648       code = swap_condition (code);
9649     }
9650
9651   /* We now enter a loop during which we will try to simplify the comparison.
9652      For the most part, we only are concerned with comparisons with zero,
9653      but some things may really be comparisons with zero but not start
9654      out looking that way.  */
9655
9656   while (GET_CODE (op1) == CONST_INT)
9657     {
9658       enum machine_mode mode = GET_MODE (op0);
9659       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9660       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9661       int equality_comparison_p;
9662       int sign_bit_comparison_p;
9663       int unsigned_comparison_p;
9664       HOST_WIDE_INT const_op;
9665
9666       /* We only want to handle integral modes.  This catches VOIDmode,
9667          CCmode, and the floating-point modes.  An exception is that we
9668          can handle VOIDmode if OP0 is a COMPARE or a comparison
9669          operation.  */
9670
9671       if (GET_MODE_CLASS (mode) != MODE_INT
9672           && ! (mode == VOIDmode
9673                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9674         break;
9675
9676       /* Get the constant we are comparing against and turn off all bits
9677          not on in our mode.  */
9678       const_op = INTVAL (op1);
9679       if (mode != VOIDmode)
9680         const_op = trunc_int_for_mode (const_op, mode);
9681       op1 = GEN_INT (const_op);
9682
9683       /* If we are comparing against a constant power of two and the value
9684          being compared can only have that single bit nonzero (e.g., it was
9685          `and'ed with that bit), we can replace this with a comparison
9686          with zero.  */
9687       if (const_op
9688           && (code == EQ || code == NE || code == GE || code == GEU
9689               || code == LT || code == LTU)
9690           && mode_width <= HOST_BITS_PER_WIDE_INT
9691           && exact_log2 (const_op) >= 0
9692           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9693         {
9694           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9695           op1 = const0_rtx, const_op = 0;
9696         }
9697
9698       /* Similarly, if we are comparing a value known to be either -1 or
9699          0 with -1, change it to the opposite comparison against zero.  */
9700
9701       if (const_op == -1
9702           && (code == EQ || code == NE || code == GT || code == LE
9703               || code == GEU || code == LTU)
9704           && num_sign_bit_copies (op0, mode) == mode_width)
9705         {
9706           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9707           op1 = const0_rtx, const_op = 0;
9708         }
9709
9710       /* Do some canonicalizations based on the comparison code.  We prefer
9711          comparisons against zero and then prefer equality comparisons.
9712          If we can reduce the size of a constant, we will do that too.  */
9713
9714       switch (code)
9715         {
9716         case LT:
9717           /* < C is equivalent to <= (C - 1) */
9718           if (const_op > 0)
9719             {
9720               const_op -= 1;
9721               op1 = GEN_INT (const_op);
9722               code = LE;
9723               /* ... fall through to LE case below.  */
9724             }
9725           else
9726             break;
9727
9728         case LE:
9729           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9730           if (const_op < 0)
9731             {
9732               const_op += 1;
9733               op1 = GEN_INT (const_op);
9734               code = LT;
9735             }
9736
9737           /* If we are doing a <= 0 comparison on a value known to have
9738              a zero sign bit, we can replace this with == 0.  */
9739           else if (const_op == 0
9740                    && mode_width <= HOST_BITS_PER_WIDE_INT
9741                    && (nonzero_bits (op0, mode)
9742                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9743             code = EQ;
9744           break;
9745
9746         case GE:
9747           /* >= C is equivalent to > (C - 1).  */
9748           if (const_op > 0)
9749             {
9750               const_op -= 1;
9751               op1 = GEN_INT (const_op);
9752               code = GT;
9753               /* ... fall through to GT below.  */
9754             }
9755           else
9756             break;
9757
9758         case GT:
9759           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9760           if (const_op < 0)
9761             {
9762               const_op += 1;
9763               op1 = GEN_INT (const_op);
9764               code = GE;
9765             }
9766
9767           /* If we are doing a > 0 comparison on a value known to have
9768              a zero sign bit, we can replace this with != 0.  */
9769           else if (const_op == 0
9770                    && mode_width <= HOST_BITS_PER_WIDE_INT
9771                    && (nonzero_bits (op0, mode)
9772                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9773             code = NE;
9774           break;
9775
9776         case LTU:
9777           /* < C is equivalent to <= (C - 1).  */
9778           if (const_op > 0)
9779             {
9780               const_op -= 1;
9781               op1 = GEN_INT (const_op);
9782               code = LEU;
9783               /* ... fall through ...  */
9784             }
9785
9786           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9787           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9788                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9789             {
9790               const_op = 0, op1 = const0_rtx;
9791               code = GE;
9792               break;
9793             }
9794           else
9795             break;
9796
9797         case LEU:
9798           /* unsigned <= 0 is equivalent to == 0 */
9799           if (const_op == 0)
9800             code = EQ;
9801
9802           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9803           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9804                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9805             {
9806               const_op = 0, op1 = const0_rtx;
9807               code = GE;
9808             }
9809           break;
9810
9811         case GEU:
9812           /* >= C is equivalent to > (C - 1).  */
9813           if (const_op > 1)
9814             {
9815               const_op -= 1;
9816               op1 = GEN_INT (const_op);
9817               code = GTU;
9818               /* ... fall through ...  */
9819             }
9820
9821           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9822           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9823                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9824             {
9825               const_op = 0, op1 = const0_rtx;
9826               code = LT;
9827               break;
9828             }
9829           else
9830             break;
9831
9832         case GTU:
9833           /* unsigned > 0 is equivalent to != 0 */
9834           if (const_op == 0)
9835             code = NE;
9836
9837           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9838           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9839                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9840             {
9841               const_op = 0, op1 = const0_rtx;
9842               code = LT;
9843             }
9844           break;
9845
9846         default:
9847           break;
9848         }
9849
9850       /* Compute some predicates to simplify code below.  */
9851
9852       equality_comparison_p = (code == EQ || code == NE);
9853       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9854       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9855                                || code == GEU);
9856
9857       /* If this is a sign bit comparison and we can do arithmetic in
9858          MODE, say that we will only be needing the sign bit of OP0.  */
9859       if (sign_bit_comparison_p
9860           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9861         op0 = force_to_mode (op0, mode,
9862                              ((HOST_WIDE_INT) 1
9863                               << (GET_MODE_BITSIZE (mode) - 1)),
9864                              0);
9865
9866       /* Now try cases based on the opcode of OP0.  If none of the cases
9867          does a "continue", we exit this loop immediately after the
9868          switch.  */
9869
9870       switch (GET_CODE (op0))
9871         {
9872         case ZERO_EXTRACT:
9873           /* If we are extracting a single bit from a variable position in
9874              a constant that has only a single bit set and are comparing it
9875              with zero, we can convert this into an equality comparison
9876              between the position and the location of the single bit.  */
9877           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9878              have already reduced the shift count modulo the word size.  */
9879           if (!SHIFT_COUNT_TRUNCATED
9880               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9881               && XEXP (op0, 1) == const1_rtx
9882               && equality_comparison_p && const_op == 0
9883               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9884             {
9885               if (BITS_BIG_ENDIAN)
9886                 {
9887                   enum machine_mode new_mode
9888                     = mode_for_extraction (EP_extzv, 1);
9889                   if (new_mode == MAX_MACHINE_MODE)
9890                     i = BITS_PER_WORD - 1 - i;
9891                   else
9892                     {
9893                       mode = new_mode;
9894                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9895                     }
9896                 }
9897
9898               op0 = XEXP (op0, 2);
9899               op1 = GEN_INT (i);
9900               const_op = i;
9901
9902               /* Result is nonzero iff shift count is equal to I.  */
9903               code = reverse_condition (code);
9904               continue;
9905             }
9906
9907           /* ... fall through ...  */
9908
9909         case SIGN_EXTRACT:
9910           tem = expand_compound_operation (op0);
9911           if (tem != op0)
9912             {
9913               op0 = tem;
9914               continue;
9915             }
9916           break;
9917
9918         case NOT:
9919           /* If testing for equality, we can take the NOT of the constant.  */
9920           if (equality_comparison_p
9921               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9922             {
9923               op0 = XEXP (op0, 0);
9924               op1 = tem;
9925               continue;
9926             }
9927
9928           /* If just looking at the sign bit, reverse the sense of the
9929              comparison.  */
9930           if (sign_bit_comparison_p)
9931             {
9932               op0 = XEXP (op0, 0);
9933               code = (code == GE ? LT : GE);
9934               continue;
9935             }
9936           break;
9937
9938         case NEG:
9939           /* If testing for equality, we can take the NEG of the constant.  */
9940           if (equality_comparison_p
9941               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9942             {
9943               op0 = XEXP (op0, 0);
9944               op1 = tem;
9945               continue;
9946             }
9947
9948           /* The remaining cases only apply to comparisons with zero.  */
9949           if (const_op != 0)
9950             break;
9951
9952           /* When X is ABS or is known positive,
9953              (neg X) is < 0 if and only if X != 0.  */
9954
9955           if (sign_bit_comparison_p
9956               && (GET_CODE (XEXP (op0, 0)) == ABS
9957                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9958                       && (nonzero_bits (XEXP (op0, 0), mode)
9959                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9960             {
9961               op0 = XEXP (op0, 0);
9962               code = (code == LT ? NE : EQ);
9963               continue;
9964             }
9965
9966           /* If we have NEG of something whose two high-order bits are the
9967              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9968           if (num_sign_bit_copies (op0, mode) >= 2)
9969             {
9970               op0 = XEXP (op0, 0);
9971               code = swap_condition (code);
9972               continue;
9973             }
9974           break;
9975
9976         case ROTATE:
9977           /* If we are testing equality and our count is a constant, we
9978              can perform the inverse operation on our RHS.  */
9979           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9980               && (tem = simplify_binary_operation (ROTATERT, mode,
9981                                                    op1, XEXP (op0, 1))) != 0)
9982             {
9983               op0 = XEXP (op0, 0);
9984               op1 = tem;
9985               continue;
9986             }
9987
9988           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9989              a particular bit.  Convert it to an AND of a constant of that
9990              bit.  This will be converted into a ZERO_EXTRACT.  */
9991           if (const_op == 0 && sign_bit_comparison_p
9992               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9993               && mode_width <= HOST_BITS_PER_WIDE_INT)
9994             {
9995               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9996                                             ((HOST_WIDE_INT) 1
9997                                              << (mode_width - 1
9998                                                  - INTVAL (XEXP (op0, 1)))));
9999               code = (code == LT ? NE : EQ);
10000               continue;
10001             }
10002
10003           /* Fall through.  */
10004
10005         case ABS:
10006           /* ABS is ignorable inside an equality comparison with zero.  */
10007           if (const_op == 0 && equality_comparison_p)
10008             {
10009               op0 = XEXP (op0, 0);
10010               continue;
10011             }
10012           break;
10013
10014         case SIGN_EXTEND:
10015           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10016              (compare FOO CONST) if CONST fits in FOO's mode and we
10017              are either testing inequality or have an unsigned
10018              comparison with ZERO_EXTEND or a signed comparison with
10019              SIGN_EXTEND.  But don't do it if we don't have a compare
10020              insn of the given mode, since we'd have to revert it
10021              later on, and then we wouldn't know whether to sign- or
10022              zero-extend.  */
10023           mode = GET_MODE (XEXP (op0, 0));
10024           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10025               && ! unsigned_comparison_p
10026               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10027               && ((unsigned HOST_WIDE_INT) const_op
10028                   < (((unsigned HOST_WIDE_INT) 1
10029                       << (GET_MODE_BITSIZE (mode) - 1))))
10030               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10031             {
10032               op0 = XEXP (op0, 0);
10033               continue;
10034             }
10035           break;
10036
10037         case SUBREG:
10038           /* Check for the case where we are comparing A - C1 with C2, that is
10039
10040                (subreg:MODE (plus (A) (-C1))) op (C2)
10041
10042              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10043              comparison in the wider mode.  One of the following two conditions
10044              must be true in order for this to be valid:
10045
10046                1. The mode extension results in the same bit pattern being added
10047                   on both sides and the comparison is equality or unsigned.  As
10048                   C2 has been truncated to fit in MODE, the pattern can only be
10049                   all 0s or all 1s.
10050
10051                2. The mode extension results in the sign bit being copied on
10052                   each side.
10053
10054              The difficulty here is that we have predicates for A but not for
10055              (A - C1) so we need to check that C1 is within proper bounds so
10056              as to perturbate A as little as possible.  */
10057
10058           if (mode_width <= HOST_BITS_PER_WIDE_INT
10059               && subreg_lowpart_p (op0)
10060               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10061               && GET_CODE (SUBREG_REG (op0)) == PLUS
10062               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10063             {
10064               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10065               rtx a = XEXP (SUBREG_REG (op0), 0);
10066               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10067
10068               if ((c1 > 0
10069                    && (unsigned HOST_WIDE_INT) c1
10070                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10071                    && (equality_comparison_p || unsigned_comparison_p)
10072                    /* (A - C1) zero-extends if it is positive and sign-extends
10073                       if it is negative, C2 both zero- and sign-extends.  */
10074                    && ((0 == (nonzero_bits (a, inner_mode)
10075                               & ~GET_MODE_MASK (mode))
10076                         && const_op >= 0)
10077                        /* (A - C1) sign-extends if it is positive and 1-extends
10078                           if it is negative, C2 both sign- and 1-extends.  */
10079                        || (num_sign_bit_copies (a, inner_mode)
10080                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10081                                              - mode_width)
10082                            && const_op < 0)))
10083                   || ((unsigned HOST_WIDE_INT) c1
10084                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10085                       /* (A - C1) always sign-extends, like C2.  */
10086                       && num_sign_bit_copies (a, inner_mode)
10087                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10088                                            - (mode_width - 1))))
10089                 {
10090                   op0 = SUBREG_REG (op0);
10091                   continue;
10092                 }
10093             }
10094
10095           /* If the inner mode is narrower and we are extracting the low part,
10096              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10097           if (subreg_lowpart_p (op0)
10098               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10099             /* Fall through */ ;
10100           else
10101             break;
10102
10103           /* ... fall through ...  */
10104
10105         case ZERO_EXTEND:
10106           mode = GET_MODE (XEXP (op0, 0));
10107           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10108               && (unsigned_comparison_p || equality_comparison_p)
10109               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10110               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10111               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10112             {
10113               op0 = XEXP (op0, 0);
10114               continue;
10115             }
10116           break;
10117
10118         case PLUS:
10119           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10120              this for equality comparisons due to pathological cases involving
10121              overflows.  */
10122           if (equality_comparison_p
10123               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10124                                                         op1, XEXP (op0, 1))))
10125             {
10126               op0 = XEXP (op0, 0);
10127               op1 = tem;
10128               continue;
10129             }
10130
10131           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10132           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10133               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10134             {
10135               op0 = XEXP (XEXP (op0, 0), 0);
10136               code = (code == LT ? EQ : NE);
10137               continue;
10138             }
10139           break;
10140
10141         case MINUS:
10142           /* We used to optimize signed comparisons against zero, but that
10143              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10144              arrive here as equality comparisons, or (GEU, LTU) are
10145              optimized away.  No need to special-case them.  */
10146
10147           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10148              (eq B (minus A C)), whichever simplifies.  We can only do
10149              this for equality comparisons due to pathological cases involving
10150              overflows.  */
10151           if (equality_comparison_p
10152               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10153                                                         XEXP (op0, 1), op1)))
10154             {
10155               op0 = XEXP (op0, 0);
10156               op1 = tem;
10157               continue;
10158             }
10159
10160           if (equality_comparison_p
10161               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10162                                                         XEXP (op0, 0), op1)))
10163             {
10164               op0 = XEXP (op0, 1);
10165               op1 = tem;
10166               continue;
10167             }
10168
10169           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10170              of bits in X minus 1, is one iff X > 0.  */
10171           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10172               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10173               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10174                  == mode_width - 1
10175               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10176             {
10177               op0 = XEXP (op0, 1);
10178               code = (code == GE ? LE : GT);
10179               continue;
10180             }
10181           break;
10182
10183         case XOR:
10184           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10185              if C is zero or B is a constant.  */
10186           if (equality_comparison_p
10187               && 0 != (tem = simplify_binary_operation (XOR, mode,
10188                                                         XEXP (op0, 1), op1)))
10189             {
10190               op0 = XEXP (op0, 0);
10191               op1 = tem;
10192               continue;
10193             }
10194           break;
10195
10196         case EQ:  case NE:
10197         case UNEQ:  case LTGT:
10198         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10199         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10200         case UNORDERED: case ORDERED:
10201           /* We can't do anything if OP0 is a condition code value, rather
10202              than an actual data value.  */
10203           if (const_op != 0
10204               || CC0_P (XEXP (op0, 0))
10205               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10206             break;
10207
10208           /* Get the two operands being compared.  */
10209           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10210             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10211           else
10212             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10213
10214           /* Check for the cases where we simply want the result of the
10215              earlier test or the opposite of that result.  */
10216           if (code == NE || code == EQ
10217               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10218                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10219                   && (STORE_FLAG_VALUE
10220                       & (((HOST_WIDE_INT) 1
10221                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10222                   && (code == LT || code == GE)))
10223             {
10224               enum rtx_code new_code;
10225               if (code == LT || code == NE)
10226                 new_code = GET_CODE (op0);
10227               else
10228                 new_code = reversed_comparison_code (op0, NULL);
10229
10230               if (new_code != UNKNOWN)
10231                 {
10232                   code = new_code;
10233                   op0 = tem;
10234                   op1 = tem1;
10235                   continue;
10236                 }
10237             }
10238           break;
10239
10240         case IOR:
10241           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10242              iff X <= 0.  */
10243           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10244               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10245               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10246             {
10247               op0 = XEXP (op0, 1);
10248               code = (code == GE ? GT : LE);
10249               continue;
10250             }
10251           break;
10252
10253         case AND:
10254           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10255              will be converted to a ZERO_EXTRACT later.  */
10256           if (const_op == 0 && equality_comparison_p
10257               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10258               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10259             {
10260               op0 = simplify_and_const_int
10261                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10262                                                    XEXP (op0, 1),
10263                                                    XEXP (XEXP (op0, 0), 1)),
10264                  (HOST_WIDE_INT) 1);
10265               continue;
10266             }
10267
10268           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10269              zero and X is a comparison and C1 and C2 describe only bits set
10270              in STORE_FLAG_VALUE, we can compare with X.  */
10271           if (const_op == 0 && equality_comparison_p
10272               && mode_width <= HOST_BITS_PER_WIDE_INT
10273               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10274               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10275               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10276               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10277               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10278             {
10279               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10280                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10281               if ((~STORE_FLAG_VALUE & mask) == 0
10282                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10283                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10284                           && COMPARISON_P (tem))))
10285                 {
10286                   op0 = XEXP (XEXP (op0, 0), 0);
10287                   continue;
10288                 }
10289             }
10290
10291           /* If we are doing an equality comparison of an AND of a bit equal
10292              to the sign bit, replace this with a LT or GE comparison of
10293              the underlying value.  */
10294           if (equality_comparison_p
10295               && const_op == 0
10296               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10297               && mode_width <= HOST_BITS_PER_WIDE_INT
10298               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10299                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10300             {
10301               op0 = XEXP (op0, 0);
10302               code = (code == EQ ? GE : LT);
10303               continue;
10304             }
10305
10306           /* If this AND operation is really a ZERO_EXTEND from a narrower
10307              mode, the constant fits within that mode, and this is either an
10308              equality or unsigned comparison, try to do this comparison in
10309              the narrower mode.
10310
10311              Note that in:
10312
10313              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10314              -> (ne:DI (reg:SI 4) (const_int 0))
10315
10316              unless TRULY_NOOP_TRUNCATION allows it or the register is
10317              known to hold a value of the required mode the
10318              transformation is invalid.  */
10319           if ((equality_comparison_p || unsigned_comparison_p)
10320               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10321               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10322                                    & GET_MODE_MASK (mode))
10323                                   + 1)) >= 0
10324               && const_op >> i == 0
10325               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10326               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10327                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10328                   || (REG_P (XEXP (op0, 0))
10329                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10330             {
10331               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10332               continue;
10333             }
10334
10335           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10336              fits in both M1 and M2 and the SUBREG is either paradoxical
10337              or represents the low part, permute the SUBREG and the AND
10338              and try again.  */
10339           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10340             {
10341               unsigned HOST_WIDE_INT c1;
10342               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10343               /* Require an integral mode, to avoid creating something like
10344                  (AND:SF ...).  */
10345               if (SCALAR_INT_MODE_P (tmode)
10346                   /* It is unsafe to commute the AND into the SUBREG if the
10347                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10348                      not defined.  As originally written the upper bits
10349                      have a defined value due to the AND operation.
10350                      However, if we commute the AND inside the SUBREG then
10351                      they no longer have defined values and the meaning of
10352                      the code has been changed.  */
10353                   && (0
10354 #ifdef WORD_REGISTER_OPERATIONS
10355                       || (mode_width > GET_MODE_BITSIZE (tmode)
10356                           && mode_width <= BITS_PER_WORD)
10357 #endif
10358                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10359                           && subreg_lowpart_p (XEXP (op0, 0))))
10360                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10361                   && mode_width <= HOST_BITS_PER_WIDE_INT
10362                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10363                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10364                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10365                   && c1 != mask
10366                   && c1 != GET_MODE_MASK (tmode))
10367                 {
10368                   op0 = simplify_gen_binary (AND, tmode,
10369                                              SUBREG_REG (XEXP (op0, 0)),
10370                                              gen_int_mode (c1, tmode));
10371                   op0 = gen_lowpart (mode, op0);
10372                   continue;
10373                 }
10374             }
10375
10376           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10377           if (const_op == 0 && equality_comparison_p
10378               && XEXP (op0, 1) == const1_rtx
10379               && GET_CODE (XEXP (op0, 0)) == NOT)
10380             {
10381               op0 = simplify_and_const_int
10382                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10383               code = (code == NE ? EQ : NE);
10384               continue;
10385             }
10386
10387           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10388              (eq (and (lshiftrt X) 1) 0).
10389              Also handle the case where (not X) is expressed using xor.  */
10390           if (const_op == 0 && equality_comparison_p
10391               && XEXP (op0, 1) == const1_rtx
10392               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10393             {
10394               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10395               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10396
10397               if (GET_CODE (shift_op) == NOT
10398                   || (GET_CODE (shift_op) == XOR
10399                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10400                       && GET_CODE (shift_count) == CONST_INT
10401                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10402                       && (INTVAL (XEXP (shift_op, 1))
10403                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10404                 {
10405                   op0 = simplify_and_const_int
10406                     (NULL_RTX, mode,
10407                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10408                      (HOST_WIDE_INT) 1);
10409                   code = (code == NE ? EQ : NE);
10410                   continue;
10411                 }
10412             }
10413           break;
10414
10415         case ASHIFT:
10416           /* If we have (compare (ashift FOO N) (const_int C)) and
10417              the high order N bits of FOO (N+1 if an inequality comparison)
10418              are known to be zero, we can do this by comparing FOO with C
10419              shifted right N bits so long as the low-order N bits of C are
10420              zero.  */
10421           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10422               && INTVAL (XEXP (op0, 1)) >= 0
10423               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10424                   < HOST_BITS_PER_WIDE_INT)
10425               && ((const_op
10426                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10427               && mode_width <= HOST_BITS_PER_WIDE_INT
10428               && (nonzero_bits (XEXP (op0, 0), mode)
10429                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10430                                + ! equality_comparison_p))) == 0)
10431             {
10432               /* We must perform a logical shift, not an arithmetic one,
10433                  as we want the top N bits of C to be zero.  */
10434               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10435
10436               temp >>= INTVAL (XEXP (op0, 1));
10437               op1 = gen_int_mode (temp, mode);
10438               op0 = XEXP (op0, 0);
10439               continue;
10440             }
10441
10442           /* If we are doing a sign bit comparison, it means we are testing
10443              a particular bit.  Convert it to the appropriate AND.  */
10444           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10445               && mode_width <= HOST_BITS_PER_WIDE_INT)
10446             {
10447               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10448                                             ((HOST_WIDE_INT) 1
10449                                              << (mode_width - 1
10450                                                  - INTVAL (XEXP (op0, 1)))));
10451               code = (code == LT ? NE : EQ);
10452               continue;
10453             }
10454
10455           /* If this an equality comparison with zero and we are shifting
10456              the low bit to the sign bit, we can convert this to an AND of the
10457              low-order bit.  */
10458           if (const_op == 0 && equality_comparison_p
10459               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10460               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10461                  == mode_width - 1)
10462             {
10463               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10464                                             (HOST_WIDE_INT) 1);
10465               continue;
10466             }
10467           break;
10468
10469         case ASHIFTRT:
10470           /* If this is an equality comparison with zero, we can do this
10471              as a logical shift, which might be much simpler.  */
10472           if (equality_comparison_p && const_op == 0
10473               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10474             {
10475               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10476                                           XEXP (op0, 0),
10477                                           INTVAL (XEXP (op0, 1)));
10478               continue;
10479             }
10480
10481           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10482              do the comparison in a narrower mode.  */
10483           if (! unsigned_comparison_p
10484               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10485               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10486               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10487               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10488                                          MODE_INT, 1)) != BLKmode
10489               && (((unsigned HOST_WIDE_INT) const_op
10490                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10491                   <= GET_MODE_MASK (tmode)))
10492             {
10493               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10494               continue;
10495             }
10496
10497           /* Likewise if OP0 is a PLUS of a sign extension with a
10498              constant, which is usually represented with the PLUS
10499              between the shifts.  */
10500           if (! unsigned_comparison_p
10501               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10502               && GET_CODE (XEXP (op0, 0)) == PLUS
10503               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10504               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10505               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10506               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10507                                          MODE_INT, 1)) != BLKmode
10508               && (((unsigned HOST_WIDE_INT) const_op
10509                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10510                   <= GET_MODE_MASK (tmode)))
10511             {
10512               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10513               rtx add_const = XEXP (XEXP (op0, 0), 1);
10514               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10515                                                    add_const, XEXP (op0, 1));
10516
10517               op0 = simplify_gen_binary (PLUS, tmode,
10518                                          gen_lowpart (tmode, inner),
10519                                          new_const);
10520               continue;
10521             }
10522
10523           /* ... fall through ...  */
10524         case LSHIFTRT:
10525           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10526              the low order N bits of FOO are known to be zero, we can do this
10527              by comparing FOO with C shifted left N bits so long as no
10528              overflow occurs.  */
10529           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10530               && INTVAL (XEXP (op0, 1)) >= 0
10531               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10532               && mode_width <= HOST_BITS_PER_WIDE_INT
10533               && (nonzero_bits (XEXP (op0, 0), mode)
10534                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10535               && (((unsigned HOST_WIDE_INT) const_op
10536                    + (GET_CODE (op0) != LSHIFTRT
10537                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10538                          + 1)
10539                       : 0))
10540                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10541             {
10542               /* If the shift was logical, then we must make the condition
10543                  unsigned.  */
10544               if (GET_CODE (op0) == LSHIFTRT)
10545                 code = unsigned_condition (code);
10546
10547               const_op <<= INTVAL (XEXP (op0, 1));
10548               op1 = GEN_INT (const_op);
10549               op0 = XEXP (op0, 0);
10550               continue;
10551             }
10552
10553           /* If we are using this shift to extract just the sign bit, we
10554              can replace this with an LT or GE comparison.  */
10555           if (const_op == 0
10556               && (equality_comparison_p || sign_bit_comparison_p)
10557               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10558               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10559                  == mode_width - 1)
10560             {
10561               op0 = XEXP (op0, 0);
10562               code = (code == NE || code == GT ? LT : GE);
10563               continue;
10564             }
10565           break;
10566
10567         default:
10568           break;
10569         }
10570
10571       break;
10572     }
10573
10574   /* Now make any compound operations involved in this comparison.  Then,
10575      check for an outmost SUBREG on OP0 that is not doing anything or is
10576      paradoxical.  The latter transformation must only be performed when
10577      it is known that the "extra" bits will be the same in op0 and op1 or
10578      that they don't matter.  There are three cases to consider:
10579
10580      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10581      care bits and we can assume they have any convenient value.  So
10582      making the transformation is safe.
10583
10584      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10585      In this case the upper bits of op0 are undefined.  We should not make
10586      the simplification in that case as we do not know the contents of
10587      those bits.
10588
10589      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10590      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10591      also be sure that they are the same as the upper bits of op1.
10592
10593      We can never remove a SUBREG for a non-equality comparison because
10594      the sign bit is in a different place in the underlying object.  */
10595
10596   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10597   op1 = make_compound_operation (op1, SET);
10598
10599   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10600       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10601       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10602       && (code == NE || code == EQ))
10603     {
10604       if (GET_MODE_SIZE (GET_MODE (op0))
10605           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10606         {
10607           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10608              implemented.  */
10609           if (REG_P (SUBREG_REG (op0)))
10610             {
10611               op0 = SUBREG_REG (op0);
10612               op1 = gen_lowpart (GET_MODE (op0), op1);
10613             }
10614         }
10615       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10616                 <= HOST_BITS_PER_WIDE_INT)
10617                && (nonzero_bits (SUBREG_REG (op0),
10618                                  GET_MODE (SUBREG_REG (op0)))
10619                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10620         {
10621           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10622
10623           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10624                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10625             op0 = SUBREG_REG (op0), op1 = tem;
10626         }
10627     }
10628
10629   /* We now do the opposite procedure: Some machines don't have compare
10630      insns in all modes.  If OP0's mode is an integer mode smaller than a
10631      word and we can't do a compare in that mode, see if there is a larger
10632      mode for which we can do the compare.  There are a number of cases in
10633      which we can use the wider mode.  */
10634
10635   mode = GET_MODE (op0);
10636   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10637       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10638       && ! have_insn_for (COMPARE, mode))
10639     for (tmode = GET_MODE_WIDER_MODE (mode);
10640          (tmode != VOIDmode
10641           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10642          tmode = GET_MODE_WIDER_MODE (tmode))
10643       if (have_insn_for (COMPARE, tmode))
10644         {
10645           int zero_extended;
10646
10647           /* If the only nonzero bits in OP0 and OP1 are those in the
10648              narrower mode and this is an equality or unsigned comparison,
10649              we can use the wider mode.  Similarly for sign-extended
10650              values, in which case it is true for all comparisons.  */
10651           zero_extended = ((code == EQ || code == NE
10652                             || code == GEU || code == GTU
10653                             || code == LEU || code == LTU)
10654                            && (nonzero_bits (op0, tmode)
10655                                & ~GET_MODE_MASK (mode)) == 0
10656                            && ((GET_CODE (op1) == CONST_INT
10657                                 || (nonzero_bits (op1, tmode)
10658                                     & ~GET_MODE_MASK (mode)) == 0)));
10659
10660           if (zero_extended
10661               || ((num_sign_bit_copies (op0, tmode)
10662                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10663                                      - GET_MODE_BITSIZE (mode)))
10664                   && (num_sign_bit_copies (op1, tmode)
10665                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10666                                         - GET_MODE_BITSIZE (mode)))))
10667             {
10668               /* If OP0 is an AND and we don't have an AND in MODE either,
10669                  make a new AND in the proper mode.  */
10670               if (GET_CODE (op0) == AND
10671                   && !have_insn_for (AND, mode))
10672                 op0 = simplify_gen_binary (AND, tmode,
10673                                            gen_lowpart (tmode,
10674                                                         XEXP (op0, 0)),
10675                                            gen_lowpart (tmode,
10676                                                         XEXP (op0, 1)));
10677
10678               op0 = gen_lowpart (tmode, op0);
10679               if (zero_extended && GET_CODE (op1) == CONST_INT)
10680                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10681               op1 = gen_lowpart (tmode, op1);
10682               break;
10683             }
10684
10685           /* If this is a test for negative, we can make an explicit
10686              test of the sign bit.  */
10687
10688           if (op1 == const0_rtx && (code == LT || code == GE)
10689               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10690             {
10691               op0 = simplify_gen_binary (AND, tmode,
10692                                          gen_lowpart (tmode, op0),
10693                                          GEN_INT ((HOST_WIDE_INT) 1
10694                                                   << (GET_MODE_BITSIZE (mode)
10695                                                       - 1)));
10696               code = (code == LT) ? NE : EQ;
10697               break;
10698             }
10699         }
10700
10701 #ifdef CANONICALIZE_COMPARISON
10702   /* If this machine only supports a subset of valid comparisons, see if we
10703      can convert an unsupported one into a supported one.  */
10704   CANONICALIZE_COMPARISON (code, op0, op1);
10705 #endif
10706
10707   *pop0 = op0;
10708   *pop1 = op1;
10709
10710   return code;
10711 }
10712 \f
10713 /* Utility function for record_value_for_reg.  Count number of
10714    rtxs in X.  */
10715 static int
10716 count_rtxs (rtx x)
10717 {
10718   enum rtx_code code = GET_CODE (x);
10719   const char *fmt;
10720   int i, ret = 1;
10721
10722   if (GET_RTX_CLASS (code) == '2'
10723       || GET_RTX_CLASS (code) == 'c')
10724     {
10725       rtx x0 = XEXP (x, 0);
10726       rtx x1 = XEXP (x, 1);
10727
10728       if (x0 == x1)
10729         return 1 + 2 * count_rtxs (x0);
10730
10731       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10732            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10733           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10734         return 2 + 2 * count_rtxs (x0)
10735                + count_rtxs (x == XEXP (x1, 0)
10736                              ? XEXP (x1, 1) : XEXP (x1, 0));
10737
10738       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10739            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10740           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10741         return 2 + 2 * count_rtxs (x1)
10742                + count_rtxs (x == XEXP (x0, 0)
10743                              ? XEXP (x0, 1) : XEXP (x0, 0));
10744     }
10745
10746   fmt = GET_RTX_FORMAT (code);
10747   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10748     if (fmt[i] == 'e')
10749       ret += count_rtxs (XEXP (x, i));
10750
10751   return ret;
10752 }
10753 \f
10754 /* Utility function for following routine.  Called when X is part of a value
10755    being stored into last_set_value.  Sets last_set_table_tick
10756    for each register mentioned.  Similar to mention_regs in cse.c  */
10757
10758 static void
10759 update_table_tick (rtx x)
10760 {
10761   enum rtx_code code = GET_CODE (x);
10762   const char *fmt = GET_RTX_FORMAT (code);
10763   int i;
10764
10765   if (code == REG)
10766     {
10767       unsigned int regno = REGNO (x);
10768       unsigned int endregno
10769         = regno + (regno < FIRST_PSEUDO_REGISTER
10770                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10771       unsigned int r;
10772
10773       for (r = regno; r < endregno; r++)
10774         reg_stat[r].last_set_table_tick = label_tick;
10775
10776       return;
10777     }
10778
10779   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10780     /* Note that we can't have an "E" in values stored; see
10781        get_last_value_validate.  */
10782     if (fmt[i] == 'e')
10783       {
10784         /* Check for identical subexpressions.  If x contains
10785            identical subexpression we only have to traverse one of
10786            them.  */
10787         if (i == 0 && ARITHMETIC_P (x))
10788           {
10789             /* Note that at this point x1 has already been
10790                processed.  */
10791             rtx x0 = XEXP (x, 0);
10792             rtx x1 = XEXP (x, 1);
10793
10794             /* If x0 and x1 are identical then there is no need to
10795                process x0.  */
10796             if (x0 == x1)
10797               break;
10798
10799             /* If x0 is identical to a subexpression of x1 then while
10800                processing x1, x0 has already been processed.  Thus we
10801                are done with x.  */
10802             if (ARITHMETIC_P (x1)
10803                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10804               break;
10805
10806             /* If x1 is identical to a subexpression of x0 then we
10807                still have to process the rest of x0.  */
10808             if (ARITHMETIC_P (x0)
10809                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10810               {
10811                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10812                 break;
10813               }
10814           }
10815
10816         update_table_tick (XEXP (x, i));
10817       }
10818 }
10819
10820 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10821    are saying that the register is clobbered and we no longer know its
10822    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10823    only permitted with VALUE also zero and is used to invalidate the
10824    register.  */
10825
10826 static void
10827 record_value_for_reg (rtx reg, rtx insn, rtx value)
10828 {
10829   unsigned int regno = REGNO (reg);
10830   unsigned int endregno
10831     = regno + (regno < FIRST_PSEUDO_REGISTER
10832                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10833   unsigned int i;
10834
10835   /* If VALUE contains REG and we have a previous value for REG, substitute
10836      the previous value.  */
10837   if (value && insn && reg_overlap_mentioned_p (reg, value))
10838     {
10839       rtx tem;
10840
10841       /* Set things up so get_last_value is allowed to see anything set up to
10842          our insn.  */
10843       subst_low_cuid = INSN_CUID (insn);
10844       tem = get_last_value (reg);
10845
10846       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10847          it isn't going to be useful and will take a lot of time to process,
10848          so just use the CLOBBER.  */
10849
10850       if (tem)
10851         {
10852           if (ARITHMETIC_P (tem)
10853               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10854               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10855             tem = XEXP (tem, 0);
10856           else if (count_occurrences (value, reg, 1) >= 2)
10857             {
10858               /* If there are two or more occurrences of REG in VALUE,
10859                  prevent the value from growing too much.  */
10860               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10861                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10862             }
10863
10864           value = replace_rtx (copy_rtx (value), reg, tem);
10865         }
10866     }
10867
10868   /* For each register modified, show we don't know its value, that
10869      we don't know about its bitwise content, that its value has been
10870      updated, and that we don't know the location of the death of the
10871      register.  */
10872   for (i = regno; i < endregno; i++)
10873     {
10874       if (insn)
10875         reg_stat[i].last_set = insn;
10876
10877       reg_stat[i].last_set_value = 0;
10878       reg_stat[i].last_set_mode = 0;
10879       reg_stat[i].last_set_nonzero_bits = 0;
10880       reg_stat[i].last_set_sign_bit_copies = 0;
10881       reg_stat[i].last_death = 0;
10882       reg_stat[i].truncated_to_mode = 0;
10883     }
10884
10885   /* Mark registers that are being referenced in this value.  */
10886   if (value)
10887     update_table_tick (value);
10888
10889   /* Now update the status of each register being set.
10890      If someone is using this register in this block, set this register
10891      to invalid since we will get confused between the two lives in this
10892      basic block.  This makes using this register always invalid.  In cse, we
10893      scan the table to invalidate all entries using this register, but this
10894      is too much work for us.  */
10895
10896   for (i = regno; i < endregno; i++)
10897     {
10898       reg_stat[i].last_set_label = label_tick;
10899       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10900         reg_stat[i].last_set_invalid = 1;
10901       else
10902         reg_stat[i].last_set_invalid = 0;
10903     }
10904
10905   /* The value being assigned might refer to X (like in "x++;").  In that
10906      case, we must replace it with (clobber (const_int 0)) to prevent
10907      infinite loops.  */
10908   if (value && ! get_last_value_validate (&value, insn,
10909                                           reg_stat[regno].last_set_label, 0))
10910     {
10911       value = copy_rtx (value);
10912       if (! get_last_value_validate (&value, insn,
10913                                      reg_stat[regno].last_set_label, 1))
10914         value = 0;
10915     }
10916
10917   /* For the main register being modified, update the value, the mode, the
10918      nonzero bits, and the number of sign bit copies.  */
10919
10920   reg_stat[regno].last_set_value = value;
10921
10922   if (value)
10923     {
10924       enum machine_mode mode = GET_MODE (reg);
10925       subst_low_cuid = INSN_CUID (insn);
10926       reg_stat[regno].last_set_mode = mode;
10927       if (GET_MODE_CLASS (mode) == MODE_INT
10928           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10929         mode = nonzero_bits_mode;
10930       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10931       reg_stat[regno].last_set_sign_bit_copies
10932         = num_sign_bit_copies (value, GET_MODE (reg));
10933     }
10934 }
10935
10936 /* Called via note_stores from record_dead_and_set_regs to handle one
10937    SET or CLOBBER in an insn.  DATA is the instruction in which the
10938    set is occurring.  */
10939
10940 static void
10941 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10942 {
10943   rtx record_dead_insn = (rtx) data;
10944
10945   if (GET_CODE (dest) == SUBREG)
10946     dest = SUBREG_REG (dest);
10947
10948   if (!record_dead_insn)
10949     {
10950       if (REG_P (dest))
10951         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10952       return;
10953     }
10954
10955   if (REG_P (dest))
10956     {
10957       /* If we are setting the whole register, we know its value.  Otherwise
10958          show that we don't know the value.  We can handle SUBREG in
10959          some cases.  */
10960       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10961         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10962       else if (GET_CODE (setter) == SET
10963                && GET_CODE (SET_DEST (setter)) == SUBREG
10964                && SUBREG_REG (SET_DEST (setter)) == dest
10965                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10966                && subreg_lowpart_p (SET_DEST (setter)))
10967         record_value_for_reg (dest, record_dead_insn,
10968                               gen_lowpart (GET_MODE (dest),
10969                                                        SET_SRC (setter)));
10970       else
10971         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10972     }
10973   else if (MEM_P (dest)
10974            /* Ignore pushes, they clobber nothing.  */
10975            && ! push_operand (dest, GET_MODE (dest)))
10976     mem_last_set = INSN_CUID (record_dead_insn);
10977 }
10978
10979 /* Update the records of when each REG was most recently set or killed
10980    for the things done by INSN.  This is the last thing done in processing
10981    INSN in the combiner loop.
10982
10983    We update reg_stat[], in particular fields last_set, last_set_value,
10984    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10985    last_death, and also the similar information mem_last_set (which insn
10986    most recently modified memory) and last_call_cuid (which insn was the
10987    most recent subroutine call).  */
10988
10989 static void
10990 record_dead_and_set_regs (rtx insn)
10991 {
10992   rtx link;
10993   unsigned int i;
10994
10995   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10996     {
10997       if (REG_NOTE_KIND (link) == REG_DEAD
10998           && REG_P (XEXP (link, 0)))
10999         {
11000           unsigned int regno = REGNO (XEXP (link, 0));
11001           unsigned int endregno
11002             = regno + (regno < FIRST_PSEUDO_REGISTER
11003                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11004                        : 1);
11005
11006           for (i = regno; i < endregno; i++)
11007             reg_stat[i].last_death = insn;
11008         }
11009       else if (REG_NOTE_KIND (link) == REG_INC)
11010         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11011     }
11012
11013   if (CALL_P (insn))
11014     {
11015       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11016         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11017           {
11018             reg_stat[i].last_set_value = 0;
11019             reg_stat[i].last_set_mode = 0;
11020             reg_stat[i].last_set_nonzero_bits = 0;
11021             reg_stat[i].last_set_sign_bit_copies = 0;
11022             reg_stat[i].last_death = 0;
11023             reg_stat[i].truncated_to_mode = 0;
11024           }
11025
11026       last_call_cuid = mem_last_set = INSN_CUID (insn);
11027
11028       /* We can't combine into a call pattern.  Remember, though, that
11029          the return value register is set at this CUID.  We could
11030          still replace a register with the return value from the
11031          wrong subroutine call!  */
11032       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11033     }
11034   else
11035     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11036 }
11037
11038 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11039    register present in the SUBREG, so for each such SUBREG go back and
11040    adjust nonzero and sign bit information of the registers that are
11041    known to have some zero/sign bits set.
11042
11043    This is needed because when combine blows the SUBREGs away, the
11044    information on zero/sign bits is lost and further combines can be
11045    missed because of that.  */
11046
11047 static void
11048 record_promoted_value (rtx insn, rtx subreg)
11049 {
11050   rtx links, set;
11051   unsigned int regno = REGNO (SUBREG_REG (subreg));
11052   enum machine_mode mode = GET_MODE (subreg);
11053
11054   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11055     return;
11056
11057   for (links = LOG_LINKS (insn); links;)
11058     {
11059       insn = XEXP (links, 0);
11060       set = single_set (insn);
11061
11062       if (! set || !REG_P (SET_DEST (set))
11063           || REGNO (SET_DEST (set)) != regno
11064           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11065         {
11066           links = XEXP (links, 1);
11067           continue;
11068         }
11069
11070       if (reg_stat[regno].last_set == insn)
11071         {
11072           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11073             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11074         }
11075
11076       if (REG_P (SET_SRC (set)))
11077         {
11078           regno = REGNO (SET_SRC (set));
11079           links = LOG_LINKS (insn);
11080         }
11081       else
11082         break;
11083     }
11084 }
11085
11086 /* Check if X, a register, is known to contain a value already
11087    truncated to MODE.  In this case we can use a subreg to refer to
11088    the truncated value even though in the generic case we would need
11089    an explicit truncation.  */
11090
11091 static bool
11092 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11093 {
11094   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11095
11096   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11097     return false;
11098   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11099     return true;
11100   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11101                              GET_MODE_BITSIZE (truncated)))
11102     return true;
11103   return false;
11104 }
11105
11106 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11107    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11108    a truncate into a subreg using this information.  */
11109
11110 static void
11111 record_truncated_value (rtx x)
11112 {
11113   enum machine_mode truncated_mode;
11114
11115   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11116     {
11117       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11118       truncated_mode = GET_MODE (x);
11119
11120       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11121         return;
11122
11123       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11124                                  GET_MODE_BITSIZE (original_mode)))
11125         return;
11126
11127       x = SUBREG_REG (x);
11128     }
11129   /* ??? For hard-regs we now record everything.  We might be able to
11130      optimize this using last_set_mode.  */
11131   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11132     truncated_mode = GET_MODE (x);
11133   else
11134     return;
11135
11136   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11137       || reg_stat[REGNO (x)].truncation_label < label_tick
11138       || (GET_MODE_SIZE (truncated_mode)
11139           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11140     {
11141       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11142       reg_stat[REGNO (x)].truncation_label = label_tick;
11143     }
11144 }
11145
11146 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11147    found, note what it implies to the registers used in it.  */
11148
11149 static void
11150 check_conversions (rtx insn, rtx x)
11151 {
11152   if (GET_CODE (x) == SUBREG || REG_P (x))
11153     {
11154       if (GET_CODE (x) == SUBREG
11155           && SUBREG_PROMOTED_VAR_P (x)
11156           && REG_P (SUBREG_REG (x)))
11157         record_promoted_value (insn, x);
11158
11159       record_truncated_value (x);
11160     }
11161   else
11162     {
11163       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11164       int i, j;
11165
11166       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11167         switch (format[i])
11168           {
11169           case 'e':
11170             check_conversions (insn, XEXP (x, i));
11171             break;
11172           case 'V':
11173           case 'E':
11174             if (XVEC (x, i) != 0)
11175               for (j = 0; j < XVECLEN (x, i); j++)
11176                 check_conversions (insn, XVECEXP (x, i, j));
11177             break;
11178           }
11179     }
11180 }
11181 \f
11182 /* Utility routine for the following function.  Verify that all the registers
11183    mentioned in *LOC are valid when *LOC was part of a value set when
11184    label_tick == TICK.  Return 0 if some are not.
11185
11186    If REPLACE is nonzero, replace the invalid reference with
11187    (clobber (const_int 0)) and return 1.  This replacement is useful because
11188    we often can get useful information about the form of a value (e.g., if
11189    it was produced by a shift that always produces -1 or 0) even though
11190    we don't know exactly what registers it was produced from.  */
11191
11192 static int
11193 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11194 {
11195   rtx x = *loc;
11196   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11197   int len = GET_RTX_LENGTH (GET_CODE (x));
11198   int i;
11199
11200   if (REG_P (x))
11201     {
11202       unsigned int regno = REGNO (x);
11203       unsigned int endregno
11204         = regno + (regno < FIRST_PSEUDO_REGISTER
11205                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11206       unsigned int j;
11207
11208       for (j = regno; j < endregno; j++)
11209         if (reg_stat[j].last_set_invalid
11210             /* If this is a pseudo-register that was only set once and not
11211                live at the beginning of the function, it is always valid.  */
11212             || (! (regno >= FIRST_PSEUDO_REGISTER
11213                    && REG_N_SETS (regno) == 1
11214                    && (! REGNO_REG_SET_P
11215                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11216                         regno)))
11217                 && reg_stat[j].last_set_label > tick))
11218           {
11219             if (replace)
11220               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11221             return replace;
11222           }
11223
11224       return 1;
11225     }
11226   /* If this is a memory reference, make sure that there were
11227      no stores after it that might have clobbered the value.  We don't
11228      have alias info, so we assume any store invalidates it.  */
11229   else if (MEM_P (x) && !MEM_READONLY_P (x)
11230            && INSN_CUID (insn) <= mem_last_set)
11231     {
11232       if (replace)
11233         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11234       return replace;
11235     }
11236
11237   for (i = 0; i < len; i++)
11238     {
11239       if (fmt[i] == 'e')
11240         {
11241           /* Check for identical subexpressions.  If x contains
11242              identical subexpression we only have to traverse one of
11243              them.  */
11244           if (i == 1 && ARITHMETIC_P (x))
11245             {
11246               /* Note that at this point x0 has already been checked
11247                  and found valid.  */
11248               rtx x0 = XEXP (x, 0);
11249               rtx x1 = XEXP (x, 1);
11250
11251               /* If x0 and x1 are identical then x is also valid.  */
11252               if (x0 == x1)
11253                 return 1;
11254
11255               /* If x1 is identical to a subexpression of x0 then
11256                  while checking x0, x1 has already been checked.  Thus
11257                  it is valid and so as x.  */
11258               if (ARITHMETIC_P (x0)
11259                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11260                 return 1;
11261
11262               /* If x0 is identical to a subexpression of x1 then x is
11263                  valid iff the rest of x1 is valid.  */
11264               if (ARITHMETIC_P (x1)
11265                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11266                 return
11267                   get_last_value_validate (&XEXP (x1,
11268                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11269                                            insn, tick, replace);
11270             }
11271
11272           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11273                                        replace) == 0)
11274             return 0;
11275         }
11276       /* Don't bother with these.  They shouldn't occur anyway.  */
11277       else if (fmt[i] == 'E')
11278         return 0;
11279     }
11280
11281   /* If we haven't found a reason for it to be invalid, it is valid.  */
11282   return 1;
11283 }
11284
11285 /* Get the last value assigned to X, if known.  Some registers
11286    in the value may be replaced with (clobber (const_int 0)) if their value
11287    is known longer known reliably.  */
11288
11289 static rtx
11290 get_last_value (rtx x)
11291 {
11292   unsigned int regno;
11293   rtx value;
11294
11295   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11296      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11297      we cannot predict what values the "extra" bits might have.  */
11298   if (GET_CODE (x) == SUBREG
11299       && subreg_lowpart_p (x)
11300       && (GET_MODE_SIZE (GET_MODE (x))
11301           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11302       && (value = get_last_value (SUBREG_REG (x))) != 0)
11303     return gen_lowpart (GET_MODE (x), value);
11304
11305   if (!REG_P (x))
11306     return 0;
11307
11308   regno = REGNO (x);
11309   value = reg_stat[regno].last_set_value;
11310
11311   /* If we don't have a value, or if it isn't for this basic block and
11312      it's either a hard register, set more than once, or it's a live
11313      at the beginning of the function, return 0.
11314
11315      Because if it's not live at the beginning of the function then the reg
11316      is always set before being used (is never used without being set).
11317      And, if it's set only once, and it's always set before use, then all
11318      uses must have the same last value, even if it's not from this basic
11319      block.  */
11320
11321   if (value == 0
11322       || (reg_stat[regno].last_set_label != label_tick
11323           && (regno < FIRST_PSEUDO_REGISTER
11324               || REG_N_SETS (regno) != 1
11325               || (REGNO_REG_SET_P
11326                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11327                    regno)))))
11328     return 0;
11329
11330   /* If the value was set in a later insn than the ones we are processing,
11331      we can't use it even if the register was only set once.  */
11332   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11333     return 0;
11334
11335   /* If the value has all its registers valid, return it.  */
11336   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11337                                reg_stat[regno].last_set_label, 0))
11338     return value;
11339
11340   /* Otherwise, make a copy and replace any invalid register with
11341      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11342
11343   value = copy_rtx (value);
11344   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11345                                reg_stat[regno].last_set_label, 1))
11346     return value;
11347
11348   return 0;
11349 }
11350 \f
11351 /* Return nonzero if expression X refers to a REG or to memory
11352    that is set in an instruction more recent than FROM_CUID.  */
11353
11354 static int
11355 use_crosses_set_p (rtx x, int from_cuid)
11356 {
11357   const char *fmt;
11358   int i;
11359   enum rtx_code code = GET_CODE (x);
11360
11361   if (code == REG)
11362     {
11363       unsigned int regno = REGNO (x);
11364       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11365                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11366
11367 #ifdef PUSH_ROUNDING
11368       /* Don't allow uses of the stack pointer to be moved,
11369          because we don't know whether the move crosses a push insn.  */
11370       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11371         return 1;
11372 #endif
11373       for (; regno < endreg; regno++)
11374         if (reg_stat[regno].last_set
11375             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11376           return 1;
11377       return 0;
11378     }
11379
11380   if (code == MEM && mem_last_set > from_cuid)
11381     return 1;
11382
11383   fmt = GET_RTX_FORMAT (code);
11384
11385   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11386     {
11387       if (fmt[i] == 'E')
11388         {
11389           int j;
11390           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11391             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11392               return 1;
11393         }
11394       else if (fmt[i] == 'e'
11395                && use_crosses_set_p (XEXP (x, i), from_cuid))
11396         return 1;
11397     }
11398   return 0;
11399 }
11400 \f
11401 /* Define three variables used for communication between the following
11402    routines.  */
11403
11404 static unsigned int reg_dead_regno, reg_dead_endregno;
11405 static int reg_dead_flag;
11406
11407 /* Function called via note_stores from reg_dead_at_p.
11408
11409    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11410    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11411
11412 static void
11413 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11414 {
11415   unsigned int regno, endregno;
11416
11417   if (!REG_P (dest))
11418     return;
11419
11420   regno = REGNO (dest);
11421   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11422                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11423
11424   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11425     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11426 }
11427
11428 /* Return nonzero if REG is known to be dead at INSN.
11429
11430    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11431    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11432    live.  Otherwise, see if it is live or dead at the start of the basic
11433    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11434    must be assumed to be always live.  */
11435
11436 static int
11437 reg_dead_at_p (rtx reg, rtx insn)
11438 {
11439   basic_block block;
11440   unsigned int i;
11441
11442   /* Set variables for reg_dead_at_p_1.  */
11443   reg_dead_regno = REGNO (reg);
11444   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11445                                         ? hard_regno_nregs[reg_dead_regno]
11446                                                           [GET_MODE (reg)]
11447                                         : 1);
11448
11449   reg_dead_flag = 0;
11450
11451   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11452      we allow the machine description to decide whether use-and-clobber
11453      patterns are OK.  */
11454   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11455     {
11456       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11457         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11458           return 0;
11459     }
11460
11461   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11462      beginning of function.  */
11463   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11464        insn = prev_nonnote_insn (insn))
11465     {
11466       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11467       if (reg_dead_flag)
11468         return reg_dead_flag == 1 ? 1 : 0;
11469
11470       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11471         return 1;
11472     }
11473
11474   /* Get the basic block that we were in.  */
11475   if (insn == 0)
11476     block = ENTRY_BLOCK_PTR->next_bb;
11477   else
11478     {
11479       FOR_EACH_BB (block)
11480         if (insn == BB_HEAD (block))
11481           break;
11482
11483       if (block == EXIT_BLOCK_PTR)
11484         return 0;
11485     }
11486
11487   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11488     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11489       return 0;
11490
11491   return 1;
11492 }
11493 \f
11494 /* Note hard registers in X that are used.  This code is similar to
11495    that in flow.c, but much simpler since we don't care about pseudos.  */
11496
11497 static void
11498 mark_used_regs_combine (rtx x)
11499 {
11500   RTX_CODE code = GET_CODE (x);
11501   unsigned int regno;
11502   int i;
11503
11504   switch (code)
11505     {
11506     case LABEL_REF:
11507     case SYMBOL_REF:
11508     case CONST_INT:
11509     case CONST:
11510     case CONST_DOUBLE:
11511     case CONST_VECTOR:
11512     case PC:
11513     case ADDR_VEC:
11514     case ADDR_DIFF_VEC:
11515     case ASM_INPUT:
11516 #ifdef HAVE_cc0
11517     /* CC0 must die in the insn after it is set, so we don't need to take
11518        special note of it here.  */
11519     case CC0:
11520 #endif
11521       return;
11522
11523     case CLOBBER:
11524       /* If we are clobbering a MEM, mark any hard registers inside the
11525          address as used.  */
11526       if (MEM_P (XEXP (x, 0)))
11527         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11528       return;
11529
11530     case REG:
11531       regno = REGNO (x);
11532       /* A hard reg in a wide mode may really be multiple registers.
11533          If so, mark all of them just like the first.  */
11534       if (regno < FIRST_PSEUDO_REGISTER)
11535         {
11536           unsigned int endregno, r;
11537
11538           /* None of this applies to the stack, frame or arg pointers.  */
11539           if (regno == STACK_POINTER_REGNUM
11540 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11541               || regno == HARD_FRAME_POINTER_REGNUM
11542 #endif
11543 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11544               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11545 #endif
11546               || regno == FRAME_POINTER_REGNUM)
11547             return;
11548
11549           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11550           for (r = regno; r < endregno; r++)
11551             SET_HARD_REG_BIT (newpat_used_regs, r);
11552         }
11553       return;
11554
11555     case SET:
11556       {
11557         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11558            the address.  */
11559         rtx testreg = SET_DEST (x);
11560
11561         while (GET_CODE (testreg) == SUBREG
11562                || GET_CODE (testreg) == ZERO_EXTRACT
11563                || GET_CODE (testreg) == STRICT_LOW_PART)
11564           testreg = XEXP (testreg, 0);
11565
11566         if (MEM_P (testreg))
11567           mark_used_regs_combine (XEXP (testreg, 0));
11568
11569         mark_used_regs_combine (SET_SRC (x));
11570       }
11571       return;
11572
11573     default:
11574       break;
11575     }
11576
11577   /* Recursively scan the operands of this expression.  */
11578
11579   {
11580     const char *fmt = GET_RTX_FORMAT (code);
11581
11582     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11583       {
11584         if (fmt[i] == 'e')
11585           mark_used_regs_combine (XEXP (x, i));
11586         else if (fmt[i] == 'E')
11587           {
11588             int j;
11589
11590             for (j = 0; j < XVECLEN (x, i); j++)
11591               mark_used_regs_combine (XVECEXP (x, i, j));
11592           }
11593       }
11594   }
11595 }
11596 \f
11597 /* Remove register number REGNO from the dead registers list of INSN.
11598
11599    Return the note used to record the death, if there was one.  */
11600
11601 rtx
11602 remove_death (unsigned int regno, rtx insn)
11603 {
11604   rtx note = find_regno_note (insn, REG_DEAD, regno);
11605
11606   if (note)
11607     {
11608       REG_N_DEATHS (regno)--;
11609       remove_note (insn, note);
11610     }
11611
11612   return note;
11613 }
11614
11615 /* For each register (hardware or pseudo) used within expression X, if its
11616    death is in an instruction with cuid between FROM_CUID (inclusive) and
11617    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11618    list headed by PNOTES.
11619
11620    That said, don't move registers killed by maybe_kill_insn.
11621
11622    This is done when X is being merged by combination into TO_INSN.  These
11623    notes will then be distributed as needed.  */
11624
11625 static void
11626 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11627              rtx *pnotes)
11628 {
11629   const char *fmt;
11630   int len, i;
11631   enum rtx_code code = GET_CODE (x);
11632
11633   if (code == REG)
11634     {
11635       unsigned int regno = REGNO (x);
11636       rtx where_dead = reg_stat[regno].last_death;
11637       rtx before_dead, after_dead;
11638
11639       /* Don't move the register if it gets killed in between from and to.  */
11640       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11641           && ! reg_referenced_p (x, maybe_kill_insn))
11642         return;
11643
11644       /* WHERE_DEAD could be a USE insn made by combine, so first we
11645          make sure that we have insns with valid INSN_CUID values.  */
11646       before_dead = where_dead;
11647       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11648         before_dead = PREV_INSN (before_dead);
11649
11650       after_dead = where_dead;
11651       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11652         after_dead = NEXT_INSN (after_dead);
11653
11654       if (before_dead && after_dead
11655           && INSN_CUID (before_dead) >= from_cuid
11656           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11657               || (where_dead != after_dead
11658                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11659         {
11660           rtx note = remove_death (regno, where_dead);
11661
11662           /* It is possible for the call above to return 0.  This can occur
11663              when last_death points to I2 or I1 that we combined with.
11664              In that case make a new note.
11665
11666              We must also check for the case where X is a hard register
11667              and NOTE is a death note for a range of hard registers
11668              including X.  In that case, we must put REG_DEAD notes for
11669              the remaining registers in place of NOTE.  */
11670
11671           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11672               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11673                   > GET_MODE_SIZE (GET_MODE (x))))
11674             {
11675               unsigned int deadregno = REGNO (XEXP (note, 0));
11676               unsigned int deadend
11677                 = (deadregno + hard_regno_nregs[deadregno]
11678                                                [GET_MODE (XEXP (note, 0))]);
11679               unsigned int ourend
11680                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11681               unsigned int i;
11682
11683               for (i = deadregno; i < deadend; i++)
11684                 if (i < regno || i >= ourend)
11685                   REG_NOTES (where_dead)
11686                     = gen_rtx_EXPR_LIST (REG_DEAD,
11687                                          regno_reg_rtx[i],
11688                                          REG_NOTES (where_dead));
11689             }
11690
11691           /* If we didn't find any note, or if we found a REG_DEAD note that
11692              covers only part of the given reg, and we have a multi-reg hard
11693              register, then to be safe we must check for REG_DEAD notes
11694              for each register other than the first.  They could have
11695              their own REG_DEAD notes lying around.  */
11696           else if ((note == 0
11697                     || (note != 0
11698                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11699                             < GET_MODE_SIZE (GET_MODE (x)))))
11700                    && regno < FIRST_PSEUDO_REGISTER
11701                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11702             {
11703               unsigned int ourend
11704                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11705               unsigned int i, offset;
11706               rtx oldnotes = 0;
11707
11708               if (note)
11709                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11710               else
11711                 offset = 1;
11712
11713               for (i = regno + offset; i < ourend; i++)
11714                 move_deaths (regno_reg_rtx[i],
11715                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11716             }
11717
11718           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11719             {
11720               XEXP (note, 1) = *pnotes;
11721               *pnotes = note;
11722             }
11723           else
11724             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11725
11726           REG_N_DEATHS (regno)++;
11727         }
11728
11729       return;
11730     }
11731
11732   else if (GET_CODE (x) == SET)
11733     {
11734       rtx dest = SET_DEST (x);
11735
11736       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11737
11738       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11739          that accesses one word of a multi-word item, some
11740          piece of everything register in the expression is used by
11741          this insn, so remove any old death.  */
11742       /* ??? So why do we test for equality of the sizes?  */
11743
11744       if (GET_CODE (dest) == ZERO_EXTRACT
11745           || GET_CODE (dest) == STRICT_LOW_PART
11746           || (GET_CODE (dest) == SUBREG
11747               && (((GET_MODE_SIZE (GET_MODE (dest))
11748                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11749                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11750                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11751         {
11752           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11753           return;
11754         }
11755
11756       /* If this is some other SUBREG, we know it replaces the entire
11757          value, so use that as the destination.  */
11758       if (GET_CODE (dest) == SUBREG)
11759         dest = SUBREG_REG (dest);
11760
11761       /* If this is a MEM, adjust deaths of anything used in the address.
11762          For a REG (the only other possibility), the entire value is
11763          being replaced so the old value is not used in this insn.  */
11764
11765       if (MEM_P (dest))
11766         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11767                      to_insn, pnotes);
11768       return;
11769     }
11770
11771   else if (GET_CODE (x) == CLOBBER)
11772     return;
11773
11774   len = GET_RTX_LENGTH (code);
11775   fmt = GET_RTX_FORMAT (code);
11776
11777   for (i = 0; i < len; i++)
11778     {
11779       if (fmt[i] == 'E')
11780         {
11781           int j;
11782           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11783             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11784                          to_insn, pnotes);
11785         }
11786       else if (fmt[i] == 'e')
11787         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11788     }
11789 }
11790 \f
11791 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11792    pattern of an insn.  X must be a REG.  */
11793
11794 static int
11795 reg_bitfield_target_p (rtx x, rtx body)
11796 {
11797   int i;
11798
11799   if (GET_CODE (body) == SET)
11800     {
11801       rtx dest = SET_DEST (body);
11802       rtx target;
11803       unsigned int regno, tregno, endregno, endtregno;
11804
11805       if (GET_CODE (dest) == ZERO_EXTRACT)
11806         target = XEXP (dest, 0);
11807       else if (GET_CODE (dest) == STRICT_LOW_PART)
11808         target = SUBREG_REG (XEXP (dest, 0));
11809       else
11810         return 0;
11811
11812       if (GET_CODE (target) == SUBREG)
11813         target = SUBREG_REG (target);
11814
11815       if (!REG_P (target))
11816         return 0;
11817
11818       tregno = REGNO (target), regno = REGNO (x);
11819       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11820         return target == x;
11821
11822       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11823       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11824
11825       return endregno > tregno && regno < endtregno;
11826     }
11827
11828   else if (GET_CODE (body) == PARALLEL)
11829     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11830       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11831         return 1;
11832
11833   return 0;
11834 }
11835 \f
11836 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11837    as appropriate.  I3 and I2 are the insns resulting from the combination
11838    insns including FROM (I2 may be zero).
11839
11840    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11841    not need REG_DEAD notes because they are being substituted for.  This
11842    saves searching in the most common cases.
11843
11844    Each note in the list is either ignored or placed on some insns, depending
11845    on the type of note.  */
11846
11847 static void
11848 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11849                   rtx elim_i1)
11850 {
11851   rtx note, next_note;
11852   rtx tem;
11853
11854   for (note = notes; note; note = next_note)
11855     {
11856       rtx place = 0, place2 = 0;
11857
11858       next_note = XEXP (note, 1);
11859       switch (REG_NOTE_KIND (note))
11860         {
11861         case REG_BR_PROB:
11862         case REG_BR_PRED:
11863           /* Doesn't matter much where we put this, as long as it's somewhere.
11864              It is preferable to keep these notes on branches, which is most
11865              likely to be i3.  */
11866           place = i3;
11867           break;
11868
11869         case REG_VALUE_PROFILE:
11870           /* Just get rid of this note, as it is unused later anyway.  */
11871           break;
11872
11873         case REG_NON_LOCAL_GOTO:
11874           if (JUMP_P (i3))
11875             place = i3;
11876           else
11877             {
11878               gcc_assert (i2 && JUMP_P (i2));
11879               place = i2;
11880             }
11881           break;
11882
11883         case REG_EH_REGION:
11884           /* These notes must remain with the call or trapping instruction.  */
11885           if (CALL_P (i3))
11886             place = i3;
11887           else if (i2 && CALL_P (i2))
11888             place = i2;
11889           else
11890             {
11891               gcc_assert (flag_non_call_exceptions);
11892               if (may_trap_p (i3))
11893                 place = i3;
11894               else if (i2 && may_trap_p (i2))
11895                 place = i2;
11896               /* ??? Otherwise assume we've combined things such that we
11897                  can now prove that the instructions can't trap.  Drop the
11898                  note in this case.  */
11899             }
11900           break;
11901
11902         case REG_NORETURN:
11903         case REG_SETJMP:
11904           /* These notes must remain with the call.  It should not be
11905              possible for both I2 and I3 to be a call.  */
11906           if (CALL_P (i3))
11907             place = i3;
11908           else
11909             {
11910               gcc_assert (i2 && CALL_P (i2));
11911               place = i2;
11912             }
11913           break;
11914
11915         case REG_UNUSED:
11916           /* Any clobbers for i3 may still exist, and so we must process
11917              REG_UNUSED notes from that insn.
11918
11919              Any clobbers from i2 or i1 can only exist if they were added by
11920              recog_for_combine.  In that case, recog_for_combine created the
11921              necessary REG_UNUSED notes.  Trying to keep any original
11922              REG_UNUSED notes from these insns can cause incorrect output
11923              if it is for the same register as the original i3 dest.
11924              In that case, we will notice that the register is set in i3,
11925              and then add a REG_UNUSED note for the destination of i3, which
11926              is wrong.  However, it is possible to have REG_UNUSED notes from
11927              i2 or i1 for register which were both used and clobbered, so
11928              we keep notes from i2 or i1 if they will turn into REG_DEAD
11929              notes.  */
11930
11931           /* If this register is set or clobbered in I3, put the note there
11932              unless there is one already.  */
11933           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11934             {
11935               if (from_insn != i3)
11936                 break;
11937
11938               if (! (REG_P (XEXP (note, 0))
11939                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11940                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11941                 place = i3;
11942             }
11943           /* Otherwise, if this register is used by I3, then this register
11944              now dies here, so we must put a REG_DEAD note here unless there
11945              is one already.  */
11946           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11947                    && ! (REG_P (XEXP (note, 0))
11948                          ? find_regno_note (i3, REG_DEAD,
11949                                             REGNO (XEXP (note, 0)))
11950                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11951             {
11952               PUT_REG_NOTE_KIND (note, REG_DEAD);
11953               place = i3;
11954             }
11955           break;
11956
11957         case REG_EQUAL:
11958         case REG_EQUIV:
11959         case REG_NOALIAS:
11960           /* These notes say something about results of an insn.  We can
11961              only support them if they used to be on I3 in which case they
11962              remain on I3.  Otherwise they are ignored.
11963
11964              If the note refers to an expression that is not a constant, we
11965              must also ignore the note since we cannot tell whether the
11966              equivalence is still true.  It might be possible to do
11967              slightly better than this (we only have a problem if I2DEST
11968              or I1DEST is present in the expression), but it doesn't
11969              seem worth the trouble.  */
11970
11971           if (from_insn == i3
11972               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11973             place = i3;
11974           break;
11975
11976         case REG_INC:
11977         case REG_NO_CONFLICT:
11978           /* These notes say something about how a register is used.  They must
11979              be present on any use of the register in I2 or I3.  */
11980           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11981             place = i3;
11982
11983           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11984             {
11985               if (place)
11986                 place2 = i2;
11987               else
11988                 place = i2;
11989             }
11990           break;
11991
11992         case REG_LABEL:
11993           /* This can show up in several ways -- either directly in the
11994              pattern, or hidden off in the constant pool with (or without?)
11995              a REG_EQUAL note.  */
11996           /* ??? Ignore the without-reg_equal-note problem for now.  */
11997           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11998               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11999                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12000                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12001             place = i3;
12002
12003           if (i2
12004               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12005                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12006                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12007                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12008             {
12009               if (place)
12010                 place2 = i2;
12011               else
12012                 place = i2;
12013             }
12014
12015           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12016              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12017           if (place && JUMP_P (place))
12018             {
12019               rtx label = JUMP_LABEL (place);
12020
12021               if (!label)
12022                 JUMP_LABEL (place) = XEXP (note, 0);
12023               else
12024                 {
12025                   gcc_assert (label == XEXP (note, 0));
12026                   if (LABEL_P (label))
12027                     LABEL_NUSES (label)--;
12028                 }
12029               place = 0;
12030             }
12031           if (place2 && JUMP_P (place2))
12032             {
12033               rtx label = JUMP_LABEL (place2);
12034
12035               if (!label)
12036                 JUMP_LABEL (place2) = XEXP (note, 0);
12037               else
12038                 {
12039                   gcc_assert (label == XEXP (note, 0));
12040                   if (LABEL_P (label))
12041                     LABEL_NUSES (label)--;
12042                 }
12043               place2 = 0;
12044             }
12045           break;
12046
12047         case REG_NONNEG:
12048           /* This note says something about the value of a register prior
12049              to the execution of an insn.  It is too much trouble to see
12050              if the note is still correct in all situations.  It is better
12051              to simply delete it.  */
12052           break;
12053
12054         case REG_RETVAL:
12055           /* If the insn previously containing this note still exists,
12056              put it back where it was.  Otherwise move it to the previous
12057              insn.  Adjust the corresponding REG_LIBCALL note.  */
12058           if (!NOTE_P (from_insn))
12059             place = from_insn;
12060           else
12061             {
12062               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12063               place = prev_real_insn (from_insn);
12064               if (tem && place)
12065                 XEXP (tem, 0) = place;
12066               /* If we're deleting the last remaining instruction of a
12067                  libcall sequence, don't add the notes.  */
12068               else if (XEXP (note, 0) == from_insn)
12069                 tem = place = 0;
12070               /* Don't add the dangling REG_RETVAL note.  */
12071               else if (! tem)
12072                 place = 0;
12073             }
12074           break;
12075
12076         case REG_LIBCALL:
12077           /* This is handled similarly to REG_RETVAL.  */
12078           if (!NOTE_P (from_insn))
12079             place = from_insn;
12080           else
12081             {
12082               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12083               place = next_real_insn (from_insn);
12084               if (tem && place)
12085                 XEXP (tem, 0) = place;
12086               /* If we're deleting the last remaining instruction of a
12087                  libcall sequence, don't add the notes.  */
12088               else if (XEXP (note, 0) == from_insn)
12089                 tem = place = 0;
12090               /* Don't add the dangling REG_LIBCALL note.  */
12091               else if (! tem)
12092                 place = 0;
12093             }
12094           break;
12095
12096         case REG_DEAD:
12097           /* If the register is used as an input in I3, it dies there.
12098              Similarly for I2, if it is nonzero and adjacent to I3.
12099
12100              If the register is not used as an input in either I3 or I2
12101              and it is not one of the registers we were supposed to eliminate,
12102              there are two possibilities.  We might have a non-adjacent I2
12103              or we might have somehow eliminated an additional register
12104              from a computation.  For example, we might have had A & B where
12105              we discover that B will always be zero.  In this case we will
12106              eliminate the reference to A.
12107
12108              In both cases, we must search to see if we can find a previous
12109              use of A and put the death note there.  */
12110
12111           if (from_insn
12112               && CALL_P (from_insn)
12113               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12114             place = from_insn;
12115           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12116             place = i3;
12117           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12118                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12119             place = i2;
12120
12121           if (place == 0
12122               && (rtx_equal_p (XEXP (note, 0), elim_i2)
12123                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
12124             break;
12125
12126           if (place == 0)
12127             {
12128               basic_block bb = this_basic_block;
12129
12130               /* You might think you could search back from FROM_INSN
12131                  rather than from I3, but combine tries to split invalid
12132                  combined instructions.  This can result in the old I2
12133                  or I1 moving later in the insn sequence.  */
12134               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12135                 {
12136                   if (! INSN_P (tem))
12137                     {
12138                       if (tem == BB_HEAD (bb))
12139                         break;
12140                       continue;
12141                     }
12142
12143                   /* If the register is being set at TEM, see if that is all
12144                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12145                      into a REG_UNUSED note instead. Don't delete sets to
12146                      global register vars.  */
12147                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12148                        || !global_regs[REGNO (XEXP (note, 0))])
12149                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12150                     {
12151                       rtx set = single_set (tem);
12152                       rtx inner_dest = 0;
12153 #ifdef HAVE_cc0
12154                       rtx cc0_setter = NULL_RTX;
12155 #endif
12156
12157                       if (set != 0)
12158                         for (inner_dest = SET_DEST (set);
12159                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12160                               || GET_CODE (inner_dest) == SUBREG
12161                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12162                              inner_dest = XEXP (inner_dest, 0))
12163                           ;
12164
12165                       /* Verify that it was the set, and not a clobber that
12166                          modified the register.
12167
12168                          CC0 targets must be careful to maintain setter/user
12169                          pairs.  If we cannot delete the setter due to side
12170                          effects, mark the user with an UNUSED note instead
12171                          of deleting it.  */
12172
12173                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12174                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12175 #ifdef HAVE_cc0
12176                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12177                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12178                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12179 #endif
12180                           )
12181                         {
12182                           /* Move the notes and links of TEM elsewhere.
12183                              This might delete other dead insns recursively.
12184                              First set the pattern to something that won't use
12185                              any register.  */
12186                           rtx old_notes = REG_NOTES (tem);
12187
12188                           PATTERN (tem) = pc_rtx;
12189                           REG_NOTES (tem) = NULL;
12190
12191                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12192                                             NULL_RTX, NULL_RTX);
12193                           distribute_links (LOG_LINKS (tem));
12194
12195                           SET_INSN_DELETED (tem);
12196
12197 #ifdef HAVE_cc0
12198                           /* Delete the setter too.  */
12199                           if (cc0_setter)
12200                             {
12201                               PATTERN (cc0_setter) = pc_rtx;
12202                               old_notes = REG_NOTES (cc0_setter);
12203                               REG_NOTES (cc0_setter) = NULL;
12204
12205                               distribute_notes (old_notes, cc0_setter,
12206                                                 cc0_setter, NULL_RTX,
12207                                                 NULL_RTX, NULL_RTX);
12208                               distribute_links (LOG_LINKS (cc0_setter));
12209
12210                               SET_INSN_DELETED (cc0_setter);
12211                             }
12212 #endif
12213                         }
12214                       else
12215                         {
12216                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12217
12218                           /*  If there isn't already a REG_UNUSED note, put one
12219                               here.  Do not place a REG_DEAD note, even if
12220                               the register is also used here; that would not
12221                               match the algorithm used in lifetime analysis
12222                               and can cause the consistency check in the
12223                               scheduler to fail.  */
12224                           if (! find_regno_note (tem, REG_UNUSED,
12225                                                  REGNO (XEXP (note, 0))))
12226                             place = tem;
12227                           break;
12228                         }
12229                     }
12230                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12231                            || (CALL_P (tem)
12232                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12233                     {
12234                       /* This may not be the correct place for the death
12235                          note if FROM_INSN is before TEM, and the reg is
12236                          set between FROM_INSN and TEM.  The reg might
12237                          die two or more times.  An existing death note
12238                          means we are looking at the wrong live range.  */
12239                       if (from_insn
12240                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12241                           && find_regno_note (tem, REG_DEAD,
12242                                               REGNO (XEXP (note, 0))))
12243                         {
12244                           tem = from_insn;
12245                           if (tem == BB_HEAD (bb))
12246                             break;
12247                           continue;
12248                         }
12249
12250                       place = tem;
12251
12252                       /* If we are doing a 3->2 combination, and we have a
12253                          register which formerly died in i3 and was not used
12254                          by i2, which now no longer dies in i3 and is used in
12255                          i2 but does not die in i2, and place is between i2
12256                          and i3, then we may need to move a link from place to
12257                          i2.  */
12258                       if (i2 && INSN_UID (place) <= max_uid_cuid
12259                           && INSN_CUID (place) > INSN_CUID (i2)
12260                           && from_insn
12261                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12262                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12263                         {
12264                           rtx links = LOG_LINKS (place);
12265                           LOG_LINKS (place) = 0;
12266                           distribute_links (links);
12267                         }
12268                       break;
12269                     }
12270
12271                   if (tem == BB_HEAD (bb))
12272                     break;
12273                 }
12274
12275               /* We haven't found an insn for the death note and it
12276                  is still a REG_DEAD note, but we have hit the beginning
12277                  of the block.  If the existing life info says the reg
12278                  was dead, there's nothing left to do.  Otherwise, we'll
12279                  need to do a global life update after combine.  */
12280               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12281                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12282                                       REGNO (XEXP (note, 0))))
12283                 SET_BIT (refresh_blocks, this_basic_block->index);
12284             }
12285
12286           /* If the register is set or already dead at PLACE, we needn't do
12287              anything with this note if it is still a REG_DEAD note.
12288              We check here if it is set at all, not if is it totally replaced,
12289              which is what `dead_or_set_p' checks, so also check for it being
12290              set partially.  */
12291
12292           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12293             {
12294               unsigned int regno = REGNO (XEXP (note, 0));
12295
12296               /* Similarly, if the instruction on which we want to place
12297                  the note is a noop, we'll need do a global live update
12298                  after we remove them in delete_noop_moves.  */
12299               if (noop_move_p (place))
12300                 SET_BIT (refresh_blocks, this_basic_block->index);
12301
12302               if (dead_or_set_p (place, XEXP (note, 0))
12303                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12304                 {
12305                   /* Unless the register previously died in PLACE, clear
12306                      last_death.  [I no longer understand why this is
12307                      being done.] */
12308                   if (reg_stat[regno].last_death != place)
12309                     reg_stat[regno].last_death = 0;
12310                   place = 0;
12311                 }
12312               else
12313                 reg_stat[regno].last_death = place;
12314
12315               /* If this is a death note for a hard reg that is occupying
12316                  multiple registers, ensure that we are still using all
12317                  parts of the object.  If we find a piece of the object
12318                  that is unused, we must arrange for an appropriate REG_DEAD
12319                  note to be added for it.  However, we can't just emit a USE
12320                  and tag the note to it, since the register might actually
12321                  be dead; so we recourse, and the recursive call then finds
12322                  the previous insn that used this register.  */
12323
12324               if (place && regno < FIRST_PSEUDO_REGISTER
12325                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12326                 {
12327                   unsigned int endregno
12328                     = regno + hard_regno_nregs[regno]
12329                                               [GET_MODE (XEXP (note, 0))];
12330                   int all_used = 1;
12331                   unsigned int i;
12332
12333                   for (i = regno; i < endregno; i++)
12334                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12335                          && ! find_regno_fusage (place, USE, i))
12336                         || dead_or_set_regno_p (place, i))
12337                       all_used = 0;
12338
12339                   if (! all_used)
12340                     {
12341                       /* Put only REG_DEAD notes for pieces that are
12342                          not already dead or set.  */
12343
12344                       for (i = regno; i < endregno;
12345                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12346                         {
12347                           rtx piece = regno_reg_rtx[i];
12348                           basic_block bb = this_basic_block;
12349
12350                           if (! dead_or_set_p (place, piece)
12351                               && ! reg_bitfield_target_p (piece,
12352                                                           PATTERN (place)))
12353                             {
12354                               rtx new_note
12355                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12356
12357                               distribute_notes (new_note, place, place,
12358                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12359                             }
12360                           else if (! refers_to_regno_p (i, i + 1,
12361                                                         PATTERN (place), 0)
12362                                    && ! find_regno_fusage (place, USE, i))
12363                             for (tem = PREV_INSN (place); ;
12364                                  tem = PREV_INSN (tem))
12365                               {
12366                                 if (! INSN_P (tem))
12367                                   {
12368                                     if (tem == BB_HEAD (bb))
12369                                       {
12370                                         SET_BIT (refresh_blocks,
12371                                                  this_basic_block->index);
12372                                         break;
12373                                       }
12374                                     continue;
12375                                   }
12376                                 if (dead_or_set_p (tem, piece)
12377                                     || reg_bitfield_target_p (piece,
12378                                                               PATTERN (tem)))
12379                                   {
12380                                     REG_NOTES (tem)
12381                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12382                                                            REG_NOTES (tem));
12383                                     break;
12384                                   }
12385                               }
12386
12387                         }
12388
12389                       place = 0;
12390                     }
12391                 }
12392             }
12393           break;
12394
12395         default:
12396           /* Any other notes should not be present at this point in the
12397              compilation.  */
12398           gcc_unreachable ();
12399         }
12400
12401       if (place)
12402         {
12403           XEXP (note, 1) = REG_NOTES (place);
12404           REG_NOTES (place) = note;
12405         }
12406       else if ((REG_NOTE_KIND (note) == REG_DEAD
12407                 || REG_NOTE_KIND (note) == REG_UNUSED)
12408                && REG_P (XEXP (note, 0)))
12409         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12410
12411       if (place2)
12412         {
12413           if ((REG_NOTE_KIND (note) == REG_DEAD
12414                || REG_NOTE_KIND (note) == REG_UNUSED)
12415               && REG_P (XEXP (note, 0)))
12416             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12417
12418           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12419                                                REG_NOTE_KIND (note),
12420                                                XEXP (note, 0),
12421                                                REG_NOTES (place2));
12422         }
12423     }
12424 }
12425 \f
12426 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12427    I3, I2, and I1 to new locations.  This is also called to add a link
12428    pointing at I3 when I3's destination is changed.  */
12429
12430 static void
12431 distribute_links (rtx links)
12432 {
12433   rtx link, next_link;
12434
12435   for (link = links; link; link = next_link)
12436     {
12437       rtx place = 0;
12438       rtx insn;
12439       rtx set, reg;
12440
12441       next_link = XEXP (link, 1);
12442
12443       /* If the insn that this link points to is a NOTE or isn't a single
12444          set, ignore it.  In the latter case, it isn't clear what we
12445          can do other than ignore the link, since we can't tell which
12446          register it was for.  Such links wouldn't be used by combine
12447          anyway.
12448
12449          It is not possible for the destination of the target of the link to
12450          have been changed by combine.  The only potential of this is if we
12451          replace I3, I2, and I1 by I3 and I2.  But in that case the
12452          destination of I2 also remains unchanged.  */
12453
12454       if (NOTE_P (XEXP (link, 0))
12455           || (set = single_set (XEXP (link, 0))) == 0)
12456         continue;
12457
12458       reg = SET_DEST (set);
12459       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12460              || GET_CODE (reg) == STRICT_LOW_PART)
12461         reg = XEXP (reg, 0);
12462
12463       /* A LOG_LINK is defined as being placed on the first insn that uses
12464          a register and points to the insn that sets the register.  Start
12465          searching at the next insn after the target of the link and stop
12466          when we reach a set of the register or the end of the basic block.
12467
12468          Note that this correctly handles the link that used to point from
12469          I3 to I2.  Also note that not much searching is typically done here
12470          since most links don't point very far away.  */
12471
12472       for (insn = NEXT_INSN (XEXP (link, 0));
12473            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12474                      || BB_HEAD (this_basic_block->next_bb) != insn));
12475            insn = NEXT_INSN (insn))
12476         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12477           {
12478             if (reg_referenced_p (reg, PATTERN (insn)))
12479               place = insn;
12480             break;
12481           }
12482         else if (CALL_P (insn)
12483                  && find_reg_fusage (insn, USE, reg))
12484           {
12485             place = insn;
12486             break;
12487           }
12488         else if (INSN_P (insn) && reg_set_p (reg, insn))
12489           break;
12490
12491       /* If we found a place to put the link, place it there unless there
12492          is already a link to the same insn as LINK at that point.  */
12493
12494       if (place)
12495         {
12496           rtx link2;
12497
12498           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12499             if (XEXP (link2, 0) == XEXP (link, 0))
12500               break;
12501
12502           if (link2 == 0)
12503             {
12504               XEXP (link, 1) = LOG_LINKS (place);
12505               LOG_LINKS (place) = link;
12506
12507               /* Set added_links_insn to the earliest insn we added a
12508                  link to.  */
12509               if (added_links_insn == 0
12510                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12511                 added_links_insn = place;
12512             }
12513         }
12514     }
12515 }
12516 \f
12517 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12518    Check whether the expression pointer to by LOC is a register or
12519    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12520    Otherwise return zero.  */
12521
12522 static int
12523 unmentioned_reg_p_1 (rtx *loc, void *expr)
12524 {
12525   rtx x = *loc;
12526
12527   if (x != NULL_RTX
12528       && (REG_P (x) || MEM_P (x))
12529       && ! reg_mentioned_p (x, (rtx) expr))
12530     return 1;
12531   return 0;
12532 }
12533
12534 /* Check for any register or memory mentioned in EQUIV that is not
12535    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12536    of EXPR where some registers may have been replaced by constants.  */
12537
12538 static bool
12539 unmentioned_reg_p (rtx equiv, rtx expr)
12540 {
12541   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12542 }
12543 \f
12544 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12545
12546 static int
12547 insn_cuid (rtx insn)
12548 {
12549   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12550          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12551     insn = NEXT_INSN (insn);
12552
12553   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12554
12555   return INSN_CUID (insn);
12556 }
12557 \f
12558 void
12559 dump_combine_stats (FILE *file)
12560 {
12561   fprintf
12562     (file,
12563      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12564      combine_attempts, combine_merges, combine_extras, combine_successes);
12565 }
12566
12567 void
12568 dump_combine_total_stats (FILE *file)
12569 {
12570   fprintf
12571     (file,
12572      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12573      total_attempts, total_merges, total_extras, total_successes);
12574 }
12575 \f
12576
12577 static bool
12578 gate_handle_combine (void)
12579 {
12580   return (optimize > 0);
12581 }
12582
12583 /* Try combining insns through substitution.  */
12584 static unsigned int
12585 rest_of_handle_combine (void)
12586 {
12587   int rebuild_jump_labels_after_combine
12588     = combine_instructions (get_insns (), max_reg_num ());
12589
12590   /* Combining insns may have turned an indirect jump into a
12591      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12592      instructions.  */
12593   if (rebuild_jump_labels_after_combine)
12594     {
12595       timevar_push (TV_JUMP);
12596       rebuild_jump_labels (get_insns ());
12597       timevar_pop (TV_JUMP);
12598
12599       delete_dead_jumptables ();
12600       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12601     }
12602   return 0;
12603 }
12604
12605 struct tree_opt_pass pass_combine =
12606 {
12607   "combine",                            /* name */
12608   gate_handle_combine,                  /* gate */
12609   rest_of_handle_combine,               /* execute */
12610   NULL,                                 /* sub */
12611   NULL,                                 /* next */
12612   0,                                    /* static_pass_number */
12613   TV_COMBINE,                           /* tv_id */
12614   0,                                    /* properties_required */
12615   0,                                    /* properties_provided */
12616   0,                                    /* properties_destroyed */
12617   0,                                    /* todo_flags_start */
12618   TODO_dump_func |
12619   TODO_ggc_collect,                     /* todo_flags_finish */
12620   'c'                                   /* letter */
12621 };
12622