1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack
{
76 int first_gp_reg_save
; /* first callee saved GP register used */
77 int first_fp_reg_save
; /* first callee saved FP register used */
78 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
79 int lr_save_p
; /* true if the link reg needs to be saved */
80 int cr_save_p
; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask
; /* mask of vec registers to save */
82 int push_p
; /* true if we need to allocate stack space */
83 int calls_p
; /* true if the function makes any calls */
84 int world_save_p
; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi
; /* which ABI to use */
87 int gp_save_offset
; /* offset to save GP regs from initial SP */
88 int fp_save_offset
; /* offset to save FP regs from initial SP */
89 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset
; /* offset to save LR from initial SP */
91 int cr_save_offset
; /* offset to save CR from initial SP */
92 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset
; /* offset to save the varargs registers */
95 int ehrd_offset
; /* offset to EH return data */
96 int reg_size
; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size
; /* variable save area size */
98 int parm_size
; /* outgoing parameter size */
99 int save_size
; /* save area size */
100 int fixed_size
; /* fixed size of stack frame */
101 int gp_size
; /* size of saved GP registers */
102 int fp_size
; /* size of saved FP registers */
103 int altivec_size
; /* size of saved AltiVec registers */
104 int cr_size
; /* size to hold CR if not in save_size */
105 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size
; /* size of altivec alignment padding if
108 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size
;
110 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
111 int spe_64bit_regs_used
;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function
GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame
;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name
;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p
;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset
;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot
;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu
;
138 struct rs6000_cpu_select rs6000_select
[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 static GTY(()) bool rs6000_cell_dont_microcode
;
148 /* Always emit branch hint bits. */
149 static GTY(()) bool rs6000_always_hint
;
151 /* Schedule instructions for group formation. */
152 static GTY(()) bool rs6000_sched_groups
;
154 /* Align branch targets. */
155 static GTY(()) bool rs6000_align_branch_targets
;
157 /* Support for -msched-costly-dep option. */
158 const char *rs6000_sched_costly_dep_str
;
159 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
161 /* Support for -minsert-sched-nops option. */
162 const char *rs6000_sched_insert_nops_str
;
163 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
165 /* Support targetm.vectorize.builtin_mask_for_load. */
166 static GTY(()) tree altivec_builtin_mask_for_load
;
168 /* Size of long double. */
169 int rs6000_long_double_type_size
;
171 /* IEEE quad extended precision long double. */
174 /* Nonzero to use AltiVec ABI. */
175 int rs6000_altivec_abi
;
177 /* Nonzero if we want SPE SIMD instructions. */
180 /* Nonzero if we want SPE ABI extensions. */
183 /* Nonzero to use isel instructions. */
186 /* Nonzero if floating point operations are done in the GPRs. */
187 int rs6000_float_gprs
= 0;
189 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
190 int rs6000_darwin64_abi
;
192 /* Set to nonzero once AIX common-mode calls have been defined. */
193 static GTY(()) int common_mode_defined
;
195 /* Save information from a "cmpxx" operation until the branch or scc is
197 rtx rs6000_compare_op0
, rs6000_compare_op1
;
198 int rs6000_compare_fp_p
;
200 /* Label number of label created for -mrelocatable, to call to so we can
201 get the address of the GOT section */
202 int rs6000_pic_labelno
;
205 /* Which abi to adhere to */
206 const char *rs6000_abi_name
;
208 /* Semantics of the small data area */
209 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
211 /* Which small data model to use */
212 const char *rs6000_sdata_name
= (char *)0;
214 /* Counter for labels which are to be placed in .fixup. */
215 int fixuplabelno
= 0;
218 /* Bit size of immediate TLS offsets and string from which it is decoded. */
219 int rs6000_tls_size
= 32;
220 const char *rs6000_tls_size_string
;
222 /* ABI enumeration available for subtarget to use. */
223 enum rs6000_abi rs6000_current_abi
;
225 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
229 const char *rs6000_debug_name
;
230 int rs6000_debug_stack
; /* debug stack applications */
231 int rs6000_debug_arg
; /* debug argument handling */
233 /* Value is TRUE if register/mode pair is acceptable. */
234 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
236 /* Built in types. */
238 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
239 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
241 const char *rs6000_traceback_name
;
243 traceback_default
= 0,
249 /* Flag to say the TOC is initialized */
251 char toc_label_name
[10];
253 /* Cached value of rs6000_variable_issue. This is cached in
254 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
255 static short cached_can_issue_more
;
257 static GTY(()) section
*read_only_data_section
;
258 static GTY(()) section
*private_data_section
;
259 static GTY(()) section
*read_only_private_data_section
;
260 static GTY(()) section
*sdata2_section
;
261 static GTY(()) section
*toc_section
;
263 /* Control alignment for fields within structures. */
264 /* String from -malign-XXXXX. */
265 int rs6000_alignment_flags
;
267 /* True for any options that were explicitly set. */
269 bool aix_struct_ret
; /* True if -maix-struct-ret was used. */
270 bool alignment
; /* True if -malign- was used. */
271 bool spe_abi
; /* True if -mabi=spe/no-spe was used. */
272 bool altivec_abi
; /* True if -mabi=altivec/no-altivec used. */
273 bool spe
; /* True if -mspe= was used. */
274 bool float_gprs
; /* True if -mfloat-gprs= was used. */
275 bool isel
; /* True if -misel was used. */
276 bool long_double
; /* True if -mlong-double- was used. */
277 bool ieee
; /* True if -mabi=ieee/ibmlongdouble used. */
278 bool vrsave
; /* True if -mvrsave was used. */
279 } rs6000_explicit_options
;
281 struct builtin_description
283 /* mask is not const because we're going to alter it below. This
284 nonsense will go away when we rewrite the -march infrastructure
285 to give us more target flag bits. */
287 const enum insn_code icode
;
288 const char *const name
;
289 const enum rs6000_builtins code
;
292 /* Target cpu costs. */
294 struct processor_costs
{
295 const int mulsi
; /* cost of SImode multiplication. */
296 const int mulsi_const
; /* cost of SImode multiplication by constant. */
297 const int mulsi_const9
; /* cost of SImode mult by short constant. */
298 const int muldi
; /* cost of DImode multiplication. */
299 const int divsi
; /* cost of SImode division. */
300 const int divdi
; /* cost of DImode division. */
301 const int fp
; /* cost of simple SFmode and DFmode insns. */
302 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
303 const int sdiv
; /* cost of SFmode division (fdivs). */
304 const int ddiv
; /* cost of DFmode division (fdiv). */
305 const int cache_line_size
; /* cache line size in bytes. */
306 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
307 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
308 const int simultaneous_prefetches
; /* number of parallel prefetch
312 const struct processor_costs
*rs6000_cost
;
314 /* Processor costs (relative to an add) */
316 /* Instruction size costs on 32bit processors. */
318 struct processor_costs size32_cost
= {
319 COSTS_N_INSNS (1), /* mulsi */
320 COSTS_N_INSNS (1), /* mulsi_const */
321 COSTS_N_INSNS (1), /* mulsi_const9 */
322 COSTS_N_INSNS (1), /* muldi */
323 COSTS_N_INSNS (1), /* divsi */
324 COSTS_N_INSNS (1), /* divdi */
325 COSTS_N_INSNS (1), /* fp */
326 COSTS_N_INSNS (1), /* dmul */
327 COSTS_N_INSNS (1), /* sdiv */
328 COSTS_N_INSNS (1), /* ddiv */
335 /* Instruction size costs on 64bit processors. */
337 struct processor_costs size64_cost
= {
338 COSTS_N_INSNS (1), /* mulsi */
339 COSTS_N_INSNS (1), /* mulsi_const */
340 COSTS_N_INSNS (1), /* mulsi_const9 */
341 COSTS_N_INSNS (1), /* muldi */
342 COSTS_N_INSNS (1), /* divsi */
343 COSTS_N_INSNS (1), /* divdi */
344 COSTS_N_INSNS (1), /* fp */
345 COSTS_N_INSNS (1), /* dmul */
346 COSTS_N_INSNS (1), /* sdiv */
347 COSTS_N_INSNS (1), /* ddiv */
354 /* Instruction costs on RIOS1 processors. */
356 struct processor_costs rios1_cost
= {
357 COSTS_N_INSNS (5), /* mulsi */
358 COSTS_N_INSNS (4), /* mulsi_const */
359 COSTS_N_INSNS (3), /* mulsi_const9 */
360 COSTS_N_INSNS (5), /* muldi */
361 COSTS_N_INSNS (19), /* divsi */
362 COSTS_N_INSNS (19), /* divdi */
363 COSTS_N_INSNS (2), /* fp */
364 COSTS_N_INSNS (2), /* dmul */
365 COSTS_N_INSNS (19), /* sdiv */
366 COSTS_N_INSNS (19), /* ddiv */
367 128, /* cache line size */
373 /* Instruction costs on RIOS2 processors. */
375 struct processor_costs rios2_cost
= {
376 COSTS_N_INSNS (2), /* mulsi */
377 COSTS_N_INSNS (2), /* mulsi_const */
378 COSTS_N_INSNS (2), /* mulsi_const9 */
379 COSTS_N_INSNS (2), /* muldi */
380 COSTS_N_INSNS (13), /* divsi */
381 COSTS_N_INSNS (13), /* divdi */
382 COSTS_N_INSNS (2), /* fp */
383 COSTS_N_INSNS (2), /* dmul */
384 COSTS_N_INSNS (17), /* sdiv */
385 COSTS_N_INSNS (17), /* ddiv */
386 256, /* cache line size */
392 /* Instruction costs on RS64A processors. */
394 struct processor_costs rs64a_cost
= {
395 COSTS_N_INSNS (20), /* mulsi */
396 COSTS_N_INSNS (12), /* mulsi_const */
397 COSTS_N_INSNS (8), /* mulsi_const9 */
398 COSTS_N_INSNS (34), /* muldi */
399 COSTS_N_INSNS (65), /* divsi */
400 COSTS_N_INSNS (67), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (4), /* dmul */
403 COSTS_N_INSNS (31), /* sdiv */
404 COSTS_N_INSNS (31), /* ddiv */
405 128, /* cache line size */
411 /* Instruction costs on MPCCORE processors. */
413 struct processor_costs mpccore_cost
= {
414 COSTS_N_INSNS (2), /* mulsi */
415 COSTS_N_INSNS (2), /* mulsi_const */
416 COSTS_N_INSNS (2), /* mulsi_const9 */
417 COSTS_N_INSNS (2), /* muldi */
418 COSTS_N_INSNS (6), /* divsi */
419 COSTS_N_INSNS (6), /* divdi */
420 COSTS_N_INSNS (4), /* fp */
421 COSTS_N_INSNS (5), /* dmul */
422 COSTS_N_INSNS (10), /* sdiv */
423 COSTS_N_INSNS (17), /* ddiv */
424 32, /* cache line size */
430 /* Instruction costs on PPC403 processors. */
432 struct processor_costs ppc403_cost
= {
433 COSTS_N_INSNS (4), /* mulsi */
434 COSTS_N_INSNS (4), /* mulsi_const */
435 COSTS_N_INSNS (4), /* mulsi_const9 */
436 COSTS_N_INSNS (4), /* muldi */
437 COSTS_N_INSNS (33), /* divsi */
438 COSTS_N_INSNS (33), /* divdi */
439 COSTS_N_INSNS (11), /* fp */
440 COSTS_N_INSNS (11), /* dmul */
441 COSTS_N_INSNS (11), /* sdiv */
442 COSTS_N_INSNS (11), /* ddiv */
443 32, /* cache line size */
449 /* Instruction costs on PPC405 processors. */
451 struct processor_costs ppc405_cost
= {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (3), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (35), /* divsi */
457 COSTS_N_INSNS (35), /* divdi */
458 COSTS_N_INSNS (11), /* fp */
459 COSTS_N_INSNS (11), /* dmul */
460 COSTS_N_INSNS (11), /* sdiv */
461 COSTS_N_INSNS (11), /* ddiv */
462 32, /* cache line size */
468 /* Instruction costs on PPC440 processors. */
470 struct processor_costs ppc440_cost
= {
471 COSTS_N_INSNS (3), /* mulsi */
472 COSTS_N_INSNS (2), /* mulsi_const */
473 COSTS_N_INSNS (2), /* mulsi_const9 */
474 COSTS_N_INSNS (3), /* muldi */
475 COSTS_N_INSNS (34), /* divsi */
476 COSTS_N_INSNS (34), /* divdi */
477 COSTS_N_INSNS (5), /* fp */
478 COSTS_N_INSNS (5), /* dmul */
479 COSTS_N_INSNS (19), /* sdiv */
480 COSTS_N_INSNS (33), /* ddiv */
481 32, /* cache line size */
487 /* Instruction costs on PPC601 processors. */
489 struct processor_costs ppc601_cost
= {
490 COSTS_N_INSNS (5), /* mulsi */
491 COSTS_N_INSNS (5), /* mulsi_const */
492 COSTS_N_INSNS (5), /* mulsi_const9 */
493 COSTS_N_INSNS (5), /* muldi */
494 COSTS_N_INSNS (36), /* divsi */
495 COSTS_N_INSNS (36), /* divdi */
496 COSTS_N_INSNS (4), /* fp */
497 COSTS_N_INSNS (5), /* dmul */
498 COSTS_N_INSNS (17), /* sdiv */
499 COSTS_N_INSNS (31), /* ddiv */
500 32, /* cache line size */
506 /* Instruction costs on PPC603 processors. */
508 struct processor_costs ppc603_cost
= {
509 COSTS_N_INSNS (5), /* mulsi */
510 COSTS_N_INSNS (3), /* mulsi_const */
511 COSTS_N_INSNS (2), /* mulsi_const9 */
512 COSTS_N_INSNS (5), /* muldi */
513 COSTS_N_INSNS (37), /* divsi */
514 COSTS_N_INSNS (37), /* divdi */
515 COSTS_N_INSNS (3), /* fp */
516 COSTS_N_INSNS (4), /* dmul */
517 COSTS_N_INSNS (18), /* sdiv */
518 COSTS_N_INSNS (33), /* ddiv */
519 32, /* cache line size */
525 /* Instruction costs on PPC604 processors. */
527 struct processor_costs ppc604_cost
= {
528 COSTS_N_INSNS (4), /* mulsi */
529 COSTS_N_INSNS (4), /* mulsi_const */
530 COSTS_N_INSNS (4), /* mulsi_const9 */
531 COSTS_N_INSNS (4), /* muldi */
532 COSTS_N_INSNS (20), /* divsi */
533 COSTS_N_INSNS (20), /* divdi */
534 COSTS_N_INSNS (3), /* fp */
535 COSTS_N_INSNS (3), /* dmul */
536 COSTS_N_INSNS (18), /* sdiv */
537 COSTS_N_INSNS (32), /* ddiv */
538 32, /* cache line size */
544 /* Instruction costs on PPC604e processors. */
546 struct processor_costs ppc604e_cost
= {
547 COSTS_N_INSNS (2), /* mulsi */
548 COSTS_N_INSNS (2), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (2), /* muldi */
551 COSTS_N_INSNS (20), /* divsi */
552 COSTS_N_INSNS (20), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (18), /* sdiv */
556 COSTS_N_INSNS (32), /* ddiv */
557 32, /* cache line size */
563 /* Instruction costs on PPC620 processors. */
565 struct processor_costs ppc620_cost
= {
566 COSTS_N_INSNS (5), /* mulsi */
567 COSTS_N_INSNS (4), /* mulsi_const */
568 COSTS_N_INSNS (3), /* mulsi_const9 */
569 COSTS_N_INSNS (7), /* muldi */
570 COSTS_N_INSNS (21), /* divsi */
571 COSTS_N_INSNS (37), /* divdi */
572 COSTS_N_INSNS (3), /* fp */
573 COSTS_N_INSNS (3), /* dmul */
574 COSTS_N_INSNS (18), /* sdiv */
575 COSTS_N_INSNS (32), /* ddiv */
576 128, /* cache line size */
582 /* Instruction costs on PPC630 processors. */
584 struct processor_costs ppc630_cost
= {
585 COSTS_N_INSNS (5), /* mulsi */
586 COSTS_N_INSNS (4), /* mulsi_const */
587 COSTS_N_INSNS (3), /* mulsi_const9 */
588 COSTS_N_INSNS (7), /* muldi */
589 COSTS_N_INSNS (21), /* divsi */
590 COSTS_N_INSNS (37), /* divdi */
591 COSTS_N_INSNS (3), /* fp */
592 COSTS_N_INSNS (3), /* dmul */
593 COSTS_N_INSNS (17), /* sdiv */
594 COSTS_N_INSNS (21), /* ddiv */
595 128, /* cache line size */
601 /* Instruction costs on Cell processor. */
602 /* COSTS_N_INSNS (1) ~ one add. */
604 struct processor_costs ppccell_cost
= {
605 COSTS_N_INSNS (9/2)+2, /* mulsi */
606 COSTS_N_INSNS (6/2), /* mulsi_const */
607 COSTS_N_INSNS (6/2), /* mulsi_const9 */
608 COSTS_N_INSNS (15/2)+2, /* muldi */
609 COSTS_N_INSNS (38/2), /* divsi */
610 COSTS_N_INSNS (70/2), /* divdi */
611 COSTS_N_INSNS (10/2), /* fp */
612 COSTS_N_INSNS (10/2), /* dmul */
613 COSTS_N_INSNS (74/2), /* sdiv */
614 COSTS_N_INSNS (74/2), /* ddiv */
615 128, /* cache line size */
621 /* Instruction costs on PPC750 and PPC7400 processors. */
623 struct processor_costs ppc750_cost
= {
624 COSTS_N_INSNS (5), /* mulsi */
625 COSTS_N_INSNS (3), /* mulsi_const */
626 COSTS_N_INSNS (2), /* mulsi_const9 */
627 COSTS_N_INSNS (5), /* muldi */
628 COSTS_N_INSNS (17), /* divsi */
629 COSTS_N_INSNS (17), /* divdi */
630 COSTS_N_INSNS (3), /* fp */
631 COSTS_N_INSNS (3), /* dmul */
632 COSTS_N_INSNS (17), /* sdiv */
633 COSTS_N_INSNS (31), /* ddiv */
634 32, /* cache line size */
640 /* Instruction costs on PPC7450 processors. */
642 struct processor_costs ppc7450_cost
= {
643 COSTS_N_INSNS (4), /* mulsi */
644 COSTS_N_INSNS (3), /* mulsi_const */
645 COSTS_N_INSNS (3), /* mulsi_const9 */
646 COSTS_N_INSNS (4), /* muldi */
647 COSTS_N_INSNS (23), /* divsi */
648 COSTS_N_INSNS (23), /* divdi */
649 COSTS_N_INSNS (5), /* fp */
650 COSTS_N_INSNS (5), /* dmul */
651 COSTS_N_INSNS (21), /* sdiv */
652 COSTS_N_INSNS (35), /* ddiv */
653 32, /* cache line size */
659 /* Instruction costs on PPC8540 processors. */
661 struct processor_costs ppc8540_cost
= {
662 COSTS_N_INSNS (4), /* mulsi */
663 COSTS_N_INSNS (4), /* mulsi_const */
664 COSTS_N_INSNS (4), /* mulsi_const9 */
665 COSTS_N_INSNS (4), /* muldi */
666 COSTS_N_INSNS (19), /* divsi */
667 COSTS_N_INSNS (19), /* divdi */
668 COSTS_N_INSNS (4), /* fp */
669 COSTS_N_INSNS (4), /* dmul */
670 COSTS_N_INSNS (29), /* sdiv */
671 COSTS_N_INSNS (29), /* ddiv */
672 32, /* cache line size */
675 1, /* prefetch streams /*/
678 /* Instruction costs on E300C2 and E300C3 cores. */
680 struct processor_costs ppce300c2c3_cost
= {
681 COSTS_N_INSNS (4), /* mulsi */
682 COSTS_N_INSNS (4), /* mulsi_const */
683 COSTS_N_INSNS (4), /* mulsi_const9 */
684 COSTS_N_INSNS (4), /* muldi */
685 COSTS_N_INSNS (19), /* divsi */
686 COSTS_N_INSNS (19), /* divdi */
687 COSTS_N_INSNS (3), /* fp */
688 COSTS_N_INSNS (4), /* dmul */
689 COSTS_N_INSNS (18), /* sdiv */
690 COSTS_N_INSNS (33), /* ddiv */
694 1, /* prefetch streams /*/
697 /* Instruction costs on PPCE500MC processors. */
699 struct processor_costs ppce500mc_cost
= {
700 COSTS_N_INSNS (4), /* mulsi */
701 COSTS_N_INSNS (4), /* mulsi_const */
702 COSTS_N_INSNS (4), /* mulsi_const9 */
703 COSTS_N_INSNS (4), /* muldi */
704 COSTS_N_INSNS (14), /* divsi */
705 COSTS_N_INSNS (14), /* divdi */
706 COSTS_N_INSNS (8), /* fp */
707 COSTS_N_INSNS (10), /* dmul */
708 COSTS_N_INSNS (36), /* sdiv */
709 COSTS_N_INSNS (66), /* ddiv */
710 64, /* cache line size */
713 1, /* prefetch streams /*/
716 /* Instruction costs on POWER4 and POWER5 processors. */
718 struct processor_costs power4_cost
= {
719 COSTS_N_INSNS (3), /* mulsi */
720 COSTS_N_INSNS (2), /* mulsi_const */
721 COSTS_N_INSNS (2), /* mulsi_const9 */
722 COSTS_N_INSNS (4), /* muldi */
723 COSTS_N_INSNS (18), /* divsi */
724 COSTS_N_INSNS (34), /* divdi */
725 COSTS_N_INSNS (3), /* fp */
726 COSTS_N_INSNS (3), /* dmul */
727 COSTS_N_INSNS (17), /* sdiv */
728 COSTS_N_INSNS (17), /* ddiv */
729 128, /* cache line size */
732 8, /* prefetch streams /*/
735 /* Instruction costs on POWER6 processors. */
737 struct processor_costs power6_cost
= {
738 COSTS_N_INSNS (8), /* mulsi */
739 COSTS_N_INSNS (8), /* mulsi_const */
740 COSTS_N_INSNS (8), /* mulsi_const9 */
741 COSTS_N_INSNS (8), /* muldi */
742 COSTS_N_INSNS (22), /* divsi */
743 COSTS_N_INSNS (28), /* divdi */
744 COSTS_N_INSNS (3), /* fp */
745 COSTS_N_INSNS (3), /* dmul */
746 COSTS_N_INSNS (13), /* sdiv */
747 COSTS_N_INSNS (16), /* ddiv */
748 128, /* cache line size */
751 16, /* prefetch streams */
755 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
756 static const char *rs6000_invalid_within_doloop (const_rtx
);
757 static rtx
rs6000_generate_compare (enum rtx_code
);
758 static void rs6000_emit_stack_tie (void);
759 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
760 static bool spe_func_has_64bit_regs_p (void);
761 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
763 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
764 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int, int);
765 static unsigned rs6000_hash_constant (rtx
);
766 static unsigned toc_hash_function (const void *);
767 static int toc_hash_eq (const void *, const void *);
768 static int constant_pool_expr_1 (rtx
, int *, int *);
769 static bool constant_pool_expr_p (rtx
);
770 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
771 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
772 static struct machine_function
* rs6000_init_machine_status (void);
773 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
774 static bool no_global_regs_above (int, bool);
775 #ifdef HAVE_GAS_HIDDEN
776 static void rs6000_assemble_visibility (tree
, int);
778 static int rs6000_ra_ever_killed (void);
779 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
780 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
781 static bool rs6000_ms_bitfield_layout_p (const_tree
);
782 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
783 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
784 static const char *rs6000_mangle_type (const_tree
);
785 extern const struct attribute_spec rs6000_attribute_table
[];
786 static void rs6000_set_default_type_attributes (tree
);
787 static rtx
rs6000_savres_routine_sym (rs6000_stack_t
*, bool, bool, bool);
788 static void rs6000_emit_stack_reset (rs6000_stack_t
*, rtx
, rtx
, int, bool);
789 static rtx
rs6000_make_savres_rtx (rs6000_stack_t
*, rtx
, int,
790 enum machine_mode
, bool, bool, bool);
791 static bool rs6000_reg_live_or_pic_offset_p (int);
792 static int rs6000_savres_strategy (rs6000_stack_t
*, bool, int, int);
793 static void rs6000_restore_saved_cr (rtx
, int);
794 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
795 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
796 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
798 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
799 static bool rs6000_return_in_memory (const_tree
, const_tree
);
800 static void rs6000_file_start (void);
802 static int rs6000_elf_reloc_rw_mask (void);
803 static void rs6000_elf_asm_out_constructor (rtx
, int);
804 static void rs6000_elf_asm_out_destructor (rtx
, int);
805 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
806 static void rs6000_elf_asm_init_sections (void);
807 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
808 unsigned HOST_WIDE_INT
);
809 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
812 static bool rs6000_use_blocks_for_constant_p (enum machine_mode
, const_rtx
);
813 static void rs6000_alloc_sdmode_stack_slot (void);
814 static void rs6000_instantiate_decls (void);
816 static void rs6000_xcoff_asm_output_anchor (rtx
);
817 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
818 static void rs6000_xcoff_asm_init_sections (void);
819 static int rs6000_xcoff_reloc_rw_mask (void);
820 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
821 static section
*rs6000_xcoff_select_section (tree
, int,
822 unsigned HOST_WIDE_INT
);
823 static void rs6000_xcoff_unique_section (tree
, int);
824 static section
*rs6000_xcoff_select_rtx_section
825 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
826 static const char * rs6000_xcoff_strip_name_encoding (const char *);
827 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
828 static void rs6000_xcoff_file_start (void);
829 static void rs6000_xcoff_file_end (void);
831 static int rs6000_variable_issue (FILE *, int, rtx
, int);
832 static bool rs6000_rtx_costs (rtx
, int, int, int *);
833 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
834 static void rs6000_sched_init (FILE *, int, int);
835 static bool is_microcoded_insn (rtx
);
836 static bool is_nonpipeline_insn (rtx
);
837 static bool is_cracked_insn (rtx
);
838 static bool is_branch_slot_insn (rtx
);
839 static bool is_load_insn (rtx
);
840 static rtx
get_store_dest (rtx pat
);
841 static bool is_store_insn (rtx
);
842 static bool set_to_load_agen (rtx
,rtx
);
843 static bool adjacent_mem_locations (rtx
,rtx
);
844 static int rs6000_adjust_priority (rtx
, int);
845 static int rs6000_issue_rate (void);
846 static bool rs6000_is_costly_dependence (dep_t
, int, int);
847 static rtx
get_next_active_insn (rtx
, rtx
);
848 static bool insn_terminates_group_p (rtx
, enum group_termination
);
849 static bool insn_must_be_first_in_group (rtx
);
850 static bool insn_must_be_last_in_group (rtx
);
851 static bool is_costly_group (rtx
*, rtx
);
852 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
853 static int redefine_groups (FILE *, int, rtx
, rtx
);
854 static int pad_groups (FILE *, int, rtx
, rtx
);
855 static void rs6000_sched_finish (FILE *, int);
856 static int rs6000_sched_reorder (FILE *, int, rtx
*, int *, int);
857 static int rs6000_sched_reorder2 (FILE *, int, rtx
*, int *, int);
858 static int rs6000_use_sched_lookahead (void);
859 static int rs6000_use_sched_lookahead_guard (rtx
);
860 static tree
rs6000_builtin_reciprocal (unsigned int, bool, bool);
861 static tree
rs6000_builtin_mask_for_load (void);
862 static tree
rs6000_builtin_mul_widen_even (tree
);
863 static tree
rs6000_builtin_mul_widen_odd (tree
);
864 static tree
rs6000_builtin_conversion (enum tree_code
, tree
);
866 static void def_builtin (int, const char *, tree
, int);
867 static bool rs6000_vector_alignment_reachable (const_tree
, bool);
868 static void rs6000_init_builtins (void);
869 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
870 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
871 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
872 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
873 static void altivec_init_builtins (void);
874 static void rs6000_common_init_builtins (void);
875 static void rs6000_init_libfuncs (void);
877 static void paired_init_builtins (void);
878 static rtx
paired_expand_builtin (tree
, rtx
, bool *);
879 static rtx
paired_expand_lv_builtin (enum insn_code
, tree
, rtx
);
880 static rtx
paired_expand_stv_builtin (enum insn_code
, tree
);
881 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
883 static void enable_mask_for_builtins (struct builtin_description
*, int,
884 enum rs6000_builtins
,
885 enum rs6000_builtins
);
886 static tree
build_opaque_vector_type (tree
, int);
887 static void spe_init_builtins (void);
888 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
889 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
890 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
891 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
892 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
893 static rs6000_stack_t
*rs6000_stack_info (void);
894 static void debug_stack_info (rs6000_stack_t
*);
896 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
897 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
898 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
899 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
900 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
901 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
902 const char *, tree
, rtx
);
903 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
904 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
905 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
906 static rtx
altivec_expand_vec_set_builtin (tree
);
907 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
908 static int get_element_number (tree
, tree
);
909 static bool rs6000_handle_option (size_t, const char *, int);
910 static void rs6000_parse_tls_size_option (void);
911 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
912 static int first_altivec_reg_to_save (void);
913 static unsigned int compute_vrsave_mask (void);
914 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
915 static void is_altivec_return_reg (rtx
, void *);
916 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
917 int easy_vector_constant (rtx
, enum machine_mode
);
918 static bool rs6000_is_opaque_type (const_tree
);
919 static rtx
rs6000_dwarf_register_span (rtx
);
920 static void rs6000_init_dwarf_reg_sizes_extra (tree
);
921 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
922 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
923 static rtx
rs6000_tls_get_addr (void);
924 static rtx
rs6000_got_sym (void);
925 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
926 static const char *rs6000_get_some_local_dynamic_name (void);
927 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
928 static rtx
rs6000_complex_function_value (enum machine_mode
);
929 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
930 enum machine_mode
, tree
);
931 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
933 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
934 tree
, HOST_WIDE_INT
);
935 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
938 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
939 const_tree
, HOST_WIDE_INT
,
941 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
, int, bool);
942 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
943 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
944 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
945 enum machine_mode
, tree
,
947 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
949 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
951 static const char *invalid_arg_for_unprototyped_fn (const_tree
, const_tree
, const_tree
);
953 static void macho_branch_islands (void);
954 static int no_previous_def (tree function_name
);
955 static tree
get_prev_label (tree function_name
);
956 static void rs6000_darwin_file_start (void);
959 static tree
rs6000_build_builtin_va_list (void);
960 static void rs6000_va_start (tree
, rtx
);
961 static tree
rs6000_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
962 static bool rs6000_must_pass_in_stack (enum machine_mode
, const_tree
);
963 static bool rs6000_scalar_mode_supported_p (enum machine_mode
);
964 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
965 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
967 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
969 static int get_vsel_insn (enum machine_mode
);
970 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
971 static tree
rs6000_stack_protect_fail (void);
973 const int INSN_NOT_AVAILABLE
= -1;
974 static enum machine_mode
rs6000_eh_return_filter_mode (void);
976 /* Hash table stuff for keeping track of TOC entries. */
978 struct toc_hash_struct
GTY(())
980 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
981 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
983 enum machine_mode key_mode
;
987 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
989 /* Default register names. */
990 char rs6000_reg_names
[][8] =
992 "0", "1", "2", "3", "4", "5", "6", "7",
993 "8", "9", "10", "11", "12", "13", "14", "15",
994 "16", "17", "18", "19", "20", "21", "22", "23",
995 "24", "25", "26", "27", "28", "29", "30", "31",
996 "0", "1", "2", "3", "4", "5", "6", "7",
997 "8", "9", "10", "11", "12", "13", "14", "15",
998 "16", "17", "18", "19", "20", "21", "22", "23",
999 "24", "25", "26", "27", "28", "29", "30", "31",
1000 "mq", "lr", "ctr","ap",
1001 "0", "1", "2", "3", "4", "5", "6", "7",
1003 /* AltiVec registers. */
1004 "0", "1", "2", "3", "4", "5", "6", "7",
1005 "8", "9", "10", "11", "12", "13", "14", "15",
1006 "16", "17", "18", "19", "20", "21", "22", "23",
1007 "24", "25", "26", "27", "28", "29", "30", "31",
1009 /* SPE registers. */
1010 "spe_acc", "spefscr",
1011 /* Soft frame pointer. */
1015 #ifdef TARGET_REGNAMES
1016 static const char alt_reg_names
[][8] =
1018 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1019 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1020 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1021 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1022 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1023 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1024 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1025 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1026 "mq", "lr", "ctr", "ap",
1027 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1029 /* AltiVec registers. */
1030 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1031 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1032 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1033 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1035 /* SPE registers. */
1036 "spe_acc", "spefscr",
1037 /* Soft frame pointer. */
1042 #ifndef MASK_STRICT_ALIGN
1043 #define MASK_STRICT_ALIGN 0
1045 #ifndef TARGET_PROFILE_KERNEL
1046 #define TARGET_PROFILE_KERNEL 0
1049 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1050 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1052 /* Initialize the GCC target structure. */
1053 #undef TARGET_ATTRIBUTE_TABLE
1054 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1055 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1056 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1058 #undef TARGET_ASM_ALIGNED_DI_OP
1059 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1061 /* Default unaligned ops are only provided for ELF. Find the ops needed
1062 for non-ELF systems. */
1063 #ifndef OBJECT_FORMAT_ELF
1065 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1067 #undef TARGET_ASM_UNALIGNED_HI_OP
1068 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1069 #undef TARGET_ASM_UNALIGNED_SI_OP
1070 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1071 #undef TARGET_ASM_UNALIGNED_DI_OP
1072 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1075 #undef TARGET_ASM_UNALIGNED_HI_OP
1076 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1077 #undef TARGET_ASM_UNALIGNED_SI_OP
1078 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1079 #undef TARGET_ASM_UNALIGNED_DI_OP
1080 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1081 #undef TARGET_ASM_ALIGNED_DI_OP
1082 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1086 /* This hook deals with fixups for relocatable code and DI-mode objects
1088 #undef TARGET_ASM_INTEGER
1089 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1091 #ifdef HAVE_GAS_HIDDEN
1092 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1093 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1096 #undef TARGET_HAVE_TLS
1097 #define TARGET_HAVE_TLS HAVE_AS_TLS
1099 #undef TARGET_CANNOT_FORCE_CONST_MEM
1100 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1102 #undef TARGET_ASM_FUNCTION_PROLOGUE
1103 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1104 #undef TARGET_ASM_FUNCTION_EPILOGUE
1105 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1107 #undef TARGET_SCHED_VARIABLE_ISSUE
1108 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1110 #undef TARGET_SCHED_ISSUE_RATE
1111 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1112 #undef TARGET_SCHED_ADJUST_COST
1113 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1114 #undef TARGET_SCHED_ADJUST_PRIORITY
1115 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1116 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1117 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1118 #undef TARGET_SCHED_INIT
1119 #define TARGET_SCHED_INIT rs6000_sched_init
1120 #undef TARGET_SCHED_FINISH
1121 #define TARGET_SCHED_FINISH rs6000_sched_finish
1122 #undef TARGET_SCHED_REORDER
1123 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1124 #undef TARGET_SCHED_REORDER2
1125 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1127 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1128 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1130 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1131 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1133 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1134 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1135 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1136 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1137 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1138 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1139 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1140 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1142 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1143 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1145 #undef TARGET_INIT_BUILTINS
1146 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1148 #undef TARGET_EXPAND_BUILTIN
1149 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1151 #undef TARGET_MANGLE_TYPE
1152 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1154 #undef TARGET_INIT_LIBFUNCS
1155 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1158 #undef TARGET_BINDS_LOCAL_P
1159 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1162 #undef TARGET_MS_BITFIELD_LAYOUT_P
1163 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1165 #undef TARGET_ASM_OUTPUT_MI_THUNK
1166 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1168 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1169 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1171 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1172 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1174 #undef TARGET_INVALID_WITHIN_DOLOOP
1175 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1177 #undef TARGET_RTX_COSTS
1178 #define TARGET_RTX_COSTS rs6000_rtx_costs
1179 #undef TARGET_ADDRESS_COST
1180 #define TARGET_ADDRESS_COST hook_int_rtx_0
1182 #undef TARGET_VECTOR_OPAQUE_P
1183 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1185 #undef TARGET_DWARF_REGISTER_SPAN
1186 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1188 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1189 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1191 /* On rs6000, function arguments are promoted, as are function return
1193 #undef TARGET_PROMOTE_FUNCTION_ARGS
1194 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1195 #undef TARGET_PROMOTE_FUNCTION_RETURN
1196 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1198 #undef TARGET_RETURN_IN_MEMORY
1199 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1201 #undef TARGET_SETUP_INCOMING_VARARGS
1202 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1204 /* Always strict argument naming on rs6000. */
1205 #undef TARGET_STRICT_ARGUMENT_NAMING
1206 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1207 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1208 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1209 #undef TARGET_SPLIT_COMPLEX_ARG
1210 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1211 #undef TARGET_MUST_PASS_IN_STACK
1212 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1213 #undef TARGET_PASS_BY_REFERENCE
1214 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1215 #undef TARGET_ARG_PARTIAL_BYTES
1216 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1218 #undef TARGET_BUILD_BUILTIN_VA_LIST
1219 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1221 #undef TARGET_EXPAND_BUILTIN_VA_START
1222 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1224 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1225 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1227 #undef TARGET_EH_RETURN_FILTER_MODE
1228 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1230 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1231 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1233 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1234 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1236 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1237 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1239 #undef TARGET_HANDLE_OPTION
1240 #define TARGET_HANDLE_OPTION rs6000_handle_option
1242 #undef TARGET_DEFAULT_TARGET_FLAGS
1243 #define TARGET_DEFAULT_TARGET_FLAGS \
1246 #undef TARGET_STACK_PROTECT_FAIL
1247 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1249 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1250 The PowerPC architecture requires only weak consistency among
1251 processors--that is, memory accesses between processors need not be
1252 sequentially consistent and memory accesses among processors can occur
1253 in any order. The ability to order memory accesses weakly provides
1254 opportunities for more efficient use of the system bus. Unless a
1255 dependency exists, the 604e allows read operations to precede store
1257 #undef TARGET_RELAXED_ORDERING
1258 #define TARGET_RELAXED_ORDERING true
1261 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1262 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1265 /* Use a 32-bit anchor range. This leads to sequences like:
1267 addis tmp,anchor,high
1270 where tmp itself acts as an anchor, and can be shared between
1271 accesses to the same 64k page. */
1272 #undef TARGET_MIN_ANCHOR_OFFSET
1273 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1274 #undef TARGET_MAX_ANCHOR_OFFSET
1275 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1276 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1277 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1279 #undef TARGET_BUILTIN_RECIPROCAL
1280 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1282 #undef TARGET_EXPAND_TO_RTL_HOOK
1283 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1285 #undef TARGET_INSTANTIATE_DECLS
1286 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1288 struct gcc_target targetm
= TARGET_INITIALIZER
;
1291 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1294 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1296 /* The GPRs can hold any mode, but values bigger than one register
1297 cannot go past R31. */
1298 if (INT_REGNO_P (regno
))
1299 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1301 /* The float registers can only hold floating modes and DImode.
1302 This excludes the 32-bit decimal float mode for now. */
1303 if (FP_REGNO_P (regno
))
1305 ((SCALAR_FLOAT_MODE_P (mode
)
1306 && (mode
!= TDmode
|| (regno
% 2) == 0)
1307 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1308 || (GET_MODE_CLASS (mode
) == MODE_INT
1309 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1310 || (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1311 && PAIRED_VECTOR_MODE (mode
)));
1313 /* The CR register can only hold CC modes. */
1314 if (CR_REGNO_P (regno
))
1315 return GET_MODE_CLASS (mode
) == MODE_CC
;
1317 if (XER_REGNO_P (regno
))
1318 return mode
== PSImode
;
1320 /* AltiVec only in AldyVec registers. */
1321 if (ALTIVEC_REGNO_P (regno
))
1322 return ALTIVEC_VECTOR_MODE (mode
);
1324 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1325 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1328 /* We cannot put TImode anywhere except general register and it must be
1329 able to fit within the register set. */
1331 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1334 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1336 rs6000_init_hard_regno_mode_ok (void)
1340 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1341 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1342 if (rs6000_hard_regno_mode_ok (r
, m
))
1343 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1347 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1350 darwin_rs6000_override_options (void)
1352 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1354 rs6000_altivec_abi
= 1;
1355 TARGET_ALTIVEC_VRSAVE
= 1;
1356 if (DEFAULT_ABI
== ABI_DARWIN
)
1358 if (MACHO_DYNAMIC_NO_PIC_P
)
1361 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1364 else if (flag_pic
== 1)
1369 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
1371 target_flags
|= MASK_POWERPC64
;
1372 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1376 rs6000_default_long_calls
= 1;
1377 target_flags
|= MASK_SOFT_FLOAT
;
1380 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1382 if (!flag_mkernel
&& !flag_apple_kext
1384 && ! (target_flags_explicit
& MASK_ALTIVEC
))
1385 target_flags
|= MASK_ALTIVEC
;
1387 /* Unless the user (not the configurer) has explicitly overridden
1388 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1389 G4 unless targetting the kernel. */
1392 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
1393 && ! (target_flags_explicit
& MASK_ALTIVEC
)
1394 && ! rs6000_select
[1].string
)
1396 target_flags
|= MASK_ALTIVEC
;
1401 /* If not otherwise specified by a target, make 'long double' equivalent to
1404 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1405 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1408 /* Override command line options. Mostly we process the processor
1409 type and sometimes adjust other TARGET_ options. */
1412 rs6000_override_options (const char *default_cpu
)
1415 struct rs6000_cpu_select
*ptr
;
1418 /* Simplifications for entries below. */
1421 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1422 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1425 /* This table occasionally claims that a processor does not support
1426 a particular feature even though it does, but the feature is slower
1427 than the alternative. Thus, it shouldn't be relied on as a
1428 complete description of the processor's support.
1430 Please keep this list in order, and don't forget to update the
1431 documentation in invoke.texi when adding a new processor or
1435 const char *const name
; /* Canonical processor name. */
1436 const enum processor_type processor
; /* Processor type enum value. */
1437 const int target_enable
; /* Target flags to enable. */
1438 } const processor_target_table
[]
1439 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1440 {"403", PROCESSOR_PPC403
,
1441 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1442 {"405", PROCESSOR_PPC405
,
1443 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1444 {"405fp", PROCESSOR_PPC405
,
1445 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1446 {"440", PROCESSOR_PPC440
,
1447 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1448 {"440fp", PROCESSOR_PPC440
,
1449 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1450 {"464", PROCESSOR_PPC440
,
1451 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1452 {"464fp", PROCESSOR_PPC440
,
1453 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1454 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1455 {"601", PROCESSOR_PPC601
,
1456 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1457 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1458 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1459 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1460 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1461 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1462 {"620", PROCESSOR_PPC620
,
1463 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1464 {"630", PROCESSOR_PPC630
,
1465 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1466 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1467 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1468 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1469 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1470 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1471 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1472 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1473 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1474 /* 8548 has a dummy entry for now. */
1475 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1476 {"e300c2", PROCESSOR_PPCE300C2
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1477 {"e300c3", PROCESSOR_PPCE300C3
, POWERPC_BASE_MASK
},
1478 {"e500mc", PROCESSOR_PPCE500MC
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1479 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1480 {"970", PROCESSOR_POWER4
,
1481 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1482 {"cell", PROCESSOR_CELL
,
1483 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1484 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1485 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1486 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1487 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1488 {"G5", PROCESSOR_POWER4
,
1489 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1490 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1491 {"power2", PROCESSOR_POWER
,
1492 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1493 {"power3", PROCESSOR_PPC630
,
1494 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1495 {"power4", PROCESSOR_POWER4
,
1496 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1498 {"power5", PROCESSOR_POWER5
,
1499 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1500 | MASK_MFCRF
| MASK_POPCNTB
},
1501 {"power5+", PROCESSOR_POWER5
,
1502 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_PPC_GFXOPT
1503 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
},
1504 {"power6", PROCESSOR_POWER6
,
1505 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_MFCRF
1506 | MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1507 {"power6x", PROCESSOR_POWER6
,
1508 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_PPC_GPOPT
| MASK_MFCRF
1509 | MASK_POPCNTB
| MASK_FPRND
| MASK_CMPB
| MASK_DFP
| MASK_MFPGPR
},
1510 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1511 {"powerpc64", PROCESSOR_POWERPC64
,
1512 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1513 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1514 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1515 {"rios2", PROCESSOR_RIOS2
,
1516 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1517 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1518 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1519 {"rs64", PROCESSOR_RS64A
,
1520 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1523 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1525 /* Some OSs don't support saving the high part of 64-bit registers on
1526 context switch. Other OSs don't support saving Altivec registers.
1527 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1528 settings; if the user wants either, the user must explicitly specify
1529 them and we won't interfere with the user's specification. */
1532 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1533 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
| MASK_STRICT_ALIGN
1534 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1535 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
1536 | MASK_DLMZB
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
)
1539 rs6000_init_hard_regno_mode_ok ();
1541 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1542 #ifdef OS_MISSING_POWERPC64
1543 if (OS_MISSING_POWERPC64
)
1544 set_masks
&= ~MASK_POWERPC64
;
1546 #ifdef OS_MISSING_ALTIVEC
1547 if (OS_MISSING_ALTIVEC
)
1548 set_masks
&= ~MASK_ALTIVEC
;
1551 /* Don't override by the processor default if given explicitly. */
1552 set_masks
&= ~target_flags_explicit
;
1554 /* Identify the processor type. */
1555 rs6000_select
[0].string
= default_cpu
;
1556 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1558 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1560 ptr
= &rs6000_select
[i
];
1561 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1563 for (j
= 0; j
< ptt_size
; j
++)
1564 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1566 if (ptr
->set_tune_p
)
1567 rs6000_cpu
= processor_target_table
[j
].processor
;
1569 if (ptr
->set_arch_p
)
1571 target_flags
&= ~set_masks
;
1572 target_flags
|= (processor_target_table
[j
].target_enable
1579 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1583 if ((TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
)
1584 && !rs6000_explicit_options
.isel
)
1587 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
1588 || rs6000_cpu
== PROCESSOR_PPCE500MC
)
1591 error ("AltiVec not supported in this target");
1593 error ("Spe not supported in this target");
1596 /* If we are optimizing big endian systems for space, use the load/store
1597 multiple and string instructions. */
1598 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1599 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1601 /* Don't allow -mmultiple or -mstring on little endian systems
1602 unless the cpu is a 750, because the hardware doesn't support the
1603 instructions used in little endian mode, and causes an alignment
1604 trap. The 750 does not cause an alignment trap (except when the
1605 target is unaligned). */
1607 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1609 if (TARGET_MULTIPLE
)
1611 target_flags
&= ~MASK_MULTIPLE
;
1612 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1613 warning (0, "-mmultiple is not supported on little endian systems");
1618 target_flags
&= ~MASK_STRING
;
1619 if ((target_flags_explicit
& MASK_STRING
) != 0)
1620 warning (0, "-mstring is not supported on little endian systems");
1624 /* Set debug flags */
1625 if (rs6000_debug_name
)
1627 if (! strcmp (rs6000_debug_name
, "all"))
1628 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1629 else if (! strcmp (rs6000_debug_name
, "stack"))
1630 rs6000_debug_stack
= 1;
1631 else if (! strcmp (rs6000_debug_name
, "arg"))
1632 rs6000_debug_arg
= 1;
1634 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1637 if (rs6000_traceback_name
)
1639 if (! strncmp (rs6000_traceback_name
, "full", 4))
1640 rs6000_traceback
= traceback_full
;
1641 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1642 rs6000_traceback
= traceback_part
;
1643 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1644 rs6000_traceback
= traceback_none
;
1646 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1647 rs6000_traceback_name
);
1650 if (!rs6000_explicit_options
.long_double
)
1651 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1653 #ifndef POWERPC_LINUX
1654 if (!rs6000_explicit_options
.ieee
)
1655 rs6000_ieeequad
= 1;
1658 /* Enable Altivec ABI for AIX -maltivec. */
1659 if (TARGET_XCOFF
&& TARGET_ALTIVEC
)
1660 rs6000_altivec_abi
= 1;
1662 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1663 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1664 be explicitly overridden in either case. */
1667 if (!rs6000_explicit_options
.altivec_abi
1668 && (TARGET_64BIT
|| TARGET_ALTIVEC
))
1669 rs6000_altivec_abi
= 1;
1671 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1672 if (!rs6000_explicit_options
.vrsave
)
1673 TARGET_ALTIVEC_VRSAVE
= rs6000_altivec_abi
;
1676 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1677 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1679 rs6000_darwin64_abi
= 1;
1681 darwin_one_byte_bool
= 1;
1683 /* Default to natural alignment, for better performance. */
1684 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1687 /* Place FP constants in the constant pool instead of TOC
1688 if section anchors enabled. */
1689 if (flag_section_anchors
)
1690 TARGET_NO_FP_IN_TOC
= 1;
1692 /* Handle -mtls-size option. */
1693 rs6000_parse_tls_size_option ();
1695 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1696 SUBTARGET_OVERRIDE_OPTIONS
;
1698 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1699 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1701 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1702 SUB3TARGET_OVERRIDE_OPTIONS
;
1705 if (TARGET_E500
|| rs6000_cpu
== PROCESSOR_PPCE500MC
)
1707 /* The e500 and e500mc do not have string instructions, and we set
1708 MASK_STRING above when optimizing for size. */
1709 if ((target_flags
& MASK_STRING
) != 0)
1710 target_flags
= target_flags
& ~MASK_STRING
;
1712 else if (rs6000_select
[1].string
!= NULL
)
1714 /* For the powerpc-eabispe configuration, we set all these by
1715 default, so let's unset them if we manually set another
1716 CPU that is not the E500. */
1717 if (!rs6000_explicit_options
.spe_abi
)
1719 if (!rs6000_explicit_options
.spe
)
1721 if (!rs6000_explicit_options
.float_gprs
)
1722 rs6000_float_gprs
= 0;
1723 if (!rs6000_explicit_options
.isel
)
1727 /* Detect invalid option combinations with E500. */
1730 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1731 && rs6000_cpu
!= PROCESSOR_POWER5
1732 && rs6000_cpu
!= PROCESSOR_POWER6
1733 && rs6000_cpu
!= PROCESSOR_CELL
);
1734 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1735 || rs6000_cpu
== PROCESSOR_POWER5
);
1736 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
1737 || rs6000_cpu
== PROCESSOR_POWER5
1738 || rs6000_cpu
== PROCESSOR_POWER6
);
1740 rs6000_sched_restricted_insns_priority
1741 = (rs6000_sched_groups
? 1 : 0);
1743 /* Handle -msched-costly-dep option. */
1744 rs6000_sched_costly_dep
1745 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1747 if (rs6000_sched_costly_dep_str
)
1749 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1750 rs6000_sched_costly_dep
= no_dep_costly
;
1751 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1752 rs6000_sched_costly_dep
= all_deps_costly
;
1753 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1754 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1755 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1756 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1758 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1761 /* Handle -minsert-sched-nops option. */
1762 rs6000_sched_insert_nops
1763 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1765 if (rs6000_sched_insert_nops_str
)
1767 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1768 rs6000_sched_insert_nops
= sched_finish_none
;
1769 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1770 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1771 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1772 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1774 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1777 #ifdef TARGET_REGNAMES
1778 /* If the user desires alternate register names, copy in the
1779 alternate names now. */
1780 if (TARGET_REGNAMES
)
1781 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1784 /* Set aix_struct_return last, after the ABI is determined.
1785 If -maix-struct-return or -msvr4-struct-return was explicitly
1786 used, don't override with the ABI default. */
1787 if (!rs6000_explicit_options
.aix_struct_ret
)
1788 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
1790 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
1791 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1794 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1796 /* We can only guarantee the availability of DI pseudo-ops when
1797 assembling for 64-bit targets. */
1800 targetm
.asm_out
.aligned_op
.di
= NULL
;
1801 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1804 /* Set branch target alignment, if not optimizing for size. */
1807 /* Cell wants to be aligned 8byte for dual issue. */
1808 if (rs6000_cpu
== PROCESSOR_CELL
)
1810 if (align_functions
<= 0)
1811 align_functions
= 8;
1812 if (align_jumps
<= 0)
1814 if (align_loops
<= 0)
1817 if (rs6000_align_branch_targets
)
1819 if (align_functions
<= 0)
1820 align_functions
= 16;
1821 if (align_jumps
<= 0)
1823 if (align_loops
<= 0)
1826 if (align_jumps_max_skip
<= 0)
1827 align_jumps_max_skip
= 15;
1828 if (align_loops_max_skip
<= 0)
1829 align_loops_max_skip
= 15;
1832 /* Arrange to save and restore machine status around nested functions. */
1833 init_machine_status
= rs6000_init_machine_status
;
1835 /* We should always be splitting complex arguments, but we can't break
1836 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1837 if (DEFAULT_ABI
!= ABI_AIX
)
1838 targetm
.calls
.split_complex_arg
= NULL
;
1840 /* Initialize rs6000_cost with the appropriate target costs. */
1842 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1846 case PROCESSOR_RIOS1
:
1847 rs6000_cost
= &rios1_cost
;
1850 case PROCESSOR_RIOS2
:
1851 rs6000_cost
= &rios2_cost
;
1854 case PROCESSOR_RS64A
:
1855 rs6000_cost
= &rs64a_cost
;
1858 case PROCESSOR_MPCCORE
:
1859 rs6000_cost
= &mpccore_cost
;
1862 case PROCESSOR_PPC403
:
1863 rs6000_cost
= &ppc403_cost
;
1866 case PROCESSOR_PPC405
:
1867 rs6000_cost
= &ppc405_cost
;
1870 case PROCESSOR_PPC440
:
1871 rs6000_cost
= &ppc440_cost
;
1874 case PROCESSOR_PPC601
:
1875 rs6000_cost
= &ppc601_cost
;
1878 case PROCESSOR_PPC603
:
1879 rs6000_cost
= &ppc603_cost
;
1882 case PROCESSOR_PPC604
:
1883 rs6000_cost
= &ppc604_cost
;
1886 case PROCESSOR_PPC604e
:
1887 rs6000_cost
= &ppc604e_cost
;
1890 case PROCESSOR_PPC620
:
1891 rs6000_cost
= &ppc620_cost
;
1894 case PROCESSOR_PPC630
:
1895 rs6000_cost
= &ppc630_cost
;
1898 case PROCESSOR_CELL
:
1899 rs6000_cost
= &ppccell_cost
;
1902 case PROCESSOR_PPC750
:
1903 case PROCESSOR_PPC7400
:
1904 rs6000_cost
= &ppc750_cost
;
1907 case PROCESSOR_PPC7450
:
1908 rs6000_cost
= &ppc7450_cost
;
1911 case PROCESSOR_PPC8540
:
1912 rs6000_cost
= &ppc8540_cost
;
1915 case PROCESSOR_PPCE300C2
:
1916 case PROCESSOR_PPCE300C3
:
1917 rs6000_cost
= &ppce300c2c3_cost
;
1920 case PROCESSOR_PPCE500MC
:
1921 rs6000_cost
= &ppce500mc_cost
;
1924 case PROCESSOR_POWER4
:
1925 case PROCESSOR_POWER5
:
1926 rs6000_cost
= &power4_cost
;
1929 case PROCESSOR_POWER6
:
1930 rs6000_cost
= &power6_cost
;
1937 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1938 set_param_value ("simultaneous-prefetches",
1939 rs6000_cost
->simultaneous_prefetches
);
1940 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1941 set_param_value ("l1-cache-size", rs6000_cost
->l1_cache_size
);
1942 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE
))
1943 set_param_value ("l1-cache-line-size", rs6000_cost
->cache_line_size
);
1944 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1945 set_param_value ("l2-cache-size", rs6000_cost
->l2_cache_size
);
1947 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1948 can be optimized to ap = __builtin_next_arg (0). */
1949 if (DEFAULT_ABI
!= ABI_V4
)
1950 targetm
.expand_builtin_va_start
= NULL
;
1953 /* Implement targetm.vectorize.builtin_mask_for_load. */
1955 rs6000_builtin_mask_for_load (void)
1958 return altivec_builtin_mask_for_load
;
1963 /* Implement targetm.vectorize.builtin_conversion. */
1965 rs6000_builtin_conversion (enum tree_code code
, tree type
)
1967 if (!TARGET_ALTIVEC
)
1973 switch (TYPE_MODE (type
))
1976 return TYPE_UNSIGNED (type
) ?
1977 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFUX
] :
1978 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFSX
];
1987 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1989 rs6000_builtin_mul_widen_even (tree type
)
1991 if (!TARGET_ALTIVEC
)
1994 switch (TYPE_MODE (type
))
1997 return TYPE_UNSIGNED (type
) ?
1998 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH
] :
1999 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
2002 return TYPE_UNSIGNED (type
) ?
2003 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB
] :
2004 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
2010 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
2012 rs6000_builtin_mul_widen_odd (tree type
)
2014 if (!TARGET_ALTIVEC
)
2017 switch (TYPE_MODE (type
))
2020 return TYPE_UNSIGNED (type
) ?
2021 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH
] :
2022 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
2025 return TYPE_UNSIGNED (type
) ?
2026 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB
] :
2027 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
2034 /* Return true iff, data reference of TYPE can reach vector alignment (16)
2035 after applying N number of iterations. This routine does not determine
2036 how may iterations are required to reach desired alignment. */
2039 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
2046 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
2049 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
2059 /* Assuming that all other types are naturally aligned. CHECKME! */
2064 /* Handle generic options of the form -mfoo=yes/no.
2065 NAME is the option name.
2066 VALUE is the option value.
2067 FLAG is the pointer to the flag where to store a 1 or 0, depending on
2068 whether the option value is 'yes' or 'no' respectively. */
2070 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
2074 else if (!strcmp (value
, "yes"))
2076 else if (!strcmp (value
, "no"))
2079 error ("unknown -m%s= option specified: '%s'", name
, value
);
2082 /* Validate and record the size specified with the -mtls-size option. */
2085 rs6000_parse_tls_size_option (void)
2087 if (rs6000_tls_size_string
== 0)
2089 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
2090 rs6000_tls_size
= 16;
2091 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
2092 rs6000_tls_size
= 32;
2093 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
2094 rs6000_tls_size
= 64;
2096 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
2100 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
2102 if (DEFAULT_ABI
== ABI_DARWIN
)
2103 /* The Darwin libraries never set errno, so we might as well
2104 avoid calling them when that's the only reason we would. */
2105 flag_errno_math
= 0;
2107 /* Double growth factor to counter reduced min jump length. */
2108 set_param_value ("max-grow-copy-bb-insns", 16);
2110 /* Enable section anchors by default.
2111 Skip section anchors for Objective C and Objective C++
2112 until front-ends fixed. */
2113 if (!TARGET_MACHO
&& lang_hooks
.name
[4] != 'O')
2114 flag_section_anchors
= 2;
2117 /* Implement TARGET_HANDLE_OPTION. */
2120 rs6000_handle_option (size_t code
, const char *arg
, int value
)
2125 target_flags
&= ~(MASK_POWER
| MASK_POWER2
2126 | MASK_MULTIPLE
| MASK_STRING
);
2127 target_flags_explicit
|= (MASK_POWER
| MASK_POWER2
2128 | MASK_MULTIPLE
| MASK_STRING
);
2130 case OPT_mno_powerpc
:
2131 target_flags
&= ~(MASK_POWERPC
| MASK_PPC_GPOPT
2132 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2133 target_flags_explicit
|= (MASK_POWERPC
| MASK_PPC_GPOPT
2134 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2137 target_flags
&= ~MASK_MINIMAL_TOC
;
2138 TARGET_NO_FP_IN_TOC
= 0;
2139 TARGET_NO_SUM_IN_TOC
= 0;
2140 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2141 #ifdef TARGET_USES_SYSV4_OPT
2142 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2143 just the same as -mminimal-toc. */
2144 target_flags
|= MASK_MINIMAL_TOC
;
2145 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2149 #ifdef TARGET_USES_SYSV4_OPT
2151 /* Make -mtoc behave like -mminimal-toc. */
2152 target_flags
|= MASK_MINIMAL_TOC
;
2153 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2157 #ifdef TARGET_USES_AIX64_OPT
2162 target_flags
|= MASK_POWERPC64
| MASK_POWERPC
;
2163 target_flags
|= ~target_flags_explicit
& MASK_PPC_GFXOPT
;
2164 target_flags_explicit
|= MASK_POWERPC64
| MASK_POWERPC
;
2167 #ifdef TARGET_USES_AIX64_OPT
2172 target_flags
&= ~MASK_POWERPC64
;
2173 target_flags_explicit
|= MASK_POWERPC64
;
2176 case OPT_minsert_sched_nops_
:
2177 rs6000_sched_insert_nops_str
= arg
;
2180 case OPT_mminimal_toc
:
2183 TARGET_NO_FP_IN_TOC
= 0;
2184 TARGET_NO_SUM_IN_TOC
= 0;
2191 target_flags
|= (MASK_MULTIPLE
| MASK_STRING
);
2192 target_flags_explicit
|= (MASK_MULTIPLE
| MASK_STRING
);
2199 target_flags
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2200 target_flags_explicit
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2204 case OPT_mpowerpc_gpopt
:
2205 case OPT_mpowerpc_gfxopt
:
2208 target_flags
|= MASK_POWERPC
;
2209 target_flags_explicit
|= MASK_POWERPC
;
2213 case OPT_maix_struct_return
:
2214 case OPT_msvr4_struct_return
:
2215 rs6000_explicit_options
.aix_struct_ret
= true;
2219 rs6000_explicit_options
.vrsave
= true;
2220 rs6000_parse_yes_no_option ("vrsave", arg
, &(TARGET_ALTIVEC_VRSAVE
));
2224 rs6000_explicit_options
.isel
= true;
2225 rs6000_isel
= value
;
2229 rs6000_explicit_options
.isel
= true;
2230 rs6000_parse_yes_no_option ("isel", arg
, &(rs6000_isel
));
2234 rs6000_explicit_options
.spe
= true;
2239 rs6000_explicit_options
.spe
= true;
2240 rs6000_parse_yes_no_option ("spe", arg
, &(rs6000_spe
));
2244 rs6000_debug_name
= arg
;
2247 #ifdef TARGET_USES_SYSV4_OPT
2249 rs6000_abi_name
= arg
;
2253 rs6000_sdata_name
= arg
;
2256 case OPT_mtls_size_
:
2257 rs6000_tls_size_string
= arg
;
2260 case OPT_mrelocatable
:
2263 target_flags
|= MASK_MINIMAL_TOC
;
2264 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2265 TARGET_NO_FP_IN_TOC
= 1;
2269 case OPT_mrelocatable_lib
:
2272 target_flags
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2273 target_flags_explicit
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2274 TARGET_NO_FP_IN_TOC
= 1;
2278 target_flags
&= ~MASK_RELOCATABLE
;
2279 target_flags_explicit
|= MASK_RELOCATABLE
;
2285 if (!strcmp (arg
, "altivec"))
2287 rs6000_explicit_options
.altivec_abi
= true;
2288 rs6000_altivec_abi
= 1;
2290 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2293 else if (! strcmp (arg
, "no-altivec"))
2295 rs6000_explicit_options
.altivec_abi
= true;
2296 rs6000_altivec_abi
= 0;
2298 else if (! strcmp (arg
, "spe"))
2300 rs6000_explicit_options
.spe_abi
= true;
2302 rs6000_altivec_abi
= 0;
2303 if (!TARGET_SPE_ABI
)
2304 error ("not configured for ABI: '%s'", arg
);
2306 else if (! strcmp (arg
, "no-spe"))
2308 rs6000_explicit_options
.spe_abi
= true;
2312 /* These are here for testing during development only, do not
2313 document in the manual please. */
2314 else if (! strcmp (arg
, "d64"))
2316 rs6000_darwin64_abi
= 1;
2317 warning (0, "Using darwin64 ABI");
2319 else if (! strcmp (arg
, "d32"))
2321 rs6000_darwin64_abi
= 0;
2322 warning (0, "Using old darwin ABI");
2325 else if (! strcmp (arg
, "ibmlongdouble"))
2327 rs6000_explicit_options
.ieee
= true;
2328 rs6000_ieeequad
= 0;
2329 warning (0, "Using IBM extended precision long double");
2331 else if (! strcmp (arg
, "ieeelongdouble"))
2333 rs6000_explicit_options
.ieee
= true;
2334 rs6000_ieeequad
= 1;
2335 warning (0, "Using IEEE extended precision long double");
2340 error ("unknown ABI specified: '%s'", arg
);
2346 rs6000_select
[1].string
= arg
;
2350 rs6000_select
[2].string
= arg
;
2353 case OPT_mtraceback_
:
2354 rs6000_traceback_name
= arg
;
2357 case OPT_mfloat_gprs_
:
2358 rs6000_explicit_options
.float_gprs
= true;
2359 if (! strcmp (arg
, "yes") || ! strcmp (arg
, "single"))
2360 rs6000_float_gprs
= 1;
2361 else if (! strcmp (arg
, "double"))
2362 rs6000_float_gprs
= 2;
2363 else if (! strcmp (arg
, "no"))
2364 rs6000_float_gprs
= 0;
2367 error ("invalid option for -mfloat-gprs: '%s'", arg
);
2372 case OPT_mlong_double_
:
2373 rs6000_explicit_options
.long_double
= true;
2374 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2375 if (value
!= 64 && value
!= 128)
2377 error ("Unknown switch -mlong-double-%s", arg
);
2378 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2382 rs6000_long_double_type_size
= value
;
2385 case OPT_msched_costly_dep_
:
2386 rs6000_sched_costly_dep_str
= arg
;
2390 rs6000_explicit_options
.alignment
= true;
2391 if (! strcmp (arg
, "power"))
2393 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2394 some C library functions, so warn about it. The flag may be
2395 useful for performance studies from time to time though, so
2396 don't disable it entirely. */
2397 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
2398 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2399 " it is incompatible with the installed C and C++ libraries");
2400 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
2402 else if (! strcmp (arg
, "natural"))
2403 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2406 error ("unknown -malign-XXXXX option specified: '%s'", arg
);
2414 /* Do anything needed at the start of the asm file. */
2417 rs6000_file_start (void)
2421 const char *start
= buffer
;
2422 struct rs6000_cpu_select
*ptr
;
2423 const char *default_cpu
= TARGET_CPU_DEFAULT
;
2424 FILE *file
= asm_out_file
;
2426 default_file_start ();
2428 #ifdef TARGET_BI_ARCH
2429 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
2433 if (flag_verbose_asm
)
2435 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
2436 rs6000_select
[0].string
= default_cpu
;
2438 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
2440 ptr
= &rs6000_select
[i
];
2441 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
2443 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
2448 if (PPC405_ERRATUM77
)
2450 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
2454 #ifdef USING_ELFOS_H
2455 switch (rs6000_sdata
)
2457 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
2458 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
2459 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
2460 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
2463 if (rs6000_sdata
&& g_switch_value
)
2465 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
2475 #ifdef HAVE_AS_GNU_ATTRIBUTE
2476 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
2478 fprintf (file
, "\t.gnu_attribute 4, %d\n",
2479 (TARGET_HARD_FLOAT
&& TARGET_FPRS
) ? 1 : 2);
2480 fprintf (file
, "\t.gnu_attribute 8, %d\n",
2481 (TARGET_ALTIVEC_ABI
? 2
2482 : TARGET_SPE_ABI
? 3
2487 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
2489 switch_to_section (toc_section
);
2490 switch_to_section (text_section
);
2495 /* Return nonzero if this function is known to have a null epilogue. */
2498 direct_return (void)
2500 if (reload_completed
)
2502 rs6000_stack_t
*info
= rs6000_stack_info ();
2504 if (info
->first_gp_reg_save
== 32
2505 && info
->first_fp_reg_save
== 64
2506 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
2507 && ! info
->lr_save_p
2508 && ! info
->cr_save_p
2509 && info
->vrsave_mask
== 0
2517 /* Return the number of instructions it takes to form a constant in an
2518 integer register. */
2521 num_insns_constant_wide (HOST_WIDE_INT value
)
2523 /* signed constant loadable with {cal|addi} */
2524 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
2527 /* constant loadable with {cau|addis} */
2528 else if ((value
& 0xffff) == 0
2529 && (value
>> 31 == -1 || value
>> 31 == 0))
2532 #if HOST_BITS_PER_WIDE_INT == 64
2533 else if (TARGET_POWERPC64
)
2535 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2536 HOST_WIDE_INT high
= value
>> 31;
2538 if (high
== 0 || high
== -1)
2544 return num_insns_constant_wide (high
) + 1;
2546 return (num_insns_constant_wide (high
)
2547 + num_insns_constant_wide (low
) + 1);
2556 num_insns_constant (rtx op
, enum machine_mode mode
)
2558 HOST_WIDE_INT low
, high
;
2560 switch (GET_CODE (op
))
2563 #if HOST_BITS_PER_WIDE_INT == 64
2564 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2565 && mask64_operand (op
, mode
))
2569 return num_insns_constant_wide (INTVAL (op
));
2572 if (mode
== SFmode
|| mode
== SDmode
)
2577 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2578 if (DECIMAL_FLOAT_MODE_P (mode
))
2579 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
2581 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2582 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2585 if (mode
== VOIDmode
|| mode
== DImode
)
2587 high
= CONST_DOUBLE_HIGH (op
);
2588 low
= CONST_DOUBLE_LOW (op
);
2595 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2596 if (DECIMAL_FLOAT_MODE_P (mode
))
2597 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
2599 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2600 high
= l
[WORDS_BIG_ENDIAN
== 0];
2601 low
= l
[WORDS_BIG_ENDIAN
!= 0];
2605 return (num_insns_constant_wide (low
)
2606 + num_insns_constant_wide (high
));
2609 if ((high
== 0 && low
>= 0)
2610 || (high
== -1 && low
< 0))
2611 return num_insns_constant_wide (low
);
2613 else if (mask64_operand (op
, mode
))
2617 return num_insns_constant_wide (high
) + 1;
2620 return (num_insns_constant_wide (high
)
2621 + num_insns_constant_wide (low
) + 1);
2629 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2630 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2631 corresponding element of the vector, but for V4SFmode and V2SFmode,
2632 the corresponding "float" is interpreted as an SImode integer. */
2634 static HOST_WIDE_INT
2635 const_vector_elt_as_int (rtx op
, unsigned int elt
)
2637 rtx tmp
= CONST_VECTOR_ELT (op
, elt
);
2638 if (GET_MODE (op
) == V4SFmode
2639 || GET_MODE (op
) == V2SFmode
)
2640 tmp
= gen_lowpart (SImode
, tmp
);
2641 return INTVAL (tmp
);
2644 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2645 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2646 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2647 all items are set to the same value and contain COPIES replicas of the
2648 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2649 operand and the others are set to the value of the operand's msb. */
2652 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
2654 enum machine_mode mode
= GET_MODE (op
);
2655 enum machine_mode inner
= GET_MODE_INNER (mode
);
2658 unsigned nunits
= GET_MODE_NUNITS (mode
);
2659 unsigned bitsize
= GET_MODE_BITSIZE (inner
);
2660 unsigned mask
= GET_MODE_MASK (inner
);
2662 HOST_WIDE_INT val
= const_vector_elt_as_int (op
, nunits
- 1);
2663 HOST_WIDE_INT splat_val
= val
;
2664 HOST_WIDE_INT msb_val
= val
> 0 ? 0 : -1;
2666 /* Construct the value to be splatted, if possible. If not, return 0. */
2667 for (i
= 2; i
<= copies
; i
*= 2)
2669 HOST_WIDE_INT small_val
;
2671 small_val
= splat_val
>> bitsize
;
2673 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
2675 splat_val
= small_val
;
2678 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2679 if (EASY_VECTOR_15 (splat_val
))
2682 /* Also check if we can splat, and then add the result to itself. Do so if
2683 the value is positive, of if the splat instruction is using OP's mode;
2684 for splat_val < 0, the splat and the add should use the same mode. */
2685 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
2686 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
2692 /* Check if VAL is present in every STEP-th element, and the
2693 other elements are filled with its most significant bit. */
2694 for (i
= 0; i
< nunits
- 1; ++i
)
2696 HOST_WIDE_INT desired_val
;
2697 if (((i
+ 1) & (step
- 1)) == 0)
2700 desired_val
= msb_val
;
2702 if (desired_val
!= const_vector_elt_as_int (op
, i
))
2710 /* Return true if OP is of the given MODE and can be synthesized
2711 with a vspltisb, vspltish or vspltisw. */
2714 easy_altivec_constant (rtx op
, enum machine_mode mode
)
2716 unsigned step
, copies
;
2718 if (mode
== VOIDmode
)
2719 mode
= GET_MODE (op
);
2720 else if (mode
!= GET_MODE (op
))
2723 /* Start with a vspltisw. */
2724 step
= GET_MODE_NUNITS (mode
) / 4;
2727 if (vspltis_constant (op
, step
, copies
))
2730 /* Then try with a vspltish. */
2736 if (vspltis_constant (op
, step
, copies
))
2739 /* And finally a vspltisb. */
2745 if (vspltis_constant (op
, step
, copies
))
2751 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2752 result is OP. Abort if it is not possible. */
2755 gen_easy_altivec_constant (rtx op
)
2757 enum machine_mode mode
= GET_MODE (op
);
2758 int nunits
= GET_MODE_NUNITS (mode
);
2759 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2760 unsigned step
= nunits
/ 4;
2761 unsigned copies
= 1;
2763 /* Start with a vspltisw. */
2764 if (vspltis_constant (op
, step
, copies
))
2765 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
2767 /* Then try with a vspltish. */
2773 if (vspltis_constant (op
, step
, copies
))
2774 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
2776 /* And finally a vspltisb. */
2782 if (vspltis_constant (op
, step
, copies
))
2783 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
2789 output_vec_const_move (rtx
*operands
)
2792 enum machine_mode mode
;
2797 mode
= GET_MODE (dest
);
2802 if (zero_constant (vec
, mode
))
2803 return "vxor %0,%0,%0";
2805 splat_vec
= gen_easy_altivec_constant (vec
);
2806 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
2807 operands
[1] = XEXP (splat_vec
, 0);
2808 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
2811 switch (GET_MODE (splat_vec
))
2814 return "vspltisw %0,%1";
2817 return "vspltish %0,%1";
2820 return "vspltisb %0,%1";
2827 gcc_assert (TARGET_SPE
);
2829 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2830 pattern of V1DI, V4HI, and V2SF.
2832 FIXME: We should probably return # and add post reload
2833 splitters for these, but this way is so easy ;-). */
2834 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2835 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2836 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
2837 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
2839 return "li %0,%1\n\tevmergelo %0,%0,%0";
2841 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2844 /* Initialize TARGET of vector PAIRED to VALS. */
2847 paired_expand_vector_init (rtx target
, rtx vals
)
2849 enum machine_mode mode
= GET_MODE (target
);
2850 int n_elts
= GET_MODE_NUNITS (mode
);
2852 rtx x
, new, tmp
, constant_op
, op1
, op2
;
2855 for (i
= 0; i
< n_elts
; ++i
)
2857 x
= XVECEXP (vals
, 0, i
);
2858 if (!CONSTANT_P (x
))
2863 /* Load from constant pool. */
2864 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
2870 /* The vector is initialized only with non-constants. */
2871 new = gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
2872 XVECEXP (vals
, 0, 1));
2874 emit_move_insn (target
, new);
2878 /* One field is non-constant and the other one is a constant. Load the
2879 constant from the constant pool and use ps_merge instruction to
2880 construct the whole vector. */
2881 op1
= XVECEXP (vals
, 0, 0);
2882 op2
= XVECEXP (vals
, 0, 1);
2884 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
2886 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
2887 emit_move_insn (tmp
, constant_op
);
2889 if (CONSTANT_P (op1
))
2890 new = gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
2892 new = gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
2894 emit_move_insn (target
, new);
2898 paired_expand_vector_move (rtx operands
[])
2900 rtx op0
= operands
[0], op1
= operands
[1];
2902 emit_move_insn (op0
, op1
);
2905 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
2906 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
2907 operands for the relation operation COND. This is a recursive
2911 paired_emit_vector_compare (enum rtx_code rcode
,
2912 rtx dest
, rtx op0
, rtx op1
,
2913 rtx cc_op0
, rtx cc_op1
)
2915 rtx tmp
= gen_reg_rtx (V2SFmode
);
2916 rtx tmp1
, max
, min
, equal_zero
;
2918 gcc_assert (TARGET_PAIRED_FLOAT
);
2919 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
2925 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2929 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
2930 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
2934 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
2937 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2940 tmp1
= gen_reg_rtx (V2SFmode
);
2941 max
= gen_reg_rtx (V2SFmode
);
2942 min
= gen_reg_rtx (V2SFmode
);
2943 equal_zero
= gen_reg_rtx (V2SFmode
);
2945 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
2946 emit_insn (gen_selv2sf4
2947 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
2948 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
2949 emit_insn (gen_selv2sf4
2950 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
2951 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
2952 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
2955 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2958 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2961 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2964 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2967 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2976 /* Emit vector conditional expression.
2977 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
2978 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
2981 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
2982 rtx cond
, rtx cc_op0
, rtx cc_op1
)
2984 enum rtx_code rcode
= GET_CODE (cond
);
2986 if (!TARGET_PAIRED_FLOAT
)
2989 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
2994 /* Initialize vector TARGET to VALS. */
2997 rs6000_expand_vector_init (rtx target
, rtx vals
)
2999 enum machine_mode mode
= GET_MODE (target
);
3000 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3001 int n_elts
= GET_MODE_NUNITS (mode
);
3002 int n_var
= 0, one_var
= -1;
3003 bool all_same
= true, all_const_zero
= true;
3007 for (i
= 0; i
< n_elts
; ++i
)
3009 x
= XVECEXP (vals
, 0, i
);
3010 if (!CONSTANT_P (x
))
3011 ++n_var
, one_var
= i
;
3012 else if (x
!= CONST0_RTX (inner_mode
))
3013 all_const_zero
= false;
3015 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
3021 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
3022 if (mode
!= V4SFmode
&& all_const_zero
)
3024 /* Zero register. */
3025 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3026 gen_rtx_XOR (mode
, target
, target
)));
3029 else if (mode
!= V4SFmode
&& easy_vector_constant (const_vec
, mode
))
3031 /* Splat immediate. */
3032 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
3036 ; /* Splat vector element. */
3039 /* Load from constant pool. */
3040 emit_move_insn (target
, const_vec
);
3045 /* Store value to stack temp. Load vector element. Splat. */
3048 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3049 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
3050 XVECEXP (vals
, 0, 0));
3051 x
= gen_rtx_UNSPEC (VOIDmode
,
3052 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3053 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3055 gen_rtx_SET (VOIDmode
,
3058 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
3059 gen_rtx_PARALLEL (VOIDmode
,
3060 gen_rtvec (1, const0_rtx
)));
3061 emit_insn (gen_rtx_SET (VOIDmode
, target
,
3062 gen_rtx_VEC_DUPLICATE (mode
, x
)));
3066 /* One field is non-constant. Load constant then overwrite
3070 rtx copy
= copy_rtx (vals
);
3072 /* Load constant part of vector, substitute neighboring value for
3074 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
3075 rs6000_expand_vector_init (target
, copy
);
3077 /* Insert variable. */
3078 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
3082 /* Construct the vector in memory one field at a time
3083 and load the whole vector. */
3084 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3085 for (i
= 0; i
< n_elts
; i
++)
3086 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
3087 i
* GET_MODE_SIZE (inner_mode
)),
3088 XVECEXP (vals
, 0, i
));
3089 emit_move_insn (target
, mem
);
3092 /* Set field ELT of TARGET to VAL. */
3095 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
3097 enum machine_mode mode
= GET_MODE (target
);
3098 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3099 rtx reg
= gen_reg_rtx (mode
);
3101 int width
= GET_MODE_SIZE (inner_mode
);
3104 /* Load single variable value. */
3105 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3106 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
3107 x
= gen_rtx_UNSPEC (VOIDmode
,
3108 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3109 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3111 gen_rtx_SET (VOIDmode
,
3115 /* Linear sequence. */
3116 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
3117 for (i
= 0; i
< 16; ++i
)
3118 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
3120 /* Set permute mask to insert element into target. */
3121 for (i
= 0; i
< width
; ++i
)
3122 XVECEXP (mask
, 0, elt
*width
+ i
)
3123 = GEN_INT (i
+ 0x10);
3124 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
3125 x
= gen_rtx_UNSPEC (mode
,
3126 gen_rtvec (3, target
, reg
,
3127 force_reg (V16QImode
, x
)),
3129 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
3132 /* Extract field ELT from VEC into TARGET. */
3135 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
3137 enum machine_mode mode
= GET_MODE (vec
);
3138 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3141 /* Allocate mode-sized buffer. */
3142 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3144 /* Add offset to field within buffer matching vector element. */
3145 mem
= adjust_address_nv (mem
, mode
, elt
* GET_MODE_SIZE (inner_mode
));
3147 /* Store single field into mode-sized buffer. */
3148 x
= gen_rtx_UNSPEC (VOIDmode
,
3149 gen_rtvec (1, const0_rtx
), UNSPEC_STVE
);
3150 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3152 gen_rtx_SET (VOIDmode
,
3155 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
3158 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3159 implement ANDing by the mask IN. */
3161 build_mask64_2_operands (rtx in
, rtx
*out
)
3163 #if HOST_BITS_PER_WIDE_INT >= 64
3164 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
3167 gcc_assert (GET_CODE (in
) == CONST_INT
);
3172 /* Assume c initially something like 0x00fff000000fffff. The idea
3173 is to rotate the word so that the middle ^^^^^^ group of zeros
3174 is at the MS end and can be cleared with an rldicl mask. We then
3175 rotate back and clear off the MS ^^ group of zeros with a
3177 c
= ~c
; /* c == 0xff000ffffff00000 */
3178 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
3179 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
3180 c
= ~c
; /* c == 0x00fff000000fffff */
3181 c
&= -lsb
; /* c == 0x00fff00000000000 */
3182 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3183 c
= ~c
; /* c == 0xff000fffffffffff */
3184 c
&= -lsb
; /* c == 0xff00000000000000 */
3186 while ((lsb
>>= 1) != 0)
3187 shift
++; /* shift == 44 on exit from loop */
3188 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
3189 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
3190 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
3194 /* Assume c initially something like 0xff000f0000000000. The idea
3195 is to rotate the word so that the ^^^ middle group of zeros
3196 is at the LS end and can be cleared with an rldicr mask. We then
3197 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3199 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
3200 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
3201 c
= ~c
; /* c == 0x00fff0ffffffffff */
3202 c
&= -lsb
; /* c == 0x00fff00000000000 */
3203 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3204 c
= ~c
; /* c == 0xff000fffffffffff */
3205 c
&= -lsb
; /* c == 0xff00000000000000 */
3207 while ((lsb
>>= 1) != 0)
3208 shift
++; /* shift == 44 on exit from loop */
3209 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
3210 m1
>>= shift
; /* m1 == 0x0000000000000fff */
3211 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
3214 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3215 masks will be all 1's. We are guaranteed more than one transition. */
3216 out
[0] = GEN_INT (64 - shift
);
3217 out
[1] = GEN_INT (m1
);
3218 out
[2] = GEN_INT (shift
);
3219 out
[3] = GEN_INT (m2
);
3227 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3230 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
3232 if (TARGET_E500_DOUBLE
)
3234 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3235 subreg:TI and reg:TF. Decimal float modes are like integer
3236 modes (only low part of each register used) for this
3238 if (GET_CODE (op
) == SUBREG
3239 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
3240 || mode
== DDmode
|| mode
== TDmode
)
3241 && REG_P (SUBREG_REG (op
))
3242 && (GET_MODE (SUBREG_REG (op
)) == DFmode
3243 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
3246 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3248 if (GET_CODE (op
) == SUBREG
3249 && (mode
== DFmode
|| mode
== TFmode
)
3250 && REG_P (SUBREG_REG (op
))
3251 && (GET_MODE (SUBREG_REG (op
)) == DImode
3252 || GET_MODE (SUBREG_REG (op
)) == TImode
3253 || GET_MODE (SUBREG_REG (op
)) == DDmode
3254 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
3259 && GET_CODE (op
) == SUBREG
3261 && REG_P (SUBREG_REG (op
))
3262 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
3268 /* AIX increases natural record alignment to doubleword if the first
3269 field is an FP double while the FP fields remain word aligned. */
3272 rs6000_special_round_type_align (tree type
, unsigned int computed
,
3273 unsigned int specified
)
3275 unsigned int align
= MAX (computed
, specified
);
3276 tree field
= TYPE_FIELDS (type
);
3278 /* Skip all non field decls */
3279 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3280 field
= TREE_CHAIN (field
);
3282 if (field
!= NULL
&& field
!= type
)
3284 type
= TREE_TYPE (field
);
3285 while (TREE_CODE (type
) == ARRAY_TYPE
)
3286 type
= TREE_TYPE (type
);
3288 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
3289 align
= MAX (align
, 64);
3295 /* Darwin increases record alignment to the natural alignment of
3299 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
3300 unsigned int specified
)
3302 unsigned int align
= MAX (computed
, specified
);
3304 if (TYPE_PACKED (type
))
3307 /* Find the first field, looking down into aggregates. */
3309 tree field
= TYPE_FIELDS (type
);
3310 /* Skip all non field decls */
3311 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3312 field
= TREE_CHAIN (field
);
3315 type
= TREE_TYPE (field
);
3316 while (TREE_CODE (type
) == ARRAY_TYPE
)
3317 type
= TREE_TYPE (type
);
3318 } while (AGGREGATE_TYPE_P (type
));
3320 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
3321 align
= MAX (align
, TYPE_ALIGN (type
));
3326 /* Return 1 for an operand in small memory on V.4/eabi. */
3329 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3330 enum machine_mode mode ATTRIBUTE_UNUSED
)
3335 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3338 if (DEFAULT_ABI
!= ABI_V4
)
3341 /* Vector and float memory instructions have a limited offset on the
3342 SPE, so using a vector or float variable directly as an operand is
3345 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
3348 if (GET_CODE (op
) == SYMBOL_REF
)
3351 else if (GET_CODE (op
) != CONST
3352 || GET_CODE (XEXP (op
, 0)) != PLUS
3353 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3354 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3359 rtx sum
= XEXP (op
, 0);
3360 HOST_WIDE_INT summand
;
3362 /* We have to be careful here, because it is the referenced address
3363 that must be 32k from _SDA_BASE_, not just the symbol. */
3364 summand
= INTVAL (XEXP (sum
, 1));
3365 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3368 sym_ref
= XEXP (sum
, 0);
3371 return SYMBOL_REF_SMALL_P (sym_ref
);
3377 /* Return true if either operand is a general purpose register. */
3380 gpr_or_gpr_p (rtx op0
, rtx op1
)
3382 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3383 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3387 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3390 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3392 switch (GET_CODE (op
))
3395 if (RS6000_SYMBOL_REF_TLS_P (op
))
3397 else if (CONSTANT_POOL_ADDRESS_P (op
))
3399 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3407 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3416 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3417 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3419 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3428 constant_pool_expr_p (rtx op
)
3432 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3436 toc_relative_expr_p (rtx op
)
3440 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3444 legitimate_constant_pool_address_p (rtx x
)
3447 && GET_CODE (x
) == PLUS
3448 && GET_CODE (XEXP (x
, 0)) == REG
3449 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3450 && constant_pool_expr_p (XEXP (x
, 1)));
3454 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3456 return (DEFAULT_ABI
== ABI_V4
3457 && !flag_pic
&& !TARGET_TOC
3458 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3459 && small_data_operand (x
, mode
));
3462 /* SPE offset addressing is limited to 5-bits worth of double words. */
3463 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3466 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3468 unsigned HOST_WIDE_INT offset
, extra
;
3470 if (GET_CODE (x
) != PLUS
)
3472 if (GET_CODE (XEXP (x
, 0)) != REG
)
3474 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3476 if (legitimate_constant_pool_address_p (x
))
3478 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3481 offset
= INTVAL (XEXP (x
, 1));
3489 /* AltiVec vector modes. Only reg+reg addressing is valid and
3490 constant offset zero should not occur due to canonicalization. */
3497 /* Paired vector modes. Only reg+reg addressing is valid and
3498 constant offset zero should not occur due to canonicalization. */
3499 if (TARGET_PAIRED_FLOAT
)
3501 /* SPE vector modes. */
3502 return SPE_CONST_OFFSET_OK (offset
);
3505 if (TARGET_E500_DOUBLE
)
3506 return SPE_CONST_OFFSET_OK (offset
);
3510 /* On e500v2, we may have:
3512 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3514 Which gets addressed with evldd instructions. */
3515 if (TARGET_E500_DOUBLE
)
3516 return SPE_CONST_OFFSET_OK (offset
);
3518 if (mode
== DFmode
|| mode
== DDmode
|| !TARGET_POWERPC64
)
3520 else if (offset
& 3)
3525 if (TARGET_E500_DOUBLE
)
3526 return (SPE_CONST_OFFSET_OK (offset
)
3527 && SPE_CONST_OFFSET_OK (offset
+ 8));
3531 if (mode
== TFmode
|| mode
== TDmode
|| !TARGET_POWERPC64
)
3533 else if (offset
& 3)
3544 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3548 legitimate_indexed_address_p (rtx x
, int strict
)
3552 if (GET_CODE (x
) != PLUS
)
3558 /* Recognize the rtl generated by reload which we know will later be
3559 replaced with proper base and index regs. */
3561 && reload_in_progress
3562 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
3566 return (REG_P (op0
) && REG_P (op1
)
3567 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3568 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3569 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3570 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
3574 legitimate_indirect_address_p (rtx x
, int strict
)
3576 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3580 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3582 if (!TARGET_MACHO
|| !flag_pic
3583 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
3587 if (GET_CODE (x
) != LO_SUM
)
3589 if (GET_CODE (XEXP (x
, 0)) != REG
)
3591 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3595 return CONSTANT_P (x
);
3599 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3601 if (GET_CODE (x
) != LO_SUM
)
3603 if (GET_CODE (XEXP (x
, 0)) != REG
)
3605 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3607 /* Restrict addressing for DI because of our SUBREG hackery. */
3608 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3609 || mode
== DDmode
|| mode
== TDmode
3614 if (TARGET_ELF
|| TARGET_MACHO
)
3616 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3620 if (GET_MODE_NUNITS (mode
) != 1)
3622 if (GET_MODE_BITSIZE (mode
) > 64
3623 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3624 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
3625 && (mode
== DFmode
|| mode
== DDmode
))))
3628 return CONSTANT_P (x
);
3635 /* Try machine-dependent ways of modifying an illegitimate address
3636 to be legitimate. If we find one, return the new, valid address.
3637 This is used from only one place: `memory_address' in explow.c.
3639 OLDX is the address as it was before break_out_memory_refs was
3640 called. In some cases it is useful to look at this to decide what
3643 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3645 It is always safe for this function to do nothing. It exists to
3646 recognize opportunities to optimize the output.
3648 On RS/6000, first check for the sum of a register with a constant
3649 integer that is out of range. If so, generate code to add the
3650 constant with the low-order 16 bits masked to the register and force
3651 this result into another register (this can be done with `cau').
3652 Then generate an address of REG+(CONST&0xffff), allowing for the
3653 possibility of bit 16 being a one.
3655 Then check for the sum of a register and something not constant, try to
3656 load the other things into a register and return the sum. */
3659 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3660 enum machine_mode mode
)
3662 if (GET_CODE (x
) == SYMBOL_REF
)
3664 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3666 return rs6000_legitimize_tls_address (x
, model
);
3669 if (GET_CODE (x
) == PLUS
3670 && GET_CODE (XEXP (x
, 0)) == REG
3671 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3672 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000
3673 && !(SPE_VECTOR_MODE (mode
)
3674 || ALTIVEC_VECTOR_MODE (mode
)
3675 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3676 || mode
== DImode
|| mode
== DDmode
3677 || mode
== TDmode
))))
3679 HOST_WIDE_INT high_int
, low_int
;
3681 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3682 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3683 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3684 GEN_INT (high_int
)), 0);
3685 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3687 else if (GET_CODE (x
) == PLUS
3688 && GET_CODE (XEXP (x
, 0)) == REG
3689 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3690 && GET_MODE_NUNITS (mode
) == 1
3691 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3693 || ((mode
!= DImode
&& mode
!= DFmode
&& mode
!= DDmode
)
3694 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
)))
3695 && (TARGET_POWERPC64
|| mode
!= DImode
)
3700 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3701 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3703 else if (ALTIVEC_VECTOR_MODE (mode
))
3707 /* Make sure both operands are registers. */
3708 if (GET_CODE (x
) == PLUS
)
3709 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3710 force_reg (Pmode
, XEXP (x
, 1)));
3712 reg
= force_reg (Pmode
, x
);
3715 else if (SPE_VECTOR_MODE (mode
)
3716 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3717 || mode
== DDmode
|| mode
== TDmode
3718 || mode
== DImode
)))
3722 /* We accept [reg + reg] and [reg + OFFSET]. */
3724 if (GET_CODE (x
) == PLUS
)
3726 rtx op1
= XEXP (x
, 0);
3727 rtx op2
= XEXP (x
, 1);
3730 op1
= force_reg (Pmode
, op1
);
3732 if (GET_CODE (op2
) != REG
3733 && (GET_CODE (op2
) != CONST_INT
3734 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
3735 || (GET_MODE_SIZE (mode
) > 8
3736 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
3737 op2
= force_reg (Pmode
, op2
);
3739 /* We can't always do [reg + reg] for these, because [reg +
3740 reg + offset] is not a legitimate addressing mode. */
3741 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3743 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
3744 return force_reg (Pmode
, y
);
3749 return force_reg (Pmode
, x
);
3755 && GET_CODE (x
) != CONST_INT
3756 && GET_CODE (x
) != CONST_DOUBLE
3758 && GET_MODE_NUNITS (mode
) == 1
3759 && (GET_MODE_BITSIZE (mode
) <= 32
3760 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3761 && (mode
== DFmode
|| mode
== DDmode
))))
3763 rtx reg
= gen_reg_rtx (Pmode
);
3764 emit_insn (gen_elf_high (reg
, x
));
3765 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3767 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3770 && ! MACHO_DYNAMIC_NO_PIC_P
3772 && GET_CODE (x
) != CONST_INT
3773 && GET_CODE (x
) != CONST_DOUBLE
3775 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3776 || (mode
!= DFmode
&& mode
!= DDmode
))
3780 rtx reg
= gen_reg_rtx (Pmode
);
3781 emit_insn (gen_macho_high (reg
, x
));
3782 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3785 && GET_CODE (x
) == SYMBOL_REF
3786 && constant_pool_expr_p (x
)
3787 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3789 return create_TOC_reference (x
);
3795 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3796 We need to emit DTP-relative relocations. */
3799 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3804 fputs ("\t.long\t", file
);
3807 fputs (DOUBLE_INT_ASM_OP
, file
);
3812 output_addr_const (file
, x
);
3813 fputs ("@dtprel+0x8000", file
);
3816 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3818 static GTY(()) rtx rs6000_tls_symbol
;
3820 rs6000_tls_get_addr (void)
3822 if (!rs6000_tls_symbol
)
3823 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3825 return rs6000_tls_symbol
;
3828 /* Construct the SYMBOL_REF for TLS GOT references. */
3830 static GTY(()) rtx rs6000_got_symbol
;
3832 rs6000_got_sym (void)
3834 if (!rs6000_got_symbol
)
3836 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3837 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3838 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3841 return rs6000_got_symbol
;
3844 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3845 this (thread-local) address. */
3848 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3852 dest
= gen_reg_rtx (Pmode
);
3853 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3859 tlsreg
= gen_rtx_REG (Pmode
, 13);
3860 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3864 tlsreg
= gen_rtx_REG (Pmode
, 2);
3865 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3869 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3873 tmp
= gen_reg_rtx (Pmode
);
3876 tlsreg
= gen_rtx_REG (Pmode
, 13);
3877 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3881 tlsreg
= gen_rtx_REG (Pmode
, 2);
3882 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3886 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3888 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3893 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3895 /* We currently use relocations like @got@tlsgd for tls, which
3896 means the linker will handle allocation of tls entries, placing
3897 them in the .got section. So use a pointer to the .got section,
3898 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3899 or to secondary GOT sections used by 32-bit -fPIC. */
3901 got
= gen_rtx_REG (Pmode
, 2);
3905 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3908 rtx gsym
= rs6000_got_sym ();
3909 got
= gen_reg_rtx (Pmode
);
3911 rs6000_emit_move (got
, gsym
, Pmode
);
3917 tmp1
= gen_reg_rtx (Pmode
);
3918 tmp2
= gen_reg_rtx (Pmode
);
3919 tmp3
= gen_reg_rtx (Pmode
);
3920 mem
= gen_const_mem (Pmode
, tmp1
);
3922 first
= emit_insn (gen_load_toc_v4_PIC_1b (gsym
));
3923 emit_move_insn (tmp1
,
3924 gen_rtx_REG (Pmode
, LR_REGNO
));
3925 emit_move_insn (tmp2
, mem
);
3926 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3927 last
= emit_move_insn (got
, tmp3
);
3928 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
3933 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3935 r3
= gen_rtx_REG (Pmode
, 3);
3936 tga
= rs6000_tls_get_addr ();
3938 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
3939 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
3940 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
3941 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
3942 else if (DEFAULT_ABI
== ABI_V4
)
3943 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
3948 insn
= emit_call_insn (insn
);
3949 RTL_CONST_CALL_P (insn
) = 1;
3950 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3951 insn
= get_insns ();
3953 emit_libcall_block (insn
, dest
, r3
, addr
);
3955 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3957 r3
= gen_rtx_REG (Pmode
, 3);
3958 tga
= rs6000_tls_get_addr ();
3960 if (DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
3961 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
3962 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_64BIT
)
3963 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
3964 else if (DEFAULT_ABI
== ABI_V4
)
3965 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
3970 insn
= emit_call_insn (insn
);
3971 RTL_CONST_CALL_P (insn
) = 1;
3972 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3973 insn
= get_insns ();
3975 tmp1
= gen_reg_rtx (Pmode
);
3976 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3978 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3979 if (rs6000_tls_size
== 16)
3982 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3984 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3986 else if (rs6000_tls_size
== 32)
3988 tmp2
= gen_reg_rtx (Pmode
);
3990 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3992 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3995 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3997 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
4001 tmp2
= gen_reg_rtx (Pmode
);
4003 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
4005 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
4007 insn
= gen_rtx_SET (Pmode
, dest
,
4008 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
4014 /* IE, or 64-bit offset LE. */
4015 tmp2
= gen_reg_rtx (Pmode
);
4017 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
4019 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
4022 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
4024 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
4032 /* Return 1 if X contains a thread-local symbol. */
4035 rs6000_tls_referenced_p (rtx x
)
4037 if (! TARGET_HAVE_TLS
)
4040 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
4043 /* Return 1 if *X is a thread-local symbol. This is the same as
4044 rs6000_tls_symbol_ref except for the type of the unused argument. */
4047 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4049 return RS6000_SYMBOL_REF_TLS_P (*x
);
4052 /* The convention appears to be to define this wherever it is used.
4053 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
4054 is now used here. */
4055 #ifndef REG_MODE_OK_FOR_BASE_P
4056 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
4059 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4060 replace the input X, or the original X if no replacement is called for.
4061 The output parameter *WIN is 1 if the calling macro should goto WIN,
4064 For RS/6000, we wish to handle large displacements off a base
4065 register by splitting the addend across an addiu/addis and the mem insn.
4066 This cuts number of extra insns needed from 3 to 1.
4068 On Darwin, we use this to generate code for floating point constants.
4069 A movsf_low is generated so we wind up with 2 instructions rather than 3.
4070 The Darwin code is inside #if TARGET_MACHO because only then is
4071 machopic_function_base_name() defined. */
4073 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
4074 int opnum
, int type
,
4075 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4077 /* We must recognize output that we have already generated ourselves. */
4078 if (GET_CODE (x
) == PLUS
4079 && GET_CODE (XEXP (x
, 0)) == PLUS
4080 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4081 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4082 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4084 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4085 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4086 opnum
, (enum reload_type
)type
);
4092 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
4093 && GET_CODE (x
) == LO_SUM
4094 && GET_CODE (XEXP (x
, 0)) == PLUS
4095 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
4096 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
4097 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
4098 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
4099 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
4100 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
4101 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
4103 /* Result of previous invocation of this function on Darwin
4104 floating point constant. */
4105 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4106 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4107 opnum
, (enum reload_type
)type
);
4113 /* Force ld/std non-word aligned offset into base register by wrapping
4115 if (GET_CODE (x
) == PLUS
4116 && GET_CODE (XEXP (x
, 0)) == REG
4117 && REGNO (XEXP (x
, 0)) < 32
4118 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4119 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4120 && (INTVAL (XEXP (x
, 1)) & 3) != 0
4121 && !ALTIVEC_VECTOR_MODE (mode
)
4122 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
4123 && TARGET_POWERPC64
)
4125 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
4126 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4127 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4128 opnum
, (enum reload_type
) type
);
4133 if (GET_CODE (x
) == PLUS
4134 && GET_CODE (XEXP (x
, 0)) == REG
4135 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
4136 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4137 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4138 && !SPE_VECTOR_MODE (mode
)
4139 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
4140 || mode
== DDmode
|| mode
== TDmode
4142 && !ALTIVEC_VECTOR_MODE (mode
))
4144 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
4145 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
4147 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4149 /* Check for 32-bit overflow. */
4150 if (high
+ low
!= val
)
4156 /* Reload the high part into a base reg; leave the low part
4157 in the mem directly. */
4159 x
= gen_rtx_PLUS (GET_MODE (x
),
4160 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
4164 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4165 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4166 opnum
, (enum reload_type
)type
);
4171 if (GET_CODE (x
) == SYMBOL_REF
4172 && !ALTIVEC_VECTOR_MODE (mode
)
4173 && !SPE_VECTOR_MODE (mode
)
4175 && DEFAULT_ABI
== ABI_DARWIN
4176 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
4178 && DEFAULT_ABI
== ABI_V4
4181 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4182 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4186 && (mode
!= DImode
|| TARGET_POWERPC64
)
4187 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
4188 || (TARGET_FPRS
&& TARGET_HARD_FLOAT
)))
4193 rtx offset
= gen_rtx_CONST (Pmode
,
4194 gen_rtx_MINUS (Pmode
, x
,
4195 machopic_function_base_sym ()));
4196 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4197 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
4198 gen_rtx_HIGH (Pmode
, offset
)), offset
);
4202 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4203 gen_rtx_HIGH (Pmode
, x
), x
);
4205 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4206 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4207 opnum
, (enum reload_type
)type
);
4212 /* Reload an offset address wrapped by an AND that represents the
4213 masking of the lower bits. Strip the outer AND and let reload
4214 convert the offset address into an indirect address. */
4216 && ALTIVEC_VECTOR_MODE (mode
)
4217 && GET_CODE (x
) == AND
4218 && GET_CODE (XEXP (x
, 0)) == PLUS
4219 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4220 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4221 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4222 && INTVAL (XEXP (x
, 1)) == -16)
4230 && GET_CODE (x
) == SYMBOL_REF
4231 && constant_pool_expr_p (x
)
4232 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
4234 x
= create_TOC_reference (x
);
4242 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4243 that is a valid memory address for an instruction.
4244 The MODE argument is the machine mode for the MEM expression
4245 that wants to use this address.
4247 On the RS/6000, there are four valid address: a SYMBOL_REF that
4248 refers to a constant pool entry of an address (or the sum of it
4249 plus a constant), a short (16-bit signed) constant plus a register,
4250 the sum of two registers, or a register indirect, possibly with an
4251 auto-increment. For DFmode, DDmode and DImode with a constant plus
4252 register, we must ensure that both words are addressable or PowerPC64
4253 with offset word aligned.
4255 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4256 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4257 because adjacent memory cells are accessed by adding word-sized offsets
4258 during assembly output. */
4260 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
4262 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4264 && ALTIVEC_VECTOR_MODE (mode
)
4265 && GET_CODE (x
) == AND
4266 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4267 && INTVAL (XEXP (x
, 1)) == -16)
4270 if (RS6000_SYMBOL_REF_TLS_P (x
))
4272 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
4274 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
4275 && !ALTIVEC_VECTOR_MODE (mode
)
4276 && !SPE_VECTOR_MODE (mode
)
4279 /* Restrict addressing for DI because of our SUBREG hackery. */
4280 && !(TARGET_E500_DOUBLE
4281 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4283 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
4285 if (legitimate_small_data_p (mode
, x
))
4287 if (legitimate_constant_pool_address_p (x
))
4289 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4291 && GET_CODE (x
) == PLUS
4292 && GET_CODE (XEXP (x
, 0)) == REG
4293 && (XEXP (x
, 0) == virtual_stack_vars_rtx
4294 || XEXP (x
, 0) == arg_pointer_rtx
)
4295 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4297 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
4302 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4304 || (mode
!= DFmode
&& mode
!= DDmode
)
4305 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
4306 && (TARGET_POWERPC64
|| mode
!= DImode
)
4307 && legitimate_indexed_address_p (x
, reg_ok_strict
))
4309 if (GET_CODE (x
) == PRE_MODIFY
4313 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4315 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
4316 && (TARGET_POWERPC64
|| mode
!= DImode
)
4317 && !ALTIVEC_VECTOR_MODE (mode
)
4318 && !SPE_VECTOR_MODE (mode
)
4319 /* Restrict addressing for DI because of our SUBREG hackery. */
4320 && !(TARGET_E500_DOUBLE
4321 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4323 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
4324 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1), reg_ok_strict
)
4325 || legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
))
4326 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4328 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4333 /* Go to LABEL if ADDR (a legitimate address expression)
4334 has an effect that depends on the machine mode it is used for.
4336 On the RS/6000 this is true of all integral offsets (since AltiVec
4337 modes don't allow them) or is a pre-increment or decrement.
4339 ??? Except that due to conceptual problems in offsettable_address_p
4340 we can't really report the problems of integral offsets. So leave
4341 this assuming that the adjustable offset must be valid for the
4342 sub-words of a TFmode operand, which is what we had before. */
4345 rs6000_mode_dependent_address (rtx addr
)
4347 switch (GET_CODE (addr
))
4350 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4352 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4353 return val
+ 12 + 0x8000 >= 0x10000;
4360 /* Auto-increment cases are now treated generically in recog.c. */
4362 return TARGET_UPDATE
;
4371 /* More elaborate version of recog's offsettable_memref_p predicate
4372 that works around the ??? note of rs6000_mode_dependent_address.
4373 In particular it accepts
4375 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4377 in 32-bit mode, that the recog predicate rejects. */
4380 rs6000_offsettable_memref_p (rtx op
)
4385 /* First mimic offsettable_memref_p. */
4386 if (offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)))
4389 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4390 the latter predicate knows nothing about the mode of the memory
4391 reference and, therefore, assumes that it is the largest supported
4392 mode (TFmode). As a consequence, legitimate offsettable memory
4393 references are rejected. rs6000_legitimate_offset_address_p contains
4394 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4395 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0), 1);
4398 /* Return number of consecutive hard regs needed starting at reg REGNO
4399 to hold something of mode MODE.
4400 This is ordinarily the length in words of a value of mode MODE
4401 but can be less for certain modes in special long registers.
4403 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4404 scalar instructions. The upper 32 bits are only available to the
4407 POWER and PowerPC GPRs hold 32 bits worth;
4408 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4411 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4413 if (FP_REGNO_P (regno
))
4414 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4416 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4417 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4419 if (ALTIVEC_REGNO_P (regno
))
4421 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4423 /* The value returned for SCmode in the E500 double case is 2 for
4424 ABI compatibility; storing an SCmode value in a single register
4425 would require function_arg and rs6000_spe_function_arg to handle
4426 SCmode so as to pass the value correctly in a pair of
4428 if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
4429 && !DECIMAL_FLOAT_MODE_P (mode
))
4430 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4432 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4435 /* Change register usage conditional on target flags. */
4437 rs6000_conditional_register_usage (void)
4441 /* Set MQ register fixed (already call_used) if not POWER
4442 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4447 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4449 fixed_regs
[13] = call_used_regs
[13]
4450 = call_really_used_regs
[13] = 1;
4452 /* Conditionally disable FPRs. */
4453 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4454 for (i
= 32; i
< 64; i
++)
4455 fixed_regs
[i
] = call_used_regs
[i
]
4456 = call_really_used_regs
[i
] = 1;
4458 /* The TOC register is not killed across calls in a way that is
4459 visible to the compiler. */
4460 if (DEFAULT_ABI
== ABI_AIX
)
4461 call_really_used_regs
[2] = 0;
4463 if (DEFAULT_ABI
== ABI_V4
4464 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4466 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4468 if (DEFAULT_ABI
== ABI_V4
4469 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4471 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4472 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4473 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4475 if (DEFAULT_ABI
== ABI_DARWIN
4476 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4477 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4478 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4479 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4481 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4482 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4483 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4487 global_regs
[SPEFSCR_REGNO
] = 1;
4488 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4489 registers in prologues and epilogues. We no longer use r14
4490 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4491 pool for link-compatibility with older versions of GCC. Once
4492 "old" code has died out, we can return r14 to the allocation
4495 = call_used_regs
[14]
4496 = call_really_used_regs
[14] = 1;
4499 if (!TARGET_ALTIVEC
)
4501 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4502 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4503 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4507 global_regs
[VSCR_REGNO
] = 1;
4509 if (TARGET_ALTIVEC_ABI
)
4511 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4512 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4514 /* AIX reserves VR20:31 in non-extended ABI mode. */
4516 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
4517 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4521 /* Try to output insns to set TARGET equal to the constant C if it can
4522 be done in less than N insns. Do all computations in MODE.
4523 Returns the place where the output has been placed if it can be
4524 done and the insns have been emitted. If it would take more than N
4525 insns, zero is returned and no insns and emitted. */
4528 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4529 rtx source
, int n ATTRIBUTE_UNUSED
)
4531 rtx result
, insn
, set
;
4532 HOST_WIDE_INT c0
, c1
;
4539 dest
= gen_reg_rtx (mode
);
4540 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4544 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
4546 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
4547 GEN_INT (INTVAL (source
)
4548 & (~ (HOST_WIDE_INT
) 0xffff))));
4549 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4550 gen_rtx_IOR (SImode
, copy_rtx (result
),
4551 GEN_INT (INTVAL (source
) & 0xffff))));
4556 switch (GET_CODE (source
))
4559 c0
= INTVAL (source
);
4564 #if HOST_BITS_PER_WIDE_INT >= 64
4565 c0
= CONST_DOUBLE_LOW (source
);
4568 c0
= CONST_DOUBLE_LOW (source
);
4569 c1
= CONST_DOUBLE_HIGH (source
);
4577 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4584 insn
= get_last_insn ();
4585 set
= single_set (insn
);
4586 if (! CONSTANT_P (SET_SRC (set
)))
4587 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4592 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4593 fall back to a straight forward decomposition. We do this to avoid
4594 exponential run times encountered when looking for longer sequences
4595 with rs6000_emit_set_const. */
4597 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4599 if (!TARGET_POWERPC64
)
4601 rtx operand1
, operand2
;
4603 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4605 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
4607 emit_move_insn (operand1
, GEN_INT (c1
));
4608 emit_move_insn (operand2
, GEN_INT (c2
));
4612 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4615 ud2
= (c1
& 0xffff0000) >> 16;
4616 #if HOST_BITS_PER_WIDE_INT >= 64
4620 ud4
= (c2
& 0xffff0000) >> 16;
4622 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4623 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4626 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4628 emit_move_insn (dest
, GEN_INT (ud1
));
4631 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4632 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4635 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4638 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4640 emit_move_insn (copy_rtx (dest
),
4641 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4644 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4645 || (ud4
== 0 && ! (ud3
& 0x8000)))
4648 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4651 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4654 emit_move_insn (copy_rtx (dest
),
4655 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4657 emit_move_insn (copy_rtx (dest
),
4658 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4661 emit_move_insn (copy_rtx (dest
),
4662 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4668 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4671 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4674 emit_move_insn (copy_rtx (dest
),
4675 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4678 emit_move_insn (copy_rtx (dest
),
4679 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4682 emit_move_insn (copy_rtx (dest
),
4683 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4684 GEN_INT (ud2
<< 16)));
4686 emit_move_insn (copy_rtx (dest
),
4687 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
4693 /* Helper for the following. Get rid of [r+r] memory refs
4694 in cases where it won't work (TImode, TFmode, TDmode). */
4697 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4699 if (GET_CODE (operands
[0]) == MEM
4700 && GET_CODE (XEXP (operands
[0], 0)) != REG
4701 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4702 && ! reload_in_progress
)
4704 = replace_equiv_address (operands
[0],
4705 copy_addr_to_reg (XEXP (operands
[0], 0)));
4707 if (GET_CODE (operands
[1]) == MEM
4708 && GET_CODE (XEXP (operands
[1], 0)) != REG
4709 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4710 && ! reload_in_progress
)
4712 = replace_equiv_address (operands
[1],
4713 copy_addr_to_reg (XEXP (operands
[1], 0)));
4716 /* Emit a move from SOURCE to DEST in mode MODE. */
4718 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4722 operands
[1] = source
;
4724 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4725 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4726 && ! FLOAT_MODE_P (mode
)
4727 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4729 /* FIXME. This should never happen. */
4730 /* Since it seems that it does, do the safe thing and convert
4732 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4734 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
4735 || FLOAT_MODE_P (mode
)
4736 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
4737 || CONST_DOUBLE_LOW (operands
[1]) < 0)
4738 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
4739 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
4741 /* Check if GCC is setting up a block move that will end up using FP
4742 registers as temporaries. We must make sure this is acceptable. */
4743 if (GET_CODE (operands
[0]) == MEM
4744 && GET_CODE (operands
[1]) == MEM
4746 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4747 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4748 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4749 ? 32 : MEM_ALIGN (operands
[0])))
4750 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4752 : MEM_ALIGN (operands
[1]))))
4753 && ! MEM_VOLATILE_P (operands
[0])
4754 && ! MEM_VOLATILE_P (operands
[1]))
4756 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4757 adjust_address (operands
[1], SImode
, 0));
4758 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
4759 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
4763 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
4764 && !gpc_reg_operand (operands
[1], mode
))
4765 operands
[1] = force_reg (mode
, operands
[1]);
4767 if (mode
== SFmode
&& ! TARGET_POWERPC
4768 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4769 && GET_CODE (operands
[0]) == MEM
)
4773 if (reload_in_progress
|| reload_completed
)
4774 regnum
= true_regnum (operands
[1]);
4775 else if (GET_CODE (operands
[1]) == REG
)
4776 regnum
= REGNO (operands
[1]);
4780 /* If operands[1] is a register, on POWER it may have
4781 double-precision data in it, so truncate it to single
4783 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4786 newreg
= (!can_create_pseudo_p () ? copy_rtx (operands
[1])
4787 : gen_reg_rtx (mode
));
4788 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4789 operands
[1] = newreg
;
4793 /* Recognize the case where operand[1] is a reference to thread-local
4794 data and load its address to a register. */
4795 if (rs6000_tls_referenced_p (operands
[1]))
4797 enum tls_model model
;
4798 rtx tmp
= operands
[1];
4801 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
4803 addend
= XEXP (XEXP (tmp
, 0), 1);
4804 tmp
= XEXP (XEXP (tmp
, 0), 0);
4807 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
4808 model
= SYMBOL_REF_TLS_MODEL (tmp
);
4809 gcc_assert (model
!= 0);
4811 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
4814 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
4815 tmp
= force_operand (tmp
, operands
[0]);
4820 /* Handle the case where reload calls us with an invalid address. */
4821 if (reload_in_progress
&& mode
== Pmode
4822 && (! general_operand (operands
[1], mode
)
4823 || ! nonimmediate_operand (operands
[0], mode
)))
4826 /* 128-bit constant floating-point values on Darwin should really be
4827 loaded as two parts. */
4828 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
4829 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4831 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4832 know how to get a DFmode SUBREG of a TFmode. */
4833 enum machine_mode imode
= (TARGET_E500_DOUBLE
? DFmode
: DImode
);
4834 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
, 0),
4835 simplify_gen_subreg (imode
, operands
[1], mode
, 0),
4837 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
,
4838 GET_MODE_SIZE (imode
)),
4839 simplify_gen_subreg (imode
, operands
[1], mode
,
4840 GET_MODE_SIZE (imode
)),
4845 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
4846 cfun
->machine
->sdmode_stack_slot
=
4847 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
4849 if (reload_in_progress
4851 && MEM_P (operands
[0])
4852 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
4853 && REG_P (operands
[1]))
4855 if (FP_REGNO_P (REGNO (operands
[1])))
4857 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
4858 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4859 emit_insn (gen_movsd_store (mem
, operands
[1]));
4861 else if (INT_REGNO_P (REGNO (operands
[1])))
4863 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
4864 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4865 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
4871 if (reload_in_progress
4873 && REG_P (operands
[0])
4874 && MEM_P (operands
[1])
4875 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
4877 if (FP_REGNO_P (REGNO (operands
[0])))
4879 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
4880 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4881 emit_insn (gen_movsd_load (operands
[0], mem
));
4883 else if (INT_REGNO_P (REGNO (operands
[0])))
4885 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
4886 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4887 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
4894 /* FIXME: In the long term, this switch statement should go away
4895 and be replaced by a sequence of tests based on things like
4901 if (CONSTANT_P (operands
[1])
4902 && GET_CODE (operands
[1]) != CONST_INT
)
4903 operands
[1] = force_const_mem (mode
, operands
[1]);
4908 rs6000_eliminate_indexed_memrefs (operands
);
4915 if (CONSTANT_P (operands
[1])
4916 && ! easy_fp_constant (operands
[1], mode
))
4917 operands
[1] = force_const_mem (mode
, operands
[1]);
4928 if (CONSTANT_P (operands
[1])
4929 && !easy_vector_constant (operands
[1], mode
))
4930 operands
[1] = force_const_mem (mode
, operands
[1]);
4935 /* Use default pattern for address of ELF small data */
4938 && DEFAULT_ABI
== ABI_V4
4939 && (GET_CODE (operands
[1]) == SYMBOL_REF
4940 || GET_CODE (operands
[1]) == CONST
)
4941 && small_data_operand (operands
[1], mode
))
4943 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4947 if (DEFAULT_ABI
== ABI_V4
4948 && mode
== Pmode
&& mode
== SImode
4949 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4951 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4955 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4959 && CONSTANT_P (operands
[1])
4960 && GET_CODE (operands
[1]) != HIGH
4961 && GET_CODE (operands
[1]) != CONST_INT
)
4963 rtx target
= (!can_create_pseudo_p ()
4965 : gen_reg_rtx (mode
));
4967 /* If this is a function address on -mcall-aixdesc,
4968 convert it to the address of the descriptor. */
4969 if (DEFAULT_ABI
== ABI_AIX
4970 && GET_CODE (operands
[1]) == SYMBOL_REF
4971 && XSTR (operands
[1], 0)[0] == '.')
4973 const char *name
= XSTR (operands
[1], 0);
4975 while (*name
== '.')
4977 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4978 CONSTANT_POOL_ADDRESS_P (new_ref
)
4979 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4980 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4981 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4982 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
4983 operands
[1] = new_ref
;
4986 if (DEFAULT_ABI
== ABI_DARWIN
)
4989 if (MACHO_DYNAMIC_NO_PIC_P
)
4991 /* Take care of any required data indirection. */
4992 operands
[1] = rs6000_machopic_legitimize_pic_address (
4993 operands
[1], mode
, operands
[0]);
4994 if (operands
[0] != operands
[1])
4995 emit_insn (gen_rtx_SET (VOIDmode
,
4996 operands
[0], operands
[1]));
5000 emit_insn (gen_macho_high (target
, operands
[1]));
5001 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
5005 emit_insn (gen_elf_high (target
, operands
[1]));
5006 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
5010 /* If this is a SYMBOL_REF that refers to a constant pool entry,
5011 and we have put it in the TOC, we just need to make a TOC-relative
5014 && GET_CODE (operands
[1]) == SYMBOL_REF
5015 && constant_pool_expr_p (operands
[1])
5016 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
5017 get_pool_mode (operands
[1])))
5019 operands
[1] = create_TOC_reference (operands
[1]);
5021 else if (mode
== Pmode
5022 && CONSTANT_P (operands
[1])
5023 && ((GET_CODE (operands
[1]) != CONST_INT
5024 && ! easy_fp_constant (operands
[1], mode
))
5025 || (GET_CODE (operands
[1]) == CONST_INT
5026 && num_insns_constant (operands
[1], mode
) > 2)
5027 || (GET_CODE (operands
[0]) == REG
5028 && FP_REGNO_P (REGNO (operands
[0]))))
5029 && GET_CODE (operands
[1]) != HIGH
5030 && ! legitimate_constant_pool_address_p (operands
[1])
5031 && ! toc_relative_expr_p (operands
[1]))
5033 /* Emit a USE operation so that the constant isn't deleted if
5034 expensive optimizations are turned on because nobody
5035 references it. This should only be done for operands that
5036 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5037 This should not be done for operands that contain LABEL_REFs.
5038 For now, we just handle the obvious case. */
5039 if (GET_CODE (operands
[1]) != LABEL_REF
)
5040 emit_use (operands
[1]);
5043 /* Darwin uses a special PIC legitimizer. */
5044 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
5047 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
5049 if (operands
[0] != operands
[1])
5050 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5055 /* If we are to limit the number of things we put in the TOC and
5056 this is a symbol plus a constant we can add in one insn,
5057 just put the symbol in the TOC and add the constant. Don't do
5058 this if reload is in progress. */
5059 if (GET_CODE (operands
[1]) == CONST
5060 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
5061 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
5062 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
5063 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
5064 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
5065 && ! side_effects_p (operands
[0]))
5068 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
5069 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
5071 sym
= force_reg (mode
, sym
);
5073 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
5075 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
5079 operands
[1] = force_const_mem (mode
, operands
[1]);
5082 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
5083 && constant_pool_expr_p (XEXP (operands
[1], 0))
5084 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
5085 get_pool_constant (XEXP (operands
[1], 0)),
5086 get_pool_mode (XEXP (operands
[1], 0))))
5089 = gen_const_mem (mode
,
5090 create_TOC_reference (XEXP (operands
[1], 0)));
5091 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
5097 rs6000_eliminate_indexed_memrefs (operands
);
5101 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5103 gen_rtx_SET (VOIDmode
,
5104 operands
[0], operands
[1]),
5105 gen_rtx_CLOBBER (VOIDmode
,
5106 gen_rtx_SCRATCH (SImode
)))));
5115 /* Above, we may have called force_const_mem which may have returned
5116 an invalid address. If we can, fix this up; otherwise, reload will
5117 have to deal with it. */
5118 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
5119 operands
[1] = validize_mem (operands
[1]);
5122 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5125 /* Nonzero if we can use a floating-point register to pass this arg. */
5126 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5127 (SCALAR_FLOAT_MODE_P (MODE) \
5128 && (CUM)->fregno <= FP_ARG_MAX_REG \
5129 && TARGET_HARD_FLOAT && TARGET_FPRS)
5131 /* Nonzero if we can use an AltiVec register to pass this arg. */
5132 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5133 (ALTIVEC_VECTOR_MODE (MODE) \
5134 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5135 && TARGET_ALTIVEC_ABI \
5138 /* Return a nonzero value to say to return the function value in
5139 memory, just as large structures are always returned. TYPE will be
5140 the data type of the value, and FNTYPE will be the type of the
5141 function doing the returning, or @code{NULL} for libcalls.
5143 The AIX ABI for the RS/6000 specifies that all structures are
5144 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5145 specifies that structures <= 8 bytes are returned in r3/r4, but a
5146 draft put them in memory, and GCC used to implement the draft
5147 instead of the final standard. Therefore, aix_struct_return
5148 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5149 compatibility can change DRAFT_V4_STRUCT_RET to override the
5150 default, and -m switches get the final word. See
5151 rs6000_override_options for more details.
5153 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5154 long double support is enabled. These values are returned in memory.
5156 int_size_in_bytes returns -1 for variable size objects, which go in
5157 memory always. The cast to unsigned makes -1 > 8. */
5160 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5162 /* In the darwin64 abi, try to use registers for larger structs
5164 if (rs6000_darwin64_abi
5165 && TREE_CODE (type
) == RECORD_TYPE
5166 && int_size_in_bytes (type
) > 0)
5168 CUMULATIVE_ARGS valcum
;
5172 valcum
.fregno
= FP_ARG_MIN_REG
;
5173 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
5174 /* Do a trial code generation as if this were going to be passed
5175 as an argument; if any part goes in memory, we return NULL. */
5176 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
5179 /* Otherwise fall through to more conventional ABI rules. */
5182 if (AGGREGATE_TYPE_P (type
)
5183 && (aix_struct_return
5184 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
5187 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5188 modes only exist for GCC vector types if -maltivec. */
5189 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
5190 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5193 /* Return synthetic vectors in memory. */
5194 if (TREE_CODE (type
) == VECTOR_TYPE
5195 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5197 static bool warned_for_return_big_vectors
= false;
5198 if (!warned_for_return_big_vectors
)
5200 warning (0, "GCC vector returned by reference: "
5201 "non-standard ABI extension with no compatibility guarantee");
5202 warned_for_return_big_vectors
= true;
5207 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
5213 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5214 for a call to a function whose data type is FNTYPE.
5215 For a library call, FNTYPE is 0.
5217 For incoming args we set the number of arguments in the prototype large
5218 so we never return a PARALLEL. */
5221 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
5222 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
5223 int libcall
, int n_named_args
)
5225 static CUMULATIVE_ARGS zero_cumulative
;
5227 *cum
= zero_cumulative
;
5229 cum
->fregno
= FP_ARG_MIN_REG
;
5230 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
5231 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
5232 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
5233 ? CALL_LIBCALL
: CALL_NORMAL
);
5234 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
5235 cum
->stdarg
= fntype
5236 && (TYPE_ARG_TYPES (fntype
) != 0
5237 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
5238 != void_type_node
));
5240 cum
->nargs_prototype
= 0;
5241 if (incoming
|| cum
->prototype
)
5242 cum
->nargs_prototype
= n_named_args
;
5244 /* Check for a longcall attribute. */
5245 if ((!fntype
&& rs6000_default_long_calls
)
5247 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
5248 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
5249 cum
->call_cookie
|= CALL_LONG
;
5251 if (TARGET_DEBUG_ARG
)
5253 fprintf (stderr
, "\ninit_cumulative_args:");
5256 tree ret_type
= TREE_TYPE (fntype
);
5257 fprintf (stderr
, " ret code = %s,",
5258 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
5261 if (cum
->call_cookie
& CALL_LONG
)
5262 fprintf (stderr
, " longcall,");
5264 fprintf (stderr
, " proto = %d, nargs = %d\n",
5265 cum
->prototype
, cum
->nargs_prototype
);
5270 && TARGET_ALTIVEC_ABI
5271 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
5273 error ("cannot return value in vector register because"
5274 " altivec instructions are disabled, use -maltivec"
5279 /* Return true if TYPE must be passed on the stack and not in registers. */
5282 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
5284 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
5285 return must_pass_in_stack_var_size (mode
, type
);
5287 return must_pass_in_stack_var_size_or_pad (mode
, type
);
5290 /* If defined, a C expression which determines whether, and in which
5291 direction, to pad out an argument with extra space. The value
5292 should be of type `enum direction': either `upward' to pad above
5293 the argument, `downward' to pad below, or `none' to inhibit
5296 For the AIX ABI structs are always stored left shifted in their
5300 function_arg_padding (enum machine_mode mode
, const_tree type
)
5302 #ifndef AGGREGATE_PADDING_FIXED
5303 #define AGGREGATE_PADDING_FIXED 0
5305 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5306 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5309 if (!AGGREGATE_PADDING_FIXED
)
5311 /* GCC used to pass structures of the same size as integer types as
5312 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5313 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5314 passed padded downward, except that -mstrict-align further
5315 muddied the water in that multi-component structures of 2 and 4
5316 bytes in size were passed padded upward.
5318 The following arranges for best compatibility with previous
5319 versions of gcc, but removes the -mstrict-align dependency. */
5320 if (BYTES_BIG_ENDIAN
)
5322 HOST_WIDE_INT size
= 0;
5324 if (mode
== BLKmode
)
5326 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
5327 size
= int_size_in_bytes (type
);
5330 size
= GET_MODE_SIZE (mode
);
5332 if (size
== 1 || size
== 2 || size
== 4)
5338 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
5340 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
5344 /* Fall back to the default. */
5345 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5348 /* If defined, a C expression that gives the alignment boundary, in bits,
5349 of an argument with the specified mode and type. If it is not defined,
5350 PARM_BOUNDARY is used for all arguments.
5352 V.4 wants long longs and doubles to be double word aligned. Just
5353 testing the mode size is a boneheaded way to do this as it means
5354 that other types such as complex int are also double word aligned.
5355 However, we're stuck with this because changing the ABI might break
5356 existing library interfaces.
5358 Doubleword align SPE vectors.
5359 Quadword align Altivec vectors.
5360 Quadword align large synthetic vector types. */
5363 function_arg_boundary (enum machine_mode mode
, tree type
)
5365 if (DEFAULT_ABI
== ABI_V4
5366 && (GET_MODE_SIZE (mode
) == 8
5367 || (TARGET_HARD_FLOAT
5369 && (mode
== TFmode
|| mode
== TDmode
))))
5371 else if (SPE_VECTOR_MODE (mode
)
5372 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5373 && int_size_in_bytes (type
) >= 8
5374 && int_size_in_bytes (type
) < 16))
5376 else if (ALTIVEC_VECTOR_MODE (mode
)
5377 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5378 && int_size_in_bytes (type
) >= 16))
5380 else if (rs6000_darwin64_abi
&& mode
== BLKmode
5381 && type
&& TYPE_ALIGN (type
) > 64)
5384 return PARM_BOUNDARY
;
5387 /* For a function parm of MODE and TYPE, return the starting word in
5388 the parameter area. NWORDS of the parameter area are already used. */
5391 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
5394 unsigned int parm_offset
;
5396 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5397 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
5398 return nwords
+ (-(parm_offset
+ nwords
) & align
);
5401 /* Compute the size (in words) of a function argument. */
5403 static unsigned long
5404 rs6000_arg_size (enum machine_mode mode
, tree type
)
5408 if (mode
!= BLKmode
)
5409 size
= GET_MODE_SIZE (mode
);
5411 size
= int_size_in_bytes (type
);
5414 return (size
+ 3) >> 2;
5416 return (size
+ 7) >> 3;
5419 /* Use this to flush pending int fields. */
5422 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
5423 HOST_WIDE_INT bitpos
)
5425 unsigned int startbit
, endbit
;
5426 int intregs
, intoffset
;
5427 enum machine_mode mode
;
5429 if (cum
->intoffset
== -1)
5432 intoffset
= cum
->intoffset
;
5433 cum
->intoffset
= -1;
5435 if (intoffset
% BITS_PER_WORD
!= 0)
5437 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5439 if (mode
== BLKmode
)
5441 /* We couldn't find an appropriate mode, which happens,
5442 e.g., in packed structs when there are 3 bytes to load.
5443 Back intoffset back to the beginning of the word in this
5445 intoffset
= intoffset
& -BITS_PER_WORD
;
5449 startbit
= intoffset
& -BITS_PER_WORD
;
5450 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5451 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5452 cum
->words
+= intregs
;
5455 /* The darwin64 ABI calls for us to recurse down through structs,
5456 looking for elements passed in registers. Unfortunately, we have
5457 to track int register count here also because of misalignments
5458 in powerpc alignment mode. */
5461 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
5463 HOST_WIDE_INT startbitpos
)
5467 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5468 if (TREE_CODE (f
) == FIELD_DECL
)
5470 HOST_WIDE_INT bitpos
= startbitpos
;
5471 tree ftype
= TREE_TYPE (f
);
5472 enum machine_mode mode
;
5473 if (ftype
== error_mark_node
)
5475 mode
= TYPE_MODE (ftype
);
5477 if (DECL_SIZE (f
) != 0
5478 && host_integerp (bit_position (f
), 1))
5479 bitpos
+= int_bit_position (f
);
5481 /* ??? FIXME: else assume zero offset. */
5483 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5484 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
5485 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5487 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5488 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5489 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5491 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
5493 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5497 else if (cum
->intoffset
== -1)
5498 cum
->intoffset
= bitpos
;
5502 /* Update the data in CUM to advance over an argument
5503 of mode MODE and data type TYPE.
5504 (TYPE is null for libcalls where that information may not be available.)
5506 Note that for args passed by reference, function_arg will be called
5507 with MODE and TYPE set to that of the pointer to the arg, not the arg
5511 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5512 tree type
, int named
, int depth
)
5516 /* Only tick off an argument if we're not recursing. */
5518 cum
->nargs_prototype
--;
5520 if (TARGET_ALTIVEC_ABI
5521 && (ALTIVEC_VECTOR_MODE (mode
)
5522 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5523 && int_size_in_bytes (type
) == 16)))
5527 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5530 if (!TARGET_ALTIVEC
)
5531 error ("cannot pass argument in vector register because"
5532 " altivec instructions are disabled, use -maltivec"
5535 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5536 even if it is going to be passed in a vector register.
5537 Darwin does the same for variable-argument functions. */
5538 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5539 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5549 /* Vector parameters must be 16-byte aligned. This places
5550 them at 2 mod 4 in terms of words in 32-bit mode, since
5551 the parameter save area starts at offset 24 from the
5552 stack. In 64-bit mode, they just have to start on an
5553 even word, since the parameter save area is 16-byte
5554 aligned. Space for GPRs is reserved even if the argument
5555 will be passed in memory. */
5557 align
= (2 - cum
->words
) & 3;
5559 align
= cum
->words
& 1;
5560 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5562 if (TARGET_DEBUG_ARG
)
5564 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5566 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5567 cum
->nargs_prototype
, cum
->prototype
,
5568 GET_MODE_NAME (mode
));
5572 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5574 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5577 else if (rs6000_darwin64_abi
5579 && TREE_CODE (type
) == RECORD_TYPE
5580 && (size
= int_size_in_bytes (type
)) > 0)
5582 /* Variable sized types have size == -1 and are
5583 treated as if consisting entirely of ints.
5584 Pad to 16 byte boundary if needed. */
5585 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5586 && (cum
->words
% 2) != 0)
5588 /* For varargs, we can just go up by the size of the struct. */
5590 cum
->words
+= (size
+ 7) / 8;
5593 /* It is tempting to say int register count just goes up by
5594 sizeof(type)/8, but this is wrong in a case such as
5595 { int; double; int; } [powerpc alignment]. We have to
5596 grovel through the fields for these too. */
5598 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
5599 rs6000_darwin64_record_arg_advance_flush (cum
,
5600 size
* BITS_PER_UNIT
);
5603 else if (DEFAULT_ABI
== ABI_V4
)
5605 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5606 && (mode
== SFmode
|| mode
== DFmode
5607 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
5608 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)))
5610 /* _Decimal128 must use an even/odd register pair. This assumes
5611 that the register number is odd when fregno is odd. */
5612 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5615 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
5616 <= FP_ARG_V4_MAX_REG
)
5617 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5620 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
5621 if (mode
== DFmode
|| mode
== TFmode
5622 || mode
== DDmode
|| mode
== TDmode
)
5623 cum
->words
+= cum
->words
& 1;
5624 cum
->words
+= rs6000_arg_size (mode
, type
);
5629 int n_words
= rs6000_arg_size (mode
, type
);
5630 int gregno
= cum
->sysv_gregno
;
5632 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5633 (r7,r8) or (r9,r10). As does any other 2 word item such
5634 as complex int due to a historical mistake. */
5636 gregno
+= (1 - gregno
) & 1;
5638 /* Multi-reg args are not split between registers and stack. */
5639 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5641 /* Long long and SPE vectors are aligned on the stack.
5642 So are other 2 word items such as complex int due to
5643 a historical mistake. */
5645 cum
->words
+= cum
->words
& 1;
5646 cum
->words
+= n_words
;
5649 /* Note: continuing to accumulate gregno past when we've started
5650 spilling to the stack indicates the fact that we've started
5651 spilling to the stack to expand_builtin_saveregs. */
5652 cum
->sysv_gregno
= gregno
+ n_words
;
5655 if (TARGET_DEBUG_ARG
)
5657 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5658 cum
->words
, cum
->fregno
);
5659 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5660 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5661 fprintf (stderr
, "mode = %4s, named = %d\n",
5662 GET_MODE_NAME (mode
), named
);
5667 int n_words
= rs6000_arg_size (mode
, type
);
5668 int start_words
= cum
->words
;
5669 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
5671 cum
->words
= align_words
+ n_words
;
5673 if (SCALAR_FLOAT_MODE_P (mode
)
5674 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5676 /* _Decimal128 must be passed in an even/odd float register pair.
5677 This assumes that the register number is odd when fregno is
5679 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5681 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5684 if (TARGET_DEBUG_ARG
)
5686 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5687 cum
->words
, cum
->fregno
);
5688 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5689 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5690 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5691 named
, align_words
- start_words
, depth
);
5697 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5704 r1
= gen_rtx_REG (DImode
, gregno
);
5705 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5706 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5710 r1
= gen_rtx_REG (DImode
, gregno
);
5711 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5712 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5713 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5714 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5717 r1
= gen_rtx_REG (DImode
, gregno
);
5718 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5719 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5720 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5721 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
5722 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
5723 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
5724 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
5725 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
5732 /* Determine where to put a SIMD argument on the SPE. */
5734 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5737 int gregno
= cum
->sysv_gregno
;
5739 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5740 are passed and returned in a pair of GPRs for ABI compatibility. */
5741 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5742 || mode
== DCmode
|| mode
== TCmode
))
5744 int n_words
= rs6000_arg_size (mode
, type
);
5746 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5748 gregno
+= (1 - gregno
) & 1;
5750 /* Multi-reg args are not split between registers and stack. */
5751 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5754 return spe_build_register_parallel (mode
, gregno
);
5758 int n_words
= rs6000_arg_size (mode
, type
);
5760 /* SPE vectors are put in odd registers. */
5761 if (n_words
== 2 && (gregno
& 1) == 0)
5764 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5767 enum machine_mode m
= SImode
;
5769 r1
= gen_rtx_REG (m
, gregno
);
5770 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5771 r2
= gen_rtx_REG (m
, gregno
+ 1);
5772 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5773 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5780 if (gregno
<= GP_ARG_MAX_REG
)
5781 return gen_rtx_REG (mode
, gregno
);
5787 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5788 structure between cum->intoffset and bitpos to integer registers. */
5791 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
5792 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
5794 enum machine_mode mode
;
5796 unsigned int startbit
, endbit
;
5797 int this_regno
, intregs
, intoffset
;
5800 if (cum
->intoffset
== -1)
5803 intoffset
= cum
->intoffset
;
5804 cum
->intoffset
= -1;
5806 /* If this is the trailing part of a word, try to only load that
5807 much into the register. Otherwise load the whole register. Note
5808 that in the latter case we may pick up unwanted bits. It's not a
5809 problem at the moment but may wish to revisit. */
5811 if (intoffset
% BITS_PER_WORD
!= 0)
5813 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5815 if (mode
== BLKmode
)
5817 /* We couldn't find an appropriate mode, which happens,
5818 e.g., in packed structs when there are 3 bytes to load.
5819 Back intoffset back to the beginning of the word in this
5821 intoffset
= intoffset
& -BITS_PER_WORD
;
5828 startbit
= intoffset
& -BITS_PER_WORD
;
5829 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5830 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5831 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
5833 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
5836 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
5840 intoffset
/= BITS_PER_UNIT
;
5843 regno
= GP_ARG_MIN_REG
+ this_regno
;
5844 reg
= gen_rtx_REG (mode
, regno
);
5846 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5849 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5853 while (intregs
> 0);
5856 /* Recursive workhorse for the following. */
5859 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
5860 HOST_WIDE_INT startbitpos
, rtx rvec
[],
5865 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5866 if (TREE_CODE (f
) == FIELD_DECL
)
5868 HOST_WIDE_INT bitpos
= startbitpos
;
5869 tree ftype
= TREE_TYPE (f
);
5870 enum machine_mode mode
;
5871 if (ftype
== error_mark_node
)
5873 mode
= TYPE_MODE (ftype
);
5875 if (DECL_SIZE (f
) != 0
5876 && host_integerp (bit_position (f
), 1))
5877 bitpos
+= int_bit_position (f
);
5879 /* ??? FIXME: else assume zero offset. */
5881 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5882 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
5883 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5888 case SCmode
: mode
= SFmode
; break;
5889 case DCmode
: mode
= DFmode
; break;
5890 case TCmode
: mode
= TFmode
; break;
5894 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5896 = gen_rtx_EXPR_LIST (VOIDmode
,
5897 gen_rtx_REG (mode
, cum
->fregno
++),
5898 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5899 if (mode
== TFmode
|| mode
== TDmode
)
5902 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
5904 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5906 = gen_rtx_EXPR_LIST (VOIDmode
,
5907 gen_rtx_REG (mode
, cum
->vregno
++),
5908 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5910 else if (cum
->intoffset
== -1)
5911 cum
->intoffset
= bitpos
;
5915 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5916 the register(s) to be used for each field and subfield of a struct
5917 being passed by value, along with the offset of where the
5918 register's value may be found in the block. FP fields go in FP
5919 register, vector fields go in vector registers, and everything
5920 else goes in int registers, packed as in memory.
5922 This code is also used for function return values. RETVAL indicates
5923 whether this is the case.
5925 Much of this is taken from the SPARC V9 port, which has a similar
5926 calling convention. */
5929 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
5930 int named
, bool retval
)
5932 rtx rvec
[FIRST_PSEUDO_REGISTER
];
5933 int k
= 1, kbase
= 1;
5934 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5935 /* This is a copy; modifications are not visible to our caller. */
5936 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
5937 CUMULATIVE_ARGS
*cum
= ©_cum
;
5939 /* Pad to 16 byte boundary if needed. */
5940 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5941 && (cum
->words
% 2) != 0)
5948 /* Put entries into rvec[] for individual FP and vector fields, and
5949 for the chunks of memory that go in int regs. Note we start at
5950 element 1; 0 is reserved for an indication of using memory, and
5951 may or may not be filled in below. */
5952 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
5953 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
5955 /* If any part of the struct went on the stack put all of it there.
5956 This hack is because the generic code for
5957 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5958 parts of the struct are not at the beginning. */
5962 return NULL_RTX
; /* doesn't go in registers at all */
5964 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5966 if (k
> 1 || cum
->use_stack
)
5967 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
5972 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5975 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
5979 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5981 if (align_words
>= GP_ARG_NUM_REG
)
5984 n_units
= rs6000_arg_size (mode
, type
);
5986 /* Optimize the simple case where the arg fits in one gpr, except in
5987 the case of BLKmode due to assign_parms assuming that registers are
5988 BITS_PER_WORD wide. */
5990 || (n_units
== 1 && mode
!= BLKmode
))
5991 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5994 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
5995 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5996 using a magic NULL_RTX component.
5997 This is not strictly correct. Only some of the arg belongs in
5998 memory, not all of it. However, the normal scheme using
5999 function_arg_partial_nregs can result in unusual subregs, eg.
6000 (subreg:SI (reg:DF) 4), which are not handled well. The code to
6001 store the whole arg to memory is often more efficient than code
6002 to store pieces, and we know that space is available in the right
6003 place for the whole arg. */
6004 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6009 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
6010 rtx off
= GEN_INT (i
++ * 4);
6011 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6013 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
6015 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6018 /* Determine where to put an argument to a function.
6019 Value is zero to push the argument on the stack,
6020 or a hard register in which to store the argument.
6022 MODE is the argument's machine mode.
6023 TYPE is the data type of the argument (as a tree).
6024 This is null for libcalls where that information may
6026 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6027 the preceding args and about the function being called. It is
6028 not modified in this routine.
6029 NAMED is nonzero if this argument is a named parameter
6030 (otherwise it is an extra parameter matching an ellipsis).
6032 On RS/6000 the first eight words of non-FP are normally in registers
6033 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
6034 Under V.4, the first 8 FP args are in registers.
6036 If this is floating-point and no prototype is specified, we use
6037 both an FP and integer register (or possibly FP reg and stack). Library
6038 functions (when CALL_LIBCALL is set) always have the proper types for args,
6039 so we can pass the FP value just in one register. emit_library_function
6040 doesn't support PARALLEL anyway.
6042 Note that for args passed by reference, function_arg will be called
6043 with MODE and TYPE set to that of the pointer to the arg, not the arg
6047 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6048 tree type
, int named
)
6050 enum rs6000_abi abi
= DEFAULT_ABI
;
6052 /* Return a marker to indicate whether CR1 needs to set or clear the
6053 bit that V.4 uses to say fp args were passed in registers.
6054 Assume that we don't need the marker for software floating point,
6055 or compiler generated library calls. */
6056 if (mode
== VOIDmode
)
6059 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
6061 || (cum
->nargs_prototype
< 0
6062 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
6064 /* For the SPE, we need to crxor CR6 always. */
6066 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
6067 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
6068 return GEN_INT (cum
->call_cookie
6069 | ((cum
->fregno
== FP_ARG_MIN_REG
)
6070 ? CALL_V4_SET_FP_ARGS
6071 : CALL_V4_CLEAR_FP_ARGS
));
6074 return GEN_INT (cum
->call_cookie
);
6077 if (rs6000_darwin64_abi
&& mode
== BLKmode
6078 && TREE_CODE (type
) == RECORD_TYPE
)
6080 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
6081 if (rslt
!= NULL_RTX
)
6083 /* Else fall through to usual handling. */
6086 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
6087 if (TARGET_64BIT
&& ! cum
->prototype
)
6089 /* Vector parameters get passed in vector register
6090 and also in GPRs or memory, in absence of prototype. */
6093 align_words
= (cum
->words
+ 1) & ~1;
6095 if (align_words
>= GP_ARG_NUM_REG
)
6101 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6103 return gen_rtx_PARALLEL (mode
,
6105 gen_rtx_EXPR_LIST (VOIDmode
,
6107 gen_rtx_EXPR_LIST (VOIDmode
,
6108 gen_rtx_REG (mode
, cum
->vregno
),
6112 return gen_rtx_REG (mode
, cum
->vregno
);
6113 else if (TARGET_ALTIVEC_ABI
6114 && (ALTIVEC_VECTOR_MODE (mode
)
6115 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
6116 && int_size_in_bytes (type
) == 16)))
6118 if (named
|| abi
== ABI_V4
)
6122 /* Vector parameters to varargs functions under AIX or Darwin
6123 get passed in memory and possibly also in GPRs. */
6124 int align
, align_words
, n_words
;
6125 enum machine_mode part_mode
;
6127 /* Vector parameters must be 16-byte aligned. This places them at
6128 2 mod 4 in terms of words in 32-bit mode, since the parameter
6129 save area starts at offset 24 from the stack. In 64-bit mode,
6130 they just have to start on an even word, since the parameter
6131 save area is 16-byte aligned. */
6133 align
= (2 - cum
->words
) & 3;
6135 align
= cum
->words
& 1;
6136 align_words
= cum
->words
+ align
;
6138 /* Out of registers? Memory, then. */
6139 if (align_words
>= GP_ARG_NUM_REG
)
6142 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6143 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6145 /* The vector value goes in GPRs. Only the part of the
6146 value in GPRs is reported here. */
6148 n_words
= rs6000_arg_size (mode
, type
);
6149 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6150 /* Fortunately, there are only two possibilities, the value
6151 is either wholly in GPRs or half in GPRs and half not. */
6154 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
6157 else if (TARGET_SPE_ABI
&& TARGET_SPE
6158 && (SPE_VECTOR_MODE (mode
)
6159 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
6162 || mode
== TCmode
))))
6163 return rs6000_spe_function_arg (cum
, mode
, type
);
6165 else if (abi
== ABI_V4
)
6167 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6168 && (mode
== SFmode
|| mode
== DFmode
6169 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
6170 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
6172 /* _Decimal128 must use an even/odd register pair. This assumes
6173 that the register number is odd when fregno is odd. */
6174 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6177 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
6178 <= FP_ARG_V4_MAX_REG
)
6179 return gen_rtx_REG (mode
, cum
->fregno
);
6185 int n_words
= rs6000_arg_size (mode
, type
);
6186 int gregno
= cum
->sysv_gregno
;
6188 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6189 (r7,r8) or (r9,r10). As does any other 2 word item such
6190 as complex int due to a historical mistake. */
6192 gregno
+= (1 - gregno
) & 1;
6194 /* Multi-reg args are not split between registers and stack. */
6195 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
6198 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6199 return rs6000_mixed_function_arg (mode
, type
,
6200 gregno
- GP_ARG_MIN_REG
);
6201 return gen_rtx_REG (mode
, gregno
);
6206 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6208 /* _Decimal128 must be passed in an even/odd float register pair.
6209 This assumes that the register number is odd when fregno is odd. */
6210 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6213 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6215 rtx rvec
[GP_ARG_NUM_REG
+ 1];
6219 enum machine_mode fmode
= mode
;
6220 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
6222 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
6224 /* Currently, we only ever need one reg here because complex
6225 doubles are split. */
6226 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
6227 && (fmode
== TFmode
|| fmode
== TDmode
));
6229 /* Long double or _Decimal128 split over regs and memory. */
6230 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
6233 /* Do we also need to pass this arg in the parameter save
6236 && (cum
->nargs_prototype
<= 0
6237 || (DEFAULT_ABI
== ABI_AIX
6239 && align_words
>= GP_ARG_NUM_REG
)));
6241 if (!needs_psave
&& mode
== fmode
)
6242 return gen_rtx_REG (fmode
, cum
->fregno
);
6247 /* Describe the part that goes in gprs or the stack.
6248 This piece must come first, before the fprs. */
6249 if (align_words
< GP_ARG_NUM_REG
)
6251 unsigned long n_words
= rs6000_arg_size (mode
, type
);
6253 if (align_words
+ n_words
> GP_ARG_NUM_REG
6254 || (TARGET_32BIT
&& TARGET_POWERPC64
))
6256 /* If this is partially on the stack, then we only
6257 include the portion actually in registers here. */
6258 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
6261 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6262 /* Not all of the arg fits in gprs. Say that it
6263 goes in memory too, using a magic NULL_RTX
6264 component. Also see comment in
6265 rs6000_mixed_function_arg for why the normal
6266 function_arg_partial_nregs scheme doesn't work
6268 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
6272 r
= gen_rtx_REG (rmode
,
6273 GP_ARG_MIN_REG
+ align_words
);
6274 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
6275 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6277 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
6281 /* The whole arg fits in gprs. */
6282 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6283 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6287 /* It's entirely in memory. */
6288 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6291 /* Describe where this piece goes in the fprs. */
6292 r
= gen_rtx_REG (fmode
, cum
->fregno
);
6293 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6295 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6297 else if (align_words
< GP_ARG_NUM_REG
)
6299 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6300 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6302 if (mode
== BLKmode
)
6305 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6312 /* For an arg passed partly in registers and partly in memory, this is
6313 the number of bytes passed in registers. For args passed entirely in
6314 registers or entirely in memory, zero. When an arg is described by a
6315 PARALLEL, perhaps using more than one register type, this function
6316 returns the number of bytes used by the first element of the PARALLEL. */
6319 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6320 tree type
, bool named
)
6325 if (DEFAULT_ABI
== ABI_V4
)
6328 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
6329 && cum
->nargs_prototype
>= 0)
6332 /* In this complicated case we just disable the partial_nregs code. */
6333 if (rs6000_darwin64_abi
&& mode
== BLKmode
6334 && TREE_CODE (type
) == RECORD_TYPE
6335 && int_size_in_bytes (type
) > 0)
6338 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6340 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6342 /* If we are passing this arg in the fixed parameter save area
6343 (gprs or memory) as well as fprs, then this function should
6344 return the number of partial bytes passed in the parameter
6345 save area rather than partial bytes passed in fprs. */
6347 && (cum
->nargs_prototype
<= 0
6348 || (DEFAULT_ABI
== ABI_AIX
6350 && align_words
>= GP_ARG_NUM_REG
)))
6352 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
6353 > FP_ARG_MAX_REG
+ 1)
6354 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
6355 else if (cum
->nargs_prototype
>= 0)
6359 if (align_words
< GP_ARG_NUM_REG
6360 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
6361 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
6363 if (ret
!= 0 && TARGET_DEBUG_ARG
)
6364 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
6369 /* A C expression that indicates when an argument must be passed by
6370 reference. If nonzero for an argument, a copy of that argument is
6371 made in memory and a pointer to the argument is passed instead of
6372 the argument itself. The pointer is passed in whatever way is
6373 appropriate for passing a pointer to that type.
6375 Under V.4, aggregates and long double are passed by reference.
6377 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6378 reference unless the AltiVec vector extension ABI is in force.
6380 As an extension to all ABIs, variable sized types are passed by
6384 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
6385 enum machine_mode mode
, const_tree type
,
6386 bool named ATTRIBUTE_UNUSED
)
6388 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
6390 if (TARGET_DEBUG_ARG
)
6391 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
6398 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
6400 if (TARGET_DEBUG_ARG
)
6401 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
6405 if (int_size_in_bytes (type
) < 0)
6407 if (TARGET_DEBUG_ARG
)
6408 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
6412 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6413 modes only exist for GCC vector types if -maltivec. */
6414 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
6416 if (TARGET_DEBUG_ARG
)
6417 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
6421 /* Pass synthetic vectors in memory. */
6422 if (TREE_CODE (type
) == VECTOR_TYPE
6423 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
6425 static bool warned_for_pass_big_vectors
= false;
6426 if (TARGET_DEBUG_ARG
)
6427 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
6428 if (!warned_for_pass_big_vectors
)
6430 warning (0, "GCC vector passed by reference: "
6431 "non-standard ABI extension with no compatibility guarantee");
6432 warned_for_pass_big_vectors
= true;
6441 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
6444 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
6449 for (i
= 0; i
< nregs
; i
++)
6451 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
6452 if (reload_completed
)
6454 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
6457 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
6458 i
* GET_MODE_SIZE (reg_mode
));
6461 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
6465 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
6469 /* Perform any needed actions needed for a function that is receiving a
6470 variable number of arguments.
6474 MODE and TYPE are the mode and type of the current parameter.
6476 PRETEND_SIZE is a variable that should be set to the amount of stack
6477 that must be pushed by the prolog to pretend that our caller pushed
6480 Normally, this macro will push all remaining incoming registers on the
6481 stack and set PRETEND_SIZE to the length of the registers pushed. */
6484 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6485 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6488 CUMULATIVE_ARGS next_cum
;
6489 int reg_size
= TARGET_32BIT
? 4 : 8;
6490 rtx save_area
= NULL_RTX
, mem
;
6491 int first_reg_offset
;
6494 /* Skip the last named argument. */
6496 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
6498 if (DEFAULT_ABI
== ABI_V4
)
6500 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
6504 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
6505 HOST_WIDE_INT offset
= 0;
6507 /* Try to optimize the size of the varargs save area.
6508 The ABI requires that ap.reg_save_area is doubleword
6509 aligned, but we don't need to allocate space for all
6510 the bytes, only those to which we actually will save
6512 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
6513 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
6514 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6515 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6516 && cfun
->va_list_fpr_size
)
6519 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
6520 * UNITS_PER_FP_WORD
;
6521 if (cfun
->va_list_fpr_size
6522 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6523 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
6525 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6526 * UNITS_PER_FP_WORD
;
6530 offset
= -((first_reg_offset
* reg_size
) & ~7);
6531 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
6533 gpr_reg_num
= cfun
->va_list_gpr_size
;
6534 if (reg_size
== 4 && (first_reg_offset
& 1))
6537 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
6540 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
6542 - (int) (GP_ARG_NUM_REG
* reg_size
);
6544 if (gpr_size
+ fpr_size
)
6547 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
6548 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
6549 reg_save_area
= XEXP (reg_save_area
, 0);
6550 if (GET_CODE (reg_save_area
) == PLUS
)
6552 gcc_assert (XEXP (reg_save_area
, 0)
6553 == virtual_stack_vars_rtx
);
6554 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
6555 offset
+= INTVAL (XEXP (reg_save_area
, 1));
6558 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
6561 cfun
->machine
->varargs_save_offset
= offset
;
6562 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
6567 first_reg_offset
= next_cum
.words
;
6568 save_area
= virtual_incoming_args_rtx
;
6570 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
6571 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
6574 set
= get_varargs_alias_set ();
6575 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
6576 && cfun
->va_list_gpr_size
)
6578 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
6580 if (va_list_gpr_counter_field
)
6582 /* V4 va_list_gpr_size counts number of registers needed. */
6583 if (nregs
> cfun
->va_list_gpr_size
)
6584 nregs
= cfun
->va_list_gpr_size
;
6588 /* char * va_list instead counts number of bytes needed. */
6589 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
6590 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
6593 mem
= gen_rtx_MEM (BLKmode
,
6594 plus_constant (save_area
,
6595 first_reg_offset
* reg_size
));
6596 MEM_NOTRAP_P (mem
) = 1;
6597 set_mem_alias_set (mem
, set
);
6598 set_mem_align (mem
, BITS_PER_WORD
);
6600 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
6604 /* Save FP registers if needed. */
6605 if (DEFAULT_ABI
== ABI_V4
6606 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6608 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6609 && cfun
->va_list_fpr_size
)
6611 int fregno
= next_cum
.fregno
, nregs
;
6612 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
6613 rtx lab
= gen_label_rtx ();
6614 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
6615 * UNITS_PER_FP_WORD
);
6618 (gen_rtx_SET (VOIDmode
,
6620 gen_rtx_IF_THEN_ELSE (VOIDmode
,
6621 gen_rtx_NE (VOIDmode
, cr1
,
6623 gen_rtx_LABEL_REF (VOIDmode
, lab
),
6627 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
6628 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
6630 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
6631 MEM_NOTRAP_P (mem
) = 1;
6632 set_mem_alias_set (mem
, set
);
6633 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
6634 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
6641 /* Create the va_list data type. */
6644 rs6000_build_builtin_va_list (void)
6646 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
6648 /* For AIX, prefer 'char *' because that's what the system
6649 header files like. */
6650 if (DEFAULT_ABI
!= ABI_V4
)
6651 return build_pointer_type (char_type_node
);
6653 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6654 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6656 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
6657 unsigned_char_type_node
);
6658 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
6659 unsigned_char_type_node
);
6660 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6662 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
6663 short_unsigned_type_node
);
6664 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
6666 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
6669 va_list_gpr_counter_field
= f_gpr
;
6670 va_list_fpr_counter_field
= f_fpr
;
6672 DECL_FIELD_CONTEXT (f_gpr
) = record
;
6673 DECL_FIELD_CONTEXT (f_fpr
) = record
;
6674 DECL_FIELD_CONTEXT (f_res
) = record
;
6675 DECL_FIELD_CONTEXT (f_ovf
) = record
;
6676 DECL_FIELD_CONTEXT (f_sav
) = record
;
6678 TREE_CHAIN (record
) = type_decl
;
6679 TYPE_NAME (record
) = type_decl
;
6680 TYPE_FIELDS (record
) = f_gpr
;
6681 TREE_CHAIN (f_gpr
) = f_fpr
;
6682 TREE_CHAIN (f_fpr
) = f_res
;
6683 TREE_CHAIN (f_res
) = f_ovf
;
6684 TREE_CHAIN (f_ovf
) = f_sav
;
6686 layout_type (record
);
6688 /* The correct type is an array type of one element. */
6689 return build_array_type (record
, build_index_type (size_zero_node
));
6692 /* Implement va_start. */
6695 rs6000_va_start (tree valist
, rtx nextarg
)
6697 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
6698 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6699 tree gpr
, fpr
, ovf
, sav
, t
;
6701 /* Only SVR4 needs something special. */
6702 if (DEFAULT_ABI
!= ABI_V4
)
6704 std_expand_builtin_va_start (valist
, nextarg
);
6708 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6709 f_fpr
= TREE_CHAIN (f_gpr
);
6710 f_res
= TREE_CHAIN (f_fpr
);
6711 f_ovf
= TREE_CHAIN (f_res
);
6712 f_sav
= TREE_CHAIN (f_ovf
);
6714 valist
= build_va_arg_indirect_ref (valist
);
6715 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6716 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
6718 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
6720 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
6723 /* Count number of gp and fp argument registers used. */
6724 words
= crtl
->args
.info
.words
;
6725 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
6727 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
6730 if (TARGET_DEBUG_ARG
)
6731 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6732 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6733 words
, n_gpr
, n_fpr
);
6735 if (cfun
->va_list_gpr_size
)
6737 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
6738 build_int_cst (NULL_TREE
, n_gpr
));
6739 TREE_SIDE_EFFECTS (t
) = 1;
6740 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6743 if (cfun
->va_list_fpr_size
)
6745 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
6746 build_int_cst (NULL_TREE
, n_fpr
));
6747 TREE_SIDE_EFFECTS (t
) = 1;
6748 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6751 /* Find the overflow area. */
6752 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6754 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6755 size_int (words
* UNITS_PER_WORD
));
6756 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
6757 TREE_SIDE_EFFECTS (t
) = 1;
6758 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6760 /* If there were no va_arg invocations, don't set up the register
6762 if (!cfun
->va_list_gpr_size
6763 && !cfun
->va_list_fpr_size
6764 && n_gpr
< GP_ARG_NUM_REG
6765 && n_fpr
< FP_ARG_V4_MAX_REG
)
6768 /* Find the register save area. */
6769 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6770 if (cfun
->machine
->varargs_save_offset
)
6771 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
6772 size_int (cfun
->machine
->varargs_save_offset
));
6773 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
6774 TREE_SIDE_EFFECTS (t
) = 1;
6775 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6778 /* Implement va_arg. */
6781 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6784 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6785 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6786 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6787 tree lab_false
, lab_over
, addr
;
6789 tree ptrtype
= build_pointer_type (type
);
6793 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6795 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6796 return build_va_arg_indirect_ref (t
);
6799 if (DEFAULT_ABI
!= ABI_V4
)
6801 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6803 tree elem_type
= TREE_TYPE (type
);
6804 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6805 int elem_size
= GET_MODE_SIZE (elem_mode
);
6807 if (elem_size
< UNITS_PER_WORD
)
6809 tree real_part
, imag_part
;
6810 gimple_seq post
= NULL
;
6812 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6814 /* Copy the value into a temporary, lest the formal temporary
6815 be reused out from under us. */
6816 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
6817 gimple_seq_add_seq (pre_p
, post
);
6819 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6822 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
6826 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6829 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6830 f_fpr
= TREE_CHAIN (f_gpr
);
6831 f_res
= TREE_CHAIN (f_fpr
);
6832 f_ovf
= TREE_CHAIN (f_res
);
6833 f_sav
= TREE_CHAIN (f_ovf
);
6835 valist
= build_va_arg_indirect_ref (valist
);
6836 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6837 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
6839 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
6841 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
6844 size
= int_size_in_bytes (type
);
6845 rsize
= (size
+ 3) / 4;
6848 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6849 && (TYPE_MODE (type
) == SFmode
6850 || TYPE_MODE (type
) == DFmode
6851 || TYPE_MODE (type
) == TFmode
6852 || TYPE_MODE (type
) == SDmode
6853 || TYPE_MODE (type
) == DDmode
6854 || TYPE_MODE (type
) == TDmode
))
6856 /* FP args go in FP registers, if present. */
6858 n_reg
= (size
+ 7) / 8;
6861 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
6866 /* Otherwise into GP registers. */
6875 /* Pull the value out of the saved registers.... */
6878 addr
= create_tmp_var (ptr_type_node
, "addr");
6879 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
6881 /* AltiVec vectors never go in registers when -mabi=altivec. */
6882 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
6886 lab_false
= create_artificial_label ();
6887 lab_over
= create_artificial_label ();
6889 /* Long long and SPE vectors are aligned in the registers.
6890 As are any other 2 gpr item such as complex int due to a
6891 historical mistake. */
6893 if (n_reg
== 2 && reg
== gpr
)
6896 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
6897 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
6898 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
6899 unshare_expr (reg
), u
);
6901 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6902 reg number is 0 for f1, so we want to make it odd. */
6903 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
6906 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
6907 build_int_cst (TREE_TYPE (reg
), 1));
6908 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
6911 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
6912 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
6913 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
6914 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
6915 gimplify_and_add (t
, pre_p
);
6919 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
6921 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
6922 build_int_cst (TREE_TYPE (reg
), n_reg
));
6923 u
= fold_convert (sizetype
, u
);
6924 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
6925 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, u
);
6927 /* _Decimal32 varargs are located in the second word of the 64-bit
6928 FP register for 32-bit binaries. */
6929 if (!TARGET_POWERPC64
6930 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6931 && TYPE_MODE (type
) == SDmode
)
6932 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6934 gimplify_assign (addr
, t
, pre_p
);
6936 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
6938 stmt
= gimple_build_label (lab_false
);
6939 gimple_seq_add_stmt (pre_p
, stmt
);
6941 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
6943 /* Ensure that we don't find any more args in regs.
6944 Alignment has taken care of for special cases. */
6945 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
6949 /* ... otherwise out of the overflow area. */
6951 /* Care for on-stack alignment if needed. */
6955 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
6956 t
= fold_convert (sizetype
, t
);
6957 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
6959 t
= fold_convert (TREE_TYPE (ovf
), t
);
6961 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
6963 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
6965 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6966 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
6970 stmt
= gimple_build_label (lab_over
);
6971 gimple_seq_add_stmt (pre_p
, stmt
);
6974 if (STRICT_ALIGNMENT
6975 && (TYPE_ALIGN (type
)
6976 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
6978 /* The value (of type complex double, for example) may not be
6979 aligned in memory in the saved registers, so copy via a
6980 temporary. (This is the same code as used for SPARC.) */
6981 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6982 tree dest_addr
= build_fold_addr_expr (tmp
);
6984 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6985 3, dest_addr
, addr
, size_int (rsize
* 4));
6987 gimplify_and_add (copy
, pre_p
);
6991 addr
= fold_convert (ptrtype
, addr
);
6992 return build_va_arg_indirect_ref (addr
);
6998 def_builtin (int mask
, const char *name
, tree type
, int code
)
7000 if ((mask
& target_flags
) || TARGET_PAIRED_FLOAT
)
7002 if (rs6000_builtin_decls
[code
])
7005 rs6000_builtin_decls
[code
] =
7006 add_builtin_function (name
, type
, code
, BUILT_IN_MD
,
7011 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
7013 static const struct builtin_description bdesc_3arg
[] =
7015 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
7016 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
7017 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
7018 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
7019 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
7020 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
7021 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
7022 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
7023 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
7024 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
7025 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
7026 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
7027 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
7028 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
7029 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
7030 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
7031 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
7032 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
7033 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
7034 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
7035 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
7036 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
7037 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
7039 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD
},
7040 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS
},
7041 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD
},
7042 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS
},
7043 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM
},
7044 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM
},
7045 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM
},
7046 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM
},
7047 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM
},
7048 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS
},
7049 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS
},
7050 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS
},
7051 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB
},
7052 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM
},
7053 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL
},
7055 { 0, CODE_FOR_paired_msub
, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB
},
7056 { 0, CODE_FOR_paired_madd
, "__builtin_paired_madd", PAIRED_BUILTIN_MADD
},
7057 { 0, CODE_FOR_paired_madds0
, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0
},
7058 { 0, CODE_FOR_paired_madds1
, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1
},
7059 { 0, CODE_FOR_paired_nmsub
, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB
},
7060 { 0, CODE_FOR_paired_nmadd
, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD
},
7061 { 0, CODE_FOR_paired_sum0
, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0
},
7062 { 0, CODE_FOR_paired_sum1
, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1
},
7063 { 0, CODE_FOR_selv2sf4
, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4
},
7066 /* DST operations: void foo (void *, const int, const char). */
7068 static const struct builtin_description bdesc_dst
[] =
7070 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
7071 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
7072 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
7073 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
},
7075 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST
},
7076 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT
},
7077 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST
},
7078 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT
}
7081 /* Simple binary operations: VECc = foo (VECa, VECb). */
7083 static struct builtin_description bdesc_2arg
[] =
7085 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
7086 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
7087 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
7088 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
7089 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
7090 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
7091 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
7092 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
7093 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
7094 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
7095 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
7096 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
7097 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
7098 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
7099 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
7100 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
7101 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
7102 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
7103 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
7104 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
7105 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
7106 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
7107 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
7108 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
7109 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
7110 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
7111 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
7112 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
7113 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
7114 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
7115 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
7116 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
7117 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
7118 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
7119 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
7120 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
7121 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
7122 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
7123 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
7124 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
7125 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
7126 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
7127 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
7128 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
7129 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
7130 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
7131 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
7132 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
7133 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
7134 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
7135 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
7136 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
7137 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
7138 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
7139 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
7140 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
7141 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
7142 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
7143 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
7144 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
7145 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
7146 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
7147 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
7148 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
7149 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
7150 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
7151 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
7152 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
7153 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
7154 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
7155 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
7156 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
7157 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
7158 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
7159 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
7160 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
7161 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
7162 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
7163 { MASK_ALTIVEC
, CODE_FOR_vashlv16qi3
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
7164 { MASK_ALTIVEC
, CODE_FOR_vashlv8hi3
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
7165 { MASK_ALTIVEC
, CODE_FOR_vashlv4si3
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
7166 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
7167 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
7168 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
7169 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
7170 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
7171 { MASK_ALTIVEC
, CODE_FOR_vlshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
7172 { MASK_ALTIVEC
, CODE_FOR_vlshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
7173 { MASK_ALTIVEC
, CODE_FOR_vlshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
7174 { MASK_ALTIVEC
, CODE_FOR_vashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
7175 { MASK_ALTIVEC
, CODE_FOR_vashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
7176 { MASK_ALTIVEC
, CODE_FOR_vashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
7177 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
7178 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
7179 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
7180 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
7181 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
7182 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
7183 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
7184 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
7185 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
7186 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
7187 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
7188 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
7189 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
7190 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
7191 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
7192 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
7193 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
7194 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
7195 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
7197 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD
},
7198 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP
},
7199 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM
},
7200 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM
},
7201 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM
},
7202 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC
},
7203 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS
},
7204 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS
},
7205 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS
},
7206 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS
},
7207 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS
},
7208 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS
},
7209 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS
},
7210 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND
},
7211 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC
},
7212 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG
},
7213 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW
},
7214 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW
},
7215 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH
},
7216 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH
},
7217 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB
},
7218 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB
},
7219 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB
},
7220 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ
},
7221 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP
},
7222 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW
},
7223 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH
},
7224 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB
},
7225 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE
},
7226 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT
},
7227 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP
},
7228 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW
},
7229 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW
},
7230 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH
},
7231 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH
},
7232 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB
},
7233 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB
},
7234 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE
},
7235 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT
},
7236 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX
},
7237 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP
},
7238 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW
},
7239 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW
},
7240 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH
},
7241 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH
},
7242 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB
},
7243 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB
},
7244 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH
},
7245 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW
},
7246 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH
},
7247 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB
},
7248 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL
},
7249 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW
},
7250 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH
},
7251 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB
},
7252 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN
},
7253 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP
},
7254 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW
},
7255 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW
},
7256 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH
},
7257 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH
},
7258 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB
},
7259 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB
},
7260 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE
},
7261 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB
},
7262 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB
},
7263 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH
},
7264 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH
},
7265 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO
},
7266 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH
},
7267 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH
},
7268 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB
},
7269 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB
},
7270 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR
},
7271 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
7272 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK
},
7273 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM
},
7274 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM
},
7275 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX
},
7276 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS
},
7277 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS
},
7278 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS
},
7279 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS
},
7280 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS
},
7281 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU
},
7282 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS
},
7283 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS
},
7284 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL
},
7285 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW
},
7286 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH
},
7287 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB
},
7288 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL
},
7289 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW
},
7290 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH
},
7291 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB
},
7292 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL
},
7293 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO
},
7294 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR
},
7295 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW
},
7296 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH
},
7297 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB
},
7298 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA
},
7299 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW
},
7300 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH
},
7301 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB
},
7302 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL
},
7303 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO
},
7304 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB
},
7305 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP
},
7306 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM
},
7307 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM
},
7308 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM
},
7309 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC
},
7310 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS
},
7311 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS
},
7312 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS
},
7313 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS
},
7314 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS
},
7315 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS
},
7316 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS
},
7317 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S
},
7318 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS
},
7319 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS
},
7320 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS
},
7321 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S
},
7322 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS
},
7323 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR
},
7325 { 0, CODE_FOR_divv2sf3
, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3
},
7326 { 0, CODE_FOR_addv2sf3
, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3
},
7327 { 0, CODE_FOR_subv2sf3
, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3
},
7328 { 0, CODE_FOR_mulv2sf3
, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3
},
7329 { 0, CODE_FOR_paired_muls0
, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0
},
7330 { 0, CODE_FOR_paired_muls1
, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1
},
7331 { 0, CODE_FOR_paired_merge00
, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00
},
7332 { 0, CODE_FOR_paired_merge01
, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01
},
7333 { 0, CODE_FOR_paired_merge10
, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10
},
7334 { 0, CODE_FOR_paired_merge11
, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11
},
7336 /* Place holder, leave as first spe builtin. */
7337 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
7338 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
7339 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
7340 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
7341 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
7342 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
7343 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
7344 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
7345 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
7346 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
7347 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
7348 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
7349 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
7350 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
7351 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
7352 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
7353 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
7354 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
7355 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
7356 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
7357 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
7358 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
7359 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
7360 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
7361 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
7362 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
7363 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
7364 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
7365 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
7366 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
7367 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
7368 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
7369 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
7370 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
7371 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
7372 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
7373 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
7374 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
7375 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
7376 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
7377 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
7378 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
7379 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
7380 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
7381 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
7382 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
7383 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
7384 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
7385 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
7386 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
7387 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
7388 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
7389 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
7390 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
7391 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
7392 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
7393 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
7394 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
7395 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
7396 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
7397 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
7398 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
7399 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
7400 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
7401 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
7402 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
7403 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
7404 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
7405 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
7406 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
7407 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
7408 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
7409 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
7410 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
7411 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
7412 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
7413 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
7414 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
7415 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
7416 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
7417 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
7418 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
7419 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
7420 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
7421 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
7422 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
7423 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
7424 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
7425 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
7426 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
7427 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
7428 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
7429 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
7430 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
7431 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
7432 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
7433 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
7434 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
7435 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
7436 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
7437 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
7438 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
7439 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
7440 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
7441 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
7442 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
7443 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
7444 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
7445 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
7447 /* SPE binary operations expecting a 5-bit unsigned literal. */
7448 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
7450 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
7451 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
7452 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
7453 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
7454 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
7455 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
7456 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
7457 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
7458 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
7459 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
7460 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
7461 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
7462 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
7463 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
7464 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
7465 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
7466 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
7467 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
7468 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
7469 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
7470 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
7471 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
7472 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
7473 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
7474 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
7475 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
7477 /* Place-holder. Leave as last binary SPE builtin. */
7478 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
}
7481 /* AltiVec predicates. */
7483 struct builtin_description_predicates
7485 const unsigned int mask
;
7486 const enum insn_code icode
;
7488 const char *const name
;
7489 const enum rs6000_builtins code
;
7492 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
7494 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
7495 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
7496 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
7497 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
7498 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
7499 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
7500 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
7501 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
7502 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
7503 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
7504 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
7505 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
7506 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
},
7508 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P
},
7509 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P
},
7510 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P
}
7513 /* SPE predicates. */
7514 static struct builtin_description bdesc_spe_predicates
[] =
7516 /* Place-holder. Leave as first. */
7517 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
7518 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
7519 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
7520 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
7521 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
7522 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
7523 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
7524 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
7525 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
7526 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
7527 /* Place-holder. Leave as last. */
7528 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
7531 /* SPE evsel predicates. */
7532 static struct builtin_description bdesc_spe_evsel
[] =
7534 /* Place-holder. Leave as first. */
7535 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
7536 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
7537 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
7538 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
7539 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
7540 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
7541 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
7542 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
7543 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
7544 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
7545 /* Place-holder. Leave as last. */
7546 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
7549 /* PAIRED predicates. */
7550 static const struct builtin_description bdesc_paired_preds
[] =
7552 /* Place-holder. Leave as first. */
7553 { 0, CODE_FOR_paired_cmpu0
, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0
},
7554 /* Place-holder. Leave as last. */
7555 { 0, CODE_FOR_paired_cmpu1
, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1
},
7558 /* ABS* operations. */
7560 static const struct builtin_description bdesc_abs
[] =
7562 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
7563 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
7564 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
7565 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
7566 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
7567 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
7568 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
7571 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7574 static struct builtin_description bdesc_1arg
[] =
7576 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
7577 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
7578 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
7579 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
7580 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
7581 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
7582 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
7583 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
7584 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
7585 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
7586 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
7587 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
7588 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
7589 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
7590 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
7591 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
7592 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
7594 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS
},
7595 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS
},
7596 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL
},
7597 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE
},
7598 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR
},
7599 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE
},
7600 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR
},
7601 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE
},
7602 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND
},
7603 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE
},
7604 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC
},
7605 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH
},
7606 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH
},
7607 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX
},
7608 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB
},
7609 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL
},
7610 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX
},
7611 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH
},
7612 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB
},
7614 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7615 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7616 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
7617 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
7618 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
7619 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
7620 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
7621 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
7622 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
7623 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
7624 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
7625 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
7626 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
7627 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
7628 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
7629 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
7630 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
7631 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
7632 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
7633 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
7634 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
7635 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
7636 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
7637 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
7638 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
7639 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
7640 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
7641 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
7642 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
7643 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
7645 /* Place-holder. Leave as last unary SPE builtin. */
7646 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
7648 { 0, CODE_FOR_absv2sf2
, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2
},
7649 { 0, CODE_FOR_nabsv2sf2
, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2
},
7650 { 0, CODE_FOR_negv2sf2
, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2
},
7651 { 0, CODE_FOR_sqrtv2sf2
, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2
},
7652 { 0, CODE_FOR_resv2sf2
, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2
}
7656 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7659 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7660 rtx op0
= expand_normal (arg0
);
7661 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7662 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7664 if (icode
== CODE_FOR_nothing
)
7665 /* Builtin not supported on this processor. */
7668 /* If we got invalid arguments bail out before generating bad rtl. */
7669 if (arg0
== error_mark_node
)
7672 if (icode
== CODE_FOR_altivec_vspltisb
7673 || icode
== CODE_FOR_altivec_vspltish
7674 || icode
== CODE_FOR_altivec_vspltisw
7675 || icode
== CODE_FOR_spe_evsplatfi
7676 || icode
== CODE_FOR_spe_evsplati
)
7678 /* Only allow 5-bit *signed* literals. */
7679 if (GET_CODE (op0
) != CONST_INT
7680 || INTVAL (op0
) > 15
7681 || INTVAL (op0
) < -16)
7683 error ("argument 1 must be a 5-bit signed literal");
7689 || GET_MODE (target
) != tmode
7690 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7691 target
= gen_reg_rtx (tmode
);
7693 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7694 op0
= copy_to_mode_reg (mode0
, op0
);
7696 pat
= GEN_FCN (icode
) (target
, op0
);
7705 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
7707 rtx pat
, scratch1
, scratch2
;
7708 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7709 rtx op0
= expand_normal (arg0
);
7710 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7711 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7713 /* If we have invalid arguments, bail out before generating bad rtl. */
7714 if (arg0
== error_mark_node
)
7718 || GET_MODE (target
) != tmode
7719 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7720 target
= gen_reg_rtx (tmode
);
7722 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7723 op0
= copy_to_mode_reg (mode0
, op0
);
7725 scratch1
= gen_reg_rtx (mode0
);
7726 scratch2
= gen_reg_rtx (mode0
);
7728 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
7737 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7740 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7741 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7742 rtx op0
= expand_normal (arg0
);
7743 rtx op1
= expand_normal (arg1
);
7744 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7745 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7746 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7748 if (icode
== CODE_FOR_nothing
)
7749 /* Builtin not supported on this processor. */
7752 /* If we got invalid arguments bail out before generating bad rtl. */
7753 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7756 if (icode
== CODE_FOR_altivec_vcfux
7757 || icode
== CODE_FOR_altivec_vcfsx
7758 || icode
== CODE_FOR_altivec_vctsxs
7759 || icode
== CODE_FOR_altivec_vctuxs
7760 || icode
== CODE_FOR_altivec_vspltb
7761 || icode
== CODE_FOR_altivec_vsplth
7762 || icode
== CODE_FOR_altivec_vspltw
7763 || icode
== CODE_FOR_spe_evaddiw
7764 || icode
== CODE_FOR_spe_evldd
7765 || icode
== CODE_FOR_spe_evldh
7766 || icode
== CODE_FOR_spe_evldw
7767 || icode
== CODE_FOR_spe_evlhhesplat
7768 || icode
== CODE_FOR_spe_evlhhossplat
7769 || icode
== CODE_FOR_spe_evlhhousplat
7770 || icode
== CODE_FOR_spe_evlwhe
7771 || icode
== CODE_FOR_spe_evlwhos
7772 || icode
== CODE_FOR_spe_evlwhou
7773 || icode
== CODE_FOR_spe_evlwhsplat
7774 || icode
== CODE_FOR_spe_evlwwsplat
7775 || icode
== CODE_FOR_spe_evrlwi
7776 || icode
== CODE_FOR_spe_evslwi
7777 || icode
== CODE_FOR_spe_evsrwis
7778 || icode
== CODE_FOR_spe_evsubifw
7779 || icode
== CODE_FOR_spe_evsrwiu
)
7781 /* Only allow 5-bit unsigned literals. */
7783 if (TREE_CODE (arg1
) != INTEGER_CST
7784 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7786 error ("argument 2 must be a 5-bit unsigned literal");
7792 || GET_MODE (target
) != tmode
7793 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7794 target
= gen_reg_rtx (tmode
);
7796 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7797 op0
= copy_to_mode_reg (mode0
, op0
);
7798 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7799 op1
= copy_to_mode_reg (mode1
, op1
);
7801 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
7810 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
7811 tree exp
, rtx target
)
7814 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
7815 tree arg0
= CALL_EXPR_ARG (exp
, 1);
7816 tree arg1
= CALL_EXPR_ARG (exp
, 2);
7817 rtx op0
= expand_normal (arg0
);
7818 rtx op1
= expand_normal (arg1
);
7819 enum machine_mode tmode
= SImode
;
7820 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7821 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7824 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
7826 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7830 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
7832 gcc_assert (mode0
== mode1
);
7834 /* If we have invalid arguments, bail out before generating bad rtl. */
7835 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7839 || GET_MODE (target
) != tmode
7840 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7841 target
= gen_reg_rtx (tmode
);
7843 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7844 op0
= copy_to_mode_reg (mode0
, op0
);
7845 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7846 op1
= copy_to_mode_reg (mode1
, op1
);
7848 scratch
= gen_reg_rtx (mode0
);
7850 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
7851 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
7856 /* The vec_any* and vec_all* predicates use the same opcodes for two
7857 different operations, but the bits in CR6 will be different
7858 depending on what information we want. So we have to play tricks
7859 with CR6 to get the right bits out.
7861 If you think this is disgusting, look at the specs for the
7862 AltiVec predicates. */
7864 switch (cr6_form_int
)
7867 emit_insn (gen_cr6_test_for_zero (target
));
7870 emit_insn (gen_cr6_test_for_zero_reverse (target
));
7873 emit_insn (gen_cr6_test_for_lt (target
));
7876 emit_insn (gen_cr6_test_for_lt_reverse (target
));
7879 error ("argument 1 of __builtin_altivec_predicate is out of range");
7887 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7890 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7891 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7892 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7893 enum machine_mode mode0
= Pmode
;
7894 enum machine_mode mode1
= Pmode
;
7895 rtx op0
= expand_normal (arg0
);
7896 rtx op1
= expand_normal (arg1
);
7898 if (icode
== CODE_FOR_nothing
)
7899 /* Builtin not supported on this processor. */
7902 /* If we got invalid arguments bail out before generating bad rtl. */
7903 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7907 || GET_MODE (target
) != tmode
7908 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7909 target
= gen_reg_rtx (tmode
);
7911 op1
= copy_to_mode_reg (mode1
, op1
);
7913 if (op0
== const0_rtx
)
7915 addr
= gen_rtx_MEM (tmode
, op1
);
7919 op0
= copy_to_mode_reg (mode0
, op0
);
7920 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7923 pat
= GEN_FCN (icode
) (target
, addr
);
7933 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7936 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7937 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7938 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7939 enum machine_mode mode0
= Pmode
;
7940 enum machine_mode mode1
= Pmode
;
7941 rtx op0
= expand_normal (arg0
);
7942 rtx op1
= expand_normal (arg1
);
7944 if (icode
== CODE_FOR_nothing
)
7945 /* Builtin not supported on this processor. */
7948 /* If we got invalid arguments bail out before generating bad rtl. */
7949 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7953 || GET_MODE (target
) != tmode
7954 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7955 target
= gen_reg_rtx (tmode
);
7957 op1
= copy_to_mode_reg (mode1
, op1
);
7959 if (op0
== const0_rtx
)
7961 addr
= gen_rtx_MEM (tmode
, op1
);
7965 op0
= copy_to_mode_reg (mode0
, op0
);
7966 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7969 pat
= GEN_FCN (icode
) (target
, addr
);
7979 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
7981 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7982 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7983 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7984 rtx op0
= expand_normal (arg0
);
7985 rtx op1
= expand_normal (arg1
);
7986 rtx op2
= expand_normal (arg2
);
7988 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
7989 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
7990 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
7992 /* Invalid arguments. Bail before doing anything stoopid! */
7993 if (arg0
== error_mark_node
7994 || arg1
== error_mark_node
7995 || arg2
== error_mark_node
)
7998 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
7999 op0
= copy_to_mode_reg (mode2
, op0
);
8000 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
8001 op1
= copy_to_mode_reg (mode0
, op1
);
8002 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
8003 op2
= copy_to_mode_reg (mode1
, op2
);
8005 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
8012 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
8014 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8015 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8016 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8017 rtx op0
= expand_normal (arg0
);
8018 rtx op1
= expand_normal (arg1
);
8019 rtx op2
= expand_normal (arg2
);
8021 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8022 enum machine_mode mode1
= Pmode
;
8023 enum machine_mode mode2
= Pmode
;
8025 /* Invalid arguments. Bail before doing anything stoopid! */
8026 if (arg0
== error_mark_node
8027 || arg1
== error_mark_node
8028 || arg2
== error_mark_node
)
8031 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
8032 op0
= copy_to_mode_reg (tmode
, op0
);
8034 op2
= copy_to_mode_reg (mode2
, op2
);
8036 if (op1
== const0_rtx
)
8038 addr
= gen_rtx_MEM (tmode
, op2
);
8042 op1
= copy_to_mode_reg (mode1
, op1
);
8043 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
8046 pat
= GEN_FCN (icode
) (addr
, op0
);
8053 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
8055 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8056 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8057 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8058 rtx op0
= expand_normal (arg0
);
8059 rtx op1
= expand_normal (arg1
);
8060 rtx op2
= expand_normal (arg2
);
8062 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8063 enum machine_mode mode1
= Pmode
;
8064 enum machine_mode mode2
= Pmode
;
8066 /* Invalid arguments. Bail before doing anything stoopid! */
8067 if (arg0
== error_mark_node
8068 || arg1
== error_mark_node
8069 || arg2
== error_mark_node
)
8072 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
8073 op0
= copy_to_mode_reg (tmode
, op0
);
8075 op2
= copy_to_mode_reg (mode2
, op2
);
8077 if (op1
== const0_rtx
)
8079 addr
= gen_rtx_MEM (tmode
, op2
);
8083 op1
= copy_to_mode_reg (mode1
, op1
);
8084 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
8087 pat
= GEN_FCN (icode
) (addr
, op0
);
8094 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
8097 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8098 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8099 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8100 rtx op0
= expand_normal (arg0
);
8101 rtx op1
= expand_normal (arg1
);
8102 rtx op2
= expand_normal (arg2
);
8103 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8104 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8105 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8106 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
8108 if (icode
== CODE_FOR_nothing
)
8109 /* Builtin not supported on this processor. */
8112 /* If we got invalid arguments bail out before generating bad rtl. */
8113 if (arg0
== error_mark_node
8114 || arg1
== error_mark_node
8115 || arg2
== error_mark_node
)
8118 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
8119 || icode
== CODE_FOR_altivec_vsldoi_v4si
8120 || icode
== CODE_FOR_altivec_vsldoi_v8hi
8121 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
8123 /* Only allow 4-bit unsigned literals. */
8125 if (TREE_CODE (arg2
) != INTEGER_CST
8126 || TREE_INT_CST_LOW (arg2
) & ~0xf)
8128 error ("argument 3 must be a 4-bit unsigned literal");
8134 || GET_MODE (target
) != tmode
8135 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8136 target
= gen_reg_rtx (tmode
);
8138 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8139 op0
= copy_to_mode_reg (mode0
, op0
);
8140 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8141 op1
= copy_to_mode_reg (mode1
, op1
);
8142 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
8143 op2
= copy_to_mode_reg (mode2
, op2
);
8145 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
8146 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
8148 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8156 /* Expand the lvx builtins. */
8158 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
8160 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8161 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8163 enum machine_mode tmode
, mode0
;
8165 enum insn_code icode
;
8169 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
8170 icode
= CODE_FOR_altivec_lvx_v16qi
;
8172 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
8173 icode
= CODE_FOR_altivec_lvx_v8hi
;
8175 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
8176 icode
= CODE_FOR_altivec_lvx_v4si
;
8178 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
8179 icode
= CODE_FOR_altivec_lvx_v4sf
;
8188 arg0
= CALL_EXPR_ARG (exp
, 0);
8189 op0
= expand_normal (arg0
);
8190 tmode
= insn_data
[icode
].operand
[0].mode
;
8191 mode0
= insn_data
[icode
].operand
[1].mode
;
8194 || GET_MODE (target
) != tmode
8195 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8196 target
= gen_reg_rtx (tmode
);
8198 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8199 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8201 pat
= GEN_FCN (icode
) (target
, op0
);
8208 /* Expand the stvx builtins. */
8210 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8213 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8214 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8216 enum machine_mode mode0
, mode1
;
8218 enum insn_code icode
;
8222 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
8223 icode
= CODE_FOR_altivec_stvx_v16qi
;
8225 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
8226 icode
= CODE_FOR_altivec_stvx_v8hi
;
8228 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
8229 icode
= CODE_FOR_altivec_stvx_v4si
;
8231 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
8232 icode
= CODE_FOR_altivec_stvx_v4sf
;
8239 arg0
= CALL_EXPR_ARG (exp
, 0);
8240 arg1
= CALL_EXPR_ARG (exp
, 1);
8241 op0
= expand_normal (arg0
);
8242 op1
= expand_normal (arg1
);
8243 mode0
= insn_data
[icode
].operand
[0].mode
;
8244 mode1
= insn_data
[icode
].operand
[1].mode
;
8246 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8247 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8248 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8249 op1
= copy_to_mode_reg (mode1
, op1
);
8251 pat
= GEN_FCN (icode
) (op0
, op1
);
8259 /* Expand the dst builtins. */
8261 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8264 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8265 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8266 tree arg0
, arg1
, arg2
;
8267 enum machine_mode mode0
, mode1
, mode2
;
8268 rtx pat
, op0
, op1
, op2
;
8269 const struct builtin_description
*d
;
8274 /* Handle DST variants. */
8276 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8277 if (d
->code
== fcode
)
8279 arg0
= CALL_EXPR_ARG (exp
, 0);
8280 arg1
= CALL_EXPR_ARG (exp
, 1);
8281 arg2
= CALL_EXPR_ARG (exp
, 2);
8282 op0
= expand_normal (arg0
);
8283 op1
= expand_normal (arg1
);
8284 op2
= expand_normal (arg2
);
8285 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8286 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8287 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8289 /* Invalid arguments, bail out before generating bad rtl. */
8290 if (arg0
== error_mark_node
8291 || arg1
== error_mark_node
8292 || arg2
== error_mark_node
)
8297 if (TREE_CODE (arg2
) != INTEGER_CST
8298 || TREE_INT_CST_LOW (arg2
) & ~0x3)
8300 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
8304 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
8305 op0
= copy_to_mode_reg (Pmode
, op0
);
8306 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
8307 op1
= copy_to_mode_reg (mode1
, op1
);
8309 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
8319 /* Expand vec_init builtin. */
8321 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
8323 enum machine_mode tmode
= TYPE_MODE (type
);
8324 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
8325 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
8326 rtvec v
= rtvec_alloc (n_elt
);
8328 gcc_assert (VECTOR_MODE_P (tmode
));
8329 gcc_assert (n_elt
== call_expr_nargs (exp
));
8331 for (i
= 0; i
< n_elt
; ++i
)
8333 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
8334 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
8337 if (!target
|| !register_operand (target
, tmode
))
8338 target
= gen_reg_rtx (tmode
);
8340 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
8344 /* Return the integer constant in ARG. Constrain it to be in the range
8345 of the subparts of VEC_TYPE; issue an error if not. */
8348 get_element_number (tree vec_type
, tree arg
)
8350 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
8352 if (!host_integerp (arg
, 1)
8353 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
8355 error ("selector must be an integer constant in the range 0..%wi", max
);
8362 /* Expand vec_set builtin. */
8364 altivec_expand_vec_set_builtin (tree exp
)
8366 enum machine_mode tmode
, mode1
;
8367 tree arg0
, arg1
, arg2
;
8371 arg0
= CALL_EXPR_ARG (exp
, 0);
8372 arg1
= CALL_EXPR_ARG (exp
, 1);
8373 arg2
= CALL_EXPR_ARG (exp
, 2);
8375 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
8376 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8377 gcc_assert (VECTOR_MODE_P (tmode
));
8379 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, 0);
8380 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, 0);
8381 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
8383 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
8384 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
8386 op0
= force_reg (tmode
, op0
);
8387 op1
= force_reg (mode1
, op1
);
8389 rs6000_expand_vector_set (op0
, op1
, elt
);
8394 /* Expand vec_ext builtin. */
8396 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
8398 enum machine_mode tmode
, mode0
;
8403 arg0
= CALL_EXPR_ARG (exp
, 0);
8404 arg1
= CALL_EXPR_ARG (exp
, 1);
8406 op0
= expand_normal (arg0
);
8407 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
8409 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8410 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
8411 gcc_assert (VECTOR_MODE_P (mode0
));
8413 op0
= force_reg (mode0
, op0
);
8415 if (optimize
|| !target
|| !register_operand (target
, tmode
))
8416 target
= gen_reg_rtx (tmode
);
8418 rs6000_expand_vector_extract (target
, op0
, elt
);
8423 /* Expand the builtin in EXP and store the result in TARGET. Store
8424 true in *EXPANDEDP if we found a builtin to expand. */
8426 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8428 const struct builtin_description
*d
;
8429 const struct builtin_description_predicates
*dp
;
8431 enum insn_code icode
;
8432 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8435 enum machine_mode tmode
, mode0
;
8436 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8438 if (fcode
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8439 && fcode
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
)
8442 error ("unresolved overload for Altivec builtin %qF", fndecl
);
8446 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
8450 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
8454 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
8462 case ALTIVEC_BUILTIN_STVX
:
8463 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, exp
);
8464 case ALTIVEC_BUILTIN_STVEBX
:
8465 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
8466 case ALTIVEC_BUILTIN_STVEHX
:
8467 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
8468 case ALTIVEC_BUILTIN_STVEWX
:
8469 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
8470 case ALTIVEC_BUILTIN_STVXL
:
8471 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
8473 case ALTIVEC_BUILTIN_MFVSCR
:
8474 icode
= CODE_FOR_altivec_mfvscr
;
8475 tmode
= insn_data
[icode
].operand
[0].mode
;
8478 || GET_MODE (target
) != tmode
8479 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8480 target
= gen_reg_rtx (tmode
);
8482 pat
= GEN_FCN (icode
) (target
);
8488 case ALTIVEC_BUILTIN_MTVSCR
:
8489 icode
= CODE_FOR_altivec_mtvscr
;
8490 arg0
= CALL_EXPR_ARG (exp
, 0);
8491 op0
= expand_normal (arg0
);
8492 mode0
= insn_data
[icode
].operand
[0].mode
;
8494 /* If we got invalid arguments bail out before generating bad rtl. */
8495 if (arg0
== error_mark_node
)
8498 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8499 op0
= copy_to_mode_reg (mode0
, op0
);
8501 pat
= GEN_FCN (icode
) (op0
);
8506 case ALTIVEC_BUILTIN_DSSALL
:
8507 emit_insn (gen_altivec_dssall ());
8510 case ALTIVEC_BUILTIN_DSS
:
8511 icode
= CODE_FOR_altivec_dss
;
8512 arg0
= CALL_EXPR_ARG (exp
, 0);
8514 op0
= expand_normal (arg0
);
8515 mode0
= insn_data
[icode
].operand
[0].mode
;
8517 /* If we got invalid arguments bail out before generating bad rtl. */
8518 if (arg0
== error_mark_node
)
8521 if (TREE_CODE (arg0
) != INTEGER_CST
8522 || TREE_INT_CST_LOW (arg0
) & ~0x3)
8524 error ("argument to dss must be a 2-bit unsigned literal");
8528 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8529 op0
= copy_to_mode_reg (mode0
, op0
);
8531 emit_insn (gen_altivec_dss (op0
));
8534 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
8535 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
8536 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
8537 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
8538 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
8540 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
8541 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
8542 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
8543 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
8544 return altivec_expand_vec_set_builtin (exp
);
8546 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
8547 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
8548 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
8549 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
8550 return altivec_expand_vec_ext_builtin (exp
, target
);
8557 /* Expand abs* operations. */
8559 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8560 if (d
->code
== fcode
)
8561 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
8563 /* Expand the AltiVec predicates. */
8564 dp
= bdesc_altivec_preds
;
8565 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8566 if (dp
->code
== fcode
)
8567 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
8570 /* LV* are funky. We initialized them differently. */
8573 case ALTIVEC_BUILTIN_LVSL
:
8574 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
8576 case ALTIVEC_BUILTIN_LVSR
:
8577 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
8579 case ALTIVEC_BUILTIN_LVEBX
:
8580 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
8582 case ALTIVEC_BUILTIN_LVEHX
:
8583 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
8585 case ALTIVEC_BUILTIN_LVEWX
:
8586 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
8588 case ALTIVEC_BUILTIN_LVXL
:
8589 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
8591 case ALTIVEC_BUILTIN_LVX
:
8592 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
8603 /* Expand the builtin in EXP and store the result in TARGET. Store
8604 true in *EXPANDEDP if we found a builtin to expand. */
8606 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
8608 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8609 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8610 const struct builtin_description
*d
;
8617 case PAIRED_BUILTIN_STX
:
8618 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
8619 case PAIRED_BUILTIN_LX
:
8620 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
8626 /* Expand the paired predicates. */
8627 d
= bdesc_paired_preds
;
8628 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
8629 if (d
->code
== fcode
)
8630 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
8636 /* Binops that need to be initialized manually, but can be expanded
8637 automagically by rs6000_expand_binop_builtin. */
8638 static struct builtin_description bdesc_2arg_spe
[] =
8640 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
8641 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
8642 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
8643 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
8644 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
8645 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
8646 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
8647 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
8648 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
8649 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
8650 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
8651 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
8652 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
8653 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
8654 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
8655 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
8656 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
8657 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
8658 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
8659 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
8660 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
8661 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
8664 /* Expand the builtin in EXP and store the result in TARGET. Store
8665 true in *EXPANDEDP if we found a builtin to expand.
8667 This expands the SPE builtins that are not simple unary and binary
8670 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8672 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8674 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8675 enum insn_code icode
;
8676 enum machine_mode tmode
, mode0
;
8678 struct builtin_description
*d
;
8683 /* Syntax check for a 5-bit unsigned immediate. */
8686 case SPE_BUILTIN_EVSTDD
:
8687 case SPE_BUILTIN_EVSTDH
:
8688 case SPE_BUILTIN_EVSTDW
:
8689 case SPE_BUILTIN_EVSTWHE
:
8690 case SPE_BUILTIN_EVSTWHO
:
8691 case SPE_BUILTIN_EVSTWWE
:
8692 case SPE_BUILTIN_EVSTWWO
:
8693 arg1
= CALL_EXPR_ARG (exp
, 2);
8694 if (TREE_CODE (arg1
) != INTEGER_CST
8695 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
8697 error ("argument 2 must be a 5-bit unsigned literal");
8705 /* The evsplat*i instructions are not quite generic. */
8708 case SPE_BUILTIN_EVSPLATFI
:
8709 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
8711 case SPE_BUILTIN_EVSPLATI
:
8712 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
8718 d
= (struct builtin_description
*) bdesc_2arg_spe
;
8719 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
8720 if (d
->code
== fcode
)
8721 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
8723 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8724 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
8725 if (d
->code
== fcode
)
8726 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
8728 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8729 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
8730 if (d
->code
== fcode
)
8731 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
8735 case SPE_BUILTIN_EVSTDDX
:
8736 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
8737 case SPE_BUILTIN_EVSTDHX
:
8738 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
8739 case SPE_BUILTIN_EVSTDWX
:
8740 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
8741 case SPE_BUILTIN_EVSTWHEX
:
8742 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
8743 case SPE_BUILTIN_EVSTWHOX
:
8744 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
8745 case SPE_BUILTIN_EVSTWWEX
:
8746 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
8747 case SPE_BUILTIN_EVSTWWOX
:
8748 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
8749 case SPE_BUILTIN_EVSTDD
:
8750 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
8751 case SPE_BUILTIN_EVSTDH
:
8752 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
8753 case SPE_BUILTIN_EVSTDW
:
8754 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
8755 case SPE_BUILTIN_EVSTWHE
:
8756 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
8757 case SPE_BUILTIN_EVSTWHO
:
8758 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
8759 case SPE_BUILTIN_EVSTWWE
:
8760 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
8761 case SPE_BUILTIN_EVSTWWO
:
8762 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
8763 case SPE_BUILTIN_MFSPEFSCR
:
8764 icode
= CODE_FOR_spe_mfspefscr
;
8765 tmode
= insn_data
[icode
].operand
[0].mode
;
8768 || GET_MODE (target
) != tmode
8769 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8770 target
= gen_reg_rtx (tmode
);
8772 pat
= GEN_FCN (icode
) (target
);
8777 case SPE_BUILTIN_MTSPEFSCR
:
8778 icode
= CODE_FOR_spe_mtspefscr
;
8779 arg0
= CALL_EXPR_ARG (exp
, 0);
8780 op0
= expand_normal (arg0
);
8781 mode0
= insn_data
[icode
].operand
[0].mode
;
8783 if (arg0
== error_mark_node
)
8786 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8787 op0
= copy_to_mode_reg (mode0
, op0
);
8789 pat
= GEN_FCN (icode
) (op0
);
8802 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8804 rtx pat
, scratch
, tmp
;
8805 tree form
= CALL_EXPR_ARG (exp
, 0);
8806 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8807 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8808 rtx op0
= expand_normal (arg0
);
8809 rtx op1
= expand_normal (arg1
);
8810 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8811 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8815 if (TREE_CODE (form
) != INTEGER_CST
)
8817 error ("argument 1 of __builtin_paired_predicate must be a constant");
8821 form_int
= TREE_INT_CST_LOW (form
);
8823 gcc_assert (mode0
== mode1
);
8825 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8829 || GET_MODE (target
) != SImode
8830 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8831 target
= gen_reg_rtx (SImode
);
8832 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8833 op0
= copy_to_mode_reg (mode0
, op0
);
8834 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8835 op1
= copy_to_mode_reg (mode1
, op1
);
8837 scratch
= gen_reg_rtx (CCFPmode
);
8839 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8861 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8864 error ("argument 1 of __builtin_paired_predicate is out of range");
8868 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8869 emit_move_insn (target
, tmp
);
8874 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8876 rtx pat
, scratch
, tmp
;
8877 tree form
= CALL_EXPR_ARG (exp
, 0);
8878 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8879 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8880 rtx op0
= expand_normal (arg0
);
8881 rtx op1
= expand_normal (arg1
);
8882 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8883 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8887 if (TREE_CODE (form
) != INTEGER_CST
)
8889 error ("argument 1 of __builtin_spe_predicate must be a constant");
8893 form_int
= TREE_INT_CST_LOW (form
);
8895 gcc_assert (mode0
== mode1
);
8897 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8901 || GET_MODE (target
) != SImode
8902 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8903 target
= gen_reg_rtx (SImode
);
8905 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8906 op0
= copy_to_mode_reg (mode0
, op0
);
8907 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8908 op1
= copy_to_mode_reg (mode1
, op1
);
8910 scratch
= gen_reg_rtx (CCmode
);
8912 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8917 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8918 _lower_. We use one compare, but look in different bits of the
8919 CR for each variant.
8921 There are 2 elements in each SPE simd type (upper/lower). The CR
8922 bits are set as follows:
8924 BIT0 | BIT 1 | BIT 2 | BIT 3
8925 U | L | (U | L) | (U & L)
8927 So, for an "all" relationship, BIT 3 would be set.
8928 For an "any" relationship, BIT 2 would be set. Etc.
8930 Following traditional nomenclature, these bits map to:
8932 BIT0 | BIT 1 | BIT 2 | BIT 3
8935 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8940 /* All variant. OV bit. */
8942 /* We need to get to the OV bit, which is the ORDERED bit. We
8943 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8944 that's ugly and will make validate_condition_mode die.
8945 So let's just use another pattern. */
8946 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8948 /* Any variant. EQ bit. */
8952 /* Upper variant. LT bit. */
8956 /* Lower variant. GT bit. */
8961 error ("argument 1 of __builtin_spe_predicate is out of range");
8965 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8966 emit_move_insn (target
, tmp
);
8971 /* The evsel builtins look like this:
8973 e = __builtin_spe_evsel_OP (a, b, c, d);
8977 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8978 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8982 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
8985 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8986 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8987 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8988 tree arg3
= CALL_EXPR_ARG (exp
, 3);
8989 rtx op0
= expand_normal (arg0
);
8990 rtx op1
= expand_normal (arg1
);
8991 rtx op2
= expand_normal (arg2
);
8992 rtx op3
= expand_normal (arg3
);
8993 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8994 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8996 gcc_assert (mode0
== mode1
);
8998 if (arg0
== error_mark_node
|| arg1
== error_mark_node
8999 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
9003 || GET_MODE (target
) != mode0
9004 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
9005 target
= gen_reg_rtx (mode0
);
9007 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9008 op0
= copy_to_mode_reg (mode0
, op0
);
9009 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
9010 op1
= copy_to_mode_reg (mode0
, op1
);
9011 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
9012 op2
= copy_to_mode_reg (mode0
, op2
);
9013 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
9014 op3
= copy_to_mode_reg (mode0
, op3
);
9016 /* Generate the compare. */
9017 scratch
= gen_reg_rtx (CCmode
);
9018 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
9023 if (mode0
== V2SImode
)
9024 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
9026 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
9031 /* Expand an expression EXP that calls a built-in function,
9032 with result going to TARGET if that's convenient
9033 (and in mode MODE if that's convenient).
9034 SUBTARGET may be used as the target for computing one of EXP's operands.
9035 IGNORE is nonzero if the value is to be ignored. */
9038 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9039 enum machine_mode mode ATTRIBUTE_UNUSED
,
9040 int ignore ATTRIBUTE_UNUSED
)
9042 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9043 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9044 const struct builtin_description
*d
;
9049 if (fcode
== RS6000_BUILTIN_RECIP
)
9050 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
9052 if (fcode
== RS6000_BUILTIN_RECIPF
)
9053 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
9055 if (fcode
== RS6000_BUILTIN_RSQRTF
)
9056 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
9058 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
9059 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
9061 int icode
= (int) CODE_FOR_altivec_lvsr
;
9062 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9063 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
9067 gcc_assert (TARGET_ALTIVEC
);
9069 arg
= CALL_EXPR_ARG (exp
, 0);
9070 gcc_assert (TREE_CODE (TREE_TYPE (arg
)) == POINTER_TYPE
);
9071 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
9072 addr
= memory_address (mode
, op
);
9073 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
9077 /* For the load case need to negate the address. */
9078 op
= gen_reg_rtx (GET_MODE (addr
));
9079 emit_insn (gen_rtx_SET (VOIDmode
, op
,
9080 gen_rtx_NEG (GET_MODE (addr
), addr
)));
9082 op
= gen_rtx_MEM (mode
, op
);
9085 || GET_MODE (target
) != tmode
9086 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9087 target
= gen_reg_rtx (tmode
);
9089 /*pat = gen_altivec_lvsr (target, op);*/
9090 pat
= GEN_FCN (icode
) (target
, op
);
9098 /* FIXME: There's got to be a nicer way to handle this case than
9099 constructing a new CALL_EXPR. */
9100 if (fcode
== ALTIVEC_BUILTIN_VCFUX
9101 || fcode
== ALTIVEC_BUILTIN_VCFSX
)
9103 if (call_expr_nargs (exp
) == 1)
9104 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
9105 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
9110 ret
= altivec_expand_builtin (exp
, target
, &success
);
9117 ret
= spe_expand_builtin (exp
, target
, &success
);
9122 if (TARGET_PAIRED_FLOAT
)
9124 ret
= paired_expand_builtin (exp
, target
, &success
);
9130 gcc_assert (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
9132 /* Handle simple unary operations. */
9133 d
= (struct builtin_description
*) bdesc_1arg
;
9134 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9135 if (d
->code
== fcode
)
9136 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
9138 /* Handle simple binary operations. */
9139 d
= (struct builtin_description
*) bdesc_2arg
;
9140 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9141 if (d
->code
== fcode
)
9142 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
9144 /* Handle simple ternary operations. */
9146 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
9147 if (d
->code
== fcode
)
9148 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
9154 build_opaque_vector_type (tree node
, int nunits
)
9156 node
= copy_node (node
);
9157 TYPE_MAIN_VARIANT (node
) = node
;
9158 TYPE_CANONICAL (node
) = node
;
9159 return build_vector_type (node
, nunits
);
9163 rs6000_init_builtins (void)
9165 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
9166 V2SF_type_node
= build_vector_type (float_type_node
, 2);
9167 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
9168 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
9169 V4SF_type_node
= build_vector_type (float_type_node
, 4);
9170 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
9171 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
9173 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
9174 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
9175 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
9177 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
9178 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
9179 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
9180 opaque_V4SI_type_node
= copy_node (V4SI_type_node
);
9182 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9183 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9184 'vector unsigned short'. */
9186 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
9187 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9188 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
9189 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9191 long_integer_type_internal_node
= long_integer_type_node
;
9192 long_unsigned_type_internal_node
= long_unsigned_type_node
;
9193 intQI_type_internal_node
= intQI_type_node
;
9194 uintQI_type_internal_node
= unsigned_intQI_type_node
;
9195 intHI_type_internal_node
= intHI_type_node
;
9196 uintHI_type_internal_node
= unsigned_intHI_type_node
;
9197 intSI_type_internal_node
= intSI_type_node
;
9198 uintSI_type_internal_node
= unsigned_intSI_type_node
;
9199 float_type_internal_node
= float_type_node
;
9200 void_type_internal_node
= void_type_node
;
9202 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9203 get_identifier ("__bool char"),
9204 bool_char_type_node
));
9205 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9206 get_identifier ("__bool short"),
9207 bool_short_type_node
));
9208 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9209 get_identifier ("__bool int"),
9210 bool_int_type_node
));
9211 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9212 get_identifier ("__pixel"),
9215 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
9216 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
9217 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
9218 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
9220 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9221 get_identifier ("__vector unsigned char"),
9222 unsigned_V16QI_type_node
));
9223 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9224 get_identifier ("__vector signed char"),
9226 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9227 get_identifier ("__vector __bool char"),
9228 bool_V16QI_type_node
));
9230 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9231 get_identifier ("__vector unsigned short"),
9232 unsigned_V8HI_type_node
));
9233 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9234 get_identifier ("__vector signed short"),
9236 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9237 get_identifier ("__vector __bool short"),
9238 bool_V8HI_type_node
));
9240 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9241 get_identifier ("__vector unsigned int"),
9242 unsigned_V4SI_type_node
));
9243 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9244 get_identifier ("__vector signed int"),
9246 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9247 get_identifier ("__vector __bool int"),
9248 bool_V4SI_type_node
));
9250 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9251 get_identifier ("__vector float"),
9253 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9254 get_identifier ("__vector __pixel"),
9255 pixel_V8HI_type_node
));
9257 if (TARGET_PAIRED_FLOAT
)
9258 paired_init_builtins ();
9260 spe_init_builtins ();
9262 altivec_init_builtins ();
9263 if (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
9264 rs6000_common_init_builtins ();
9265 if (TARGET_PPC_GFXOPT
)
9267 tree ftype
= build_function_type_list (float_type_node
,
9271 def_builtin (MASK_PPC_GFXOPT
, "__builtin_recipdivf", ftype
,
9272 RS6000_BUILTIN_RECIPF
);
9274 ftype
= build_function_type_list (float_type_node
,
9277 def_builtin (MASK_PPC_GFXOPT
, "__builtin_rsqrtf", ftype
,
9278 RS6000_BUILTIN_RSQRTF
);
9282 tree ftype
= build_function_type_list (double_type_node
,
9286 def_builtin (MASK_POPCNTB
, "__builtin_recipdiv", ftype
,
9287 RS6000_BUILTIN_RECIP
);
9292 /* AIX libm provides clog as __clog. */
9293 if (built_in_decls
[BUILT_IN_CLOG
])
9294 set_user_assembler_name (built_in_decls
[BUILT_IN_CLOG
], "__clog");
9297 #ifdef SUBTARGET_INIT_BUILTINS
9298 SUBTARGET_INIT_BUILTINS
;
9302 /* Search through a set of builtins and enable the mask bits.
9303 DESC is an array of builtins.
9304 SIZE is the total number of builtins.
9305 START is the builtin enum at which to start.
9306 END is the builtin enum at which to end. */
9308 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
9309 enum rs6000_builtins start
,
9310 enum rs6000_builtins end
)
9314 for (i
= 0; i
< size
; ++i
)
9315 if (desc
[i
].code
== start
)
9321 for (; i
< size
; ++i
)
9323 /* Flip all the bits on. */
9324 desc
[i
].mask
= target_flags
;
9325 if (desc
[i
].code
== end
)
9331 spe_init_builtins (void)
9333 tree endlink
= void_list_node
;
9334 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
9335 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
9336 struct builtin_description
*d
;
9339 tree v2si_ftype_4_v2si
9340 = build_function_type
9341 (opaque_V2SI_type_node
,
9342 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9343 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9344 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9345 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9348 tree v2sf_ftype_4_v2sf
9349 = build_function_type
9350 (opaque_V2SF_type_node
,
9351 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9352 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9353 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9354 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9357 tree int_ftype_int_v2si_v2si
9358 = build_function_type
9360 tree_cons (NULL_TREE
, integer_type_node
,
9361 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9362 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9365 tree int_ftype_int_v2sf_v2sf
9366 = build_function_type
9368 tree_cons (NULL_TREE
, integer_type_node
,
9369 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9370 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9373 tree void_ftype_v2si_puint_int
9374 = build_function_type (void_type_node
,
9375 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9376 tree_cons (NULL_TREE
, puint_type_node
,
9377 tree_cons (NULL_TREE
,
9381 tree void_ftype_v2si_puint_char
9382 = build_function_type (void_type_node
,
9383 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9384 tree_cons (NULL_TREE
, puint_type_node
,
9385 tree_cons (NULL_TREE
,
9389 tree void_ftype_v2si_pv2si_int
9390 = build_function_type (void_type_node
,
9391 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9392 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9393 tree_cons (NULL_TREE
,
9397 tree void_ftype_v2si_pv2si_char
9398 = build_function_type (void_type_node
,
9399 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9400 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9401 tree_cons (NULL_TREE
,
9406 = build_function_type (void_type_node
,
9407 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
9410 = build_function_type (integer_type_node
, endlink
);
9412 tree v2si_ftype_pv2si_int
9413 = build_function_type (opaque_V2SI_type_node
,
9414 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9415 tree_cons (NULL_TREE
, integer_type_node
,
9418 tree v2si_ftype_puint_int
9419 = build_function_type (opaque_V2SI_type_node
,
9420 tree_cons (NULL_TREE
, puint_type_node
,
9421 tree_cons (NULL_TREE
, integer_type_node
,
9424 tree v2si_ftype_pushort_int
9425 = build_function_type (opaque_V2SI_type_node
,
9426 tree_cons (NULL_TREE
, pushort_type_node
,
9427 tree_cons (NULL_TREE
, integer_type_node
,
9430 tree v2si_ftype_signed_char
9431 = build_function_type (opaque_V2SI_type_node
,
9432 tree_cons (NULL_TREE
, signed_char_type_node
,
9435 /* The initialization of the simple binary and unary builtins is
9436 done in rs6000_common_init_builtins, but we have to enable the
9437 mask bits here manually because we have run out of `target_flags'
9438 bits. We really need to redesign this mask business. */
9440 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
9441 ARRAY_SIZE (bdesc_2arg
),
9444 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
9445 ARRAY_SIZE (bdesc_1arg
),
9447 SPE_BUILTIN_EVSUBFUSIAAW
);
9448 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
9449 ARRAY_SIZE (bdesc_spe_predicates
),
9450 SPE_BUILTIN_EVCMPEQ
,
9451 SPE_BUILTIN_EVFSTSTLT
);
9452 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
9453 ARRAY_SIZE (bdesc_spe_evsel
),
9454 SPE_BUILTIN_EVSEL_CMPGTS
,
9455 SPE_BUILTIN_EVSEL_FSTSTEQ
);
9457 (*lang_hooks
.decls
.pushdecl
)
9458 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
9459 opaque_V2SI_type_node
));
9461 /* Initialize irregular SPE builtins. */
9463 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
9464 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
9465 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
9466 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
9467 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
9468 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
9469 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
9470 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
9471 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
9472 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
9473 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
9474 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
9475 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
9476 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
9477 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
9478 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
9479 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
9480 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
9483 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
9484 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
9485 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
9486 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
9487 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
9488 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
9489 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
9490 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
9491 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
9492 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
9493 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
9494 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
9495 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
9496 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
9497 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
9498 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
9499 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
9500 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
9501 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
9502 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
9503 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
9504 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
9507 d
= (struct builtin_description
*) bdesc_spe_predicates
;
9508 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
9512 switch (insn_data
[d
->icode
].operand
[1].mode
)
9515 type
= int_ftype_int_v2si_v2si
;
9518 type
= int_ftype_int_v2sf_v2sf
;
9524 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9527 /* Evsel predicates. */
9528 d
= (struct builtin_description
*) bdesc_spe_evsel
;
9529 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
9533 switch (insn_data
[d
->icode
].operand
[1].mode
)
9536 type
= v2si_ftype_4_v2si
;
9539 type
= v2sf_ftype_4_v2sf
;
9545 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9550 paired_init_builtins (void)
9552 const struct builtin_description
*d
;
9554 tree endlink
= void_list_node
;
9556 tree int_ftype_int_v2sf_v2sf
9557 = build_function_type
9559 tree_cons (NULL_TREE
, integer_type_node
,
9560 tree_cons (NULL_TREE
, V2SF_type_node
,
9561 tree_cons (NULL_TREE
, V2SF_type_node
,
9563 tree pcfloat_type_node
=
9564 build_pointer_type (build_qualified_type
9565 (float_type_node
, TYPE_QUAL_CONST
));
9567 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
9568 long_integer_type_node
,
9571 tree void_ftype_v2sf_long_pcfloat
=
9572 build_function_type_list (void_type_node
,
9574 long_integer_type_node
,
9579 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
9583 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
9584 PAIRED_BUILTIN_STX
);
9587 d
= bdesc_paired_preds
;
9588 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
9592 switch (insn_data
[d
->icode
].operand
[1].mode
)
9595 type
= int_ftype_int_v2sf_v2sf
;
9601 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9606 altivec_init_builtins (void)
9608 const struct builtin_description
*d
;
9609 const struct builtin_description_predicates
*dp
;
9613 tree pfloat_type_node
= build_pointer_type (float_type_node
);
9614 tree pint_type_node
= build_pointer_type (integer_type_node
);
9615 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
9616 tree pchar_type_node
= build_pointer_type (char_type_node
);
9618 tree pvoid_type_node
= build_pointer_type (void_type_node
);
9620 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
9621 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
9622 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
9623 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
9625 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
9627 tree int_ftype_opaque
9628 = build_function_type_list (integer_type_node
,
9629 opaque_V4SI_type_node
, NULL_TREE
);
9631 tree opaque_ftype_opaque_int
9632 = build_function_type_list (opaque_V4SI_type_node
,
9633 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
9634 tree opaque_ftype_opaque_opaque_int
9635 = build_function_type_list (opaque_V4SI_type_node
,
9636 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9637 integer_type_node
, NULL_TREE
);
9638 tree int_ftype_int_opaque_opaque
9639 = build_function_type_list (integer_type_node
,
9640 integer_type_node
, opaque_V4SI_type_node
,
9641 opaque_V4SI_type_node
, NULL_TREE
);
9642 tree int_ftype_int_v4si_v4si
9643 = build_function_type_list (integer_type_node
,
9644 integer_type_node
, V4SI_type_node
,
9645 V4SI_type_node
, NULL_TREE
);
9646 tree v4sf_ftype_pcfloat
9647 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
9648 tree void_ftype_pfloat_v4sf
9649 = build_function_type_list (void_type_node
,
9650 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
9651 tree v4si_ftype_pcint
9652 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
9653 tree void_ftype_pint_v4si
9654 = build_function_type_list (void_type_node
,
9655 pint_type_node
, V4SI_type_node
, NULL_TREE
);
9656 tree v8hi_ftype_pcshort
9657 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
9658 tree void_ftype_pshort_v8hi
9659 = build_function_type_list (void_type_node
,
9660 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
9661 tree v16qi_ftype_pcchar
9662 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
9663 tree void_ftype_pchar_v16qi
9664 = build_function_type_list (void_type_node
,
9665 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
9666 tree void_ftype_v4si
9667 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
9668 tree v8hi_ftype_void
9669 = build_function_type (V8HI_type_node
, void_list_node
);
9670 tree void_ftype_void
9671 = build_function_type (void_type_node
, void_list_node
);
9673 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
9675 tree opaque_ftype_long_pcvoid
9676 = build_function_type_list (opaque_V4SI_type_node
,
9677 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9678 tree v16qi_ftype_long_pcvoid
9679 = build_function_type_list (V16QI_type_node
,
9680 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9681 tree v8hi_ftype_long_pcvoid
9682 = build_function_type_list (V8HI_type_node
,
9683 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9684 tree v4si_ftype_long_pcvoid
9685 = build_function_type_list (V4SI_type_node
,
9686 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9688 tree void_ftype_opaque_long_pvoid
9689 = build_function_type_list (void_type_node
,
9690 opaque_V4SI_type_node
, long_integer_type_node
,
9691 pvoid_type_node
, NULL_TREE
);
9692 tree void_ftype_v4si_long_pvoid
9693 = build_function_type_list (void_type_node
,
9694 V4SI_type_node
, long_integer_type_node
,
9695 pvoid_type_node
, NULL_TREE
);
9696 tree void_ftype_v16qi_long_pvoid
9697 = build_function_type_list (void_type_node
,
9698 V16QI_type_node
, long_integer_type_node
,
9699 pvoid_type_node
, NULL_TREE
);
9700 tree void_ftype_v8hi_long_pvoid
9701 = build_function_type_list (void_type_node
,
9702 V8HI_type_node
, long_integer_type_node
,
9703 pvoid_type_node
, NULL_TREE
);
9704 tree int_ftype_int_v8hi_v8hi
9705 = build_function_type_list (integer_type_node
,
9706 integer_type_node
, V8HI_type_node
,
9707 V8HI_type_node
, NULL_TREE
);
9708 tree int_ftype_int_v16qi_v16qi
9709 = build_function_type_list (integer_type_node
,
9710 integer_type_node
, V16QI_type_node
,
9711 V16QI_type_node
, NULL_TREE
);
9712 tree int_ftype_int_v4sf_v4sf
9713 = build_function_type_list (integer_type_node
,
9714 integer_type_node
, V4SF_type_node
,
9715 V4SF_type_node
, NULL_TREE
);
9716 tree v4si_ftype_v4si
9717 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9718 tree v8hi_ftype_v8hi
9719 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9720 tree v16qi_ftype_v16qi
9721 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9722 tree v4sf_ftype_v4sf
9723 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9724 tree void_ftype_pcvoid_int_int
9725 = build_function_type_list (void_type_node
,
9726 pcvoid_type_node
, integer_type_node
,
9727 integer_type_node
, NULL_TREE
);
9729 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
9730 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
9731 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
9732 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
9733 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
9734 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
9735 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
9736 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
9737 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
9738 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
9739 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
9740 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
9741 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
9742 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
9743 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
9744 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
9745 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
9746 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
9747 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
9748 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
9749 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
9750 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
9751 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
9752 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
9753 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
9754 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
9755 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
9756 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
9757 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
9758 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
9759 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
9760 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
9761 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
9762 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
9763 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
9764 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
9765 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
9766 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
9767 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
9768 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
9769 def_builtin (MASK_ALTIVEC
, "__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
9770 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
9771 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
9772 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
9773 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
9774 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
9776 def_builtin (MASK_ALTIVEC
, "__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
9778 def_builtin (MASK_ALTIVEC
, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
9779 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
9780 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
9781 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
9782 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
9783 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
9784 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
9785 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
9786 def_builtin (MASK_ALTIVEC
, "__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
9787 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
9789 /* Add the DST variants. */
9791 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
9792 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
9794 /* Initialize the predicates. */
9795 dp
= bdesc_altivec_preds
;
9796 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
9798 enum machine_mode mode1
;
9800 bool is_overloaded
= dp
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9801 && dp
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9806 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
9811 type
= int_ftype_int_opaque_opaque
;
9814 type
= int_ftype_int_v4si_v4si
;
9817 type
= int_ftype_int_v8hi_v8hi
;
9820 type
= int_ftype_int_v16qi_v16qi
;
9823 type
= int_ftype_int_v4sf_v4sf
;
9829 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
9832 /* Initialize the abs* operators. */
9834 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
9836 enum machine_mode mode0
;
9839 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9844 type
= v4si_ftype_v4si
;
9847 type
= v8hi_ftype_v8hi
;
9850 type
= v16qi_ftype_v16qi
;
9853 type
= v4sf_ftype_v4sf
;
9859 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9866 /* Initialize target builtin that implements
9867 targetm.vectorize.builtin_mask_for_load. */
9869 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
9870 v16qi_ftype_long_pcvoid
,
9871 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
9872 BUILT_IN_MD
, NULL
, NULL_TREE
);
9873 TREE_READONLY (decl
) = 1;
9874 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9875 altivec_builtin_mask_for_load
= decl
;
9878 /* Access to the vec_init patterns. */
9879 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
9880 integer_type_node
, integer_type_node
,
9881 integer_type_node
, NULL_TREE
);
9882 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4si", ftype
,
9883 ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
9885 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
9886 short_integer_type_node
,
9887 short_integer_type_node
,
9888 short_integer_type_node
,
9889 short_integer_type_node
,
9890 short_integer_type_node
,
9891 short_integer_type_node
,
9892 short_integer_type_node
, NULL_TREE
);
9893 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v8hi", ftype
,
9894 ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
9896 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
9897 char_type_node
, char_type_node
,
9898 char_type_node
, char_type_node
,
9899 char_type_node
, char_type_node
,
9900 char_type_node
, char_type_node
,
9901 char_type_node
, char_type_node
,
9902 char_type_node
, char_type_node
,
9903 char_type_node
, char_type_node
,
9904 char_type_node
, NULL_TREE
);
9905 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v16qi", ftype
,
9906 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
9908 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
9909 float_type_node
, float_type_node
,
9910 float_type_node
, NULL_TREE
);
9911 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4sf", ftype
,
9912 ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
9914 /* Access to the vec_set patterns. */
9915 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
9917 integer_type_node
, NULL_TREE
);
9918 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4si", ftype
,
9919 ALTIVEC_BUILTIN_VEC_SET_V4SI
);
9921 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
9923 integer_type_node
, NULL_TREE
);
9924 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v8hi", ftype
,
9925 ALTIVEC_BUILTIN_VEC_SET_V8HI
);
9927 ftype
= build_function_type_list (V8HI_type_node
, V16QI_type_node
,
9929 integer_type_node
, NULL_TREE
);
9930 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v16qi", ftype
,
9931 ALTIVEC_BUILTIN_VEC_SET_V16QI
);
9933 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
9935 integer_type_node
, NULL_TREE
);
9936 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4sf", ftype
,
9937 ALTIVEC_BUILTIN_VEC_SET_V4SF
);
9939 /* Access to the vec_extract patterns. */
9940 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
9941 integer_type_node
, NULL_TREE
);
9942 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4si", ftype
,
9943 ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
9945 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
9946 integer_type_node
, NULL_TREE
);
9947 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v8hi", ftype
,
9948 ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
9950 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
9951 integer_type_node
, NULL_TREE
);
9952 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v16qi", ftype
,
9953 ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
9955 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
9956 integer_type_node
, NULL_TREE
);
9957 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4sf", ftype
,
9958 ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
9962 rs6000_common_init_builtins (void)
9964 const struct builtin_description
*d
;
9967 tree v2sf_ftype_v2sf_v2sf_v2sf
9968 = build_function_type_list (V2SF_type_node
,
9969 V2SF_type_node
, V2SF_type_node
,
9970 V2SF_type_node
, NULL_TREE
);
9972 tree v4sf_ftype_v4sf_v4sf_v16qi
9973 = build_function_type_list (V4SF_type_node
,
9974 V4SF_type_node
, V4SF_type_node
,
9975 V16QI_type_node
, NULL_TREE
);
9976 tree v4si_ftype_v4si_v4si_v16qi
9977 = build_function_type_list (V4SI_type_node
,
9978 V4SI_type_node
, V4SI_type_node
,
9979 V16QI_type_node
, NULL_TREE
);
9980 tree v8hi_ftype_v8hi_v8hi_v16qi
9981 = build_function_type_list (V8HI_type_node
,
9982 V8HI_type_node
, V8HI_type_node
,
9983 V16QI_type_node
, NULL_TREE
);
9984 tree v16qi_ftype_v16qi_v16qi_v16qi
9985 = build_function_type_list (V16QI_type_node
,
9986 V16QI_type_node
, V16QI_type_node
,
9987 V16QI_type_node
, NULL_TREE
);
9989 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
9991 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
9992 tree v16qi_ftype_int
9993 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
9994 tree v8hi_ftype_v16qi
9995 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
9996 tree v4sf_ftype_v4sf
9997 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9999 tree v2si_ftype_v2si_v2si
10000 = build_function_type_list (opaque_V2SI_type_node
,
10001 opaque_V2SI_type_node
,
10002 opaque_V2SI_type_node
, NULL_TREE
);
10004 tree v2sf_ftype_v2sf_v2sf_spe
10005 = build_function_type_list (opaque_V2SF_type_node
,
10006 opaque_V2SF_type_node
,
10007 opaque_V2SF_type_node
, NULL_TREE
);
10009 tree v2sf_ftype_v2sf_v2sf
10010 = build_function_type_list (V2SF_type_node
,
10012 V2SF_type_node
, NULL_TREE
);
10015 tree v2si_ftype_int_int
10016 = build_function_type_list (opaque_V2SI_type_node
,
10017 integer_type_node
, integer_type_node
,
10020 tree opaque_ftype_opaque
10021 = build_function_type_list (opaque_V4SI_type_node
,
10022 opaque_V4SI_type_node
, NULL_TREE
);
10024 tree v2si_ftype_v2si
10025 = build_function_type_list (opaque_V2SI_type_node
,
10026 opaque_V2SI_type_node
, NULL_TREE
);
10028 tree v2sf_ftype_v2sf_spe
10029 = build_function_type_list (opaque_V2SF_type_node
,
10030 opaque_V2SF_type_node
, NULL_TREE
);
10032 tree v2sf_ftype_v2sf
10033 = build_function_type_list (V2SF_type_node
,
10034 V2SF_type_node
, NULL_TREE
);
10036 tree v2sf_ftype_v2si
10037 = build_function_type_list (opaque_V2SF_type_node
,
10038 opaque_V2SI_type_node
, NULL_TREE
);
10040 tree v2si_ftype_v2sf
10041 = build_function_type_list (opaque_V2SI_type_node
,
10042 opaque_V2SF_type_node
, NULL_TREE
);
10044 tree v2si_ftype_v2si_char
10045 = build_function_type_list (opaque_V2SI_type_node
,
10046 opaque_V2SI_type_node
,
10047 char_type_node
, NULL_TREE
);
10049 tree v2si_ftype_int_char
10050 = build_function_type_list (opaque_V2SI_type_node
,
10051 integer_type_node
, char_type_node
, NULL_TREE
);
10053 tree v2si_ftype_char
10054 = build_function_type_list (opaque_V2SI_type_node
,
10055 char_type_node
, NULL_TREE
);
10057 tree int_ftype_int_int
10058 = build_function_type_list (integer_type_node
,
10059 integer_type_node
, integer_type_node
,
10062 tree opaque_ftype_opaque_opaque
10063 = build_function_type_list (opaque_V4SI_type_node
,
10064 opaque_V4SI_type_node
, opaque_V4SI_type_node
, NULL_TREE
);
10065 tree v4si_ftype_v4si_v4si
10066 = build_function_type_list (V4SI_type_node
,
10067 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10068 tree v4sf_ftype_v4si_int
10069 = build_function_type_list (V4SF_type_node
,
10070 V4SI_type_node
, integer_type_node
, NULL_TREE
);
10071 tree v4si_ftype_v4sf_int
10072 = build_function_type_list (V4SI_type_node
,
10073 V4SF_type_node
, integer_type_node
, NULL_TREE
);
10074 tree v4si_ftype_v4si_int
10075 = build_function_type_list (V4SI_type_node
,
10076 V4SI_type_node
, integer_type_node
, NULL_TREE
);
10077 tree v8hi_ftype_v8hi_int
10078 = build_function_type_list (V8HI_type_node
,
10079 V8HI_type_node
, integer_type_node
, NULL_TREE
);
10080 tree v16qi_ftype_v16qi_int
10081 = build_function_type_list (V16QI_type_node
,
10082 V16QI_type_node
, integer_type_node
, NULL_TREE
);
10083 tree v16qi_ftype_v16qi_v16qi_int
10084 = build_function_type_list (V16QI_type_node
,
10085 V16QI_type_node
, V16QI_type_node
,
10086 integer_type_node
, NULL_TREE
);
10087 tree v8hi_ftype_v8hi_v8hi_int
10088 = build_function_type_list (V8HI_type_node
,
10089 V8HI_type_node
, V8HI_type_node
,
10090 integer_type_node
, NULL_TREE
);
10091 tree v4si_ftype_v4si_v4si_int
10092 = build_function_type_list (V4SI_type_node
,
10093 V4SI_type_node
, V4SI_type_node
,
10094 integer_type_node
, NULL_TREE
);
10095 tree v4sf_ftype_v4sf_v4sf_int
10096 = build_function_type_list (V4SF_type_node
,
10097 V4SF_type_node
, V4SF_type_node
,
10098 integer_type_node
, NULL_TREE
);
10099 tree v4sf_ftype_v4sf_v4sf
10100 = build_function_type_list (V4SF_type_node
,
10101 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10102 tree opaque_ftype_opaque_opaque_opaque
10103 = build_function_type_list (opaque_V4SI_type_node
,
10104 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
10105 opaque_V4SI_type_node
, NULL_TREE
);
10106 tree v4sf_ftype_v4sf_v4sf_v4si
10107 = build_function_type_list (V4SF_type_node
,
10108 V4SF_type_node
, V4SF_type_node
,
10109 V4SI_type_node
, NULL_TREE
);
10110 tree v4sf_ftype_v4sf_v4sf_v4sf
10111 = build_function_type_list (V4SF_type_node
,
10112 V4SF_type_node
, V4SF_type_node
,
10113 V4SF_type_node
, NULL_TREE
);
10114 tree v4si_ftype_v4si_v4si_v4si
10115 = build_function_type_list (V4SI_type_node
,
10116 V4SI_type_node
, V4SI_type_node
,
10117 V4SI_type_node
, NULL_TREE
);
10118 tree v8hi_ftype_v8hi_v8hi
10119 = build_function_type_list (V8HI_type_node
,
10120 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10121 tree v8hi_ftype_v8hi_v8hi_v8hi
10122 = build_function_type_list (V8HI_type_node
,
10123 V8HI_type_node
, V8HI_type_node
,
10124 V8HI_type_node
, NULL_TREE
);
10125 tree v4si_ftype_v8hi_v8hi_v4si
10126 = build_function_type_list (V4SI_type_node
,
10127 V8HI_type_node
, V8HI_type_node
,
10128 V4SI_type_node
, NULL_TREE
);
10129 tree v4si_ftype_v16qi_v16qi_v4si
10130 = build_function_type_list (V4SI_type_node
,
10131 V16QI_type_node
, V16QI_type_node
,
10132 V4SI_type_node
, NULL_TREE
);
10133 tree v16qi_ftype_v16qi_v16qi
10134 = build_function_type_list (V16QI_type_node
,
10135 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10136 tree v4si_ftype_v4sf_v4sf
10137 = build_function_type_list (V4SI_type_node
,
10138 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10139 tree v8hi_ftype_v16qi_v16qi
10140 = build_function_type_list (V8HI_type_node
,
10141 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10142 tree v4si_ftype_v8hi_v8hi
10143 = build_function_type_list (V4SI_type_node
,
10144 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10145 tree v8hi_ftype_v4si_v4si
10146 = build_function_type_list (V8HI_type_node
,
10147 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10148 tree v16qi_ftype_v8hi_v8hi
10149 = build_function_type_list (V16QI_type_node
,
10150 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10151 tree v4si_ftype_v16qi_v4si
10152 = build_function_type_list (V4SI_type_node
,
10153 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
10154 tree v4si_ftype_v16qi_v16qi
10155 = build_function_type_list (V4SI_type_node
,
10156 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10157 tree v4si_ftype_v8hi_v4si
10158 = build_function_type_list (V4SI_type_node
,
10159 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
10160 tree v4si_ftype_v8hi
10161 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
10162 tree int_ftype_v4si_v4si
10163 = build_function_type_list (integer_type_node
,
10164 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10165 tree int_ftype_v4sf_v4sf
10166 = build_function_type_list (integer_type_node
,
10167 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10168 tree int_ftype_v16qi_v16qi
10169 = build_function_type_list (integer_type_node
,
10170 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10171 tree int_ftype_v8hi_v8hi
10172 = build_function_type_list (integer_type_node
,
10173 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10175 /* Add the simple ternary operators. */
10177 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
10179 enum machine_mode mode0
, mode1
, mode2
, mode3
;
10181 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10182 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10193 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10196 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10197 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10198 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10199 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
10202 /* When all four are of the same mode. */
10203 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
10208 type
= opaque_ftype_opaque_opaque_opaque
;
10211 type
= v4si_ftype_v4si_v4si_v4si
;
10214 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
10217 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
10220 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10223 type
= v2sf_ftype_v2sf_v2sf_v2sf
;
10226 gcc_unreachable ();
10229 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
10234 type
= v4si_ftype_v4si_v4si_v16qi
;
10237 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
10240 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
10243 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10246 gcc_unreachable ();
10249 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
10250 && mode3
== V4SImode
)
10251 type
= v4si_ftype_v16qi_v16qi_v4si
;
10252 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
10253 && mode3
== V4SImode
)
10254 type
= v4si_ftype_v8hi_v8hi_v4si
;
10255 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
10256 && mode3
== V4SImode
)
10257 type
= v4sf_ftype_v4sf_v4sf_v4si
;
10259 /* vchar, vchar, vchar, 4-bit literal. */
10260 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
10261 && mode3
== QImode
)
10262 type
= v16qi_ftype_v16qi_v16qi_int
;
10264 /* vshort, vshort, vshort, 4-bit literal. */
10265 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
10266 && mode3
== QImode
)
10267 type
= v8hi_ftype_v8hi_v8hi_int
;
10269 /* vint, vint, vint, 4-bit literal. */
10270 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
10271 && mode3
== QImode
)
10272 type
= v4si_ftype_v4si_v4si_int
;
10274 /* vfloat, vfloat, vfloat, 4-bit literal. */
10275 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
10276 && mode3
== QImode
)
10277 type
= v4sf_ftype_v4sf_v4sf_int
;
10280 gcc_unreachable ();
10282 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10285 /* Add the simple binary operators. */
10286 d
= (struct builtin_description
*) bdesc_2arg
;
10287 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
10289 enum machine_mode mode0
, mode1
, mode2
;
10291 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10292 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10302 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10305 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10306 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10307 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10310 /* When all three operands are of the same mode. */
10311 if (mode0
== mode1
&& mode1
== mode2
)
10316 type
= opaque_ftype_opaque_opaque
;
10319 type
= v4sf_ftype_v4sf_v4sf
;
10322 type
= v4si_ftype_v4si_v4si
;
10325 type
= v16qi_ftype_v16qi_v16qi
;
10328 type
= v8hi_ftype_v8hi_v8hi
;
10331 type
= v2si_ftype_v2si_v2si
;
10334 if (TARGET_PAIRED_FLOAT
)
10335 type
= v2sf_ftype_v2sf_v2sf
;
10337 type
= v2sf_ftype_v2sf_v2sf_spe
;
10340 type
= int_ftype_int_int
;
10343 gcc_unreachable ();
10347 /* A few other combos we really don't want to do manually. */
10349 /* vint, vfloat, vfloat. */
10350 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
10351 type
= v4si_ftype_v4sf_v4sf
;
10353 /* vshort, vchar, vchar. */
10354 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10355 type
= v8hi_ftype_v16qi_v16qi
;
10357 /* vint, vshort, vshort. */
10358 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10359 type
= v4si_ftype_v8hi_v8hi
;
10361 /* vshort, vint, vint. */
10362 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
10363 type
= v8hi_ftype_v4si_v4si
;
10365 /* vchar, vshort, vshort. */
10366 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10367 type
= v16qi_ftype_v8hi_v8hi
;
10369 /* vint, vchar, vint. */
10370 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
10371 type
= v4si_ftype_v16qi_v4si
;
10373 /* vint, vchar, vchar. */
10374 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10375 type
= v4si_ftype_v16qi_v16qi
;
10377 /* vint, vshort, vint. */
10378 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
10379 type
= v4si_ftype_v8hi_v4si
;
10381 /* vint, vint, 5-bit literal. */
10382 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
10383 type
= v4si_ftype_v4si_int
;
10385 /* vshort, vshort, 5-bit literal. */
10386 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
10387 type
= v8hi_ftype_v8hi_int
;
10389 /* vchar, vchar, 5-bit literal. */
10390 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
10391 type
= v16qi_ftype_v16qi_int
;
10393 /* vfloat, vint, 5-bit literal. */
10394 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
10395 type
= v4sf_ftype_v4si_int
;
10397 /* vint, vfloat, 5-bit literal. */
10398 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
10399 type
= v4si_ftype_v4sf_int
;
10401 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
10402 type
= v2si_ftype_int_int
;
10404 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
10405 type
= v2si_ftype_v2si_char
;
10407 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
10408 type
= v2si_ftype_int_char
;
10413 gcc_assert (mode0
== SImode
);
10417 type
= int_ftype_v4si_v4si
;
10420 type
= int_ftype_v4sf_v4sf
;
10423 type
= int_ftype_v16qi_v16qi
;
10426 type
= int_ftype_v8hi_v8hi
;
10429 gcc_unreachable ();
10433 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10436 /* Add the simple unary operators. */
10437 d
= (struct builtin_description
*) bdesc_1arg
;
10438 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
10440 enum machine_mode mode0
, mode1
;
10442 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10443 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10452 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10455 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10456 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10459 if (mode0
== V4SImode
&& mode1
== QImode
)
10460 type
= v4si_ftype_int
;
10461 else if (mode0
== V8HImode
&& mode1
== QImode
)
10462 type
= v8hi_ftype_int
;
10463 else if (mode0
== V16QImode
&& mode1
== QImode
)
10464 type
= v16qi_ftype_int
;
10465 else if (mode0
== VOIDmode
&& mode1
== VOIDmode
)
10466 type
= opaque_ftype_opaque
;
10467 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
10468 type
= v4sf_ftype_v4sf
;
10469 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
10470 type
= v8hi_ftype_v16qi
;
10471 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
10472 type
= v4si_ftype_v8hi
;
10473 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
10474 type
= v2si_ftype_v2si
;
10475 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
10477 if (TARGET_PAIRED_FLOAT
)
10478 type
= v2sf_ftype_v2sf
;
10480 type
= v2sf_ftype_v2sf_spe
;
10482 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
10483 type
= v2sf_ftype_v2si
;
10484 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
10485 type
= v2si_ftype_v2sf
;
10486 else if (mode0
== V2SImode
&& mode1
== QImode
)
10487 type
= v2si_ftype_char
;
10489 gcc_unreachable ();
10491 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10496 rs6000_init_libfuncs (void)
10498 if (DEFAULT_ABI
!= ABI_V4
&& TARGET_XCOFF
10499 && !TARGET_POWER2
&& !TARGET_POWERPC
)
10501 /* AIX library routines for float->int conversion. */
10502 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
10503 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
10504 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
10505 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
10508 if (!TARGET_IEEEQUAD
)
10509 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10510 if (!TARGET_XL_COMPAT
)
10512 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
10513 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
10514 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
10515 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
10517 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
10519 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
10520 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
10521 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
10522 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
10523 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
10524 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
10525 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
10527 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
10528 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
10529 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
10530 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
10531 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
10532 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
10533 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
10534 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
10537 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
10538 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
10542 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
10543 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
10544 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
10545 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
10549 /* 32-bit SVR4 quad floating point routines. */
10551 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
10552 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
10553 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
10554 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
10555 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
10556 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
10557 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
10559 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
10560 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
10561 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
10562 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
10563 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
10564 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
10566 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
10567 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
10568 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
10569 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
10570 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
10571 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
10572 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
10573 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
10578 /* Expand a block clear operation, and return 1 if successful. Return 0
10579 if we should let the compiler generate normal code.
10581 operands[0] is the destination
10582 operands[1] is the length
10583 operands[3] is the alignment */
10586 expand_block_clear (rtx operands
[])
10588 rtx orig_dest
= operands
[0];
10589 rtx bytes_rtx
= operands
[1];
10590 rtx align_rtx
= operands
[3];
10591 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10592 HOST_WIDE_INT align
;
10593 HOST_WIDE_INT bytes
;
10598 /* If this is not a fixed size move, just call memcpy */
10602 /* This must be a fixed size alignment */
10603 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10604 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10606 /* Anything to clear? */
10607 bytes
= INTVAL (bytes_rtx
);
10611 /* Use the builtin memset after a point, to avoid huge code bloat.
10612 When optimize_size, avoid any significant code bloat; calling
10613 memset is about 4 instructions, so allow for one instruction to
10614 load zero and three to do clearing. */
10615 if (TARGET_ALTIVEC
&& align
>= 128)
10617 else if (TARGET_POWERPC64
&& align
>= 32)
10619 else if (TARGET_SPE
&& align
>= 64)
10624 if (optimize_size
&& bytes
> 3 * clear_step
)
10626 if (! optimize_size
&& bytes
> 8 * clear_step
)
10629 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
10631 enum machine_mode mode
= BLKmode
;
10634 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
10639 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
10644 else if (bytes
>= 8 && TARGET_POWERPC64
10645 /* 64-bit loads and stores require word-aligned
10647 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10652 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10653 { /* move 4 bytes */
10657 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10658 { /* move 2 bytes */
10662 else /* move 1 byte at a time */
10668 dest
= adjust_address (orig_dest
, mode
, offset
);
10670 emit_move_insn (dest
, CONST0_RTX (mode
));
10677 /* Expand a block move operation, and return 1 if successful. Return 0
10678 if we should let the compiler generate normal code.
10680 operands[0] is the destination
10681 operands[1] is the source
10682 operands[2] is the length
10683 operands[3] is the alignment */
10685 #define MAX_MOVE_REG 4
10688 expand_block_move (rtx operands
[])
10690 rtx orig_dest
= operands
[0];
10691 rtx orig_src
= operands
[1];
10692 rtx bytes_rtx
= operands
[2];
10693 rtx align_rtx
= operands
[3];
10694 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10699 rtx stores
[MAX_MOVE_REG
];
10702 /* If this is not a fixed size move, just call memcpy */
10706 /* This must be a fixed size alignment */
10707 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10708 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10710 /* Anything to move? */
10711 bytes
= INTVAL (bytes_rtx
);
10715 /* store_one_arg depends on expand_block_move to handle at least the size of
10716 reg_parm_stack_space. */
10717 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
10720 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
10723 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
10724 rtx (*mov
) (rtx
, rtx
);
10726 enum machine_mode mode
= BLKmode
;
10729 /* Altivec first, since it will be faster than a string move
10730 when it applies, and usually not significantly larger. */
10731 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
10735 gen_func
.mov
= gen_movv4si
;
10737 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
10741 gen_func
.mov
= gen_movv2si
;
10743 else if (TARGET_STRING
10744 && bytes
> 24 /* move up to 32 bytes at a time */
10750 && ! fixed_regs
[10]
10751 && ! fixed_regs
[11]
10752 && ! fixed_regs
[12])
10754 move_bytes
= (bytes
> 32) ? 32 : bytes
;
10755 gen_func
.movmemsi
= gen_movmemsi_8reg
;
10757 else if (TARGET_STRING
10758 && bytes
> 16 /* move up to 24 bytes at a time */
10764 && ! fixed_regs
[10])
10766 move_bytes
= (bytes
> 24) ? 24 : bytes
;
10767 gen_func
.movmemsi
= gen_movmemsi_6reg
;
10769 else if (TARGET_STRING
10770 && bytes
> 8 /* move up to 16 bytes at a time */
10774 && ! fixed_regs
[8])
10776 move_bytes
= (bytes
> 16) ? 16 : bytes
;
10777 gen_func
.movmemsi
= gen_movmemsi_4reg
;
10779 else if (bytes
>= 8 && TARGET_POWERPC64
10780 /* 64-bit loads and stores require word-aligned
10782 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10786 gen_func
.mov
= gen_movdi
;
10788 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
10789 { /* move up to 8 bytes at a time */
10790 move_bytes
= (bytes
> 8) ? 8 : bytes
;
10791 gen_func
.movmemsi
= gen_movmemsi_2reg
;
10793 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10794 { /* move 4 bytes */
10797 gen_func
.mov
= gen_movsi
;
10799 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10800 { /* move 2 bytes */
10803 gen_func
.mov
= gen_movhi
;
10805 else if (TARGET_STRING
&& bytes
> 1)
10806 { /* move up to 4 bytes at a time */
10807 move_bytes
= (bytes
> 4) ? 4 : bytes
;
10808 gen_func
.movmemsi
= gen_movmemsi_1reg
;
10810 else /* move 1 byte at a time */
10814 gen_func
.mov
= gen_movqi
;
10817 src
= adjust_address (orig_src
, mode
, offset
);
10818 dest
= adjust_address (orig_dest
, mode
, offset
);
10820 if (mode
!= BLKmode
)
10822 rtx tmp_reg
= gen_reg_rtx (mode
);
10824 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
10825 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
10828 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
10831 for (i
= 0; i
< num_reg
; i
++)
10832 emit_insn (stores
[i
]);
10836 if (mode
== BLKmode
)
10838 /* Move the address into scratch registers. The movmemsi
10839 patterns require zero offset. */
10840 if (!REG_P (XEXP (src
, 0)))
10842 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
10843 src
= replace_equiv_address (src
, src_reg
);
10845 set_mem_size (src
, GEN_INT (move_bytes
));
10847 if (!REG_P (XEXP (dest
, 0)))
10849 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
10850 dest
= replace_equiv_address (dest
, dest_reg
);
10852 set_mem_size (dest
, GEN_INT (move_bytes
));
10854 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
10855 GEN_INT (move_bytes
& 31),
10864 /* Return a string to perform a load_multiple operation.
10865 operands[0] is the vector.
10866 operands[1] is the source address.
10867 operands[2] is the first destination register. */
10870 rs6000_output_load_multiple (rtx operands
[3])
10872 /* We have to handle the case where the pseudo used to contain the address
10873 is assigned to one of the output registers. */
10875 int words
= XVECLEN (operands
[0], 0);
10878 if (XVECLEN (operands
[0], 0) == 1)
10879 return "{l|lwz} %2,0(%1)";
10881 for (i
= 0; i
< words
; i
++)
10882 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
10883 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
10887 xop
[0] = GEN_INT (4 * (words
-1));
10888 xop
[1] = operands
[1];
10889 xop
[2] = operands
[2];
10890 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
10895 xop
[0] = GEN_INT (4 * (words
-1));
10896 xop
[1] = operands
[1];
10897 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10898 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
10903 for (j
= 0; j
< words
; j
++)
10906 xop
[0] = GEN_INT (j
* 4);
10907 xop
[1] = operands
[1];
10908 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
10909 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
10911 xop
[0] = GEN_INT (i
* 4);
10912 xop
[1] = operands
[1];
10913 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
10918 return "{lsi|lswi} %2,%1,%N0";
10922 /* A validation routine: say whether CODE, a condition code, and MODE
10923 match. The other alternatives either don't make sense or should
10924 never be generated. */
10927 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
10929 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
10930 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
10931 && GET_MODE_CLASS (mode
) == MODE_CC
);
10933 /* These don't make sense. */
10934 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
10935 || mode
!= CCUNSmode
);
10937 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
10938 || mode
== CCUNSmode
);
10940 gcc_assert (mode
== CCFPmode
10941 || (code
!= ORDERED
&& code
!= UNORDERED
10942 && code
!= UNEQ
&& code
!= LTGT
10943 && code
!= UNGT
&& code
!= UNLT
10944 && code
!= UNGE
&& code
!= UNLE
));
10946 /* These should never be generated except for
10947 flag_finite_math_only. */
10948 gcc_assert (mode
!= CCFPmode
10949 || flag_finite_math_only
10950 || (code
!= LE
&& code
!= GE
10951 && code
!= UNEQ
&& code
!= LTGT
10952 && code
!= UNGT
&& code
!= UNLT
));
10954 /* These are invalid; the information is not there. */
10955 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
10959 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10960 mask required to convert the result of a rotate insn into a shift
10961 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10964 includes_lshift_p (rtx shiftop
, rtx andop
)
10966 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10968 shift_mask
<<= INTVAL (shiftop
);
10970 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10973 /* Similar, but for right shift. */
10976 includes_rshift_p (rtx shiftop
, rtx andop
)
10978 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10980 shift_mask
>>= INTVAL (shiftop
);
10982 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10985 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10986 to perform a left shift. It must have exactly SHIFTOP least
10987 significant 0's, then one or more 1's, then zero or more 0's. */
10990 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
10992 if (GET_CODE (andop
) == CONST_INT
)
10994 HOST_WIDE_INT c
, lsb
, shift_mask
;
10996 c
= INTVAL (andop
);
10997 if (c
== 0 || c
== ~0)
11001 shift_mask
<<= INTVAL (shiftop
);
11003 /* Find the least significant one bit. */
11006 /* It must coincide with the LSB of the shift mask. */
11007 if (-lsb
!= shift_mask
)
11010 /* Invert to look for the next transition (if any). */
11013 /* Remove the low group of ones (originally low group of zeros). */
11016 /* Again find the lsb, and check we have all 1's above. */
11020 else if (GET_CODE (andop
) == CONST_DOUBLE
11021 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
11023 HOST_WIDE_INT low
, high
, lsb
;
11024 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
11026 low
= CONST_DOUBLE_LOW (andop
);
11027 if (HOST_BITS_PER_WIDE_INT
< 64)
11028 high
= CONST_DOUBLE_HIGH (andop
);
11030 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
11031 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
11034 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
11036 shift_mask_high
= ~0;
11037 if (INTVAL (shiftop
) > 32)
11038 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11040 lsb
= high
& -high
;
11042 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
11048 lsb
= high
& -high
;
11049 return high
== -lsb
;
11052 shift_mask_low
= ~0;
11053 shift_mask_low
<<= INTVAL (shiftop
);
11057 if (-lsb
!= shift_mask_low
)
11060 if (HOST_BITS_PER_WIDE_INT
< 64)
11065 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
11067 lsb
= high
& -high
;
11068 return high
== -lsb
;
11072 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
11078 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
11079 to perform a left shift. It must have SHIFTOP or more least
11080 significant 0's, with the remainder of the word 1's. */
11083 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
11085 if (GET_CODE (andop
) == CONST_INT
)
11087 HOST_WIDE_INT c
, lsb
, shift_mask
;
11090 shift_mask
<<= INTVAL (shiftop
);
11091 c
= INTVAL (andop
);
11093 /* Find the least significant one bit. */
11096 /* It must be covered by the shift mask.
11097 This test also rejects c == 0. */
11098 if ((lsb
& shift_mask
) == 0)
11101 /* Check we have all 1's above the transition, and reject all 1's. */
11102 return c
== -lsb
&& lsb
!= 1;
11104 else if (GET_CODE (andop
) == CONST_DOUBLE
11105 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
11107 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
11109 low
= CONST_DOUBLE_LOW (andop
);
11111 if (HOST_BITS_PER_WIDE_INT
< 64)
11113 HOST_WIDE_INT high
, shift_mask_high
;
11115 high
= CONST_DOUBLE_HIGH (andop
);
11119 shift_mask_high
= ~0;
11120 if (INTVAL (shiftop
) > 32)
11121 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11123 lsb
= high
& -high
;
11125 if ((lsb
& shift_mask_high
) == 0)
11128 return high
== -lsb
;
11134 shift_mask_low
= ~0;
11135 shift_mask_low
<<= INTVAL (shiftop
);
11139 if ((lsb
& shift_mask_low
) == 0)
11142 return low
== -lsb
&& lsb
!= 1;
11148 /* Return 1 if operands will generate a valid arguments to rlwimi
11149 instruction for insert with right shift in 64-bit mode. The mask may
11150 not start on the first bit or stop on the last bit because wrap-around
11151 effects of instruction do not correspond to semantics of RTL insn. */
11154 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
11156 if (INTVAL (startop
) > 32
11157 && INTVAL (startop
) < 64
11158 && INTVAL (sizeop
) > 1
11159 && INTVAL (sizeop
) + INTVAL (startop
) < 64
11160 && INTVAL (shiftop
) > 0
11161 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
11162 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
11168 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11169 for lfq and stfq insns iff the registers are hard registers. */
11172 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
11174 /* We might have been passed a SUBREG. */
11175 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
11178 /* We might have been passed non floating point registers. */
11179 if (!FP_REGNO_P (REGNO (reg1
))
11180 || !FP_REGNO_P (REGNO (reg2
)))
11183 return (REGNO (reg1
) == REGNO (reg2
) - 1);
11186 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11187 addr1 and addr2 must be in consecutive memory locations
11188 (addr2 == addr1 + 8). */
11191 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
11194 unsigned int reg1
, reg2
;
11195 int offset1
, offset2
;
11197 /* The mems cannot be volatile. */
11198 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
11201 addr1
= XEXP (mem1
, 0);
11202 addr2
= XEXP (mem2
, 0);
11204 /* Extract an offset (if used) from the first addr. */
11205 if (GET_CODE (addr1
) == PLUS
)
11207 /* If not a REG, return zero. */
11208 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
11212 reg1
= REGNO (XEXP (addr1
, 0));
11213 /* The offset must be constant! */
11214 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
11216 offset1
= INTVAL (XEXP (addr1
, 1));
11219 else if (GET_CODE (addr1
) != REG
)
11223 reg1
= REGNO (addr1
);
11224 /* This was a simple (mem (reg)) expression. Offset is 0. */
11228 /* And now for the second addr. */
11229 if (GET_CODE (addr2
) == PLUS
)
11231 /* If not a REG, return zero. */
11232 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
11236 reg2
= REGNO (XEXP (addr2
, 0));
11237 /* The offset must be constant. */
11238 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
11240 offset2
= INTVAL (XEXP (addr2
, 1));
11243 else if (GET_CODE (addr2
) != REG
)
11247 reg2
= REGNO (addr2
);
11248 /* This was a simple (mem (reg)) expression. Offset is 0. */
11252 /* Both of these must have the same base register. */
11256 /* The offset for the second addr must be 8 more than the first addr. */
11257 if (offset2
!= offset1
+ 8)
11260 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11267 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
11269 static bool eliminated
= false;
11270 if (mode
!= SDmode
)
11271 return assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
11274 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
11275 gcc_assert (mem
!= NULL_RTX
);
11279 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
11280 cfun
->machine
->sdmode_stack_slot
= mem
;
11288 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
11290 /* Don't walk into types. */
11291 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
11293 *walk_subtrees
= 0;
11297 switch (TREE_CODE (*tp
))
11305 case ALIGN_INDIRECT_REF
:
11306 case MISALIGNED_INDIRECT_REF
:
11307 case VIEW_CONVERT_EXPR
:
11308 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
11319 /* Allocate a 64-bit stack slot to be used for copying SDmode
11320 values through if this function has any SDmode references. */
11323 rs6000_alloc_sdmode_stack_slot (void)
11327 gimple_stmt_iterator gsi
;
11329 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
11332 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
11334 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
11337 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11338 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11344 /* Check for any SDmode parameters of the function. */
11345 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= TREE_CHAIN (t
))
11347 if (TREE_TYPE (t
) == error_mark_node
)
11350 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
11351 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
11353 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11354 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11362 rs6000_instantiate_decls (void)
11364 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
11365 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
11368 /* Return the register class of a scratch register needed to copy IN into
11369 or out of a register in CLASS in MODE. If it can be done directly,
11370 NO_REGS is returned. */
11373 rs6000_secondary_reload_class (enum reg_class
class,
11374 enum machine_mode mode ATTRIBUTE_UNUSED
,
11379 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
11381 && MACHOPIC_INDIRECT
11385 /* We cannot copy a symbolic operand directly into anything
11386 other than BASE_REGS for TARGET_ELF. So indicate that a
11387 register from BASE_REGS is needed as an intermediate
11390 On Darwin, pic addresses require a load from memory, which
11391 needs a base register. */
11392 if (class != BASE_REGS
11393 && (GET_CODE (in
) == SYMBOL_REF
11394 || GET_CODE (in
) == HIGH
11395 || GET_CODE (in
) == LABEL_REF
11396 || GET_CODE (in
) == CONST
))
11400 if (GET_CODE (in
) == REG
)
11402 regno
= REGNO (in
);
11403 if (regno
>= FIRST_PSEUDO_REGISTER
)
11405 regno
= true_regnum (in
);
11406 if (regno
>= FIRST_PSEUDO_REGISTER
)
11410 else if (GET_CODE (in
) == SUBREG
)
11412 regno
= true_regnum (in
);
11413 if (regno
>= FIRST_PSEUDO_REGISTER
)
11419 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11421 if (class == GENERAL_REGS
|| class == BASE_REGS
11422 || (regno
>= 0 && INT_REGNO_P (regno
)))
11425 /* Constants, memory, and FP registers can go into FP registers. */
11426 if ((regno
== -1 || FP_REGNO_P (regno
))
11427 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
11428 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
11430 /* Memory, and AltiVec registers can go into AltiVec registers. */
11431 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
11432 && class == ALTIVEC_REGS
)
11435 /* We can copy among the CR registers. */
11436 if ((class == CR_REGS
|| class == CR0_REGS
)
11437 && regno
>= 0 && CR_REGNO_P (regno
))
11440 /* Otherwise, we need GENERAL_REGS. */
11441 return GENERAL_REGS
;
11444 /* Given a comparison operation, return the bit number in CCR to test. We
11445 know this is a valid comparison.
11447 SCC_P is 1 if this is for an scc. That means that %D will have been
11448 used instead of %C, so the bits will be in different places.
11450 Return -1 if OP isn't a valid comparison for some reason. */
11453 ccr_bit (rtx op
, int scc_p
)
11455 enum rtx_code code
= GET_CODE (op
);
11456 enum machine_mode cc_mode
;
11461 if (!COMPARISON_P (op
))
11464 reg
= XEXP (op
, 0);
11466 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
11468 cc_mode
= GET_MODE (reg
);
11469 cc_regnum
= REGNO (reg
);
11470 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
11472 validate_condition_mode (code
, cc_mode
);
11474 /* When generating a sCOND operation, only positive conditions are
11477 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
11478 || code
== GTU
|| code
== LTU
);
11483 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
11485 return base_bit
+ 2;
11486 case GT
: case GTU
: case UNLE
:
11487 return base_bit
+ 1;
11488 case LT
: case LTU
: case UNGE
:
11490 case ORDERED
: case UNORDERED
:
11491 return base_bit
+ 3;
11494 /* If scc, we will have done a cror to put the bit in the
11495 unordered position. So test that bit. For integer, this is ! LT
11496 unless this is an scc insn. */
11497 return scc_p
? base_bit
+ 3 : base_bit
;
11500 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
11503 gcc_unreachable ();
11507 /* Return the GOT register. */
11510 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
11512 /* The second flow pass currently (June 1999) can't update
11513 regs_ever_live without disturbing other parts of the compiler, so
11514 update it here to make the prolog/epilogue code happy. */
11515 if (!can_create_pseudo_p ()
11516 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
11517 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
11519 crtl
->uses_pic_offset_table
= 1;
11521 return pic_offset_table_rtx
;
11524 /* Function to init struct machine_function.
11525 This will be called, via a pointer variable,
11526 from push_function_context. */
11528 static struct machine_function
*
11529 rs6000_init_machine_status (void)
11531 return GGC_CNEW (machine_function
);
11534 /* These macros test for integers and extract the low-order bits. */
11536 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11537 && GET_MODE (X) == VOIDmode)
11539 #define INT_LOWPART(X) \
11540 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11543 extract_MB (rtx op
)
11546 unsigned long val
= INT_LOWPART (op
);
11548 /* If the high bit is zero, the value is the first 1 bit we find
11550 if ((val
& 0x80000000) == 0)
11552 gcc_assert (val
& 0xffffffff);
11555 while (((val
<<= 1) & 0x80000000) == 0)
11560 /* If the high bit is set and the low bit is not, or the mask is all
11561 1's, the value is zero. */
11562 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
11565 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11568 while (((val
>>= 1) & 1) != 0)
11575 extract_ME (rtx op
)
11578 unsigned long val
= INT_LOWPART (op
);
11580 /* If the low bit is zero, the value is the first 1 bit we find from
11582 if ((val
& 1) == 0)
11584 gcc_assert (val
& 0xffffffff);
11587 while (((val
>>= 1) & 1) == 0)
11593 /* If the low bit is set and the high bit is not, or the mask is all
11594 1's, the value is 31. */
11595 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
11598 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11601 while (((val
<<= 1) & 0x80000000) != 0)
11607 /* Locate some local-dynamic symbol still in use by this function
11608 so that we can print its name in some tls_ld pattern. */
11610 static const char *
11611 rs6000_get_some_local_dynamic_name (void)
11615 if (cfun
->machine
->some_ld_name
)
11616 return cfun
->machine
->some_ld_name
;
11618 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11620 && for_each_rtx (&PATTERN (insn
),
11621 rs6000_get_some_local_dynamic_name_1
, 0))
11622 return cfun
->machine
->some_ld_name
;
11624 gcc_unreachable ();
11627 /* Helper function for rs6000_get_some_local_dynamic_name. */
11630 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11634 if (GET_CODE (x
) == SYMBOL_REF
)
11636 const char *str
= XSTR (x
, 0);
11637 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11639 cfun
->machine
->some_ld_name
= str
;
11647 /* Write out a function code label. */
11650 rs6000_output_function_entry (FILE *file
, const char *fname
)
11652 if (fname
[0] != '.')
11654 switch (DEFAULT_ABI
)
11657 gcc_unreachable ();
11663 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
11672 RS6000_OUTPUT_BASENAME (file
, fname
);
11674 assemble_name (file
, fname
);
11677 /* Print an operand. Recognize special options, documented below. */
11680 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11681 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11683 #define SMALL_DATA_RELOC "sda21"
11684 #define SMALL_DATA_REG 0
11688 print_operand (FILE *file
, rtx x
, int code
)
11692 unsigned HOST_WIDE_INT uval
;
11697 /* Write out an instruction after the call which may be replaced
11698 with glue code by the loader. This depends on the AIX version. */
11699 asm_fprintf (file
, RS6000_CALL_GLUE
);
11702 /* %a is output_address. */
11705 /* If X is a constant integer whose low-order 5 bits are zero,
11706 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11707 in the AIX assembler where "sri" with a zero shift count
11708 writes a trash instruction. */
11709 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
11716 /* If constant, low-order 16 bits of constant, unsigned.
11717 Otherwise, write normally. */
11719 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
11721 print_operand (file
, x
, 0);
11725 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11726 for 64-bit mask direction. */
11727 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
11730 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11734 /* X is a CR register. Print the number of the GT bit of the CR. */
11735 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11736 output_operand_lossage ("invalid %%E value");
11738 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
11742 /* Like 'J' but get to the GT bit only. */
11743 gcc_assert (GET_CODE (x
) == REG
);
11745 /* Bit 1 is GT bit. */
11746 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
11748 /* Add one for shift count in rlinm for scc. */
11749 fprintf (file
, "%d", i
+ 1);
11753 /* X is a CR register. Print the number of the EQ bit of the CR */
11754 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11755 output_operand_lossage ("invalid %%E value");
11757 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
11761 /* X is a CR register. Print the shift count needed to move it
11762 to the high-order four bits. */
11763 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11764 output_operand_lossage ("invalid %%f value");
11766 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
11770 /* Similar, but print the count for the rotate in the opposite
11772 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11773 output_operand_lossage ("invalid %%F value");
11775 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
11779 /* X is a constant integer. If it is negative, print "m",
11780 otherwise print "z". This is to make an aze or ame insn. */
11781 if (GET_CODE (x
) != CONST_INT
)
11782 output_operand_lossage ("invalid %%G value");
11783 else if (INTVAL (x
) >= 0)
11790 /* If constant, output low-order five bits. Otherwise, write
11793 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
11795 print_operand (file
, x
, 0);
11799 /* If constant, output low-order six bits. Otherwise, write
11802 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
11804 print_operand (file
, x
, 0);
11808 /* Print `i' if this is a constant, else nothing. */
11814 /* Write the bit number in CCR for jump. */
11815 i
= ccr_bit (x
, 0);
11817 output_operand_lossage ("invalid %%j code");
11819 fprintf (file
, "%d", i
);
11823 /* Similar, but add one for shift count in rlinm for scc and pass
11824 scc flag to `ccr_bit'. */
11825 i
= ccr_bit (x
, 1);
11827 output_operand_lossage ("invalid %%J code");
11829 /* If we want bit 31, write a shift count of zero, not 32. */
11830 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
11834 /* X must be a constant. Write the 1's complement of the
11837 output_operand_lossage ("invalid %%k value");
11839 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
11843 /* X must be a symbolic constant on ELF. Write an
11844 expression suitable for an 'addi' that adds in the low 16
11845 bits of the MEM. */
11846 if (GET_CODE (x
) != CONST
)
11848 print_operand_address (file
, x
);
11849 fputs ("@l", file
);
11853 if (GET_CODE (XEXP (x
, 0)) != PLUS
11854 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
11855 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
11856 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
11857 output_operand_lossage ("invalid %%K value");
11858 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
11859 fputs ("@l", file
);
11860 /* For GNU as, there must be a non-alphanumeric character
11861 between 'l' and the number. The '-' is added by
11862 print_operand() already. */
11863 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
11865 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
11869 /* %l is output_asm_label. */
11872 /* Write second word of DImode or DFmode reference. Works on register
11873 or non-indexed memory only. */
11874 if (GET_CODE (x
) == REG
)
11875 fputs (reg_names
[REGNO (x
) + 1], file
);
11876 else if (GET_CODE (x
) == MEM
)
11878 /* Handle possible auto-increment. Since it is pre-increment and
11879 we have already done it, we can just use an offset of word. */
11880 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11881 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11882 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11884 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11885 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11888 output_address (XEXP (adjust_address_nv (x
, SImode
,
11892 if (small_data_operand (x
, GET_MODE (x
)))
11893 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11894 reg_names
[SMALL_DATA_REG
]);
11899 /* MB value for a mask operand. */
11900 if (! mask_operand (x
, SImode
))
11901 output_operand_lossage ("invalid %%m value");
11903 fprintf (file
, "%d", extract_MB (x
));
11907 /* ME value for a mask operand. */
11908 if (! mask_operand (x
, SImode
))
11909 output_operand_lossage ("invalid %%M value");
11911 fprintf (file
, "%d", extract_ME (x
));
11914 /* %n outputs the negative of its operand. */
11917 /* Write the number of elements in the vector times 4. */
11918 if (GET_CODE (x
) != PARALLEL
)
11919 output_operand_lossage ("invalid %%N value");
11921 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
11925 /* Similar, but subtract 1 first. */
11926 if (GET_CODE (x
) != PARALLEL
)
11927 output_operand_lossage ("invalid %%O value");
11929 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
11933 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11935 || INT_LOWPART (x
) < 0
11936 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
11937 output_operand_lossage ("invalid %%p value");
11939 fprintf (file
, "%d", i
);
11943 /* The operand must be an indirect memory reference. The result
11944 is the register name. */
11945 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
11946 || REGNO (XEXP (x
, 0)) >= 32)
11947 output_operand_lossage ("invalid %%P value");
11949 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
11953 /* This outputs the logical code corresponding to a boolean
11954 expression. The expression may have one or both operands
11955 negated (if one, only the first one). For condition register
11956 logical operations, it will also treat the negated
11957 CR codes as NOTs, but not handle NOTs of them. */
11959 const char *const *t
= 0;
11961 enum rtx_code code
= GET_CODE (x
);
11962 static const char * const tbl
[3][3] = {
11963 { "and", "andc", "nor" },
11964 { "or", "orc", "nand" },
11965 { "xor", "eqv", "xor" } };
11969 else if (code
== IOR
)
11971 else if (code
== XOR
)
11974 output_operand_lossage ("invalid %%q value");
11976 if (GET_CODE (XEXP (x
, 0)) != NOT
)
11980 if (GET_CODE (XEXP (x
, 1)) == NOT
)
11998 /* X is a CR register. Print the mask for `mtcrf'. */
11999 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
12000 output_operand_lossage ("invalid %%R value");
12002 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
12006 /* Low 5 bits of 32 - value */
12008 output_operand_lossage ("invalid %%s value");
12010 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
12014 /* PowerPC64 mask position. All 0's is excluded.
12015 CONST_INT 32-bit mask is considered sign-extended so any
12016 transition must occur within the CONST_INT, not on the boundary. */
12017 if (! mask64_operand (x
, DImode
))
12018 output_operand_lossage ("invalid %%S value");
12020 uval
= INT_LOWPART (x
);
12022 if (uval
& 1) /* Clear Left */
12024 #if HOST_BITS_PER_WIDE_INT > 64
12025 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
12029 else /* Clear Right */
12032 #if HOST_BITS_PER_WIDE_INT > 64
12033 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
12039 gcc_assert (i
>= 0);
12040 fprintf (file
, "%d", i
);
12044 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
12045 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
12047 /* Bit 3 is OV bit. */
12048 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
12050 /* If we want bit 31, write a shift count of zero, not 32. */
12051 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
12055 /* Print the symbolic name of a branch target register. */
12056 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
12057 && REGNO (x
) != CTR_REGNO
))
12058 output_operand_lossage ("invalid %%T value");
12059 else if (REGNO (x
) == LR_REGNO
)
12060 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
12062 fputs ("ctr", file
);
12066 /* High-order 16 bits of constant for use in unsigned operand. */
12068 output_operand_lossage ("invalid %%u value");
12070 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
12071 (INT_LOWPART (x
) >> 16) & 0xffff);
12075 /* High-order 16 bits of constant for use in signed operand. */
12077 output_operand_lossage ("invalid %%v value");
12079 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
12080 (INT_LOWPART (x
) >> 16) & 0xffff);
12084 /* Print `u' if this has an auto-increment or auto-decrement. */
12085 if (GET_CODE (x
) == MEM
12086 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
12087 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
12088 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
12093 /* Print the trap code for this operand. */
12094 switch (GET_CODE (x
))
12097 fputs ("eq", file
); /* 4 */
12100 fputs ("ne", file
); /* 24 */
12103 fputs ("lt", file
); /* 16 */
12106 fputs ("le", file
); /* 20 */
12109 fputs ("gt", file
); /* 8 */
12112 fputs ("ge", file
); /* 12 */
12115 fputs ("llt", file
); /* 2 */
12118 fputs ("lle", file
); /* 6 */
12121 fputs ("lgt", file
); /* 1 */
12124 fputs ("lge", file
); /* 5 */
12127 gcc_unreachable ();
12132 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12135 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
12136 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
12138 print_operand (file
, x
, 0);
12142 /* MB value for a PowerPC64 rldic operand. */
12143 val
= (GET_CODE (x
) == CONST_INT
12144 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
12149 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
12150 if ((val
<<= 1) < 0)
12153 #if HOST_BITS_PER_WIDE_INT == 32
12154 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
12155 i
+= 32; /* zero-extend high-part was all 0's */
12156 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
12158 val
= CONST_DOUBLE_LOW (x
);
12164 for ( ; i
< 64; i
++)
12165 if ((val
<<= 1) < 0)
12170 fprintf (file
, "%d", i
+ 1);
12174 if (GET_CODE (x
) == MEM
12175 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
12176 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
12177 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
12182 /* Like 'L', for third word of TImode */
12183 if (GET_CODE (x
) == REG
)
12184 fputs (reg_names
[REGNO (x
) + 2], file
);
12185 else if (GET_CODE (x
) == MEM
)
12187 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12188 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12189 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12190 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12191 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12193 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
12194 if (small_data_operand (x
, GET_MODE (x
)))
12195 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12196 reg_names
[SMALL_DATA_REG
]);
12201 /* X is a SYMBOL_REF. Write out the name preceded by a
12202 period and without any trailing data in brackets. Used for function
12203 names. If we are configured for System V (or the embedded ABI) on
12204 the PowerPC, do not emit the period, since those systems do not use
12205 TOCs and the like. */
12206 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
12208 /* Mark the decl as referenced so that cgraph will output the
12210 if (SYMBOL_REF_DECL (x
))
12211 mark_decl_referenced (SYMBOL_REF_DECL (x
));
12213 /* For macho, check to see if we need a stub. */
12216 const char *name
= XSTR (x
, 0);
12218 if (MACHOPIC_INDIRECT
12219 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
12220 name
= machopic_indirection_name (x
, /*stub_p=*/true);
12222 assemble_name (file
, name
);
12224 else if (!DOT_SYMBOLS
)
12225 assemble_name (file
, XSTR (x
, 0));
12227 rs6000_output_function_entry (file
, XSTR (x
, 0));
12231 /* Like 'L', for last word of TImode. */
12232 if (GET_CODE (x
) == REG
)
12233 fputs (reg_names
[REGNO (x
) + 3], file
);
12234 else if (GET_CODE (x
) == MEM
)
12236 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12237 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12238 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12239 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12240 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12242 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
12243 if (small_data_operand (x
, GET_MODE (x
)))
12244 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12245 reg_names
[SMALL_DATA_REG
]);
12249 /* Print AltiVec or SPE memory operand. */
12254 gcc_assert (GET_CODE (x
) == MEM
);
12258 /* Ugly hack because %y is overloaded. */
12259 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
12260 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
12261 || GET_MODE (x
) == TFmode
12262 || GET_MODE (x
) == TImode
))
12264 /* Handle [reg]. */
12265 if (GET_CODE (tmp
) == REG
)
12267 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
12270 /* Handle [reg+UIMM]. */
12271 else if (GET_CODE (tmp
) == PLUS
&&
12272 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
12276 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
12278 x
= INTVAL (XEXP (tmp
, 1));
12279 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
12283 /* Fall through. Must be [reg+reg]. */
12286 && GET_CODE (tmp
) == AND
12287 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
12288 && INTVAL (XEXP (tmp
, 1)) == -16)
12289 tmp
= XEXP (tmp
, 0);
12290 if (GET_CODE (tmp
) == REG
)
12291 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
12294 if (!GET_CODE (tmp
) == PLUS
12295 || !REG_P (XEXP (tmp
, 0))
12296 || !REG_P (XEXP (tmp
, 1)))
12298 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
12302 if (REGNO (XEXP (tmp
, 0)) == 0)
12303 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
12304 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
12306 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
12307 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
12313 if (GET_CODE (x
) == REG
)
12314 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
12315 else if (GET_CODE (x
) == MEM
)
12317 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12318 know the width from the mode. */
12319 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
12320 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
12321 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12322 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12323 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
12324 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12325 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12326 output_address (XEXP (XEXP (x
, 0), 1));
12328 output_address (XEXP (x
, 0));
12331 output_addr_const (file
, x
);
12335 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
12339 output_operand_lossage ("invalid %%xn code");
12343 /* Print the address of an operand. */
12346 print_operand_address (FILE *file
, rtx x
)
12348 if (GET_CODE (x
) == REG
)
12349 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
12350 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
12351 || GET_CODE (x
) == LABEL_REF
)
12353 output_addr_const (file
, x
);
12354 if (small_data_operand (x
, GET_MODE (x
)))
12355 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12356 reg_names
[SMALL_DATA_REG
]);
12358 gcc_assert (!TARGET_TOC
);
12360 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
12362 gcc_assert (REG_P (XEXP (x
, 0)));
12363 if (REGNO (XEXP (x
, 0)) == 0)
12364 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
12365 reg_names
[ REGNO (XEXP (x
, 0)) ]);
12367 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
12368 reg_names
[ REGNO (XEXP (x
, 1)) ]);
12370 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12371 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
12372 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
12374 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12375 && CONSTANT_P (XEXP (x
, 1)))
12377 output_addr_const (file
, XEXP (x
, 1));
12378 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12382 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12383 && CONSTANT_P (XEXP (x
, 1)))
12385 fprintf (file
, "lo16(");
12386 output_addr_const (file
, XEXP (x
, 1));
12387 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12390 else if (legitimate_constant_pool_address_p (x
))
12392 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
12394 rtx contains_minus
= XEXP (x
, 1);
12398 /* Find the (minus (sym) (toc)) buried in X, and temporarily
12399 turn it into (sym) for output_addr_const. */
12400 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
12401 contains_minus
= XEXP (contains_minus
, 0);
12403 minus
= XEXP (contains_minus
, 0);
12404 symref
= XEXP (minus
, 0);
12405 gcc_assert (GET_CODE (XEXP (minus
, 1)) == SYMBOL_REF
);
12406 XEXP (contains_minus
, 0) = symref
;
12411 name
= XSTR (symref
, 0);
12412 newname
= XALLOCAVEC (char, strlen (name
) + sizeof ("@toc"));
12413 strcpy (newname
, name
);
12414 strcat (newname
, "@toc");
12415 XSTR (symref
, 0) = newname
;
12417 output_addr_const (file
, XEXP (x
, 1));
12419 XSTR (symref
, 0) = name
;
12420 XEXP (contains_minus
, 0) = minus
;
12423 output_addr_const (file
, XEXP (x
, 1));
12425 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
12428 gcc_unreachable ();
12431 /* Target hook for assembling integer objects. The PowerPC version has
12432 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12433 is defined. It also needs to handle DI-mode objects on 64-bit
12437 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
12439 #ifdef RELOCATABLE_NEEDS_FIXUP
12440 /* Special handling for SI values. */
12441 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
12443 static int recurse
= 0;
12445 /* For -mrelocatable, we mark all addresses that need to be fixed up
12446 in the .fixup section. */
12447 if (TARGET_RELOCATABLE
12448 && in_section
!= toc_section
12449 && in_section
!= text_section
12450 && !unlikely_text_section_p (in_section
)
12452 && GET_CODE (x
) != CONST_INT
12453 && GET_CODE (x
) != CONST_DOUBLE
12459 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
12461 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
12462 fprintf (asm_out_file
, "\t.long\t(");
12463 output_addr_const (asm_out_file
, x
);
12464 fprintf (asm_out_file
, ")@fixup\n");
12465 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
12466 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
12467 fprintf (asm_out_file
, "\t.long\t");
12468 assemble_name (asm_out_file
, buf
);
12469 fprintf (asm_out_file
, "\n\t.previous\n");
12473 /* Remove initial .'s to turn a -mcall-aixdesc function
12474 address into the address of the descriptor, not the function
12476 else if (GET_CODE (x
) == SYMBOL_REF
12477 && XSTR (x
, 0)[0] == '.'
12478 && DEFAULT_ABI
== ABI_AIX
)
12480 const char *name
= XSTR (x
, 0);
12481 while (*name
== '.')
12484 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
12488 #endif /* RELOCATABLE_NEEDS_FIXUP */
12489 return default_assemble_integer (x
, size
, aligned_p
);
12492 #ifdef HAVE_GAS_HIDDEN
12493 /* Emit an assembler directive to set symbol visibility for DECL to
12494 VISIBILITY_TYPE. */
12497 rs6000_assemble_visibility (tree decl
, int vis
)
12499 /* Functions need to have their entry point symbol visibility set as
12500 well as their descriptor symbol visibility. */
12501 if (DEFAULT_ABI
== ABI_AIX
12503 && TREE_CODE (decl
) == FUNCTION_DECL
)
12505 static const char * const visibility_types
[] = {
12506 NULL
, "internal", "hidden", "protected"
12509 const char *name
, *type
;
12511 name
= ((* targetm
.strip_name_encoding
)
12512 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
12513 type
= visibility_types
[vis
];
12515 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
12516 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
12519 default_assemble_visibility (decl
, vis
);
12524 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
12526 /* Reversal of FP compares takes care -- an ordered compare
12527 becomes an unordered compare and vice versa. */
12528 if (mode
== CCFPmode
12529 && (!flag_finite_math_only
12530 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
12531 || code
== UNEQ
|| code
== LTGT
))
12532 return reverse_condition_maybe_unordered (code
);
12534 return reverse_condition (code
);
12537 /* Generate a compare for CODE. Return a brand-new rtx that
12538 represents the result of the compare. */
12541 rs6000_generate_compare (enum rtx_code code
)
12543 enum machine_mode comp_mode
;
12544 rtx compare_result
;
12546 if (rs6000_compare_fp_p
)
12547 comp_mode
= CCFPmode
;
12548 else if (code
== GTU
|| code
== LTU
12549 || code
== GEU
|| code
== LEU
)
12550 comp_mode
= CCUNSmode
;
12551 else if ((code
== EQ
|| code
== NE
)
12552 && GET_CODE (rs6000_compare_op0
) == SUBREG
12553 && GET_CODE (rs6000_compare_op1
) == SUBREG
12554 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
12555 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
12556 /* These are unsigned values, perhaps there will be a later
12557 ordering compare that can be shared with this one.
12558 Unfortunately we cannot detect the signedness of the operands
12559 for non-subregs. */
12560 comp_mode
= CCUNSmode
;
12562 comp_mode
= CCmode
;
12564 /* First, the compare. */
12565 compare_result
= gen_reg_rtx (comp_mode
);
12567 /* E500 FP compare instructions on the GPRs. Yuck! */
12568 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12569 && rs6000_compare_fp_p
)
12571 rtx cmp
, or_result
, compare_result2
;
12572 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
12574 if (op_mode
== VOIDmode
)
12575 op_mode
= GET_MODE (rs6000_compare_op1
);
12577 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12578 This explains the following mess. */
12582 case EQ
: case UNEQ
: case NE
: case LTGT
:
12586 cmp
= flag_unsafe_math_optimizations
12587 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
12588 rs6000_compare_op1
)
12589 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
12590 rs6000_compare_op1
);
12594 cmp
= flag_unsafe_math_optimizations
12595 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
12596 rs6000_compare_op1
)
12597 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
12598 rs6000_compare_op1
);
12602 cmp
= flag_unsafe_math_optimizations
12603 ? gen_tsttfeq_gpr (compare_result
, rs6000_compare_op0
,
12604 rs6000_compare_op1
)
12605 : gen_cmptfeq_gpr (compare_result
, rs6000_compare_op0
,
12606 rs6000_compare_op1
);
12610 gcc_unreachable ();
12614 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
12618 cmp
= flag_unsafe_math_optimizations
12619 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
12620 rs6000_compare_op1
)
12621 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
12622 rs6000_compare_op1
);
12626 cmp
= flag_unsafe_math_optimizations
12627 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
12628 rs6000_compare_op1
)
12629 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
12630 rs6000_compare_op1
);
12634 cmp
= flag_unsafe_math_optimizations
12635 ? gen_tsttfgt_gpr (compare_result
, rs6000_compare_op0
,
12636 rs6000_compare_op1
)
12637 : gen_cmptfgt_gpr (compare_result
, rs6000_compare_op0
,
12638 rs6000_compare_op1
);
12642 gcc_unreachable ();
12646 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
12650 cmp
= flag_unsafe_math_optimizations
12651 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
12652 rs6000_compare_op1
)
12653 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
12654 rs6000_compare_op1
);
12658 cmp
= flag_unsafe_math_optimizations
12659 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
12660 rs6000_compare_op1
)
12661 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
12662 rs6000_compare_op1
);
12666 cmp
= flag_unsafe_math_optimizations
12667 ? gen_tsttflt_gpr (compare_result
, rs6000_compare_op0
,
12668 rs6000_compare_op1
)
12669 : gen_cmptflt_gpr (compare_result
, rs6000_compare_op0
,
12670 rs6000_compare_op1
);
12674 gcc_unreachable ();
12678 gcc_unreachable ();
12681 /* Synthesize LE and GE from LT/GT || EQ. */
12682 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
12688 case LE
: code
= LT
; break;
12689 case GE
: code
= GT
; break;
12690 case LEU
: code
= LT
; break;
12691 case GEU
: code
= GT
; break;
12692 default: gcc_unreachable ();
12695 compare_result2
= gen_reg_rtx (CCFPmode
);
12701 cmp
= flag_unsafe_math_optimizations
12702 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12703 rs6000_compare_op1
)
12704 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12705 rs6000_compare_op1
);
12709 cmp
= flag_unsafe_math_optimizations
12710 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12711 rs6000_compare_op1
)
12712 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12713 rs6000_compare_op1
);
12717 cmp
= flag_unsafe_math_optimizations
12718 ? gen_tsttfeq_gpr (compare_result2
, rs6000_compare_op0
,
12719 rs6000_compare_op1
)
12720 : gen_cmptfeq_gpr (compare_result2
, rs6000_compare_op0
,
12721 rs6000_compare_op1
);
12725 gcc_unreachable ();
12729 /* OR them together. */
12730 or_result
= gen_reg_rtx (CCFPmode
);
12731 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
12733 compare_result
= or_result
;
12738 if (code
== NE
|| code
== LTGT
)
12748 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12749 CLOBBERs to match cmptf_internal2 pattern. */
12750 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
12751 && GET_MODE (rs6000_compare_op0
) == TFmode
12752 && !TARGET_IEEEQUAD
12753 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
12754 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
12756 gen_rtx_SET (VOIDmode
,
12758 gen_rtx_COMPARE (comp_mode
,
12759 rs6000_compare_op0
,
12760 rs6000_compare_op1
)),
12761 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12762 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12763 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12764 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12765 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12766 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12767 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12768 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
12769 else if (GET_CODE (rs6000_compare_op1
) == UNSPEC
12770 && XINT (rs6000_compare_op1
, 1) == UNSPEC_SP_TEST
)
12772 rtx op1
= XVECEXP (rs6000_compare_op1
, 0, 0);
12773 comp_mode
= CCEQmode
;
12774 compare_result
= gen_reg_rtx (CCEQmode
);
12776 emit_insn (gen_stack_protect_testdi (compare_result
,
12777 rs6000_compare_op0
, op1
));
12779 emit_insn (gen_stack_protect_testsi (compare_result
,
12780 rs6000_compare_op0
, op1
));
12783 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
12784 gen_rtx_COMPARE (comp_mode
,
12785 rs6000_compare_op0
,
12786 rs6000_compare_op1
)));
12789 /* Some kinds of FP comparisons need an OR operation;
12790 under flag_finite_math_only we don't bother. */
12791 if (rs6000_compare_fp_p
12792 && !flag_finite_math_only
12793 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
12794 && (code
== LE
|| code
== GE
12795 || code
== UNEQ
|| code
== LTGT
12796 || code
== UNGT
|| code
== UNLT
))
12798 enum rtx_code or1
, or2
;
12799 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
12800 rtx or_result
= gen_reg_rtx (CCEQmode
);
12804 case LE
: or1
= LT
; or2
= EQ
; break;
12805 case GE
: or1
= GT
; or2
= EQ
; break;
12806 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
12807 case LTGT
: or1
= LT
; or2
= GT
; break;
12808 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
12809 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
12810 default: gcc_unreachable ();
12812 validate_condition_mode (or1
, comp_mode
);
12813 validate_condition_mode (or2
, comp_mode
);
12814 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
12815 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
12816 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
12817 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
12819 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
12821 compare_result
= or_result
;
12825 validate_condition_mode (code
, GET_MODE (compare_result
));
12827 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
12831 /* Emit the RTL for an sCOND pattern. */
12834 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
12837 enum machine_mode op_mode
;
12838 enum rtx_code cond_code
;
12840 condition_rtx
= rs6000_generate_compare (code
);
12841 cond_code
= GET_CODE (condition_rtx
);
12843 if (rs6000_compare_fp_p
12844 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12848 PUT_MODE (condition_rtx
, SImode
);
12849 t
= XEXP (condition_rtx
, 0);
12851 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
12853 if (cond_code
== NE
)
12854 emit_insn (gen_e500_flip_gt_bit (t
, t
));
12856 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
12860 if (cond_code
== NE
12861 || cond_code
== GE
|| cond_code
== LE
12862 || cond_code
== GEU
|| cond_code
== LEU
12863 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
12865 rtx not_result
= gen_reg_rtx (CCEQmode
);
12866 rtx not_op
, rev_cond_rtx
;
12867 enum machine_mode cc_mode
;
12869 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
12871 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
12872 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
12873 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
12874 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
12875 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
12878 op_mode
= GET_MODE (rs6000_compare_op0
);
12879 if (op_mode
== VOIDmode
)
12880 op_mode
= GET_MODE (rs6000_compare_op1
);
12882 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
12884 PUT_MODE (condition_rtx
, DImode
);
12885 convert_move (result
, condition_rtx
, 0);
12889 PUT_MODE (condition_rtx
, SImode
);
12890 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
12894 /* Emit a branch of kind CODE to location LOC. */
12897 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
12899 rtx condition_rtx
, loc_ref
;
12901 condition_rtx
= rs6000_generate_compare (code
);
12902 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
12903 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
12904 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
12905 loc_ref
, pc_rtx
)));
12908 /* Return the string to output a conditional branch to LABEL, which is
12909 the operand number of the label, or -1 if the branch is really a
12910 conditional return.
12912 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12913 condition code register and its mode specifies what kind of
12914 comparison we made.
12916 REVERSED is nonzero if we should reverse the sense of the comparison.
12918 INSN is the insn. */
12921 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
12923 static char string
[64];
12924 enum rtx_code code
= GET_CODE (op
);
12925 rtx cc_reg
= XEXP (op
, 0);
12926 enum machine_mode mode
= GET_MODE (cc_reg
);
12927 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
12928 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
12929 int really_reversed
= reversed
^ need_longbranch
;
12935 validate_condition_mode (code
, mode
);
12937 /* Work out which way this really branches. We could use
12938 reverse_condition_maybe_unordered here always but this
12939 makes the resulting assembler clearer. */
12940 if (really_reversed
)
12942 /* Reversal of FP compares takes care -- an ordered compare
12943 becomes an unordered compare and vice versa. */
12944 if (mode
== CCFPmode
)
12945 code
= reverse_condition_maybe_unordered (code
);
12947 code
= reverse_condition (code
);
12950 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
12952 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12957 /* Opposite of GT. */
12966 gcc_unreachable ();
12972 /* Not all of these are actually distinct opcodes, but
12973 we distinguish them for clarity of the resulting assembler. */
12974 case NE
: case LTGT
:
12975 ccode
= "ne"; break;
12976 case EQ
: case UNEQ
:
12977 ccode
= "eq"; break;
12979 ccode
= "ge"; break;
12980 case GT
: case GTU
: case UNGT
:
12981 ccode
= "gt"; break;
12983 ccode
= "le"; break;
12984 case LT
: case LTU
: case UNLT
:
12985 ccode
= "lt"; break;
12986 case UNORDERED
: ccode
= "un"; break;
12987 case ORDERED
: ccode
= "nu"; break;
12988 case UNGE
: ccode
= "nl"; break;
12989 case UNLE
: ccode
= "ng"; break;
12991 gcc_unreachable ();
12994 /* Maybe we have a guess as to how likely the branch is.
12995 The old mnemonics don't have a way to specify this information. */
12997 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
12998 if (note
!= NULL_RTX
)
13000 /* PROB is the difference from 50%. */
13001 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
13003 /* Only hint for highly probable/improbable branches on newer
13004 cpus as static prediction overrides processor dynamic
13005 prediction. For older cpus we may as well always hint, but
13006 assume not taken for branches that are very close to 50% as a
13007 mispredicted taken branch is more expensive than a
13008 mispredicted not-taken branch. */
13009 if (rs6000_always_hint
13010 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
13011 && br_prob_note_reliable_p (note
)))
13013 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
13014 && ((prob
> 0) ^ need_longbranch
))
13022 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
13024 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
13026 /* We need to escape any '%' characters in the reg_names string.
13027 Assume they'd only be the first character.... */
13028 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
13030 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
13034 /* If the branch distance was too far, we may have to use an
13035 unconditional branch to go the distance. */
13036 if (need_longbranch
)
13037 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
13039 s
+= sprintf (s
, ",%s", label
);
13045 /* Return the string to flip the GT bit on a CR. */
13047 output_e500_flip_gt_bit (rtx dst
, rtx src
)
13049 static char string
[64];
13052 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
13053 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
13056 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
13057 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
13059 sprintf (string
, "crnot %d,%d", a
, b
);
13063 /* Return insn index for the vector compare instruction for given CODE,
13064 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
13068 get_vec_cmp_insn (enum rtx_code code
,
13069 enum machine_mode dest_mode
,
13070 enum machine_mode op_mode
)
13072 if (!TARGET_ALTIVEC
)
13073 return INSN_NOT_AVAILABLE
;
13078 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13079 return UNSPEC_VCMPEQUB
;
13080 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13081 return UNSPEC_VCMPEQUH
;
13082 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13083 return UNSPEC_VCMPEQUW
;
13084 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13085 return UNSPEC_VCMPEQFP
;
13088 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13089 return UNSPEC_VCMPGEFP
;
13091 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13092 return UNSPEC_VCMPGTSB
;
13093 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13094 return UNSPEC_VCMPGTSH
;
13095 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13096 return UNSPEC_VCMPGTSW
;
13097 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
13098 return UNSPEC_VCMPGTFP
;
13101 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
13102 return UNSPEC_VCMPGTUB
;
13103 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
13104 return UNSPEC_VCMPGTUH
;
13105 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
13106 return UNSPEC_VCMPGTUW
;
13111 return INSN_NOT_AVAILABLE
;
13114 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
13115 DMODE is expected destination mode. This is a recursive function. */
13118 rs6000_emit_vector_compare (enum rtx_code rcode
,
13120 enum machine_mode dmode
)
13124 enum machine_mode dest_mode
;
13125 enum machine_mode op_mode
= GET_MODE (op1
);
13127 gcc_assert (TARGET_ALTIVEC
);
13128 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
13130 /* Floating point vector compare instructions uses destination V4SImode.
13131 Move destination to appropriate mode later. */
13132 if (dmode
== V4SFmode
)
13133 dest_mode
= V4SImode
;
13137 mask
= gen_reg_rtx (dest_mode
);
13138 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13140 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
13142 bool swap_operands
= false;
13143 bool try_again
= false;
13148 swap_operands
= true;
13153 swap_operands
= true;
13161 /* Invert condition and try again.
13162 e.g., A != B becomes ~(A==B). */
13164 enum rtx_code rev_code
;
13165 enum insn_code nor_code
;
13168 rev_code
= reverse_condition_maybe_unordered (rcode
);
13169 eq_rtx
= rs6000_emit_vector_compare (rev_code
, op0
, op1
,
13172 nor_code
= optab_handler (one_cmpl_optab
, (int)dest_mode
)->insn_code
;
13173 gcc_assert (nor_code
!= CODE_FOR_nothing
);
13174 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
13176 if (dmode
!= dest_mode
)
13178 rtx temp
= gen_reg_rtx (dest_mode
);
13179 convert_move (temp
, mask
, 0);
13189 /* Try GT/GTU/LT/LTU OR EQ */
13192 enum insn_code ior_code
;
13193 enum rtx_code new_code
;
13214 gcc_unreachable ();
13217 c_rtx
= rs6000_emit_vector_compare (new_code
,
13218 op0
, op1
, dest_mode
);
13219 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
13222 ior_code
= optab_handler (ior_optab
, (int)dest_mode
)->insn_code
;
13223 gcc_assert (ior_code
!= CODE_FOR_nothing
);
13224 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
13225 if (dmode
!= dest_mode
)
13227 rtx temp
= gen_reg_rtx (dest_mode
);
13228 convert_move (temp
, mask
, 0);
13235 gcc_unreachable ();
13240 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13241 /* You only get two chances. */
13242 gcc_assert (vec_cmp_insn
!= INSN_NOT_AVAILABLE
);
13254 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
13255 gen_rtx_UNSPEC (dest_mode
,
13256 gen_rtvec (2, op0
, op1
),
13258 if (dmode
!= dest_mode
)
13260 rtx temp
= gen_reg_rtx (dest_mode
);
13261 convert_move (temp
, mask
, 0);
13267 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13268 valid insn doesn exist for given mode. */
13271 get_vsel_insn (enum machine_mode mode
)
13276 return UNSPEC_VSEL4SI
;
13279 return UNSPEC_VSEL4SF
;
13282 return UNSPEC_VSEL8HI
;
13285 return UNSPEC_VSEL16QI
;
13288 return INSN_NOT_AVAILABLE
;
13291 return INSN_NOT_AVAILABLE
;
13294 /* Emit vector select insn where DEST is destination using
13295 operands OP1, OP2 and MASK. */
13298 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
13301 enum machine_mode dest_mode
= GET_MODE (dest
);
13302 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
13304 temp
= gen_reg_rtx (dest_mode
);
13306 /* For each vector element, select op1 when mask is 1 otherwise
13308 t
= gen_rtx_SET (VOIDmode
, temp
,
13309 gen_rtx_UNSPEC (dest_mode
,
13310 gen_rtvec (3, op2
, op1
, mask
),
13313 emit_move_insn (dest
, temp
);
13317 /* Emit vector conditional expression.
13318 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13319 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13322 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
13323 rtx cond
, rtx cc_op0
, rtx cc_op1
)
13325 enum machine_mode dest_mode
= GET_MODE (dest
);
13326 enum rtx_code rcode
= GET_CODE (cond
);
13329 if (!TARGET_ALTIVEC
)
13332 /* Get the vector mask for the given relational operations. */
13333 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
13335 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
13340 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13341 operands of the last comparison is nonzero/true, FALSE_COND if it
13342 is zero/false. Return 0 if the hardware has no such operation. */
13345 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13347 enum rtx_code code
= GET_CODE (op
);
13348 rtx op0
= rs6000_compare_op0
;
13349 rtx op1
= rs6000_compare_op1
;
13350 REAL_VALUE_TYPE c1
;
13351 enum machine_mode compare_mode
= GET_MODE (op0
);
13352 enum machine_mode result_mode
= GET_MODE (dest
);
13354 bool is_against_zero
;
13356 /* These modes should always match. */
13357 if (GET_MODE (op1
) != compare_mode
13358 /* In the isel case however, we can use a compare immediate, so
13359 op1 may be a small constant. */
13360 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
13362 if (GET_MODE (true_cond
) != result_mode
)
13364 if (GET_MODE (false_cond
) != result_mode
)
13367 /* First, work out if the hardware can do this at all, or
13368 if it's too slow.... */
13369 if (! rs6000_compare_fp_p
)
13372 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
13375 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
13376 && SCALAR_FLOAT_MODE_P (compare_mode
))
13379 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
13381 /* A floating-point subtract might overflow, underflow, or produce
13382 an inexact result, thus changing the floating-point flags, so it
13383 can't be generated if we care about that. It's safe if one side
13384 of the construct is zero, since then no subtract will be
13386 if (SCALAR_FLOAT_MODE_P (compare_mode
)
13387 && flag_trapping_math
&& ! is_against_zero
)
13390 /* Eliminate half of the comparisons by switching operands, this
13391 makes the remaining code simpler. */
13392 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
13393 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
13395 code
= reverse_condition_maybe_unordered (code
);
13397 true_cond
= false_cond
;
13401 /* UNEQ and LTGT take four instructions for a comparison with zero,
13402 it'll probably be faster to use a branch here too. */
13403 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
13406 if (GET_CODE (op1
) == CONST_DOUBLE
)
13407 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
13409 /* We're going to try to implement comparisons by performing
13410 a subtract, then comparing against zero. Unfortunately,
13411 Inf - Inf is NaN which is not zero, and so if we don't
13412 know that the operand is finite and the comparison
13413 would treat EQ different to UNORDERED, we can't do it. */
13414 if (HONOR_INFINITIES (compare_mode
)
13415 && code
!= GT
&& code
!= UNGE
13416 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
13417 /* Constructs of the form (a OP b ? a : b) are safe. */
13418 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
13419 || (! rtx_equal_p (op0
, true_cond
)
13420 && ! rtx_equal_p (op1
, true_cond
))))
13423 /* At this point we know we can use fsel. */
13425 /* Reduce the comparison to a comparison against zero. */
13426 if (! is_against_zero
)
13428 temp
= gen_reg_rtx (compare_mode
);
13429 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13430 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
13432 op1
= CONST0_RTX (compare_mode
);
13435 /* If we don't care about NaNs we can reduce some of the comparisons
13436 down to faster ones. */
13437 if (! HONOR_NANS (compare_mode
))
13443 true_cond
= false_cond
;
13456 /* Now, reduce everything down to a GE. */
13463 temp
= gen_reg_rtx (compare_mode
);
13464 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13469 temp
= gen_reg_rtx (compare_mode
);
13470 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
13475 temp
= gen_reg_rtx (compare_mode
);
13476 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13477 gen_rtx_NEG (compare_mode
,
13478 gen_rtx_ABS (compare_mode
, op0
))));
13483 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13484 temp
= gen_reg_rtx (result_mode
);
13485 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13486 gen_rtx_IF_THEN_ELSE (result_mode
,
13487 gen_rtx_GE (VOIDmode
,
13489 true_cond
, false_cond
)));
13490 false_cond
= true_cond
;
13493 temp
= gen_reg_rtx (compare_mode
);
13494 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13499 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13500 temp
= gen_reg_rtx (result_mode
);
13501 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13502 gen_rtx_IF_THEN_ELSE (result_mode
,
13503 gen_rtx_GE (VOIDmode
,
13505 true_cond
, false_cond
)));
13506 true_cond
= false_cond
;
13509 temp
= gen_reg_rtx (compare_mode
);
13510 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13515 gcc_unreachable ();
13518 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
13519 gen_rtx_IF_THEN_ELSE (result_mode
,
13520 gen_rtx_GE (VOIDmode
,
13522 true_cond
, false_cond
)));
13526 /* Same as above, but for ints (isel). */
13529 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13531 rtx condition_rtx
, cr
;
13533 /* All isel implementations thus far are 32-bits. */
13534 if (GET_MODE (rs6000_compare_op0
) != SImode
)
13537 /* We still have to do the compare, because isel doesn't do a
13538 compare, it just looks at the CRx bits set by a previous compare
13540 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
13541 cr
= XEXP (condition_rtx
, 0);
13543 if (GET_MODE (cr
) == CCmode
)
13544 emit_insn (gen_isel_signed (dest
, condition_rtx
,
13545 true_cond
, false_cond
, cr
));
13547 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
13548 true_cond
, false_cond
, cr
));
13554 output_isel (rtx
*operands
)
13556 enum rtx_code code
;
13558 code
= GET_CODE (operands
[1]);
13559 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
13561 PUT_CODE (operands
[1], reverse_condition (code
));
13562 return "isel %0,%3,%2,%j1";
13565 return "isel %0,%2,%3,%j1";
13569 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
13571 enum machine_mode mode
= GET_MODE (op0
);
13575 if (code
== SMAX
|| code
== SMIN
)
13580 if (code
== SMAX
|| code
== UMAX
)
13581 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13582 op0
, op1
, mode
, 0);
13584 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13585 op1
, op0
, mode
, 0);
13586 gcc_assert (target
);
13587 if (target
!= dest
)
13588 emit_move_insn (dest
, target
);
13591 /* Emit instructions to perform a load-reserved/store-conditional operation.
13592 The operation performed is an atomic
13593 (set M (CODE:MODE M OP))
13594 If not NULL, BEFORE is atomically set to M before the operation, and
13595 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13596 If SYNC_P then a memory barrier is emitted before the operation.
13597 Either OP or M may be wrapped in a NOT operation. */
13600 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
13601 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
13604 enum machine_mode used_mode
;
13605 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
13608 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13609 rtx shift
= NULL_RTX
;
13612 emit_insn (gen_memory_barrier ());
13614 if (GET_CODE (m
) == NOT
)
13615 used_m
= XEXP (m
, 0);
13619 /* If this is smaller than SImode, we'll have to use SImode with
13621 if (mode
== QImode
|| mode
== HImode
)
13625 if (MEM_ALIGN (used_m
) >= 32)
13628 if (BYTES_BIG_ENDIAN
)
13629 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
13631 shift
= GEN_INT (ishift
);
13632 used_m
= change_address (used_m
, SImode
, 0);
13636 rtx addrSI
, aligned_addr
;
13637 int shift_mask
= mode
== QImode
? 0x18 : 0x10;
13639 addrSI
= gen_lowpart_common (SImode
,
13640 force_reg (Pmode
, XEXP (used_m
, 0)));
13641 addrSI
= force_reg (SImode
, addrSI
);
13642 shift
= gen_reg_rtx (SImode
);
13644 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13645 GEN_INT (shift_mask
)));
13646 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13648 aligned_addr
= expand_binop (Pmode
, and_optab
,
13650 GEN_INT (-4), NULL_RTX
,
13651 1, OPTAB_LIB_WIDEN
);
13652 used_m
= change_address (used_m
, SImode
, aligned_addr
);
13653 set_mem_align (used_m
, 32);
13655 /* It's safe to keep the old alias set of USED_M, because
13656 the operation is atomic and only affects the original
13658 if (GET_CODE (m
) == NOT
)
13659 m
= gen_rtx_NOT (SImode
, used_m
);
13663 if (GET_CODE (op
) == NOT
)
13665 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
13666 oldop
= gen_rtx_NOT (SImode
, oldop
);
13669 oldop
= lowpart_subreg (SImode
, op
, mode
);
13675 newop
= expand_binop (SImode
, and_optab
,
13676 oldop
, GEN_INT (imask
), NULL_RTX
,
13677 1, OPTAB_LIB_WIDEN
);
13678 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13682 newop
= expand_binop (SImode
, ior_optab
,
13683 oldop
, GEN_INT (~imask
), NULL_RTX
,
13684 1, OPTAB_LIB_WIDEN
);
13685 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
13693 newop
= expand_binop (SImode
, and_optab
,
13694 oldop
, GEN_INT (imask
), NULL_RTX
,
13695 1, OPTAB_LIB_WIDEN
);
13696 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13698 mask
= gen_reg_rtx (SImode
);
13699 emit_move_insn (mask
, GEN_INT (imask
));
13700 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13703 newop
= gen_rtx_PLUS (SImode
, m
, newop
);
13705 newop
= gen_rtx_MINUS (SImode
, m
, newop
);
13706 newop
= gen_rtx_AND (SImode
, newop
, mask
);
13707 newop
= gen_rtx_IOR (SImode
, newop
,
13708 gen_rtx_AND (SImode
,
13709 gen_rtx_NOT (SImode
, mask
),
13715 gcc_unreachable ();
13718 if (GET_CODE (m
) == NOT
)
13722 mask
= gen_reg_rtx (SImode
);
13723 emit_move_insn (mask
, GEN_INT (imask
));
13724 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13726 xorm
= gen_rtx_XOR (SImode
, used_m
, mask
);
13727 /* Depending on the value of 'op', the XOR or the operation might
13728 be able to be simplified away. */
13729 newop
= simplify_gen_binary (code
, SImode
, xorm
, newop
);
13732 used_mode
= SImode
;
13733 before
= gen_reg_rtx (used_mode
);
13734 after
= gen_reg_rtx (used_mode
);
13739 before
= before_param
;
13740 after
= after_param
;
13742 if (before
== NULL_RTX
)
13743 before
= gen_reg_rtx (used_mode
);
13744 if (after
== NULL_RTX
)
13745 after
= gen_reg_rtx (used_mode
);
13748 if ((code
== PLUS
|| code
== MINUS
|| GET_CODE (m
) == NOT
)
13749 && used_mode
!= mode
)
13750 the_op
= op
; /* Computed above. */
13751 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
13752 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
13754 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
13756 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
13757 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
13758 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
13759 gen_rtx_UNSPEC (used_mode
,
13760 gen_rtvec (1, the_op
),
13762 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
13764 if ((code
== PLUS
|| code
== MINUS
) && used_mode
!= mode
)
13765 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
13766 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
13768 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
13769 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
13771 /* Shift and mask the return values properly. */
13772 if (used_mode
!= mode
&& before_param
)
13774 emit_insn (gen_lshrsi3 (before
, before
, shift
));
13775 convert_move (before_param
, before
, 1);
13778 if (used_mode
!= mode
&& after_param
)
13780 emit_insn (gen_lshrsi3 (after
, after
, shift
));
13781 convert_move (after_param
, after
, 1);
13784 /* The previous sequence will end with a branch that's dependent on
13785 the conditional store, so placing an isync will ensure that no
13786 other instructions (especially, no load or store instructions)
13787 can start before the atomic operation completes. */
13789 emit_insn (gen_isync ());
13792 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13793 COND is true. Mark the jump as unlikely to be taken. */
13796 emit_unlikely_jump (rtx cond
, rtx label
)
13798 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
13801 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
13802 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
13803 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
13806 /* A subroutine of the atomic operation splitters. Emit a load-locked
13807 instruction in MODE. */
13810 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
13812 rtx (*fn
) (rtx
, rtx
) = NULL
;
13813 if (mode
== SImode
)
13814 fn
= gen_load_locked_si
;
13815 else if (mode
== DImode
)
13816 fn
= gen_load_locked_di
;
13817 emit_insn (fn (reg
, mem
));
13820 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13821 instruction in MODE. */
13824 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
13826 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
13827 if (mode
== SImode
)
13828 fn
= gen_store_conditional_si
;
13829 else if (mode
== DImode
)
13830 fn
= gen_store_conditional_di
;
13832 /* Emit sync before stwcx. to address PPC405 Erratum. */
13833 if (PPC405_ERRATUM77
)
13834 emit_insn (gen_memory_barrier ());
13836 emit_insn (fn (res
, mem
, val
));
13839 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13840 to perform. MEM is the memory on which to operate. VAL is the second
13841 operand of the binary operator. BEFORE and AFTER are optional locations to
13842 return the value of MEM either before of after the operation. SCRATCH is
13843 a scratch register. */
13846 rs6000_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
13847 rtx before
, rtx after
, rtx scratch
)
13849 enum machine_mode mode
= GET_MODE (mem
);
13850 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13852 emit_insn (gen_memory_barrier ());
13854 label
= gen_label_rtx ();
13855 emit_label (label
);
13856 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
13858 if (before
== NULL_RTX
)
13860 emit_load_locked (mode
, before
, mem
);
13863 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
13864 else if (code
== AND
)
13865 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (2, before
, val
), UNSPEC_AND
);
13867 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
13869 if (after
!= NULL_RTX
)
13870 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
13871 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
13873 emit_store_conditional (mode
, cond
, mem
, scratch
);
13875 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13876 emit_unlikely_jump (x
, label
);
13878 emit_insn (gen_isync ());
13881 /* Expand an atomic compare and swap operation. MEM is the memory on which
13882 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13883 value to be stored. SCRATCH is a scratch GPR. */
13886 rs6000_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
13889 enum machine_mode mode
= GET_MODE (mem
);
13890 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13892 emit_insn (gen_memory_barrier ());
13894 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13895 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13896 emit_label (XEXP (label1
, 0));
13898 emit_load_locked (mode
, retval
, mem
);
13900 x
= gen_rtx_COMPARE (CCmode
, retval
, oldval
);
13901 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
13903 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13904 emit_unlikely_jump (x
, label2
);
13906 emit_move_insn (scratch
, newval
);
13907 emit_store_conditional (mode
, cond
, mem
, scratch
);
13909 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13910 emit_unlikely_jump (x
, label1
);
13912 emit_insn (gen_isync ());
13913 emit_label (XEXP (label2
, 0));
13916 /* Expand an atomic test and set operation. MEM is the memory on which
13917 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13920 rs6000_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
13922 enum machine_mode mode
= GET_MODE (mem
);
13923 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13925 emit_insn (gen_memory_barrier ());
13927 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13928 emit_label (XEXP (label
, 0));
13930 emit_load_locked (mode
, retval
, mem
);
13931 emit_move_insn (scratch
, val
);
13932 emit_store_conditional (mode
, cond
, mem
, scratch
);
13934 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13935 emit_unlikely_jump (x
, label
);
13937 emit_insn (gen_isync ());
13941 rs6000_expand_compare_and_swapqhi (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
13943 enum machine_mode mode
= GET_MODE (mem
);
13944 rtx addrSI
, align
, wdst
, shift
, mask
;
13945 HOST_WIDE_INT shift_mask
= mode
== QImode
? 0x18 : 0x10;
13946 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13948 /* Shift amount for subword relative to aligned word. */
13949 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
, XEXP (mem
, 0)));
13950 shift
= gen_reg_rtx (SImode
);
13951 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13952 GEN_INT (shift_mask
)));
13953 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13955 /* Shift and mask old value into position within word. */
13956 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
13957 oldval
= expand_binop (SImode
, and_optab
,
13958 oldval
, GEN_INT (imask
), NULL_RTX
,
13959 1, OPTAB_LIB_WIDEN
);
13960 emit_insn (gen_ashlsi3 (oldval
, oldval
, shift
));
13962 /* Shift and mask new value into position within word. */
13963 newval
= convert_modes (SImode
, mode
, newval
, 1);
13964 newval
= expand_binop (SImode
, and_optab
,
13965 newval
, GEN_INT (imask
), NULL_RTX
,
13966 1, OPTAB_LIB_WIDEN
);
13967 emit_insn (gen_ashlsi3 (newval
, newval
, shift
));
13969 /* Mask for insertion. */
13970 mask
= gen_reg_rtx (SImode
);
13971 emit_move_insn (mask
, GEN_INT (imask
));
13972 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13974 /* Address of aligned word containing subword. */
13975 align
= expand_binop (Pmode
, and_optab
, XEXP (mem
, 0), GEN_INT (-4),
13976 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
13977 mem
= change_address (mem
, SImode
, align
);
13978 set_mem_align (mem
, 32);
13979 MEM_VOLATILE_P (mem
) = 1;
13981 wdst
= gen_reg_rtx (SImode
);
13982 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst
, mask
,
13983 oldval
, newval
, mem
));
13985 /* Shift the result back. */
13986 emit_insn (gen_lshrsi3 (wdst
, wdst
, shift
));
13988 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
13992 rs6000_split_compare_and_swapqhi (rtx dest
, rtx mask
,
13993 rtx oldval
, rtx newval
, rtx mem
,
13996 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13998 emit_insn (gen_memory_barrier ());
13999 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14000 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
14001 emit_label (XEXP (label1
, 0));
14003 emit_load_locked (SImode
, scratch
, mem
);
14005 /* Mask subword within loaded value for comparison with oldval.
14006 Use UNSPEC_AND to avoid clobber.*/
14007 emit_insn (gen_rtx_SET (SImode
, dest
,
14008 gen_rtx_UNSPEC (SImode
,
14009 gen_rtvec (2, scratch
, mask
),
14012 x
= gen_rtx_COMPARE (CCmode
, dest
, oldval
);
14013 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
14015 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14016 emit_unlikely_jump (x
, label2
);
14018 /* Clear subword within loaded value for insertion of new value. */
14019 emit_insn (gen_rtx_SET (SImode
, scratch
,
14020 gen_rtx_AND (SImode
,
14021 gen_rtx_NOT (SImode
, mask
), scratch
)));
14022 emit_insn (gen_iorsi3 (scratch
, scratch
, newval
));
14023 emit_store_conditional (SImode
, cond
, mem
, scratch
);
14025 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
14026 emit_unlikely_jump (x
, label1
);
14028 emit_insn (gen_isync ());
14029 emit_label (XEXP (label2
, 0));
14033 /* Emit instructions to move SRC to DST. Called by splitters for
14034 multi-register moves. It will emit at most one instruction for
14035 each register that is accessed; that is, it won't emit li/lis pairs
14036 (or equivalent for 64-bit code). One of SRC or DST must be a hard
14040 rs6000_split_multireg_move (rtx dst
, rtx src
)
14042 /* The register number of the first register being moved. */
14044 /* The mode that is to be moved. */
14045 enum machine_mode mode
;
14046 /* The mode that the move is being done in, and its size. */
14047 enum machine_mode reg_mode
;
14049 /* The number of registers that will be moved. */
14052 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
14053 mode
= GET_MODE (dst
);
14054 nregs
= hard_regno_nregs
[reg
][mode
];
14055 if (FP_REGNO_P (reg
))
14056 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
14057 else if (ALTIVEC_REGNO_P (reg
))
14058 reg_mode
= V16QImode
;
14059 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
14062 reg_mode
= word_mode
;
14063 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
14065 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
14067 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
14069 /* Move register range backwards, if we might have destructive
14072 for (i
= nregs
- 1; i
>= 0; i
--)
14073 emit_insn (gen_rtx_SET (VOIDmode
,
14074 simplify_gen_subreg (reg_mode
, dst
, mode
,
14075 i
* reg_mode_size
),
14076 simplify_gen_subreg (reg_mode
, src
, mode
,
14077 i
* reg_mode_size
)));
14083 bool used_update
= false;
14085 if (MEM_P (src
) && INT_REGNO_P (reg
))
14089 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
14090 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
14093 breg
= XEXP (XEXP (src
, 0), 0);
14094 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
14095 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
14096 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
14097 emit_insn (TARGET_32BIT
14098 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14099 : gen_adddi3 (breg
, breg
, delta_rtx
));
14100 src
= replace_equiv_address (src
, breg
);
14102 else if (! rs6000_offsettable_memref_p (src
))
14105 basereg
= gen_rtx_REG (Pmode
, reg
);
14106 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
14107 src
= replace_equiv_address (src
, basereg
);
14110 breg
= XEXP (src
, 0);
14111 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
14112 breg
= XEXP (breg
, 0);
14114 /* If the base register we are using to address memory is
14115 also a destination reg, then change that register last. */
14117 && REGNO (breg
) >= REGNO (dst
)
14118 && REGNO (breg
) < REGNO (dst
) + nregs
)
14119 j
= REGNO (breg
) - REGNO (dst
);
14122 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
14126 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14127 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
14130 breg
= XEXP (XEXP (dst
, 0), 0);
14131 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14132 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
14133 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
14135 /* We have to update the breg before doing the store.
14136 Use store with update, if available. */
14140 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
14141 emit_insn (TARGET_32BIT
14142 ? (TARGET_POWERPC64
14143 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
14144 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
14145 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
14146 used_update
= true;
14149 emit_insn (TARGET_32BIT
14150 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14151 : gen_adddi3 (breg
, breg
, delta_rtx
));
14152 dst
= replace_equiv_address (dst
, breg
);
14155 gcc_assert (rs6000_offsettable_memref_p (dst
));
14158 for (i
= 0; i
< nregs
; i
++)
14160 /* Calculate index to next subword. */
14165 /* If compiler already emitted move of first word by
14166 store with update, no need to do anything. */
14167 if (j
== 0 && used_update
)
14170 emit_insn (gen_rtx_SET (VOIDmode
,
14171 simplify_gen_subreg (reg_mode
, dst
, mode
,
14172 j
* reg_mode_size
),
14173 simplify_gen_subreg (reg_mode
, src
, mode
,
14174 j
* reg_mode_size
)));
14180 /* This page contains routines that are used to determine what the
14181 function prologue and epilogue code will do and write them out. */
14183 /* Return the first fixed-point register that is required to be
14184 saved. 32 if none. */
14187 first_reg_to_save (void)
14191 /* Find lowest numbered live register. */
14192 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
14193 if (df_regs_ever_live_p (first_reg
)
14194 && (! call_used_regs
[first_reg
]
14195 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
14196 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14197 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
14198 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
14203 && crtl
->uses_pic_offset_table
14204 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14205 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
14211 /* Similar, for FP regs. */
14214 first_fp_reg_to_save (void)
14218 /* Find lowest numbered live register. */
14219 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
14220 if (df_regs_ever_live_p (first_reg
))
14226 /* Similar, for AltiVec regs. */
14229 first_altivec_reg_to_save (void)
14233 /* Stack frame remains as is unless we are in AltiVec ABI. */
14234 if (! TARGET_ALTIVEC_ABI
)
14235 return LAST_ALTIVEC_REGNO
+ 1;
14237 /* On Darwin, the unwind routines are compiled without
14238 TARGET_ALTIVEC, and use save_world to save/restore the
14239 altivec registers when necessary. */
14240 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
14241 && ! TARGET_ALTIVEC
)
14242 return FIRST_ALTIVEC_REGNO
+ 20;
14244 /* Find lowest numbered live register. */
14245 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14246 if (df_regs_ever_live_p (i
))
14252 /* Return a 32-bit mask of the AltiVec registers we need to set in
14253 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14254 the 32-bit word is 0. */
14256 static unsigned int
14257 compute_vrsave_mask (void)
14259 unsigned int i
, mask
= 0;
14261 /* On Darwin, the unwind routines are compiled without
14262 TARGET_ALTIVEC, and use save_world to save/restore the
14263 call-saved altivec registers when necessary. */
14264 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
14265 && ! TARGET_ALTIVEC
)
14268 /* First, find out if we use _any_ altivec registers. */
14269 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14270 if (df_regs_ever_live_p (i
))
14271 mask
|= ALTIVEC_REG_BIT (i
);
14276 /* Next, remove the argument registers from the set. These must
14277 be in the VRSAVE mask set by the caller, so we don't need to add
14278 them in again. More importantly, the mask we compute here is
14279 used to generate CLOBBERs in the set_vrsave insn, and we do not
14280 wish the argument registers to die. */
14281 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
14282 mask
&= ~ALTIVEC_REG_BIT (i
);
14284 /* Similarly, remove the return value from the set. */
14287 diddle_return_value (is_altivec_return_reg
, &yes
);
14289 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
14295 /* For a very restricted set of circumstances, we can cut down the
14296 size of prologues/epilogues by calling our own save/restore-the-world
14300 compute_save_world_info (rs6000_stack_t
*info_ptr
)
14302 info_ptr
->world_save_p
= 1;
14303 info_ptr
->world_save_p
14304 = (WORLD_SAVE_P (info_ptr
)
14305 && DEFAULT_ABI
== ABI_DARWIN
14306 && ! (cfun
->calls_setjmp
&& flag_exceptions
)
14307 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
14308 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
14309 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
14310 && info_ptr
->cr_save_p
);
14312 /* This will not work in conjunction with sibcalls. Make sure there
14313 are none. (This check is expensive, but seldom executed.) */
14314 if (WORLD_SAVE_P (info_ptr
))
14317 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
14318 if ( GET_CODE (insn
) == CALL_INSN
14319 && SIBLING_CALL_P (insn
))
14321 info_ptr
->world_save_p
= 0;
14326 if (WORLD_SAVE_P (info_ptr
))
14328 /* Even if we're not touching VRsave, make sure there's room on the
14329 stack for it, if it looks like we're calling SAVE_WORLD, which
14330 will attempt to save it. */
14331 info_ptr
->vrsave_size
= 4;
14333 /* If we are going to save the world, we need to save the link register too. */
14334 info_ptr
->lr_save_p
= 1;
14336 /* "Save" the VRsave register too if we're saving the world. */
14337 if (info_ptr
->vrsave_mask
== 0)
14338 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14340 /* Because the Darwin register save/restore routines only handle
14341 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14343 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
14344 && (info_ptr
->first_altivec_reg_save
14345 >= FIRST_SAVED_ALTIVEC_REGNO
));
14352 is_altivec_return_reg (rtx reg
, void *xyes
)
14354 bool *yes
= (bool *) xyes
;
14355 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
14360 /* Calculate the stack information for the current function. This is
14361 complicated by having two separate calling sequences, the AIX calling
14362 sequence and the V.4 calling sequence.
14364 AIX (and Darwin/Mac OS X) stack frames look like:
14366 SP----> +---------------------------------------+
14367 | back chain to caller | 0 0
14368 +---------------------------------------+
14369 | saved CR | 4 8 (8-11)
14370 +---------------------------------------+
14372 +---------------------------------------+
14373 | reserved for compilers | 12 24
14374 +---------------------------------------+
14375 | reserved for binders | 16 32
14376 +---------------------------------------+
14377 | saved TOC pointer | 20 40
14378 +---------------------------------------+
14379 | Parameter save area (P) | 24 48
14380 +---------------------------------------+
14381 | Alloca space (A) | 24+P etc.
14382 +---------------------------------------+
14383 | Local variable space (L) | 24+P+A
14384 +---------------------------------------+
14385 | Float/int conversion temporary (X) | 24+P+A+L
14386 +---------------------------------------+
14387 | Save area for AltiVec registers (W) | 24+P+A+L+X
14388 +---------------------------------------+
14389 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14390 +---------------------------------------+
14391 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14392 +---------------------------------------+
14393 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14394 +---------------------------------------+
14395 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14396 +---------------------------------------+
14397 old SP->| back chain to caller's caller |
14398 +---------------------------------------+
14400 The required alignment for AIX configurations is two words (i.e., 8
14404 V.4 stack frames look like:
14406 SP----> +---------------------------------------+
14407 | back chain to caller | 0
14408 +---------------------------------------+
14409 | caller's saved LR | 4
14410 +---------------------------------------+
14411 | Parameter save area (P) | 8
14412 +---------------------------------------+
14413 | Alloca space (A) | 8+P
14414 +---------------------------------------+
14415 | Varargs save area (V) | 8+P+A
14416 +---------------------------------------+
14417 | Local variable space (L) | 8+P+A+V
14418 +---------------------------------------+
14419 | Float/int conversion temporary (X) | 8+P+A+V+L
14420 +---------------------------------------+
14421 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14422 +---------------------------------------+
14423 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14424 +---------------------------------------+
14425 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14426 +---------------------------------------+
14427 | SPE: area for 64-bit GP registers |
14428 +---------------------------------------+
14429 | SPE alignment padding |
14430 +---------------------------------------+
14431 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14432 +---------------------------------------+
14433 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14434 +---------------------------------------+
14435 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14436 +---------------------------------------+
14437 old SP->| back chain to caller's caller |
14438 +---------------------------------------+
14440 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14441 given. (But note below and in sysv4.h that we require only 8 and
14442 may round up the size of our stack frame anyways. The historical
14443 reason is early versions of powerpc-linux which didn't properly
14444 align the stack at program startup. A happy side-effect is that
14445 -mno-eabi libraries can be used with -meabi programs.)
14447 The EABI configuration defaults to the V.4 layout. However,
14448 the stack alignment requirements may differ. If -mno-eabi is not
14449 given, the required stack alignment is 8 bytes; if -mno-eabi is
14450 given, the required alignment is 16 bytes. (But see V.4 comment
14453 #ifndef ABI_STACK_BOUNDARY
14454 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14457 static rs6000_stack_t
*
14458 rs6000_stack_info (void)
14460 static rs6000_stack_t info
;
14461 rs6000_stack_t
*info_ptr
= &info
;
14462 int reg_size
= TARGET_32BIT
? 4 : 8;
14466 HOST_WIDE_INT non_fixed_size
;
14468 memset (&info
, 0, sizeof (info
));
14472 /* Cache value so we don't rescan instruction chain over and over. */
14473 if (cfun
->machine
->insn_chain_scanned_p
== 0)
14474 cfun
->machine
->insn_chain_scanned_p
14475 = spe_func_has_64bit_regs_p () + 1;
14476 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
14479 /* Select which calling sequence. */
14480 info_ptr
->abi
= DEFAULT_ABI
;
14482 /* Calculate which registers need to be saved & save area size. */
14483 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
14484 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14485 even if it currently looks like we won't. Reload may need it to
14486 get at a constant; if so, it will have already created a constant
14487 pool entry for it. */
14488 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
14489 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
14490 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
14491 && crtl
->uses_const_pool
14492 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14493 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
14495 first_gp
= info_ptr
->first_gp_reg_save
;
14497 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
14499 /* For the SPE, we have an additional upper 32-bits on each GPR.
14500 Ideally we should save the entire 64-bits only when the upper
14501 half is used in SIMD instructions. Since we only record
14502 registers live (not the size they are used in), this proves
14503 difficult because we'd have to traverse the instruction chain at
14504 the right time, taking reload into account. This is a real pain,
14505 so we opt to save the GPRs in 64-bits always if but one register
14506 gets used in 64-bits. Otherwise, all the registers in the frame
14507 get saved in 32-bits.
14509 So... since when we save all GPRs (except the SP) in 64-bits, the
14510 traditional GP save area will be empty. */
14511 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14512 info_ptr
->gp_size
= 0;
14514 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
14515 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
14517 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
14518 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
14519 - info_ptr
->first_altivec_reg_save
);
14521 /* Does this function call anything? */
14522 info_ptr
->calls_p
= (! current_function_is_leaf
14523 || cfun
->machine
->ra_needs_full_frame
);
14525 /* Determine if we need to save the link register. */
14526 if ((DEFAULT_ABI
== ABI_AIX
14528 && !TARGET_PROFILE_KERNEL
)
14529 #ifdef TARGET_RELOCATABLE
14530 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
14532 || (info_ptr
->first_fp_reg_save
!= 64
14533 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
14534 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
14535 || info_ptr
->calls_p
14536 || rs6000_ra_ever_killed ())
14538 info_ptr
->lr_save_p
= 1;
14539 df_set_regs_ever_live (LR_REGNO
, true);
14542 /* Determine if we need to save the condition code registers. */
14543 if (df_regs_ever_live_p (CR2_REGNO
)
14544 || df_regs_ever_live_p (CR3_REGNO
)
14545 || df_regs_ever_live_p (CR4_REGNO
))
14547 info_ptr
->cr_save_p
= 1;
14548 if (DEFAULT_ABI
== ABI_V4
)
14549 info_ptr
->cr_size
= reg_size
;
14552 /* If the current function calls __builtin_eh_return, then we need
14553 to allocate stack space for registers that will hold data for
14554 the exception handler. */
14555 if (crtl
->calls_eh_return
)
14558 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
14561 /* SPE saves EH registers in 64-bits. */
14562 ehrd_size
= i
* (TARGET_SPE_ABI
14563 && info_ptr
->spe_64bit_regs_used
!= 0
14564 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
14569 /* Determine various sizes. */
14570 info_ptr
->reg_size
= reg_size
;
14571 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
14572 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
14573 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
14574 TARGET_ALTIVEC
? 16 : 8);
14575 if (FRAME_GROWS_DOWNWARD
)
14576 info_ptr
->vars_size
14577 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
14578 + info_ptr
->parm_size
,
14579 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
14580 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
14581 + info_ptr
->parm_size
);
14583 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14584 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
14586 info_ptr
->spe_gp_size
= 0;
14588 if (TARGET_ALTIVEC_ABI
)
14589 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14591 info_ptr
->vrsave_mask
= 0;
14593 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
14594 info_ptr
->vrsave_size
= 4;
14596 info_ptr
->vrsave_size
= 0;
14598 compute_save_world_info (info_ptr
);
14600 /* Calculate the offsets. */
14601 switch (DEFAULT_ABI
)
14605 gcc_unreachable ();
14609 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14610 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14612 if (TARGET_ALTIVEC_ABI
)
14614 info_ptr
->vrsave_save_offset
14615 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
14617 /* Align stack so vector save area is on a quadword boundary.
14618 The padding goes above the vectors. */
14619 if (info_ptr
->altivec_size
!= 0)
14620 info_ptr
->altivec_padding_size
14621 = info_ptr
->vrsave_save_offset
& 0xF;
14623 info_ptr
->altivec_padding_size
= 0;
14625 info_ptr
->altivec_save_offset
14626 = info_ptr
->vrsave_save_offset
14627 - info_ptr
->altivec_padding_size
14628 - info_ptr
->altivec_size
;
14629 gcc_assert (info_ptr
->altivec_size
== 0
14630 || info_ptr
->altivec_save_offset
% 16 == 0);
14632 /* Adjust for AltiVec case. */
14633 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
14636 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
14637 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
14638 info_ptr
->lr_save_offset
= 2*reg_size
;
14642 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14643 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14644 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
14646 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14648 /* Align stack so SPE GPR save area is aligned on a
14649 double-word boundary. */
14650 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
14651 info_ptr
->spe_padding_size
14652 = 8 - (-info_ptr
->cr_save_offset
% 8);
14654 info_ptr
->spe_padding_size
= 0;
14656 info_ptr
->spe_gp_save_offset
14657 = info_ptr
->cr_save_offset
14658 - info_ptr
->spe_padding_size
14659 - info_ptr
->spe_gp_size
;
14661 /* Adjust for SPE case. */
14662 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
14664 else if (TARGET_ALTIVEC_ABI
)
14666 info_ptr
->vrsave_save_offset
14667 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
14669 /* Align stack so vector save area is on a quadword boundary. */
14670 if (info_ptr
->altivec_size
!= 0)
14671 info_ptr
->altivec_padding_size
14672 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
14674 info_ptr
->altivec_padding_size
= 0;
14676 info_ptr
->altivec_save_offset
14677 = info_ptr
->vrsave_save_offset
14678 - info_ptr
->altivec_padding_size
14679 - info_ptr
->altivec_size
;
14681 /* Adjust for AltiVec case. */
14682 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
14685 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
14686 info_ptr
->ehrd_offset
-= ehrd_size
;
14687 info_ptr
->lr_save_offset
= reg_size
;
14691 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
14692 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
14693 + info_ptr
->gp_size
14694 + info_ptr
->altivec_size
14695 + info_ptr
->altivec_padding_size
14696 + info_ptr
->spe_gp_size
14697 + info_ptr
->spe_padding_size
14699 + info_ptr
->cr_size
14700 + info_ptr
->vrsave_size
,
14703 non_fixed_size
= (info_ptr
->vars_size
14704 + info_ptr
->parm_size
14705 + info_ptr
->save_size
);
14707 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
14708 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
14710 /* Determine if we need to allocate any stack frame:
14712 For AIX we need to push the stack if a frame pointer is needed
14713 (because the stack might be dynamically adjusted), if we are
14714 debugging, if we make calls, or if the sum of fp_save, gp_save,
14715 and local variables are more than the space needed to save all
14716 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14717 + 18*8 = 288 (GPR13 reserved).
14719 For V.4 we don't have the stack cushion that AIX uses, but assume
14720 that the debugger can handle stackless frames. */
14722 if (info_ptr
->calls_p
)
14723 info_ptr
->push_p
= 1;
14725 else if (DEFAULT_ABI
== ABI_V4
)
14726 info_ptr
->push_p
= non_fixed_size
!= 0;
14728 else if (frame_pointer_needed
)
14729 info_ptr
->push_p
= 1;
14731 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
14732 info_ptr
->push_p
= 1;
14735 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
14737 /* Zero offsets if we're not saving those registers. */
14738 if (info_ptr
->fp_size
== 0)
14739 info_ptr
->fp_save_offset
= 0;
14741 if (info_ptr
->gp_size
== 0)
14742 info_ptr
->gp_save_offset
= 0;
14744 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
14745 info_ptr
->altivec_save_offset
= 0;
14747 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
14748 info_ptr
->vrsave_save_offset
= 0;
14750 if (! TARGET_SPE_ABI
14751 || info_ptr
->spe_64bit_regs_used
== 0
14752 || info_ptr
->spe_gp_size
== 0)
14753 info_ptr
->spe_gp_save_offset
= 0;
14755 if (! info_ptr
->lr_save_p
)
14756 info_ptr
->lr_save_offset
= 0;
14758 if (! info_ptr
->cr_save_p
)
14759 info_ptr
->cr_save_offset
= 0;
14764 /* Return true if the current function uses any GPRs in 64-bit SIMD
14768 spe_func_has_64bit_regs_p (void)
14772 /* Functions that save and restore all the call-saved registers will
14773 need to save/restore the registers in 64-bits. */
14774 if (crtl
->calls_eh_return
14775 || cfun
->calls_setjmp
14776 || crtl
->has_nonlocal_goto
)
14779 insns
= get_insns ();
14781 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
14787 /* FIXME: This should be implemented with attributes...
14789 (set_attr "spe64" "true")....then,
14790 if (get_spe64(insn)) return true;
14792 It's the only reliable way to do the stuff below. */
14794 i
= PATTERN (insn
);
14795 if (GET_CODE (i
) == SET
)
14797 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
14799 if (SPE_VECTOR_MODE (mode
))
14801 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
14811 debug_stack_info (rs6000_stack_t
*info
)
14813 const char *abi_string
;
14816 info
= rs6000_stack_info ();
14818 fprintf (stderr
, "\nStack information for function %s:\n",
14819 ((current_function_decl
&& DECL_NAME (current_function_decl
))
14820 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
14825 default: abi_string
= "Unknown"; break;
14826 case ABI_NONE
: abi_string
= "NONE"; break;
14827 case ABI_AIX
: abi_string
= "AIX"; break;
14828 case ABI_DARWIN
: abi_string
= "Darwin"; break;
14829 case ABI_V4
: abi_string
= "V.4"; break;
14832 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
14834 if (TARGET_ALTIVEC_ABI
)
14835 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
14837 if (TARGET_SPE_ABI
)
14838 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
14840 if (info
->first_gp_reg_save
!= 32)
14841 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
14843 if (info
->first_fp_reg_save
!= 64)
14844 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
14846 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
14847 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
14848 info
->first_altivec_reg_save
);
14850 if (info
->lr_save_p
)
14851 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
14853 if (info
->cr_save_p
)
14854 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
14856 if (info
->vrsave_mask
)
14857 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
14860 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
14863 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
14865 if (info
->gp_save_offset
)
14866 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
14868 if (info
->fp_save_offset
)
14869 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
14871 if (info
->altivec_save_offset
)
14872 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
14873 info
->altivec_save_offset
);
14875 if (info
->spe_gp_save_offset
)
14876 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
14877 info
->spe_gp_save_offset
);
14879 if (info
->vrsave_save_offset
)
14880 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
14881 info
->vrsave_save_offset
);
14883 if (info
->lr_save_offset
)
14884 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
14886 if (info
->cr_save_offset
)
14887 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
14889 if (info
->varargs_save_offset
)
14890 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
14892 if (info
->total_size
)
14893 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14896 if (info
->vars_size
)
14897 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14900 if (info
->parm_size
)
14901 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
14903 if (info
->fixed_size
)
14904 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
14907 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
14909 if (info
->spe_gp_size
)
14910 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
14913 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
14915 if (info
->altivec_size
)
14916 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
14918 if (info
->vrsave_size
)
14919 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
14921 if (info
->altivec_padding_size
)
14922 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
14923 info
->altivec_padding_size
);
14925 if (info
->spe_padding_size
)
14926 fprintf (stderr
, "\tspe_padding_size = %5d\n",
14927 info
->spe_padding_size
);
14930 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
14932 if (info
->save_size
)
14933 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
14935 if (info
->reg_size
!= 4)
14936 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
14938 fprintf (stderr
, "\n");
14942 rs6000_return_addr (int count
, rtx frame
)
14944 /* Currently we don't optimize very well between prolog and body
14945 code and for PIC code the code can be actually quite bad, so
14946 don't try to be too clever here. */
14947 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
14949 cfun
->machine
->ra_needs_full_frame
= 1;
14956 plus_constant (copy_to_reg
14957 (gen_rtx_MEM (Pmode
,
14958 memory_address (Pmode
, frame
))),
14959 RETURN_ADDRESS_OFFSET
)));
14962 cfun
->machine
->ra_need_lr
= 1;
14963 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
14966 /* Say whether a function is a candidate for sibcall handling or not.
14967 We do not allow indirect calls to be optimized into sibling calls.
14968 Also, we can't do it if there are any vector parameters; there's
14969 nowhere to put the VRsave code so it works; note that functions with
14970 vector parameters are required to have a prototype, so the argument
14971 type info must be available here. (The tail recursion case can work
14972 with vector parameters, but there's no way to distinguish here.) */
14974 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
14979 if (TARGET_ALTIVEC_VRSAVE
)
14981 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
14982 type
; type
= TREE_CHAIN (type
))
14984 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
14988 if (DEFAULT_ABI
== ABI_DARWIN
14989 || ((*targetm
.binds_local_p
) (decl
)
14990 && (DEFAULT_ABI
!= ABI_AIX
|| !DECL_EXTERNAL (decl
))))
14992 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
14994 if (!lookup_attribute ("longcall", attr_list
)
14995 || lookup_attribute ("shortcall", attr_list
))
15002 /* NULL if INSN insn is valid within a low-overhead loop.
15003 Otherwise return why doloop cannot be applied.
15004 PowerPC uses the COUNT register for branch on table instructions. */
15006 static const char *
15007 rs6000_invalid_within_doloop (const_rtx insn
)
15010 return "Function call in the loop.";
15013 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
15014 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
15015 return "Computed branch in the loop.";
15021 rs6000_ra_ever_killed (void)
15027 if (crtl
->is_thunk
)
15030 /* regs_ever_live has LR marked as used if any sibcalls are present,
15031 but this should not force saving and restoring in the
15032 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
15033 clobbers LR, so that is inappropriate. */
15035 /* Also, the prologue can generate a store into LR that
15036 doesn't really count, like this:
15039 bcl to set PIC register
15043 When we're called from the epilogue, we need to avoid counting
15044 this as a store. */
15046 push_topmost_sequence ();
15047 top
= get_insns ();
15048 pop_topmost_sequence ();
15049 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
15051 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
15057 if (!SIBLING_CALL_P (insn
))
15060 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
15062 else if (set_of (reg
, insn
) != NULL_RTX
15063 && !prologue_epilogue_contains (insn
))
15070 /* Emit instructions needed to load the TOC register.
15071 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
15072 a constant pool; or for SVR4 -fpic. */
15075 rs6000_emit_load_toc_table (int fromprolog
)
15078 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
15080 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
15083 rtx lab
, tmp1
, tmp2
, got
;
15085 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
15086 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15088 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15090 got
= rs6000_got_sym ();
15091 tmp1
= tmp2
= dest
;
15094 tmp1
= gen_reg_rtx (Pmode
);
15095 tmp2
= gen_reg_rtx (Pmode
);
15097 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
15098 emit_move_insn (tmp1
,
15099 gen_rtx_REG (Pmode
, LR_REGNO
));
15100 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
15101 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
15103 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
15105 emit_insn (gen_load_toc_v4_pic_si ());
15106 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
15108 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
15111 rtx temp0
= (fromprolog
15112 ? gen_rtx_REG (Pmode
, 0)
15113 : gen_reg_rtx (Pmode
));
15119 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
15120 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15122 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
15123 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15125 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
15126 emit_move_insn (dest
,
15127 gen_rtx_REG (Pmode
, LR_REGNO
));
15128 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
15134 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15135 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
));
15136 emit_move_insn (dest
,
15137 gen_rtx_REG (Pmode
, LR_REGNO
));
15138 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
15140 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
15142 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
15144 /* This is for AIX code running in non-PIC ELF32. */
15147 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
15148 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15150 emit_insn (gen_elf_high (dest
, realsym
));
15151 emit_insn (gen_elf_low (dest
, dest
, realsym
));
15155 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
15158 emit_insn (gen_load_toc_aix_si (dest
));
15160 emit_insn (gen_load_toc_aix_di (dest
));
15164 /* Emit instructions to restore the link register after determining where
15165 its value has been stored. */
15168 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
15170 rs6000_stack_t
*info
= rs6000_stack_info ();
15173 operands
[0] = source
;
15174 operands
[1] = scratch
;
15176 if (info
->lr_save_p
)
15178 rtx frame_rtx
= stack_pointer_rtx
;
15179 HOST_WIDE_INT sp_offset
= 0;
15182 if (frame_pointer_needed
15183 || cfun
->calls_alloca
15184 || info
->total_size
> 32767)
15186 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
15187 emit_move_insn (operands
[1], tmp
);
15188 frame_rtx
= operands
[1];
15190 else if (info
->push_p
)
15191 sp_offset
= info
->total_size
;
15193 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
15194 tmp
= gen_frame_mem (Pmode
, tmp
);
15195 emit_move_insn (tmp
, operands
[0]);
15198 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
15201 static GTY(()) alias_set_type set
= -1;
15204 get_TOC_alias_set (void)
15207 set
= new_alias_set ();
15211 /* This returns nonzero if the current function uses the TOC. This is
15212 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15213 is generated by the ABI_V4 load_toc_* patterns. */
15220 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15223 rtx pat
= PATTERN (insn
);
15226 if (GET_CODE (pat
) == PARALLEL
)
15227 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15229 rtx sub
= XVECEXP (pat
, 0, i
);
15230 if (GET_CODE (sub
) == USE
)
15232 sub
= XEXP (sub
, 0);
15233 if (GET_CODE (sub
) == UNSPEC
15234 && XINT (sub
, 1) == UNSPEC_TOC
)
15244 create_TOC_reference (rtx symbol
)
15246 if (!can_create_pseudo_p ())
15247 df_set_regs_ever_live (TOC_REGISTER
, true);
15248 return gen_rtx_PLUS (Pmode
,
15249 gen_rtx_REG (Pmode
, TOC_REGISTER
),
15250 gen_rtx_CONST (Pmode
,
15251 gen_rtx_MINUS (Pmode
, symbol
,
15252 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
15255 /* If _Unwind_* has been called from within the same module,
15256 toc register is not guaranteed to be saved to 40(1) on function
15257 entry. Save it there in that case. */
15260 rs6000_aix_emit_builtin_unwind_init (void)
15263 rtx stack_top
= gen_reg_rtx (Pmode
);
15264 rtx opcode_addr
= gen_reg_rtx (Pmode
);
15265 rtx opcode
= gen_reg_rtx (SImode
);
15266 rtx tocompare
= gen_reg_rtx (SImode
);
15267 rtx no_toc_save_needed
= gen_label_rtx ();
15269 mem
= gen_frame_mem (Pmode
, hard_frame_pointer_rtx
);
15270 emit_move_insn (stack_top
, mem
);
15272 mem
= gen_frame_mem (Pmode
,
15273 gen_rtx_PLUS (Pmode
, stack_top
,
15274 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
15275 emit_move_insn (opcode_addr
, mem
);
15276 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
15277 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
15278 : 0xE8410028, SImode
));
15280 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
15281 SImode
, NULL_RTX
, NULL_RTX
,
15282 no_toc_save_needed
);
15284 mem
= gen_frame_mem (Pmode
,
15285 gen_rtx_PLUS (Pmode
, stack_top
,
15286 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
15287 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
15288 emit_label (no_toc_save_needed
);
15291 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15292 and the change to the stack pointer. */
15295 rs6000_emit_stack_tie (void)
15297 rtx mem
= gen_frame_mem (BLKmode
,
15298 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
15300 emit_insn (gen_stack_tie (mem
));
15303 /* Emit the correct code for allocating stack space, as insns.
15304 If COPY_R12, make sure a copy of the old frame is left in r12.
15305 If COPY_R11, make sure a copy of the old frame is left in r11,
15306 in preference to r12 if COPY_R12.
15307 The generated code may use hard register 0 as a temporary. */
15310 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
, int copy_r11
)
15313 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15314 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
15315 rtx todec
= gen_int_mode (-size
, Pmode
);
15317 if (INTVAL (todec
) != -size
)
15319 warning (0, "stack frame too large");
15320 emit_insn (gen_trap ());
15324 if (crtl
->limit_stack
)
15326 if (REG_P (stack_limit_rtx
)
15327 && REGNO (stack_limit_rtx
) > 1
15328 && REGNO (stack_limit_rtx
) <= 31)
15330 emit_insn (TARGET_32BIT
15331 ? gen_addsi3 (tmp_reg
,
15334 : gen_adddi3 (tmp_reg
,
15338 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15341 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
15343 && DEFAULT_ABI
== ABI_V4
)
15345 rtx toload
= gen_rtx_CONST (VOIDmode
,
15346 gen_rtx_PLUS (Pmode
,
15350 emit_insn (gen_elf_high (tmp_reg
, toload
));
15351 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
15352 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15356 warning (0, "stack limit expression is not supported");
15359 if (copy_r12
|| copy_r11
|| ! TARGET_UPDATE
)
15360 emit_move_insn (copy_r11
15361 ? gen_rtx_REG (Pmode
, 11)
15362 : gen_rtx_REG (Pmode
, 12),
15369 /* Need a note here so that try_split doesn't get confused. */
15370 if (get_last_insn () == NULL_RTX
)
15371 emit_note (NOTE_INSN_DELETED
);
15372 insn
= emit_move_insn (tmp_reg
, todec
);
15373 try_split (PATTERN (insn
), insn
, 0);
15377 insn
= emit_insn (TARGET_32BIT
15378 ? gen_movsi_update (stack_reg
, stack_reg
,
15380 : gen_movdi_di_update (stack_reg
, stack_reg
,
15381 todec
, stack_reg
));
15385 insn
= emit_insn (TARGET_32BIT
15386 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
15387 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
15388 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
15390 ? gen_rtx_REG (Pmode
, 11)
15391 : gen_rtx_REG (Pmode
, 12));
15394 RTX_FRAME_RELATED_P (insn
) = 1;
15396 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15397 gen_rtx_SET (VOIDmode
, stack_reg
,
15398 gen_rtx_PLUS (Pmode
, stack_reg
,
15403 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15404 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15405 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15406 deduce these equivalences by itself so it wasn't necessary to hold
15407 its hand so much. */
15410 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
15411 rtx reg2
, rtx rreg
)
15415 /* copy_rtx will not make unique copies of registers, so we need to
15416 ensure we don't have unwanted sharing here. */
15418 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15421 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15423 real
= copy_rtx (PATTERN (insn
));
15425 if (reg2
!= NULL_RTX
)
15426 real
= replace_rtx (real
, reg2
, rreg
);
15428 real
= replace_rtx (real
, reg
,
15429 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
15430 STACK_POINTER_REGNUM
),
15433 /* We expect that 'real' is either a SET or a PARALLEL containing
15434 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15435 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15437 if (GET_CODE (real
) == SET
)
15441 temp
= simplify_rtx (SET_SRC (set
));
15443 SET_SRC (set
) = temp
;
15444 temp
= simplify_rtx (SET_DEST (set
));
15446 SET_DEST (set
) = temp
;
15447 if (GET_CODE (SET_DEST (set
)) == MEM
)
15449 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15451 XEXP (SET_DEST (set
), 0) = temp
;
15458 gcc_assert (GET_CODE (real
) == PARALLEL
);
15459 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
15460 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
15462 rtx set
= XVECEXP (real
, 0, i
);
15464 temp
= simplify_rtx (SET_SRC (set
));
15466 SET_SRC (set
) = temp
;
15467 temp
= simplify_rtx (SET_DEST (set
));
15469 SET_DEST (set
) = temp
;
15470 if (GET_CODE (SET_DEST (set
)) == MEM
)
15472 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15474 XEXP (SET_DEST (set
), 0) = temp
;
15476 RTX_FRAME_RELATED_P (set
) = 1;
15480 RTX_FRAME_RELATED_P (insn
) = 1;
15481 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15486 /* Returns an insn that has a vrsave set operation with the
15487 appropriate CLOBBERs. */
15490 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
15493 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
15494 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
15497 = gen_rtx_SET (VOIDmode
,
15499 gen_rtx_UNSPEC_VOLATILE (SImode
,
15500 gen_rtvec (2, reg
, vrsave
),
15501 UNSPECV_SET_VRSAVE
));
15505 /* We need to clobber the registers in the mask so the scheduler
15506 does not move sets to VRSAVE before sets of AltiVec registers.
15508 However, if the function receives nonlocal gotos, reload will set
15509 all call saved registers live. We will end up with:
15511 (set (reg 999) (mem))
15512 (parallel [ (set (reg vrsave) (unspec blah))
15513 (clobber (reg 999))])
15515 The clobber will cause the store into reg 999 to be dead, and
15516 flow will attempt to delete an epilogue insn. In this case, we
15517 need an unspec use/set of the register. */
15519 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
15520 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
15522 if (!epiloguep
|| call_used_regs
[i
])
15523 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
15524 gen_rtx_REG (V4SImode
, i
));
15527 rtx reg
= gen_rtx_REG (V4SImode
, i
);
15530 = gen_rtx_SET (VOIDmode
,
15532 gen_rtx_UNSPEC (V4SImode
,
15533 gen_rtvec (1, reg
), 27));
15537 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
15539 for (i
= 0; i
< nclobs
; ++i
)
15540 XVECEXP (insn
, 0, i
) = clobs
[i
];
15545 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15546 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15549 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
15550 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
15552 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
15553 rtx replacea
, replaceb
;
15555 int_rtx
= GEN_INT (offset
);
15557 /* Some cases that need register indexed addressing. */
15558 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
15559 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
15561 && SPE_VECTOR_MODE (mode
)
15562 && !SPE_CONST_OFFSET_OK (offset
)))
15564 /* Whomever calls us must make sure r11 is available in the
15565 flow path of instructions in the prologue. */
15566 offset_rtx
= gen_rtx_REG (Pmode
, 11);
15567 emit_move_insn (offset_rtx
, int_rtx
);
15569 replacea
= offset_rtx
;
15570 replaceb
= int_rtx
;
15574 offset_rtx
= int_rtx
;
15575 replacea
= NULL_RTX
;
15576 replaceb
= NULL_RTX
;
15579 reg
= gen_rtx_REG (mode
, regno
);
15580 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
15581 mem
= gen_frame_mem (mode
, addr
);
15583 insn
= emit_move_insn (mem
, reg
);
15585 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
15588 /* Emit an offset memory reference suitable for a frame store, while
15589 converting to a valid addressing mode. */
15592 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
15594 rtx int_rtx
, offset_rtx
;
15596 int_rtx
= GEN_INT (offset
);
15598 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
15599 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
15601 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
15602 emit_move_insn (offset_rtx
, int_rtx
);
15605 offset_rtx
= int_rtx
;
15607 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
15610 /* Look for user-defined global regs. We should not save and restore these,
15611 and cannot use stmw/lmw if there are any in its range. */
15614 no_global_regs_above (int first
, bool gpr
)
15617 for (i
= first
; i
< gpr
? 32 : 64 ; i
++)
15618 if (global_regs
[i
])
15623 #ifndef TARGET_FIX_AND_CONTINUE
15624 #define TARGET_FIX_AND_CONTINUE 0
15627 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
15628 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
15629 #define LAST_SAVRES_REGISTER 31
15630 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
15632 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][8];
15634 /* Return the symbol for an out-of-line register save/restore routine.
15635 We are saving/restoring GPRs if GPR is true. */
15638 rs6000_savres_routine_sym (rs6000_stack_t
*info
, bool savep
, bool gpr
, bool exitp
)
15640 int regno
= gpr
? info
->first_gp_reg_save
: (info
->first_fp_reg_save
- 32);
15642 int select
= ((savep
? 1 : 0) << 2
15644 /* On the SPE, we never have any FPRs, but we do have
15645 32/64-bit versions of the routines. */
15646 ? (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
? 1 : 0)
15650 /* Don't generate bogus routine names. */
15651 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
&& regno
<= LAST_SAVRES_REGISTER
);
15653 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
15658 const char *action
;
15659 const char *regkind
;
15660 const char *exit_suffix
;
15662 action
= savep
? "save" : "rest";
15664 /* SPE has slightly different names for its routines depending on
15665 whether we are saving 32-bit or 64-bit registers. */
15666 if (TARGET_SPE_ABI
)
15668 /* No floating point saves on the SPE. */
15671 regkind
= info
->spe_64bit_regs_used
? "64gpr" : "32gpr";
15674 regkind
= gpr
? "gpr" : "fpr";
15676 exit_suffix
= exitp
? "_x" : "";
15678 sprintf (name
, "_%s%s_%d%s", action
, regkind
, regno
, exit_suffix
);
15680 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
15681 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
15687 /* Emit a sequence of insns, including a stack tie if needed, for
15688 resetting the stack pointer. If SAVRES is true, then don't reset the
15689 stack pointer, but move the base of the frame into r11 for use by
15690 out-of-line register restore routines. */
15693 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
15694 rtx sp_reg_rtx
, rtx frame_reg_rtx
,
15695 int sp_offset
, bool savres
)
15697 /* This blockage is needed so that sched doesn't decide to move
15698 the sp change before the register restores. */
15699 if (frame_reg_rtx
!= sp_reg_rtx
15701 && info
->spe_64bit_regs_used
!= 0
15702 && info
->first_gp_reg_save
!= 32))
15703 rs6000_emit_stack_tie ();
15705 if (frame_reg_rtx
!= sp_reg_rtx
)
15707 rs6000_emit_stack_tie ();
15708 if (sp_offset
!= 0)
15709 emit_insn (gen_addsi3 (sp_reg_rtx
, frame_reg_rtx
,
15710 GEN_INT (sp_offset
)));
15712 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
15714 else if (sp_offset
!= 0)
15716 /* If we are restoring registers out-of-line, we will be using the
15717 "exit" variants of the restore routines, which will reset the
15718 stack for us. But we do need to point r11 into the right place
15719 for those routines. */
15720 rtx dest_reg
= (savres
15721 ? gen_rtx_REG (Pmode
, 11)
15724 emit_insn (TARGET_32BIT
15725 ? gen_addsi3 (dest_reg
, sp_reg_rtx
,
15726 GEN_INT (sp_offset
))
15727 : gen_adddi3 (dest_reg
, sp_reg_rtx
,
15728 GEN_INT (sp_offset
)));
15732 /* Construct a parallel rtx describing the effect of a call to an
15733 out-of-line register save/restore routine. */
15736 rs6000_make_savres_rtx (rs6000_stack_t
*info
,
15737 rtx frame_reg_rtx
, int save_area_offset
,
15738 enum machine_mode reg_mode
,
15739 bool savep
, bool gpr
, bool exitp
)
15742 int offset
, start_reg
, end_reg
, n_regs
;
15743 int reg_size
= GET_MODE_SIZE (reg_mode
);
15749 ? info
->first_gp_reg_save
15750 : info
->first_fp_reg_save
);
15751 end_reg
= gpr
? 32 : 64;
15752 n_regs
= end_reg
- start_reg
;
15753 p
= rtvec_alloc ((exitp
? 4 : 3) + n_regs
);
15755 /* If we're saving registers, then we should never say we're exiting. */
15756 gcc_assert ((savep
&& !exitp
) || !savep
);
15759 RTVEC_ELT (p
, offset
++) = gen_rtx_RETURN (VOIDmode
);
15761 RTVEC_ELT (p
, offset
++)
15762 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 65));
15764 sym
= rs6000_savres_routine_sym (info
, savep
, gpr
, exitp
);
15765 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
15766 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 11));
15768 for (i
= 0; i
< end_reg
- start_reg
; i
++)
15770 rtx addr
, reg
, mem
;
15771 reg
= gen_rtx_REG (reg_mode
, start_reg
+ i
);
15772 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15773 GEN_INT (save_area_offset
+ reg_size
*i
));
15774 mem
= gen_frame_mem (reg_mode
, addr
);
15776 RTVEC_ELT (p
, i
+ offset
) = gen_rtx_SET (VOIDmode
,
15778 savep
? reg
: mem
);
15781 return gen_rtx_PARALLEL (VOIDmode
, p
);
15784 /* Determine whether the gp REG is really used. */
15787 rs6000_reg_live_or_pic_offset_p (int reg
)
15789 return ((df_regs_ever_live_p (reg
)
15790 && (!call_used_regs
[reg
]
15791 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15792 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
15793 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15794 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
15795 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
15799 SAVRES_MULTIPLE
= 0x1,
15800 SAVRES_INLINE_FPRS
= 0x2,
15801 SAVRES_INLINE_GPRS
= 0x4
15804 /* Determine the strategy for savings/restoring registers. */
15807 rs6000_savres_strategy (rs6000_stack_t
*info
, bool savep
,
15808 int using_static_chain_p
, int sibcall
)
15810 bool using_multiple_p
;
15812 bool savres_fprs_inline
;
15813 bool savres_gprs_inline
;
15814 bool noclobber_global_gprs
15815 = no_global_regs_above (info
->first_gp_reg_save
, /*gpr=*/true);
15817 using_multiple_p
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
15818 && (!TARGET_SPE_ABI
15819 || info
->spe_64bit_regs_used
== 0)
15820 && info
->first_gp_reg_save
< 31
15821 && noclobber_global_gprs
);
15822 /* Don't bother to try to save things out-of-line if r11 is occupied
15823 by the static chain. It would require too much fiddling and the
15824 static chain is rarely used anyway. */
15825 common
= (using_static_chain_p
15827 || crtl
->calls_eh_return
15828 || !info
->lr_save_p
15829 || cfun
->machine
->ra_need_lr
15830 || info
->total_size
> 32767);
15831 savres_fprs_inline
= (common
15832 || info
->first_fp_reg_save
== 64
15833 || !no_global_regs_above (info
->first_fp_reg_save
,
15835 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
15836 savres_gprs_inline
= (common
15837 /* Saving CR interferes with the exit routines
15838 used on the SPE, so just punt here. */
15841 && info
->spe_64bit_regs_used
!= 0
15842 && info
->cr_save_p
!= 0)
15843 || info
->first_gp_reg_save
== 32
15844 || !noclobber_global_gprs
15845 || GP_SAVE_INLINE (info
->first_gp_reg_save
));
15848 /* If we are going to use store multiple, then don't even bother
15849 with the out-of-line routines, since the store-multiple instruction
15850 will always be smaller. */
15851 savres_gprs_inline
= savres_gprs_inline
|| using_multiple_p
;
15854 /* The situation is more complicated with load multiple. We'd
15855 prefer to use the out-of-line routines for restores, since the
15856 "exit" out-of-line routines can handle the restore of LR and
15857 the frame teardown. But we can only use the out-of-line
15858 routines if we know that we've used store multiple or
15859 out-of-line routines in the prologue, i.e. if we've saved all
15860 the registers from first_gp_reg_save. Otherwise, we risk
15861 loading garbage from the stack. Furthermore, we can only use
15862 the "exit" out-of-line gpr restore if we haven't saved any
15864 bool saved_all
= !savres_gprs_inline
|| using_multiple_p
;
15866 if (saved_all
&& info
->first_fp_reg_save
!= 64)
15867 /* We can't use the exit routine; use load multiple if it's
15869 savres_gprs_inline
= savres_gprs_inline
|| using_multiple_p
;
15872 return (using_multiple_p
15873 | (savres_fprs_inline
<< 1)
15874 | (savres_gprs_inline
<< 2));
15877 /* Emit function prologue as insns. */
15880 rs6000_emit_prologue (void)
15882 rs6000_stack_t
*info
= rs6000_stack_info ();
15883 enum machine_mode reg_mode
= Pmode
;
15884 int reg_size
= TARGET_32BIT
? 4 : 8;
15885 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15886 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
15887 rtx frame_reg_rtx
= sp_reg_rtx
;
15888 rtx cr_save_rtx
= NULL_RTX
;
15891 int saving_FPRs_inline
;
15892 int saving_GPRs_inline
;
15893 int using_store_multiple
;
15894 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
15895 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
15896 && !call_used_regs
[STATIC_CHAIN_REGNUM
]);
15897 HOST_WIDE_INT sp_offset
= 0;
15899 if (TARGET_FIX_AND_CONTINUE
)
15901 /* gdb on darwin arranges to forward a function from the old
15902 address by modifying the first 5 instructions of the function
15903 to branch to the overriding function. This is necessary to
15904 permit function pointers that point to the old function to
15905 actually forward to the new function. */
15906 emit_insn (gen_nop ());
15907 emit_insn (gen_nop ());
15908 emit_insn (gen_nop ());
15909 emit_insn (gen_nop ());
15910 emit_insn (gen_nop ());
15913 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
15915 reg_mode
= V2SImode
;
15919 strategy
= rs6000_savres_strategy (info
, /*savep=*/true,
15920 /*static_chain_p=*/using_static_chain_p
,
15922 using_store_multiple
= strategy
& SAVRES_MULTIPLE
;
15923 saving_FPRs_inline
= strategy
& SAVRES_INLINE_FPRS
;
15924 saving_GPRs_inline
= strategy
& SAVRES_INLINE_GPRS
;
15926 /* For V.4, update stack before we do any saving and set back pointer. */
15927 if (! WORLD_SAVE_P (info
)
15929 && (DEFAULT_ABI
== ABI_V4
15930 || crtl
->calls_eh_return
))
15932 bool need_r11
= (TARGET_SPE
15933 ? (!saving_GPRs_inline
15934 && info
->spe_64bit_regs_used
== 0)
15935 : (!saving_FPRs_inline
|| !saving_GPRs_inline
));
15936 if (info
->total_size
< 32767)
15937 sp_offset
= info
->total_size
;
15939 frame_reg_rtx
= (need_r11
15940 ? gen_rtx_REG (Pmode
, 11)
15942 rs6000_emit_allocate_stack (info
->total_size
,
15943 (frame_reg_rtx
!= sp_reg_rtx
15944 && (info
->cr_save_p
15946 || info
->first_fp_reg_save
< 64
15947 || info
->first_gp_reg_save
< 32
15950 if (frame_reg_rtx
!= sp_reg_rtx
)
15951 rs6000_emit_stack_tie ();
15954 /* Handle world saves specially here. */
15955 if (WORLD_SAVE_P (info
))
15962 /* save_world expects lr in r0. */
15963 reg0
= gen_rtx_REG (Pmode
, 0);
15964 if (info
->lr_save_p
)
15966 insn
= emit_move_insn (reg0
,
15967 gen_rtx_REG (Pmode
, LR_REGNO
));
15968 RTX_FRAME_RELATED_P (insn
) = 1;
15971 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15972 assumptions about the offsets of various bits of the stack
15974 gcc_assert (info
->gp_save_offset
== -220
15975 && info
->fp_save_offset
== -144
15976 && info
->lr_save_offset
== 8
15977 && info
->cr_save_offset
== 4
15980 && (!crtl
->calls_eh_return
15981 || info
->ehrd_offset
== -432)
15982 && info
->vrsave_save_offset
== -224
15983 && info
->altivec_save_offset
== -416);
15985 treg
= gen_rtx_REG (SImode
, 11);
15986 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
15988 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15989 in R11. It also clobbers R12, so beware! */
15991 /* Preserve CR2 for save_world prologues */
15993 sz
+= 32 - info
->first_gp_reg_save
;
15994 sz
+= 64 - info
->first_fp_reg_save
;
15995 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
15996 p
= rtvec_alloc (sz
);
15998 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
15999 gen_rtx_REG (SImode
,
16001 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16002 gen_rtx_SYMBOL_REF (Pmode
,
16004 /* We do floats first so that the instruction pattern matches
16006 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16008 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
16009 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16010 GEN_INT (info
->fp_save_offset
16011 + sp_offset
+ 8 * i
));
16012 rtx mem
= gen_frame_mem (DFmode
, addr
);
16014 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16016 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16018 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16019 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16020 GEN_INT (info
->altivec_save_offset
16021 + sp_offset
+ 16 * i
));
16022 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16024 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16026 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16028 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16029 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16030 GEN_INT (info
->gp_save_offset
16031 + sp_offset
+ reg_size
* i
));
16032 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16034 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16038 /* CR register traditionally saved as CR2. */
16039 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16040 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16041 GEN_INT (info
->cr_save_offset
16043 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16045 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16047 /* Explain about use of R0. */
16048 if (info
->lr_save_p
)
16050 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16051 GEN_INT (info
->lr_save_offset
16053 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16055 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg0
);
16057 /* Explain what happens to the stack pointer. */
16059 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
16060 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
16063 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16064 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16065 treg
, GEN_INT (-info
->total_size
));
16066 sp_offset
= info
->total_size
;
16069 /* If we use the link register, get it into r0. */
16070 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
16072 rtx addr
, reg
, mem
;
16074 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
16075 gen_rtx_REG (Pmode
, LR_REGNO
));
16076 RTX_FRAME_RELATED_P (insn
) = 1;
16078 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16079 GEN_INT (info
->lr_save_offset
+ sp_offset
));
16080 reg
= gen_rtx_REG (Pmode
, 0);
16081 mem
= gen_rtx_MEM (Pmode
, addr
);
16082 /* This should not be of rs6000_sr_alias_set, because of
16083 __builtin_return_address. */
16085 insn
= emit_move_insn (mem
, reg
);
16086 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16087 NULL_RTX
, NULL_RTX
);
16090 /* If we need to save CR, put it into r12. */
16091 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
16095 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
16096 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16097 RTX_FRAME_RELATED_P (insn
) = 1;
16098 /* Now, there's no way that dwarf2out_frame_debug_expr is going
16099 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
16100 But that's OK. All we have to do is specify that _one_ condition
16101 code register is saved in this stack slot. The thrower's epilogue
16102 will then restore all the call-saved registers.
16103 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
16104 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
16105 gen_rtx_REG (SImode
, CR2_REGNO
));
16106 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
16111 /* Do any required saving of fpr's. If only one or two to save, do
16112 it ourselves. Otherwise, call function. */
16113 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
16116 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16117 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
16118 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
16119 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
16120 info
->first_fp_reg_save
+ i
,
16121 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
16124 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
16128 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
16129 info
->fp_save_offset
+ sp_offset
,
16131 /*savep=*/true, /*gpr=*/false,
16133 insn
= emit_insn (par
);
16134 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16135 NULL_RTX
, NULL_RTX
);
16138 /* Save GPRs. This is done as a PARALLEL if we are using
16139 the store-multiple instructions. */
16140 if (!WORLD_SAVE_P (info
)
16142 && info
->spe_64bit_regs_used
!= 0
16143 && info
->first_gp_reg_save
!= 32)
16146 rtx spe_save_area_ptr
;
16148 /* Determine whether we can address all of the registers that need
16149 to be saved with an offset from the stack pointer that fits in
16150 the small const field for SPE memory instructions. */
16151 int spe_regs_addressable_via_sp
16152 = (SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
16153 + (32 - info
->first_gp_reg_save
- 1) * reg_size
)
16154 && saving_GPRs_inline
);
16157 if (spe_regs_addressable_via_sp
)
16159 spe_save_area_ptr
= frame_reg_rtx
;
16160 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
16164 /* Make r11 point to the start of the SPE save area. We need
16165 to be careful here if r11 is holding the static chain. If
16166 it is, then temporarily save it in r0. We would use r0 as
16167 our base register here, but using r0 as a base register in
16168 loads and stores means something different from what we
16170 int ool_adjust
= (saving_GPRs_inline
16172 : (info
->first_gp_reg_save
16173 - (FIRST_SAVRES_REGISTER
+1))*8);
16174 HOST_WIDE_INT offset
= (info
->spe_gp_save_offset
16175 + sp_offset
- ool_adjust
);
16177 if (using_static_chain_p
)
16179 rtx r0
= gen_rtx_REG (Pmode
, 0);
16180 gcc_assert (info
->first_gp_reg_save
> 11);
16182 emit_move_insn (r0
, gen_rtx_REG (Pmode
, 11));
16185 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
16186 insn
= emit_insn (gen_addsi3 (spe_save_area_ptr
,
16188 GEN_INT (offset
)));
16189 /* We need to make sure the move to r11 gets noted for
16190 properly outputting unwind information. */
16191 if (!saving_GPRs_inline
)
16192 rs6000_frame_related (insn
, frame_reg_rtx
, offset
,
16193 NULL_RTX
, NULL_RTX
);
16197 if (saving_GPRs_inline
)
16199 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16200 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16202 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16203 rtx offset
, addr
, mem
;
16205 /* We're doing all this to ensure that the offset fits into
16206 the immediate offset of 'evstdd'. */
16207 gcc_assert (SPE_CONST_OFFSET_OK (reg_size
* i
+ spe_offset
));
16209 offset
= GEN_INT (reg_size
* i
+ spe_offset
);
16210 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
16211 mem
= gen_rtx_MEM (V2SImode
, addr
);
16213 insn
= emit_move_insn (mem
, reg
);
16215 rs6000_frame_related (insn
, spe_save_area_ptr
,
16216 info
->spe_gp_save_offset
16217 + sp_offset
+ reg_size
* i
,
16218 offset
, const0_rtx
);
16225 par
= rs6000_make_savres_rtx (info
, gen_rtx_REG (Pmode
, 11),
16227 /*savep=*/true, /*gpr=*/true,
16229 insn
= emit_insn (par
);
16230 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16231 NULL_RTX
, NULL_RTX
);
16235 /* Move the static chain pointer back. */
16236 if (using_static_chain_p
&& !spe_regs_addressable_via_sp
)
16237 emit_move_insn (gen_rtx_REG (Pmode
, 11), gen_rtx_REG (Pmode
, 0));
16239 else if (!WORLD_SAVE_P (info
) && !saving_GPRs_inline
)
16243 /* Need to adjust r11 if we saved any FPRs. */
16244 if (info
->first_fp_reg_save
!= 64)
16246 rtx r11
= gen_rtx_REG (reg_mode
, 11);
16247 rtx offset
= GEN_INT (info
->total_size
16248 + (-8 * (64-info
->first_fp_reg_save
)));
16249 rtx ptr_reg
= (sp_reg_rtx
== frame_reg_rtx
16250 ? sp_reg_rtx
: r11
);
16252 emit_insn (TARGET_32BIT
16253 ? gen_addsi3 (r11
, ptr_reg
, offset
)
16254 : gen_adddi3 (r11
, ptr_reg
, offset
));
16257 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
16258 info
->gp_save_offset
+ sp_offset
,
16260 /*savep=*/true, /*gpr=*/true,
16262 insn
= emit_insn (par
);
16263 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16264 NULL_RTX
, NULL_RTX
);
16266 else if (!WORLD_SAVE_P (info
) && using_store_multiple
)
16270 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
16271 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16273 rtx addr
, reg
, mem
;
16274 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16275 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16276 GEN_INT (info
->gp_save_offset
16279 mem
= gen_frame_mem (reg_mode
, addr
);
16281 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
16283 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16284 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16285 NULL_RTX
, NULL_RTX
);
16287 else if (!WORLD_SAVE_P (info
))
16290 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16291 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16293 rtx addr
, reg
, mem
;
16294 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16296 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16297 GEN_INT (info
->gp_save_offset
16300 mem
= gen_frame_mem (reg_mode
, addr
);
16302 insn
= emit_move_insn (mem
, reg
);
16303 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16304 NULL_RTX
, NULL_RTX
);
16308 /* ??? There's no need to emit actual instructions here, but it's the
16309 easiest way to get the frame unwind information emitted. */
16310 if (crtl
->calls_eh_return
)
16312 unsigned int i
, regno
;
16314 /* In AIX ABI we need to pretend we save r2 here. */
16317 rtx addr
, reg
, mem
;
16319 reg
= gen_rtx_REG (reg_mode
, 2);
16320 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16321 GEN_INT (sp_offset
+ 5 * reg_size
));
16322 mem
= gen_frame_mem (reg_mode
, addr
);
16324 insn
= emit_move_insn (mem
, reg
);
16325 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16326 NULL_RTX
, NULL_RTX
);
16327 PATTERN (insn
) = gen_blockage ();
16332 regno
= EH_RETURN_DATA_REGNO (i
);
16333 if (regno
== INVALID_REGNUM
)
16336 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
16337 info
->ehrd_offset
+ sp_offset
16338 + reg_size
* (int) i
,
16343 /* Save CR if we use any that must be preserved. */
16344 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
16346 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16347 GEN_INT (info
->cr_save_offset
+ sp_offset
));
16348 rtx mem
= gen_frame_mem (SImode
, addr
);
16349 /* See the large comment above about why CR2_REGNO is used. */
16350 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
16352 /* If r12 was used to hold the original sp, copy cr into r0 now
16354 if (REGNO (frame_reg_rtx
) == 12)
16358 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
16359 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16360 RTX_FRAME_RELATED_P (insn
) = 1;
16361 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
16362 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
16367 insn
= emit_move_insn (mem
, cr_save_rtx
);
16369 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16370 NULL_RTX
, NULL_RTX
);
16373 /* Update stack and set back pointer unless this is V.4,
16374 for which it was done previously. */
16375 if (!WORLD_SAVE_P (info
) && info
->push_p
16376 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
16378 if (info
->total_size
< 32767)
16379 sp_offset
= info
->total_size
;
16381 frame_reg_rtx
= frame_ptr_rtx
;
16382 rs6000_emit_allocate_stack (info
->total_size
,
16383 (frame_reg_rtx
!= sp_reg_rtx
16384 && ((info
->altivec_size
!= 0)
16385 || (info
->vrsave_mask
!= 0)
16388 if (frame_reg_rtx
!= sp_reg_rtx
)
16389 rs6000_emit_stack_tie ();
16392 /* Set frame pointer, if needed. */
16393 if (frame_pointer_needed
)
16395 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
16397 RTX_FRAME_RELATED_P (insn
) = 1;
16400 /* Save AltiVec registers if needed. Save here because the red zone does
16401 not include AltiVec registers. */
16402 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
16406 /* There should be a non inline version of this, for when we
16407 are saving lots of vector registers. */
16408 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16409 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16411 rtx areg
, savereg
, mem
;
16414 offset
= info
->altivec_save_offset
+ sp_offset
16415 + 16 * (i
- info
->first_altivec_reg_save
);
16417 savereg
= gen_rtx_REG (V4SImode
, i
);
16419 areg
= gen_rtx_REG (Pmode
, 0);
16420 emit_move_insn (areg
, GEN_INT (offset
));
16422 /* AltiVec addressing mode is [reg+reg]. */
16423 mem
= gen_frame_mem (V4SImode
,
16424 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
16426 insn
= emit_move_insn (mem
, savereg
);
16428 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16429 areg
, GEN_INT (offset
));
16433 /* VRSAVE is a bit vector representing which AltiVec registers
16434 are used. The OS uses this to determine which vector
16435 registers to save on a context switch. We need to save
16436 VRSAVE on the stack frame, add whatever AltiVec registers we
16437 used in this function, and do the corresponding magic in the
16440 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
16441 && info
->vrsave_mask
!= 0)
16443 rtx reg
, mem
, vrsave
;
16446 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16447 as frame_reg_rtx and r11 as the static chain pointer for
16448 nested functions. */
16449 reg
= gen_rtx_REG (SImode
, 0);
16450 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
16452 emit_insn (gen_get_vrsave_internal (reg
));
16454 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
16456 if (!WORLD_SAVE_P (info
))
16459 offset
= info
->vrsave_save_offset
+ sp_offset
;
16460 mem
= gen_frame_mem (SImode
,
16461 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16462 GEN_INT (offset
)));
16463 insn
= emit_move_insn (mem
, reg
);
16466 /* Include the registers in the mask. */
16467 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
16469 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
16472 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16473 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
16474 || (DEFAULT_ABI
== ABI_V4
16475 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
16476 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
)))
16478 /* If emit_load_toc_table will use the link register, we need to save
16479 it. We use R12 for this purpose because emit_load_toc_table
16480 can use register 0. This allows us to use a plain 'blr' to return
16481 from the procedure more often. */
16482 int save_LR_around_toc_setup
= (TARGET_ELF
16483 && DEFAULT_ABI
!= ABI_AIX
16485 && ! info
->lr_save_p
16486 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
16487 if (save_LR_around_toc_setup
)
16489 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16491 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
16492 RTX_FRAME_RELATED_P (insn
) = 1;
16494 rs6000_emit_load_toc_table (TRUE
);
16496 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
16497 RTX_FRAME_RELATED_P (insn
) = 1;
16500 rs6000_emit_load_toc_table (TRUE
);
16504 if (DEFAULT_ABI
== ABI_DARWIN
16505 && flag_pic
&& crtl
->uses_pic_offset_table
)
16507 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16508 rtx src
= machopic_function_base_sym ();
16510 /* Save and restore LR locally around this call (in R0). */
16511 if (!info
->lr_save_p
)
16512 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
16514 emit_insn (gen_load_macho_picbase (src
));
16516 emit_move_insn (gen_rtx_REG (Pmode
,
16517 RS6000_PIC_OFFSET_TABLE_REGNUM
),
16520 if (!info
->lr_save_p
)
16521 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
16526 /* Write function prologue. */
16529 rs6000_output_function_prologue (FILE *file
,
16530 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
16532 rs6000_stack_t
*info
= rs6000_stack_info ();
16534 if (TARGET_DEBUG_STACK
)
16535 debug_stack_info (info
);
16537 /* Write .extern for any function we will call to save and restore
16539 if (info
->first_fp_reg_save
< 64
16540 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
16541 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16542 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
16543 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
16545 /* Write .extern for AIX common mode routines, if needed. */
16546 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
16548 fputs ("\t.extern __mulh\n", file
);
16549 fputs ("\t.extern __mull\n", file
);
16550 fputs ("\t.extern __divss\n", file
);
16551 fputs ("\t.extern __divus\n", file
);
16552 fputs ("\t.extern __quoss\n", file
);
16553 fputs ("\t.extern __quous\n", file
);
16554 common_mode_defined
= 1;
16557 if (! HAVE_prologue
)
16561 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16562 the "toplevel" insn chain. */
16563 emit_note (NOTE_INSN_DELETED
);
16564 rs6000_emit_prologue ();
16565 emit_note (NOTE_INSN_DELETED
);
16567 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16571 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16573 INSN_ADDRESSES_NEW (insn
, addr
);
16578 if (TARGET_DEBUG_STACK
)
16579 debug_rtx_list (get_insns (), 100);
16580 final (get_insns (), file
, FALSE
);
16584 rs6000_pic_labelno
++;
16587 /* Non-zero if vmx regs are restored before the frame pop, zero if
16588 we restore after the pop when possible. */
16589 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
16591 /* Reload CR from REG. */
16594 rs6000_restore_saved_cr (rtx reg
, int using_mfcr_multiple
)
16599 if (using_mfcr_multiple
)
16601 for (i
= 0; i
< 8; i
++)
16602 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16604 gcc_assert (count
);
16607 if (using_mfcr_multiple
&& count
> 1)
16612 p
= rtvec_alloc (count
);
16615 for (i
= 0; i
< 8; i
++)
16616 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16618 rtvec r
= rtvec_alloc (2);
16619 RTVEC_ELT (r
, 0) = reg
;
16620 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
16621 RTVEC_ELT (p
, ndx
) =
16622 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
16623 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
16626 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16627 gcc_assert (ndx
== count
);
16630 for (i
= 0; i
< 8; i
++)
16631 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16633 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
16639 /* Emit function epilogue as insns.
16641 At present, dwarf2out_frame_debug_expr doesn't understand
16642 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16643 anywhere in the epilogue. Most of the insns below would in any case
16644 need special notes to explain where r11 is in relation to the stack. */
16647 rs6000_emit_epilogue (int sibcall
)
16649 rs6000_stack_t
*info
;
16650 int restoring_GPRs_inline
;
16651 int restoring_FPRs_inline
;
16652 int using_load_multiple
;
16653 int using_mtcr_multiple
;
16654 int use_backchain_to_restore_sp
;
16658 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
16659 rtx frame_reg_rtx
= sp_reg_rtx
;
16660 enum machine_mode reg_mode
= Pmode
;
16661 int reg_size
= TARGET_32BIT
? 4 : 8;
16664 info
= rs6000_stack_info ();
16666 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
16668 reg_mode
= V2SImode
;
16672 strategy
= rs6000_savres_strategy (info
, /*savep=*/false,
16673 /*static_chain_p=*/0, sibcall
);
16674 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
16675 restoring_FPRs_inline
= strategy
& SAVRES_INLINE_FPRS
;
16676 restoring_GPRs_inline
= strategy
& SAVRES_INLINE_GPRS
;
16677 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
16678 || rs6000_cpu
== PROCESSOR_PPC603
16679 || rs6000_cpu
== PROCESSOR_PPC750
16681 /* Restore via the backchain when we have a large frame, since this
16682 is more efficient than an addis, addi pair. The second condition
16683 here will not trigger at the moment; We don't actually need a
16684 frame pointer for alloca, but the generic parts of the compiler
16685 give us one anyway. */
16686 use_backchain_to_restore_sp
= (info
->total_size
> 32767
16687 || info
->total_size
16688 + (info
->lr_save_p
? info
->lr_save_offset
: 0)
16690 || (cfun
->calls_alloca
16691 && !frame_pointer_needed
));
16692 restore_lr
= (info
->lr_save_p
16693 && restoring_GPRs_inline
16694 && restoring_FPRs_inline
);
16696 if (WORLD_SAVE_P (info
))
16700 const char *alloc_rname
;
16703 /* eh_rest_world_r10 will return to the location saved in the LR
16704 stack slot (which is not likely to be our caller.)
16705 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16706 rest_world is similar, except any R10 parameter is ignored.
16707 The exception-handling stuff that was here in 2.95 is no
16708 longer necessary. */
16712 + 32 - info
->first_gp_reg_save
16713 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
16714 + 63 + 1 - info
->first_fp_reg_save
);
16716 strcpy (rname
, ((crtl
->calls_eh_return
) ?
16717 "*eh_rest_world_r10" : "*rest_world"));
16718 alloc_rname
= ggc_strdup (rname
);
16721 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
16722 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16723 gen_rtx_REG (Pmode
,
16726 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
16727 /* The instruction pattern requires a clobber here;
16728 it is shared with the restVEC helper. */
16730 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
16733 /* CR register traditionally saved as CR2. */
16734 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16735 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16736 GEN_INT (info
->cr_save_offset
));
16737 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16739 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16742 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16744 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16745 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16746 GEN_INT (info
->gp_save_offset
16748 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16750 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16752 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16754 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16755 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16756 GEN_INT (info
->altivec_save_offset
16758 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16760 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16762 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
16764 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
16765 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16766 GEN_INT (info
->fp_save_offset
16768 rtx mem
= gen_frame_mem (DFmode
, addr
);
16770 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16773 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
16775 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
16777 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
16779 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
16781 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
16782 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16787 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16789 sp_offset
= info
->total_size
;
16791 /* Restore AltiVec registers if we must do so before adjusting the
16793 if (TARGET_ALTIVEC_ABI
16794 && info
->altivec_size
!= 0
16795 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16796 || (DEFAULT_ABI
!= ABI_V4
16797 && info
->altivec_save_offset
< (TARGET_32BIT
? -220 : -288))))
16801 if (use_backchain_to_restore_sp
)
16803 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16804 emit_move_insn (frame_reg_rtx
,
16805 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16808 else if (frame_pointer_needed
)
16809 frame_reg_rtx
= hard_frame_pointer_rtx
;
16811 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16812 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16814 rtx addr
, areg
, mem
;
16816 areg
= gen_rtx_REG (Pmode
, 0);
16818 (areg
, GEN_INT (info
->altivec_save_offset
16820 + 16 * (i
- info
->first_altivec_reg_save
)));
16822 /* AltiVec addressing mode is [reg+reg]. */
16823 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
16824 mem
= gen_frame_mem (V4SImode
, addr
);
16826 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
16830 /* Restore VRSAVE if we must do so before adjusting the stack. */
16832 && TARGET_ALTIVEC_VRSAVE
16833 && info
->vrsave_mask
!= 0
16834 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16835 || (DEFAULT_ABI
!= ABI_V4
16836 && info
->vrsave_save_offset
< (TARGET_32BIT
? -220 : -288))))
16838 rtx addr
, mem
, reg
;
16840 if (frame_reg_rtx
== sp_reg_rtx
)
16842 if (use_backchain_to_restore_sp
)
16844 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16845 emit_move_insn (frame_reg_rtx
,
16846 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16849 else if (frame_pointer_needed
)
16850 frame_reg_rtx
= hard_frame_pointer_rtx
;
16853 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16854 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
16855 mem
= gen_frame_mem (SImode
, addr
);
16856 reg
= gen_rtx_REG (SImode
, 12);
16857 emit_move_insn (reg
, mem
);
16859 emit_insn (generate_set_vrsave (reg
, info
, 1));
16862 /* If we have a large stack frame, restore the old stack pointer
16863 using the backchain. */
16864 if (use_backchain_to_restore_sp
)
16866 if (frame_reg_rtx
== sp_reg_rtx
)
16868 /* Under V.4, don't reset the stack pointer until after we're done
16869 loading the saved registers. */
16870 if (DEFAULT_ABI
== ABI_V4
)
16871 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16873 emit_move_insn (frame_reg_rtx
,
16874 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16877 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16878 && DEFAULT_ABI
== ABI_V4
)
16879 /* frame_reg_rtx has been set up by the altivec restore. */
16883 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
16884 frame_reg_rtx
= sp_reg_rtx
;
16887 /* If we have a frame pointer, we can restore the old stack pointer
16889 else if (frame_pointer_needed
)
16891 frame_reg_rtx
= sp_reg_rtx
;
16892 if (DEFAULT_ABI
== ABI_V4
)
16893 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16895 emit_insn (TARGET_32BIT
16896 ? gen_addsi3 (frame_reg_rtx
, hard_frame_pointer_rtx
,
16897 GEN_INT (info
->total_size
))
16898 : gen_adddi3 (frame_reg_rtx
, hard_frame_pointer_rtx
,
16899 GEN_INT (info
->total_size
)));
16902 else if (info
->push_p
16903 && DEFAULT_ABI
!= ABI_V4
16904 && !crtl
->calls_eh_return
)
16906 emit_insn (TARGET_32BIT
16907 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
16908 GEN_INT (info
->total_size
))
16909 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
16910 GEN_INT (info
->total_size
)));
16914 /* Restore AltiVec registers if we have not done so already. */
16915 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16916 && TARGET_ALTIVEC_ABI
16917 && info
->altivec_size
!= 0
16918 && (DEFAULT_ABI
== ABI_V4
16919 || info
->altivec_save_offset
>= (TARGET_32BIT
? -220 : -288)))
16923 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16924 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16926 rtx addr
, areg
, mem
;
16928 areg
= gen_rtx_REG (Pmode
, 0);
16930 (areg
, GEN_INT (info
->altivec_save_offset
16932 + 16 * (i
- info
->first_altivec_reg_save
)));
16934 /* AltiVec addressing mode is [reg+reg]. */
16935 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
16936 mem
= gen_frame_mem (V4SImode
, addr
);
16938 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
16942 /* Restore VRSAVE if we have not done so already. */
16943 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
16945 && TARGET_ALTIVEC_VRSAVE
16946 && info
->vrsave_mask
!= 0
16947 && (DEFAULT_ABI
== ABI_V4
16948 || info
->vrsave_save_offset
>= (TARGET_32BIT
? -220 : -288)))
16950 rtx addr
, mem
, reg
;
16952 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16953 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
16954 mem
= gen_frame_mem (SImode
, addr
);
16955 reg
= gen_rtx_REG (SImode
, 12);
16956 emit_move_insn (reg
, mem
);
16958 emit_insn (generate_set_vrsave (reg
, info
, 1));
16961 /* Get the old lr if we saved it. If we are restoring registers
16962 out-of-line, then the out-of-line routines can do this for us. */
16965 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
16966 info
->lr_save_offset
+ sp_offset
);
16968 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
16971 /* Get the old cr if we saved it. */
16972 if (info
->cr_save_p
)
16974 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16975 GEN_INT (info
->cr_save_offset
+ sp_offset
));
16976 rtx mem
= gen_frame_mem (SImode
, addr
);
16978 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
16981 /* Set LR here to try to overlap restores below. */
16983 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
16984 gen_rtx_REG (Pmode
, 0));
16986 /* Load exception handler data registers, if needed. */
16987 if (crtl
->calls_eh_return
)
16989 unsigned int i
, regno
;
16993 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16994 GEN_INT (sp_offset
+ 5 * reg_size
));
16995 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16997 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
17004 regno
= EH_RETURN_DATA_REGNO (i
);
17005 if (regno
== INVALID_REGNUM
)
17008 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
17009 info
->ehrd_offset
+ sp_offset
17010 + reg_size
* (int) i
);
17012 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
17016 /* Restore GPRs. This is done as a PARALLEL if we are using
17017 the load-multiple instructions. */
17019 && info
->spe_64bit_regs_used
!= 0
17020 && info
->first_gp_reg_save
!= 32)
17022 /* Determine whether we can address all of the registers that need
17023 to be saved with an offset from the stack pointer that fits in
17024 the small const field for SPE memory instructions. */
17025 int spe_regs_addressable_via_sp
17026 = (SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
17027 + (32 - info
->first_gp_reg_save
- 1) * reg_size
)
17028 && restoring_GPRs_inline
);
17031 if (spe_regs_addressable_via_sp
)
17032 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
17035 rtx old_frame_reg_rtx
= frame_reg_rtx
;
17036 /* Make r11 point to the start of the SPE save area. We worried about
17037 not clobbering it when we were saving registers in the prologue.
17038 There's no need to worry here because the static chain is passed
17039 anew to every function. */
17040 int ool_adjust
= (restoring_GPRs_inline
17042 : (info
->first_gp_reg_save
17043 - (FIRST_SAVRES_REGISTER
+1))*8);
17045 if (frame_reg_rtx
== sp_reg_rtx
)
17046 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
17047 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
17048 GEN_INT (info
->spe_gp_save_offset
17051 /* Keep the invariant that frame_reg_rtx + sp_offset points
17052 at the top of the stack frame. */
17053 sp_offset
= -info
->spe_gp_save_offset
;
17058 if (restoring_GPRs_inline
)
17060 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17061 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
17063 rtx offset
, addr
, mem
;
17065 /* We're doing all this to ensure that the immediate offset
17066 fits into the immediate field of 'evldd'. */
17067 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
17069 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
17070 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
17071 mem
= gen_rtx_MEM (V2SImode
, addr
);
17073 emit_move_insn (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
17081 par
= rs6000_make_savres_rtx (info
, gen_rtx_REG (Pmode
, 11),
17083 /*savep=*/false, /*gpr=*/true,
17085 emit_jump_insn (par
);
17087 /* We don't want anybody else emitting things after we jumped
17092 else if (!restoring_GPRs_inline
)
17094 /* We are jumping to an out-of-line function. */
17095 bool can_use_exit
= info
->first_fp_reg_save
== 64;
17098 /* Emit stack reset code if we need it. */
17100 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
17101 sp_offset
, can_use_exit
);
17103 emit_insn (gen_addsi3 (gen_rtx_REG (Pmode
, 11),
17105 GEN_INT (sp_offset
- info
->fp_size
)));
17107 par
= rs6000_make_savres_rtx (info
, frame_reg_rtx
,
17108 info
->gp_save_offset
, reg_mode
,
17109 /*savep=*/false, /*gpr=*/true,
17110 /*exitp=*/can_use_exit
);
17114 if (info
->cr_save_p
)
17115 rs6000_restore_saved_cr (gen_rtx_REG (SImode
, 12),
17116 using_mtcr_multiple
);
17118 emit_jump_insn (par
);
17120 /* We don't want anybody else emitting things after we jumped
17127 else if (using_load_multiple
)
17130 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
17131 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17133 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17134 GEN_INT (info
->gp_save_offset
17137 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17140 gen_rtx_SET (VOIDmode
,
17141 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
17144 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
17148 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
17149 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
17151 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17152 GEN_INT (info
->gp_save_offset
17155 rtx mem
= gen_frame_mem (reg_mode
, addr
);
17157 emit_move_insn (gen_rtx_REG (reg_mode
,
17158 info
->first_gp_reg_save
+ i
), mem
);
17162 /* Restore fpr's if we need to do it without calling a function. */
17163 if (restoring_FPRs_inline
)
17164 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
17165 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
17166 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
17169 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
17170 GEN_INT (info
->fp_save_offset
17173 mem
= gen_frame_mem (DFmode
, addr
);
17175 emit_move_insn (gen_rtx_REG (DFmode
,
17176 info
->first_fp_reg_save
+ i
),
17180 /* If we saved cr, restore it here. Just those that were used. */
17181 if (info
->cr_save_p
)
17182 rs6000_restore_saved_cr (gen_rtx_REG (SImode
, 12), using_mtcr_multiple
);
17184 /* If this is V.4, unwind the stack pointer after all of the loads
17186 rs6000_emit_stack_reset (info
, sp_reg_rtx
, frame_reg_rtx
,
17187 sp_offset
, !restoring_FPRs_inline
);
17189 if (crtl
->calls_eh_return
)
17191 rtx sa
= EH_RETURN_STACKADJ_RTX
;
17192 emit_insn (TARGET_32BIT
17193 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
17194 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
17200 if (! restoring_FPRs_inline
)
17201 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
17203 p
= rtvec_alloc (2);
17205 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
17206 RTVEC_ELT (p
, 1) = (restoring_FPRs_inline
17207 ? gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 65))
17208 : gen_rtx_CLOBBER (VOIDmode
,
17209 gen_rtx_REG (Pmode
, 65)));
17211 /* If we have to restore more than two FP registers, branch to the
17212 restore function. It will return to our caller. */
17213 if (! restoring_FPRs_inline
)
17218 sym
= rs6000_savres_routine_sym (info
,
17222 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
17223 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
,
17224 gen_rtx_REG (Pmode
, 11));
17225 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
17228 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
17229 GEN_INT (info
->fp_save_offset
+ 8*i
));
17230 mem
= gen_frame_mem (DFmode
, addr
);
17232 RTVEC_ELT (p
, i
+4) =
17233 gen_rtx_SET (VOIDmode
,
17234 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
17239 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
17243 /* Write function epilogue. */
17246 rs6000_output_function_epilogue (FILE *file
,
17247 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
17249 if (! HAVE_epilogue
)
17251 rtx insn
= get_last_insn ();
17252 /* If the last insn was a BARRIER, we don't have to write anything except
17253 the trace table. */
17254 if (GET_CODE (insn
) == NOTE
)
17255 insn
= prev_nonnote_insn (insn
);
17256 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
17258 /* This is slightly ugly, but at least we don't have two
17259 copies of the epilogue-emitting code. */
17262 /* A NOTE_INSN_DELETED is supposed to be at the start
17263 and end of the "toplevel" insn chain. */
17264 emit_note (NOTE_INSN_DELETED
);
17265 rs6000_emit_epilogue (FALSE
);
17266 emit_note (NOTE_INSN_DELETED
);
17268 /* Expand INSN_ADDRESSES so final() doesn't crash. */
17272 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
17274 INSN_ADDRESSES_NEW (insn
, addr
);
17279 if (TARGET_DEBUG_STACK
)
17280 debug_rtx_list (get_insns (), 100);
17281 final (get_insns (), file
, FALSE
);
17287 macho_branch_islands ();
17288 /* Mach-O doesn't support labels at the end of objects, so if
17289 it looks like we might want one, insert a NOP. */
17291 rtx insn
= get_last_insn ();
17294 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
17295 insn
= PREV_INSN (insn
);
17299 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
17300 fputs ("\tnop\n", file
);
17304 /* Output a traceback table here. See /usr/include/sys/debug.h for info
17307 We don't output a traceback table if -finhibit-size-directive was
17308 used. The documentation for -finhibit-size-directive reads
17309 ``don't output a @code{.size} assembler directive, or anything
17310 else that would cause trouble if the function is split in the
17311 middle, and the two halves are placed at locations far apart in
17312 memory.'' The traceback table has this property, since it
17313 includes the offset from the start of the function to the
17314 traceback table itself.
17316 System V.4 Powerpc's (and the embedded ABI derived from it) use a
17317 different traceback table. */
17318 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
17319 && rs6000_traceback
!= traceback_none
&& !crtl
->is_thunk
)
17321 const char *fname
= NULL
;
17322 const char *language_string
= lang_hooks
.name
;
17323 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
17325 int optional_tbtab
;
17326 rs6000_stack_t
*info
= rs6000_stack_info ();
17328 if (rs6000_traceback
== traceback_full
)
17329 optional_tbtab
= 1;
17330 else if (rs6000_traceback
== traceback_part
)
17331 optional_tbtab
= 0;
17333 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
17335 if (optional_tbtab
)
17337 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
17338 while (*fname
== '.') /* V.4 encodes . in the name */
17341 /* Need label immediately before tbtab, so we can compute
17342 its offset from the function start. */
17343 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
17344 ASM_OUTPUT_LABEL (file
, fname
);
17347 /* The .tbtab pseudo-op can only be used for the first eight
17348 expressions, since it can't handle the possibly variable
17349 length fields that follow. However, if you omit the optional
17350 fields, the assembler outputs zeros for all optional fields
17351 anyways, giving each variable length field is minimum length
17352 (as defined in sys/debug.h). Thus we can not use the .tbtab
17353 pseudo-op at all. */
17355 /* An all-zero word flags the start of the tbtab, for debuggers
17356 that have to find it by searching forward from the entry
17357 point or from the current pc. */
17358 fputs ("\t.long 0\n", file
);
17360 /* Tbtab format type. Use format type 0. */
17361 fputs ("\t.byte 0,", file
);
17363 /* Language type. Unfortunately, there does not seem to be any
17364 official way to discover the language being compiled, so we
17365 use language_string.
17366 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
17367 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
17368 a number, so for now use 9. */
17369 if (! strcmp (language_string
, "GNU C"))
17371 else if (! strcmp (language_string
, "GNU F77")
17372 || ! strcmp (language_string
, "GNU Fortran"))
17374 else if (! strcmp (language_string
, "GNU Pascal"))
17376 else if (! strcmp (language_string
, "GNU Ada"))
17378 else if (! strcmp (language_string
, "GNU C++")
17379 || ! strcmp (language_string
, "GNU Objective-C++"))
17381 else if (! strcmp (language_string
, "GNU Java"))
17383 else if (! strcmp (language_string
, "GNU Objective-C"))
17386 gcc_unreachable ();
17387 fprintf (file
, "%d,", i
);
17389 /* 8 single bit fields: global linkage (not set for C extern linkage,
17390 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
17391 from start of procedure stored in tbtab, internal function, function
17392 has controlled storage, function has no toc, function uses fp,
17393 function logs/aborts fp operations. */
17394 /* Assume that fp operations are used if any fp reg must be saved. */
17395 fprintf (file
, "%d,",
17396 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
17398 /* 6 bitfields: function is interrupt handler, name present in
17399 proc table, function calls alloca, on condition directives
17400 (controls stack walks, 3 bits), saves condition reg, saves
17402 /* The `function calls alloca' bit seems to be set whenever reg 31 is
17403 set up as a frame pointer, even when there is no alloca call. */
17404 fprintf (file
, "%d,",
17405 ((optional_tbtab
<< 6)
17406 | ((optional_tbtab
& frame_pointer_needed
) << 5)
17407 | (info
->cr_save_p
<< 1)
17408 | (info
->lr_save_p
)));
17410 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
17412 fprintf (file
, "%d,",
17413 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
17415 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
17416 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
17418 if (optional_tbtab
)
17420 /* Compute the parameter info from the function decl argument
17423 int next_parm_info_bit
= 31;
17425 for (decl
= DECL_ARGUMENTS (current_function_decl
);
17426 decl
; decl
= TREE_CHAIN (decl
))
17428 rtx parameter
= DECL_INCOMING_RTL (decl
);
17429 enum machine_mode mode
= GET_MODE (parameter
);
17431 if (GET_CODE (parameter
) == REG
)
17433 if (SCALAR_FLOAT_MODE_P (mode
))
17454 gcc_unreachable ();
17457 /* If only one bit will fit, don't or in this entry. */
17458 if (next_parm_info_bit
> 0)
17459 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
17460 next_parm_info_bit
-= 2;
17464 fixed_parms
+= ((GET_MODE_SIZE (mode
)
17465 + (UNITS_PER_WORD
- 1))
17467 next_parm_info_bit
-= 1;
17473 /* Number of fixed point parameters. */
17474 /* This is actually the number of words of fixed point parameters; thus
17475 an 8 byte struct counts as 2; and thus the maximum value is 8. */
17476 fprintf (file
, "%d,", fixed_parms
);
17478 /* 2 bitfields: number of floating point parameters (7 bits), parameters
17480 /* This is actually the number of fp registers that hold parameters;
17481 and thus the maximum value is 13. */
17482 /* Set parameters on stack bit if parameters are not in their original
17483 registers, regardless of whether they are on the stack? Xlc
17484 seems to set the bit when not optimizing. */
17485 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
17487 if (! optional_tbtab
)
17490 /* Optional fields follow. Some are variable length. */
17492 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
17493 11 double float. */
17494 /* There is an entry for each parameter in a register, in the order that
17495 they occur in the parameter list. Any intervening arguments on the
17496 stack are ignored. If the list overflows a long (max possible length
17497 34 bits) then completely leave off all elements that don't fit. */
17498 /* Only emit this long if there was at least one parameter. */
17499 if (fixed_parms
|| float_parms
)
17500 fprintf (file
, "\t.long %d\n", parm_info
);
17502 /* Offset from start of code to tb table. */
17503 fputs ("\t.long ", file
);
17504 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
17506 RS6000_OUTPUT_BASENAME (file
, fname
);
17508 assemble_name (file
, fname
);
17510 rs6000_output_function_entry (file
, fname
);
17513 /* Interrupt handler mask. */
17514 /* Omit this long, since we never set the interrupt handler bit
17517 /* Number of CTL (controlled storage) anchors. */
17518 /* Omit this long, since the has_ctl bit is never set above. */
17520 /* Displacement into stack of each CTL anchor. */
17521 /* Omit this list of longs, because there are no CTL anchors. */
17523 /* Length of function name. */
17526 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
17528 /* Function name. */
17529 assemble_string (fname
, strlen (fname
));
17531 /* Register for alloca automatic storage; this is always reg 31.
17532 Only emit this if the alloca bit was set above. */
17533 if (frame_pointer_needed
)
17534 fputs ("\t.byte 31\n", file
);
17536 fputs ("\t.align 2\n", file
);
17540 /* A C compound statement that outputs the assembler code for a thunk
17541 function, used to implement C++ virtual function calls with
17542 multiple inheritance. The thunk acts as a wrapper around a virtual
17543 function, adjusting the implicit object parameter before handing
17544 control off to the real function.
17546 First, emit code to add the integer DELTA to the location that
17547 contains the incoming first argument. Assume that this argument
17548 contains a pointer, and is the one used to pass the `this' pointer
17549 in C++. This is the incoming argument *before* the function
17550 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17551 values of all other incoming arguments.
17553 After the addition, emit code to jump to FUNCTION, which is a
17554 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17555 not touch the return address. Hence returning from FUNCTION will
17556 return to whoever called the current `thunk'.
17558 The effect must be as if FUNCTION had been called directly with the
17559 adjusted first argument. This macro is responsible for emitting
17560 all of the code for a thunk function; output_function_prologue()
17561 and output_function_epilogue() are not invoked.
17563 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17564 been extracted from it.) It might possibly be useful on some
17565 targets, but probably not.
17567 If you do not define this macro, the target-independent code in the
17568 C++ frontend will generate a less efficient heavyweight thunk that
17569 calls FUNCTION instead of jumping to it. The generic approach does
17570 not support varargs. */
17573 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
17574 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
17577 rtx
this, insn
, funexp
;
17579 reload_completed
= 1;
17580 epilogue_completed
= 1;
17582 /* Mark the end of the (empty) prologue. */
17583 emit_note (NOTE_INSN_PROLOGUE_END
);
17585 /* Find the "this" pointer. If the function returns a structure,
17586 the structure return pointer is in r3. */
17587 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
17588 this = gen_rtx_REG (Pmode
, 4);
17590 this = gen_rtx_REG (Pmode
, 3);
17592 /* Apply the constant offset, if required. */
17595 rtx delta_rtx
= GEN_INT (delta
);
17596 emit_insn (TARGET_32BIT
17597 ? gen_addsi3 (this, this, delta_rtx
)
17598 : gen_adddi3 (this, this, delta_rtx
));
17601 /* Apply the offset from the vtable, if required. */
17604 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
17605 rtx tmp
= gen_rtx_REG (Pmode
, 12);
17607 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
17608 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
17610 emit_insn (TARGET_32BIT
17611 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
17612 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
17613 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
17617 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
17619 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
17621 emit_insn (TARGET_32BIT
17622 ? gen_addsi3 (this, this, tmp
)
17623 : gen_adddi3 (this, this, tmp
));
17626 /* Generate a tail call to the target function. */
17627 if (!TREE_USED (function
))
17629 assemble_external (function
);
17630 TREE_USED (function
) = 1;
17632 funexp
= XEXP (DECL_RTL (function
), 0);
17633 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
17636 if (MACHOPIC_INDIRECT
)
17637 funexp
= machopic_indirect_call_target (funexp
);
17640 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17641 generate sibcall RTL explicitly. */
17642 insn
= emit_call_insn (
17643 gen_rtx_PARALLEL (VOIDmode
,
17645 gen_rtx_CALL (VOIDmode
,
17646 funexp
, const0_rtx
),
17647 gen_rtx_USE (VOIDmode
, const0_rtx
),
17648 gen_rtx_USE (VOIDmode
,
17649 gen_rtx_REG (SImode
,
17651 gen_rtx_RETURN (VOIDmode
))));
17652 SIBLING_CALL_P (insn
) = 1;
17655 /* Run just enough of rest_of_compilation to get the insns emitted.
17656 There's not really enough bulk here to make other passes such as
17657 instruction scheduling worth while. Note that use_thunk calls
17658 assemble_start_function and assemble_end_function. */
17659 insn
= get_insns ();
17660 insn_locators_alloc ();
17661 shorten_branches (insn
);
17662 final_start_function (insn
, file
, 1);
17663 final (insn
, file
, 1);
17664 final_end_function ();
17665 free_after_compilation (cfun
);
17667 reload_completed
= 0;
17668 epilogue_completed
= 0;
17671 /* A quick summary of the various types of 'constant-pool tables'
17674 Target Flags Name One table per
17675 AIX (none) AIX TOC object file
17676 AIX -mfull-toc AIX TOC object file
17677 AIX -mminimal-toc AIX minimal TOC translation unit
17678 SVR4/EABI (none) SVR4 SDATA object file
17679 SVR4/EABI -fpic SVR4 pic object file
17680 SVR4/EABI -fPIC SVR4 PIC translation unit
17681 SVR4/EABI -mrelocatable EABI TOC function
17682 SVR4/EABI -maix AIX TOC object file
17683 SVR4/EABI -maix -mminimal-toc
17684 AIX minimal TOC translation unit
17686 Name Reg. Set by entries contains:
17687 made by addrs? fp? sum?
17689 AIX TOC 2 crt0 as Y option option
17690 AIX minimal TOC 30 prolog gcc Y Y option
17691 SVR4 SDATA 13 crt0 gcc N Y N
17692 SVR4 pic 30 prolog ld Y not yet N
17693 SVR4 PIC 30 prolog gcc Y option option
17694 EABI TOC 30 prolog gcc Y option option
17698 /* Hash functions for the hash table. */
17701 rs6000_hash_constant (rtx k
)
17703 enum rtx_code code
= GET_CODE (k
);
17704 enum machine_mode mode
= GET_MODE (k
);
17705 unsigned result
= (code
<< 3) ^ mode
;
17706 const char *format
;
17709 format
= GET_RTX_FORMAT (code
);
17710 flen
= strlen (format
);
17716 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
17719 if (mode
!= VOIDmode
)
17720 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
17732 for (; fidx
< flen
; fidx
++)
17733 switch (format
[fidx
])
17738 const char *str
= XSTR (k
, fidx
);
17739 len
= strlen (str
);
17740 result
= result
* 613 + len
;
17741 for (i
= 0; i
< len
; i
++)
17742 result
= result
* 613 + (unsigned) str
[i
];
17747 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
17751 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
17754 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
17755 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
17759 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
17760 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
17767 gcc_unreachable ();
17774 toc_hash_function (const void *hash_entry
)
17776 const struct toc_hash_struct
*thc
=
17777 (const struct toc_hash_struct
*) hash_entry
;
17778 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
17781 /* Compare H1 and H2 for equivalence. */
17784 toc_hash_eq (const void *h1
, const void *h2
)
17786 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
17787 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
17789 if (((const struct toc_hash_struct
*) h1
)->key_mode
17790 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
17793 return rtx_equal_p (r1
, r2
);
17796 /* These are the names given by the C++ front-end to vtables, and
17797 vtable-like objects. Ideally, this logic should not be here;
17798 instead, there should be some programmatic way of inquiring as
17799 to whether or not an object is a vtable. */
17801 #define VTABLE_NAME_P(NAME) \
17802 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
17803 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
17804 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
17805 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
17806 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
17809 rs6000_output_symbol_ref (FILE *file
, rtx x
)
17811 /* Currently C++ toc references to vtables can be emitted before it
17812 is decided whether the vtable is public or private. If this is
17813 the case, then the linker will eventually complain that there is
17814 a reference to an unknown section. Thus, for vtables only,
17815 we emit the TOC reference to reference the symbol and not the
17817 const char *name
= XSTR (x
, 0);
17819 if (VTABLE_NAME_P (name
))
17821 RS6000_OUTPUT_BASENAME (file
, name
);
17824 assemble_name (file
, name
);
17827 /* Output a TOC entry. We derive the entry name from what is being
17831 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
17834 const char *name
= buf
;
17835 const char *real_name
;
17837 HOST_WIDE_INT offset
= 0;
17839 gcc_assert (!TARGET_NO_TOC
);
17841 /* When the linker won't eliminate them, don't output duplicate
17842 TOC entries (this happens on AIX if there is any kind of TOC,
17843 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17845 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
17847 struct toc_hash_struct
*h
;
17850 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17851 time because GGC is not initialized at that point. */
17852 if (toc_hash_table
== NULL
)
17853 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
17854 toc_hash_eq
, NULL
);
17856 h
= GGC_NEW (struct toc_hash_struct
);
17858 h
->key_mode
= mode
;
17859 h
->labelno
= labelno
;
17861 found
= htab_find_slot (toc_hash_table
, h
, 1);
17862 if (*found
== NULL
)
17864 else /* This is indeed a duplicate.
17865 Set this label equal to that label. */
17867 fputs ("\t.set ", file
);
17868 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
17869 fprintf (file
, "%d,", labelno
);
17870 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
17871 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
17877 /* If we're going to put a double constant in the TOC, make sure it's
17878 aligned properly when strict alignment is on. */
17879 if (GET_CODE (x
) == CONST_DOUBLE
17880 && STRICT_ALIGNMENT
17881 && GET_MODE_BITSIZE (mode
) >= 64
17882 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
17883 ASM_OUTPUT_ALIGN (file
, 3);
17886 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
17888 /* Handle FP constants specially. Note that if we have a minimal
17889 TOC, things we put here aren't actually in the TOC, so we can allow
17891 if (GET_CODE (x
) == CONST_DOUBLE
&&
17892 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
17894 REAL_VALUE_TYPE rv
;
17897 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17898 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17899 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
17901 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
17905 if (TARGET_MINIMAL_TOC
)
17906 fputs (DOUBLE_INT_ASM_OP
, file
);
17908 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17909 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17910 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17911 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
17912 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17913 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17918 if (TARGET_MINIMAL_TOC
)
17919 fputs ("\t.long ", file
);
17921 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17922 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17923 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17924 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17925 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17926 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17930 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17931 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
17933 REAL_VALUE_TYPE rv
;
17936 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17938 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17939 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
17941 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
17945 if (TARGET_MINIMAL_TOC
)
17946 fputs (DOUBLE_INT_ASM_OP
, file
);
17948 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17949 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17950 fprintf (file
, "0x%lx%08lx\n",
17951 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17956 if (TARGET_MINIMAL_TOC
)
17957 fputs ("\t.long ", file
);
17959 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17960 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17961 fprintf (file
, "0x%lx,0x%lx\n",
17962 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17966 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17967 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
17969 REAL_VALUE_TYPE rv
;
17972 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17973 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17974 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
17976 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
17980 if (TARGET_MINIMAL_TOC
)
17981 fputs (DOUBLE_INT_ASM_OP
, file
);
17983 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
17984 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
17989 if (TARGET_MINIMAL_TOC
)
17990 fputs ("\t.long ", file
);
17992 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
17993 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
17997 else if (GET_MODE (x
) == VOIDmode
17998 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
18000 unsigned HOST_WIDE_INT low
;
18001 HOST_WIDE_INT high
;
18003 if (GET_CODE (x
) == CONST_DOUBLE
)
18005 low
= CONST_DOUBLE_LOW (x
);
18006 high
= CONST_DOUBLE_HIGH (x
);
18009 #if HOST_BITS_PER_WIDE_INT == 32
18012 high
= (low
& 0x80000000) ? ~0 : 0;
18016 low
= INTVAL (x
) & 0xffffffff;
18017 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
18021 /* TOC entries are always Pmode-sized, but since this
18022 is a bigendian machine then if we're putting smaller
18023 integer constants in the TOC we have to pad them.
18024 (This is still a win over putting the constants in
18025 a separate constant pool, because then we'd have
18026 to have both a TOC entry _and_ the actual constant.)
18028 For a 32-bit target, CONST_INT values are loaded and shifted
18029 entirely within `low' and can be stored in one TOC entry. */
18031 /* It would be easy to make this work, but it doesn't now. */
18032 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
18034 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
18036 #if HOST_BITS_PER_WIDE_INT == 32
18037 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
18038 POINTER_SIZE
, &low
, &high
, 0);
18041 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
18042 high
= (HOST_WIDE_INT
) low
>> 32;
18049 if (TARGET_MINIMAL_TOC
)
18050 fputs (DOUBLE_INT_ASM_OP
, file
);
18052 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
18053 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18054 fprintf (file
, "0x%lx%08lx\n",
18055 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18060 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
18062 if (TARGET_MINIMAL_TOC
)
18063 fputs ("\t.long ", file
);
18065 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
18066 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18067 fprintf (file
, "0x%lx,0x%lx\n",
18068 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
18072 if (TARGET_MINIMAL_TOC
)
18073 fputs ("\t.long ", file
);
18075 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
18076 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
18082 if (GET_CODE (x
) == CONST
)
18084 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
);
18086 base
= XEXP (XEXP (x
, 0), 0);
18087 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
18090 switch (GET_CODE (base
))
18093 name
= XSTR (base
, 0);
18097 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
18098 CODE_LABEL_NUMBER (XEXP (base
, 0)));
18102 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
18106 gcc_unreachable ();
18109 real_name
= (*targetm
.strip_name_encoding
) (name
);
18110 if (TARGET_MINIMAL_TOC
)
18111 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
18114 fprintf (file
, "\t.tc %s", real_name
);
18117 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
18119 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
18121 fputs ("[TC],", file
);
18124 /* Currently C++ toc references to vtables can be emitted before it
18125 is decided whether the vtable is public or private. If this is
18126 the case, then the linker will eventually complain that there is
18127 a TOC reference to an unknown section. Thus, for vtables only,
18128 we emit the TOC reference to reference the symbol and not the
18130 if (VTABLE_NAME_P (name
))
18132 RS6000_OUTPUT_BASENAME (file
, name
);
18134 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
18135 else if (offset
> 0)
18136 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
18139 output_addr_const (file
, x
);
18143 /* Output an assembler pseudo-op to write an ASCII string of N characters
18144 starting at P to FILE.
18146 On the RS/6000, we have to do this using the .byte operation and
18147 write out special characters outside the quoted string.
18148 Also, the assembler is broken; very long strings are truncated,
18149 so we must artificially break them up early. */
18152 output_ascii (FILE *file
, const char *p
, int n
)
18155 int i
, count_string
;
18156 const char *for_string
= "\t.byte \"";
18157 const char *for_decimal
= "\t.byte ";
18158 const char *to_close
= NULL
;
18161 for (i
= 0; i
< n
; i
++)
18164 if (c
>= ' ' && c
< 0177)
18167 fputs (for_string
, file
);
18170 /* Write two quotes to get one. */
18178 for_decimal
= "\"\n\t.byte ";
18182 if (count_string
>= 512)
18184 fputs (to_close
, file
);
18186 for_string
= "\t.byte \"";
18187 for_decimal
= "\t.byte ";
18195 fputs (for_decimal
, file
);
18196 fprintf (file
, "%d", c
);
18198 for_string
= "\n\t.byte \"";
18199 for_decimal
= ", ";
18205 /* Now close the string if we have written one. Then end the line. */
18207 fputs (to_close
, file
);
18210 /* Generate a unique section name for FILENAME for a section type
18211 represented by SECTION_DESC. Output goes into BUF.
18213 SECTION_DESC can be any string, as long as it is different for each
18214 possible section type.
18216 We name the section in the same manner as xlc. The name begins with an
18217 underscore followed by the filename (after stripping any leading directory
18218 names) with the last period replaced by the string SECTION_DESC. If
18219 FILENAME does not contain a period, SECTION_DESC is appended to the end of
18223 rs6000_gen_section_name (char **buf
, const char *filename
,
18224 const char *section_desc
)
18226 const char *q
, *after_last_slash
, *last_period
= 0;
18230 after_last_slash
= filename
;
18231 for (q
= filename
; *q
; q
++)
18234 after_last_slash
= q
+ 1;
18235 else if (*q
== '.')
18239 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
18240 *buf
= (char *) xmalloc (len
);
18245 for (q
= after_last_slash
; *q
; q
++)
18247 if (q
== last_period
)
18249 strcpy (p
, section_desc
);
18250 p
+= strlen (section_desc
);
18254 else if (ISALNUM (*q
))
18258 if (last_period
== 0)
18259 strcpy (p
, section_desc
);
18264 /* Emit profile function. */
18267 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
18269 /* Non-standard profiling for kernels, which just saves LR then calls
18270 _mcount without worrying about arg saves. The idea is to change
18271 the function prologue as little as possible as it isn't easy to
18272 account for arg save/restore code added just for _mcount. */
18273 if (TARGET_PROFILE_KERNEL
)
18276 if (DEFAULT_ABI
== ABI_AIX
)
18278 #ifndef NO_PROFILE_COUNTERS
18279 # define NO_PROFILE_COUNTERS 0
18281 if (NO_PROFILE_COUNTERS
)
18282 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
18286 const char *label_name
;
18289 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
18290 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
18291 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
18293 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
18297 else if (DEFAULT_ABI
== ABI_DARWIN
)
18299 const char *mcount_name
= RS6000_MCOUNT
;
18300 int caller_addr_regno
= LR_REGNO
;
18302 /* Be conservative and always set this, at least for now. */
18303 crtl
->uses_pic_offset_table
= 1;
18306 /* For PIC code, set up a stub and collect the caller's address
18307 from r0, which is where the prologue puts it. */
18308 if (MACHOPIC_INDIRECT
18309 && crtl
->uses_pic_offset_table
)
18310 caller_addr_regno
= 0;
18312 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
18314 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
18318 /* Write function profiler code. */
18321 output_function_profiler (FILE *file
, int labelno
)
18325 switch (DEFAULT_ABI
)
18328 gcc_unreachable ();
18333 warning (0, "no profiling of 64-bit code for this ABI");
18336 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
18337 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
18338 if (NO_PROFILE_COUNTERS
)
18340 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18341 reg_names
[0], reg_names
[1]);
18343 else if (TARGET_SECURE_PLT
&& flag_pic
)
18345 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
18346 reg_names
[0], reg_names
[1]);
18347 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
18348 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
18349 reg_names
[12], reg_names
[12]);
18350 assemble_name (file
, buf
);
18351 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
18352 assemble_name (file
, buf
);
18353 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
18355 else if (flag_pic
== 1)
18357 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
18358 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18359 reg_names
[0], reg_names
[1]);
18360 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
18361 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
18362 assemble_name (file
, buf
);
18363 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
18365 else if (flag_pic
> 1)
18367 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18368 reg_names
[0], reg_names
[1]);
18369 /* Now, we need to get the address of the label. */
18370 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
18371 assemble_name (file
, buf
);
18372 fputs ("-.\n1:", file
);
18373 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
18374 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
18375 reg_names
[0], reg_names
[11]);
18376 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
18377 reg_names
[0], reg_names
[0], reg_names
[11]);
18381 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
18382 assemble_name (file
, buf
);
18383 fputs ("@ha\n", file
);
18384 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
18385 reg_names
[0], reg_names
[1]);
18386 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
18387 assemble_name (file
, buf
);
18388 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
18391 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
18392 fprintf (file
, "\tbl %s%s\n",
18393 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
18398 if (!TARGET_PROFILE_KERNEL
)
18400 /* Don't do anything, done in output_profile_hook (). */
18404 gcc_assert (!TARGET_32BIT
);
18406 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
18407 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
18409 if (cfun
->static_chain_decl
!= NULL
)
18411 asm_fprintf (file
, "\tstd %s,24(%s)\n",
18412 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
18413 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
18414 asm_fprintf (file
, "\tld %s,24(%s)\n",
18415 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
18418 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
18426 /* The following variable value is the last issued insn. */
18428 static rtx last_scheduled_insn
;
18430 /* The following variable helps to balance issuing of load and
18431 store instructions */
18433 static int load_store_pendulum
;
18435 /* Power4 load update and store update instructions are cracked into a
18436 load or store and an integer insn which are executed in the same cycle.
18437 Branches have their own dispatch slot which does not count against the
18438 GCC issue rate, but it changes the program flow so there are no other
18439 instructions to issue in this cycle. */
18442 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
18443 int verbose ATTRIBUTE_UNUSED
,
18444 rtx insn
, int more
)
18446 last_scheduled_insn
= insn
;
18447 if (GET_CODE (PATTERN (insn
)) == USE
18448 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18450 cached_can_issue_more
= more
;
18451 return cached_can_issue_more
;
18454 if (insn_terminates_group_p (insn
, current_group
))
18456 cached_can_issue_more
= 0;
18457 return cached_can_issue_more
;
18460 /* If no reservation, but reach here */
18461 if (recog_memoized (insn
) < 0)
18464 if (rs6000_sched_groups
)
18466 if (is_microcoded_insn (insn
))
18467 cached_can_issue_more
= 0;
18468 else if (is_cracked_insn (insn
))
18469 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
18471 cached_can_issue_more
= more
- 1;
18473 return cached_can_issue_more
;
18476 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
18479 cached_can_issue_more
= more
- 1;
18480 return cached_can_issue_more
;
18483 /* Adjust the cost of a scheduling dependency. Return the new cost of
18484 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
18487 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
18489 enum attr_type attr_type
;
18491 if (! recog_memoized (insn
))
18494 switch (REG_NOTE_KIND (link
))
18498 /* Data dependency; DEP_INSN writes a register that INSN reads
18499 some cycles later. */
18501 /* Separate a load from a narrower, dependent store. */
18502 if (rs6000_sched_groups
18503 && GET_CODE (PATTERN (insn
)) == SET
18504 && GET_CODE (PATTERN (dep_insn
)) == SET
18505 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
18506 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
18507 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
18508 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
18511 attr_type
= get_attr_type (insn
);
18516 /* Tell the first scheduling pass about the latency between
18517 a mtctr and bctr (and mtlr and br/blr). The first
18518 scheduling pass will not know about this latency since
18519 the mtctr instruction, which has the latency associated
18520 to it, will be generated by reload. */
18521 return TARGET_POWER
? 5 : 4;
18523 /* Leave some extra cycles between a compare and its
18524 dependent branch, to inhibit expensive mispredicts. */
18525 if ((rs6000_cpu_attr
== CPU_PPC603
18526 || rs6000_cpu_attr
== CPU_PPC604
18527 || rs6000_cpu_attr
== CPU_PPC604E
18528 || rs6000_cpu_attr
== CPU_PPC620
18529 || rs6000_cpu_attr
== CPU_PPC630
18530 || rs6000_cpu_attr
== CPU_PPC750
18531 || rs6000_cpu_attr
== CPU_PPC7400
18532 || rs6000_cpu_attr
== CPU_PPC7450
18533 || rs6000_cpu_attr
== CPU_POWER4
18534 || rs6000_cpu_attr
== CPU_POWER5
18535 || rs6000_cpu_attr
== CPU_CELL
)
18536 && recog_memoized (dep_insn
)
18537 && (INSN_CODE (dep_insn
) >= 0))
18539 switch (get_attr_type (dep_insn
))
18543 case TYPE_DELAYED_COMPARE
:
18544 case TYPE_IMUL_COMPARE
:
18545 case TYPE_LMUL_COMPARE
:
18546 case TYPE_FPCOMPARE
:
18547 case TYPE_CR_LOGICAL
:
18548 case TYPE_DELAYED_CR
:
18557 case TYPE_STORE_UX
:
18559 case TYPE_FPSTORE_U
:
18560 case TYPE_FPSTORE_UX
:
18561 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18562 && recog_memoized (dep_insn
)
18563 && (INSN_CODE (dep_insn
) >= 0))
18566 if (GET_CODE (PATTERN (insn
)) != SET
)
18567 /* If this happens, we have to extend this to schedule
18568 optimally. Return default for now. */
18571 /* Adjust the cost for the case where the value written
18572 by a fixed point operation is used as the address
18573 gen value on a store. */
18574 switch (get_attr_type (dep_insn
))
18581 if (! store_data_bypass_p (dep_insn
, insn
))
18585 case TYPE_LOAD_EXT
:
18586 case TYPE_LOAD_EXT_U
:
18587 case TYPE_LOAD_EXT_UX
:
18588 case TYPE_VAR_SHIFT_ROTATE
:
18589 case TYPE_VAR_DELAYED_COMPARE
:
18591 if (! store_data_bypass_p (dep_insn
, insn
))
18597 case TYPE_FAST_COMPARE
:
18600 case TYPE_INSERT_WORD
:
18601 case TYPE_INSERT_DWORD
:
18602 case TYPE_FPLOAD_U
:
18603 case TYPE_FPLOAD_UX
:
18605 case TYPE_STORE_UX
:
18606 case TYPE_FPSTORE_U
:
18607 case TYPE_FPSTORE_UX
:
18609 if (! store_data_bypass_p (dep_insn
, insn
))
18617 case TYPE_IMUL_COMPARE
:
18618 case TYPE_LMUL_COMPARE
:
18620 if (! store_data_bypass_p (dep_insn
, insn
))
18626 if (! store_data_bypass_p (dep_insn
, insn
))
18632 if (! store_data_bypass_p (dep_insn
, insn
))
18645 case TYPE_LOAD_EXT
:
18646 case TYPE_LOAD_EXT_U
:
18647 case TYPE_LOAD_EXT_UX
:
18648 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18649 && recog_memoized (dep_insn
)
18650 && (INSN_CODE (dep_insn
) >= 0))
18653 /* Adjust the cost for the case where the value written
18654 by a fixed point instruction is used within the address
18655 gen portion of a subsequent load(u)(x) */
18656 switch (get_attr_type (dep_insn
))
18663 if (set_to_load_agen (dep_insn
, insn
))
18667 case TYPE_LOAD_EXT
:
18668 case TYPE_LOAD_EXT_U
:
18669 case TYPE_LOAD_EXT_UX
:
18670 case TYPE_VAR_SHIFT_ROTATE
:
18671 case TYPE_VAR_DELAYED_COMPARE
:
18673 if (set_to_load_agen (dep_insn
, insn
))
18679 case TYPE_FAST_COMPARE
:
18682 case TYPE_INSERT_WORD
:
18683 case TYPE_INSERT_DWORD
:
18684 case TYPE_FPLOAD_U
:
18685 case TYPE_FPLOAD_UX
:
18687 case TYPE_STORE_UX
:
18688 case TYPE_FPSTORE_U
:
18689 case TYPE_FPSTORE_UX
:
18691 if (set_to_load_agen (dep_insn
, insn
))
18699 case TYPE_IMUL_COMPARE
:
18700 case TYPE_LMUL_COMPARE
:
18702 if (set_to_load_agen (dep_insn
, insn
))
18708 if (set_to_load_agen (dep_insn
, insn
))
18714 if (set_to_load_agen (dep_insn
, insn
))
18725 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18726 && recog_memoized (dep_insn
)
18727 && (INSN_CODE (dep_insn
) >= 0)
18728 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
18735 /* Fall out to return default cost. */
18739 case REG_DEP_OUTPUT
:
18740 /* Output dependency; DEP_INSN writes a register that INSN writes some
18742 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18743 && recog_memoized (dep_insn
)
18744 && (INSN_CODE (dep_insn
) >= 0))
18746 attr_type
= get_attr_type (insn
);
18751 if (get_attr_type (dep_insn
) == TYPE_FP
)
18755 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
18763 /* Anti dependency; DEP_INSN reads a register that INSN writes some
18768 gcc_unreachable ();
18774 /* The function returns a true if INSN is microcoded.
18775 Return false otherwise. */
18778 is_microcoded_insn (rtx insn
)
18780 if (!insn
|| !INSN_P (insn
)
18781 || GET_CODE (PATTERN (insn
)) == USE
18782 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18785 if (rs6000_cpu_attr
== CPU_CELL
)
18786 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
18788 if (rs6000_sched_groups
)
18790 enum attr_type type
= get_attr_type (insn
);
18791 if (type
== TYPE_LOAD_EXT_U
18792 || type
== TYPE_LOAD_EXT_UX
18793 || type
== TYPE_LOAD_UX
18794 || type
== TYPE_STORE_UX
18795 || type
== TYPE_MFCR
)
18802 /* The function returns true if INSN is cracked into 2 instructions
18803 by the processor (and therefore occupies 2 issue slots). */
18806 is_cracked_insn (rtx insn
)
18808 if (!insn
|| !INSN_P (insn
)
18809 || GET_CODE (PATTERN (insn
)) == USE
18810 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18813 if (rs6000_sched_groups
)
18815 enum attr_type type
= get_attr_type (insn
);
18816 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
18817 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
18818 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
18819 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
18820 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
18821 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
18822 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
18823 || type
== TYPE_INSERT_WORD
)
18830 /* The function returns true if INSN can be issued only from
18831 the branch slot. */
18834 is_branch_slot_insn (rtx insn
)
18836 if (!insn
|| !INSN_P (insn
)
18837 || GET_CODE (PATTERN (insn
)) == USE
18838 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18841 if (rs6000_sched_groups
)
18843 enum attr_type type
= get_attr_type (insn
);
18844 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
18852 /* The function returns true if out_inst sets a value that is
18853 used in the address generation computation of in_insn */
18855 set_to_load_agen (rtx out_insn
, rtx in_insn
)
18857 rtx out_set
, in_set
;
18859 /* For performance reasons, only handle the simple case where
18860 both loads are a single_set. */
18861 out_set
= single_set (out_insn
);
18864 in_set
= single_set (in_insn
);
18866 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
18872 /* The function returns true if the target storage location of
18873 out_insn is adjacent to the target storage location of in_insn */
18874 /* Return 1 if memory locations are adjacent. */
18877 adjacent_mem_locations (rtx insn1
, rtx insn2
)
18880 rtx a
= get_store_dest (PATTERN (insn1
));
18881 rtx b
= get_store_dest (PATTERN (insn2
));
18883 if ((GET_CODE (XEXP (a
, 0)) == REG
18884 || (GET_CODE (XEXP (a
, 0)) == PLUS
18885 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
18886 && (GET_CODE (XEXP (b
, 0)) == REG
18887 || (GET_CODE (XEXP (b
, 0)) == PLUS
18888 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
18890 HOST_WIDE_INT val0
= 0, val1
= 0, val_diff
;
18893 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
18895 reg0
= XEXP (XEXP (a
, 0), 0);
18896 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
18899 reg0
= XEXP (a
, 0);
18901 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
18903 reg1
= XEXP (XEXP (b
, 0), 0);
18904 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
18907 reg1
= XEXP (b
, 0);
18909 val_diff
= val1
- val0
;
18911 return ((REGNO (reg0
) == REGNO (reg1
))
18912 && ((MEM_SIZE (a
) && val_diff
== INTVAL (MEM_SIZE (a
)))
18913 || (MEM_SIZE (b
) && val_diff
== -INTVAL (MEM_SIZE (b
)))));
18919 /* A C statement (sans semicolon) to update the integer scheduling
18920 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18921 INSN earlier, reduce the priority to execute INSN later. Do not
18922 define this macro if you do not need to adjust the scheduling
18923 priorities of insns. */
18926 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
18928 /* On machines (like the 750) which have asymmetric integer units,
18929 where one integer unit can do multiply and divides and the other
18930 can't, reduce the priority of multiply/divide so it is scheduled
18931 before other integer operations. */
18934 if (! INSN_P (insn
))
18937 if (GET_CODE (PATTERN (insn
)) == USE
)
18940 switch (rs6000_cpu_attr
) {
18942 switch (get_attr_type (insn
))
18949 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
18950 priority
, priority
);
18951 if (priority
>= 0 && priority
< 0x01000000)
18958 if (insn_must_be_first_in_group (insn
)
18959 && reload_completed
18960 && current_sched_info
->sched_max_insns_priority
18961 && rs6000_sched_restricted_insns_priority
)
18964 /* Prioritize insns that can be dispatched only in the first
18966 if (rs6000_sched_restricted_insns_priority
== 1)
18967 /* Attach highest priority to insn. This means that in
18968 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18969 precede 'priority' (critical path) considerations. */
18970 return current_sched_info
->sched_max_insns_priority
;
18971 else if (rs6000_sched_restricted_insns_priority
== 2)
18972 /* Increase priority of insn by a minimal amount. This means that in
18973 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18974 considerations precede dispatch-slot restriction considerations. */
18975 return (priority
+ 1);
18978 if (rs6000_cpu
== PROCESSOR_POWER6
18979 && ((load_store_pendulum
== -2 && is_load_insn (insn
))
18980 || (load_store_pendulum
== 2 && is_store_insn (insn
))))
18981 /* Attach highest priority to insn if the scheduler has just issued two
18982 stores and this instruction is a load, or two loads and this instruction
18983 is a store. Power6 wants loads and stores scheduled alternately
18985 return current_sched_info
->sched_max_insns_priority
;
18990 /* Return true if the instruction is nonpipelined on the Cell. */
18992 is_nonpipeline_insn (rtx insn
)
18994 enum attr_type type
;
18995 if (!insn
|| !INSN_P (insn
)
18996 || GET_CODE (PATTERN (insn
)) == USE
18997 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19000 type
= get_attr_type (insn
);
19001 if (type
== TYPE_IMUL
19002 || type
== TYPE_IMUL2
19003 || type
== TYPE_IMUL3
19004 || type
== TYPE_LMUL
19005 || type
== TYPE_IDIV
19006 || type
== TYPE_LDIV
19007 || type
== TYPE_SDIV
19008 || type
== TYPE_DDIV
19009 || type
== TYPE_SSQRT
19010 || type
== TYPE_DSQRT
19011 || type
== TYPE_MFCR
19012 || type
== TYPE_MFCRF
19013 || type
== TYPE_MFJMPR
)
19021 /* Return how many instructions the machine can issue per cycle. */
19024 rs6000_issue_rate (void)
19026 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
19027 if (!reload_completed
)
19030 switch (rs6000_cpu_attr
) {
19031 case CPU_RIOS1
: /* ? */
19033 case CPU_PPC601
: /* ? */
19042 case CPU_PPCE300C2
:
19043 case CPU_PPCE300C3
:
19044 case CPU_PPCE500MC
:
19061 /* Return how many instructions to look ahead for better insn
19065 rs6000_use_sched_lookahead (void)
19067 if (rs6000_cpu_attr
== CPU_PPC8540
)
19069 if (rs6000_cpu_attr
== CPU_CELL
)
19070 return (reload_completed
? 8 : 0);
19074 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
19076 rs6000_use_sched_lookahead_guard (rtx insn
)
19078 if (rs6000_cpu_attr
!= CPU_CELL
)
19081 if (insn
== NULL_RTX
|| !INSN_P (insn
))
19084 if (!reload_completed
19085 || is_nonpipeline_insn (insn
)
19086 || is_microcoded_insn (insn
))
19092 /* Determine is PAT refers to memory. */
19095 is_mem_ref (rtx pat
)
19101 /* stack_tie does not produce any real memory traffic. */
19102 if (GET_CODE (pat
) == UNSPEC
19103 && XINT (pat
, 1) == UNSPEC_TIE
)
19106 if (GET_CODE (pat
) == MEM
)
19109 /* Recursively process the pattern. */
19110 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
19112 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
19115 ret
|= is_mem_ref (XEXP (pat
, i
));
19116 else if (fmt
[i
] == 'E')
19117 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
19118 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
19124 /* Determine if PAT is a PATTERN of a load insn. */
19127 is_load_insn1 (rtx pat
)
19129 if (!pat
|| pat
== NULL_RTX
)
19132 if (GET_CODE (pat
) == SET
)
19133 return is_mem_ref (SET_SRC (pat
));
19135 if (GET_CODE (pat
) == PARALLEL
)
19139 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19140 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
19147 /* Determine if INSN loads from memory. */
19150 is_load_insn (rtx insn
)
19152 if (!insn
|| !INSN_P (insn
))
19155 if (GET_CODE (insn
) == CALL_INSN
)
19158 return is_load_insn1 (PATTERN (insn
));
19161 /* Determine if PAT is a PATTERN of a store insn. */
19164 is_store_insn1 (rtx pat
)
19166 if (!pat
|| pat
== NULL_RTX
)
19169 if (GET_CODE (pat
) == SET
)
19170 return is_mem_ref (SET_DEST (pat
));
19172 if (GET_CODE (pat
) == PARALLEL
)
19176 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19177 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
19184 /* Determine if INSN stores to memory. */
19187 is_store_insn (rtx insn
)
19189 if (!insn
|| !INSN_P (insn
))
19192 return is_store_insn1 (PATTERN (insn
));
19195 /* Return the dest of a store insn. */
19198 get_store_dest (rtx pat
)
19200 gcc_assert (is_store_insn1 (pat
));
19202 if (GET_CODE (pat
) == SET
)
19203 return SET_DEST (pat
);
19204 else if (GET_CODE (pat
) == PARALLEL
)
19208 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
19210 rtx inner_pat
= XVECEXP (pat
, 0, i
);
19211 if (GET_CODE (inner_pat
) == SET
19212 && is_mem_ref (SET_DEST (inner_pat
)))
19216 /* We shouldn't get here, because we should have either a simple
19217 store insn or a store with update which are covered above. */
19221 /* Returns whether the dependence between INSN and NEXT is considered
19222 costly by the given target. */
19225 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
19230 /* If the flag is not enabled - no dependence is considered costly;
19231 allow all dependent insns in the same group.
19232 This is the most aggressive option. */
19233 if (rs6000_sched_costly_dep
== no_dep_costly
)
19236 /* If the flag is set to 1 - a dependence is always considered costly;
19237 do not allow dependent instructions in the same group.
19238 This is the most conservative option. */
19239 if (rs6000_sched_costly_dep
== all_deps_costly
)
19242 insn
= DEP_PRO (dep
);
19243 next
= DEP_CON (dep
);
19245 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
19246 && is_load_insn (next
)
19247 && is_store_insn (insn
))
19248 /* Prevent load after store in the same group. */
19251 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
19252 && is_load_insn (next
)
19253 && is_store_insn (insn
)
19254 && DEP_TYPE (dep
) == REG_DEP_TRUE
)
19255 /* Prevent load after store in the same group if it is a true
19259 /* The flag is set to X; dependences with latency >= X are considered costly,
19260 and will not be scheduled in the same group. */
19261 if (rs6000_sched_costly_dep
<= max_dep_latency
19262 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
19268 /* Return the next insn after INSN that is found before TAIL is reached,
19269 skipping any "non-active" insns - insns that will not actually occupy
19270 an issue slot. Return NULL_RTX if such an insn is not found. */
19273 get_next_active_insn (rtx insn
, rtx tail
)
19275 if (insn
== NULL_RTX
|| insn
== tail
)
19280 insn
= NEXT_INSN (insn
);
19281 if (insn
== NULL_RTX
|| insn
== tail
)
19286 || (NONJUMP_INSN_P (insn
)
19287 && GET_CODE (PATTERN (insn
)) != USE
19288 && GET_CODE (PATTERN (insn
)) != CLOBBER
19289 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
19295 /* We are about to begin issuing insns for this clock cycle. */
19298 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
19299 rtx
*ready ATTRIBUTE_UNUSED
,
19300 int *pn_ready ATTRIBUTE_UNUSED
,
19301 int clock_var ATTRIBUTE_UNUSED
)
19303 int n_ready
= *pn_ready
;
19306 fprintf (dump
, "// rs6000_sched_reorder :\n");
19308 /* Reorder the ready list, if the second to last ready insn
19309 is a nonepipeline insn. */
19310 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
19312 if (is_nonpipeline_insn (ready
[n_ready
- 1])
19313 && (recog_memoized (ready
[n_ready
- 2]) > 0))
19314 /* Simply swap first two insns. */
19316 rtx tmp
= ready
[n_ready
- 1];
19317 ready
[n_ready
- 1] = ready
[n_ready
- 2];
19318 ready
[n_ready
- 2] = tmp
;
19322 if (rs6000_cpu
== PROCESSOR_POWER6
)
19323 load_store_pendulum
= 0;
19325 return rs6000_issue_rate ();
19328 /* Like rs6000_sched_reorder, but called after issuing each insn. */
19331 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
19332 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
19335 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
19337 /* For Power6, we need to handle some special cases to try and keep the
19338 store queue from overflowing and triggering expensive flushes.
19340 This code monitors how load and store instructions are being issued
19341 and skews the ready list one way or the other to increase the likelihood
19342 that a desired instruction is issued at the proper time.
19344 A couple of things are done. First, we maintain a "load_store_pendulum"
19345 to track the current state of load/store issue.
19347 - If the pendulum is at zero, then no loads or stores have been
19348 issued in the current cycle so we do nothing.
19350 - If the pendulum is 1, then a single load has been issued in this
19351 cycle and we attempt to locate another load in the ready list to
19354 - If the pendulum is -2, then two stores have already been
19355 issued in this cycle, so we increase the priority of the first load
19356 in the ready list to increase it's likelihood of being chosen first
19359 - If the pendulum is -1, then a single store has been issued in this
19360 cycle and we attempt to locate another store in the ready list to
19361 issue with it, preferring a store to an adjacent memory location to
19362 facilitate store pairing in the store queue.
19364 - If the pendulum is 2, then two loads have already been
19365 issued in this cycle, so we increase the priority of the first store
19366 in the ready list to increase it's likelihood of being chosen first
19369 - If the pendulum < -2 or > 2, then do nothing.
19371 Note: This code covers the most common scenarios. There exist non
19372 load/store instructions which make use of the LSU and which
19373 would need to be accounted for to strictly model the behavior
19374 of the machine. Those instructions are currently unaccounted
19375 for to help minimize compile time overhead of this code.
19377 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
19383 if (is_store_insn (last_scheduled_insn
))
19384 /* Issuing a store, swing the load_store_pendulum to the left */
19385 load_store_pendulum
--;
19386 else if (is_load_insn (last_scheduled_insn
))
19387 /* Issuing a load, swing the load_store_pendulum to the right */
19388 load_store_pendulum
++;
19390 return cached_can_issue_more
;
19392 /* If the pendulum is balanced, or there is only one instruction on
19393 the ready list, then all is well, so return. */
19394 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
19395 return cached_can_issue_more
;
19397 if (load_store_pendulum
== 1)
19399 /* A load has been issued in this cycle. Scan the ready list
19400 for another load to issue with it */
19405 if (is_load_insn (ready
[pos
]))
19407 /* Found a load. Move it to the head of the ready list,
19408 and adjust it's priority so that it is more likely to
19411 for (i
=pos
; i
<*pn_ready
-1; i
++)
19412 ready
[i
] = ready
[i
+ 1];
19413 ready
[*pn_ready
-1] = tmp
;
19414 if INSN_PRIORITY_KNOWN (tmp
)
19415 INSN_PRIORITY (tmp
)++;
19421 else if (load_store_pendulum
== -2)
19423 /* Two stores have been issued in this cycle. Increase the
19424 priority of the first load in the ready list to favor it for
19425 issuing in the next cycle. */
19430 if (is_load_insn (ready
[pos
])
19431 && INSN_PRIORITY_KNOWN (ready
[pos
]))
19433 INSN_PRIORITY (ready
[pos
])++;
19435 /* Adjust the pendulum to account for the fact that a load
19436 was found and increased in priority. This is to prevent
19437 increasing the priority of multiple loads */
19438 load_store_pendulum
--;
19445 else if (load_store_pendulum
== -1)
19447 /* A store has been issued in this cycle. Scan the ready list for
19448 another store to issue with it, preferring a store to an adjacent
19450 int first_store_pos
= -1;
19456 if (is_store_insn (ready
[pos
]))
19458 /* Maintain the index of the first store found on the
19460 if (first_store_pos
== -1)
19461 first_store_pos
= pos
;
19463 if (is_store_insn (last_scheduled_insn
)
19464 && adjacent_mem_locations (last_scheduled_insn
,ready
[pos
]))
19466 /* Found an adjacent store. Move it to the head of the
19467 ready list, and adjust it's priority so that it is
19468 more likely to stay there */
19470 for (i
=pos
; i
<*pn_ready
-1; i
++)
19471 ready
[i
] = ready
[i
+ 1];
19472 ready
[*pn_ready
-1] = tmp
;
19473 if INSN_PRIORITY_KNOWN (tmp
)
19474 INSN_PRIORITY (tmp
)++;
19475 first_store_pos
= -1;
19483 if (first_store_pos
>= 0)
19485 /* An adjacent store wasn't found, but a non-adjacent store was,
19486 so move the non-adjacent store to the front of the ready
19487 list, and adjust its priority so that it is more likely to
19489 tmp
= ready
[first_store_pos
];
19490 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
19491 ready
[i
] = ready
[i
+ 1];
19492 ready
[*pn_ready
-1] = tmp
;
19493 if INSN_PRIORITY_KNOWN (tmp
)
19494 INSN_PRIORITY (tmp
)++;
19497 else if (load_store_pendulum
== 2)
19499 /* Two loads have been issued in this cycle. Increase the priority
19500 of the first store in the ready list to favor it for issuing in
19506 if (is_store_insn (ready
[pos
])
19507 && INSN_PRIORITY_KNOWN (ready
[pos
]))
19509 INSN_PRIORITY (ready
[pos
])++;
19511 /* Adjust the pendulum to account for the fact that a store
19512 was found and increased in priority. This is to prevent
19513 increasing the priority of multiple stores */
19514 load_store_pendulum
++;
19523 return cached_can_issue_more
;
19526 /* Return whether the presence of INSN causes a dispatch group termination
19527 of group WHICH_GROUP.
19529 If WHICH_GROUP == current_group, this function will return true if INSN
19530 causes the termination of the current group (i.e, the dispatch group to
19531 which INSN belongs). This means that INSN will be the last insn in the
19532 group it belongs to.
19534 If WHICH_GROUP == previous_group, this function will return true if INSN
19535 causes the termination of the previous group (i.e, the dispatch group that
19536 precedes the group to which INSN belongs). This means that INSN will be
19537 the first insn in the group it belongs to). */
19540 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
19547 first
= insn_must_be_first_in_group (insn
);
19548 last
= insn_must_be_last_in_group (insn
);
19553 if (which_group
== current_group
)
19555 else if (which_group
== previous_group
)
19563 insn_must_be_first_in_group (rtx insn
)
19565 enum attr_type type
;
19568 || insn
== NULL_RTX
19569 || GET_CODE (insn
) == NOTE
19570 || GET_CODE (PATTERN (insn
)) == USE
19571 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19574 switch (rs6000_cpu
)
19576 case PROCESSOR_POWER5
:
19577 if (is_cracked_insn (insn
))
19579 case PROCESSOR_POWER4
:
19580 if (is_microcoded_insn (insn
))
19583 if (!rs6000_sched_groups
)
19586 type
= get_attr_type (insn
);
19593 case TYPE_DELAYED_CR
:
19594 case TYPE_CR_LOGICAL
:
19608 case PROCESSOR_POWER6
:
19609 type
= get_attr_type (insn
);
19613 case TYPE_INSERT_DWORD
:
19617 case TYPE_VAR_SHIFT_ROTATE
:
19624 case TYPE_INSERT_WORD
:
19625 case TYPE_DELAYED_COMPARE
:
19626 case TYPE_IMUL_COMPARE
:
19627 case TYPE_LMUL_COMPARE
:
19628 case TYPE_FPCOMPARE
:
19639 case TYPE_LOAD_EXT_UX
:
19641 case TYPE_STORE_UX
:
19642 case TYPE_FPLOAD_U
:
19643 case TYPE_FPLOAD_UX
:
19644 case TYPE_FPSTORE_U
:
19645 case TYPE_FPSTORE_UX
:
19659 insn_must_be_last_in_group (rtx insn
)
19661 enum attr_type type
;
19664 || insn
== NULL_RTX
19665 || GET_CODE (insn
) == NOTE
19666 || GET_CODE (PATTERN (insn
)) == USE
19667 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19670 switch (rs6000_cpu
) {
19671 case PROCESSOR_POWER4
:
19672 case PROCESSOR_POWER5
:
19673 if (is_microcoded_insn (insn
))
19676 if (is_branch_slot_insn (insn
))
19680 case PROCESSOR_POWER6
:
19681 type
= get_attr_type (insn
);
19688 case TYPE_VAR_SHIFT_ROTATE
:
19695 case TYPE_DELAYED_COMPARE
:
19696 case TYPE_IMUL_COMPARE
:
19697 case TYPE_LMUL_COMPARE
:
19698 case TYPE_FPCOMPARE
:
19719 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19720 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19723 is_costly_group (rtx
*group_insns
, rtx next_insn
)
19726 int issue_rate
= rs6000_issue_rate ();
19728 for (i
= 0; i
< issue_rate
; i
++)
19730 sd_iterator_def sd_it
;
19732 rtx insn
= group_insns
[i
];
19737 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
19739 rtx next
= DEP_CON (dep
);
19741 if (next
== next_insn
19742 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
19750 /* Utility of the function redefine_groups.
19751 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19752 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
19753 to keep it "far" (in a separate group) from GROUP_INSNS, following
19754 one of the following schemes, depending on the value of the flag
19755 -minsert_sched_nops = X:
19756 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
19757 in order to force NEXT_INSN into a separate group.
19758 (2) X < sched_finish_regroup_exact: insert exactly X nops.
19759 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
19760 insertion (has a group just ended, how many vacant issue slots remain in the
19761 last group, and how many dispatch groups were encountered so far). */
19764 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
19765 rtx next_insn
, bool *group_end
, int can_issue_more
,
19770 int issue_rate
= rs6000_issue_rate ();
19771 bool end
= *group_end
;
19774 if (next_insn
== NULL_RTX
)
19775 return can_issue_more
;
19777 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
19778 return can_issue_more
;
19780 force
= is_costly_group (group_insns
, next_insn
);
19782 return can_issue_more
;
19784 if (sched_verbose
> 6)
19785 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
19786 *group_count
,can_issue_more
);
19788 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
19791 can_issue_more
= 0;
19793 /* Since only a branch can be issued in the last issue_slot, it is
19794 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
19795 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
19796 in this case the last nop will start a new group and the branch
19797 will be forced to the new group. */
19798 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
19801 while (can_issue_more
> 0)
19804 emit_insn_before (nop
, next_insn
);
19812 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
19814 int n_nops
= rs6000_sched_insert_nops
;
19816 /* Nops can't be issued from the branch slot, so the effective
19817 issue_rate for nops is 'issue_rate - 1'. */
19818 if (can_issue_more
== 0)
19819 can_issue_more
= issue_rate
;
19821 if (can_issue_more
== 0)
19823 can_issue_more
= issue_rate
- 1;
19826 for (i
= 0; i
< issue_rate
; i
++)
19828 group_insns
[i
] = 0;
19835 emit_insn_before (nop
, next_insn
);
19836 if (can_issue_more
== issue_rate
- 1) /* new group begins */
19839 if (can_issue_more
== 0)
19841 can_issue_more
= issue_rate
- 1;
19844 for (i
= 0; i
< issue_rate
; i
++)
19846 group_insns
[i
] = 0;
19852 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19855 /* Is next_insn going to start a new group? */
19858 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19859 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19860 || (can_issue_more
< issue_rate
&&
19861 insn_terminates_group_p (next_insn
, previous_group
)));
19862 if (*group_end
&& end
)
19865 if (sched_verbose
> 6)
19866 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
19867 *group_count
, can_issue_more
);
19868 return can_issue_more
;
19871 return can_issue_more
;
19874 /* This function tries to synch the dispatch groups that the compiler "sees"
19875 with the dispatch groups that the processor dispatcher is expected to
19876 form in practice. It tries to achieve this synchronization by forcing the
19877 estimated processor grouping on the compiler (as opposed to the function
19878 'pad_goups' which tries to force the scheduler's grouping on the processor).
19880 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19881 examines the (estimated) dispatch groups that will be formed by the processor
19882 dispatcher. It marks these group boundaries to reflect the estimated
19883 processor grouping, overriding the grouping that the scheduler had marked.
19884 Depending on the value of the flag '-minsert-sched-nops' this function can
19885 force certain insns into separate groups or force a certain distance between
19886 them by inserting nops, for example, if there exists a "costly dependence"
19889 The function estimates the group boundaries that the processor will form as
19890 follows: It keeps track of how many vacant issue slots are available after
19891 each insn. A subsequent insn will start a new group if one of the following
19893 - no more vacant issue slots remain in the current dispatch group.
19894 - only the last issue slot, which is the branch slot, is vacant, but the next
19895 insn is not a branch.
19896 - only the last 2 or less issue slots, including the branch slot, are vacant,
19897 which means that a cracked insn (which occupies two issue slots) can't be
19898 issued in this group.
19899 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19900 start a new group. */
19903 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19905 rtx insn
, next_insn
;
19907 int can_issue_more
;
19910 int group_count
= 0;
19914 issue_rate
= rs6000_issue_rate ();
19915 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
19916 for (i
= 0; i
< issue_rate
; i
++)
19918 group_insns
[i
] = 0;
19920 can_issue_more
= issue_rate
;
19922 insn
= get_next_active_insn (prev_head_insn
, tail
);
19925 while (insn
!= NULL_RTX
)
19927 slot
= (issue_rate
- can_issue_more
);
19928 group_insns
[slot
] = insn
;
19930 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
19931 if (insn_terminates_group_p (insn
, current_group
))
19932 can_issue_more
= 0;
19934 next_insn
= get_next_active_insn (insn
, tail
);
19935 if (next_insn
== NULL_RTX
)
19936 return group_count
+ 1;
19938 /* Is next_insn going to start a new group? */
19940 = (can_issue_more
== 0
19941 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19942 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19943 || (can_issue_more
< issue_rate
&&
19944 insn_terminates_group_p (next_insn
, previous_group
)));
19946 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
19947 next_insn
, &group_end
, can_issue_more
,
19953 can_issue_more
= 0;
19954 for (i
= 0; i
< issue_rate
; i
++)
19956 group_insns
[i
] = 0;
19960 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
19961 PUT_MODE (next_insn
, VOIDmode
);
19962 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
19963 PUT_MODE (next_insn
, TImode
);
19966 if (can_issue_more
== 0)
19967 can_issue_more
= issue_rate
;
19970 return group_count
;
19973 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19974 dispatch group boundaries that the scheduler had marked. Pad with nops
19975 any dispatch groups which have vacant issue slots, in order to force the
19976 scheduler's grouping on the processor dispatcher. The function
19977 returns the number of dispatch groups found. */
19980 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19982 rtx insn
, next_insn
;
19985 int can_issue_more
;
19987 int group_count
= 0;
19989 /* Initialize issue_rate. */
19990 issue_rate
= rs6000_issue_rate ();
19991 can_issue_more
= issue_rate
;
19993 insn
= get_next_active_insn (prev_head_insn
, tail
);
19994 next_insn
= get_next_active_insn (insn
, tail
);
19996 while (insn
!= NULL_RTX
)
19999 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
20001 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
20003 if (next_insn
== NULL_RTX
)
20008 /* If the scheduler had marked group termination at this location
20009 (between insn and next_indn), and neither insn nor next_insn will
20010 force group termination, pad the group with nops to force group
20013 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
20014 && !insn_terminates_group_p (insn
, current_group
)
20015 && !insn_terminates_group_p (next_insn
, previous_group
))
20017 if (!is_branch_slot_insn (next_insn
))
20020 while (can_issue_more
)
20023 emit_insn_before (nop
, next_insn
);
20028 can_issue_more
= issue_rate
;
20033 next_insn
= get_next_active_insn (insn
, tail
);
20036 return group_count
;
20039 /* We're beginning a new block. Initialize data structures as necessary. */
20042 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
20043 int sched_verbose ATTRIBUTE_UNUSED
,
20044 int max_ready ATTRIBUTE_UNUSED
)
20046 last_scheduled_insn
= NULL_RTX
;
20047 load_store_pendulum
= 0;
20050 /* The following function is called at the end of scheduling BB.
20051 After reload, it inserts nops at insn group bundling. */
20054 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
20059 fprintf (dump
, "=== Finishing schedule.\n");
20061 if (reload_completed
&& rs6000_sched_groups
)
20063 if (rs6000_sched_insert_nops
== sched_finish_none
)
20066 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
20067 n_groups
= pad_groups (dump
, sched_verbose
,
20068 current_sched_info
->prev_head
,
20069 current_sched_info
->next_tail
);
20071 n_groups
= redefine_groups (dump
, sched_verbose
,
20072 current_sched_info
->prev_head
,
20073 current_sched_info
->next_tail
);
20075 if (sched_verbose
>= 6)
20077 fprintf (dump
, "ngroups = %d\n", n_groups
);
20078 print_rtl (dump
, current_sched_info
->prev_head
);
20079 fprintf (dump
, "Done finish_sched\n");
20084 /* Length in units of the trampoline for entering a nested function. */
20087 rs6000_trampoline_size (void)
20091 switch (DEFAULT_ABI
)
20094 gcc_unreachable ();
20097 ret
= (TARGET_32BIT
) ? 12 : 24;
20102 ret
= (TARGET_32BIT
) ? 40 : 48;
20109 /* Emit RTL insns to initialize the variable parts of a trampoline.
20110 FNADDR is an RTX for the address of the function's pure code.
20111 CXT is an RTX for the static chain value for the function. */
20114 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
20116 int regsize
= (TARGET_32BIT
) ? 4 : 8;
20117 rtx ctx_reg
= force_reg (Pmode
, cxt
);
20119 switch (DEFAULT_ABI
)
20122 gcc_unreachable ();
20124 /* Macros to shorten the code expansions below. */
20125 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
20126 #define MEM_PLUS(addr,offset) \
20127 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
20129 /* Under AIX, just build the 3 word function descriptor */
20132 rtx fn_reg
= gen_reg_rtx (Pmode
);
20133 rtx toc_reg
= gen_reg_rtx (Pmode
);
20134 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
20135 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
20136 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
20137 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
20138 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
20142 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
20145 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
20146 FALSE
, VOIDmode
, 4,
20148 GEN_INT (rs6000_trampoline_size ()), SImode
,
20158 /* Table of valid machine attributes. */
20160 const struct attribute_spec rs6000_attribute_table
[] =
20162 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
20163 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
20164 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
20165 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
20166 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
20167 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
20168 #ifdef SUBTARGET_ATTRIBUTE_TABLE
20169 SUBTARGET_ATTRIBUTE_TABLE
,
20171 { NULL
, 0, 0, false, false, false, NULL
}
20174 /* Handle the "altivec" attribute. The attribute may have
20175 arguments as follows:
20177 __attribute__((altivec(vector__)))
20178 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
20179 __attribute__((altivec(bool__))) (always followed by 'unsigned')
20181 and may appear more than once (e.g., 'vector bool char') in a
20182 given declaration. */
20185 rs6000_handle_altivec_attribute (tree
*node
,
20186 tree name ATTRIBUTE_UNUSED
,
20188 int flags ATTRIBUTE_UNUSED
,
20189 bool *no_add_attrs
)
20191 tree type
= *node
, result
= NULL_TREE
;
20192 enum machine_mode mode
;
20195 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
20196 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
20197 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
20200 while (POINTER_TYPE_P (type
)
20201 || TREE_CODE (type
) == FUNCTION_TYPE
20202 || TREE_CODE (type
) == METHOD_TYPE
20203 || TREE_CODE (type
) == ARRAY_TYPE
)
20204 type
= TREE_TYPE (type
);
20206 mode
= TYPE_MODE (type
);
20208 /* Check for invalid AltiVec type qualifiers. */
20209 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
20212 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
20213 else if (rs6000_warn_altivec_long
)
20214 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
20216 else if (type
== long_long_unsigned_type_node
20217 || type
== long_long_integer_type_node
)
20218 error ("use of %<long long%> in AltiVec types is invalid");
20219 else if (type
== double_type_node
)
20220 error ("use of %<double%> in AltiVec types is invalid");
20221 else if (type
== long_double_type_node
)
20222 error ("use of %<long double%> in AltiVec types is invalid");
20223 else if (type
== boolean_type_node
)
20224 error ("use of boolean types in AltiVec types is invalid");
20225 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
20226 error ("use of %<complex%> in AltiVec types is invalid");
20227 else if (DECIMAL_FLOAT_MODE_P (mode
))
20228 error ("use of decimal floating point types in AltiVec types is invalid");
20230 switch (altivec_type
)
20233 unsigned_p
= TYPE_UNSIGNED (type
);
20237 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
20240 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
20243 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
20245 case SFmode
: result
= V4SF_type_node
; break;
20246 /* If the user says 'vector int bool', we may be handed the 'bool'
20247 attribute _before_ the 'vector' attribute, and so select the
20248 proper type in the 'b' case below. */
20249 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
20257 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
20258 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
20259 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
20266 case V8HImode
: result
= pixel_V8HI_type_node
;
20272 if (result
&& result
!= type
&& TYPE_READONLY (type
))
20273 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
20275 *no_add_attrs
= true; /* No need to hang on to the attribute. */
20278 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
20283 /* AltiVec defines four built-in scalar types that serve as vector
20284 elements; we must teach the compiler how to mangle them. */
20286 static const char *
20287 rs6000_mangle_type (const_tree type
)
20289 type
= TYPE_MAIN_VARIANT (type
);
20291 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
20292 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
20295 if (type
== bool_char_type_node
) return "U6__boolc";
20296 if (type
== bool_short_type_node
) return "U6__bools";
20297 if (type
== pixel_type_node
) return "u7__pixel";
20298 if (type
== bool_int_type_node
) return "U6__booli";
20300 /* Mangle IBM extended float long double as `g' (__float128) on
20301 powerpc*-linux where long-double-64 previously was the default. */
20302 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
20304 && TARGET_LONG_DOUBLE_128
20305 && !TARGET_IEEEQUAD
)
20308 /* For all other types, use normal C++ mangling. */
20312 /* Handle a "longcall" or "shortcall" attribute; arguments as in
20313 struct attribute_spec.handler. */
20316 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
20317 tree args ATTRIBUTE_UNUSED
,
20318 int flags ATTRIBUTE_UNUSED
,
20319 bool *no_add_attrs
)
20321 if (TREE_CODE (*node
) != FUNCTION_TYPE
20322 && TREE_CODE (*node
) != FIELD_DECL
20323 && TREE_CODE (*node
) != TYPE_DECL
)
20325 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
20326 IDENTIFIER_POINTER (name
));
20327 *no_add_attrs
= true;
20333 /* Set longcall attributes on all functions declared when
20334 rs6000_default_long_calls is true. */
20336 rs6000_set_default_type_attributes (tree type
)
20338 if (rs6000_default_long_calls
20339 && (TREE_CODE (type
) == FUNCTION_TYPE
20340 || TREE_CODE (type
) == METHOD_TYPE
))
20341 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
20343 TYPE_ATTRIBUTES (type
));
20346 darwin_set_default_type_attributes (type
);
20350 /* Return a reference suitable for calling a function with the
20351 longcall attribute. */
20354 rs6000_longcall_ref (rtx call_ref
)
20356 const char *call_name
;
20359 if (GET_CODE (call_ref
) != SYMBOL_REF
)
20362 /* System V adds '.' to the internal name, so skip them. */
20363 call_name
= XSTR (call_ref
, 0);
20364 if (*call_name
== '.')
20366 while (*call_name
== '.')
20369 node
= get_identifier (call_name
);
20370 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
20373 return force_reg (Pmode
, call_ref
);
20376 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
20377 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
20380 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20381 struct attribute_spec.handler. */
20383 rs6000_handle_struct_attribute (tree
*node
, tree name
,
20384 tree args ATTRIBUTE_UNUSED
,
20385 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
20388 if (DECL_P (*node
))
20390 if (TREE_CODE (*node
) == TYPE_DECL
)
20391 type
= &TREE_TYPE (*node
);
20396 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
20397 || TREE_CODE (*type
) == UNION_TYPE
)))
20399 warning (OPT_Wattributes
, "%qs attribute ignored", IDENTIFIER_POINTER (name
));
20400 *no_add_attrs
= true;
20403 else if ((is_attribute_p ("ms_struct", name
)
20404 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
20405 || ((is_attribute_p ("gcc_struct", name
)
20406 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
20408 warning (OPT_Wattributes
, "%qs incompatible attribute ignored",
20409 IDENTIFIER_POINTER (name
));
20410 *no_add_attrs
= true;
20417 rs6000_ms_bitfield_layout_p (const_tree record_type
)
20419 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
20420 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
20421 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
20424 #ifdef USING_ELFOS_H
20426 /* A get_unnamed_section callback, used for switching to toc_section. */
20429 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
20431 if (DEFAULT_ABI
== ABI_AIX
20432 && TARGET_MINIMAL_TOC
20433 && !TARGET_RELOCATABLE
)
20435 if (!toc_initialized
)
20437 toc_initialized
= 1;
20438 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
20439 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
20440 fprintf (asm_out_file
, "\t.tc ");
20441 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
20442 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20443 fprintf (asm_out_file
, "\n");
20445 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20446 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20447 fprintf (asm_out_file
, " = .+32768\n");
20450 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20452 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
20453 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
20456 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20457 if (!toc_initialized
)
20459 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
20460 fprintf (asm_out_file
, " = .+32768\n");
20461 toc_initialized
= 1;
20466 /* Implement TARGET_ASM_INIT_SECTIONS. */
20469 rs6000_elf_asm_init_sections (void)
20472 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
20475 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
20476 SDATA2_SECTION_ASM_OP
);
20479 /* Implement TARGET_SELECT_RTX_SECTION. */
20482 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
20483 unsigned HOST_WIDE_INT align
)
20485 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
20486 return toc_section
;
20488 return default_elf_select_rtx_section (mode
, x
, align
);
20491 /* For a SYMBOL_REF, set generic flags and then perform some
20492 target-specific processing.
20494 When the AIX ABI is requested on a non-AIX system, replace the
20495 function name with the real name (with a leading .) rather than the
20496 function descriptor name. This saves a lot of overriding code to
20497 read the prefixes. */
20500 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
20502 default_encode_section_info (decl
, rtl
, first
);
20505 && TREE_CODE (decl
) == FUNCTION_DECL
20507 && DEFAULT_ABI
== ABI_AIX
)
20509 rtx sym_ref
= XEXP (rtl
, 0);
20510 size_t len
= strlen (XSTR (sym_ref
, 0));
20511 char *str
= XALLOCAVEC (char, len
+ 2);
20513 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
20514 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
20519 compare_section_name (const char *section
, const char *template)
20523 len
= strlen (template);
20524 return (strncmp (section
, template, len
) == 0
20525 && (section
[len
] == 0 || section
[len
] == '.'));
20529 rs6000_elf_in_small_data_p (const_tree decl
)
20531 if (rs6000_sdata
== SDATA_NONE
)
20534 /* We want to merge strings, so we never consider them small data. */
20535 if (TREE_CODE (decl
) == STRING_CST
)
20538 /* Functions are never in the small data area. */
20539 if (TREE_CODE (decl
) == FUNCTION_DECL
)
20542 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
20544 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
20545 if (compare_section_name (section
, ".sdata")
20546 || compare_section_name (section
, ".sdata2")
20547 || compare_section_name (section
, ".gnu.linkonce.s")
20548 || compare_section_name (section
, ".sbss")
20549 || compare_section_name (section
, ".sbss2")
20550 || compare_section_name (section
, ".gnu.linkonce.sb")
20551 || strcmp (section
, ".PPC.EMB.sdata0") == 0
20552 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
20557 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
20560 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
20561 /* If it's not public, and we're not going to reference it there,
20562 there's no need to put it in the small data section. */
20563 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
20570 #endif /* USING_ELFOS_H */
20572 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20575 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
20577 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
20580 /* Return a REG that occurs in ADDR with coefficient 1.
20581 ADDR can be effectively incremented by incrementing REG.
20583 r0 is special and we must not select it as an address
20584 register by this routine since our caller will try to
20585 increment the returned register via an "la" instruction. */
20588 find_addr_reg (rtx addr
)
20590 while (GET_CODE (addr
) == PLUS
)
20592 if (GET_CODE (XEXP (addr
, 0)) == REG
20593 && REGNO (XEXP (addr
, 0)) != 0)
20594 addr
= XEXP (addr
, 0);
20595 else if (GET_CODE (XEXP (addr
, 1)) == REG
20596 && REGNO (XEXP (addr
, 1)) != 0)
20597 addr
= XEXP (addr
, 1);
20598 else if (CONSTANT_P (XEXP (addr
, 0)))
20599 addr
= XEXP (addr
, 1);
20600 else if (CONSTANT_P (XEXP (addr
, 1)))
20601 addr
= XEXP (addr
, 0);
20603 gcc_unreachable ();
20605 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
20610 rs6000_fatal_bad_address (rtx op
)
20612 fatal_insn ("bad address", op
);
20617 static tree branch_island_list
= 0;
20619 /* Remember to generate a branch island for far calls to the given
20623 add_compiler_branch_island (tree label_name
, tree function_name
,
20626 tree branch_island
= build_tree_list (function_name
, label_name
);
20627 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
20628 TREE_CHAIN (branch_island
) = branch_island_list
;
20629 branch_island_list
= branch_island
;
20632 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20633 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20634 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20635 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20637 /* Generate far-jump branch islands for everything on the
20638 branch_island_list. Invoked immediately after the last instruction
20639 of the epilogue has been emitted; the branch-islands must be
20640 appended to, and contiguous with, the function body. Mach-O stubs
20641 are generated in machopic_output_stub(). */
20644 macho_branch_islands (void)
20647 tree branch_island
;
20649 for (branch_island
= branch_island_list
;
20651 branch_island
= TREE_CHAIN (branch_island
))
20653 const char *label
=
20654 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
20656 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
20657 char name_buf
[512];
20658 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20659 if (name
[0] == '*' || name
[0] == '&')
20660 strcpy (name_buf
, name
+1);
20664 strcpy (name_buf
+1, name
);
20666 strcpy (tmp_buf
, "\n");
20667 strcat (tmp_buf
, label
);
20668 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20669 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20670 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20671 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20674 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
20675 strcat (tmp_buf
, label
);
20676 strcat (tmp_buf
, "_pic\n");
20677 strcat (tmp_buf
, label
);
20678 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
20680 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
20681 strcat (tmp_buf
, name_buf
);
20682 strcat (tmp_buf
, " - ");
20683 strcat (tmp_buf
, label
);
20684 strcat (tmp_buf
, "_pic)\n");
20686 strcat (tmp_buf
, "\tmtlr r0\n");
20688 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
20689 strcat (tmp_buf
, name_buf
);
20690 strcat (tmp_buf
, " - ");
20691 strcat (tmp_buf
, label
);
20692 strcat (tmp_buf
, "_pic)\n");
20694 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
20698 strcat (tmp_buf
, ":\nlis r12,hi16(");
20699 strcat (tmp_buf
, name_buf
);
20700 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
20701 strcat (tmp_buf
, name_buf
);
20702 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
20704 output_asm_insn (tmp_buf
, 0);
20705 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20706 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20707 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20708 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20711 branch_island_list
= 0;
20714 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
20715 already there or not. */
20718 no_previous_def (tree function_name
)
20720 tree branch_island
;
20721 for (branch_island
= branch_island_list
;
20723 branch_island
= TREE_CHAIN (branch_island
))
20724 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
20729 /* GET_PREV_LABEL gets the label name from the previous definition of
20733 get_prev_label (tree function_name
)
20735 tree branch_island
;
20736 for (branch_island
= branch_island_list
;
20738 branch_island
= TREE_CHAIN (branch_island
))
20739 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
20740 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
20744 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
20745 #define DARWIN_LINKER_GENERATES_ISLANDS 0
20748 /* KEXTs still need branch islands. */
20749 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
20750 || flag_mkernel || flag_apple_kext)
20752 /* INSN is either a function call or a millicode call. It may have an
20753 unconditional jump in its delay slot.
20755 CALL_DEST is the routine we are calling. */
20758 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
20759 int cookie_operand_number
)
20761 static char buf
[256];
20762 if (DARWIN_GENERATE_ISLANDS
20763 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
20764 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
20767 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
20769 if (no_previous_def (funname
))
20771 rtx label_rtx
= gen_label_rtx ();
20772 char *label_buf
, temp_buf
[256];
20773 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
20774 CODE_LABEL_NUMBER (label_rtx
));
20775 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
20776 labelname
= get_identifier (label_buf
);
20777 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
20780 labelname
= get_prev_label (funname
);
20782 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
20783 instruction will reach 'foo', otherwise link as 'bl L42'".
20784 "L42" should be a 'branch island', that will do a far jump to
20785 'foo'. Branch islands are generated in
20786 macho_branch_islands(). */
20787 sprintf (buf
, "jbsr %%z%d,%.246s",
20788 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
20791 sprintf (buf
, "bl %%z%d", dest_operand_number
);
20795 /* Generate PIC and indirect symbol stubs. */
20798 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
20800 unsigned int length
;
20801 char *symbol_name
, *lazy_ptr_name
;
20802 char *local_label_0
;
20803 static int label
= 0;
20805 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20806 symb
= (*targetm
.strip_name_encoding
) (symb
);
20809 length
= strlen (symb
);
20810 symbol_name
= XALLOCAVEC (char, length
+ 32);
20811 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
20813 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
20814 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
20817 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
20819 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
20823 fprintf (file
, "\t.align 5\n");
20825 fprintf (file
, "%s:\n", stub
);
20826 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20829 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
20830 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
20832 fprintf (file
, "\tmflr r0\n");
20833 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
20834 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
20835 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
20836 lazy_ptr_name
, local_label_0
);
20837 fprintf (file
, "\tmtlr r0\n");
20838 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
20839 (TARGET_64BIT
? "ldu" : "lwzu"),
20840 lazy_ptr_name
, local_label_0
);
20841 fprintf (file
, "\tmtctr r12\n");
20842 fprintf (file
, "\tbctr\n");
20846 fprintf (file
, "\t.align 4\n");
20848 fprintf (file
, "%s:\n", stub
);
20849 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20851 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
20852 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
20853 (TARGET_64BIT
? "ldu" : "lwzu"),
20855 fprintf (file
, "\tmtctr r12\n");
20856 fprintf (file
, "\tbctr\n");
20859 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
20860 fprintf (file
, "%s:\n", lazy_ptr_name
);
20861 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20862 fprintf (file
, "%sdyld_stub_binding_helper\n",
20863 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
20866 /* Legitimize PIC addresses. If the address is already
20867 position-independent, we return ORIG. Newly generated
20868 position-independent addresses go into a reg. This is REG if non
20869 zero, otherwise we allocate register(s) as necessary. */
20871 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20874 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
20879 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
20880 reg
= gen_reg_rtx (Pmode
);
20882 if (GET_CODE (orig
) == CONST
)
20886 if (GET_CODE (XEXP (orig
, 0)) == PLUS
20887 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
20890 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
20892 /* Use a different reg for the intermediate value, as
20893 it will be marked UNCHANGING. */
20894 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
20895 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
20898 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
20901 if (GET_CODE (offset
) == CONST_INT
)
20903 if (SMALL_INT (offset
))
20904 return plus_constant (base
, INTVAL (offset
));
20905 else if (! reload_in_progress
&& ! reload_completed
)
20906 offset
= force_reg (Pmode
, offset
);
20909 rtx mem
= force_const_mem (Pmode
, orig
);
20910 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
20913 return gen_rtx_PLUS (Pmode
, base
, offset
);
20916 /* Fall back on generic machopic code. */
20917 return machopic_legitimize_pic_address (orig
, mode
, reg
);
20920 /* Output a .machine directive for the Darwin assembler, and call
20921 the generic start_file routine. */
20924 rs6000_darwin_file_start (void)
20926 static const struct
20932 { "ppc64", "ppc64", MASK_64BIT
},
20933 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
20934 { "power4", "ppc970", 0 },
20935 { "G5", "ppc970", 0 },
20936 { "7450", "ppc7450", 0 },
20937 { "7400", "ppc7400", MASK_ALTIVEC
},
20938 { "G4", "ppc7400", 0 },
20939 { "750", "ppc750", 0 },
20940 { "740", "ppc750", 0 },
20941 { "G3", "ppc750", 0 },
20942 { "604e", "ppc604e", 0 },
20943 { "604", "ppc604", 0 },
20944 { "603e", "ppc603", 0 },
20945 { "603", "ppc603", 0 },
20946 { "601", "ppc601", 0 },
20947 { NULL
, "ppc", 0 } };
20948 const char *cpu_id
= "";
20951 rs6000_file_start ();
20952 darwin_file_start ();
20954 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20955 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
20956 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
20957 && rs6000_select
[i
].string
[0] != '\0')
20958 cpu_id
= rs6000_select
[i
].string
;
20960 /* Look through the mapping array. Pick the first name that either
20961 matches the argument, has a bit set in IF_SET that is also set
20962 in the target flags, or has a NULL name. */
20965 while (mapping
[i
].arg
!= NULL
20966 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
20967 && (mapping
[i
].if_set
& target_flags
) == 0)
20970 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
20973 #endif /* TARGET_MACHO */
20977 rs6000_elf_reloc_rw_mask (void)
20981 else if (DEFAULT_ABI
== ABI_AIX
)
20987 /* Record an element in the table of global constructors. SYMBOL is
20988 a SYMBOL_REF of the function to be called; PRIORITY is a number
20989 between 0 and MAX_INIT_PRIORITY.
20991 This differs from default_named_section_asm_out_constructor in
20992 that we have special handling for -mrelocatable. */
20995 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
20997 const char *section
= ".ctors";
21000 if (priority
!= DEFAULT_INIT_PRIORITY
)
21002 sprintf (buf
, ".ctors.%.5u",
21003 /* Invert the numbering so the linker puts us in the proper
21004 order; constructors are run from right to left, and the
21005 linker sorts in increasing order. */
21006 MAX_INIT_PRIORITY
- priority
);
21010 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
21011 assemble_align (POINTER_SIZE
);
21013 if (TARGET_RELOCATABLE
)
21015 fputs ("\t.long (", asm_out_file
);
21016 output_addr_const (asm_out_file
, symbol
);
21017 fputs (")@fixup\n", asm_out_file
);
21020 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
21024 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
21026 const char *section
= ".dtors";
21029 if (priority
!= DEFAULT_INIT_PRIORITY
)
21031 sprintf (buf
, ".dtors.%.5u",
21032 /* Invert the numbering so the linker puts us in the proper
21033 order; constructors are run from right to left, and the
21034 linker sorts in increasing order. */
21035 MAX_INIT_PRIORITY
- priority
);
21039 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
21040 assemble_align (POINTER_SIZE
);
21042 if (TARGET_RELOCATABLE
)
21044 fputs ("\t.long (", asm_out_file
);
21045 output_addr_const (asm_out_file
, symbol
);
21046 fputs (")@fixup\n", asm_out_file
);
21049 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
21053 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
21057 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
21058 ASM_OUTPUT_LABEL (file
, name
);
21059 fputs (DOUBLE_INT_ASM_OP
, file
);
21060 rs6000_output_function_entry (file
, name
);
21061 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
21064 fputs ("\t.size\t", file
);
21065 assemble_name (file
, name
);
21066 fputs (",24\n\t.type\t.", file
);
21067 assemble_name (file
, name
);
21068 fputs (",@function\n", file
);
21069 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
21071 fputs ("\t.globl\t.", file
);
21072 assemble_name (file
, name
);
21077 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21078 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21079 rs6000_output_function_entry (file
, name
);
21080 fputs (":\n", file
);
21084 if (TARGET_RELOCATABLE
21085 && !TARGET_SECURE_PLT
21086 && (get_pool_size () != 0 || crtl
->profile
)
21091 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
21093 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21094 fprintf (file
, "\t.long ");
21095 assemble_name (file
, buf
);
21097 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21098 assemble_name (file
, buf
);
21102 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21103 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21105 if (DEFAULT_ABI
== ABI_AIX
)
21107 const char *desc_name
, *orig_name
;
21109 orig_name
= (*targetm
.strip_name_encoding
) (name
);
21110 desc_name
= orig_name
;
21111 while (*desc_name
== '.')
21114 if (TREE_PUBLIC (decl
))
21115 fprintf (file
, "\t.globl %s\n", desc_name
);
21117 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
21118 fprintf (file
, "%s:\n", desc_name
);
21119 fprintf (file
, "\t.long %s\n", orig_name
);
21120 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
21121 if (DEFAULT_ABI
== ABI_AIX
)
21122 fputs ("\t.long 0\n", file
);
21123 fprintf (file
, "\t.previous\n");
21125 ASM_OUTPUT_LABEL (file
, name
);
21129 rs6000_elf_end_indicate_exec_stack (void)
21132 file_end_indicate_exec_stack ();
21138 rs6000_xcoff_asm_output_anchor (rtx symbol
)
21142 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
21143 SYMBOL_REF_BLOCK_OFFSET (symbol
));
21144 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
21148 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
21150 fputs (GLOBAL_ASM_OP
, stream
);
21151 RS6000_OUTPUT_BASENAME (stream
, name
);
21152 putc ('\n', stream
);
21155 /* A get_unnamed_decl callback, used for read-only sections. PTR
21156 points to the section string variable. */
21159 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
21161 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
21162 *(const char *const *) directive
,
21163 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
21166 /* Likewise for read-write sections. */
21169 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
21171 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
21172 *(const char *const *) directive
,
21173 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
21176 /* A get_unnamed_section callback, used for switching to toc_section. */
21179 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
21181 if (TARGET_MINIMAL_TOC
)
21183 /* toc_section is always selected at least once from
21184 rs6000_xcoff_file_start, so this is guaranteed to
21185 always be defined once and only once in each file. */
21186 if (!toc_initialized
)
21188 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
21189 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
21190 toc_initialized
= 1;
21192 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
21193 (TARGET_32BIT
? "" : ",3"));
21196 fputs ("\t.toc\n", asm_out_file
);
21199 /* Implement TARGET_ASM_INIT_SECTIONS. */
21202 rs6000_xcoff_asm_init_sections (void)
21204 read_only_data_section
21205 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
21206 &xcoff_read_only_section_name
);
21208 private_data_section
21209 = get_unnamed_section (SECTION_WRITE
,
21210 rs6000_xcoff_output_readwrite_section_asm_op
,
21211 &xcoff_private_data_section_name
);
21213 read_only_private_data_section
21214 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
21215 &xcoff_private_data_section_name
);
21218 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
21220 readonly_data_section
= read_only_data_section
;
21221 exception_section
= data_section
;
21225 rs6000_xcoff_reloc_rw_mask (void)
21231 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
21232 tree decl ATTRIBUTE_UNUSED
)
21235 static const char * const suffix
[3] = { "PR", "RO", "RW" };
21237 if (flags
& SECTION_CODE
)
21239 else if (flags
& SECTION_WRITE
)
21244 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
21245 (flags
& SECTION_CODE
) ? "." : "",
21246 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
21250 rs6000_xcoff_select_section (tree decl
, int reloc
,
21251 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
21253 if (decl_readonly_section (decl
, reloc
))
21255 if (TREE_PUBLIC (decl
))
21256 return read_only_data_section
;
21258 return read_only_private_data_section
;
21262 if (TREE_PUBLIC (decl
))
21263 return data_section
;
21265 return private_data_section
;
21270 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
21274 /* Use select_section for private and uninitialized data. */
21275 if (!TREE_PUBLIC (decl
)
21276 || DECL_COMMON (decl
)
21277 || DECL_INITIAL (decl
) == NULL_TREE
21278 || DECL_INITIAL (decl
) == error_mark_node
21279 || (flag_zero_initialized_in_bss
21280 && initializer_zerop (DECL_INITIAL (decl
))))
21283 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
21284 name
= (*targetm
.strip_name_encoding
) (name
);
21285 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
21288 /* Select section for constant in constant pool.
21290 On RS/6000, all constants are in the private read-only data area.
21291 However, if this is being placed in the TOC it must be output as a
21295 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
21296 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
21298 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
21299 return toc_section
;
21301 return read_only_private_data_section
;
21304 /* Remove any trailing [DS] or the like from the symbol name. */
21306 static const char *
21307 rs6000_xcoff_strip_name_encoding (const char *name
)
21312 len
= strlen (name
);
21313 if (name
[len
- 1] == ']')
21314 return ggc_alloc_string (name
, len
- 4);
21319 /* Section attributes. AIX is always PIC. */
21321 static unsigned int
21322 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
21324 unsigned int align
;
21325 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
21327 /* Align to at least UNIT size. */
21328 if (flags
& SECTION_CODE
)
21329 align
= MIN_UNITS_PER_WORD
;
21331 /* Increase alignment of large objects if not already stricter. */
21332 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
21333 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
21334 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
21336 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
21339 /* Output at beginning of assembler file.
21341 Initialize the section names for the RS/6000 at this point.
21343 Specify filename, including full path, to assembler.
21345 We want to go into the TOC section so at least one .toc will be emitted.
21346 Also, in order to output proper .bs/.es pairs, we need at least one static
21347 [RW] section emitted.
21349 Finally, declare mcount when profiling to make the assembler happy. */
21352 rs6000_xcoff_file_start (void)
21354 rs6000_gen_section_name (&xcoff_bss_section_name
,
21355 main_input_filename
, ".bss_");
21356 rs6000_gen_section_name (&xcoff_private_data_section_name
,
21357 main_input_filename
, ".rw_");
21358 rs6000_gen_section_name (&xcoff_read_only_section_name
,
21359 main_input_filename
, ".ro_");
21361 fputs ("\t.file\t", asm_out_file
);
21362 output_quoted_string (asm_out_file
, main_input_filename
);
21363 fputc ('\n', asm_out_file
);
21364 if (write_symbols
!= NO_DEBUG
)
21365 switch_to_section (private_data_section
);
21366 switch_to_section (text_section
);
21368 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
21369 rs6000_file_start ();
21372 /* Output at end of assembler file.
21373 On the RS/6000, referencing data should automatically pull in text. */
21376 rs6000_xcoff_file_end (void)
21378 switch_to_section (text_section
);
21379 fputs ("_section_.text:\n", asm_out_file
);
21380 switch_to_section (data_section
);
21381 fputs (TARGET_32BIT
21382 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
21385 #endif /* TARGET_XCOFF */
21387 /* Compute a (partial) cost for rtx X. Return true if the complete
21388 cost has been computed, and false if subexpressions should be
21389 scanned. In either case, *TOTAL contains the cost result. */
21392 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
21394 enum machine_mode mode
= GET_MODE (x
);
21398 /* On the RS/6000, if it is valid in the insn, it is free. */
21400 if (((outer_code
== SET
21401 || outer_code
== PLUS
21402 || outer_code
== MINUS
)
21403 && (satisfies_constraint_I (x
)
21404 || satisfies_constraint_L (x
)))
21405 || (outer_code
== AND
21406 && (satisfies_constraint_K (x
)
21408 ? satisfies_constraint_L (x
)
21409 : satisfies_constraint_J (x
))
21410 || mask_operand (x
, mode
)
21412 && mask64_operand (x
, DImode
))))
21413 || ((outer_code
== IOR
|| outer_code
== XOR
)
21414 && (satisfies_constraint_K (x
)
21416 ? satisfies_constraint_L (x
)
21417 : satisfies_constraint_J (x
))))
21418 || outer_code
== ASHIFT
21419 || outer_code
== ASHIFTRT
21420 || outer_code
== LSHIFTRT
21421 || outer_code
== ROTATE
21422 || outer_code
== ROTATERT
21423 || outer_code
== ZERO_EXTRACT
21424 || (outer_code
== MULT
21425 && satisfies_constraint_I (x
))
21426 || ((outer_code
== DIV
|| outer_code
== UDIV
21427 || outer_code
== MOD
|| outer_code
== UMOD
)
21428 && exact_log2 (INTVAL (x
)) >= 0)
21429 || (outer_code
== COMPARE
21430 && (satisfies_constraint_I (x
)
21431 || satisfies_constraint_K (x
)))
21432 || (outer_code
== EQ
21433 && (satisfies_constraint_I (x
)
21434 || satisfies_constraint_K (x
)
21436 ? satisfies_constraint_L (x
)
21437 : satisfies_constraint_J (x
))))
21438 || (outer_code
== GTU
21439 && satisfies_constraint_I (x
))
21440 || (outer_code
== LTU
21441 && satisfies_constraint_P (x
)))
21446 else if ((outer_code
== PLUS
21447 && reg_or_add_cint_operand (x
, VOIDmode
))
21448 || (outer_code
== MINUS
21449 && reg_or_sub_cint_operand (x
, VOIDmode
))
21450 || ((outer_code
== SET
21451 || outer_code
== IOR
21452 || outer_code
== XOR
)
21454 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
21456 *total
= COSTS_N_INSNS (1);
21462 if (mode
== DImode
&& code
== CONST_DOUBLE
)
21464 if ((outer_code
== IOR
|| outer_code
== XOR
)
21465 && CONST_DOUBLE_HIGH (x
) == 0
21466 && (CONST_DOUBLE_LOW (x
)
21467 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
21472 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
21473 || ((outer_code
== SET
21474 || outer_code
== IOR
21475 || outer_code
== XOR
)
21476 && CONST_DOUBLE_HIGH (x
) == 0))
21478 *total
= COSTS_N_INSNS (1);
21488 /* When optimizing for size, MEM should be slightly more expensive
21489 than generating address, e.g., (plus (reg) (const)).
21490 L1 cache latency is about two instructions. */
21491 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
21499 if (mode
== DFmode
)
21501 if (GET_CODE (XEXP (x
, 0)) == MULT
)
21503 /* FNMA accounted in outer NEG. */
21504 if (outer_code
== NEG
)
21505 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21507 *total
= rs6000_cost
->dmul
;
21510 *total
= rs6000_cost
->fp
;
21512 else if (mode
== SFmode
)
21514 /* FNMA accounted in outer NEG. */
21515 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21518 *total
= rs6000_cost
->fp
;
21521 *total
= COSTS_N_INSNS (1);
21525 if (mode
== DFmode
)
21527 if (GET_CODE (XEXP (x
, 0)) == MULT
21528 || GET_CODE (XEXP (x
, 1)) == MULT
)
21530 /* FNMA accounted in outer NEG. */
21531 if (outer_code
== NEG
)
21532 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21534 *total
= rs6000_cost
->dmul
;
21537 *total
= rs6000_cost
->fp
;
21539 else if (mode
== SFmode
)
21541 /* FNMA accounted in outer NEG. */
21542 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21545 *total
= rs6000_cost
->fp
;
21548 *total
= COSTS_N_INSNS (1);
21552 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21553 && satisfies_constraint_I (XEXP (x
, 1)))
21555 if (INTVAL (XEXP (x
, 1)) >= -256
21556 && INTVAL (XEXP (x
, 1)) <= 255)
21557 *total
= rs6000_cost
->mulsi_const9
;
21559 *total
= rs6000_cost
->mulsi_const
;
21561 /* FMA accounted in outer PLUS/MINUS. */
21562 else if ((mode
== DFmode
|| mode
== SFmode
)
21563 && (outer_code
== PLUS
|| outer_code
== MINUS
))
21565 else if (mode
== DFmode
)
21566 *total
= rs6000_cost
->dmul
;
21567 else if (mode
== SFmode
)
21568 *total
= rs6000_cost
->fp
;
21569 else if (mode
== DImode
)
21570 *total
= rs6000_cost
->muldi
;
21572 *total
= rs6000_cost
->mulsi
;
21577 if (FLOAT_MODE_P (mode
))
21579 *total
= mode
== DFmode
? rs6000_cost
->ddiv
21580 : rs6000_cost
->sdiv
;
21587 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21588 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
21590 if (code
== DIV
|| code
== MOD
)
21592 *total
= COSTS_N_INSNS (2);
21595 *total
= COSTS_N_INSNS (1);
21599 if (GET_MODE (XEXP (x
, 1)) == DImode
)
21600 *total
= rs6000_cost
->divdi
;
21602 *total
= rs6000_cost
->divsi
;
21604 /* Add in shift and subtract for MOD. */
21605 if (code
== MOD
|| code
== UMOD
)
21606 *total
+= COSTS_N_INSNS (2);
21611 *total
= COSTS_N_INSNS (4);
21615 *total
= COSTS_N_INSNS (6);
21619 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
21631 *total
= COSTS_N_INSNS (1);
21639 /* Handle mul_highpart. */
21640 if (outer_code
== TRUNCATE
21641 && GET_CODE (XEXP (x
, 0)) == MULT
)
21643 if (mode
== DImode
)
21644 *total
= rs6000_cost
->muldi
;
21646 *total
= rs6000_cost
->mulsi
;
21649 else if (outer_code
== AND
)
21652 *total
= COSTS_N_INSNS (1);
21657 if (GET_CODE (XEXP (x
, 0)) == MEM
)
21660 *total
= COSTS_N_INSNS (1);
21666 if (!FLOAT_MODE_P (mode
))
21668 *total
= COSTS_N_INSNS (1);
21674 case UNSIGNED_FLOAT
:
21677 case FLOAT_TRUNCATE
:
21678 *total
= rs6000_cost
->fp
;
21682 if (mode
== DFmode
)
21685 *total
= rs6000_cost
->fp
;
21689 switch (XINT (x
, 1))
21692 *total
= rs6000_cost
->fp
;
21704 *total
= COSTS_N_INSNS (1);
21707 else if (FLOAT_MODE_P (mode
)
21708 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21710 *total
= rs6000_cost
->fp
;
21718 /* Carry bit requires mode == Pmode.
21719 NEG or PLUS already counted so only add one. */
21721 && (outer_code
== NEG
|| outer_code
== PLUS
))
21723 *total
= COSTS_N_INSNS (1);
21726 if (outer_code
== SET
)
21728 if (XEXP (x
, 1) == const0_rtx
)
21730 *total
= COSTS_N_INSNS (2);
21733 else if (mode
== Pmode
)
21735 *total
= COSTS_N_INSNS (3);
21744 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
21746 *total
= COSTS_N_INSNS (2);
21750 if (outer_code
== COMPARE
)
21764 /* A C expression returning the cost of moving data from a register of class
21765 CLASS1 to one of CLASS2. */
21768 rs6000_register_move_cost (enum machine_mode mode
,
21769 enum reg_class from
, enum reg_class to
)
21771 /* Moves from/to GENERAL_REGS. */
21772 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
21773 || reg_classes_intersect_p (from
, GENERAL_REGS
))
21775 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
21778 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
21779 return (rs6000_memory_move_cost (mode
, from
, 0)
21780 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
21782 /* It's more expensive to move CR_REGS than CR0_REGS because of the
21784 else if (from
== CR_REGS
)
21787 /* Power6 has slower LR/CTR moves so make them more expensive than
21788 memory in order to bias spills to memory .*/
21789 else if (rs6000_cpu
== PROCESSOR_POWER6
21790 && reg_classes_intersect_p (from
, LINK_OR_CTR_REGS
))
21791 return 6 * hard_regno_nregs
[0][mode
];
21794 /* A move will cost one instruction per GPR moved. */
21795 return 2 * hard_regno_nregs
[0][mode
];
21798 /* Moving between two similar registers is just one instruction. */
21799 else if (reg_classes_intersect_p (to
, from
))
21800 return (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
21802 /* Everything else has to go through GENERAL_REGS. */
21804 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
21805 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
21808 /* A C expressions returning the cost of moving data of MODE from a register to
21812 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
21813 int in ATTRIBUTE_UNUSED
)
21815 if (reg_classes_intersect_p (class, GENERAL_REGS
))
21816 return 4 * hard_regno_nregs
[0][mode
];
21817 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
21818 return 4 * hard_regno_nregs
[32][mode
];
21819 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
21820 return 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
21822 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
21825 /* Returns a code for a target-specific builtin that implements
21826 reciprocal of the function, or NULL_TREE if not available. */
21829 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
21830 bool sqrt ATTRIBUTE_UNUSED
)
21832 if (! (TARGET_RECIP
&& TARGET_PPC_GFXOPT
&& !optimize_size
21833 && flag_finite_math_only
&& !flag_trapping_math
21834 && flag_unsafe_math_optimizations
))
21842 case BUILT_IN_SQRTF
:
21843 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
21850 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21851 Assumes no trapping math and finite arguments. */
21854 rs6000_emit_swdivsf (rtx dst
, rtx n
, rtx d
)
21856 rtx x0
, e0
, e1
, y1
, u0
, v0
, one
;
21858 x0
= gen_reg_rtx (SFmode
);
21859 e0
= gen_reg_rtx (SFmode
);
21860 e1
= gen_reg_rtx (SFmode
);
21861 y1
= gen_reg_rtx (SFmode
);
21862 u0
= gen_reg_rtx (SFmode
);
21863 v0
= gen_reg_rtx (SFmode
);
21864 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
21866 /* x0 = 1./d estimate */
21867 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21868 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, d
),
21870 /* e0 = 1. - d * x0 */
21871 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21872 gen_rtx_MINUS (SFmode
, one
,
21873 gen_rtx_MULT (SFmode
, d
, x0
))));
21874 /* e1 = e0 + e0 * e0 */
21875 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21876 gen_rtx_PLUS (SFmode
,
21877 gen_rtx_MULT (SFmode
, e0
, e0
), e0
)));
21878 /* y1 = x0 + e1 * x0 */
21879 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21880 gen_rtx_PLUS (SFmode
,
21881 gen_rtx_MULT (SFmode
, e1
, x0
), x0
)));
21883 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21884 gen_rtx_MULT (SFmode
, n
, y1
)));
21885 /* v0 = n - d * u0 */
21886 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21887 gen_rtx_MINUS (SFmode
, n
,
21888 gen_rtx_MULT (SFmode
, d
, u0
))));
21889 /* dst = u0 + v0 * y1 */
21890 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21891 gen_rtx_PLUS (SFmode
,
21892 gen_rtx_MULT (SFmode
, v0
, y1
), u0
)));
21895 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21896 Assumes no trapping math and finite arguments. */
21899 rs6000_emit_swdivdf (rtx dst
, rtx n
, rtx d
)
21901 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
21903 x0
= gen_reg_rtx (DFmode
);
21904 e0
= gen_reg_rtx (DFmode
);
21905 e1
= gen_reg_rtx (DFmode
);
21906 e2
= gen_reg_rtx (DFmode
);
21907 y1
= gen_reg_rtx (DFmode
);
21908 y2
= gen_reg_rtx (DFmode
);
21909 y3
= gen_reg_rtx (DFmode
);
21910 u0
= gen_reg_rtx (DFmode
);
21911 v0
= gen_reg_rtx (DFmode
);
21912 one
= force_reg (DFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, DFmode
));
21914 /* x0 = 1./d estimate */
21915 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21916 gen_rtx_UNSPEC (DFmode
, gen_rtvec (1, d
),
21918 /* e0 = 1. - d * x0 */
21919 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21920 gen_rtx_MINUS (DFmode
, one
,
21921 gen_rtx_MULT (SFmode
, d
, x0
))));
21922 /* y1 = x0 + e0 * x0 */
21923 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21924 gen_rtx_PLUS (DFmode
,
21925 gen_rtx_MULT (DFmode
, e0
, x0
), x0
)));
21927 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21928 gen_rtx_MULT (DFmode
, e0
, e0
)));
21929 /* y2 = y1 + e1 * y1 */
21930 emit_insn (gen_rtx_SET (VOIDmode
, y2
,
21931 gen_rtx_PLUS (DFmode
,
21932 gen_rtx_MULT (DFmode
, e1
, y1
), y1
)));
21934 emit_insn (gen_rtx_SET (VOIDmode
, e2
,
21935 gen_rtx_MULT (DFmode
, e1
, e1
)));
21936 /* y3 = y2 + e2 * y2 */
21937 emit_insn (gen_rtx_SET (VOIDmode
, y3
,
21938 gen_rtx_PLUS (DFmode
,
21939 gen_rtx_MULT (DFmode
, e2
, y2
), y2
)));
21941 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21942 gen_rtx_MULT (DFmode
, n
, y3
)));
21943 /* v0 = n - d * u0 */
21944 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21945 gen_rtx_MINUS (DFmode
, n
,
21946 gen_rtx_MULT (DFmode
, d
, u0
))));
21947 /* dst = u0 + v0 * y3 */
21948 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21949 gen_rtx_PLUS (DFmode
,
21950 gen_rtx_MULT (DFmode
, v0
, y3
), u0
)));
21954 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21955 Assumes no trapping math and finite arguments. */
21958 rs6000_emit_swrsqrtsf (rtx dst
, rtx src
)
21960 rtx x0
, x1
, x2
, y1
, u0
, u1
, u2
, v0
, v1
, v2
, t0
,
21961 half
, one
, halfthree
, c1
, cond
, label
;
21963 x0
= gen_reg_rtx (SFmode
);
21964 x1
= gen_reg_rtx (SFmode
);
21965 x2
= gen_reg_rtx (SFmode
);
21966 y1
= gen_reg_rtx (SFmode
);
21967 u0
= gen_reg_rtx (SFmode
);
21968 u1
= gen_reg_rtx (SFmode
);
21969 u2
= gen_reg_rtx (SFmode
);
21970 v0
= gen_reg_rtx (SFmode
);
21971 v1
= gen_reg_rtx (SFmode
);
21972 v2
= gen_reg_rtx (SFmode
);
21973 t0
= gen_reg_rtx (SFmode
);
21974 halfthree
= gen_reg_rtx (SFmode
);
21975 cond
= gen_rtx_REG (CCFPmode
, CR1_REGNO
);
21976 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
21978 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21979 emit_insn (gen_rtx_SET (VOIDmode
, t0
,
21980 gen_rtx_MULT (SFmode
, src
, src
)));
21982 emit_insn (gen_rtx_SET (VOIDmode
, cond
,
21983 gen_rtx_COMPARE (CCFPmode
, t0
, src
)));
21984 c1
= gen_rtx_EQ (VOIDmode
, cond
, const0_rtx
);
21985 emit_unlikely_jump (c1
, label
);
21987 half
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf
, SFmode
));
21988 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
21990 /* halfthree = 1.5 = 1.0 + 0.5 */
21991 emit_insn (gen_rtx_SET (VOIDmode
, halfthree
,
21992 gen_rtx_PLUS (SFmode
, one
, half
)));
21994 /* x0 = rsqrt estimate */
21995 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21996 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, src
),
21999 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
22000 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
22001 gen_rtx_MINUS (SFmode
,
22002 gen_rtx_MULT (SFmode
, src
, halfthree
),
22005 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
22006 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
22007 gen_rtx_MULT (SFmode
, x0
, x0
)));
22008 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
22009 gen_rtx_MINUS (SFmode
,
22011 gen_rtx_MULT (SFmode
, y1
, u0
))));
22012 emit_insn (gen_rtx_SET (VOIDmode
, x1
,
22013 gen_rtx_MULT (SFmode
, x0
, v0
)));
22015 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
22016 emit_insn (gen_rtx_SET (VOIDmode
, u1
,
22017 gen_rtx_MULT (SFmode
, x1
, x1
)));
22018 emit_insn (gen_rtx_SET (VOIDmode
, v1
,
22019 gen_rtx_MINUS (SFmode
,
22021 gen_rtx_MULT (SFmode
, y1
, u1
))));
22022 emit_insn (gen_rtx_SET (VOIDmode
, x2
,
22023 gen_rtx_MULT (SFmode
, x1
, v1
)));
22025 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
22026 emit_insn (gen_rtx_SET (VOIDmode
, u2
,
22027 gen_rtx_MULT (SFmode
, x2
, x2
)));
22028 emit_insn (gen_rtx_SET (VOIDmode
, v2
,
22029 gen_rtx_MINUS (SFmode
,
22031 gen_rtx_MULT (SFmode
, y1
, u2
))));
22032 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
22033 gen_rtx_MULT (SFmode
, x2
, v2
)));
22035 emit_label (XEXP (label
, 0));
22038 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
22039 target, and SRC is the argument operand. */
22042 rs6000_emit_popcount (rtx dst
, rtx src
)
22044 enum machine_mode mode
= GET_MODE (dst
);
22047 tmp1
= gen_reg_rtx (mode
);
22049 if (mode
== SImode
)
22051 emit_insn (gen_popcntbsi2 (tmp1
, src
));
22052 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
22054 tmp2
= force_reg (SImode
, tmp2
);
22055 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
22059 emit_insn (gen_popcntbdi2 (tmp1
, src
));
22060 tmp2
= expand_mult (DImode
, tmp1
,
22061 GEN_INT ((HOST_WIDE_INT
)
22062 0x01010101 << 32 | 0x01010101),
22064 tmp2
= force_reg (DImode
, tmp2
);
22065 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
22070 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
22071 target, and SRC is the argument operand. */
22074 rs6000_emit_parity (rtx dst
, rtx src
)
22076 enum machine_mode mode
= GET_MODE (dst
);
22079 tmp
= gen_reg_rtx (mode
);
22080 if (mode
== SImode
)
22082 /* Is mult+shift >= shift+xor+shift+xor? */
22083 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
22085 rtx tmp1
, tmp2
, tmp3
, tmp4
;
22087 tmp1
= gen_reg_rtx (SImode
);
22088 emit_insn (gen_popcntbsi2 (tmp1
, src
));
22090 tmp2
= gen_reg_rtx (SImode
);
22091 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
22092 tmp3
= gen_reg_rtx (SImode
);
22093 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
22095 tmp4
= gen_reg_rtx (SImode
);
22096 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
22097 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
22100 rs6000_emit_popcount (tmp
, src
);
22101 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
22105 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
22106 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
22108 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
22110 tmp1
= gen_reg_rtx (DImode
);
22111 emit_insn (gen_popcntbdi2 (tmp1
, src
));
22113 tmp2
= gen_reg_rtx (DImode
);
22114 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
22115 tmp3
= gen_reg_rtx (DImode
);
22116 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
22118 tmp4
= gen_reg_rtx (DImode
);
22119 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
22120 tmp5
= gen_reg_rtx (DImode
);
22121 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
22123 tmp6
= gen_reg_rtx (DImode
);
22124 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
22125 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
22128 rs6000_emit_popcount (tmp
, src
);
22129 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
22133 /* Return an RTX representing where to find the function value of a
22134 function returning MODE. */
22136 rs6000_complex_function_value (enum machine_mode mode
)
22138 unsigned int regno
;
22140 enum machine_mode inner
= GET_MODE_INNER (mode
);
22141 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
22143 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22144 regno
= FP_ARG_RETURN
;
22147 regno
= GP_ARG_RETURN
;
22149 /* 32-bit is OK since it'll go in r3/r4. */
22150 if (TARGET_32BIT
&& inner_bytes
>= 4)
22151 return gen_rtx_REG (mode
, regno
);
22154 if (inner_bytes
>= 8)
22155 return gen_rtx_REG (mode
, regno
);
22157 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
22159 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
22160 GEN_INT (inner_bytes
));
22161 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
22164 /* Define how to find the value returned by a function.
22165 VALTYPE is the data type of the value (as a tree).
22166 If the precise function being called is known, FUNC is its FUNCTION_DECL;
22167 otherwise, FUNC is 0.
22169 On the SPE, both FPs and vectors are returned in r3.
22171 On RS/6000 an integer value is in r3 and a floating-point value is in
22172 fp1, unless -msoft-float. */
22175 rs6000_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
22177 enum machine_mode mode
;
22178 unsigned int regno
;
22180 /* Special handling for structs in darwin64. */
22181 if (rs6000_darwin64_abi
22182 && TYPE_MODE (valtype
) == BLKmode
22183 && TREE_CODE (valtype
) == RECORD_TYPE
22184 && int_size_in_bytes (valtype
) > 0)
22186 CUMULATIVE_ARGS valcum
;
22190 valcum
.fregno
= FP_ARG_MIN_REG
;
22191 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
22192 /* Do a trial code generation as if this were going to be passed as
22193 an argument; if any part goes in memory, we return NULL. */
22194 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
22197 /* Otherwise fall through to standard ABI rules. */
22200 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
22202 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22203 return gen_rtx_PARALLEL (DImode
,
22205 gen_rtx_EXPR_LIST (VOIDmode
,
22206 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22208 gen_rtx_EXPR_LIST (VOIDmode
,
22209 gen_rtx_REG (SImode
,
22210 GP_ARG_RETURN
+ 1),
22213 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
22215 return gen_rtx_PARALLEL (DCmode
,
22217 gen_rtx_EXPR_LIST (VOIDmode
,
22218 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22220 gen_rtx_EXPR_LIST (VOIDmode
,
22221 gen_rtx_REG (SImode
,
22222 GP_ARG_RETURN
+ 1),
22224 gen_rtx_EXPR_LIST (VOIDmode
,
22225 gen_rtx_REG (SImode
,
22226 GP_ARG_RETURN
+ 2),
22228 gen_rtx_EXPR_LIST (VOIDmode
,
22229 gen_rtx_REG (SImode
,
22230 GP_ARG_RETURN
+ 3),
22234 mode
= TYPE_MODE (valtype
);
22235 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
22236 || POINTER_TYPE_P (valtype
))
22237 mode
= TARGET_32BIT
? SImode
: DImode
;
22239 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22240 /* _Decimal128 must use an even/odd register pair. */
22241 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
22242 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22243 regno
= FP_ARG_RETURN
;
22244 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
22245 && targetm
.calls
.split_complex_arg
)
22246 return rs6000_complex_function_value (mode
);
22247 else if (TREE_CODE (valtype
) == VECTOR_TYPE
22248 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
22249 && ALTIVEC_VECTOR_MODE (mode
))
22250 regno
= ALTIVEC_ARG_RETURN
;
22251 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
22252 && (mode
== DFmode
|| mode
== DCmode
22253 || mode
== TFmode
|| mode
== TCmode
))
22254 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
22256 regno
= GP_ARG_RETURN
;
22258 return gen_rtx_REG (mode
, regno
);
22261 /* Define how to find the value returned by a library function
22262 assuming the value has mode MODE. */
22264 rs6000_libcall_value (enum machine_mode mode
)
22266 unsigned int regno
;
22268 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
22270 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
22271 return gen_rtx_PARALLEL (DImode
,
22273 gen_rtx_EXPR_LIST (VOIDmode
,
22274 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
22276 gen_rtx_EXPR_LIST (VOIDmode
,
22277 gen_rtx_REG (SImode
,
22278 GP_ARG_RETURN
+ 1),
22282 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22283 /* _Decimal128 must use an even/odd register pair. */
22284 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
22285 else if (SCALAR_FLOAT_MODE_P (mode
)
22286 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
22287 regno
= FP_ARG_RETURN
;
22288 else if (ALTIVEC_VECTOR_MODE (mode
)
22289 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
22290 regno
= ALTIVEC_ARG_RETURN
;
22291 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
22292 return rs6000_complex_function_value (mode
);
22293 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
22294 && (mode
== DFmode
|| mode
== DCmode
22295 || mode
== TFmode
|| mode
== TCmode
))
22296 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
22298 regno
= GP_ARG_RETURN
;
22300 return gen_rtx_REG (mode
, regno
);
22303 /* Define the offset between two registers, FROM to be eliminated and its
22304 replacement TO, at the start of a routine. */
22306 rs6000_initial_elimination_offset (int from
, int to
)
22308 rs6000_stack_t
*info
= rs6000_stack_info ();
22309 HOST_WIDE_INT offset
;
22311 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22312 offset
= info
->push_p
? 0 : -info
->total_size
;
22313 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22315 offset
= info
->push_p
? 0 : -info
->total_size
;
22316 if (FRAME_GROWS_DOWNWARD
)
22317 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
22319 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
22320 offset
= FRAME_GROWS_DOWNWARD
22321 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
22323 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
22324 offset
= info
->total_size
;
22325 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
22326 offset
= info
->push_p
? info
->total_size
: 0;
22327 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
22330 gcc_unreachable ();
22335 /* Return true if TYPE is a SPE or AltiVec opaque type. */
22338 rs6000_is_opaque_type (const_tree type
)
22340 return (type
== opaque_V2SI_type_node
22341 || type
== opaque_V2SF_type_node
22342 || type
== opaque_V4SI_type_node
);
22346 rs6000_dwarf_register_span (rtx reg
)
22351 && (SPE_VECTOR_MODE (GET_MODE (reg
))
22352 || (TARGET_E500_DOUBLE
22353 && (GET_MODE (reg
) == DFmode
|| GET_MODE (reg
) == DDmode
))))
22358 regno
= REGNO (reg
);
22360 /* The duality of the SPE register size wreaks all kinds of havoc.
22361 This is a way of distinguishing r0 in 32-bits from r0 in
22364 gen_rtx_PARALLEL (VOIDmode
,
22367 gen_rtx_REG (SImode
, regno
+ 1200),
22368 gen_rtx_REG (SImode
, regno
))
22370 gen_rtx_REG (SImode
, regno
),
22371 gen_rtx_REG (SImode
, regno
+ 1200)));
22374 /* Fill in sizes for SPE register high parts in table used by unwinder. */
22377 rs6000_init_dwarf_reg_sizes_extra (tree address
)
22382 enum machine_mode mode
= TYPE_MODE (char_type_node
);
22383 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, 0);
22384 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
22385 rtx value
= gen_int_mode (4, mode
);
22387 for (i
= 1201; i
< 1232; i
++)
22389 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
22390 HOST_WIDE_INT offset
22391 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
22393 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
22398 /* Map internal gcc register numbers to DWARF2 register numbers. */
22401 rs6000_dbx_register_number (unsigned int regno
)
22403 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
22405 if (regno
== MQ_REGNO
)
22407 if (regno
== LR_REGNO
)
22409 if (regno
== CTR_REGNO
)
22411 if (CR_REGNO_P (regno
))
22412 return regno
- CR0_REGNO
+ 86;
22413 if (regno
== XER_REGNO
)
22415 if (ALTIVEC_REGNO_P (regno
))
22416 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
22417 if (regno
== VRSAVE_REGNO
)
22419 if (regno
== VSCR_REGNO
)
22421 if (regno
== SPE_ACC_REGNO
)
22423 if (regno
== SPEFSCR_REGNO
)
22425 /* SPE high reg number. We get these values of regno from
22426 rs6000_dwarf_register_span. */
22427 gcc_assert (regno
>= 1200 && regno
< 1232);
22431 /* target hook eh_return_filter_mode */
22432 static enum machine_mode
22433 rs6000_eh_return_filter_mode (void)
22435 return TARGET_32BIT
? SImode
: word_mode
;
22438 /* Target hook for scalar_mode_supported_p. */
22440 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
22442 if (DECIMAL_FLOAT_MODE_P (mode
))
22445 return default_scalar_mode_supported_p (mode
);
22448 /* Target hook for vector_mode_supported_p. */
22450 rs6000_vector_mode_supported_p (enum machine_mode mode
)
22453 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
22456 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
22459 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
22466 /* Target hook for invalid_arg_for_unprototyped_fn. */
22467 static const char *
22468 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
22470 return (!rs6000_darwin64_abi
22472 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
22473 && (funcdecl
== NULL_TREE
22474 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
22475 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
22476 ? N_("AltiVec argument passed to unprototyped function")
22480 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
22481 setup by using __stack_chk_fail_local hidden function instead of
22482 calling __stack_chk_fail directly. Otherwise it is better to call
22483 __stack_chk_fail directly. */
22486 rs6000_stack_protect_fail (void)
22488 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
22489 ? default_hidden_stack_protect_fail ()
22490 : default_external_stack_protect_fail ();
22493 #include "gt-rs6000.h"