1 ; Options for the IA-32 and AMD64 ports of the compiler.
3 ; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
21 ;; Definitions to add to the cl_target_option structure
36 unsigned char branch_cost
38 ;; which flags were passed by the user
40 int ix86_isa_flags_explicit
42 ;; which flags were passed by the user
44 int target_flags_explicit
46 ;; whether -mtune was not specified
48 unsigned char tune_defaulted
50 ;; whether -march was specified
52 unsigned char arch_specified
56 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
57 sizeof(long double) is 16
60 Target Report Mask(80387) Save
64 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
65 sizeof(long double) is 12
67 maccumulate-outgoing-args
68 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
69 Reserve space for outgoing arguments in the function prologue
72 Target Report Mask(ALIGN_DOUBLE) Save
73 Align some doubles on dword boundary
76 Target RejectNegative Joined Var(ix86_align_funcs_string)
77 Function starts are aligned to this power of 2
80 Target RejectNegative Joined Var(ix86_align_jumps_string)
81 Jump targets are aligned to this power of 2
84 Target RejectNegative Joined Var(ix86_align_loops_string)
85 Loop code aligned to this power of 2
88 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
89 Align destination of the string operations
92 Target RejectNegative Joined Var(ix86_arch_string)
93 Generate code for given CPU
96 Target RejectNegative Joined Var(ix86_asm_string)
97 Use given assembler dialect
100 Target RejectNegative Joined Var(ix86_branch_cost_string)
101 Branches are this expensive (1-5, arbitrary units)
103 mlarge-data-threshold=
104 Target RejectNegative Joined Var(ix86_section_threshold_string)
105 Data greater than given threshold will go into .ldata section in x86-64 medium model
108 Target RejectNegative Joined Var(ix86_cmodel_string)
109 Use given x86-64 code model
112 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
113 Generate sin, cos, sqrt for FPU
116 Target Report Mask(FLOAT_RETURNS) Save
117 Return values of functions in FPU registers
120 Target RejectNegative Joined Var(ix86_fpmath_string)
121 Generate floating point mathematics using given instruction set
124 Target RejectNegative Mask(80387) MaskExists Save
128 Target Report Mask(IEEE_FP) Save
129 Use IEEE math for fp comparisons
131 minline-all-stringops
132 Target Report Mask(INLINE_ALL_STRINGOPS) Save
133 Inline all known string operations
135 minline-stringops-dynamically
136 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
137 Inline memset/memcpy string operations, but perform inline version only for small blocks
144 Target Report Mask(MS_BITFIELD_LAYOUT) Save
145 Use native (MS) bitfield layout
148 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
151 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
154 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
157 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
159 momit-leaf-frame-pointer
160 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
161 Omit the frame pointer in leaf functions
164 Target RejectNegative Report Joined Var(ix87_precision_string)
165 Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80)
167 mpreferred-stack-boundary=
168 Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string)
169 Attempt to keep stack aligned to this power of 2
172 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
173 Use push instructions to save outgoing arguments
176 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
177 Use red-zone in the x86-64 code
180 Target RejectNegative Joined Var(ix86_regparm_string)
181 Number of registers used to pass integer arguments
184 Target Report Mask(RTD) Save
185 Alternate calling convention
188 Target InverseMask(80387) Save
189 Do not use hardware fp
192 Target RejectNegative Mask(SSEREGPARM) Save
193 Use SSE register passing conventions for SF and DF mode
196 Target Report Var(ix86_force_align_arg_pointer)
197 Realign stack in prologue
200 Target Report Mask(STACK_PROBE) Save
204 Target RejectNegative Joined Var(ix86_stringop_string)
205 Chose strategy to generate stringop using
208 Target RejectNegative Joined Var(ix86_tls_dialect_string)
209 Use given thread-local storage dialect
212 Target Report Mask(TLS_DIRECT_SEG_REFS)
213 Use direct references against %gs when accessing tls data
216 Target RejectNegative Joined Var(ix86_tune_string)
217 Schedule code for given CPU
220 Target RejectNegative Joined Var(ix86_veclibabi_string)
221 Vector library ABI to use
224 Target Report Mask(RECIP) Save
225 Generate reciprocals instead of divss and sqrtss.
228 Target Report Mask(CLD) Save
229 Generate cld instruction in the function prologue.
232 Target RejectNegative Report Mask(NO_FUSED_MADD) Undocumented Save
235 Target Report InverseMask(NO_FUSED_MADD, FUSED_MADD) Save
236 Enable automatic generation of fused floating point multiply-add instructions
237 if the ISA supports such instructions. The -mfused-madd option is on by
243 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
244 Generate 32bit i386 code
247 Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
248 Generate 64bit x86-64 code
251 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Save
252 Support MMX built-in functions
255 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Save
256 Support 3DNow! built-in functions
259 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Save
260 Support Athlon 3Dnow! built-in functions
263 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Save
264 Support MMX and SSE built-in functions and code generation
267 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Save
268 Support MMX, SSE and SSE2 built-in functions and code generation
271 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Save
272 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
275 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Save
276 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
279 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Save
280 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
283 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Save
284 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
287 Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Save
288 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
291 Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Save
292 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
295 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
296 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
299 Target Report Mask(ISA_SSE5) Var(ix86_isa_flags) VarExists Save
300 Support SSE5 built-in functions and code generation
303 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
304 Support code generation of Advanced Bit Manipulation (ABM) instructions.
307 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save
308 Support code generation of popcnt instruction.
311 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) VarExists Save
312 Support code generation of cmpxchg16b instruction.
315 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save
316 Support code generation of sahf instruction in 64bit x86-64 code.
319 Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
320 Support AES built-in functions and code generation
323 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save
324 Support PCLMUL built-in functions and code generation