| blob | 62d1b8d9bce6815a02a195e0de1d8f42b288c53d |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
62 #endif
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
70 : 4)
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
78 static const
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
106 in SFmode, DFmode and XFmode */
108 in SFmode, DFmode and XFmode */
111 in SImode and DImode */
113 in SImode and DImode */
116 in SImode, DImode and TImode */
118 in SImode, DImode and TImode */
146 };
148 /* Processor costs (relative to an add) */
149 static const
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
177 in SFmode, DFmode and XFmode */
179 in SFmode, DFmode and XFmode */
182 in SImode and DImode */
184 in SImode and DImode */
187 in SImode, DImode and TImode */
189 in SImode, DImode and TImode */
203 DUMMY_STRINGOP_ALGS},
205 DUMMY_STRINGOP_ALGS},
217 };
219 static const
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
247 in SFmode, DFmode and XFmode */
249 in SFmode, DFmode and XFmode */
252 in SImode and DImode */
254 in SImode and DImode */
257 in SImode, DImode and TImode */
259 in SImode, DImode and TImode */
262 shared for code and data, so 4kB is
263 not really precise. */
275 DUMMY_STRINGOP_ALGS},
277 DUMMY_STRINGOP_ALGS},
289 };
291 static const
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
319 in SFmode, DFmode and XFmode */
321 in SFmode, DFmode and XFmode */
324 in SImode and DImode */
326 in SImode and DImode */
329 in SImode, DImode and TImode */
331 in SImode, DImode and TImode */
345 DUMMY_STRINGOP_ALGS},
347 DUMMY_STRINGOP_ALGS},
359 };
361 static const
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
389 in SFmode, DFmode and XFmode */
391 in SFmode, DFmode and XFmode */
394 in SImode and DImode */
396 in SImode and DImode */
399 in SImode, DImode and TImode */
401 in SImode, DImode and TImode */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
418 */
421 DUMMY_STRINGOP_ALGS},
424 DUMMY_STRINGOP_ALGS},
436 };
438 static const
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
466 in SFmode, DFmode and XFmode */
468 in SFmode, DFmode and XFmode */
472 in SImode and DImode */
474 in SImode and DImode */
477 in SImode, DImode and TImode */
479 in SImode, DImode and TImode */
493 DUMMY_STRINGOP_ALGS},
495 DUMMY_STRINGOP_ALGS},
507 };
509 static const
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
537 in SFmode, DFmode and XFmode */
539 in SFmode, DFmode and XFmode */
542 in SImode and DImode */
544 in SImode and DImode */
547 in SImode, DImode and TImode */
549 in SImode, DImode and TImode */
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
566 DUMMY_STRINGOP_ALGS},
568 DUMMY_STRINGOP_ALGS},
580 };
582 static const
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
610 in SFmode, DFmode and XFmode */
612 in SFmode, DFmode and XFmode */
615 in SImode and DImode */
617 in SImode and DImode */
620 in SImode, DImode and TImode */
622 in SImode, DImode and TImode */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
639 DUMMY_STRINGOP_ALGS},
641 DUMMY_STRINGOP_ALGS},
653 };
655 static const
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
683 in SFmode, DFmode and XFmode */
685 in SFmode, DFmode and XFmode */
688 in SImode and DImode */
690 in SImode and DImode */
693 in SImode, DImode and TImode */
695 in SImode, DImode and TImode */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
704 time). */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
732 };
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
761 in SFmode, DFmode and XFmode */
763 in SFmode, DFmode and XFmode */
766 in SImode and DImode */
768 in SImode and DImode */
771 in SImode, DImode and TImode */
773 in SImode, DImode and TImode */
775 /* On K8
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
778 On AMDFAM10
779 MOVD reg64, xmmreg Double FADD 3
780 1/1 1/1
781 MOVD reg32, xmmreg Double FADD 3
782 1/1 1/1 */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
790 time). */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
819 };
821 static const
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
849 in SFmode, DFmode and XFmode */
851 in SFmode, DFmode and XFmode */
854 in SImode and DImode */
856 in SImode and DImode */
859 in SImode, DImode and TImode */
861 in SImode, DImode and TImode */
875 DUMMY_STRINGOP_ALGS},
878 DUMMY_STRINGOP_ALGS},
890 };
892 static const
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
920 in SFmode, DFmode and XFmode */
922 in SFmode, DFmode and XFmode */
925 in SImode and DImode */
927 in SImode and DImode */
930 in SImode, DImode and TImode */
932 in SImode, DImode and TImode */
963 };
965 static const
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
993 in SFmode, DFmode and XFmode */
997 in SImode and DImode */
999 in SImode and DImode */
1002 in SImode, DImode and TImode */
1004 in SImode, DImode and TImode */
1035 };
1037 /* Generic64 should produce code tuned for Nocona and K8. */
1038 static const
1041 /* On all chips taken into consideration lea is 2 cycles and more. With
1042 this cost however our current implementation of synth_mult results in
1043 use of unnecessary temporary registers causing regression on several
1044 SPECfp benchmarks. */
1065 in QImode, HImode and SImode.
1066 Relative to reg-reg move (2). */
1070 in SFmode, DFmode and XFmode */
1072 in SFmode, DFmode and XFmode */
1075 in SImode and DImode */
1077 in SImode and DImode */
1080 in SImode, DImode and TImode */
1082 in SImode, DImode and TImode */
1088 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1089 is increased to perhaps more appropriate value of 5. */
1112 };
1114 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1115 static const
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1143 in SFmode, DFmode and XFmode */
1145 in SFmode, DFmode and XFmode */
1148 in SImode and DImode */
1150 in SImode and DImode */
1153 in SImode, DImode and TImode */
1155 in SImode, DImode and TImode */
1169 DUMMY_STRINGOP_ALGS},
1171 DUMMY_STRINGOP_ALGS},
1183 };
1187 /* Processor feature/optimization bitmasks. */
1188 #define m_386 (1<<PROCESSOR_I386)
1189 #define m_486 (1<<PROCESSOR_I486)
1190 #define m_PENT (1<<PROCESSOR_PENTIUM)
1191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1192 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1193 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1194 #define m_CORE2 (1<<PROCESSOR_CORE2)
1196 #define m_GEODE (1<<PROCESSOR_GEODE)
1197 #define m_K6 (1<<PROCESSOR_K6)
1198 #define m_K6_GEODE (m_K6 | m_GEODE)
1199 #define m_K8 (1<<PROCESSOR_K8)
1200 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1201 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1202 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1203 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1205 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1206 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1208 /* Generic instruction choice should be common subset of supported CPUs
1209 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1210 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1212 /* Feature tests against the various tunings. */
1215 /* Feature tests against the various tunings used to create ix86_tune_features
1216 based on the processor mask. */
1218 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1219 negatively, so enabling for Generic64 seems like good code size
1220 tradeoff. We can't enable it for 32bit generic because it does not
1221 work well with PPro base chips. */
1224 /* X86_TUNE_PUSH_MEMORY */
1228 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1231 /* X86_TUNE_USE_BIT_TEST */
1232 m_386,
1234 /* X86_TUNE_UNROLL_STRLEN */
1237 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1240 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1241 on simulation result. But after P4 was made, no performance benefit
1242 was observed with branch hints. It also increases the code size.
1243 As a result, icc never generates branch hints. */
1246 /* X86_TUNE_DOUBLE_WITH_ADD */
1249 /* X86_TUNE_USE_SAHF */
1253 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1254 partial dependencies. */
1258 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1259 register stalls on Generic32 compilation setting as well. However
1260 in current implementation the partial register stalls are not eliminated
1261 very well - they can be introduced via subregs synthesized by combine
1262 and can happen in caller/callee saving sequences. Because this option
1263 pays back little on PPro based chips and is in conflict with partial reg
1264 dependencies used by Athlon/P4 based chips, it is better to leave it off
1265 for generic32 for now. */
1266 m_PPRO,
1268 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1271 /* X86_TUNE_USE_HIMODE_FIOP */
1274 /* X86_TUNE_USE_SIMODE_FIOP */
1277 /* X86_TUNE_USE_MOV0 */
1278 m_K6,
1280 /* X86_TUNE_USE_CLTD */
1283 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1284 m_PENT4,
1286 /* X86_TUNE_SPLIT_LONG_MOVES */
1287 m_PPRO,
1289 /* X86_TUNE_READ_MODIFY_WRITE */
1292 /* X86_TUNE_READ_MODIFY */
1295 /* X86_TUNE_PROMOTE_QIMODE */
1299 /* X86_TUNE_FAST_PREFIX */
1302 /* X86_TUNE_SINGLE_STRINGOP */
1305 /* X86_TUNE_QIMODE_MATH */
1308 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1309 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1310 might be considered for Generic32 if our scheme for avoiding partial
1311 stalls was more effective. */
1314 /* X86_TUNE_PROMOTE_QI_REGS */
1317 /* X86_TUNE_PROMOTE_HI_REGS */
1318 m_PPRO,
1320 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1323 /* X86_TUNE_ADD_ESP_8 */
1327 /* X86_TUNE_SUB_ESP_4 */
1330 /* X86_TUNE_SUB_ESP_8 */
1334 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1335 for DFmode copies */
1339 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1342 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1343 conflict here in between PPro/Pentium4 based chips that thread 128bit
1344 SSE registers as single units versus K8 based chips that divide SSE
1345 registers to two 64bit halves. This knob promotes all store destinations
1346 to be 128bit to allow register renaming on 128bit SSE units, but usually
1347 results in one extra microop on 64bit SSE units. Experimental results
1348 shows that disabling this option on P4 brings over 20% SPECfp regression,
1349 while enabling it on K8 brings roughly 2.4% regression that can be partly
1350 masked by careful scheduling of moves. */
1353 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1354 m_AMDFAM10,
1356 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1357 are resolved on SSE register parts instead of whole registers, so we may
1358 maintain just lower part of scalar values in proper format leaving the
1359 upper part undefined. */
1360 m_ATHLON_K8,
1362 /* X86_TUNE_SSE_TYPELESS_STORES */
1363 m_AMD_MULTIPLE,
1365 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1368 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1371 /* X86_TUNE_PROLOGUE_USING_MOVE */
1374 /* X86_TUNE_EPILOGUE_USING_MOVE */
1377 /* X86_TUNE_SHIFT1 */
1380 /* X86_TUNE_USE_FFREEP */
1381 m_AMD_MULTIPLE,
1383 /* X86_TUNE_INTER_UNIT_MOVES */
1386 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1389 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1390 than 4 branch instructions in the 16 byte window. */
1393 /* X86_TUNE_SCHEDULE */
1396 /* X86_TUNE_USE_BT */
1399 /* X86_TUNE_USE_INCDEC */
1402 /* X86_TUNE_PAD_RETURNS */
1405 /* X86_TUNE_EXT_80387_CONSTANTS */
1408 /* X86_TUNE_SHORTEN_X87_SSE */
1411 /* X86_TUNE_AVOID_VECTOR_DECODE */
1414 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1415 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1418 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1419 vector path on AMD machines. */
1422 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 machines. */
1426 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1427 than a MOV. */
1428 m_PENT,
1430 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1431 but one byte longer. */
1432 m_PENT,
1434 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1435 operand that cannot be represented using a modRM byte. The XOR
1436 replacement is long decoded, so this split helps here as well. */
1437 m_K6,
1439 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1440 from integer to FP. */
1441 m_AMDFAM10,
1443 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1444 with a subsequent conditional jump instruction into a single
1445 compare-and-branch uop. */
1446 m_CORE2,
1447 };
1449 /* Feature tests against the various architecture variations. */
1452 /* Feature tests against the various architecture variations, used to create
1453 ix86_arch_features based on the processor mask. */
1455 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1458 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1461 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1464 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1467 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1469 };
1471 static const unsigned int x86_accumulate_outgoing_args
1474 static const unsigned int x86_arch_always_fancy_math_387
1480 /* In case the average insn count for single function invocation is
1481 lower than this constant, emit fast (but longer) prologue and
1482 epilogue code. */
1483 #define FAST_PROLOGUE_INSN_COUNT 20
1485 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1490 /* Array of the smallest class containing reg number REGNO, indexed by
1491 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1494 {
1495 /* ax, dx, cx, bx */
1497 /* si, di, bp, sp */
1499 /* FP registers */
1502 /* arg pointer */
1503 NON_Q_REGS,
1504 /* flags, fpsr, fpcr, frame */
1506 /* SSE registers */
1509 /* MMX registers */
1512 /* REX registers */
1515 /* SSE REX registers */
1518 };
1520 /* The "default" register map used in 32bit mode. */
1523 {
1531 };
1534 {
1537 };
1540 {
1543 };
1546 {
1548 };
1550 /* The "default" register map used in 64bit mode. */
1552 {
1560 };
1562 /* Define the register numbers to be used in Dwarf debugging information.
1563 The SVR4 reference port C compiler uses the following register numbers
1564 in its Dwarf output code:
1565 0 for %eax (gcc regno = 0)
1566 1 for %ecx (gcc regno = 2)
1567 2 for %edx (gcc regno = 1)
1568 3 for %ebx (gcc regno = 3)
1569 4 for %esp (gcc regno = 7)
1570 5 for %ebp (gcc regno = 6)
1571 6 for %esi (gcc regno = 4)
1572 7 for %edi (gcc regno = 5)
1573 The following three DWARF register numbers are never generated by
1574 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1575 believes these numbers have these meanings.
1576 8 for %eip (no gcc equivalent)
1577 9 for %eflags (gcc regno = 17)
1578 10 for %trapno (no gcc equivalent)
1579 It is not at all clear how we should number the FP stack registers
1580 for the x86 architecture. If the version of SDB on x86/svr4 were
1581 a bit less brain dead with respect to floating-point then we would
1582 have a precedent to follow with respect to DWARF register numbers
1583 for x86 FP registers, but the SDB on x86/svr4 is so completely
1584 broken with respect to FP registers that it is hardly worth thinking
1585 of it as something to strive for compatibility with.
1586 The version of x86/svr4 SDB I have at the moment does (partially)
1587 seem to believe that DWARF register number 11 is associated with
1588 the x86 register %st(0), but that's about all. Higher DWARF
1589 register numbers don't seem to be associated with anything in
1590 particular, and even for DWARF regno 11, SDB only seems to under-
1591 stand that it should say that a variable lives in %st(0) (when
1592 asked via an `=' command) if we said it was in DWARF regno 11,
1593 but SDB still prints garbage when asked for the value of the
1594 variable in question (via a `/' command).
1595 (Also note that the labels SDB prints for various FP stack regs
1596 when doing an `x' command are all wrong.)
1597 Note that these problems generally don't affect the native SVR4
1598 C compiler because it doesn't allow the use of -O with -g and
1599 because when it is *not* optimizing, it allocates a memory
1600 location for each floating-point variable, and the memory
1601 location is what gets described in the DWARF AT_location
1602 attribute for the variable in question.
1603 Regardless of the severe mental illness of the x86/svr4 SDB, we
1604 do something sensible here and we use the following DWARF
1605 register numbers. Note that these are all stack-top-relative
1606 numbers.
1607 11 for %st(0) (gcc regno = 8)
1608 12 for %st(1) (gcc regno = 9)
1609 13 for %st(2) (gcc regno = 10)
1610 14 for %st(3) (gcc regno = 11)
1611 15 for %st(4) (gcc regno = 12)
1612 16 for %st(5) (gcc regno = 13)
1613 17 for %st(6) (gcc regno = 14)
1614 18 for %st(7) (gcc regno = 15)
1615 */
1617 {
1625 };
1627 /* Test and compare insns in i386.md store the information needed to
1628 generate branch and scc insns here. */
1634 /* Size of the register save area. */
1635 #define X86_64_VARARGS_SIZE (X86_64_REGPARM_MAX * UNITS_PER_WORD + X86_64_SSE_REGPARM_MAX * 16)
1637 /* Define the structure for the machine field in struct function. */
1640 {
1643 rtx rtl;
1645 };
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1650 [arguments]
1651 <- ARG_POINTER
1652 saved pc
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1656 [saved regs]
1658 [padding1] \
1659 )
1660 [va_arg registers] (
1661 > to_allocate <- FRAME_POINTER
1662 [frame] (
1663 )
1664 [padding2] /
1665 */
1666 struct ix86_frame
1667 {
1671 HOST_WIDE_INT frame;
1676 HOST_WIDE_INT to_allocate;
1677 /* The offsets relative to ARG_POINTER. */
1678 HOST_WIDE_INT frame_pointer_offset;
1679 HOST_WIDE_INT hard_frame_pointer_offset;
1680 HOST_WIDE_INT stack_pointer_offset;
1682 /* When save_regs_using_mov is set, emit prologue using
1683 move instead of push instructions. */
1685 };
1687 /* Code model option. */
1689 /* Asm dialect. */
1691 /* TLS dialects. */
1694 /* Which unit we are generating floating point math for. */
1697 /* Which cpu are we scheduling for. */
1700 /* Which instruction set architecture to use. */
1703 /* true if sse prefetch instruction is not NOOP. */
1706 /* ix86_regparm_string as a number */
1709 /* -mstackrealign option */
1721 /* Preferred alignment for stack boundary in bits. */
1724 /* Values 1-5: see jump.c */
1727 /* Calling abi specific va_list type nodes. */
1731 /* Variables which are this size or smaller are put in the data/bss
1732 or ldata/lbss sections. */
1736 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1740 /* Fence to use after loop using movnt. */
1741 tree x86_mfence;
1743 /* Register class used for passing given 64bit part of the argument.
1744 These represent classes as documented by the PS ABI, with the exception
1745 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1746 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1748 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1749 whenever possible (upper half does contain padding). */
1750 enum x86_64_reg_class
1751 {
1752 X86_64_NO_CLASS,
1753 X86_64_INTEGER_CLASS,
1754 X86_64_INTEGERSI_CLASS,
1755 X86_64_SSE_CLASS,
1756 X86_64_SSESF_CLASS,
1757 X86_64_SSEDF_CLASS,
1758 X86_64_SSEUP_CLASS,
1759 X86_64_X87_CLASS,
1760 X86_64_X87UP_CLASS,
1761 X86_64_COMPLEX_X87_CLASS,
1762 X86_64_MEMORY_CLASS
1763 };
1765 {
1768 };
1770 #define MAX_CLASSES 4
1772 /* Table of constants used by fldpi, fldln2, etc.... */
1776 \f
1784 enum ix86_function_specific_strings
1785 {
1786 IX86_FUNCTION_SPECIFIC_ARCH,
1787 IX86_FUNCTION_SPECIFIC_TUNE,
1788 IX86_FUNCTION_SPECIFIC_FPMATH,
1789 IX86_FUNCTION_SPECIFIC_MAX
1790 };
1804 \f
1805 /* The svr4 ABI for the i386 says that records and unions are returned
1806 in memory. */
1807 #ifndef DEFAULT_PCC_STRUCT_RETURN
1808 #define DEFAULT_PCC_STRUCT_RETURN 1
1809 #endif
1811 /* Whether -mtune= or -march= were specified */
1815 /* Bit flags that specify the ISA we are compiling for. */
1818 /* A mask of ix86_isa_flags that includes bit X if X
1819 was set or cleared on the command line. */
1822 /* Define a set of ISAs which are available when a given ISA is
1823 enabled. MMX and SSE ISAs are handled separately. */
1825 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1826 #define OPTION_MASK_ISA_3DNOW_SET \
1827 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1829 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1830 #define OPTION_MASK_ISA_SSE2_SET \
1831 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1832 #define OPTION_MASK_ISA_SSE3_SET \
1833 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1834 #define OPTION_MASK_ISA_SSSE3_SET \
1835 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1836 #define OPTION_MASK_ISA_SSE4_1_SET \
1837 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1838 #define OPTION_MASK_ISA_SSE4_2_SET \
1839 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1841 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1842 as -msse4.2. */
1843 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1845 #define OPTION_MASK_ISA_SSE4A_SET \
1846 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1847 #define OPTION_MASK_ISA_SSE5_SET \
1848 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1850 /* AES and PCLMUL need SSE2 because they use xmm registers */
1851 #define OPTION_MASK_ISA_AES_SET \
1852 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1853 #define OPTION_MASK_ISA_PCLMUL_SET \
1854 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1856 #define OPTION_MASK_ISA_ABM_SET \
1857 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1858 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1859 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1860 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1862 /* Define a set of ISAs which aren't available when a given ISA is
1863 disabled. MMX and SSE ISAs are handled separately. */
1865 #define OPTION_MASK_ISA_MMX_UNSET \
1866 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1867 #define OPTION_MASK_ISA_3DNOW_UNSET \
1868 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1869 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1871 #define OPTION_MASK_ISA_SSE_UNSET \
1872 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1873 #define OPTION_MASK_ISA_SSE2_UNSET \
1874 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1875 #define OPTION_MASK_ISA_SSE3_UNSET \
1876 (OPTION_MASK_ISA_SSE3 \
1877 | OPTION_MASK_ISA_SSSE3_UNSET \
1878 | OPTION_MASK_ISA_SSE4A_UNSET )
1879 #define OPTION_MASK_ISA_SSSE3_UNSET \
1880 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1881 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1882 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1883 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1885 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1886 as -mno-sse4.1. */
1887 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1889 #define OPTION_MASK_ISA_SSE4A_UNSET \
1890 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1891 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1892 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1893 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1894 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1895 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1896 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1897 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1899 /* Vectorization library interface and handlers. */
1904 /* Processor target table, indexed by processor number */
1905 struct ptt
1906 {
1913 };
1916 {
1931 };
1934 {
1955 "amdfam10"
1956 };
1957 \f
1958 /* Implement TARGET_HANDLE_OPTION. */
1960 static bool
1962 {
1964 {
1967 {
1970 }
1971 else
1972 {
1975 }
1980 {
1983 }
1984 else
1985 {
1988 }
1996 {
1999 }
2000 else
2001 {
2004 }
2009 {
2012 }
2013 else
2014 {
2017 }
2022 {
2025 }
2026 else
2027 {
2030 }
2035 {
2038 }
2039 else
2040 {
2043 }
2048 {
2051 }
2052 else
2053 {
2056 }
2061 {
2064 }
2065 else
2066 {
2069 }
2084 {
2087 }
2088 else
2089 {
2092 }
2097 {
2100 }
2101 else
2102 {
2105 }
2110 {
2113 }
2114 else
2115 {
2118 }
2123 {
2126 }
2127 else
2128 {
2131 }
2136 {
2139 }
2140 else
2141 {
2144 }
2149 {
2152 }
2153 else
2154 {
2157 }
2162 {
2165 }
2166 else
2167 {
2170 }
2175 {
2178 }
2179 else
2180 {
2183 }
2188 }
2189 }
2190 \f
2191 /* Return a string the documents the current -m options. The caller is
2192 responsible for freeing the string. */
2197 {
2198 struct ix86_target_opts
2199 {
2202 };
2204 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2205 preceding options while match those first. */
2207 {
2224 };
2226 /* Flag options. */
2228 {
2250 };
2268 /* Add -march= option. */
2270 {
2273 }
2275 /* Add -mtune= option. */
2277 {
2280 }
2282 /* Pick out the options in isa options. */
2284 {
2286 {
2289 }
2290 }
2293 {
2296 }
2298 /* Add flag options. */
2300 {
2302 {
2305 }
2306 }
2309 {
2312 }
2314 /* Add -fpmath= option. */
2316 {
2319 }
2321 /* Any options? */
2327 /* Size the string. */
2331 {
2336 }
2338 /* Build the string. */
2343 {
2350 {
2352 line_len++;
2355 {
2359 }
2360 }
2364 {
2368 }
2369 }
2375 }
2377 /* Function that is callable from the debugger to print the current
2378 options. */
2379 void
2381 {
2387 {
2390 }
2391 else
2395 }
2396 \f
2397 /* Sometimes certain combinations of command options do not make
2398 sense on a particular target machine. You can define a macro
2399 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2400 defined, is executed once just after all the command options have
2401 been parsed.
2403 Don't use this macro to turn on various extra optimizations for
2404 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2406 void
2408 {
2415 /* Comes from final.c -- no real reason to change it. */
2416 #define MAX_CODE_ALIGN 16
2418 enum pta_flags
2419 {
2439 };
2441 static struct pta
2442 {
2446 }
2448 {
2472 | PTA_SSSE3
2523 | PTA_SSE4A
2528 | PTA_SSE4A
2532 };
2536 /* Set up prefix/suffix so the error messages refer to either the command
2537 line argument, or the attribute(option). */
2539 {
2543 }
2544 else
2545 {
2549 }
2551 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2552 SUBTARGET_OVERRIDE_OPTIONS;
2553 #endif
2555 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2556 SUBSUBTARGET_OVERRIDE_OPTIONS;
2557 #endif
2559 /* -fPIC is the default for x86_64. */
2563 /* Set the default values for switches whose default depends on TARGET_64BIT
2564 in case they weren't overwritten by command line options. */
2566 {
2567 /* Mach-O doesn't support omitting the frame pointer for now. */
2574 }
2575 else
2576 {
2583 }
2585 /* Need to check -mtune=generic first. */
2587 {
2590 /* As special support for cross compilers we read -mtune=native
2591 as -mtune=generic. With native compilers we won't see the
2592 -mtune=native, as it was changed by the driver. */
2594 {
2597 else
2599 }
2600 /* If this call is for setting the option attribute, allow the
2601 generic32/generic64 that was previously set. */
2605 ;
2609 }
2610 else
2611 {
2615 {
2618 }
2620 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2621 need to use a sensible tune option. */
2625 {
2628 else
2630 }
2631 }
2633 {
2648 else
2651 }
2659 else
2670 {
2683 else
2686 }
2687 else
2688 {
2689 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2690 use of rip-relative addressing. This eliminates fixups that
2691 would otherwise be needed if this object is to be placed in a
2692 DLL, and is essentially just as efficient as direct addressing. */
2697 else
2699 }
2701 {
2707 else
2710 }
2720 {
2722 /* Default cpu tuning to the architecture. */
2784 }
2796 {
2799 {
2801 {
2808 }
2809 else
2812 }
2813 /* Intel CPUs have always interpreted SSE prefetch instructions as
2814 NOPs; so, we can enable SSE prefetch instructions even when
2815 -mtune (rather than -march) points us to a processor that has them.
2816 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2817 higher processors. */
2822 }
2833 else
2836 /* Arrange to set up i386_stack_locals for all functions. */
2839 /* Validate -mregparm= value. */
2841 {
2848 else
2850 }
2854 /* If the user has provided any of the -malign-* options,
2855 warn and use that value only if -falign-* is not set.
2856 Remove this code in GCC 3.2 or later. */
2858 {
2862 {
2867 else
2869 }
2870 }
2873 {
2877 {
2882 else
2884 }
2885 }
2888 {
2892 {
2897 else
2899 }
2900 }
2902 /* Default align_* from the processor table. */
2904 {
2907 }
2909 {
2912 }
2914 {
2916 }
2918 /* Validate -mbranch-cost= value, or provide default. */
2921 {
2925 else
2927 }
2929 {
2933 else
2935 }
2938 {
2945 else
2948 }
2951 {
2955 }
2958 {
2961 /* Enable by default the SSE and MMX builtins. Do allow the user to
2962 explicitly disable any of these. In particular, disabling SSE and
2963 MMX for kernel code is extremely useful. */
2965 ix86_isa_flags
2971 }
2972 else
2973 {
2977 ix86_isa_flags
2980 /* i386 ABI does not specify red zone. It still makes sense to use it
2981 when programmer takes care to stack from being destroyed. */
2984 }
2986 /* Keep nonleaf frame pointers. */
2992 /* If we're doing fast math, we don't care about comparison order
2993 wrt NaNs. This lets us use a shorter comparison sequence. */
2997 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2998 since the insns won't need emulation. */
3002 /* Likewise, if the target doesn't have a 387, or we've specified
3003 software floating point, don't use 387 inline intrinsics. */
3007 /* Turn on MMX builtins for -msse. */
3009 {
3012 }
3014 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3018 /* Validate -mpreferred-stack-boundary= value, or provide default.
3019 The default of 128 bits is for Pentium III's SSE __m128. We can't
3020 change it because of optimize_size. Otherwise, we can't mix object
3021 files compiled with -Os and -On. */
3024 {
3029 else
3031 }
3033 /* Accept -msseregparm only if at least SSE support is enabled. */
3040 {
3044 {
3046 {
3049 }
3050 else
3052 }
3058 {
3060 {
3063 }
3065 {
3068 }
3069 else
3071 }
3072 else
3075 }
3077 /* If the i387 is disabled, then do not return values in it. */
3081 /* Use external vectorized library in vectorizing intrinsics. */
3083 {
3088 else
3092 }
3099 /* ??? Unwind info is not correct around the CFG unless either a frame
3100 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3101 unwind info generation to be aware of the CFG and propagating states
3102 around edges. */
3105 && flag_omit_frame_pointer
3107 {
3113 }
3115 /* If stack probes are required, the space used for large function
3116 arguments on the stack must also be probed, so enable
3117 -maccumulate-outgoing-args so this happens in the prologue. */
3120 {
3125 }
3127 /* For sane SSE instruction set generation we need fcomi instruction.
3128 It is safe to enable all CMOVE instructions. */
3132 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3133 {
3139 }
3151 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3152 can be optimized to ap = __builtin_next_arg (0). */
3157 {
3165 }
3166 else
3167 {
3175 }
3177 #ifdef USE_IX86_CLD
3178 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3181 #endif
3183 /* Save the initial options in case the user does function specific options */
3185 target_option_default_node = target_option_current_node
3187 }
3188 \f
3189 /* Save the current options */
3191 static void
3193 {
3207 }
3209 /* Restore the current options */
3211 static void
3213 {
3228 /* Recreate the arch feature tests if the arch changed */
3230 {
3235 }
3237 /* Recreate the tune optimization tests */
3239 {
3244 }
3245 }
3247 /* Print the current options */
3249 static void
3252 {
3277 {
3280 }
3281 }
3283 \f
3284 /* Inner function to process the attribute((option(...))), take an argument and
3285 set the current options from the argument. If we have a list, recursively go
3286 over the list. */
3288 static bool
3290 {
3294 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3295 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3296 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3297 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3299 enum ix86_opt_type
3300 {
3301 ix86_opt_unknown,
3302 ix86_opt_yes,
3303 ix86_opt_no,
3304 ix86_opt_str,
3305 ix86_opt_isa
3306 };
3308 static const struct
3309 {
3316 /* isa options */
3333 /* string options */
3338 /* flag options */
3340 OPT_mcld,
3341 MASK_CLD),
3344 OPT_mfancy_math_387,
3345 MASK_NO_FANCY_MATH_387),
3348 OPT_mfused_madd,
3349 MASK_NO_FUSED_MADD),
3352 OPT_mieee_fp,
3353 MASK_IEEE_FP),
3356 OPT_minline_all_stringops,
3357 MASK_INLINE_ALL_STRINGOPS),
3360 OPT_minline_stringops_dynamically,
3361 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3364 OPT_mno_align_stringops,
3365 MASK_NO_ALIGN_STRINGOPS),
3368 OPT_mrecip,
3369 MASK_RECIP),
3371 };
3373 /* If this is a list, recurse to get the options. */
3375 {
3384 }
3389 /* Handle multiple arguments separated by commas. */
3393 {
3407 {
3411 }
3412 else
3413 {
3416 }
3418 /* Recognize no-xxx. */
3420 {
3424 }
3425 else
3428 /* Find the option. */
3432 {
3438 {
3443 }
3444 }
3446 /* Process the option. */
3448 {
3451 }
3457 {
3463 else
3465 }
3468 {
3470 {
3473 }
3474 else
3476 }
3478 else
3480 }
3483 }
3485 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3487 tree
3489 {
3501 /* Process each of the options on the chain. */
3505 /* If the changed options are different from the default, rerun override_options,
3506 and then save the options away. The string options are are attribute options,
3507 and will be undone when we copy the save structure. */
3513 {
3514 /* If we are using the default tune= or arch=, undo the string assigned,
3515 and use the default. */
3526 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3532 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3535 /* Save the current options unless we are validating options for
3536 #pragma. */
3543 /* Free up memory allocated to hold the strings */
3547 }
3550 }
3552 /* Hook to validate attribute((option("string"))). */
3554 static bool
3557 tree args,
3559 {
3562 tree new_opts;
3574 }
3576 \f
3577 /* Hook to determine if one function can safely inline another. */
3579 static bool
3581 {
3586 /* If callee has no option attributes, then it is ok to inline. */
3590 /* If caller has no option attributes, but callee does then it is not ok to
3591 inline. */
3595 else
3596 {
3600 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3601 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3602 function. */
3607 /* See if we have the same non-isa options. */
3611 /* See if arch, tune, etc. are the same. */
3624 else
3626 }
3629 }
3631 \f
3632 /* Remember the last target of ix86_set_current_function. */
3635 /* Establish appropriate back-end context for processing the function
3636 FNDECL. The argument might be NULL to indicate processing at top
3637 level, outside of any function scope. */
3638 static void
3640 {
3641 /* Only change the context if the function changes. This hook is called
3642 several times in the course of compiling a function, and we don't want to
3643 slow things down too much or call target_reinit when it isn't safe. */
3645 {
3646 tree old_tree = (ix86_previous_fndecl
3650 tree new_tree = (fndecl
3656 ;
3659 {
3662 }
3665 {
3671 }
3672 }
3673 }
3675 \f
3676 /* Return true if this goes in large data/bss. */
3678 static bool
3680 {
3684 /* Functions are never large data. */
3689 {
3695 }
3696 else
3697 {
3700 /* If this is an incomplete type with size 0, then we can't put it
3701 in data because it might be too big when completed. */
3704 }
3707 }
3709 /* Switch to the appropriate section for output of DECL.
3710 DECL is either a `VAR_DECL' node or a constant of some sort.
3711 RELOC indicates whether forming the initial value of DECL requires
3712 link-time relocations. */
3715 ATTRIBUTE_UNUSED;
3720 {
3723 {
3727 {
3761 /* We don't split these for medium model. Place them into
3762 default sections and hope for best. */
3767 }
3769 {
3770 /* We might get called with string constants, but get_named_section
3771 doesn't like them as they are not DECLs. Also, we need to set
3772 flags in that case. */
3776 }
3777 }
3779 }
3781 /* Build up a unique section name, expressed as a
3782 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3783 RELOC indicates whether the initial value of EXP requires
3784 link-time relocations. */
3786 static void ATTRIBUTE_UNUSED
3788 {
3791 {
3793 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3797 {
3821 /* We don't split these for medium model. Place them into
3822 default sections and hope for best. */
3830 }
3832 {
3839 /* If we're using one_only, then there needs to be a .gnu.linkonce
3840 prefix to the section name. */
3847 }
3848 }
3850 }
3852 #ifdef COMMON_ASM_OP
3853 /* This says how to output assembler code to declare an
3854 uninitialized external linkage data object.
3856 For medium model x86-64 we need to use .largecomm opcode for
3857 large objects. */
3858 void
3862 {
3866 else
3871 }
3872 #endif
3874 /* Utility function for targets to use in implementing
3875 ASM_OUTPUT_ALIGNED_BSS. */
3877 void
3881 {
3885 else
3888 #ifdef ASM_DECLARE_OBJECT_NAME
3891 #else
3892 /* Standard thing is just output label for the object. */
3896 }
3897 \f
3898 void
3900 {
3901 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
3902 make the problem with not enough registers even worse. */
3903 #ifdef INSN_SCHEDULING
3906 #endif
3908 /* When scheduling description is not available, disable scheduler pass
3909 so it won't slow down the compilation and make x87 code slower. */
3914 /* The Darwin libraries never set errno, so we might as well
3915 avoid calling them when that's the only reason we would. */
3918 /* The default values of these switches depend on the TARGET_64BIT
3919 that is not known at this moment. Mark these values with 2 and
3920 let user the to override these. In case there is no command line option
3921 specifying them, we will set the defaults in override_options. */
3927 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
3928 SUBTARGET_OPTIMIZATION_OPTIONS;
3929 #endif
3930 }
3931 \f
3932 /* Decide whether we can make a sibling call to a function. DECL is the
3933 declaration of the function being targeted by the call and EXP is the
3934 CALL_EXPR representing the call. */
3936 static bool
3938 {
3939 tree func;
3942 /* If we are generating position-independent code, we cannot sibcall
3943 optimize any indirect call, or a direct call to a global function,
3944 as the PLT requires %ebx be live. */
3950 else
3951 {
3955 }
3957 /* Check that the return value locations are the same. Like
3958 if we are returning floats on the 80387 register stack, we cannot
3959 make a sibcall from a function that doesn't return a float to a
3960 function that does or, conversely, from a function that does return
3961 a float to a function that doesn't; the necessary stack adjustment
3962 would not be executed. This is also the place we notice
3963 differences in the return value ABI. Note that it is ok for one
3964 of the functions to have void return type as long as the return
3965 value of the other is passed in a register. */
3970 {
3973 }
3975 ;
3979 /* If this call is indirect, we'll need to be able to use a call-clobbered
3980 register for the address of the target function. Make sure that all
3981 such registers are not used for passing parameters. */
3983 {
3984 tree type;
3986 /* We're looking at the CALL_EXPR, we need the type of the function. */
3992 {
3993 /* ??? Need to count the actual number of registers to be used,
3994 not the possible number of registers. Fix later. */
3996 }
3997 }
3999 /* Dllimport'd functions are also called indirectly. */
4005 /* If we forced aligned the stack, then sibcalling would unalign the
4006 stack, which may break the called function. */
4010 /* Otherwise okay. That also includes certain types of indirect calls. */
4012 }
4014 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4015 calling convention attributes;
4016 arguments as in struct attribute_spec.handler. */
4018 static tree
4020 tree args,
4023 {
4028 {
4033 }
4035 /* Can combine regparm with all attributes but fastcall. */
4037 {
4038 tree cst;
4041 {
4043 }
4047 {
4052 }
4054 {
4058 }
4064 {
4067 }
4070 }
4073 {
4074 /* Do not warn when emulating the MS ABI. */
4080 }
4082 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4084 {
4086 {
4088 }
4090 {
4092 }
4094 {
4096 }
4097 }
4099 /* Can combine stdcall with fastcall (redundant), regparm and
4100 sseregparm. */
4102 {
4104 {
4106 }
4108 {
4110 }
4111 }
4113 /* Can combine cdecl with regparm and sseregparm. */
4115 {
4117 {
4119 }
4121 {
4123 }
4124 }
4126 /* Can combine sseregparm with all attributes. */
4129 }
4131 /* Return 0 if the attributes for two types are incompatible, 1 if they
4132 are compatible, and 2 if they are nearly compatible (which causes a
4133 warning to be generated). */
4135 static int
4137 {
4138 /* Check for mismatch of non-default calling convention. */
4145 /* Check for mismatched fastcall/regparm types. */
4152 /* Check for mismatched sseregparm types. */
4157 /* Check for mismatched return types (cdecl vs stdcall). */
4163 }
4164 \f
4165 /* Return the regparm value for a function with the indicated TYPE and DECL.
4166 DECL may be NULL when calling function indirectly
4167 or considering a libcall. */
4169 static int
4171 {
4172 tree attr;
4178 {
4182 }
4186 {
4187 regparm
4191 {
4192 /* We can't use regparm(3) for nested functions because
4193 these pass static chain pointer in %ecx register. */
4197 {
4201 }
4202 }
4205 }
4210 /* Use register calling convention for local functions when possible. */
4213 {
4214 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4217 {
4221 /* Make sure no regparm register is taken by a
4222 fixed register variable. */
4227 /* We can't use regparm(3) for nested functions as these use
4228 static chain pointer in third argument. */
4235 /* If the function realigns its stackpointer, the prologue will
4236 clobber %ecx. If we've already generated code for the callee,
4237 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4238 scanning the attributes for the self-realigning property. */
4246 /* Each fixed register usage increases register pressure,
4247 so less registers should be used for argument passing.
4248 This functionality can be overriden by an explicit
4249 regparm value. */
4252 globals++;
4254 local_regparm
4259 }
4260 }
4263 }
4265 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4266 DFmode (2) arguments in SSE registers for a function with the
4267 indicated TYPE and DECL. DECL may be NULL when calling function
4268 indirectly or considering a libcall. Otherwise return 0. */
4270 static int
4272 {
4275 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4276 by the sseregparm attribute. */
4279 {
4281 {
4283 {
4287 else
4290 }
4292 }
4295 }
4297 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4298 (and DFmode for SSE2) arguments in SSE registers. */
4300 {
4301 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4305 }
4308 }
4310 /* Return true if EAX is live at the start of the function. Used by
4311 ix86_expand_prologue to determine if we need special help before
4312 calling allocate_stack_worker. */
4314 static bool
4316 {
4317 /* Cheat. Don't bother working forward from ix86_function_regparm
4318 to the function type to whether an actual argument is located in
4319 eax. Instead just look at cfg info, which is still close enough
4320 to correct at this point. This gives false positives for broken
4321 functions that might use uninitialized data that happens to be
4322 allocated in eax, but who cares? */
4324 }
4326 /* Value is the number of bytes of arguments automatically
4327 popped when returning from a subroutine call.
4328 FUNDECL is the declaration node of the function (as a tree),
4329 FUNTYPE is the data type of the function (as a tree),
4330 or for a library call it is an identifier node for the subroutine name.
4331 SIZE is the number of bytes of arguments passed on the stack.
4333 On the 80386, the RTD insn may be used to pop them if the number
4334 of args is fixed, but if the number is variable then the caller
4335 must pop them all. RTD can't be used for library calls now
4336 because the library is compiled with the Unix compiler.
4337 Use of RTD is a selectable option, since it is incompatible with
4338 standard Unix calling sequences. If the option is not selected,
4339 the caller must always pop the args.
4341 The attribute stdcall is equivalent to RTD on a per module basis. */
4343 int
4345 {
4348 /* None of the 64-bit ABIs pop arguments. */
4354 /* Cdecl functions override -mrtd, and never pop the stack. */
4356 {
4357 /* Stdcall and fastcall functions will pop the stack if not
4358 variable args. */
4365 }
4367 /* Lose any fake structure return argument if it is passed on the stack. */
4370 {
4374 }
4377 }
4378 \f
4379 /* Argument support functions. */
4381 /* Return true when register may be used to pass function parameters. */
4382 bool
4384 {
4389 {
4393 else
4399 }
4402 {
4405 }
4406 else
4407 {
4411 }
4413 /* TODO: The function should depend on current function ABI but
4414 builtins.c would need updating then. Therefore we use the
4415 default ABI. */
4417 /* RAX is used as hidden argument to va_arg functions. */
4423 else
4430 }
4432 /* Return if we do not know how to pass TYPE solely in registers. */
4434 static bool
4436 {
4440 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4441 The layout_type routine is crafty and tries to trick us into passing
4442 currently unsupported vector types on the stack by using TImode. */
4445 }
4447 /* It returns the size, in bytes, of the area reserved for arguments passed
4448 in registers for the function represented by fndecl dependent to the used
4449 abi format. */
4450 int
4452 {
4454 /* For libcalls it is possible that there is no fndecl at hand.
4455 Therefore assume for this case the default abi of the target. */
4458 else
4463 }
4465 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4466 call abi used. */
4467 int
4469 {
4471 {
4475 else
4479 }
4481 }
4483 int
4485 {
4489 }
4491 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4492 call abi used. */
4493 int
4495 {
4499 }
4501 /* regclass.c */
4504 /* Implementation of call abi switching target hook. Specific to FNDECL
4505 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4506 for more details.
4507 To prevent redudant calls of costy function init_regs (), it checks not to
4508 reset register usage for default abi. */
4509 void
4511 {
4514 else
4517 {
4519 {
4523 }
4524 }
4526 {
4528 {
4532 }
4533 }
4534 }
4536 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4537 for a call to a function whose data type is FNTYPE.
4538 For a library call, FNTYPE is 0. */
4540 void
4544 tree fndecl)
4545 {
4550 /* Set up the number of registers to use for passing arguments. */
4553 {
4557 }
4559 {
4562 {
4566 }
4567 }
4573 /* Because type might mismatch in between caller and callee, we need to
4574 use actual type of function for local calls.
4575 FIXME: cgraph_analyze can be told to actually record if function uses
4576 va_start so for local functions maybe_vaarg can be made aggressive
4577 helping K&R code.
4578 FIXME: once typesytem is fixed, we won't need this code anymore. */
4586 {
4587 /* If there are variable arguments, then we won't pass anything
4588 in registers in 32-bit mode. */
4590 {
4597 }
4599 /* Use ecx and edx registers if function has fastcall attribute,
4600 else look for regparm information. */
4602 {
4604 {
4607 }
4608 else
4610 }
4612 /* Set up the number of SSE registers used for passing SFmode
4613 and DFmode arguments. Warn for mismatching ABI. */
4615 }
4616 }
4618 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4619 But in the case of vector types, it is some vector mode.
4621 When we have only some of our vector isa extensions enabled, then there
4622 are some modes for which vector_mode_supported_p is false. For these
4623 modes, the generic vector support in gcc will choose some non-vector mode
4624 in order to implement the type. By computing the natural mode, we'll
4625 select the proper ABI location for the operand and not depend on whatever
4626 the middle-end decides to do with these vector types. */
4628 static enum machine_mode
4630 {
4634 {
4637 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4639 {
4644 else
4647 /* Get the mode which has this inner mode and number of units. */
4654 }
4655 }
4658 }
4660 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4661 this may not agree with the mode that the type system has chosen for the
4662 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4663 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4665 static rtx
4668 {
4669 rtx tmp;
4673 else
4674 {
4678 }
4681 }
4683 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4684 of this code is to classify each 8bytes of incoming argument by the register
4685 class and assign registers accordingly. */
4687 /* Return the union class of CLASS1 and CLASS2.
4688 See the x86-64 PS ABI for details. */
4690 static enum x86_64_reg_class
4692 {
4693 /* Rule #1: If both classes are equal, this is the resulting class. */
4697 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4698 the other class. */
4704 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4708 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4716 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4717 MEMORY is used. */
4726 /* Rule #6: Otherwise class SSE is used. */
4728 }
4730 /* Classify the argument of type TYPE and mode MODE.
4731 CLASSES will be filled by the register class used to pass each word
4732 of the operand. The number of words is returned. In case the parameter
4733 should be passed in memory, 0 is returned. As a special case for zero
4734 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4736 BIT_OFFSET is used internally for handling records and specifies offset
4737 of the offset in bits modulo 256 to avoid overflow cases.
4739 See the x86-64 PS ABI for details.
4740 */
4742 static int
4745 {
4746 HOST_WIDE_INT bytes =
4750 /* Variable sized entities are always passed/returned in memory. */
4759 {
4761 tree field;
4764 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
4771 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4772 signalize memory class, so handle it as special case. */
4774 {
4777 }
4779 /* Classify each field of record and merge classes. */
4781 {
4783 /* And now merge the fields of structure. */
4785 {
4787 {
4793 /* Bitfields are always classified as integer. Handle them
4794 early, since later code would consider them to be
4795 misaligned integers. */
4797 {
4805 }
4806 else
4807 {
4815 {
4820 }
4821 }
4822 }
4823 }
4827 /* Arrays are handled as small records. */
4828 {
4835 /* The partial classes are now full classes. */
4845 }
4848 /* Unions are similar to RECORD_TYPE but offset is always 0.
4849 */
4851 {
4853 {
4861 bit_offset);
4866 }
4867 }
4872 }
4874 /* Final merger cleanup. */
4876 {
4877 /* If one class is MEMORY, everything should be passed in
4878 memory. */
4882 /* The X86_64_SSEUP_CLASS should be always preceded by
4883 X86_64_SSE_CLASS. */
4888 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4892 }
4894 }
4896 /* Compute alignment needed. We align all types to natural boundaries with
4897 exception of XFmode that is aligned to 64bits. */
4899 {
4908 /* Misaligned fields are always returned in memory. */
4911 }
4913 /* for V1xx modes, just use the base mode */
4918 /* Classification of atomic types. */
4920 {
4938 else
4950 else
4975 /* This modes is larger than 16 bytes. */
5006 else
5010 }
5011 }
5013 /* Examine the argument and return set number of register required in each
5014 class. Return 0 iff parameter should be passed in memory. */
5015 static int
5018 {
5028 {
5050 }
5052 }
5054 /* Construct container for the argument used by GCC interface. See
5055 FUNCTION_ARG for the detailed description. */
5057 static rtx
5061 {
5062 /* The following variables hold the static issued_error state. */
5076 rtx ret;
5087 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5088 some less clueful developer tries to use floating-point anyway. */
5090 {
5092 {
5094 {
5097 }
5098 }
5100 {
5103 }
5105 }
5107 /* Likewise, error if the ABI requires us to return values in the
5108 x87 registers and the user specified -mno-80387. */
5114 {
5116 {
5119 }
5121 }
5123 /* First construct simple cases. Avoid SCmode, since we want to use
5124 single register to pass this type. */
5127 {
5139 /* Zero sized array, struct or class. */
5143 }
5157 /* Otherwise figure out the entries of the PARALLEL. */
5159 {
5161 {
5166 /* Merge TImodes on aligned occasions here too. */
5171 else
5173 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5179 intreg++;
5186 sse_regno++;
5193 sse_regno++;
5198 else
5205 i++;
5206 sse_regno++;
5210 }
5211 }
5213 /* Empty aligned struct, union or class. */
5221 }
5223 /* Update the data in CUM to advance over an argument of mode MODE
5224 and data type TYPE. (TYPE is null for libcalls where that information
5225 may not be available.) */
5227 static void
5230 {
5232 {
5239 /* FALLTHRU */
5250 {
5253 }
5262 /* FALLTHRU */
5272 {
5277 {
5280 }
5281 }
5290 {
5295 {
5298 }
5299 }
5301 }
5302 }
5304 static void
5307 {
5313 {
5318 }
5319 else
5321 }
5323 static void
5325 HOST_WIDE_INT words)
5326 {
5327 /* Otherwise, this should be passed indirect. */
5332 {
5335 }
5336 }
5338 void
5341 {
5346 else
5357 else
5359 }
5361 /* Define where to put the arguments to a function.
5362 Value is zero to push the argument on the stack,
5363 or a hard register in which to store the argument.
5365 MODE is the argument's machine mode.
5366 TYPE is the data type of the argument (as a tree).
5367 This is null for libcalls where that information may
5368 not be available.
5369 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5370 the preceding args and about the function being called.
5371 NAMED is nonzero if this argument is a named parameter
5372 (otherwise it is an extra parameter matching an ellipsis). */
5374 static rtx
5378 {
5381 /* Avoid the AL settings for the Unix64 ABI. */
5386 {
5393 /* FALLTHRU */
5399 {
5402 /* Fastcall allocates the first two DWORD (SImode) or
5403 smaller arguments to ECX and EDX if it isn't an
5404 aggregate type . */
5406 {
5412 /* ECX not EAX is the first allocated register. */
5415 }
5417 }
5426 /* FALLTHRU */
5435 {
5437 {
5441 }
5445 }
5454 {
5456 {
5460 }
5464 }
5466 }
5469 }
5471 static rtx
5474 {
5475 /* Handle a hidden AL argument containing number of registers
5476 for varargs x86-64 functions. */
5481 ? SSE_REGPARM_MAX
5491 }
5493 static rtx
5496 HOST_WIDE_INT bytes)
5497 {
5500 /* Avoid the AL settings for the Unix64 ABI. */
5504 /* If we've run out of registers, it goes on the stack. */
5510 /* Only floating point modes are passed in anything but integer regs. */
5512 {
5515 else
5516 {
5519 /* Unnamed floating parameters are passed in both the
5520 SSE and integer registers. */
5526 }
5527 }
5528 /* Handle aggregated types passed in register. */
5530 {
5535 }
5538 }
5540 rtx
5543 {
5549 else
5553 /* To simplify the code below, represent vector types with a vector mode
5554 even if MMX/SSE are not active. */
5562 else
5564 }
5566 /* A C expression that indicates when an argument must be passed by
5567 reference. If nonzero for an argument, a copy of that argument is
5568 made in memory and a pointer to the argument is passed instead of
5569 the argument itself. The pointer is passed in whatever way is
5570 appropriate for passing a pointer to that type. */
5572 static bool
5576 {
5577 /* See Windows x64 Software Convention. */
5579 {
5582 {
5583 /* Arrays are passed by reference. */
5588 {
5589 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5590 are passed by reference. */
5592 }
5593 }
5595 /* __m128 is passed by reference. */
5601 }
5602 }
5607 }
5609 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5610 ABI. */
5611 static bool
5613 {
5625 {
5626 /* Walk the aggregates recursively. */
5628 {
5632 {
5633 tree field;
5635 /* Walk all the structure fields. */
5637 {
5641 }
5643 }
5646 /* Just for use if some languages passes arrays by value. */
5653 }
5654 }
5656 }
5658 /* Gives the alignment boundary, in bits, of an argument with the
5659 specified mode and type. */
5661 int
5663 {
5666 {
5667 /* Since canonical type is used for call, we convert it to
5668 canonical type if needed. */
5672 }
5673 else
5677 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5678 natural boundaries. */
5680 {
5681 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5682 make an exception for SSE modes since these require 128bit
5683 alignment.
5685 The handling here differs from field_alignment. ICC aligns MMX
5686 arguments to 4 byte boundaries, while structure fields are aligned
5687 to 8 byte boundaries. */
5689 {
5692 }
5693 else
5694 {
5697 }
5698 }
5702 }
5704 /* Return true if N is a possible register number of function value. */
5706 bool
5708 {
5710 {
5715 /* TODO: The function should depend on current function ABI but
5716 builtins.c would need updating then. Therefore we use the
5717 default ABI. */
5729 }
5732 }
5734 /* Define how to find the value returned by a function.
5735 VALTYPE is the data type of the value (as a tree).
5736 If the precise function being called is known, FUNC is its FUNCTION_DECL;
5737 otherwise, FUNC is 0. */
5739 static rtx
5742 {
5745 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
5746 we normally prevent this case when mmx is not available. However
5747 some ABIs may require the result to be returned like DImode. */
5751 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
5752 we prevent this case when sse is not available. However some ABIs
5753 may require the result to be returned like integer TImode. */
5758 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
5761 else
5762 /* Most things go in %eax. */
5765 /* Override FP return register with %xmm0 for local functions when
5766 SSE math is enabled or for functions with sseregparm attribute. */
5768 {
5773 }
5776 }
5778 static rtx
5780 const_tree valtype)
5781 {
5782 rtx ret;
5784 /* Handle libcalls, which don't provide a type node. */
5786 {
5788 {
5805 }
5806 }
5812 /* For zero sized structures, construct_container returns NULL, but we
5813 need to keep rest of compiler happy by returning meaningful value. */
5818 }
5820 static rtx
5822 {
5826 {
5828 {
5841 }
5842 }
5844 }
5846 static rtx
5849 {
5861 else
5863 }
5865 static rtx
5868 {
5874 }
5876 rtx
5878 {
5880 }
5882 /* Return true iff type is returned in memory. */
5884 static int ATTRIBUTE_UNUSED
5886 {
5887 HOST_WIDE_INT size;
5898 {
5899 /* User-created vectors small enough to fit in EAX. */
5903 /* MMX/3dNow values are returned in MM0,
5904 except when it doesn't exits. */
5908 /* SSE values are returned in XMM0, except when it doesn't exist. */
5911 }
5919 }
5921 static int ATTRIBUTE_UNUSED
5923 {
5926 }
5928 static int ATTRIBUTE_UNUSED
5930 {
5933 /* __m128 is returned in xmm0. */
5938 /* Otherwise, the size must be exactly in [1248]. */
5940 }
5942 static bool
5944 {
5945 #ifdef SUBTARGET_RETURN_IN_MEMORY
5947 #else
5954 else
5956 #endif
5957 }
5959 /* Return false iff TYPE is returned in memory. This version is used
5960 on Solaris 10. It is similar to the generic ix86_return_in_memory,
5961 but differs notably in that when MMX is available, 8-byte vectors
5962 are returned in memory, rather than in MMX registers. */
5964 bool
5966 {
5979 {
5980 /* Return in memory only if MMX registers *are* available. This
5981 seems backwards, but it is consistent with the existing
5982 Solaris x86 ABI. */
5987 }
5994 }
5996 /* When returning SSE vector types, we have a choice of either
5997 (1) being abi incompatible with a -march switch, or
5998 (2) generating an error.
5999 Given no good solution, I think the safest thing is one warning.
6000 The user won't be able to use -Werror, but....
6002 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6003 called in response to actually generating a caller or callee that
6004 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6005 via aggregate_value_p for general type probing from tree-ssa. */
6007 static rtx
6009 {
6013 {
6014 /* Look at the return type of the function, not the function type. */
6018 {
6021 {
6025 }
6026 }
6029 {
6031 {
6035 }
6036 }
6037 }
6040 }
6042 \f
6043 /* Create the va_list data type. */
6045 /* Returns the calling convention specific va_list date type.
6046 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6048 static tree
6050 {
6053 /* For i386 we use plain pointer to argument area. */
6061 unsigned_type_node);
6063 unsigned_type_node);
6065 ptr_type_node);
6067 ptr_type_node);
6086 /* The correct type is an array type of one element. */
6088 }
6090 /* Setup the builtin va_list data type and for 64-bit the additional
6091 calling convention specific va_list data types. */
6093 static tree
6095 {
6098 /* Initialize abi specific va_list builtin types. */
6100 {
6101 tree t;
6103 {
6108 }
6109 else
6110 {
6115 }
6117 {
6122 }
6123 else
6124 {
6129 }
6130 }
6133 }
6135 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6137 static void
6139 {
6141 rtx label;
6142 rtx label_ref;
6143 rtx tmp_reg;
6144 rtx nsse_reg;
6145 alias_set_type set;
6155 /* Indicate to allocate space on the stack for varargs save area. */
6157 /* We need 16-byte stack alignment to save SSE registers. If user
6158 asked for lower preferred_stack_boundary, lets just hope that he knows
6159 what he is doing and won't varargs SSE values.
6161 We also may end up assuming that only 64bit values are stored in SSE
6162 register let some floating point program work. */
6170 i < regparm
6172 i++)
6173 {
6180 }
6183 {
6184 /* Now emit code to save SSE registers. The AX parameter contains number
6185 of SSE parameter registers used to call this function. We use
6186 sse_prologue_save insn template that produces computed jump across
6187 SSE saves. We need some preparation work to get this working. */
6192 /* Compute address to jump to :
6193 label - eax*4 + nnamed_sse_arguments*4 */
6201 emit_move_insn
6205 label_ref,
6207 else
6211 /* Compute address of memory block we save into. We always use pointer
6212 pointing 127 bytes after first byte to store - this is needed to keep
6213 instruction size limited by 4 bytes. */
6223 /* And finally do the dirty job! */
6226 }
6227 }
6229 static void
6231 {
6236 {
6247 }
6248 }
6250 static void
6254 {
6255 CUMULATIVE_ARGS next_cum;
6256 tree fntype;
6258 /* This argument doesn't appear to be used anymore. Which is good,
6259 because the old code here didn't suppress rtl generation. */
6267 /* For varargs, we do not want to skip the dummy va_dcl argument.
6268 For stdargs, we do want to skip the last named argument. */
6275 else
6277 }
6279 /* Checks if TYPE is of kind va_list char *. */
6281 static bool
6283 {
6284 tree canonic;
6286 /* For 32-bit it is always true. */
6292 }
6294 /* Implement va_start. */
6296 static void
6298 {
6302 tree type;
6304 /* Only 64bit target needs something special. */
6306 {
6309 }
6322 /* Count number of gp and fp argument registers used. */
6328 {
6334 }
6337 {
6343 }
6345 /* Find the overflow area. */
6356 {
6357 /* Find the register save area.
6358 Prologue of the function save it right above stack frame. */
6364 }
6365 }
6367 /* Implement va_arg. */
6369 static tree
6372 {
6379 rtx container;
6381 tree ptrtype;
6385 /* Only 64bit target needs something special. */
6411 /* Pull the value out of the saved registers. */
6417 {
6431 /* In case we are passing structure, verify that it is consecutive block
6432 on the register save area. If not we need to do moves. */
6434 {
6435 /* Verify that all registers are strictly consecutive */
6437 {
6441 {
6446 }
6447 }
6448 else
6449 {
6453 {
6458 }
6459 }
6460 }
6462 {
6465 }
6466 else
6467 {
6472 }
6474 /* First ensure that we fit completely in registers. */
6476 {
6483 }
6485 {
6493 }
6495 /* Compute index to start of area used for integer regs. */
6497 {
6498 /* int_addr = gpr + sav; */
6502 }
6504 {
6505 /* sse_addr = fpr + sav; */
6509 }
6511 {
6515 /* addr = &temp; */
6520 {
6531 {
6534 }
6535 else
6536 {
6539 }
6551 }
6552 }
6555 {
6559 }
6562 {
6566 }
6571 }
6573 /* ... otherwise out of the overflow area. */
6575 /* When we align parameter on stack for caller, if the parameter
6576 alignment is beyond PREFERRED_STACK_BOUNDARY, it will be
6577 aligned at PREFERRED_STACK_BOUNDARY. We will match callee
6578 here with caller. */
6583 /* Care for on-stack alignment if needed. */
6587 else
6588 {
6596 }
6613 }
6614 \f
6615 /* Return nonzero if OPNUM's MEM should be matched
6616 in movabs* patterns. */
6618 int
6620 {
6632 }
6633 \f
6634 /* Initialize the table of extra 80387 mathematical constants. */
6636 static void
6638 {
6640 {
6646 };
6650 {
6652 /* Ensure each constant is rounded to XFmode precision. */
6655 }
6658 }
6660 /* Return true if the constant is something that can be loaded with
6661 a special instruction. */
6663 int
6665 {
6668 REAL_VALUE_TYPE r;
6680 /* For XFmode constants, try to find a special 80387 instruction when
6681 optimizing for size or on those CPUs that benefit from them. */
6684 {
6693 }
6695 /* Load of the constant -0.0 or -1.0 will be split as
6696 fldz;fchs or fld1;fchs sequence. */
6703 }
6705 /* Return the opcode of the special instruction to be used to load
6706 the constant X. */
6710 {
6712 {
6732 }
6733 }
6735 /* Return the CONST_DOUBLE representing the 80387 constant that is
6736 loaded by the specified special instruction. The argument IDX
6737 matches the return value from standard_80387_constant_p. */
6739 rtx
6741 {
6748 {
6759 }
6762 XFmode);
6763 }
6765 /* Return 1 if mode is a valid mode for sse. */
6766 static int
6768 {
6770 {
6781 }
6782 }
6784 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
6785 */
6786 int
6788 {
6798 }
6800 /* Return the opcode of the special instruction to be used to load
6801 the constant X. */
6805 {
6807 {
6813 else
6817 }
6819 }
6821 /* Returns 1 if OP contains a symbol reference */
6823 int
6825 {
6834 {
6836 {
6842 }
6846 }
6849 }
6851 /* Return 1 if it is appropriate to emit `ret' instructions in the
6852 body of a function. Do this only if the epilogue is simple, needing a
6853 couple of insns. Prior to reloading, we can't tell how many registers
6854 must be saved, so return 0 then. Return 0 if there is no frame
6855 marker to de-allocate. */
6857 int
6859 {
6865 /* Don't allow more than 32 pop, since that's all we can do
6866 with one instruction. */
6873 }
6874 \f
6875 /* Value should be nonzero if functions must have frame pointers.
6876 Zero means the frame pointer need not be set up (and parms may
6877 be accessed via the stack pointer) in functions that seem suitable. */
6879 int
6881 {
6882 /* If we accessed previous frames, then the generated code expects
6883 to be able to access the saved ebp value in our frame. */
6887 /* Several x86 os'es need a frame pointer for other reasons,
6888 usually pertaining to setjmp. */
6892 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
6893 the frame pointer by default. Turn it back on now if we've not
6894 got a leaf function. */
6896 && (!current_function_is_leaf
6904 }
6906 /* Record that the current function accesses previous call frames. */
6908 void
6910 {
6912 }
6913 \f
6914 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
6915 # define USE_HIDDEN_LINKONCE 1
6916 #else
6917 # define USE_HIDDEN_LINKONCE 0
6918 #endif
6922 /* Fills in the label name that should be used for a pc thunk for
6923 the given register. */
6925 static void
6927 {
6932 else
6934 }
6937 /* This function generates code for -fpic that loads %ebx with
6938 the return address of the caller and then returns. */
6940 void
6942 {
6947 {
6955 #if TARGET_MACHO
6957 {
6965 }
6966 else
6967 #endif
6969 {
6970 tree decl;
6973 error_mark_node);
6986 }
6987 else
6988 {
6991 }
6997 }
7001 }
7003 /* Emit code for the SET_GOT patterns. */
7007 {
7013 {
7014 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7019 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7020 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7021 an unadorned address. */
7026 }
7031 {
7036 else
7039 #if TARGET_MACHO
7040 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7041 is what will be referenced by the Mach-O PIC subsystem. */
7044 #endif
7051 }
7052 else
7053 {
7061 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7062 is what will be referenced by the Mach-O PIC subsystem. */
7063 #if TARGET_MACHO
7066 else
7069 #endif
7070 }
7077 else
7081 }
7083 /* Generate an "push" pattern for input ARG. */
7085 static rtx
7087 {
7091 stack_pointer_rtx)),
7092 arg);
7093 }
7095 /* Return >= 0 if there is an unused call-clobbered register available
7096 for the entire function. */
7098 static unsigned int
7100 {
7103 {
7108 }
7111 }
7113 /* Return 1 if we need to save REGNO. */
7114 static int
7116 {
7123 {
7127 }
7130 {
7133 {
7139 }
7140 }
7150 }
7152 /* Return number of registers to be saved on the stack. */
7154 static int
7156 {
7162 nregs++;
7164 }
7166 /* Return the offset between two registers, one to be eliminated, and the other
7167 its replacement, at the start of a routine. */
7169 HOST_WIDE_INT
7171 {
7180 else
7181 {
7189 }
7190 }
7192 /* Fill structure ix86_frame about frame of currently computed function. */
7194 static void
7196 {
7197 HOST_WIDE_INT total_size;
7199 HOST_WIDE_INT offset;
7209 /* During reload iteration the amount of registers saved can change.
7210 Recompute the value as needed. Do not recompute when amount of registers
7211 didn't change as reload does multiple calls to the function and does not
7212 expect the decision to change within single iteration. */
7215 {
7219 /* The fast prologue uses move instead of push to save registers. This
7220 is significantly longer, but also executes faster as modern hardware
7221 can execute the moves in parallel, but can't do that for push/pop.
7223 Be careful about choosing what prologue to emit: When function takes
7224 many instructions to execute we may use slow version as well as in
7225 case function is known to be outside hot spot (this is known with
7226 feedback only). Weight the size of function by number of registers
7227 to save as it is cheap to use one or two push instructions but very
7228 slow to use many of them. */
7232 || (flag_branch_probabilities
7235 else
7238 }
7242 else
7246 /* Skip return address and saved base pointer. */
7251 /* Do some sanity checking of stack_alignment_needed and
7252 preferred_alignment, since i386 port is the only using those features
7253 that may break easily. */
7264 /* Register save area */
7267 /* Va-arg area */
7269 {
7272 }
7273 else
7276 /* Align start of frame for local function. */
7282 /* Frame pointer points here. */
7287 /* Add outgoing arguments area. Can be skipped if we eliminated
7288 all the function calls as dead code.
7289 Skipping is however impossible when function calls alloca. Alloca
7290 expander assumes that last crtl->outgoing_args_size
7291 of stack frame are unused. */
7295 {
7298 }
7299 else
7302 /* Align stack boundary. Only needed if we're calling another function
7303 or using alloca. */
7308 else
7313 /* We've reached end of stack frame. */
7316 /* Size prologue needs to allocate. */
7326 && current_function_is_leaf
7328 {
7334 }
7335 else
7339 #if 0
7355 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7356 #endif
7357 }
7359 /* Emit code to save registers in the prologue. */
7361 static void
7363 {
7365 rtx insn;
7369 {
7372 }
7373 }
7375 /* Emit code to save registers using MOV insns. First register
7376 is restored from POINTER + OFFSET. */
7377 static void
7379 {
7381 rtx insn;
7385 {
7391 }
7392 }
7394 /* Expand prologue or epilogue stack adjustment.
7395 The pattern exist to put a dependency on all ebp-based memory accesses.
7396 STYLE should be negative if instructions should be marked as frame related,
7397 zero if %r11 register is live and cannot be freely used and positive
7398 otherwise. */
7400 static void
7402 {
7403 rtx insn;
7409 else
7410 {
7411 rtx r11;
7412 /* r11 is used by indirect sibcall return as well, set before the
7413 epilogue and used after the epilogue. ATM indirect sibcall
7414 shouldn't be used together with huge frame sizes in one
7415 function because of the frame_size check in sibcall.c. */
7422 offset));
7423 }
7426 }
7428 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7430 static rtx
7432 {
7440 || ix86_force_align_arg_pointer
7442 {
7443 /* Nested functions can't realign the stack due to a register
7444 conflict. */
7447 {
7452 ix86_force_align_arg_pointer_string);
7454 }
7457 }
7458 else
7460 }
7462 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7463 This is called from dwarf2out.c to emit call frame instructions
7464 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7465 static void
7467 {
7472 {
7483 }
7484 }
7486 /* Expand the prologue into a bunch of separate insns. */
7488 void
7490 {
7491 rtx insn;
7494 HOST_WIDE_INT allocate;
7499 {
7502 /* Grab the argument pointer. */
7508 /* The unwind info consists of two parts: install the fafp as the cfa,
7509 and record the fafp as the "save register" of the stack pointer.
7510 The later is there in order that the unwinder can see where it
7511 should restore the stack pointer across the and insn. */
7516 UNSPEC_REG_SAVE);
7523 /* Align the stack. */
7527 /* And here we cheat like madmen with the unwind info. We force the
7528 cfa register back to sp+4, which is exactly what it was at the
7529 start of the function. Re-pushing the return address results in
7530 the return at the same spot relative to the cfa, and thus is
7531 correct wrt the unwind info. */
7542 }
7544 /* Note: AT&T enter does NOT have reversed args. Enter is probably
7545 slower on all targets. Also sdb doesn't like it. */
7548 {
7554 }
7560 else
7563 /* When using red zone we may start register saving before allocating
7564 the stack frame saving one cycle of the prologue. However I will
7565 avoid doing this if I am going to have to probe the stack since
7566 at least on x86_64 the stack probe can turn into a call that clobbers
7567 a red zone location */
7575 ;
7579 else
7580 {
7581 /* Only valid for Win32. */
7584 rtx t;
7590 else
7594 {
7597 }
7603 else
7613 {
7616 allocate
7619 else
7622 }
7623 }
7628 {
7631 else
7634 }
7640 {
7647 }
7650 {
7652 {
7654 {
7664 }
7665 else
7667 }
7668 else
7670 }
7672 /* Prevent function calls from being scheduled before the call to mcount.
7673 In the pic_reg_used case, make sure that the got load isn't deleted. */
7675 {
7679 }
7681 /* Emit cld instruction if stringops are used in the function. */
7684 }
7686 /* Emit code to restore saved registers using MOV insns. First register
7687 is restored from POINTER + OFFSET. */
7688 static void
7691 {
7697 {
7698 /* Ensure that adjust_address won't be forced to produce pointer
7699 out of range allowed by x86-64 instruction set. */
7701 {
7702 rtx r11;
7709 }
7713 }
7714 }
7716 /* Restore function stack, frame, and registers. */
7718 void
7720 {
7724 HOST_WIDE_INT offset;
7728 /* Calculate start of saved registers relative to ebp. Special care
7729 must be taken for the normal return case of a function using
7730 eh_return: the eax and edx registers are marked as saved, but not
7731 restored along this path. */
7737 /* If we're only restoring one register and sp is not valid then
7738 using a move instruction to restore the register since it's
7739 less work than reloading sp and popping the register.
7741 The default code result in stack adjustment using add/lea instruction,
7742 while this code results in LEAVE instruction (or discrete equivalent),
7743 so it is profitable in some other cases as well. Especially when there
7744 are no registers to restore. We also use this code when TARGET_USE_LEAVE
7745 and there is exactly one register to pop. This heuristic may need some
7746 tuning in future. */
7748 || (TARGET_EPILOGUE_USING_MOVE
7756 {
7757 /* Restore registers. We can use ebp or esp to address the memory
7758 locations. If both are available, default to ebp, since offsets
7759 are known to be small. Only exception is esp pointing directly to the
7760 end of block of saved registers, where we may simplify addressing
7761 mode. */
7766 else
7770 /* eh_return epilogues need %ecx added to the stack pointer. */
7772 {
7776 {
7786 }
7787 else
7788 {
7793 }
7794 }
7799 style);
7800 /* If not an i386, mov & pop is faster than "leave". */
7804 else
7805 {
7807 hard_frame_pointer_rtx,
7811 }
7812 }
7813 else
7814 {
7815 /* First step is to deallocate the stack frame so that we can
7816 pop the registers. */
7818 {
7821 hard_frame_pointer_rtx,
7823 }
7832 {
7833 /* Leave results in shorter dependency chains on CPUs that are
7834 able to grok it fast. */
7837 else
7839 }
7840 }
7843 {
7847 }
7849 /* Sibcall epilogues don't want a return instruction. */
7854 {
7857 /* i386 can only pop 64K bytes. If asked to pop more, pop
7858 return address, do explicit add, and jump indirectly to the
7859 caller. */
7862 {
7865 /* There is no "pascal" calling convention in any 64bit ABI. */
7871 }
7872 else
7874 }
7875 else
7877 }
7879 /* Reset from the function's potential modifications. */
7881 static void
7883 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7884 {
7887 #if TARGET_MACHO
7888 /* Mach-O doesn't support labels at the end of objects, so if
7889 it looks like we might want one, insert a NOP. */
7890 {
7901 }
7902 #endif
7904 }
7905 \f
7906 /* Extract the parts of an RTL expression that is a valid memory address
7907 for an instruction. Return 0 if the structure of the address is
7908 grossly off. Return -1 if the address contains ASHIFT, so it is not
7909 strictly valid, but still used for computing length of lea instruction. */
7911 int
7913 {
7924 {
7929 do
7930 {
7935 }
7942 {
7945 {
7955 && TARGET_TLS_DIRECT_SEG_REFS
7958 else
7968 else
7983 }
7984 }
7985 }
7987 {
7990 }
7992 {
7993 rtx tmp;
7995 /* We're called for lea too, which implements ashift on occasion. */
8005 }
8006 else
8009 /* Extract the integral value of scale. */
8011 {
8015 }
8020 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8025 {
8026 rtx tmp;
8029 }
8031 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8037 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8038 Avoid this by transforming to [%esi+0]. */
8045 /* Special case: encode reg+reg instead of reg*2. */
8049 /* Special case: scaling cannot be encoded without base or displacement. */
8060 }
8061 \f
8062 /* Return cost of the memory address x.
8063 For i386, it is better to use a complex address than let gcc copy
8064 the address into a reg and make a new pseudo. But not if the address
8065 requires to two regs - that would mean more pseudos with longer
8066 lifetimes. */
8067 static int
8069 {
8081 /* Attempt to minimize number of registers in the address. */
8087 cost++;
8094 cost++;
8096 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8097 since it's predecode logic can't detect the length of instructions
8098 and it degenerates to vector decoded. Increase cost of such
8099 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8100 to split such addresses or even refuse such addresses at all.
8102 Following addressing modes are affected:
8103 [base+scale*index]
8104 [scale*index+disp]
8105 [base+index]
8107 The first and last case may be avoidable by explicitly coding the zero in
8108 memory address, but I don't have AMD-K6 machine handy to check this
8109 theory. */
8118 }
8119 \f
8120 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8121 this is used for to form addresses to local data when -fPIC is in
8122 use. */
8124 static bool
8126 {
8128 {
8132 {
8136 }
8137 }
8140 }
8142 /* Determine if a given RTX is a valid constant. We already know this
8143 satisfies CONSTANT_P. */
8145 bool
8147 {
8149 {
8154 {
8158 }
8163 /* Only some unspecs are valid as "constants". */
8166 {
8182 }
8184 /* We must have drilled down to a symbol. */
8189 /* FALLTHRU */
8192 /* TLS symbols are never valid. */
8196 /* DLLIMPORT symbols are never valid. */
8216 }
8218 /* Otherwise we handle everything else in the move patterns. */
8220 }
8222 /* Determine if it's legal to put X into the constant pool. This
8223 is not possible for the address of thread-local symbols, which
8224 is checked above. */
8226 static bool
8228 {
8229 /* We can always put integral constants and vectors in memory. */
8231 {
8239 }
8241 }
8243 /* Determine if a given RTX is a valid constant address. */
8245 bool
8247 {
8249 }
8251 /* Nonzero if the constant value X is a legitimate general operand
8252 when generating PIC code. It is given that flag_pic is on and
8253 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8255 bool
8257 {
8258 rtx inner;
8261 {
8268 /* Only some unspecs are valid as "constants". */
8271 {
8282 }
8283 /* FALLTHRU */
8291 }
8292 }
8294 /* Determine if a given CONST RTX is a valid memory displacement
8295 in PIC mode. */
8297 int
8299 {
8302 /* In 64bit mode we can allow direct addresses of symbols and labels
8303 when they are not dynamic symbols. */
8305 {
8309 {
8326 /* FALLTHRU */
8329 /* TLS references should always be enclosed in UNSPEC. */
8339 }
8340 }
8346 {
8347 /* We are unsafe to allow PLUS expressions. This limit allowed distance
8348 of GOT tables. We should not need these anyway. */
8359 }
8363 {
8368 }
8377 {
8381 /* We need to check for both symbols and labels because VxWorks loads
8382 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
8383 details. */
8387 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
8388 While ABI specify also 32bit relocation but we don't produce it in
8389 small PIC model at all. */
8411 }
8414 }
8416 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
8417 memory address for an instruction. The MODE argument is the machine mode
8418 for the MEM expression that wants to use this address.
8420 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
8421 convert common non-canonical forms to canonical form so that they will
8422 be recognized. */
8424 int
8427 {
8430 HOST_WIDE_INT scale;
8435 {
8438 }
8445 /* Validate base register.
8447 Don't allow SUBREG's that span more than a word here. It can lead to spill
8448 failures when the base is one word out of a two word structure, which is
8449 represented internally as a DImode int. */
8452 {
8453 rtx reg;
8463 else
8464 {
8467 }
8470 {
8473 }
8477 {
8480 }
8481 }
8483 /* Validate index register.
8485 Don't allow SUBREG's that span more than a word here -- same as above. */
8488 {
8489 rtx reg;
8499 else
8500 {
8503 }
8506 {
8509 }
8513 {
8516 }
8517 }
8519 /* Validate scale factor. */
8521 {
8524 {
8527 }
8530 {
8533 }
8534 }
8536 /* Validate displacement. */
8538 {
8544 {
8545 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
8546 used. While ABI specify also 32bit relocations, we don't produce
8547 them at all and use IP relative instead. */
8570 }
8573 && (flag_pic
8574 || (TARGET_MACHO
8575 #if TARGET_MACHO
8576 && MACHOPIC_INDIRECT
8578 #endif
8579 )))
8580 {
8582 is_legitimate_pic:
8584 {
8585 /* foo@dtpoff(%rX) is ok. */
8592 {
8595 }
8596 }
8598 {
8601 }
8603 /* This code used to verify that a symbolic pic displacement
8604 includes the pic_offset_table_rtx register.
8606 While this is good idea, unfortunately these constructs may
8607 be created by "adds using lea" optimization for incorrect
8608 code like:
8610 int a;
8611 int foo(int i)
8612 {
8613 return *(&a+i);
8614 }
8616 This code is nonsensical, but results in addressing
8617 GOT table with pic_offset_table_rtx base. We can't
8618 just refuse it easily, since it gets matched by
8619 "addsi3" pattern, that later gets split to lea in the
8620 case output register differs from input. While this
8621 can be handled by separate addsi pattern for this case
8622 that never results in lea, this seems to be easier and
8623 correct fix for crash to disable this test. */
8624 }
8631 {
8634 }
8637 {
8640 }
8641 }
8643 /* Everything looks valid. */
8646 report_error:
8648 }
8649 \f
8650 /* Return a unique alias set for the GOT. */
8652 static alias_set_type
8654 {
8659 }
8661 /* Return a legitimate reference for ORIG (an address) using the
8662 register REG. If REG is 0, a new pseudo is generated.
8664 There are two types of references that must be handled:
8666 1. Global data references must load the address from the GOT, via
8667 the PIC reg. An insn is emitted to do this load, and the reg is
8668 returned.
8670 2. Static data references, constant pool addresses, and code labels
8671 compute the address as an offset from the GOT, whose base is in
8672 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
8673 differentiate them from global data objects. The returned
8674 address is the PIC reg + an unspec constant.
8676 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
8677 reg also appears in the address. */
8679 static rtx
8681 {
8684 rtx base;
8686 #if TARGET_MACHO
8688 {
8691 /* Use the generic Mach-O PIC machinery. */
8693 }
8694 #endif
8701 {
8702 rtx tmpreg;
8703 /* This symbol may be referenced via a displacement from the PIC
8704 base address (@GOTOFF). */
8711 {
8713 UNSPEC_GOTOFF);
8715 }
8716 else
8721 else
8726 {
8730 }
8732 }
8734 {
8735 /* This symbol may be referenced via a displacement from the PIC
8736 base address (@GOTOFF). */
8743 {
8745 UNSPEC_GOTOFF);
8747 }
8748 else
8754 {
8757 }
8758 }
8760 /* We can't use @GOTOFF for text labels on VxWorks;
8761 see gotoff_operand. */
8763 {
8765 {
8771 {
8774 }
8775 }
8778 {
8786 /* Use directly gen_movsi, otherwise the address is loaded
8787 into register for CSE. We don't want to CSE this addresses,
8788 instead we CSE addresses from the GOT table, so skip this. */
8791 }
8792 else
8793 {
8794 /* This symbol must be referenced via a load from the
8795 Global Offset Table (@GOT). */
8811 }
8812 }
8813 else
8814 {
8817 {
8819 {
8822 }
8823 else
8825 }
8827 {
8830 /* We must match stuff we generate before. Assume the only
8831 unspecs that can get here are ours. Not that we could do
8832 anything with them anyway.... */
8838 }
8840 {
8843 /* Check first to see if this is a constant offset from a @GOTOFF
8844 symbol reference. */
8847 {
8849 {
8853 UNSPEC_GOTOFF);
8859 {
8862 }
8863 }
8864 else
8865 {
8868 {
8872 }
8873 }
8874 }
8875 else
8876 {
8883 else
8884 {
8886 {
8889 }
8891 }
8892 }
8893 }
8894 }
8896 }
8897 \f
8898 /* Load the thread pointer. If TO_REG is true, force it into a register. */
8900 static rtx
8902 {
8914 }
8916 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
8917 false if we expect this to be used for a memory address and true if
8918 we expect to load the address into a register. */
8920 static rtx
8922 {
8927 {
8933 {
8943 }
8946 else
8950 {
8954 }
8962 {
8974 }
8977 else
8981 {
8986 }
8994 {
8998 }
9004 {
9007 }
9009 {
9014 }
9016 {
9020 }
9021 else
9022 {
9025 }
9035 {
9039 }
9040 else
9041 {
9045 }
9055 {
9058 }
9059 else
9060 {
9064 }
9069 }
9072 }
9074 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9075 to symbol DECL. */
9078 htab_t dllimport_map;
9080 static tree
9082 {
9089 tree to;
9090 rtx rtl;
9133 }
9135 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9136 true if we require the result be a register. */
9138 static rtx
9140 {
9141 tree imp_decl;
9142 rtx x;
9151 }
9153 /* Try machine-dependent ways of modifying an illegitimate address
9154 to be legitimate. If we find one, return the new, valid address.
9155 This macro is used in only one place: `memory_address' in explow.c.
9157 OLDX is the address as it was before break_out_memory_refs was called.
9158 In some cases it is useful to look at this to decide what needs to be done.
9160 MODE and WIN are passed so that this macro can use
9161 GO_IF_LEGITIMATE_ADDRESS.
9163 It is always safe for this macro to do nothing. It exists to recognize
9164 opportunities to optimize the output.
9166 For the 80386, we handle X+REG by loading X into a register R and
9167 using R+REG. R will go in a general reg and indexing will be used.
9168 However, if REG is a broken-out memory address or multiplication,
9169 nothing needs to be done because REG can certainly go in a general reg.
9171 When -fpic is used, special handling is needed for symbolic references.
9172 See comments by legitimize_pic_address in i386.c for details. */
9174 rtx
9176 {
9187 {
9191 }
9194 {
9201 {
9204 }
9205 }
9210 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9214 {
9219 }
9222 {
9223 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9228 {
9234 }
9239 {
9245 }
9247 /* Put multiply first if it isn't already. */
9249 {
9254 }
9256 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9257 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9258 created by virtual register instantiation, register elimination, and
9259 similar optimizations. */
9261 {
9267 }
9269 /* Canonicalize
9270 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9271 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9276 {
9277 rtx constant;
9281 {
9284 }
9286 {
9289 }
9290 else
9294 {
9300 }
9301 }
9307 {
9310 }
9313 {
9316 }
9324 {
9327 }
9333 {
9341 }
9344 {
9352 }
9353 }
9356 }
9357 \f
9358 /* Print an integer constant expression in assembler syntax. Addition
9359 and subtraction are the only arithmetic that may appear in these
9360 expressions. FILE is the stdio stream to write to, X is the rtx, and
9361 CODE is the operand print code from the output string. */
9363 static void
9365 {
9369 {
9378 else
9379 {
9382 /* Mark the decl as referenced so that cgraph will
9383 output the function. */
9387 #if TARGET_MACHO
9391 #endif
9393 }
9401 /* FALLTHRU */
9412 /* This used to output parentheses around the expression,
9413 but that does not work on the 386 (either ATT or BSD assembler). */
9419 {
9420 /* We can use %d if the number is <32 bits and positive. */
9425 else
9427 }
9428 else
9429 /* We can't handle floating point constants;
9430 PRINT_OPERAND must handle them. */
9435 /* Some assemblers need integer constants to appear first. */
9437 {
9441 }
9442 else
9443 {
9448 }
9465 {
9480 /* FIXME: This might be @TPOFF in Sun ld too. */
9489 else
9499 else
9508 }
9513 }
9514 }
9516 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9517 We need to emit DTP-relative relocations. */
9519 static void ATTRIBUTE_UNUSED
9521 {
9526 {
9534 }
9535 }
9537 /* In the name of slightly smaller debug output, and to cater to
9538 general assembler lossage, recognize PIC+GOTOFF and turn it back
9539 into a direct symbol reference.
9541 On Darwin, this is necessary to avoid a crash, because Darwin
9542 has a different PIC label for each routine but the DWARF debugging
9543 information is not associated with any particular routine, so it's
9544 necessary to remove references to the PIC label from RTL stored by
9545 the DWARF output code. */
9547 static rtx
9549 {
9551 /* reg_addend is NULL or a multiple of some register. */
9553 /* const_addend is NULL or a const_int. */
9555 /* This is the result, or NULL. */
9562 {
9569 }
9577 /* %ebx + GOT/GOTOFF */
9578 ;
9580 {
9581 /* %ebx + %reg * scale + GOT/GOTOFF */
9589 else
9595 }
9596 else
9602 {
9605 }
9624 }
9626 /* If X is a machine specific address (i.e. a symbol or label being
9627 referenced as a displacement from the GOT implemented using an
9628 UNSPEC), then return the base term. Otherwise return X. */
9630 rtx
9632 {
9633 rtx term;
9636 {
9655 }
9664 }
9665 \f
9666 static void
9669 {
9673 {
9679 }
9684 {
9687 {
9706 }
9710 {
9729 }
9736 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
9737 Those same assemblers have the same but opposite lossage on cmov. */
9742 else
9747 {
9760 }
9768 {
9781 }
9784 /* ??? As above. */
9793 /* ??? As above. */
9798 else
9809 }
9811 }
9813 /* Print the name of register X to FILE based on its machine mode and number.
9814 If CODE is 'w', pretend the mode is HImode.
9815 If CODE is 'b', pretend the mode is QImode.
9816 If CODE is 'k', pretend the mode is SImode.
9817 If CODE is 'q', pretend the mode is DImode.
9818 If CODE is 'h', pretend the reg is the 'high' byte register.
9819 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
9821 void
9823 {
9835 {
9839 }
9853 else
9856 /* Irritatingly, AMD extended registers use different naming convention
9857 from the normal registers. */
9859 {
9862 {
9881 }
9883 }
9885 {
9888 {
9891 }
9892 /* FALLTHRU */
9898 /* FALLTHRU */
9901 normal:
9916 }
9917 }
9919 /* Locate some local-dynamic symbol still in use by this function
9920 so that we can print its name in some tls_local_dynamic_base
9921 pattern. */
9923 static int
9925 {
9930 {
9933 }
9936 }
9940 {
9941 rtx insn;
9952 }
9954 /* Meaning of CODE:
9955 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
9956 C -- print opcode suffix for set/cmov insn.
9957 c -- like C, but print reversed condition
9958 E,e -- likewise, but for compare-and-branch fused insn.
9959 F,f -- likewise, but for floating-point.
9960 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
9961 otherwise nothing
9962 R -- print the prefix for register names.
9963 z -- print the opcode suffix for the size of the current operand.
9964 * -- print a star (in certain assembler syntax)
9965 A -- print an absolute memory reference.
9966 w -- print the operand as if it's a "word" (HImode) even if it isn't.
9967 s -- print a shift double count, followed by the assemblers argument
9968 delimiter.
9969 b -- print the QImode name of the register for the indicated operand.
9970 %b0 would print %al if operands[0] is reg 0.
9971 w -- likewise, print the HImode name of the register.
9972 k -- likewise, print the SImode name of the register.
9973 q -- likewise, print the DImode name of the register.
9974 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
9975 y -- print "st(0)" instead of "st" as a register.
9976 D -- print condition for SSE cmp instruction.
9977 P -- if PIC, print an @PLT suffix.
9978 X -- don't print any sort of PIC '@' suffix for a symbol.
9979 & -- print some in-use local-dynamic symbol name.
9980 H -- print a memory address offset by 8; used for sse high-parts
9981 Y -- print condition for SSE5 com* instruction.
9982 + -- print a branch hint as 'cs' or 'ds' prefix
9983 ; -- print a semicolon (after prefixes due to bug in older gas).
9984 */
9986 void
9988 {
9990 {
9992 {
10004 {
10010 /* Intel syntax. For absolute addresses, registers should not
10011 be surrounded by braces. */
10013 {
10018 }
10023 }
10060 /* 387 opcodes don't get size suffixes if the operands are
10061 registers. */
10065 /* Likewise if using Intel opcodes. */
10069 /* This is the size of op from size of operand. */
10071 {
10078 {
10079 #ifdef HAVE_GAS_FILDS_FISTS
10081 #endif
10083 }
10084 else
10090 {
10093 }
10094 else
10105 {
10107 {
10108 #ifdef GAS_MNEMONICS
10110 #else
10113 #endif
10114 }
10115 else
10117 }
10118 else
10124 }
10138 {
10141 }
10145 /* Little bit of braindamage here. The SSE compare instructions
10146 does use completely different names for the comparisons that the
10147 fp conditional moves. */
10149 {
10182 }
10185 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10187 {
10189 {
10196 }
10198 }
10199 #endif
10205 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10208 #endif
10212 /* Like above, but reverse condition */
10214 /* Check to see if argument to %c is really a constant
10215 and not a condition code which needs to be reversed. */
10217 {
10218 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
10220 }
10224 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10227 #endif
10240 /* It doesn't actually matter what mode we use here, as we're
10241 only going to use this for printing. */
10246 {
10247 rtx x;
10254 {
10259 {
10263 /* Emit hints only in the case default branch prediction
10264 heuristics would fail. */
10266 {
10267 /* We use 3e (DS) prefix for taken branches and
10268 2e (CS) prefix for not taken branches. */
10271 else
10273 }
10274 }
10275 }
10277 }
10281 {
10330 }
10334 #if TARGET_MACHO
10336 #else
10338 #endif
10343 }
10344 }
10350 {
10351 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
10354 {
10357 {
10366 else
10371 }
10373 /* Check for explicit size override (codes 'b', 'w' and 'k') */
10383 }
10386 /* Avoid (%rip) for call operands. */
10392 else
10394 }
10397 {
10398 REAL_VALUE_TYPE r;
10407 }
10409 /* These float cases don't actually occur as immediate operands. */
10411 {
10416 }
10420 {
10425 }
10427 else
10428 {
10429 /* We have patterns that allow zero sets of memory, for instance.
10430 In 64-bit mode, we should probably support all 8-byte vectors,
10431 since we can in fact encode that into an immediate. */
10433 {
10436 }
10439 {
10441 {
10444 }
10447 {
10450 else
10452 }
10453 }
10458 else
10460 }
10461 }
10462 \f
10463 /* Print a memory operand whose address is ADDR. */
10465 void
10467 {
10481 {
10492 }
10494 /* Use one byte shorter RIP relative addressing for 64bit mode. */
10496 {
10508 }
10510 {
10511 /* Displacement only requires special attention. */
10514 {
10518 }
10521 else
10523 }
10524 else
10525 {
10527 {
10529 {
10534 else
10536 }
10542 {
10547 }
10549 }
10550 else
10551 {
10555 {
10556 /* Pull out the offset of a symbol; print any symbol itself. */
10560 {
10564 }
10572 else
10574 }
10578 {
10581 {
10585 }
10586 }
10589 else
10593 {
10598 }
10600 }
10601 }
10602 }
10604 bool
10606 {
10607 rtx op;
10614 {
10617 /* FIXME: This might be @TPOFF in Sun ld. */
10628 else
10640 else
10650 }
10653 }
10654 \f
10655 /* Split one or more DImode RTL references into pairs of SImode
10656 references. The RTL can be REG, offsettable MEM, integer constant, or
10657 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
10658 split and "num" is its length. lo_half and hi_half are output arrays
10659 that parallel "operands". */
10661 void
10663 {
10665 {
10668 /* simplify_subreg refuse to split volatile memory addresses,
10669 but we still have to handle it. */
10671 {
10674 }
10675 else
10676 {
10683 }
10684 }
10685 }
10686 /* Split one or more TImode RTL references into pairs of DImode
10687 references. The RTL can be REG, offsettable MEM, integer constant, or
10688 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
10689 split and "num" is its length. lo_half and hi_half are output arrays
10690 that parallel "operands". */
10692 void
10694 {
10696 {
10699 /* simplify_subreg refuse to split volatile memory addresses, but we
10700 still have to handle it. */
10702 {
10705 }
10706 else
10707 {
10710 }
10711 }
10712 }
10713 \f
10714 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
10715 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
10716 is the expression of the binary operation. The output may either be
10717 emitted here, or returned to the caller, like all output_* functions.
10719 There is no guarantee that the operands are the same mode, as they
10720 might be within FLOAT or FLOAT_EXTEND expressions. */
10722 #ifndef SYSV386_COMPAT
10723 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
10724 wants to fix the assemblers because that causes incompatibility
10725 with gcc. No-one wants to fix gcc because that causes
10726 incompatibility with assemblers... You can use the option of
10727 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
10728 #define SYSV386_COMPAT 1
10729 #endif
10733 {
10739 #ifdef ENABLE_CHECKING
10740 /* Even if we do not want to check the inputs, this documents input
10741 constraints. Which helps in understanding the following code. */
10751 else
10753 #endif
10756 {
10761 else
10770 else
10779 else
10788 else
10795 }
10798 {
10802 else
10805 }
10809 {
10813 {
10817 }
10819 /* know operands[0] == operands[1]. */
10822 {
10825 }
10828 {
10830 /* How is it that we are storing to a dead operand[2]?
10831 Well, presumably operands[1] is dead too. We can't
10832 store the result to st(0) as st(0) gets popped on this
10833 instruction. Instead store to operands[2] (which I
10834 think has to be st(1)). st(1) will be popped later.
10835 gcc <= 2.8.1 didn't have this check and generated
10836 assembly code that the Unixware assembler rejected. */
10838 else
10841 }
10845 else
10852 {
10855 }
10858 {
10861 }
10864 {
10865 #if SYSV386_COMPAT
10866 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
10867 derived assemblers, confusingly reverse the direction of
10868 the operation for fsub{r} and fdiv{r} when the
10869 destination register is not st(0). The Intel assembler
10870 doesn't have this brain damage. Read !SYSV386_COMPAT to
10871 figure out what the hardware really does. */
10874 else
10876 #else
10878 /* As above for fmul/fadd, we can't store to st(0). */
10880 else
10882 #endif
10884 }
10887 {
10888 #if SYSV386_COMPAT
10891 else
10893 #else
10896 else
10898 #endif
10900 }
10903 {
10906 else
10909 }
10911 {
10912 #if SYSV386_COMPAT
10914 #else
10916 #endif
10917 }
10918 else
10919 {
10920 #if SYSV386_COMPAT
10922 #else
10924 #endif
10925 }
10930 }
10934 }
10936 /* Return needed mode for entity in optimize_mode_switching pass. */
10938 int
10940 {
10943 /* The mode UNINITIALIZED is used to store control word after a
10944 function call or ASM pattern. The mode ANY specify that function
10945 has no requirements on the control word and make no changes in the
10946 bits we are interested in. */
10960 {
10983 }
10986 }
10988 /* Output code to initialize control word copies used by trunc?f?i and
10989 rounding patterns. CURRENT_MODE is set to current control word,
10990 while NEW_MODE is set to new control word. */
10992 void
10994 {
10996 rtx new_mode;
11006 {
11008 {
11010 /* round toward zero (truncate) */
11016 /* round down toward -oo */
11023 /* round up toward +oo */
11030 /* mask precision exception for nearbyint() */
11037 }
11038 }
11039 else
11040 {
11042 {
11044 /* round toward zero (truncate) */
11050 /* round down toward -oo */
11056 /* round up toward +oo */
11062 /* mask precision exception for nearbyint() */
11069 }
11070 }
11076 }
11078 /* Output code for INSN to convert a float to a signed int. OPERANDS
11079 are the insn operands. The output may be [HSD]Imode and the input
11080 operand may be [SDX]Fmode. */
11084 {
11089 /* Jump through a hoop or two for DImode, since the hardware has no
11090 non-popping instruction. We used to do this a different way, but
11091 that was somewhat fragile and broke with post-reload splitters. */
11101 else
11102 {
11107 else
11111 }
11114 }
11116 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11117 have the values zero or one, indicates the ffreep insn's operand
11118 from the OPERANDS array. */
11122 {
11124 #if HAVE_AS_IX86_FFREEP
11126 #else
11127 {
11135 }
11136 #endif
11139 }
11142 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11143 should be used. UNORDERED_P is true when fucom should be used. */
11147 {
11153 {
11156 }
11157 else
11158 {
11161 }
11164 {
11168 else
11170 else
11173 else
11175 }
11182 {
11184 {
11187 }
11188 else
11190 }
11193 && stack_top_dies
11196 {
11197 /* If both the top of the 387 stack dies, and the other operand
11198 is also a stack register that dies, then this must be a
11199 `fcompp' float compare */
11202 {
11203 /* There is no double popping fcomi variant. Fortunately,
11204 eflags is immune from the fstp's cc clobbering. */
11207 else
11210 }
11211 else
11212 {
11215 else
11217 }
11218 }
11219 else
11220 {
11221 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
11224 {
11232 NULL,
11233 NULL,
11240 NULL,
11241 NULL,
11242 NULL,
11243 NULL
11244 };
11259 }
11260 }
11262 void
11264 {
11267 #ifdef ASM_QUAD
11270 #else
11272 #endif
11275 }
11277 void
11279 {
11282 #ifdef ASM_QUAD
11285 #else
11287 #endif
11288 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
11294 #if TARGET_MACHO
11296 {
11300 }
11301 #endif
11302 else
11305 }
11306 \f
11307 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
11308 for the target. */
11310 void
11312 {
11313 rtx tmp;
11315 /* We play register width games, which are only valid after reload. */
11318 /* Avoid HImode and its attendant prefix byte. */
11323 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
11325 {
11328 }
11331 }
11333 /* X is an unchanging MEM. If it is a constant pool reference, return
11334 the constant pool rtx, else NULL. */
11336 rtx
11338 {
11345 }
11347 void
11349 {
11357 {
11360 {
11365 }
11369 }
11373 {
11386 {
11392 }
11393 }
11396 {
11398 {
11399 #if TARGET_MACHO
11401 {
11402 rtx temp = ((reload_in_progress
11409 }
11414 #endif
11415 }
11416 else
11417 {
11421 {
11426 }
11427 }
11428 }
11429 else
11430 {
11441 /* Force large constants in 64bit compilation into register
11442 to get them CSEed. */
11454 {
11455 /* If we are loading a floating point constant to a register,
11456 force the value to memory now, since we'll get better code
11457 out the back end. */
11461 {
11466 }
11467 }
11468 }
11471 }
11473 void
11475 {
11479 /* Force constants other than zero into memory. We do not know how
11480 the instructions used to build constants modify the upper 64 bits
11481 of the register, once we have that information we may be able
11482 to handle some of them more efficiently. */
11491 /* We need to check memory alignment for SSE mode since attribute
11492 can make operands unaligned. */
11497 {
11500 /* ix86_expand_vector_move_misalign() does not like constants ... */
11506 /* ... nor both arguments in memory. */
11514 }
11516 /* Make operand1 a register if it isn't already. */
11520 {
11523 }
11526 }
11528 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
11529 straight to ix86_expand_vector_move. */
11530 /* Code generation for scalar reg-reg moves of single and double precision data:
11531 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
11532 movaps reg, reg
11533 else
11534 movss reg, reg
11535 if (x86_sse_partial_reg_dependency == true)
11536 movapd reg, reg
11537 else
11538 movsd reg, reg
11540 Code generation for scalar loads of double precision data:
11541 if (x86_sse_split_regs == true)
11542 movlpd mem, reg (gas syntax)
11543 else
11544 movsd mem, reg
11546 Code generation for unaligned packed loads of single precision data
11547 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
11548 if (x86_sse_unaligned_move_optimal)
11549 movups mem, reg
11551 if (x86_sse_partial_reg_dependency == true)
11552 {
11553 xorps reg, reg
11554 movlps mem, reg
11555 movhps mem+8, reg
11556 }
11557 else
11558 {
11559 movlps mem, reg
11560 movhps mem+8, reg
11561 }
11563 Code generation for unaligned packed loads of double precision data
11564 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
11565 if (x86_sse_unaligned_move_optimal)
11566 movupd mem, reg
11568 if (x86_sse_split_regs == true)
11569 {
11570 movlpd mem, reg
11571 movhpd mem+8, reg
11572 }
11573 else
11574 {
11575 movsd mem, reg
11576 movhpd mem+8, reg
11577 }
11578 */
11580 void
11582 {
11589 {
11590 /* If we're optimizing for size, movups is the smallest. */
11592 {
11597 }
11599 /* ??? If we have typed data, then it would appear that using
11600 movdqu is the only way to get unaligned data loaded with
11601 integer type. */
11603 {
11608 }
11611 {
11612 rtx zero;
11615 {
11620 }
11622 /* When SSE registers are split into halves, we can avoid
11623 writing to the top half twice. */
11625 {
11628 }
11629 else
11630 {
11631 /* ??? Not sure about the best option for the Intel chips.
11632 The following would seem to satisfy; the register is
11633 entirely cleared, breaking the dependency chain. We
11634 then store to the upper half, with a dependency depth
11635 of one. A rumor has it that Intel recommends two movsd
11636 followed by an unpacklpd, but this is unconfirmed. And
11637 given that the dependency depth of the unpacklpd would
11638 still be one, I'm not sure why this would be better. */
11640 }
11646 }
11647 else
11648 {
11650 {
11655 }
11659 else
11668 }
11669 }
11671 {
11672 /* If we're optimizing for size, movups is the smallest. */
11674 {
11679 }
11681 /* ??? Similar to above, only less clear because of quote
11682 typeless stores unquote. */
11685 {
11690 }
11693 {
11698 }
11699 else
11700 {
11707 }
11708 }
11709 else
11711 }
11713 /* Expand a push in MODE. This is some mode for which we do not support
11714 proper push instructions, at least from the registers that we expect
11715 the value to live in. */
11717 void
11719 {
11720 rtx tmp;
11730 }
11732 /* Helper function of ix86_fixup_binary_operands to canonicalize
11733 operand order. Returns true if the operands should be swapped. */
11735 static bool
11737 rtx operands[])
11738 {
11743 /* If the operation is not commutative, we can't do anything. */
11747 /* Highest priority is that src1 should match dst. */
11753 /* Next highest priority is that immediate constants come second. */
11759 /* Lowest priority is that memory references should come second. */
11766 }
11769 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
11770 destination to use for the operation. If different from the true
11771 destination in operands[0], a copy operation will be required. */
11773 rtx
11775 rtx operands[])
11776 {
11781 /* Canonicalize operand order. */
11783 {
11784 rtx temp;
11786 /* It is invalid to swap operands of different modes. */
11792 }
11794 /* Both source operands cannot be in memory. */
11796 {
11797 /* Optimization: Only read from memory once. */
11799 {
11802 }
11803 else
11805 }
11807 /* If the destination is memory, and we do not have matching source
11808 operands, do things in registers. */
11812 /* Source 1 cannot be a constant. */
11816 /* Source 1 cannot be a non-matching memory. */
11823 }
11825 /* Similarly, but assume that the destination has already been
11826 set up properly. */
11828 void
11831 {
11834 }
11836 /* Attempt to expand a binary operator. Make the expansion closer to the
11837 actual machine, then just general_operand, which will allow 3 separate
11838 memory references (one output, two input) in a single insn. */
11840 void
11842 rtx operands[])
11843 {
11850 /* Emit the instruction. */
11854 {
11855 /* Reload doesn't know about the flags register, and doesn't know that
11856 it doesn't want to clobber it. We can only do this with PLUS. */
11859 }
11860 else
11861 {
11864 }
11866 /* Fix up the destination if needed. */
11869 }
11871 /* Return TRUE or FALSE depending on whether the binary operator meets the
11872 appropriate constraints. */
11874 int
11877 {
11882 /* Both source operands cannot be in memory. */
11886 /* Canonicalize operand order for commutative operators. */
11888 {
11892 }
11894 /* If the destination is memory, we must have a matching source operand. */
11898 /* Source 1 cannot be a constant. */
11902 /* Source 1 cannot be a non-matching memory. */
11907 }
11909 /* Attempt to expand a unary operator. Make the expansion closer to the
11910 actual machine, then just general_operand, which will allow 2 separate
11911 memory references (one output, one input) in a single insn. */
11913 void
11915 rtx operands[])
11916 {
11923 /* If the destination is memory, and we do not have matching source
11924 operands, do things in registers. */
11927 {
11930 else
11932 }
11934 /* When source operand is memory, destination must match. */
11938 /* Emit the instruction. */
11942 {
11943 /* Reload doesn't know about the flags register, and doesn't know that
11944 it doesn't want to clobber it. */
11947 }
11948 else
11949 {
11952 }
11954 /* Fix up the destination if needed. */
11957 }
11959 /* Return TRUE or FALSE depending on whether the unary operator meets the
11960 appropriate constraints. */
11962 int
11966 {
11967 /* If one of operands is memory, source and destination must match. */
11973 }
11975 /* Post-reload splitter for converting an SF or DFmode value in an
11976 SSE register into an unsigned SImode. */
11978 void
11980 {
11991 /* Load up the value into the low element. We must ensure that the other
11992 elements are valid floats -- zero is the easiest such value. */
11994 {
11997 else
11999 }
12000 else
12001 {
12006 else
12008 }
12028 else
12033 }
12035 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12036 Expects the 64-bit DImode to be supplied in a pair of integral
12037 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12038 -mfpmath=sse, !optimize_size only. */
12040 void
12042 {
12046 rtx x;
12052 {
12055 }
12056 else
12057 {
12061 }
12069 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12072 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12073 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12074 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12075 (0x1.0p84 + double(fp_value_hi_xmm)).
12076 Note these exponents differ by 32. */
12080 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12081 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12090 /* Add the upper and lower DFmode values together. */
12093 else
12094 {
12098 }
12101 }
12103 /* Not used, but eases macroization of patterns. */
12104 void
12106 rtx input ATTRIBUTE_UNUSED)
12107 {
12109 }
12111 /* Convert an unsigned SImode value into a DFmode. Only currently used
12112 for SSE, but applicable anywhere. */
12114 void
12116 {
12117 REAL_VALUE_TYPE TWO31r;
12132 }
12134 /* Convert a signed DImode value into a DFmode. Only used for SSE in
12135 32-bit mode; otherwise we have a direct convert instruction. */
12137 void
12139 {
12140 REAL_VALUE_TYPE TWO32r;
12158 }
12160 /* Convert an unsigned SImode value into a SFmode, using only SSE.
12161 For x86_32, -mfpmath=sse, !optimize_size only. */
12162 void
12164 {
12165 REAL_VALUE_TYPE ONE16r;
12184 }
12186 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
12187 then replicate the value for all elements of the vector
12188 register. */
12190 rtx
12192 {
12193 rtvec v;
12195 {
12209 else
12217 else
12223 }
12224 }
12226 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
12227 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
12228 for an SSE register. If VECT is true, then replicate the mask for
12229 all elements of the vector register. If INVERT is true, then create
12230 a mask excluding the sign bit. */
12232 rtx
12234 {
12238 rtx v;
12239 rtx mask;
12241 /* Find the sign bit, sign extended to 2*HWI. */
12243 {
12257 else
12265 {
12268 }
12269 else
12270 {
12271 rtvec vec;
12277 {
12280 }
12281 else
12291 }
12296 }
12301 /* Force this value into the low part of a fp vector constant. */
12310 }
12312 /* Generate code for floating point ABS or NEG. */
12314 void
12316 rtx operands[])
12317 {
12324 {
12327 }
12333 /* NEG and ABS performed with SSE use bitwise mask operations.
12334 Create the appropriate mask now. */
12337 else
12344 {
12348 }
12349 else
12350 {
12354 {
12359 }
12360 else
12362 }
12363 }
12365 /* Expand a copysign operation. Special case operand 0 being a constant. */
12367 void
12369 {
12380 {
12387 {
12394 else
12395 {
12396 rtvec v;
12401 else
12405 }
12406 }
12416 else
12420 }
12421 else
12422 {
12432 else
12436 }
12437 }
12439 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
12440 be a constant, and so has already been expanded into a vector constant. */
12442 void
12444 {
12461 {
12464 }
12465 }
12467 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
12468 so we have to do two masks. */
12470 void
12472 {
12487 {
12488 /* Shouldn't happen often (it's useless, obviously), but when it does
12489 we'd generate incorrect code if we continue below. */
12492 }
12495 {
12506 }
12507 else
12508 {
12510 {
12512 }
12514 {
12518 }
12522 {
12525 }
12527 {
12532 }
12534 }
12538 }
12540 /* Return TRUE or FALSE depending on whether the first SET in INSN
12541 has source and destination with matching CC modes, and that the
12542 CC mode is at least as constrained as REQ_MODE. */
12544 int
12546 {
12547 rtx set;
12558 {
12568 /* FALLTHRU */
12572 /* FALLTHRU */
12576 /* FALLTHRU */
12582 }
12585 }
12587 /* Generate insn patterns to do an integer compare of OPERANDS. */
12589 static rtx
12591 {
12598 /* This is very simple, but making the interface the same as in the
12599 FP case makes the rest of the code easier. */
12603 /* Return the test that should be put into the flags user, i.e.
12604 the bcc, scc, or cmov instruction. */
12606 }
12608 /* Figure out whether to use ordered or unordered fp comparisons.
12609 Return the appropriate mode to use. */
12611 enum machine_mode
12613 {
12614 /* ??? In order to make all comparisons reversible, we do all comparisons
12615 non-trapping when compiling for IEEE. Once gcc is able to distinguish
12616 all forms trapping and nontrapping comparisons, we can make inequality
12617 comparisons trapping again, since it results in better code when using
12618 FCOM based compares. */
12620 }
12622 enum machine_mode
12624 {
12628 {
12631 }
12634 {
12635 /* Only zero flag is needed. */
12639 /* Codes needing carry flag. */
12642 /* Detect overflow checks. They need just the carry flag. */
12646 else
12650 /* Detect overflow checks. They need just the carry flag. */
12654 else
12656 /* Codes possibly doable only with sign flag when
12657 comparing against zero. */
12662 else
12663 /* For other cases Carry flag is not required. */
12665 /* Codes doable only with sign flag when comparing
12666 against zero, but we miss jump instruction for it
12667 so we need to use relational tests against overflow
12668 that thus needs to be zero. */
12673 else
12675 /* strcmp pattern do (use flags) and combine may ask us for proper
12676 mode. */
12681 }
12682 }
12684 /* Return the fixed registers used for condition codes. */
12686 static bool
12688 {
12692 }
12694 /* If two condition code modes are compatible, return a condition code
12695 mode which is compatible with both. Otherwise, return
12696 VOIDmode. */
12698 static enum machine_mode
12700 {
12712 {
12726 {
12740 }
12744 /* These are only compatible with themselves, which we already
12745 checked above. */
12747 }
12748 }
12750 /* Split comparison code CODE into comparisons we can do using branch
12751 instructions. BYPASS_CODE is comparison code for branch that will
12752 branch around FIRST_CODE and SECOND_CODE. If some of branches
12753 is not required, set value to UNKNOWN.
12754 We never require more than two branches. */
12756 void
12760 {
12765 /* The fcomi comparison sets flags as follows:
12767 cmp ZF PF CF
12768 > 0 0 0
12769 < 0 0 1
12770 = 1 0 0
12771 un 1 1 1 */
12774 {
12810 }
12812 {
12815 }
12816 }
12818 /* Return cost of comparison done fcom + arithmetics operations on AX.
12819 All following functions do use number of instructions as a cost metrics.
12820 In future this should be tweaked to compute bytes for optimize_size and
12821 take into account performance of various instructions on various CPUs. */
12822 static int
12824 {
12827 /* The cost of code output by ix86_expand_fp_compare. */
12829 {
12852 }
12853 }
12855 /* Return cost of comparison done using fcomi operation.
12856 See ix86_fp_comparison_arithmetics_cost for the metrics. */
12857 static int
12859 {
12861 /* Return arbitrarily high cost when instruction is not supported - this
12862 prevents gcc from using it. */
12867 }
12869 /* Return cost of comparison done using sahf operation.
12870 See ix86_fp_comparison_arithmetics_cost for the metrics. */
12871 static int
12873 {
12875 /* Return arbitrarily high cost when instruction is not preferred - this
12876 avoids gcc from using it. */
12881 }
12883 /* Compute cost of the comparison done using any method.
12884 See ix86_fp_comparison_arithmetics_cost for the metrics. */
12885 static int
12887 {
12900 }
12902 /* Return true if we should use an FCOMI instruction for this
12903 fp comparison. */
12905 int
12907 {
12914 }
12916 /* Swap, force into registers, or otherwise massage the two operands
12917 to a fp comparison. The operands are updated in place; the new
12918 comparison code is returned. */
12920 static enum rtx_code
12922 {
12928 /* All of the unordered compare instructions only work on registers.
12929 The same is true of the fcomi compare instructions. The XFmode
12930 compare instructions require registers except when comparing
12931 against zero or when converting operand 1 from fixed point to
12932 floating point. */
12941 {
12944 }
12945 else
12946 {
12947 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
12948 things around if they appear profitable, otherwise force op0
12949 into a register. */
12955 {
12956 rtx tmp;
12959 }
12965 {
12970 {
12973 }
12974 else
12976 }
12977 }
12979 /* Try to rearrange the comparison to make it cheaper. */
12983 {
12984 rtx tmp;
12989 }
12994 }
12996 /* Convert comparison codes we use to represent FP comparison to integer
12997 code that will result in proper branch. Return UNKNOWN if no such code
12998 is available. */
13000 enum rtx_code
13002 {
13004 {
13027 }
13028 }
13030 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13032 static rtx
13035 {
13051 /* Do fcomi/sahf based test when profitable. */
13055 {
13058 tmp);
13061 else
13062 {
13070 }
13072 /* The FP codes work out to act like unsigned. */
13078 const0_rtx);
13082 const0_rtx);
13083 }
13084 else
13085 {
13086 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13093 /* In the unordered case, we have to check C2 for NaN's, which
13094 doesn't happen to work out to anything nice combination-wise.
13095 So do some bit twiddling on the value we've got in AH to come
13096 up with an appropriate set of condition codes. */
13100 {
13104 {
13107 }
13108 else
13109 {
13115 }
13120 {
13125 }
13126 else
13127 {
13130 }
13135 {
13138 }
13139 else
13140 {
13145 }
13150 {
13156 }
13157 else
13158 {
13161 }
13166 {
13171 }
13172 else
13173 {
13177 }
13182 {
13187 }
13188 else
13189 {
13192 }
13206 }
13207 }
13209 /* Return the test that should be put into the flags user, i.e.
13210 the bcc, scc, or cmov instruction. */
13213 const0_rtx);
13214 }
13216 rtx
13218 {
13229 {
13232 }
13234 {
13238 }
13239 else
13243 }
13245 /* Return true if the CODE will result in nontrivial jump sequence. */
13246 bool
13248 {
13254 }
13256 void
13258 {
13259 rtx tmp;
13261 /* If we have emitted a compare insn, go straight to simple.
13262 ix86_expand_compare won't emit anything if ix86_compare_emitted
13263 is non NULL. */
13268 {
13272 simple:
13276 pc_rtx);
13283 {
13284 rtvec vec;
13293 /* Check whether we will use the natural sequence with one jump. If
13294 so, we can expand jump early. Otherwise delay expansion by
13295 creating compound insn to not confuse optimizers. */
13297 {
13301 }
13302 else
13303 {
13308 pc_rtx);
13323 }
13325 }
13331 /* Expand DImode branch into multiple compare+branch. */
13332 {
13338 {
13343 }
13345 {
13349 }
13350 else
13351 {
13355 }
13357 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
13358 avoid two branches. This costs one extra insn, so disable when
13359 optimizing for size. */
13362 && (!optimize_size
13364 {
13384 }
13386 /* Otherwise, if we are doing less-than or greater-or-equal-than,
13387 op1 is a constant and the low word is zero, then we can just
13388 examine the high word. Similarly for low word -1 and
13389 less-or-equal-than or greater-than. */
13393 {
13396 {
13401 }
13405 {
13410 }
13414 }
13416 /* Otherwise, we need two or three jumps. */
13425 {
13439 }
13441 /*
13442 * a < b =>
13443 * if (hi(a) < hi(b)) goto true;
13444 * if (hi(a) > hi(b)) goto false;
13445 * if (lo(a) < lo(b)) goto true;
13446 * false:
13447 */
13464 }
13468 }
13469 }
13471 /* Split branch based on floating point condition. */
13472 void
13475 {
13478 rtx condition;
13480 rtx i;
13483 {
13488 }
13493 /* Remove pushed operand from stack. */
13498 {
13499 /* Distribute the probabilities across the jumps.
13500 Assume the BYPASS and SECOND to be always test
13501 for UNORDERED. */
13504 /* Value of 1 is low enough to make no need for probability
13505 to be updated. Later we may run some experiments and see
13506 if unordered values are more frequent in practice. */
13511 }
13513 {
13518 bypass,
13520 label),
13521 pc_rtx)));
13527 }
13538 {
13542 target2)));
13548 }
13551 }
13553 int
13555 {
13572 {
13577 {
13582 }
13588 else
13590 }
13592 /* Attach a REG_EQUAL note describing the comparison result. */
13594 {
13599 }
13602 }
13604 /* Expand comparison setting or clearing carry flag. Return true when
13605 successful and set pop for the operation. */
13606 static bool
13608 {
13612 /* Do not handle DImode compares that go through special path. */
13617 {
13623 /* Shortcut: following common codes never translate
13624 into carry flag compares. */
13629 /* These comparisons require zero flag; swap operands so they won't. */
13632 {
13637 }
13639 /* Try to expand the comparison and verify that we end up with
13640 carry flag based comparison. This fails to be true only when
13641 we decide to expand comparison using arithmetic that is not
13642 too common scenario. */
13655 else
13664 }
13670 {
13675 /* Convert a==0 into (unsigned)a<1. */
13684 /* Convert a>b into b<a or a>=b-1. */
13688 {
13690 /* Bail out on overflow. We still can swap operands but that
13691 would force loading of the constant into register. */
13696 }
13697 else
13698 {
13703 }
13706 /* Convert a>=0 into (unsigned)a<0x80000000. */
13724 }
13725 /* Swapping operands may cause constant to appear as first operand. */
13727 {
13731 }
13737 }
13739 int
13741 {
13759 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
13760 HImode insns, we'd be swallowed in word prefix ops. */
13766 {
13770 HOST_WIDE_INT diff;
13773 /* Sign bit compares are better done using shifts than we do by using
13774 sbb. */
13778 {
13779 /* Detect overlap between destination and compare sources. */
13783 {
13790 {
13793 }
13795 /* To simplify rest of code, restrict to the GEU case. */
13797 {
13803 }
13804 else
13805 {
13808 reverse_condition_maybe_unordered
13810 else
13812 }
13821 else
13823 }
13824 else
13825 {
13828 else
13829 {
13834 }
13837 }
13840 {
13841 /*
13842 * cmpl op0,op1
13843 * sbbl dest,dest
13844 * [addl dest, ct]
13845 *
13846 * Size 5 - 8.
13847 */
13852 }
13854 {
13855 /*
13856 * cmpl op0,op1
13857 * sbbl dest,dest
13858 * orl $ct, dest
13859 *
13860 * Size 8.
13861 */
13865 }
13867 {
13868 /*
13869 * cmpl op0,op1
13870 * sbbl dest,dest
13871 * notl dest
13872 * [addl dest, cf]
13873 *
13874 * Size 8 - 11.
13875 */
13881 }
13882 else
13883 {
13884 /*
13885 * cmpl op0,op1
13886 * sbbl dest,dest
13887 * [notl dest]
13888 * andl cf - ct, dest
13889 * [addl dest, ct]
13890 *
13891 * Size 8 - 11.
13892 */
13895 {
13899 }
13909 }
13915 }
13918 {
13921 HOST_WIDE_INT tmp;
13926 {
13929 /* We may be reversing unordered compare to normal compare, that
13930 is not valid in general (we may convert non-trapping condition
13931 to trapping one), however on i386 we currently emit all
13932 comparisons unordered. */
13935 }
13936 else
13937 {
13940 }
13941 }
13946 {
13951 {
13956 }
13957 }
13959 /* Optimize dest = (op0 < 0) ? -1 : cf. */
13963 {
13964 /* If lea code below could be used, only optimize
13965 if it results in a 2 insn sequence. */
13971 {
13972 /*
13973 * notl op1 (if necessary)
13974 * sarl $31, op1
13975 * orl cf, op1
13976 */
13978 {
13982 }
13994 }
13995 }
14003 {
14004 /*
14005 * xorl dest,dest
14006 * cmpl op1,op2
14007 * setcc dest
14008 * lea cf(dest*(ct-cf)),dest
14009 *
14010 * Size 14.
14011 *
14012 * This also catches the degenerate setcc-only case.
14013 */
14015 rtx tmp;
14022 /* On x86_64 the lea instruction operates on Pmode, so we need
14023 to get arithmetics done in proper mode to match. */
14026 else
14027 {
14028 rtx out1;
14031 nops++;
14033 {
14035 nops++;
14036 }
14037 }
14039 {
14041 nops++;
14042 }
14044 {
14047 else
14049 }
14054 }
14056 /*
14057 * General case: Jumpful:
14058 * xorl dest,dest cmpl op1, op2
14059 * cmpl op1, op2 movl ct, dest
14060 * setcc dest jcc 1f
14061 * decl dest movl cf, dest
14062 * andl (cf-ct),dest 1:
14063 * addl ct,dest
14064 *
14065 * Size 20. Size 14.
14066 *
14067 * This is reasonably steep, but branch mispredict costs are
14068 * high on modern cpus, so consider failing only if optimizing
14069 * for space.
14070 */
14074 {
14076 {
14083 {
14086 /* We may be reversing unordered compare to normal compare,
14087 that is not valid in general (we may convert non-trapping
14088 condition to trapping one), however on i386 we currently
14089 emit all comparisons unordered. */
14091 }
14092 else
14093 {
14097 }
14098 }
14101 {
14102 /* notl op1 (if needed)
14103 sarl $31, op1
14104 andl (cf-ct), op1
14105 addl ct, op1
14107 For x < 0 (resp. x <= -1) there will be no notl,
14108 so if possible swap the constants to get rid of the
14109 complement.
14110 True/false will be -1/0 while code below (store flag
14111 followed by decrement) is 0/-1, so the constants need
14112 to be exchanged once more. */
14115 {
14118 }
14119 else
14120 {
14124 }
14128 }
14129 else
14130 {
14136 }
14148 }
14149 }
14152 {
14153 /* Try a few things more with specific constants and a variable. */
14155 optab op;
14161 /* If one of the two operands is an interesting constant, load a
14162 constant with the above and mask it in with a logical operation. */
14165 {
14171 else
14173 }
14175 {
14181 else
14183 }
14184 else
14191 /* Recurse to get the constant loaded. */
14195 /* Mask in the interesting variable. */
14197 OPTAB_WIDEN);
14202 }
14204 /*
14205 * For comparison with above,
14206 *
14207 * movl cf,dest
14208 * movl ct,tmp
14209 * cmpl op1,op2
14210 * cmovcc tmp,dest
14211 *
14212 * Size 15.
14213 */
14221 {
14225 }
14227 {
14231 }
14250 bypass_test,
14256 second_test,
14261 }
14263 /* Swap, force into registers, or otherwise massage the two operands
14264 to an sse comparison with a mask result. Thus we differ a bit from
14265 ix86_prepare_fp_compare_args which expects to produce a flags result.
14267 The DEST operand exists to help determine whether to commute commutative
14268 operators. The POP0/POP1 operands are updated in place. The new
14269 comparison code is returned, or UNKNOWN if not implementable. */
14271 static enum rtx_code
14274 {
14275 rtx tmp;
14278 {
14281 /* We have no LTGT as an operator. We could implement it with
14282 NE & ORDERED, but this requires an extra temporary. It's
14283 not clear that it's worth it. */
14290 /* These are supported directly. */
14297 /* For commutative operators, try to canonicalize the destination
14298 operand to be first in the comparison - this helps reload to
14299 avoid extra moves. */
14302 /* FALLTHRU */
14308 /* These are not supported directly. Swap the comparison operands
14309 to transform into something that is supported. */
14318 }
14321 }
14323 /* Detect conditional moves that exactly match min/max operational
14324 semantics. Note that this is IEEE safe, as long as we don't
14325 interchange the operands.
14327 Returns FALSE if this conditional move doesn't match a MIN/MAX,
14328 and TRUE if the operation is successful and instructions are emitted. */
14330 static bool
14333 {
14336 rtx tmp;
14339 ;
14341 {
14345 }
14346 else
14353 else
14358 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
14359 but MODE may be a vector mode and thus not appropriate. */
14361 {
14363 rtvec v;
14368 }
14369 else
14370 {
14373 }
14377 }
14379 /* Expand an sse vector comparison. Return the register with the result. */
14381 static rtx
14384 {
14386 rtx x;
14401 }
14403 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
14404 operations. This is used for both scalar and vector conditional moves. */
14406 static void
14408 {
14413 {
14417 }
14419 {
14424 }
14426 {
14429 op_true,
14430 op_false));
14432 }
14433 else
14434 {
14441 else
14453 }
14454 }
14456 /* Expand a floating-point conditional move. Return true if successful. */
14458 int
14460 {
14466 {
14469 /* Since we've no cmove for sse registers, don't force bad register
14470 allocation just to gain access to it. Deny movcc when the
14471 comparison mode doesn't match the move mode. */
14493 }
14495 /* The floating point conditional move instructions don't directly
14496 support conditions resulting from a signed integer comparison. */
14500 /* The floating point conditional move instructions don't directly
14501 support signed integer comparisons. */
14504 {
14512 }
14514 {
14518 }
14520 {
14524 }
14539 }
14541 /* Expand a floating-point vector conditional move; a vcond operation
14542 rather than a movcc operation. */
14544 bool
14546 {
14548 rtx cmp;
14563 }
14565 /* Expand a signed/unsigned integral vector conditional move. */
14567 bool
14569 {
14578 /* SSE5 supports all of the comparisons on all vector int types. */
14580 {
14581 /* Canonicalize the comparison to EQ, GT, GTU. */
14583 {
14600 /* FALLTHRU */
14610 }
14612 /* Only SSE4.1/SSE4.2 supports V2DImode. */
14614 {
14616 {
14618 /* SSE4.1 supports EQ. */
14625 /* SSE4.2 supports GT/GTU. */
14632 }
14633 }
14635 /* Unsigned parallel compare is not supported by the hardware. Play some
14636 tricks to turn this into a signed comparison against 0. */
14638 {
14642 {
14645 {
14648 /* Perform a parallel modulo subtraction. */
14651 ? gen_subv4si3
14654 /* Extract the original sign bit of op0. */
14659 ? gen_andv4si3
14662 /* XOR it back into the result of the subtraction. This results
14663 in the sign bit set iff we saw unsigned underflow. */
14666 ? gen_xorv4si3
14670 }
14675 /* Perform a parallel unsigned saturating subtraction. */
14686 }
14690 }
14691 }
14699 }
14701 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
14702 true if we should do zero extension, else sign extension. HIGH_P is
14703 true if we want the N/2 high elements, else the low elements. */
14705 void
14707 {
14713 {
14717 else
14723 else
14729 else
14734 }
14740 else
14745 }
14747 /* This function performs the same task as ix86_expand_sse_unpack,
14748 but with SSE4.1 instructions. */
14750 void
14752 {
14758 {
14762 else
14768 else
14774 else
14779 }
14783 {
14784 /* Shift higher 8 bytes to lower 8 bytes. */
14789 }
14790 else
14794 }
14796 /* This function performs the same task as ix86_expand_sse_unpack,
14797 but with sse5 instructions. */
14799 void
14801 {
14809 rtvec vs;
14814 {
14819 {
14822 ? PPERM_ZERO
14824 }
14836 else
14844 {
14846 ? PPERM_ZERO
14852 }
14864 else
14872 {
14874 ? PPERM_ZERO
14884 }
14896 else
14902 }
14905 }
14907 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
14908 next narrower integer vector type */
14909 void
14911 {
14916 rtx x;
14922 {
14925 {
14928 }
14939 {
14944 }
14955 {
14964 }
14975 }
14978 }
14980 /* Expand conditional increment or decrement using adb/sbb instructions.
14981 The default case using setcc followed by the conditional move can be
14982 done by generic code. */
14983 int
14985 {
14987 rtx compare_op;
15002 {
15005 }
15008 {
15012 reverse_condition_maybe_unordered
15014 else
15016 }
15019 /* Construct either adc or sbb insn. */
15021 {
15023 {
15038 }
15039 }
15040 else
15041 {
15043 {
15058 }
15059 }
15061 }
15064 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15065 works for floating pointer parameters and nonoffsetable memories.
15066 For pushes, it returns just stack offsets; the values will be saved
15067 in the right order. Maximally three parts are generated. */
15069 static int
15071 {
15076 else
15082 /* Optimize constant pool reference to immediates. This is used by fp
15083 moves, that force all constants to memory to allow combining. */
15085 {
15089 }
15092 {
15093 /* The only non-offsetable memories we handle are pushes. */
15102 }
15105 {
15107 /* Caution: if we looked through a constant pool memory above,
15108 the operand may actually have a different mode now. That's
15109 ok, since we want to pun this all the way back to an integer. */
15113 }
15116 {
15119 else
15120 {
15124 {
15128 }
15130 {
15135 }
15137 {
15138 REAL_VALUE_TYPE r;
15143 {
15158 }
15161 }
15162 else
15164 }
15165 }
15166 else
15167 {
15171 {
15174 {
15178 }
15180 {
15184 }
15186 {
15187 REAL_VALUE_TYPE r;
15193 /* Do not use shift by 32 to avoid warning on 32bit systems. */
15196 = gen_int_mode
15199 DImode);
15200 else
15207 = gen_int_mode
15210 DImode);
15211 else
15213 }
15214 else
15216 }
15217 }
15220 }
15222 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
15223 Return false when normal moves are needed; true when all required
15224 insns have been emitted. Operands 2-4 contain the input values
15225 int the correct order; operands 5-7 contain the output values. */
15227 void
15229 {
15237 /* The DFmode expanders may ask us to move double.
15238 For 64bit target this is single move. By hiding the fact
15239 here we simplify i386.md splitters. */
15241 {
15242 /* Optimize constant pool reference to immediates. This is used by
15243 fp moves, that force all constants to memory to allow combining. */
15250 {
15253 }
15254 else
15259 }
15261 /* The only non-offsettable memory we handle is push. */
15264 else
15271 /* When emitting push, take care for source operands on the stack. */
15279 /* We need to do copy in the right order in case an address register
15280 of the source overlaps the destination. */
15282 {
15283 rtx tmp;
15286 {
15290 collisions++;
15291 }
15293 /* Collision in the middle part can be handled by reordering. */
15295 {
15298 }
15302 {
15304 {
15307 }
15308 else
15309 {
15312 }
15313 }
15315 /* If there are more collisions, we can't handle it by reordering.
15316 Do an lea to the last part and use only one colliding move. */
15318 {
15319 rtx base;
15325 /* Handle the case when the last part isn't valid for lea.
15326 Happens in 64-bit mode storing the 12-byte XFmode. */
15333 {
15336 }
15337 }
15338 }
15341 {
15343 {
15345 {
15349 }
15351 {
15354 }
15355 }
15356 else
15357 {
15358 /* In 64bit mode we don't have 32bit push available. In case this is
15359 register, it is OK - we will just use larger counterpart. We also
15360 retype memory - these comes from attempt to avoid REX prefix on
15361 moving of second half of TFmode value. */
15363 {
15365 {
15376 }
15380 }
15381 }
15385 }
15387 /* Choose correct order to not overwrite the source before it is copied. */
15397 {
15399 {
15402 }
15403 }
15404 else
15405 {
15407 {
15410 }
15411 }
15413 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
15415 {
15424 }
15430 }
15432 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
15433 left shift by a constant, either using a single shift or
15434 a sequence of add instructions. */
15436 static void
15438 {
15440 {
15442 ? gen_addsi3
15444 }
15447 {
15450 {
15452 ? gen_addsi3
15454 }
15455 }
15456 else
15458 ? gen_ashlsi3
15460 }
15462 void
15464 {
15470 {
15475 {
15481 }
15482 else
15483 {
15487 ? gen_x86_shld
15490 }
15492 }
15497 {
15498 /* Assuming we've chosen a QImode capable registers, then 1 << N
15499 can be done with two 32/64-bit shifts, no branches, no cmoves. */
15501 {
15517 }
15519 /* Otherwise, we can get the same results by manually performing
15520 a bit extract operation on bit 5/6, and then performing the two
15521 shifts. The two methods of getting 0/1 into low/high are exactly
15522 the same size. Avoiding the shift in the bit extract case helps
15523 pentium4 a bit; no one else seems to care much either way. */
15524 else
15525 {
15526 rtx x;
15530 else
15535 ? gen_lshrsi3
15538 ? gen_andsi3
15542 ? gen_xorsi3
15544 }
15547 ? gen_ashlsi3
15550 ? gen_ashlsi3
15553 }
15556 {
15557 /* For -1 << N, we can avoid the shld instruction, because we
15558 know that we're shifting 0...31/63 ones into a -1. */
15562 else
15564 }
15565 else
15566 {
15572 ? gen_x86_shld
15574 }
15579 {
15582 ? gen_x86_shift_adj_1
15584 scratch));
15585 }
15586 else
15588 ? gen_x86_shift_adj_2
15590 }
15592 void
15594 {
15600 {
15605 {
15608 ? gen_ashrsi3
15613 }
15615 {
15619 ? gen_ashrsi3
15624 ? gen_ashrsi3
15627 }
15628 else
15629 {
15633 ? gen_x86_shrd
15636 ? gen_ashrsi3
15638 }
15639 }
15640 else
15641 {
15648 ? gen_x86_shrd
15651 ? gen_ashrsi3
15655 {
15658 ? gen_ashrsi3
15662 ? gen_x86_shift_adj_1
15664 scratch));
15665 }
15666 else
15668 ? gen_x86_shift_adj_3
15670 }
15671 }
15673 void
15675 {
15681 {
15686 {
15692 ? gen_lshrsi3
15695 }
15696 else
15697 {
15701 ? gen_x86_shrd
15704 ? gen_lshrsi3
15706 }
15707 }
15708 else
15709 {
15716 ? gen_x86_shrd
15719 ? gen_lshrsi3
15722 /* Heh. By reversing the arguments, we can reuse this pattern. */
15724 {
15727 ? gen_x86_shift_adj_1
15729 scratch));
15730 }
15731 else
15733 ? gen_x86_shift_adj_2
15735 }
15736 }
15738 /* Predict just emitted jump instruction to be taken with probability PROB. */
15739 static void
15741 {
15748 }
15750 /* Helper function for the string operations below. Dest VARIABLE whether
15751 it is aligned to VALUE bytes. If true, jump to the label. */
15752 static rtx
15754 {
15759 else
15765 else
15768 }
15770 /* Adjust COUNTER by the VALUE. */
15771 static void
15773 {
15776 else
15778 }
15780 /* Zero extend possibly SImode EXP to Pmode register. */
15781 rtx
15783 {
15784 rtx r;
15792 }
15794 /* Divide COUNTREG by SCALE. */
15795 static rtx
15797 {
15798 rtx sc;
15799 rtx piece_size_mask;
15812 }
15814 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
15815 DImode for constant loop counts. */
15817 static enum machine_mode
15819 {
15827 }
15829 /* When SRCPTR is non-NULL, output simple loop to move memory
15830 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
15831 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
15832 equivalent loop to set memory by VALUE (supposed to be in MODE).
15834 The size is rounded down to whole number of chunk size moved at once.
15835 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
15838 static void
15843 {
15848 rtx size;
15849 rtx x_addr;
15850 rtx y_addr;
15859 /* Those two should combine. */
15861 {
15865 }
15875 {
15879 /* When unrolling for chips that reorder memory reads and writes,
15880 we can save registers by using single temporary.
15881 Also using 4 temporaries is overkill in 32bit mode. */
15883 {
15885 {
15887 {
15888 destmem =
15890 srcmem =
15892 }
15894 }
15895 }
15896 else
15897 {
15901 {
15904 {
15905 srcmem =
15907 }
15909 }
15911 {
15913 {
15914 destmem =
15916 }
15918 }
15919 }
15920 }
15921 else
15923 {
15925 destmem =
15928 }
15938 {
15944 else
15946 }
15947 else
15955 {
15960 }
15962 }
15964 /* Output "rep; mov" instruction.
15965 Arguments have same meaning as for previous function */
15966 static void
15969 rtx count,
15971 {
15972 rtx destexp;
15973 rtx srcexp;
15974 rtx countreg;
15976 /* If the size is known, it is shorter to use rep movs. */
15987 {
15994 }
15995 else
15996 {
15999 }
16002 }
16004 /* Output "rep; stos" instruction.
16005 Arguments have same meaning as for previous function */
16006 static void
16008 rtx count,
16010 {
16011 rtx destexp;
16012 rtx countreg;
16019 {
16023 }
16024 else
16027 }
16029 static void
16032 {
16036 }
16038 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16039 static void
16042 {
16045 {
16050 {
16052 {
16055 }
16056 else
16059 }
16061 {
16064 else
16065 {
16068 }
16070 }
16072 {
16075 }
16077 {
16080 }
16082 {
16085 }
16087 }
16089 {
16095 }
16097 /* When there are stringops, we can cheaply increase dest and src pointers.
16098 Otherwise we save code size by maintaining offset (zero is readily
16099 available from preceding rep operation) and using x86 addressing modes.
16100 */
16102 {
16104 {
16111 }
16113 {
16120 }
16122 {
16129 }
16130 }
16131 else
16132 {
16134 rtx tmp;
16137 {
16148 }
16150 {
16163 }
16165 {
16174 }
16175 }
16176 }
16178 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16179 static void
16182 {
16183 count =
16189 }
16191 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16192 static void
16194 {
16195 rtx dest;
16198 {
16203 {
16205 {
16210 }
16211 else
16214 }
16216 {
16218 {
16221 }
16222 else
16223 {
16228 }
16230 }
16232 {
16236 }
16238 {
16242 }
16244 {
16248 }
16250 }
16252 {
16255 }
16257 {
16260 {
16264 }
16265 else
16266 {
16272 }
16275 }
16277 {
16280 {
16283 }
16284 else
16285 {
16289 }
16292 }
16294 {
16300 }
16302 {
16308 }
16310 {
16316 }
16317 }
16319 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
16320 DESIRED_ALIGNMENT. */
16321 static void
16325 {
16327 {
16335 }
16337 {
16345 }
16347 {
16355 }
16357 }
16359 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
16360 DESIRED_ALIGNMENT. */
16361 static void
16364 {
16366 {
16373 }
16375 {
16382 }
16384 {
16391 }
16393 }
16395 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
16396 static enum stringop_alg
16399 {
16401 /* Algorithms using the rep prefix want at least edi and ecx;
16402 additionally, memset wants eax and memcpy wants esi. Don't
16403 consider such algorithms if the user has appropriated those
16404 registers for their own purposes. */
16406 || (memset
16409 #define ALG_USABLE_P(alg) (rep_prefix_usable \
16410 || (alg != rep_prefix_1_byte \
16411 && alg != rep_prefix_4_byte \
16412 && alg != rep_prefix_8_byte))
16417 else
16421 /* rep; movq or rep; movl is the smallest variant. */
16423 {
16426 else
16428 }
16429 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
16430 */
16434 {
16438 {
16439 /* We get here if the algorithms that were not libcall-based
16440 were rep-prefix based and we are unable to use rep prefixes
16441 based on global register usage. Break out of the loop and
16442 use the heuristic below. */
16446 {
16451 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
16452 last non-libcall inline algorithm. */
16454 {
16455 /* When the current size is best to be copied by a libcall,
16456 but we are still forced to inline, run the heuristic below
16457 that will pick code for medium sized blocks. */
16461 }
16464 }
16465 }
16467 }
16468 /* When asked to inline the call anyway, try to pick meaningful choice.
16469 We look for maximal size of block that is faster to copy by hand and
16470 take blocks of at most of that size guessing that average size will
16471 be roughly half of the block.
16473 If this turns out to be bad, we might simply specify the preferred
16474 choice in ix86_costs. */
16477 {
16484 {
16491 }
16492 /* If there aren't any usable algorithms, then recursing on
16493 smaller sizes isn't going to find anything. Just return the
16494 simple byte-at-a-time copy loop. */
16496 {
16497 /* Pick something reasonable. */
16501 }
16510 }
16512 #undef ALG_USABLE_P
16513 }
16515 /* Decide on alignment. We know that the operand is already aligned to ALIGN
16516 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
16517 static int
16521 {
16524 {
16535 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
16536 copying whole cacheline at once. */
16539 else
16543 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
16544 copying whole cacheline at once. */
16547 else
16555 }
16564 }
16566 /* Return the smallest power of 2 greater than VAL. */
16567 static int
16569 {
16574 }
16576 /* Expand string move (memcpy) operation. Use i386 string operations when
16577 profitable. expand_setmem contains similar code. The code depends upon
16578 architecture, block size and alignment, but always has the same
16579 overall structure:
16581 1) Prologue guard: Conditional that jumps up to epilogues for small
16582 blocks that can be handled by epilogue alone. This is faster but
16583 also needed for correctness, since prologue assume the block is larger
16584 than the desired alignment.
16586 Optional dynamic check for size and libcall for large
16587 blocks is emitted here too, with -minline-stringops-dynamically.
16589 2) Prologue: copy first few bytes in order to get destination aligned
16590 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
16591 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
16592 We emit either a jump tree on power of two sized blocks, or a byte loop.
16594 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
16595 with specified algorithm.
16597 4) Epilogue: code copying tail of the block that is too small to be
16598 handled by main body (or up to size guarded by prologue guard). */
16600 int
16603 {
16604 rtx destreg;
16605 rtx srcreg;
16607 rtx tmp;
16619 /* i386 can do misaligned access on reasonably increased cost. */
16628 /* Make sure we don't need to care about overflow later on. */
16632 /* Step 0: Decide on preferred algorithm, desired alignment and
16633 size of chunks to be copied by main loop. */
16649 {
16669 }
16673 /* Step 1: Prologue guard. */
16675 /* Alignment code needs count to be in register. */
16680 /* Ensure that alignment prologue won't copy past end of block. */
16682 {
16684 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
16685 Make sure it is power of 2. */
16689 {
16692 }
16693 else
16694 {
16701 else
16703 }
16704 }
16706 /* Emit code to decide on runtime whether library call or inline should be
16707 used. */
16709 {
16711 {
16713 {
16717 }
16718 }
16719 else
16720 {
16729 }
16730 }
16732 /* Step 2: Alignment prologue. */
16735 {
16736 /* Except for the first move in epilogue, we no longer know
16737 constant offset in aliasing info. It don't seems to worth
16738 the pain to maintain it for the first move, so throw away
16739 the info early. */
16743 desired_align);
16744 }
16746 {
16750 }
16752 /* Step 3: Main loop. */
16755 {
16768 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
16769 registers for 4 temporaries anyway. */
16772 expected_size);
16776 DImode);
16780 SImode);
16784 QImode);
16786 }
16787 /* Adjust properly the offset of src and dest memory for aliasing. */
16789 {
16794 }
16795 else
16796 {
16799 }
16801 /* Step 4: Epilogue to copy the remaining bytes. */
16802 epilogue:
16804 {
16805 /* When the main loop is done, COUNT_EXP might hold original count,
16806 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
16807 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
16808 bytes. Compensate if needed. */
16811 {
16812 tmp =
16815 OPTAB_DIRECT);
16818 }
16821 }
16825 epilogue_size_needed);
16829 }
16831 /* Helper function for memcpy. For QImode value 0xXY produce
16832 0xXYXYXYXY of wide specified by MODE. This is essentially
16833 a * 0x10101010, but we can do slightly better than
16834 synth_mult by unwinding the sequence by hand on CPUs with
16835 slow multiply. */
16836 static rtx
16838 {
16840 rtx tmp;
16847 {
16855 }
16864 nops--;
16869 {
16873 OPTAB_DIRECT);
16874 }
16875 else
16876 {
16882 else
16884 else
16885 {
16888 reg =
16890 }
16900 }
16901 }
16903 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
16904 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
16905 alignment from ALIGN to DESIRED_ALIGN. */
16906 static rtx
16908 {
16909 rtx promoted_val;
16918 else
16922 }
16924 /* Expand string clear operation (bzero). Use i386 string operations when
16925 profitable. See expand_movmem comment for explanation of individual
16926 steps performed. */
16927 int
16930 {
16931 rtx destreg;
16933 rtx tmp;
16947 /* i386 can do misaligned access on reasonably increased cost. */
16956 /* Make sure we don't need to care about overflow later on. */
16960 /* Step 0: Decide on preferred algorithm, desired alignment and
16961 size of chunks to be copied by main loop. */
16976 {
16996 }
16999 /* Step 1: Prologue guard. */
17001 /* Alignment code needs count to be in register. */
17003 {
17008 }
17009 /* Do the cheap promotion to allow better CSE across the
17010 main loop and epilogue (ie one load of the big constant in the
17011 front of all code. */
17015 /* Ensure that alignment prologue won't copy past end of block. */
17017 {
17019 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17020 Make sure it is power of 2. */
17023 /* To improve performance of small blocks, we jump around the VAL
17024 promoting mode. This mean that if the promoted VAL is not constant,
17025 we might not use it in the epilogue and have to use byte
17026 loop variant. */
17034 ;
17037 else
17039 }
17041 {
17050 }
17052 /* Step 2: Alignment prologue. */
17054 /* Do the expensive promotion once we branched off the small blocks. */
17061 {
17062 /* Except for the first move in epilogue, we no longer know
17063 constant offset in aliasing info. It don't seems to worth
17064 the pain to maintain it for the first move, so throw away
17065 the info early. */
17068 desired_align);
17069 }
17071 {
17075 }
17077 /* Step 3: Main loop. */
17080 {
17098 DImode);
17102 SImode);
17106 QImode);
17108 }
17109 /* Adjust properly the offset of src and dest memory for aliasing. */
17113 else
17116 /* Step 4: Epilogue to copy the remaining bytes. */
17119 {
17120 /* When the main loop is done, COUNT_EXP might hold original count,
17121 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17122 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17123 bytes. Compensate if needed. */
17126 {
17127 tmp =
17130 OPTAB_DIRECT);
17134 }
17137 }
17139 {
17142 size_needed);
17143 else
17145 size_needed);
17146 }
17150 }
17152 /* Expand the appropriate insns for doing strlen if not just doing
17153 repnz; scasb
17155 out = result, initialized with the start address
17156 align_rtx = alignment of the address.
17157 scratch = scratch register, initialized with the startaddress when
17158 not aligned, otherwise undefined
17160 This is just the body. It needs the initializations mentioned above and
17161 some address computing at the end. These things are done in i386.md. */
17163 static void
17165 {
17167 rtx tmp;
17172 rtx mem;
17175 rtx cmp;
17181 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
17183 /* Is there a known alignment and is it less than 4? */
17185 {
17188 /* Is there a known alignment and is it not 2? */
17190 {
17194 /* Leave just the 3 lower bits. */
17204 }
17205 else
17206 {
17207 /* Since the alignment is 2, we have to check 2 or 0 bytes;
17208 check if is aligned to 4 - byte. */
17215 }
17219 /* Now compare the bytes. */
17221 /* Compare the first n unaligned byte on a byte per byte basis. */
17225 /* Increment the address. */
17228 /* Not needed with an alignment of 2 */
17230 {
17234 end_0_label);
17239 }
17242 end_0_label);
17245 }
17247 /* Generate loop to check 4 bytes at a time. It is not a good idea to
17248 align this loop. It gives only huge programs, but does not help to
17249 speed up. */
17256 /* This formula yields a nonzero result iff one of the bytes is zero.
17257 This saves three branches inside loop and many cycles. */
17265 align_4_label);
17268 {
17274 /* If zero is not in the first two bytes, move two bytes forward. */
17280 reg,
17281 tmpreg)));
17282 /* Emit lea manually to avoid clobbering of flags. */
17290 reg2,
17291 out)));
17293 }
17294 else
17295 {
17297 /* Is zero in the first two bytes? */
17304 pc_rtx);
17308 /* Not in the first two. Move two bytes forward. */
17314 }
17316 /* Avoid branch in fixing the byte. */
17323 }
17325 /* Expand strlen. */
17327 int
17329 {
17332 /* The generic case of strlen expander is long. Avoid it's
17333 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
17336 && !TARGET_INLINE_ALL_STRINGOPS
17337 && !optimize_size
17346 {
17347 /* Well it seems that some optimizer does not combine a call like
17348 foo(strlen(bar), strlen(bar));
17349 when the move and the subtraction is done here. It does calculate
17350 the length just once when these instructions are done inside of
17351 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
17352 often used and I use one fewer register for the lifetime of
17353 output_strlen_unroll() this is better. */
17359 /* strlensi_unroll_1 returns the address of the zero at the end of
17360 the string, like memchr(), so compute the length by subtracting
17361 the start address. */
17363 }
17364 else
17365 {
17366 rtx unspec;
17368 /* Can't use this if the user has appropriated eax, ecx, or edi. */
17381 /* If .md starts supporting :P, this can be done in .md. */
17387 }
17389 }
17391 /* For given symbol (function) construct code to compute address of it's PLT
17392 entry in large x86-64 PIC model. */
17393 rtx
17395 {
17405 }
17407 void
17409 rtx callarg2 ATTRIBUTE_UNUSED,
17411 {
17419 {
17420 #if TARGET_MACHO
17423 #endif
17424 }
17425 else
17426 {
17427 /* Static functions and indirect calls don't need the pic register. */
17432 }
17435 {
17439 }
17447 {
17450 }
17453 {
17454 rtx addr;
17459 }
17465 {
17469 }
17474 }
17476 \f
17477 /* Clear stack slot assignments remembered from previous functions.
17478 This is called from INIT_EXPANDERS once before RTL is emitted for each
17479 function. */
17483 {
17492 }
17494 /* Return a MEM corresponding to a stack slot with mode MODE.
17495 Allocate a new slot if necessary.
17497 The RTL for a function can have several slots available: N is
17498 which slot to use. */
17500 rtx
17502 {
17507 /* Virtual slot is valid only before vregs are instantiated. */
17523 }
17525 /* Construct the SYMBOL_REF for the tls_get_addr function. */
17528 rtx
17530 {
17533 {
17535 (TARGET_ANY_GNU_TLS
17539 }
17542 }
17544 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
17547 rtx
17549 {
17552 {
17557 }
17560 }
17561 \f
17562 /* Calculate the length of the memory address in the instruction
17563 encoding. Does not include the one-byte modrm, opcode, or prefix. */
17565 int
17567 {
17592 /* Rule of thumb:
17593 - esp as the base always wants an index,
17594 - ebp as the base always wants a displacement. */
17596 /* Register Indirect. */
17598 {
17599 /* esp (for its index) and ebp (for its displacement) need
17600 the two-byte modrm form. */
17606 }
17608 /* Direct Addressing. */
17612 else
17613 {
17614 /* Find the length of the displacement constant. */
17616 {
17619 else
17621 }
17622 /* ebp always wants a displacement. */
17626 /* An index requires the two-byte modrm form.... */
17628 /* ...like esp, which always wants an index. */
17633 }
17636 }
17638 /* Compute default value for "length_immediate" attribute. When SHORTFORM
17639 is set, expect that insn have 8bit immediate alternative. */
17640 int
17642 {
17648 {
17652 else
17653 {
17655 {
17665 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
17671 }
17672 }
17673 }
17675 }
17676 /* Compute default value for "length_address" attribute. */
17677 int
17679 {
17683 {
17692 }
17697 {
17700 }
17702 }
17703 \f
17704 /* Return the maximum number of instructions a cpu can issue. */
17706 static int
17708 {
17710 {
17730 }
17731 }
17733 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
17734 by DEP_INSN and nothing set by DEP_INSN. */
17736 static int
17738 {
17741 /* Simplify the test for uninteresting insns. */
17749 {
17752 }
17757 {
17760 }
17761 else
17767 /* This test is true if the dependent insn reads the flags but
17768 not any other potentially set register. */
17776 }
17778 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
17779 address with operands set by DEP_INSN. */
17781 static int
17783 {
17784 rtx addr;
17788 {
17797 }
17798 else
17799 {
17804 {
17807 }
17809 found:;
17810 }
17813 }
17815 static int
17817 {
17823 /* Anti and output dependencies have zero cost on all CPUs. */
17829 /* If we can't recognize the insns, we can't really do anything. */
17837 {
17839 /* Address Generation Interlock adds a cycle of latency. */
17843 /* ??? Compares pair with jump/setcc. */
17847 /* Floating point stores require value to be ready one cycle earlier. */
17857 /* INT->FP conversion is expensive. */
17861 /* There is one cycle extra latency between an FP op and a store. */
17869 /* Show ability of reorder buffer to hide latency of load by executing
17870 in parallel with previous instruction in case
17871 previous instruction is not needed to compute the address. */
17874 {
17875 /* Claim moves to take one cycle, as core can issue one load
17876 at time and the next load can start cycle later. */
17881 cost--;
17882 }
17888 /* The esp dependency is resolved before the instruction is really
17889 finished. */
17894 /* INT->FP conversion is expensive. */
17898 /* Show ability of reorder buffer to hide latency of load by executing
17899 in parallel with previous instruction in case
17900 previous instruction is not needed to compute the address. */
17903 {
17904 /* Claim moves to take one cycle, as core can issue one load
17905 at time and the next load can start cycle later. */
17911 else
17913 }
17923 /* Show ability of reorder buffer to hide latency of load by executing
17924 in parallel with previous instruction in case
17925 previous instruction is not needed to compute the address. */
17928 {
17932 /* Because of the difference between the length of integer and
17933 floating unit pipeline preparation stages, the memory operands
17934 for floating point are cheaper.
17936 ??? For Athlon it the difference is most probably 2. */
17939 else
17944 else
17946 }
17950 }
17953 }
17955 /* How many alternative schedules to try. This should be as wide as the
17956 scheduling freedom in the DFA, but no wider. Making this value too
17957 large results extra work for the scheduler. */
17959 static int
17961 {
17963 {
17973 }
17974 }
17976 \f
17977 /* Compute the alignment given to a constant that is being placed in memory.
17978 EXP is the constant and ALIGN is the alignment that the object would
17979 ordinarily have.
17980 The value of this function is used instead of that alignment to align
17981 the object. */
17983 int
17985 {
17988 {
17993 }
17999 }
18001 /* Compute the alignment for a static variable.
18002 TYPE is the data type, and ALIGN is the alignment that
18003 the object would ordinarily have. The value of this function is used
18004 instead of that alignment to align the object. */
18006 int
18008 {
18019 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18020 to 16byte boundary. */
18022 {
18029 }
18032 {
18037 }
18039 {
18046 }
18051 {
18056 }
18059 {
18064 }
18067 }
18069 /* Compute the alignment for a local variable or a stack slot. TYPE is
18070 the data type, MODE is the widest mode available and ALIGN is the
18071 alignment that the object would ordinarily have. The value of this
18072 macro is used instead of that alignment to align the object. */
18074 unsigned int
18077 {
18078 /* If TYPE is NULL, we are allocating a stack slot for caller-save
18079 register in MODE. We will return the largest alignment of XF
18080 and DF. */
18082 {
18086 }
18088 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18089 to 16byte boundary. */
18091 {
18098 }
18100 {
18105 }
18107 {
18113 }
18118 {
18123 }
18126 {
18132 }
18134 }
18135 \f
18136 /* Emit RTL insns to initialize the variable parts of a trampoline.
18137 FNADDR is an RTX for the address of the function's pure code.
18138 CXT is an RTX for the static chain value for the function. */
18139 void
18141 {
18143 {
18144 /* Compute offset from the end of the jmp to the target function. */
18154 }
18155 else
18156 {
18158 /* Try to load address using shorter movl instead of movabs.
18159 We may want to support movq for kernel mode, but kernel does not use
18160 trampolines at the moment. */
18162 {
18169 }
18170 else
18171 {
18175 fnaddr);
18177 }
18178 /* Load static chain using movabs to r10. */
18182 cxt);
18184 /* Jump to the r11 */
18191 }
18193 #ifdef ENABLE_EXECUTE_STACK
18196 #endif
18197 }
18198 \f
18199 /* Codes for all the SSE/MMX builtins. */
18200 enum ix86_builtins
18201 {
18202 IX86_BUILTIN_ADDPS,
18203 IX86_BUILTIN_ADDSS,
18204 IX86_BUILTIN_DIVPS,
18205 IX86_BUILTIN_DIVSS,
18206 IX86_BUILTIN_MULPS,
18207 IX86_BUILTIN_MULSS,
18208 IX86_BUILTIN_SUBPS,
18209 IX86_BUILTIN_SUBSS,
18211 IX86_BUILTIN_CMPEQPS,
18212 IX86_BUILTIN_CMPLTPS,
18213 IX86_BUILTIN_CMPLEPS,
18214 IX86_BUILTIN_CMPGTPS,
18215 IX86_BUILTIN_CMPGEPS,
18216 IX86_BUILTIN_CMPNEQPS,
18217 IX86_BUILTIN_CMPNLTPS,
18218 IX86_BUILTIN_CMPNLEPS,
18219 IX86_BUILTIN_CMPNGTPS,
18220 IX86_BUILTIN_CMPNGEPS,
18221 IX86_BUILTIN_CMPORDPS,
18222 IX86_BUILTIN_CMPUNORDPS,
18223 IX86_BUILTIN_CMPEQSS,
18224 IX86_BUILTIN_CMPLTSS,
18225 IX86_BUILTIN_CMPLESS,
18226 IX86_BUILTIN_CMPNEQSS,
18227 IX86_BUILTIN_CMPNLTSS,
18228 IX86_BUILTIN_CMPNLESS,
18229 IX86_BUILTIN_CMPNGTSS,
18230 IX86_BUILTIN_CMPNGESS,
18231 IX86_BUILTIN_CMPORDSS,
18232 IX86_BUILTIN_CMPUNORDSS,
18234 IX86_BUILTIN_COMIEQSS,
18235 IX86_BUILTIN_COMILTSS,
18236 IX86_BUILTIN_COMILESS,
18237 IX86_BUILTIN_COMIGTSS,
18238 IX86_BUILTIN_COMIGESS,
18239 IX86_BUILTIN_COMINEQSS,
18240 IX86_BUILTIN_UCOMIEQSS,
18241 IX86_BUILTIN_UCOMILTSS,
18242 IX86_BUILTIN_UCOMILESS,
18243 IX86_BUILTIN_UCOMIGTSS,
18244 IX86_BUILTIN_UCOMIGESS,
18245 IX86_BUILTIN_UCOMINEQSS,
18247 IX86_BUILTIN_CVTPI2PS,
18248 IX86_BUILTIN_CVTPS2PI,
18249 IX86_BUILTIN_CVTSI2SS,
18250 IX86_BUILTIN_CVTSI642SS,
18251 IX86_BUILTIN_CVTSS2SI,
18252 IX86_BUILTIN_CVTSS2SI64,
18253 IX86_BUILTIN_CVTTPS2PI,
18254 IX86_BUILTIN_CVTTSS2SI,
18255 IX86_BUILTIN_CVTTSS2SI64,
18257 IX86_BUILTIN_MAXPS,
18258 IX86_BUILTIN_MAXSS,
18259 IX86_BUILTIN_MINPS,
18260 IX86_BUILTIN_MINSS,
18262 IX86_BUILTIN_LOADUPS,
18263 IX86_BUILTIN_STOREUPS,
18264 IX86_BUILTIN_MOVSS,
18266 IX86_BUILTIN_MOVHLPS,
18267 IX86_BUILTIN_MOVLHPS,
18268 IX86_BUILTIN_LOADHPS,
18269 IX86_BUILTIN_LOADLPS,
18270 IX86_BUILTIN_STOREHPS,
18271 IX86_BUILTIN_STORELPS,
18273 IX86_BUILTIN_MASKMOVQ,
18274 IX86_BUILTIN_MOVMSKPS,
18275 IX86_BUILTIN_PMOVMSKB,
18277 IX86_BUILTIN_MOVNTPS,
18278 IX86_BUILTIN_MOVNTQ,
18280 IX86_BUILTIN_LOADDQU,
18281 IX86_BUILTIN_STOREDQU,
18283 IX86_BUILTIN_PACKSSWB,
18284 IX86_BUILTIN_PACKSSDW,
18285 IX86_BUILTIN_PACKUSWB,
18287 IX86_BUILTIN_PADDB,
18288 IX86_BUILTIN_PADDW,
18289 IX86_BUILTIN_PADDD,
18290 IX86_BUILTIN_PADDQ,
18291 IX86_BUILTIN_PADDSB,
18292 IX86_BUILTIN_PADDSW,
18293 IX86_BUILTIN_PADDUSB,
18294 IX86_BUILTIN_PADDUSW,
18295 IX86_BUILTIN_PSUBB,
18296 IX86_BUILTIN_PSUBW,
18297 IX86_BUILTIN_PSUBD,
18298 IX86_BUILTIN_PSUBQ,
18299 IX86_BUILTIN_PSUBSB,
18300 IX86_BUILTIN_PSUBSW,
18301 IX86_BUILTIN_PSUBUSB,
18302 IX86_BUILTIN_PSUBUSW,
18304 IX86_BUILTIN_PAND,
18305 IX86_BUILTIN_PANDN,
18306 IX86_BUILTIN_POR,
18307 IX86_BUILTIN_PXOR,
18309 IX86_BUILTIN_PAVGB,
18310 IX86_BUILTIN_PAVGW,
18312 IX86_BUILTIN_PCMPEQB,
18313 IX86_BUILTIN_PCMPEQW,
18314 IX86_BUILTIN_PCMPEQD,
18315 IX86_BUILTIN_PCMPGTB,
18316 IX86_BUILTIN_PCMPGTW,
18317 IX86_BUILTIN_PCMPGTD,
18319 IX86_BUILTIN_PMADDWD,
18321 IX86_BUILTIN_PMAXSW,
18322 IX86_BUILTIN_PMAXUB,
18323 IX86_BUILTIN_PMINSW,
18324 IX86_BUILTIN_PMINUB,
18326 IX86_BUILTIN_PMULHUW,
18327 IX86_BUILTIN_PMULHW,
18328 IX86_BUILTIN_PMULLW,
18330 IX86_BUILTIN_PSADBW,
18331 IX86_BUILTIN_PSHUFW,
18333 IX86_BUILTIN_PSLLW,
18334 IX86_BUILTIN_PSLLD,
18335 IX86_BUILTIN_PSLLQ,
18336 IX86_BUILTIN_PSRAW,
18337 IX86_BUILTIN_PSRAD,
18338 IX86_BUILTIN_PSRLW,
18339 IX86_BUILTIN_PSRLD,
18340 IX86_BUILTIN_PSRLQ,
18341 IX86_BUILTIN_PSLLWI,
18342 IX86_BUILTIN_PSLLDI,
18343 IX86_BUILTIN_PSLLQI,
18344 IX86_BUILTIN_PSRAWI,
18345 IX86_BUILTIN_PSRADI,
18346 IX86_BUILTIN_PSRLWI,
18347 IX86_BUILTIN_PSRLDI,
18348 IX86_BUILTIN_PSRLQI,
18350 IX86_BUILTIN_PUNPCKHBW,
18351 IX86_BUILTIN_PUNPCKHWD,
18352 IX86_BUILTIN_PUNPCKHDQ,
18353 IX86_BUILTIN_PUNPCKLBW,
18354 IX86_BUILTIN_PUNPCKLWD,
18355 IX86_BUILTIN_PUNPCKLDQ,
18357 IX86_BUILTIN_SHUFPS,
18359 IX86_BUILTIN_RCPPS,
18360 IX86_BUILTIN_RCPSS,
18361 IX86_BUILTIN_RSQRTPS,
18362 IX86_BUILTIN_RSQRTPS_NR,
18363 IX86_BUILTIN_RSQRTSS,
18364 IX86_BUILTIN_RSQRTF,
18365 IX86_BUILTIN_SQRTPS,
18366 IX86_BUILTIN_SQRTPS_NR,
18367 IX86_BUILTIN_SQRTSS,
18369 IX86_BUILTIN_UNPCKHPS,
18370 IX86_BUILTIN_UNPCKLPS,
18372 IX86_BUILTIN_ANDPS,
18373 IX86_BUILTIN_ANDNPS,
18374 IX86_BUILTIN_ORPS,
18375 IX86_BUILTIN_XORPS,
18377 IX86_BUILTIN_EMMS,
18378 IX86_BUILTIN_LDMXCSR,
18379 IX86_BUILTIN_STMXCSR,
18380 IX86_BUILTIN_SFENCE,
18382 /* 3DNow! Original */
18383 IX86_BUILTIN_FEMMS,
18384 IX86_BUILTIN_PAVGUSB,
18385 IX86_BUILTIN_PF2ID,
18386 IX86_BUILTIN_PFACC,
18387 IX86_BUILTIN_PFADD,
18388 IX86_BUILTIN_PFCMPEQ,
18389 IX86_BUILTIN_PFCMPGE,
18390 IX86_BUILTIN_PFCMPGT,
18391 IX86_BUILTIN_PFMAX,
18392 IX86_BUILTIN_PFMIN,
18393 IX86_BUILTIN_PFMUL,
18394 IX86_BUILTIN_PFRCP,
18395 IX86_BUILTIN_PFRCPIT1,
18396 IX86_BUILTIN_PFRCPIT2,
18397 IX86_BUILTIN_PFRSQIT1,
18398 IX86_BUILTIN_PFRSQRT,
18399 IX86_BUILTIN_PFSUB,
18400 IX86_BUILTIN_PFSUBR,
18401 IX86_BUILTIN_PI2FD,
18402 IX86_BUILTIN_PMULHRW,
18404 /* 3DNow! Athlon Extensions */
18405 IX86_BUILTIN_PF2IW,
18406 IX86_BUILTIN_PFNACC,
18407 IX86_BUILTIN_PFPNACC,
18408 IX86_BUILTIN_PI2FW,
18409 IX86_BUILTIN_PSWAPDSI,
18410 IX86_BUILTIN_PSWAPDSF,
18412 /* SSE2 */
18413 IX86_BUILTIN_ADDPD,
18414 IX86_BUILTIN_ADDSD,
18415 IX86_BUILTIN_DIVPD,
18416 IX86_BUILTIN_DIVSD,
18417 IX86_BUILTIN_MULPD,
18418 IX86_BUILTIN_MULSD,
18419 IX86_BUILTIN_SUBPD,
18420 IX86_BUILTIN_SUBSD,
18422 IX86_BUILTIN_CMPEQPD,
18423 IX86_BUILTIN_CMPLTPD,
18424 IX86_BUILTIN_CMPLEPD,
18425 IX86_BUILTIN_CMPGTPD,
18426 IX86_BUILTIN_CMPGEPD,
18427 IX86_BUILTIN_CMPNEQPD,
18428 IX86_BUILTIN_CMPNLTPD,
18429 IX86_BUILTIN_CMPNLEPD,
18430 IX86_BUILTIN_CMPNGTPD,
18431 IX86_BUILTIN_CMPNGEPD,
18432 IX86_BUILTIN_CMPORDPD,
18433 IX86_BUILTIN_CMPUNORDPD,
18434 IX86_BUILTIN_CMPEQSD,
18435 IX86_BUILTIN_CMPLTSD,
18436 IX86_BUILTIN_CMPLESD,
18437 IX86_BUILTIN_CMPNEQSD,
18438 IX86_BUILTIN_CMPNLTSD,
18439 IX86_BUILTIN_CMPNLESD,
18440 IX86_BUILTIN_CMPORDSD,
18441 IX86_BUILTIN_CMPUNORDSD,
18443 IX86_BUILTIN_COMIEQSD,
18444 IX86_BUILTIN_COMILTSD,
18445 IX86_BUILTIN_COMILESD,
18446 IX86_BUILTIN_COMIGTSD,
18447 IX86_BUILTIN_COMIGESD,
18448 IX86_BUILTIN_COMINEQSD,
18449 IX86_BUILTIN_UCOMIEQSD,
18450 IX86_BUILTIN_UCOMILTSD,
18451 IX86_BUILTIN_UCOMILESD,
18452 IX86_BUILTIN_UCOMIGTSD,
18453 IX86_BUILTIN_UCOMIGESD,
18454 IX86_BUILTIN_UCOMINEQSD,
18456 IX86_BUILTIN_MAXPD,
18457 IX86_BUILTIN_MAXSD,
18458 IX86_BUILTIN_MINPD,
18459 IX86_BUILTIN_MINSD,
18461 IX86_BUILTIN_ANDPD,
18462 IX86_BUILTIN_ANDNPD,
18463 IX86_BUILTIN_ORPD,
18464 IX86_BUILTIN_XORPD,
18466 IX86_BUILTIN_SQRTPD,
18467 IX86_BUILTIN_SQRTSD,
18469 IX86_BUILTIN_UNPCKHPD,
18470 IX86_BUILTIN_UNPCKLPD,
18472 IX86_BUILTIN_SHUFPD,
18474 IX86_BUILTIN_LOADUPD,
18475 IX86_BUILTIN_STOREUPD,
18476 IX86_BUILTIN_MOVSD,
18478 IX86_BUILTIN_LOADHPD,
18479 IX86_BUILTIN_LOADLPD,
18481 IX86_BUILTIN_CVTDQ2PD,
18482 IX86_BUILTIN_CVTDQ2PS,
18484 IX86_BUILTIN_CVTPD2DQ,
18485 IX86_BUILTIN_CVTPD2PI,
18486 IX86_BUILTIN_CVTPD2PS,
18487 IX86_BUILTIN_CVTTPD2DQ,
18488 IX86_BUILTIN_CVTTPD2PI,
18490 IX86_BUILTIN_CVTPI2PD,
18491 IX86_BUILTIN_CVTSI2SD,
18492 IX86_BUILTIN_CVTSI642SD,
18494 IX86_BUILTIN_CVTSD2SI,
18495 IX86_BUILTIN_CVTSD2SI64,
18496 IX86_BUILTIN_CVTSD2SS,
18497 IX86_BUILTIN_CVTSS2SD,
18498 IX86_BUILTIN_CVTTSD2SI,
18499 IX86_BUILTIN_CVTTSD2SI64,
18501 IX86_BUILTIN_CVTPS2DQ,
18502 IX86_BUILTIN_CVTPS2PD,
18503 IX86_BUILTIN_CVTTPS2DQ,
18505 IX86_BUILTIN_MOVNTI,
18506 IX86_BUILTIN_MOVNTPD,
18507 IX86_BUILTIN_MOVNTDQ,
18509 /* SSE2 MMX */
18510 IX86_BUILTIN_MASKMOVDQU,
18511 IX86_BUILTIN_MOVMSKPD,
18512 IX86_BUILTIN_PMOVMSKB128,
18514 IX86_BUILTIN_PACKSSWB128,
18515 IX86_BUILTIN_PACKSSDW128,
18516 IX86_BUILTIN_PACKUSWB128,
18518 IX86_BUILTIN_PADDB128,
18519 IX86_BUILTIN_PADDW128,
18520 IX86_BUILTIN_PADDD128,
18521 IX86_BUILTIN_PADDQ128,
18522 IX86_BUILTIN_PADDSB128,
18523 IX86_BUILTIN_PADDSW128,
18524 IX86_BUILTIN_PADDUSB128,
18525 IX86_BUILTIN_PADDUSW128,
18526 IX86_BUILTIN_PSUBB128,
18527 IX86_BUILTIN_PSUBW128,
18528 IX86_BUILTIN_PSUBD128,
18529 IX86_BUILTIN_PSUBQ128,
18530 IX86_BUILTIN_PSUBSB128,
18531 IX86_BUILTIN_PSUBSW128,
18532 IX86_BUILTIN_PSUBUSB128,
18533 IX86_BUILTIN_PSUBUSW128,
18535 IX86_BUILTIN_PAND128,
18536 IX86_BUILTIN_PANDN128,
18537 IX86_BUILTIN_POR128,
18538 IX86_BUILTIN_PXOR128,
18540 IX86_BUILTIN_PAVGB128,
18541 IX86_BUILTIN_PAVGW128,
18543 IX86_BUILTIN_PCMPEQB128,
18544 IX86_BUILTIN_PCMPEQW128,
18545 IX86_BUILTIN_PCMPEQD128,
18546 IX86_BUILTIN_PCMPGTB128,
18547 IX86_BUILTIN_PCMPGTW128,
18548 IX86_BUILTIN_PCMPGTD128,
18550 IX86_BUILTIN_PMADDWD128,
18552 IX86_BUILTIN_PMAXSW128,
18553 IX86_BUILTIN_PMAXUB128,
18554 IX86_BUILTIN_PMINSW128,
18555 IX86_BUILTIN_PMINUB128,
18557 IX86_BUILTIN_PMULUDQ,
18558 IX86_BUILTIN_PMULUDQ128,
18559 IX86_BUILTIN_PMULHUW128,
18560 IX86_BUILTIN_PMULHW128,
18561 IX86_BUILTIN_PMULLW128,
18563 IX86_BUILTIN_PSADBW128,
18564 IX86_BUILTIN_PSHUFHW,
18565 IX86_BUILTIN_PSHUFLW,
18566 IX86_BUILTIN_PSHUFD,
18568 IX86_BUILTIN_PSLLDQI128,
18569 IX86_BUILTIN_PSLLWI128,
18570 IX86_BUILTIN_PSLLDI128,
18571 IX86_BUILTIN_PSLLQI128,
18572 IX86_BUILTIN_PSRAWI128,
18573 IX86_BUILTIN_PSRADI128,
18574 IX86_BUILTIN_PSRLDQI128,
18575 IX86_BUILTIN_PSRLWI128,
18576 IX86_BUILTIN_PSRLDI128,
18577 IX86_BUILTIN_PSRLQI128,
18579 IX86_BUILTIN_PSLLDQ128,
18580 IX86_BUILTIN_PSLLW128,
18581 IX86_BUILTIN_PSLLD128,
18582 IX86_BUILTIN_PSLLQ128,
18583 IX86_BUILTIN_PSRAW128,
18584 IX86_BUILTIN_PSRAD128,
18585 IX86_BUILTIN_PSRLW128,
18586 IX86_BUILTIN_PSRLD128,
18587 IX86_BUILTIN_PSRLQ128,
18589 IX86_BUILTIN_PUNPCKHBW128,
18590 IX86_BUILTIN_PUNPCKHWD128,
18591 IX86_BUILTIN_PUNPCKHDQ128,
18592 IX86_BUILTIN_PUNPCKHQDQ128,
18593 IX86_BUILTIN_PUNPCKLBW128,
18594 IX86_BUILTIN_PUNPCKLWD128,
18595 IX86_BUILTIN_PUNPCKLDQ128,
18596 IX86_BUILTIN_PUNPCKLQDQ128,
18598 IX86_BUILTIN_CLFLUSH,
18599 IX86_BUILTIN_MFENCE,
18600 IX86_BUILTIN_LFENCE,
18602 /* SSE3. */
18603 IX86_BUILTIN_ADDSUBPS,
18604 IX86_BUILTIN_HADDPS,
18605 IX86_BUILTIN_HSUBPS,
18606 IX86_BUILTIN_MOVSHDUP,
18607 IX86_BUILTIN_MOVSLDUP,
18608 IX86_BUILTIN_ADDSUBPD,
18609 IX86_BUILTIN_HADDPD,
18610 IX86_BUILTIN_HSUBPD,
18611 IX86_BUILTIN_LDDQU,
18613 IX86_BUILTIN_MONITOR,
18614 IX86_BUILTIN_MWAIT,
18616 /* SSSE3. */
18617 IX86_BUILTIN_PHADDW,
18618 IX86_BUILTIN_PHADDD,
18619 IX86_BUILTIN_PHADDSW,
18620 IX86_BUILTIN_PHSUBW,
18621 IX86_BUILTIN_PHSUBD,
18622 IX86_BUILTIN_PHSUBSW,
18623 IX86_BUILTIN_PMADDUBSW,
18624 IX86_BUILTIN_PMULHRSW,
18625 IX86_BUILTIN_PSHUFB,
18626 IX86_BUILTIN_PSIGNB,
18627 IX86_BUILTIN_PSIGNW,
18628 IX86_BUILTIN_PSIGND,
18629 IX86_BUILTIN_PALIGNR,
18630 IX86_BUILTIN_PABSB,
18631 IX86_BUILTIN_PABSW,
18632 IX86_BUILTIN_PABSD,
18634 IX86_BUILTIN_PHADDW128,
18635 IX86_BUILTIN_PHADDD128,
18636 IX86_BUILTIN_PHADDSW128,
18637 IX86_BUILTIN_PHSUBW128,
18638 IX86_BUILTIN_PHSUBD128,
18639 IX86_BUILTIN_PHSUBSW128,
18640 IX86_BUILTIN_PMADDUBSW128,
18641 IX86_BUILTIN_PMULHRSW128,
18642 IX86_BUILTIN_PSHUFB128,
18643 IX86_BUILTIN_PSIGNB128,
18644 IX86_BUILTIN_PSIGNW128,
18645 IX86_BUILTIN_PSIGND128,
18646 IX86_BUILTIN_PALIGNR128,
18647 IX86_BUILTIN_PABSB128,
18648 IX86_BUILTIN_PABSW128,
18649 IX86_BUILTIN_PABSD128,
18651 /* AMDFAM10 - SSE4A New Instructions. */
18652 IX86_BUILTIN_MOVNTSD,
18653 IX86_BUILTIN_MOVNTSS,
18654 IX86_BUILTIN_EXTRQI,
18655 IX86_BUILTIN_EXTRQ,
18656 IX86_BUILTIN_INSERTQI,
18657 IX86_BUILTIN_INSERTQ,
18659 /* SSE4.1. */
18660 IX86_BUILTIN_BLENDPD,
18661 IX86_BUILTIN_BLENDPS,
18662 IX86_BUILTIN_BLENDVPD,
18663 IX86_BUILTIN_BLENDVPS,
18664 IX86_BUILTIN_PBLENDVB128,
18665 IX86_BUILTIN_PBLENDW128,
18667 IX86_BUILTIN_DPPD,
18668 IX86_BUILTIN_DPPS,
18670 IX86_BUILTIN_INSERTPS128,
18672 IX86_BUILTIN_MOVNTDQA,
18673 IX86_BUILTIN_MPSADBW128,
18674 IX86_BUILTIN_PACKUSDW128,
18675 IX86_BUILTIN_PCMPEQQ,
18676 IX86_BUILTIN_PHMINPOSUW128,
18678 IX86_BUILTIN_PMAXSB128,
18679 IX86_BUILTIN_PMAXSD128,
18680 IX86_BUILTIN_PMAXUD128,
18681 IX86_BUILTIN_PMAXUW128,
18683 IX86_BUILTIN_PMINSB128,
18684 IX86_BUILTIN_PMINSD128,
18685 IX86_BUILTIN_PMINUD128,
18686 IX86_BUILTIN_PMINUW128,
18688 IX86_BUILTIN_PMOVSXBW128,
18689 IX86_BUILTIN_PMOVSXBD128,
18690 IX86_BUILTIN_PMOVSXBQ128,
18691 IX86_BUILTIN_PMOVSXWD128,
18692 IX86_BUILTIN_PMOVSXWQ128,
18693 IX86_BUILTIN_PMOVSXDQ128,
18695 IX86_BUILTIN_PMOVZXBW128,
18696 IX86_BUILTIN_PMOVZXBD128,
18697 IX86_BUILTIN_PMOVZXBQ128,
18698 IX86_BUILTIN_PMOVZXWD128,
18699 IX86_BUILTIN_PMOVZXWQ128,
18700 IX86_BUILTIN_PMOVZXDQ128,
18702 IX86_BUILTIN_PMULDQ128,
18703 IX86_BUILTIN_PMULLD128,
18705 IX86_BUILTIN_ROUNDPD,
18706 IX86_BUILTIN_ROUNDPS,
18707 IX86_BUILTIN_ROUNDSD,
18708 IX86_BUILTIN_ROUNDSS,
18710 IX86_BUILTIN_PTESTZ,
18711 IX86_BUILTIN_PTESTC,
18712 IX86_BUILTIN_PTESTNZC,
18714 IX86_BUILTIN_VEC_INIT_V2SI,
18715 IX86_BUILTIN_VEC_INIT_V4HI,
18716 IX86_BUILTIN_VEC_INIT_V8QI,
18717 IX86_BUILTIN_VEC_EXT_V2DF,
18718 IX86_BUILTIN_VEC_EXT_V2DI,
18719 IX86_BUILTIN_VEC_EXT_V4SF,
18720 IX86_BUILTIN_VEC_EXT_V4SI,
18721 IX86_BUILTIN_VEC_EXT_V8HI,
18722 IX86_BUILTIN_VEC_EXT_V2SI,
18723 IX86_BUILTIN_VEC_EXT_V4HI,
18724 IX86_BUILTIN_VEC_EXT_V16QI,
18725 IX86_BUILTIN_VEC_SET_V2DI,
18726 IX86_BUILTIN_VEC_SET_V4SF,
18727 IX86_BUILTIN_VEC_SET_V4SI,
18728 IX86_BUILTIN_VEC_SET_V8HI,
18729 IX86_BUILTIN_VEC_SET_V4HI,
18730 IX86_BUILTIN_VEC_SET_V16QI,
18732 IX86_BUILTIN_VEC_PACK_SFIX,
18734 /* SSE4.2. */
18735 IX86_BUILTIN_CRC32QI,
18736 IX86_BUILTIN_CRC32HI,
18737 IX86_BUILTIN_CRC32SI,
18738 IX86_BUILTIN_CRC32DI,
18740 IX86_BUILTIN_PCMPESTRI128,
18741 IX86_BUILTIN_PCMPESTRM128,
18742 IX86_BUILTIN_PCMPESTRA128,
18743 IX86_BUILTIN_PCMPESTRC128,
18744 IX86_BUILTIN_PCMPESTRO128,
18745 IX86_BUILTIN_PCMPESTRS128,
18746 IX86_BUILTIN_PCMPESTRZ128,
18747 IX86_BUILTIN_PCMPISTRI128,
18748 IX86_BUILTIN_PCMPISTRM128,
18749 IX86_BUILTIN_PCMPISTRA128,
18750 IX86_BUILTIN_PCMPISTRC128,
18751 IX86_BUILTIN_PCMPISTRO128,
18752 IX86_BUILTIN_PCMPISTRS128,
18753 IX86_BUILTIN_PCMPISTRZ128,
18755 IX86_BUILTIN_PCMPGTQ,
18757 /* AES instructions */
18758 IX86_BUILTIN_AESENC128,
18759 IX86_BUILTIN_AESENCLAST128,
18760 IX86_BUILTIN_AESDEC128,
18761 IX86_BUILTIN_AESDECLAST128,
18762 IX86_BUILTIN_AESIMC128,
18763 IX86_BUILTIN_AESKEYGENASSIST128,
18765 /* PCLMUL instruction */
18766 IX86_BUILTIN_PCLMULQDQ128,
18768 /* TFmode support builtins. */
18769 IX86_BUILTIN_INFQ,
18770 IX86_BUILTIN_FABSQ,
18771 IX86_BUILTIN_COPYSIGNQ,
18773 /* SSE5 instructions */
18774 IX86_BUILTIN_FMADDSS,
18775 IX86_BUILTIN_FMADDSD,
18776 IX86_BUILTIN_FMADDPS,
18777 IX86_BUILTIN_FMADDPD,
18778 IX86_BUILTIN_FMSUBSS,
18779 IX86_BUILTIN_FMSUBSD,
18780 IX86_BUILTIN_FMSUBPS,
18781 IX86_BUILTIN_FMSUBPD,
18782 IX86_BUILTIN_FNMADDSS,
18783 IX86_BUILTIN_FNMADDSD,
18784 IX86_BUILTIN_FNMADDPS,
18785 IX86_BUILTIN_FNMADDPD,
18786 IX86_BUILTIN_FNMSUBSS,
18787 IX86_BUILTIN_FNMSUBSD,
18788 IX86_BUILTIN_FNMSUBPS,
18789 IX86_BUILTIN_FNMSUBPD,
18790 IX86_BUILTIN_PCMOV_V2DI,
18791 IX86_BUILTIN_PCMOV_V4SI,
18792 IX86_BUILTIN_PCMOV_V8HI,
18793 IX86_BUILTIN_PCMOV_V16QI,
18794 IX86_BUILTIN_PCMOV_V4SF,
18795 IX86_BUILTIN_PCMOV_V2DF,
18796 IX86_BUILTIN_PPERM,
18797 IX86_BUILTIN_PERMPS,
18798 IX86_BUILTIN_PERMPD,
18799 IX86_BUILTIN_PMACSSWW,
18800 IX86_BUILTIN_PMACSWW,
18801 IX86_BUILTIN_PMACSSWD,
18802 IX86_BUILTIN_PMACSWD,
18803 IX86_BUILTIN_PMACSSDD,
18804 IX86_BUILTIN_PMACSDD,
18805 IX86_BUILTIN_PMACSSDQL,
18806 IX86_BUILTIN_PMACSSDQH,
18807 IX86_BUILTIN_PMACSDQL,
18808 IX86_BUILTIN_PMACSDQH,
18809 IX86_BUILTIN_PMADCSSWD,
18810 IX86_BUILTIN_PMADCSWD,
18811 IX86_BUILTIN_PHADDBW,
18812 IX86_BUILTIN_PHADDBD,
18813 IX86_BUILTIN_PHADDBQ,
18814 IX86_BUILTIN_PHADDWD,
18815 IX86_BUILTIN_PHADDWQ,
18816 IX86_BUILTIN_PHADDDQ,
18817 IX86_BUILTIN_PHADDUBW,
18818 IX86_BUILTIN_PHADDUBD,
18819 IX86_BUILTIN_PHADDUBQ,
18820 IX86_BUILTIN_PHADDUWD,
18821 IX86_BUILTIN_PHADDUWQ,
18822 IX86_BUILTIN_PHADDUDQ,
18823 IX86_BUILTIN_PHSUBBW,
18824 IX86_BUILTIN_PHSUBWD,
18825 IX86_BUILTIN_PHSUBDQ,
18826 IX86_BUILTIN_PROTB,
18827 IX86_BUILTIN_PROTW,
18828 IX86_BUILTIN_PROTD,
18829 IX86_BUILTIN_PROTQ,
18830 IX86_BUILTIN_PROTB_IMM,
18831 IX86_BUILTIN_PROTW_IMM,
18832 IX86_BUILTIN_PROTD_IMM,
18833 IX86_BUILTIN_PROTQ_IMM,
18834 IX86_BUILTIN_PSHLB,
18835 IX86_BUILTIN_PSHLW,
18836 IX86_BUILTIN_PSHLD,
18837 IX86_BUILTIN_PSHLQ,
18838 IX86_BUILTIN_PSHAB,
18839 IX86_BUILTIN_PSHAW,
18840 IX86_BUILTIN_PSHAD,
18841 IX86_BUILTIN_PSHAQ,
18842 IX86_BUILTIN_FRCZSS,
18843 IX86_BUILTIN_FRCZSD,
18844 IX86_BUILTIN_FRCZPS,
18845 IX86_BUILTIN_FRCZPD,
18846 IX86_BUILTIN_CVTPH2PS,
18847 IX86_BUILTIN_CVTPS2PH,
18849 IX86_BUILTIN_COMEQSS,
18850 IX86_BUILTIN_COMNESS,
18851 IX86_BUILTIN_COMLTSS,
18852 IX86_BUILTIN_COMLESS,
18853 IX86_BUILTIN_COMGTSS,
18854 IX86_BUILTIN_COMGESS,
18855 IX86_BUILTIN_COMUEQSS,
18856 IX86_BUILTIN_COMUNESS,
18857 IX86_BUILTIN_COMULTSS,
18858 IX86_BUILTIN_COMULESS,
18859 IX86_BUILTIN_COMUGTSS,
18860 IX86_BUILTIN_COMUGESS,
18861 IX86_BUILTIN_COMORDSS,
18862 IX86_BUILTIN_COMUNORDSS,
18863 IX86_BUILTIN_COMFALSESS,
18864 IX86_BUILTIN_COMTRUESS,
18866 IX86_BUILTIN_COMEQSD,
18867 IX86_BUILTIN_COMNESD,
18868 IX86_BUILTIN_COMLTSD,
18869 IX86_BUILTIN_COMLESD,
18870 IX86_BUILTIN_COMGTSD,
18871 IX86_BUILTIN_COMGESD,
18872 IX86_BUILTIN_COMUEQSD,
18873 IX86_BUILTIN_COMUNESD,
18874 IX86_BUILTIN_COMULTSD,
18875 IX86_BUILTIN_COMULESD,
18876 IX86_BUILTIN_COMUGTSD,
18877 IX86_BUILTIN_COMUGESD,
18878 IX86_BUILTIN_COMORDSD,
18879 IX86_BUILTIN_COMUNORDSD,
18880 IX86_BUILTIN_COMFALSESD,
18881 IX86_BUILTIN_COMTRUESD,
18883 IX86_BUILTIN_COMEQPS,
18884 IX86_BUILTIN_COMNEPS,
18885 IX86_BUILTIN_COMLTPS,
18886 IX86_BUILTIN_COMLEPS,
18887 IX86_BUILTIN_COMGTPS,
18888 IX86_BUILTIN_COMGEPS,
18889 IX86_BUILTIN_COMUEQPS,
18890 IX86_BUILTIN_COMUNEPS,
18891 IX86_BUILTIN_COMULTPS,
18892 IX86_BUILTIN_COMULEPS,
18893 IX86_BUILTIN_COMUGTPS,
18894 IX86_BUILTIN_COMUGEPS,
18895 IX86_BUILTIN_COMORDPS,
18896 IX86_BUILTIN_COMUNORDPS,
18897 IX86_BUILTIN_COMFALSEPS,
18898 IX86_BUILTIN_COMTRUEPS,
18900 IX86_BUILTIN_COMEQPD,
18901 IX86_BUILTIN_COMNEPD,
18902 IX86_BUILTIN_COMLTPD,
18903 IX86_BUILTIN_COMLEPD,
18904 IX86_BUILTIN_COMGTPD,
18905 IX86_BUILTIN_COMGEPD,
18906 IX86_BUILTIN_COMUEQPD,
18907 IX86_BUILTIN_COMUNEPD,
18908 IX86_BUILTIN_COMULTPD,
18909 IX86_BUILTIN_COMULEPD,
18910 IX86_BUILTIN_COMUGTPD,
18911 IX86_BUILTIN_COMUGEPD,
18912 IX86_BUILTIN_COMORDPD,
18913 IX86_BUILTIN_COMUNORDPD,
18914 IX86_BUILTIN_COMFALSEPD,
18915 IX86_BUILTIN_COMTRUEPD,
18917 IX86_BUILTIN_PCOMEQUB,
18918 IX86_BUILTIN_PCOMNEUB,
18919 IX86_BUILTIN_PCOMLTUB,
18920 IX86_BUILTIN_PCOMLEUB,
18921 IX86_BUILTIN_PCOMGTUB,
18922 IX86_BUILTIN_PCOMGEUB,
18923 IX86_BUILTIN_PCOMFALSEUB,
18924 IX86_BUILTIN_PCOMTRUEUB,
18925 IX86_BUILTIN_PCOMEQUW,
18926 IX86_BUILTIN_PCOMNEUW,
18927 IX86_BUILTIN_PCOMLTUW,
18928 IX86_BUILTIN_PCOMLEUW,
18929 IX86_BUILTIN_PCOMGTUW,
18930 IX86_BUILTIN_PCOMGEUW,
18931 IX86_BUILTIN_PCOMFALSEUW,
18932 IX86_BUILTIN_PCOMTRUEUW,
18933 IX86_BUILTIN_PCOMEQUD,
18934 IX86_BUILTIN_PCOMNEUD,
18935 IX86_BUILTIN_PCOMLTUD,
18936 IX86_BUILTIN_PCOMLEUD,
18937 IX86_BUILTIN_PCOMGTUD,
18938 IX86_BUILTIN_PCOMGEUD,
18939 IX86_BUILTIN_PCOMFALSEUD,
18940 IX86_BUILTIN_PCOMTRUEUD,
18941 IX86_BUILTIN_PCOMEQUQ,
18942 IX86_BUILTIN_PCOMNEUQ,
18943 IX86_BUILTIN_PCOMLTUQ,
18944 IX86_BUILTIN_PCOMLEUQ,
18945 IX86_BUILTIN_PCOMGTUQ,
18946 IX86_BUILTIN_PCOMGEUQ,
18947 IX86_BUILTIN_PCOMFALSEUQ,
18948 IX86_BUILTIN_PCOMTRUEUQ,
18950 IX86_BUILTIN_PCOMEQB,
18951 IX86_BUILTIN_PCOMNEB,
18952 IX86_BUILTIN_PCOMLTB,
18953 IX86_BUILTIN_PCOMLEB,
18954 IX86_BUILTIN_PCOMGTB,
18955 IX86_BUILTIN_PCOMGEB,
18956 IX86_BUILTIN_PCOMFALSEB,
18957 IX86_BUILTIN_PCOMTRUEB,
18958 IX86_BUILTIN_PCOMEQW,
18959 IX86_BUILTIN_PCOMNEW,
18960 IX86_BUILTIN_PCOMLTW,
18961 IX86_BUILTIN_PCOMLEW,
18962 IX86_BUILTIN_PCOMGTW,
18963 IX86_BUILTIN_PCOMGEW,
18964 IX86_BUILTIN_PCOMFALSEW,
18965 IX86_BUILTIN_PCOMTRUEW,
18966 IX86_BUILTIN_PCOMEQD,
18967 IX86_BUILTIN_PCOMNED,
18968 IX86_BUILTIN_PCOMLTD,
18969 IX86_BUILTIN_PCOMLED,
18970 IX86_BUILTIN_PCOMGTD,
18971 IX86_BUILTIN_PCOMGED,
18972 IX86_BUILTIN_PCOMFALSED,
18973 IX86_BUILTIN_PCOMTRUED,
18974 IX86_BUILTIN_PCOMEQQ,
18975 IX86_BUILTIN_PCOMNEQ,
18976 IX86_BUILTIN_PCOMLTQ,
18977 IX86_BUILTIN_PCOMLEQ,
18978 IX86_BUILTIN_PCOMGTQ,
18979 IX86_BUILTIN_PCOMGEQ,
18980 IX86_BUILTIN_PCOMFALSEQ,
18981 IX86_BUILTIN_PCOMTRUEQ,
18983 IX86_BUILTIN_MAX
18984 };
18986 /* Table for the ix86 builtin decls. */
18989 /* Table to record which ISA options the builtin needs. */
18992 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
18993 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
18994 * function decl in the ix86_builtins array. Returns the function decl or
18995 * NULL_TREE, if the builtin was not added.
18996 *
18997 * Record all builtins, even if it isn't an instruction set in the current ISA
18998 * in case the user uses function specific options for a different ISA. When
18999 * the builtin is expanded, check at that time whether it is valid. */
19003 {
19007 {
19012 }
19015 }
19017 /* Like def_builtin, but also marks the function decl "const". */
19022 {
19027 }
19029 /* Bits for builtin_description.flag. */
19031 /* Set when we don't support the comparison natively, and should
19032 swap_comparison in order to support it. */
19033 #define BUILTIN_DESC_SWAP_OPERANDS 1
19035 struct builtin_description
19036 {
19043 };
19046 {
19047 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
19048 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
19049 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
19050 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
19051 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
19052 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
19053 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
19054 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
19055 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
19056 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
19057 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
19058 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
19059 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
19060 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
19061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
19062 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
19063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
19064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
19065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
19066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
19067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
19068 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
19069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
19070 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
19071 };
19074 {
19075 /* SSE4.2 */
19076 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
19077 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
19078 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
19079 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
19080 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
19081 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
19082 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
19083 };
19086 {
19087 /* SSE4.2 */
19088 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
19089 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
19090 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
19091 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
19092 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
19093 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
19094 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
19095 };
19097 /* Special builtin types */
19098 enum ix86_special_builtin_type
19099 {
19100 SPECIAL_FTYPE_UNKNOWN,
19101 VOID_FTYPE_VOID,
19102 V16QI_FTYPE_PCCHAR,
19103 V4SF_FTYPE_PCFLOAT,
19104 V2DF_FTYPE_PCDOUBLE,
19105 V4SF_FTYPE_V4SF_PCV2SF,
19106 V2DF_FTYPE_V2DF_PCDOUBLE,
19107 V2DI_FTYPE_PV2DI,
19108 VOID_FTYPE_PV2SF_V4SF,
19109 VOID_FTYPE_PV2DI_V2DI,
19110 VOID_FTYPE_PCHAR_V16QI,
19111 VOID_FTYPE_PFLOAT_V4SF,
19112 VOID_FTYPE_PDOUBLE_V2DF,
19113 VOID_FTYPE_PDI_DI,
19114 VOID_FTYPE_PINT_INT
19115 };
19117 /* Builtin types */
19118 enum ix86_builtin_type
19119 {
19120 FTYPE_UNKNOWN,
19121 FLOAT128_FTYPE_FLOAT128,
19122 FLOAT_FTYPE_FLOAT,
19123 FLOAT128_FTYPE_FLOAT128_FLOAT128,
19124 INT_FTYPE_V2DI_V2DI_PTEST,
19125 INT64_FTYPE_V4SF,
19126 INT64_FTYPE_V2DF,
19127 INT_FTYPE_V16QI,
19128 INT_FTYPE_V8QI,
19129 INT_FTYPE_V4SF,
19130 INT_FTYPE_V2DF,
19131 V16QI_FTYPE_V16QI,
19132 V8HI_FTYPE_V8HI,
19133 V8HI_FTYPE_V16QI,
19134 V8QI_FTYPE_V8QI,
19135 V4SI_FTYPE_V4SI,
19136 V4SI_FTYPE_V16QI,
19137 V4SI_FTYPE_V8HI,
19138 V4SI_FTYPE_V4SF,
19139 V4SI_FTYPE_V2DF,
19140 V4HI_FTYPE_V4HI,
19141 V4SF_FTYPE_V4SF,
19142 V4SF_FTYPE_V4SF_VEC_MERGE,
19143 V4SF_FTYPE_V4SI,
19144 V4SF_FTYPE_V2DF,
19145 V2DI_FTYPE_V2DI,
19146 V2DI_FTYPE_V16QI,
19147 V2DI_FTYPE_V8HI,
19148 V2DI_FTYPE_V4SI,
19149 V2DF_FTYPE_V2DF,
19150 V2DF_FTYPE_V2DF_VEC_MERGE,
19151 V2DF_FTYPE_V4SI,
19152 V2DF_FTYPE_V4SF,
19153 V2DF_FTYPE_V2SI,
19154 V2SI_FTYPE_V2SI,
19155 V2SI_FTYPE_V4SF,
19156 V2SI_FTYPE_V2SF,
19157 V2SI_FTYPE_V2DF,
19158 V2SF_FTYPE_V2SF,
19159 V2SF_FTYPE_V2SI,
19160 V16QI_FTYPE_V16QI_V16QI,
19161 V16QI_FTYPE_V8HI_V8HI,
19162 V8QI_FTYPE_V8QI_V8QI,
19163 V8QI_FTYPE_V4HI_V4HI,
19164 V8HI_FTYPE_V8HI_V8HI,
19165 V8HI_FTYPE_V8HI_V8HI_COUNT,
19166 V8HI_FTYPE_V16QI_V16QI,
19167 V8HI_FTYPE_V4SI_V4SI,
19168 V8HI_FTYPE_V8HI_SI_COUNT,
19169 V4SI_FTYPE_V4SI_V4SI,
19170 V4SI_FTYPE_V4SI_V4SI_COUNT,
19171 V4SI_FTYPE_V8HI_V8HI,
19172 V4SI_FTYPE_V4SF_V4SF,
19173 V4SI_FTYPE_V2DF_V2DF,
19174 V4SI_FTYPE_V4SI_SI_COUNT,
19175 V4HI_FTYPE_V4HI_V4HI,
19176 V4HI_FTYPE_V4HI_V4HI_COUNT,
19177 V4HI_FTYPE_V8QI_V8QI,
19178 V4HI_FTYPE_V2SI_V2SI,
19179 V4HI_FTYPE_V4HI_SI_COUNT,
19180 V4SF_FTYPE_V4SF_V4SF,
19181 V4SF_FTYPE_V4SF_V4SF_SWAP,
19182 V4SF_FTYPE_V4SF_V2SI,
19183 V4SF_FTYPE_V4SF_V2DF,
19184 V4SF_FTYPE_V4SF_DI,
19185 V4SF_FTYPE_V4SF_SI,
19186 V2DI_FTYPE_V2DI_V2DI,
19187 V2DI_FTYPE_V2DI_V2DI_COUNT,
19188 V2DI_FTYPE_V16QI_V16QI,
19189 V2DI_FTYPE_V4SI_V4SI,
19190 V2DI_FTYPE_V2DI_V16QI,
19191 V2DI_FTYPE_V2DF_V2DF,
19192 V2DI_FTYPE_V2DI_SI_COUNT,
19193 V2SI_FTYPE_V2SI_V2SI,
19194 V2SI_FTYPE_V2SI_V2SI_COUNT,
19195 V2SI_FTYPE_V4HI_V4HI,
19196 V2SI_FTYPE_V2SF_V2SF,
19197 V2SI_FTYPE_V2SI_SI_COUNT,
19198 V2DF_FTYPE_V2DF_V2DF,
19199 V2DF_FTYPE_V2DF_V2DF_SWAP,
19200 V2DF_FTYPE_V2DF_V4SF,
19201 V2DF_FTYPE_V2DF_DI,
19202 V2DF_FTYPE_V2DF_SI,
19203 V2SF_FTYPE_V2SF_V2SF,
19204 V1DI_FTYPE_V1DI_V1DI,
19205 V1DI_FTYPE_V1DI_V1DI_COUNT,
19206 V1DI_FTYPE_V8QI_V8QI,
19207 V1DI_FTYPE_V2SI_V2SI,
19208 V1DI_FTYPE_V1DI_SI_COUNT,
19209 UINT64_FTYPE_UINT64_UINT64,
19210 UINT_FTYPE_UINT_UINT,
19211 UINT_FTYPE_UINT_USHORT,
19212 UINT_FTYPE_UINT_UCHAR,
19213 V8HI_FTYPE_V8HI_INT,
19214 V4SI_FTYPE_V4SI_INT,
19215 V4HI_FTYPE_V4HI_INT,
19216 V4SF_FTYPE_V4SF_INT,
19217 V2DI_FTYPE_V2DI_INT,
19218 V2DI2TI_FTYPE_V2DI_INT,
19219 V2DF_FTYPE_V2DF_INT,
19220 V16QI_FTYPE_V16QI_V16QI_V16QI,
19221 V4SF_FTYPE_V4SF_V4SF_V4SF,
19222 V2DF_FTYPE_V2DF_V2DF_V2DF,
19223 V16QI_FTYPE_V16QI_V16QI_INT,
19224 V8HI_FTYPE_V8HI_V8HI_INT,
19225 V4SI_FTYPE_V4SI_V4SI_INT,
19226 V4SF_FTYPE_V4SF_V4SF_INT,
19227 V2DI_FTYPE_V2DI_V2DI_INT,
19228 V2DI2TI_FTYPE_V2DI_V2DI_INT,
19229 V1DI2DI_FTYPE_V1DI_V1DI_INT,
19230 V2DF_FTYPE_V2DF_V2DF_INT,
19231 V2DI_FTYPE_V2DI_UINT_UINT,
19232 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
19233 };
19235 /* Special builtins with variable number of arguments. */
19237 {
19238 /* MMX */
19239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
19241 /* 3DNow! */
19242 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
19244 /* SSE */
19245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
19246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
19247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
19249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
19250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
19251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
19252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
19254 /* SSE or 3DNow!A */
19255 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
19256 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
19258 /* SSE2 */
19259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
19260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
19261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
19262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
19263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
19264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
19265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
19266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
19267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
19269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
19270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
19272 /* SSE3 */
19273 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
19275 /* SSE4.1 */
19276 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
19278 /* SSE4A */
19279 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
19280 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
19281 };
19283 /* Builtins with variable number of arguments. */
19285 {
19286 /* MMX */
19287 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19298 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19301 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19303 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19308 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19314 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19321 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
19323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
19325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
19326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
19327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
19329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
19331 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
19332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
19333 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
19334 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
19335 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
19336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
19338 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
19339 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
19340 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
19341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
19342 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
19343 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
19345 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
19346 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
19347 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
19348 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
19350 /* 3DNow! */
19351 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
19352 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
19353 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
19354 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
19356 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19357 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19358 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19359 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
19360 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
19361 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
19362 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19363 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19364 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19365 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19366 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19367 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19368 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19369 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19370 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19372 /* 3DNow!A */
19373 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
19374 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
19375 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
19376 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
19377 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19378 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19380 /* SSE */
19381 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
19382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19383 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19385 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
19388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
19389 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
19390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
19391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
19392 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
19394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19396 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19397 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19398 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
19406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
19407 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
19408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
19412 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
19413 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
19414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
19416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
19418 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
19419 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
19420 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19421 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
19422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
19423 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
19424 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19425 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19426 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19428 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19429 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19430 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19431 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19433 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19435 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19436 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19440 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19441 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
19445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
19446 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
19448 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
19450 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
19451 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
19452 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
19454 /* SSE MMX or 3Dnow!A */
19455 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19456 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19457 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19459 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19460 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19461 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19462 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19464 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
19465 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
19467 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
19469 /* SSE2 */
19470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
19473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
19474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
19475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
19476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
19478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
19479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
19480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
19481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
19482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
19484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
19486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
19487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
19488 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
19489 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
19491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
19492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
19493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
19495 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19496 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19497 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19498 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
19505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
19506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
19507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
19508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
19509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
19511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
19512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
19513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
19514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
19515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
19517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
19518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
19519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
19521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
19522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
19523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19525 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19526 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19530 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19532 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19533 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19539 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
19541 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19542 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19543 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19544 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19545 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19546 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19547 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19548 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19551 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19559 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19560 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
19562 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19563 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19564 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19565 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19574 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19577 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19578 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19579 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19584 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19586 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19587 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19588 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19589 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
19592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
19593 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
19595 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
19598 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
19599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
19601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
19603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
19604 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
19605 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
19606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
19608 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
19609 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
19610 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
19611 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
19612 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
19613 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
19614 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
19616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
19617 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
19618 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
19619 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
19620 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
19621 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
19622 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
19624 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
19625 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
19626 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
19627 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
19629 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
19630 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
19631 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
19633 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
19635 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
19636 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
19638 /* SSE2 MMX */
19639 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
19640 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
19642 /* SSE3 */
19643 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
19644 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19646 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19647 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19648 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19649 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19650 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19651 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19653 /* SSSE3 */
19654 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
19655 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
19656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
19657 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
19658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
19659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
19661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19662 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19670 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19671 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19672 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
19674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
19675 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19676 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19677 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19678 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19679 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19680 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19681 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19682 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19683 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19684 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19686 /* SSSE3. */
19687 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
19688 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
19690 /* SSE4.1 */
19691 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19692 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
19694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
19695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19696 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19698 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
19699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
19700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
19702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
19703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
19704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
19705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
19706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
19707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
19708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
19709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
19710 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
19711 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
19712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
19713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
19714 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
19716 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
19717 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19718 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19719 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19720 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19721 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19723 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19724 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19725 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19726 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
19727 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19729 /* SSE4.1 and SSE5 */
19730 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
19731 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
19732 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19733 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19735 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
19736 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
19737 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
19739 /* SSE4.2 */
19740 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19741 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
19742 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
19743 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
19744 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
19746 /* SSE4A */
19747 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
19748 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
19749 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
19750 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19752 /* AES */
19753 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
19754 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
19756 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19757 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19758 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19759 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19761 /* PCLMUL */
19762 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
19763 };
19765 /* SSE5 */
19767 MULTI_ARG_UNKNOWN,
19768 MULTI_ARG_3_SF,
19769 MULTI_ARG_3_DF,
19770 MULTI_ARG_3_DI,
19771 MULTI_ARG_3_SI,
19772 MULTI_ARG_3_SI_DI,
19773 MULTI_ARG_3_HI,
19774 MULTI_ARG_3_HI_SI,
19775 MULTI_ARG_3_QI,
19776 MULTI_ARG_3_PERMPS,
19777 MULTI_ARG_3_PERMPD,
19778 MULTI_ARG_2_SF,
19779 MULTI_ARG_2_DF,
19780 MULTI_ARG_2_DI,
19781 MULTI_ARG_2_SI,
19782 MULTI_ARG_2_HI,
19783 MULTI_ARG_2_QI,
19784 MULTI_ARG_2_DI_IMM,
19785 MULTI_ARG_2_SI_IMM,
19786 MULTI_ARG_2_HI_IMM,
19787 MULTI_ARG_2_QI_IMM,
19788 MULTI_ARG_2_SF_CMP,
19789 MULTI_ARG_2_DF_CMP,
19790 MULTI_ARG_2_DI_CMP,
19791 MULTI_ARG_2_SI_CMP,
19792 MULTI_ARG_2_HI_CMP,
19793 MULTI_ARG_2_QI_CMP,
19794 MULTI_ARG_2_DI_TF,
19795 MULTI_ARG_2_SI_TF,
19796 MULTI_ARG_2_HI_TF,
19797 MULTI_ARG_2_QI_TF,
19798 MULTI_ARG_2_SF_TF,
19799 MULTI_ARG_2_DF_TF,
19800 MULTI_ARG_1_SF,
19801 MULTI_ARG_1_DF,
19802 MULTI_ARG_1_DI,
19803 MULTI_ARG_1_SI,
19804 MULTI_ARG_1_HI,
19805 MULTI_ARG_1_QI,
19806 MULTI_ARG_1_SI_DI,
19807 MULTI_ARG_1_HI_DI,
19808 MULTI_ARG_1_HI_SI,
19809 MULTI_ARG_1_QI_DI,
19810 MULTI_ARG_1_QI_SI,
19811 MULTI_ARG_1_QI_HI,
19812 MULTI_ARG_1_PH2PS,
19813 MULTI_ARG_1_PS2PH
19814 };
19817 {
19818 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
19819 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
19820 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
19821 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
19822 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
19823 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
19824 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
19825 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
19826 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
19827 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
19828 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
19829 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
19830 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
19831 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
19832 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
19833 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
19834 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
19835 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
19836 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
19837 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
19838 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
19839 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
19840 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
19841 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
19842 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
19843 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
19844 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
19845 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
19846 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
19847 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
19848 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
19849 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
19850 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
19851 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
19852 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
19853 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
19854 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
19855 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
19856 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
19857 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
19858 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
19859 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
19860 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
19861 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
19862 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
19863 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
19864 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
19865 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
19866 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
19867 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
19868 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
19869 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
19870 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
19871 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
19872 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
19873 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
19874 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
19875 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
19876 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
19877 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
19878 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
19879 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
19880 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
19881 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
19882 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
19883 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
19884 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
19885 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
19886 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
19887 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
19888 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
19889 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
19890 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
19891 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
19892 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
19894 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
19895 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
19896 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
19897 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
19898 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
19899 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
19900 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
19901 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
19902 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
19903 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
19904 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
19905 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
19906 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
19907 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
19908 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
19909 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
19911 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
19912 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
19913 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
19914 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
19915 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
19916 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
19917 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
19918 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
19919 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
19920 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
19921 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
19922 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
19923 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
19924 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
19925 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
19926 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
19928 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
19929 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
19930 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
19931 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
19932 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
19933 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
19934 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
19935 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
19936 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
19937 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
19938 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
19939 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
19940 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
19941 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
19942 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
19943 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
19945 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
19946 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
19947 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
19948 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
19949 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
19950 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
19951 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
19952 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
19953 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
19954 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
19955 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
19956 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
19957 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
19958 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
19959 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
19960 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
19962 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
19963 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
19964 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
19965 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
19966 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
19967 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
19968 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
19970 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
19971 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
19972 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
19973 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
19974 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
19975 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
19976 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
19978 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
19979 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
19980 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
19981 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
19982 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
19983 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
19984 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
19986 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
19987 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
19988 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
19989 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
19990 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
19991 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
19992 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
19994 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
19995 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
19996 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
19997 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
19998 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
19999 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
20000 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
20002 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
20003 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
20004 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
20005 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
20006 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
20007 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
20008 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
20010 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
20011 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
20012 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
20013 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
20014 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
20015 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
20016 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
20018 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
20019 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
20020 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
20021 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
20022 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
20023 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
20024 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
20026 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
20027 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
20028 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
20029 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
20030 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
20031 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
20032 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
20033 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
20035 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
20036 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
20037 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
20038 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
20039 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
20040 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
20041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
20042 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
20044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
20045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
20046 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
20047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
20048 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
20049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
20050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
20051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
20052 };
20054 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
20055 in the current target ISA to allow the user to compile particular modules
20056 with different target specific options that differ from the command line
20057 options. */
20058 static void
20060 {
20066 tree V1DI_type_node
20069 tree V2DI_type_node
20079 tree pcchar_type_node
20082 tree pcfloat_type_node
20085 tree pcv2sf_type_node
20090 /* Comparisons. */
20091 tree int_ftype_v4sf_v4sf
20094 tree v4si_ftype_v4sf_v4sf
20097 /* MMX/SSE/integer conversions. */
20098 tree int_ftype_v4sf
20101 tree int64_ftype_v4sf
20104 tree int_ftype_v8qi
20106 tree v4sf_ftype_v4sf_int
20109 tree v4sf_ftype_v4sf_int64
20112 NULL_TREE);
20113 tree v4sf_ftype_v4sf_v2si
20117 /* Miscellaneous. */
20118 tree v8qi_ftype_v4hi_v4hi
20121 tree v4hi_ftype_v2si_v2si
20124 tree v4sf_ftype_v4sf_v4sf_int
20128 tree v2si_ftype_v4hi_v4hi
20131 tree v4hi_ftype_v4hi_int
20134 tree v2si_ftype_v2si_int
20137 tree v1di_ftype_v1di_int
20141 tree void_ftype_void
20143 tree void_ftype_unsigned
20145 tree void_ftype_unsigned_unsigned
20148 tree void_ftype_pcvoid_unsigned_unsigned
20151 NULL_TREE);
20152 tree unsigned_ftype_void
20154 tree v2si_ftype_v4sf
20156 /* Loads/stores. */
20157 tree void_ftype_v8qi_v8qi_pchar
20161 tree v4sf_ftype_pcfloat
20163 tree v4sf_ftype_v4sf_pcv2sf
20166 tree void_ftype_pv2sf_v4sf
20169 tree void_ftype_pfloat_v4sf
20172 tree void_ftype_pdi_di
20175 NULL_TREE);
20176 tree void_ftype_pv2di_v2di
20179 /* Normal vector unops. */
20180 tree v4sf_ftype_v4sf
20182 tree v16qi_ftype_v16qi
20184 tree v8hi_ftype_v8hi
20186 tree v4si_ftype_v4si
20188 tree v8qi_ftype_v8qi
20190 tree v4hi_ftype_v4hi
20193 /* Normal vector binops. */
20194 tree v4sf_ftype_v4sf_v4sf
20197 tree v8qi_ftype_v8qi_v8qi
20200 tree v4hi_ftype_v4hi_v4hi
20203 tree v2si_ftype_v2si_v2si
20206 tree v1di_ftype_v1di_v1di
20209 tree v1di_ftype_v1di_v1di_int
20213 tree v2si_ftype_v2sf
20215 tree v2sf_ftype_v2si
20217 tree v2si_ftype_v2si
20219 tree v2sf_ftype_v2sf
20221 tree v2sf_ftype_v2sf_v2sf
20224 tree v2si_ftype_v2sf_v2sf
20231 tree int_ftype_v2df_v2df
20235 tree void_ftype_pcvoid
20237 tree v4sf_ftype_v4si
20239 tree v4si_ftype_v4sf
20241 tree v2df_ftype_v4si
20243 tree v4si_ftype_v2df
20245 tree v4si_ftype_v2df_v2df
20248 tree v2si_ftype_v2df
20250 tree v4sf_ftype_v2df
20252 tree v2df_ftype_v2si
20254 tree v2df_ftype_v4sf
20256 tree int_ftype_v2df
20258 tree int64_ftype_v2df
20261 tree v2df_ftype_v2df_int
20264 tree v2df_ftype_v2df_int64
20267 NULL_TREE);
20268 tree v4sf_ftype_v4sf_v2df
20271 tree v2df_ftype_v2df_v4sf
20274 tree v2df_ftype_v2df_v2df_int
20277 integer_type_node,
20278 NULL_TREE);
20279 tree v2df_ftype_v2df_pcdouble
20282 tree void_ftype_pdouble_v2df
20285 tree void_ftype_pint_int
20288 tree void_ftype_v16qi_v16qi_pchar
20292 tree v2df_ftype_pcdouble
20294 tree v2df_ftype_v2df_v2df
20297 tree v16qi_ftype_v16qi_v16qi
20300 tree v8hi_ftype_v8hi_v8hi
20303 tree v4si_ftype_v4si_v4si
20306 tree v2di_ftype_v2di_v2di
20309 tree v2di_ftype_v2df_v2df
20312 tree v2df_ftype_v2df
20314 tree v2di_ftype_v2di_int
20317 tree v2di_ftype_v2di_v2di_int
20320 tree v4si_ftype_v4si_int
20323 tree v8hi_ftype_v8hi_int
20326 tree v4si_ftype_v8hi_v8hi
20329 tree v1di_ftype_v8qi_v8qi
20332 tree v1di_ftype_v2si_v2si
20335 tree v2di_ftype_v16qi_v16qi
20338 tree v2di_ftype_v4si_v4si
20341 tree int_ftype_v16qi
20343 tree v16qi_ftype_pcchar
20345 tree void_ftype_pchar_v16qi
20349 tree v2di_ftype_v2di_unsigned_unsigned
20352 NULL_TREE);
20353 tree v2di_ftype_v2di_v2di_unsigned_unsigned
20356 NULL_TREE);
20357 tree v2di_ftype_v2di_v16qi
20359 NULL_TREE);
20360 tree v2df_ftype_v2df_v2df_v2df
20364 tree v4sf_ftype_v4sf_v4sf_v4sf
20368 tree v8hi_ftype_v16qi
20370 NULL_TREE);
20371 tree v4si_ftype_v16qi
20373 NULL_TREE);
20374 tree v2di_ftype_v16qi
20376 NULL_TREE);
20377 tree v4si_ftype_v8hi
20379 NULL_TREE);
20380 tree v2di_ftype_v8hi
20382 NULL_TREE);
20383 tree v2di_ftype_v4si
20385 NULL_TREE);
20386 tree v2di_ftype_pv2di
20388 NULL_TREE);
20389 tree v16qi_ftype_v16qi_v16qi_int
20392 NULL_TREE);
20393 tree v16qi_ftype_v16qi_v16qi_v16qi
20396 NULL_TREE);
20397 tree v8hi_ftype_v8hi_v8hi_int
20400 NULL_TREE);
20401 tree v4si_ftype_v4si_v4si_int
20404 NULL_TREE);
20405 tree int_ftype_v2di_v2di
20408 NULL_TREE);
20409 tree int_ftype_v16qi_int_v16qi_int_int
20411 V16QI_type_node,
20412 integer_type_node,
20413 V16QI_type_node,
20414 integer_type_node,
20415 integer_type_node,
20416 NULL_TREE);
20417 tree v16qi_ftype_v16qi_int_v16qi_int_int
20419 V16QI_type_node,
20420 integer_type_node,
20421 V16QI_type_node,
20422 integer_type_node,
20423 integer_type_node,
20424 NULL_TREE);
20425 tree int_ftype_v16qi_v16qi_int
20427 V16QI_type_node,
20428 V16QI_type_node,
20429 integer_type_node,
20430 NULL_TREE);
20432 /* SSE5 instructions */
20433 tree v2di_ftype_v2di_v2di_v2di
20435 V2DI_type_node,
20436 V2DI_type_node,
20437 V2DI_type_node,
20438 NULL_TREE);
20440 tree v4si_ftype_v4si_v4si_v4si
20442 V4SI_type_node,
20443 V4SI_type_node,
20444 V4SI_type_node,
20445 NULL_TREE);
20447 tree v4si_ftype_v4si_v4si_v2di
20449 V4SI_type_node,
20450 V4SI_type_node,
20451 V2DI_type_node,
20452 NULL_TREE);
20454 tree v8hi_ftype_v8hi_v8hi_v8hi
20456 V8HI_type_node,
20457 V8HI_type_node,
20458 V8HI_type_node,
20459 NULL_TREE);
20461 tree v8hi_ftype_v8hi_v8hi_v4si
20463 V8HI_type_node,
20464 V8HI_type_node,
20465 V4SI_type_node,
20466 NULL_TREE);
20468 tree v2df_ftype_v2df_v2df_v16qi
20470 V2DF_type_node,
20471 V2DF_type_node,
20472 V16QI_type_node,
20473 NULL_TREE);
20475 tree v4sf_ftype_v4sf_v4sf_v16qi
20477 V4SF_type_node,
20478 V4SF_type_node,
20479 V16QI_type_node,
20480 NULL_TREE);
20482 tree v2di_ftype_v2di_si
20484 V2DI_type_node,
20485 integer_type_node,
20486 NULL_TREE);
20488 tree v4si_ftype_v4si_si
20490 V4SI_type_node,
20491 integer_type_node,
20492 NULL_TREE);
20494 tree v8hi_ftype_v8hi_si
20496 V8HI_type_node,
20497 integer_type_node,
20498 NULL_TREE);
20500 tree v16qi_ftype_v16qi_si
20502 V16QI_type_node,
20503 integer_type_node,
20504 NULL_TREE);
20505 tree v4sf_ftype_v4hi
20507 V4HI_type_node,
20508 NULL_TREE);
20510 tree v4hi_ftype_v4sf
20512 V4SF_type_node,
20513 NULL_TREE);
20515 tree v2di_ftype_v2di
20518 tree v16qi_ftype_v8hi_v8hi
20521 NULL_TREE);
20522 tree v8hi_ftype_v4si_v4si
20525 NULL_TREE);
20526 tree v8hi_ftype_v16qi_v16qi
20529 NULL_TREE);
20530 tree v4hi_ftype_v8qi_v8qi
20533 NULL_TREE);
20534 tree unsigned_ftype_unsigned_uchar
20536 unsigned_type_node,
20537 unsigned_char_type_node,
20538 NULL_TREE);
20539 tree unsigned_ftype_unsigned_ushort
20541 unsigned_type_node,
20542 short_unsigned_type_node,
20543 NULL_TREE);
20544 tree unsigned_ftype_unsigned_unsigned
20546 unsigned_type_node,
20547 unsigned_type_node,
20548 NULL_TREE);
20549 tree uint64_ftype_uint64_uint64
20551 long_long_unsigned_type_node,
20552 long_long_unsigned_type_node,
20553 NULL_TREE);
20554 tree float_ftype_float
20556 float_type_node,
20557 NULL_TREE);
20559 tree ftype;
20561 /* Add all special builtins with variable number of operands. */
20565 {
20566 tree type;
20572 {
20617 }
20620 }
20622 /* Add all builtins with variable number of operands. */
20626 {
20627 tree type;
20633 {
20942 }
20945 }
20947 /* pcmpestr[im] insns. */
20951 {
20954 else
20957 }
20959 /* pcmpistr[im] insns. */
20963 {
20966 else
20969 }
20971 /* comi/ucomi insns. */
20975 else
20978 /* SSE */
20979 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
20980 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
20982 /* SSE or 3DNow!A */
20983 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
20985 /* SSE2 */
20986 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
20988 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
20989 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
20991 /* SSE3. */
20992 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
20993 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
20995 /* AES */
20996 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
20997 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
20998 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
20999 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
21000 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
21001 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
21003 /* PCLMUL */
21004 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
21006 /* Access to the vec_init patterns. */
21009 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
21012 short_integer_type_node,
21013 short_integer_type_node,
21015 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
21022 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
21024 /* Access to the vec_extract patterns. */
21027 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
21031 NULL_TREE);
21032 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
21036 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
21040 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
21044 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
21048 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
21052 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
21056 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
21058 /* Access to the vec_set patterns. */
21060 intDI_type_node,
21062 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
21065 float_type_node,
21067 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
21070 intSI_type_node,
21072 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
21075 intHI_type_node,
21077 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
21080 intHI_type_node,
21082 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
21085 intQI_type_node,
21087 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
21089 /* Add SSE5 multi-arg argument instructions */
21091 {
21098 {
21148 }
21152 }
21153 }
21155 /* Internal method for ix86_init_builtins. */
21157 static void
21159 {
21171 sysv_va_ref =
21174 fnvoid_va_end_ms =
21176 fnvoid_va_start_ms =
21178 fnvoid_va_end_sysv =
21180 fnvoid_va_start_sysv =
21182 NULL_TREE);
21183 fnvoid_va_copy_ms =
21185 NULL_TREE);
21186 fnvoid_va_copy_sysv =
21202 }
21204 static void
21206 {
21210 /* The __float80 type. */
21214 else
21215 {
21216 /* The __float80 type. */
21223 }
21225 /* The __float128 type. */
21231 /* TFmode support builtins. */
21238 /* We will expand them to normal call if SSE2 isn't available since
21239 they are used by libgcc. */
21241 float128_type_node,
21242 NULL_TREE);
21250 float128_type_node,
21251 float128_type_node,
21252 NULL_TREE);
21262 }
21264 /* Errors in the source file can cause expand_expr to return const0_rtx
21265 where we expect a vector. To avoid crashing, use one of the vector
21266 clear instructions. */
21267 static rtx
21269 {
21273 }
21275 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
21277 static rtx
21279 {
21280 rtx pat;
21300 {
21304 }
21318 }
21320 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
21322 static rtx
21326 {
21327 rtx pat;
21335 rtx op;
21342 {
21413 }
21423 {
21430 {
21432 {
21435 }
21436 }
21437 else
21438 {
21442 /* If we aren't optimizing, only allow one memory operand to be
21443 generated. */
21445 num_memory++;
21453 }
21457 }
21460 {
21471 else
21472 {
21478 }
21487 }
21494 }
21496 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
21497 insns with vec_merge. */
21499 static rtx
21501 rtx target)
21502 {
21503 rtx pat;
21530 }
21532 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
21534 static rtx
21537 {
21538 rtx pat;
21543 rtx op2;
21554 /* Swap operands if we have a comparison that isn't available in
21555 hardware. */
21557 {
21562 }
21582 }
21584 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
21586 static rtx
21588 rtx target)
21589 {
21590 rtx pat;
21604 /* Swap operands if we have a comparison that isn't available in
21605 hardware. */
21607 {
21611 }
21632 const0_rtx)));
21635 }
21637 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
21639 static rtx
21641 rtx target)
21642 {
21643 rtx pat;
21676 const0_rtx)));
21679 }
21681 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
21683 static rtx
21686 {
21687 rtx pat;
21725 {
21728 }
21731 {
21740 }
21742 {
21751 }
21752 else
21753 {
21760 }
21768 {
21773 emit_insn
21777 FLAGS_REG),
21778 const0_rtx)));
21780 }
21781 else
21783 }
21786 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
21788 static rtx
21791 {
21792 rtx pat;
21820 {
21823 }
21826 {
21835 }
21837 {
21846 }
21847 else
21848 {
21855 }
21863 {
21868 emit_insn
21872 FLAGS_REG),
21873 const0_rtx)));
21875 }
21876 else
21878 }
21880 /* Subroutine of ix86_expand_builtin to take care of insns with
21881 variable number of operands. */
21883 static rtx
21886 {
21891 struct
21892 {
21893 rtx op;
21905 {
22063 }
22068 {
22071 }
22074 {
22081 }
22082 else
22083 {
22086 }
22089 {
22096 {
22097 /* SIMD shift insns take either an 8-bit immediate or
22098 register as count. But builtin functions take int as
22099 count. If count doesn't match, we put it in register. */
22101 {
22105 }
22106 }
22108 {
22111 {
22126 {
22129 {
22132 }
22138 }
22140 }
22141 }
22142 else
22143 {
22147 /* If we aren't optimizing, only allow one memory operand to
22148 be generated. */
22150 num_memory++;
22153 {
22156 }
22157 else
22158 {
22161 }
22162 }
22166 }
22169 {
22186 }
22193 }
22195 /* Subroutine of ix86_expand_builtin to take care of special insns
22196 with variable number of operands. */
22198 static rtx
22201 {
22202 tree arg;
22205 struct
22206 {
22207 rtx op;
22217 {
22238 /* Reserve memory operand for target. */
22249 }
22254 {
22260 }
22261 else
22262 {
22269 }
22272 {
22281 {
22284 {
22288 }
22289 }
22290 else
22291 {
22293 {
22294 /* This must be the memory operand. */
22298 }
22299 else
22300 {
22301 /* This must be register. */
22308 }
22309 }
22313 }
22316 {
22325 }
22331 }
22333 /* Return the integer constant in ARG. Constrain it to be in the range
22334 of the subparts of VEC_TYPE; issue an error if not. */
22336 static int
22338 {
22343 {
22346 }
22349 }
22351 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
22352 ix86_expand_vector_init. We DO have language-level syntax for this, in
22353 the form of (type){ init-list }. Except that since we can't place emms
22354 instructions from inside the compiler, we can't allow the use of MMX
22355 registers unless the user explicitly asks for it. So we do *not* define
22356 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
22357 we have builtins invoked by mmintrin.h that gives us license to emit
22358 these sorts of instructions. */
22360 static rtx
22362 {
22372 {
22375 }
22382 }
22384 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
22385 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
22386 had a language-level syntax for referencing vector elements. */
22388 static rtx
22390 {
22394 rtx op0;
22414 }
22416 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
22417 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
22418 a language-level syntax for referencing vector elements. */
22420 static rtx
22422 {
22446 /* OP0 is the source of these builtin functions and shouldn't be
22447 modified. Create a copy, use it and return it as target. */
22453 }
22455 /* Expand an expression EXP that calls a built-in function,
22456 with result going to TARGET if that's convenient
22457 (and in mode MODE if that's convenient).
22458 SUBTARGET may be used as the target for computing one of EXP's operands.
22459 IGNORE is nonzero if the value is to be ignored. */
22461 static rtx
22465 {
22475 /* Determine whether the builtin function is available under the current ISA.
22476 Originally the builtin was not created if it wasn't applicable to the
22477 current ISA based on the command line switches. With function specific
22478 options, we need to check in the context of the function making the call
22479 whether it is supported. */
22482 {
22488 else
22489 {
22493 }
22495 }
22498 {
22502 ? CODE_FOR_mmx_maskmovq
22504 /* Note the arg order is different from the operand order. */
22604 {
22605 REAL_VALUE_TYPE inf;
22606 rtx tmp;
22618 }
22622 }
22635 {
22639 /* Emit a normal call if SSE2 isn't available. */
22643 }
22668 }
22670 /* Returns a function decl for a vectorized version of the builtin function
22671 with builtin function code FN and the result vector type TYPE, or NULL_TREE
22672 if it is not available. */
22674 static tree
22676 tree type_in)
22677 {
22691 {
22717 ;
22718 }
22720 /* Dispatch to a handler for a vectorization library. */
22725 }
22727 /* Handler for an SVML-style interface to
22728 a library with vectorized intrinsics. */
22730 static tree
22732 {
22740 /* The SVML is suitable for unsafe math only. */
22753 {
22800 }
22809 {
22812 }
22813 else
22816 /* Convert to uppercase. */
22822 arity++;
22826 else
22829 /* Build a function declaration for the vectorized function. */
22837 }
22839 /* Handler for an ACML-style interface to
22840 a library with vectorized intrinsics. */
22842 static tree
22844 {
22852 /* The ACML is 64bits only and suitable for unsafe math only as
22853 it does not correctly support parts of IEEE with the required
22854 precision such as denormals. */
22868 {
22898 }
22906 arity++;
22910 else
22913 /* Build a function declaration for the vectorized function. */
22921 }
22924 /* Returns a decl of a function that implements conversion of the
22925 input vector of type TYPE, or NULL_TREE if it is not available. */
22927 static tree
22929 {
22934 {
22937 {
22942 }
22946 {
22951 }
22955 }
22956 }
22958 /* Returns a code for a target-specific builtin that implements
22959 reciprocal of the function, or NULL_TREE if not available. */
22961 static tree
22964 {
22971 /* Machine dependent builtins. */
22973 {
22974 /* Vectorized version of sqrt to rsqrt conversion. */
22980 }
22981 else
22982 /* Normal builtins. */
22984 {
22985 /* Sqrt to rsqrt conversion. */
22991 }
22992 }
22994 /* Store OPERAND to the memory after reload is completed. This means
22995 that we can't easily use assign_stack_local. */
22996 rtx
22998 {
22999 rtx result;
23003 {
23006 stack_pointer_rtx,
23009 }
23011 {
23013 {
23017 /* FALLTHRU */
23023 stack_pointer_rtx)),
23024 operand));
23028 }
23030 }
23031 else
23032 {
23034 {
23036 {
23043 stack_pointer_rtx)),
23049 stack_pointer_rtx)),
23051 }
23054 /* Store HImodes as SImodes. */
23056 /* FALLTHRU */
23062 stack_pointer_rtx)),
23063 operand));
23067 }
23069 }
23071 }
23073 /* Free operand from the memory. */
23074 void
23076 {
23078 {
23083 else
23085 /* Use LEA to deallocate stack space. In peephole2 it will be converted
23086 to pop or add instruction if registers are available. */
23090 }
23091 }
23093 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
23094 QImode must go into class Q_REGS.
23095 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
23096 movdf to do mem-to-mem moves through integer regs. */
23097 enum reg_class
23099 {
23102 /* We're only allowed to return a subclass of CLASS. Many of the
23103 following checks fail for NO_REGS, so eliminate that early. */
23107 /* All classes can load zeros. */
23111 /* Force constants into memory if we are loading a (nonzero) constant into
23112 an MMX or SSE register. This is because there are no MMX/SSE instructions
23113 to load from a constant. */
23118 /* Prefer SSE regs only, if we can use them for math. */
23122 /* Floating-point constants need more complex checks. */
23124 {
23125 /* General regs can load everything. */
23129 /* Floats can load 0 and 1 plus some others. Note that we eliminated
23130 zero above. We only want to wind up preferring 80387 registers if
23131 we plan on doing computation with them. */
23134 {
23135 /* Limit class to non-sse. */
23144 }
23147 }
23149 /* Generally when we see PLUS here, it's the function invariant
23150 (plus soft-fp const_int). Which can only be computed into general
23151 regs. */
23155 /* QImode constants are easy to load, but non-constant QImode data
23156 must go into Q_REGS. */
23158 {
23164 }
23167 }
23169 /* Discourage putting floating-point values in SSE registers unless
23170 SSE math is being used, and likewise for the 387 registers. */
23171 enum reg_class
23173 {
23176 /* Restrict the output reload class to the register bank that we are doing
23177 math on. If we would like not to return a subset of CLASS, reject this
23178 alternative: if reload cannot do this, it will still use its choice. */
23184 {
23189 else
23191 }
23194 }
23196 static enum reg_class
23200 {
23201 /* QImode spills from non-QI registers require
23202 intermediate register on 32bit targets. */
23207 {
23212 else
23218 /* Return Q_REGS if the operand is in memory. */
23221 }
23224 }
23226 /* If we are copying between general and FP registers, we need a memory
23227 location. The same is true for SSE and MMX registers.
23229 To optimize register_move_cost performance, allow inline variant.
23231 The macro can't work reliably when one of the CLASSES is class containing
23232 registers from multiple units (SSE, MMX, integer). We avoid this by never
23233 combining those units in single alternative in the machine description.
23234 Ensure that this constraint holds to avoid unexpected surprises.
23236 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
23237 enforce these sanity checks. */
23242 {
23249 {
23252 }
23257 /* ??? This is a lie. We do have moves between mmx/general, and for
23258 mmx/sse2. But by saying we need secondary memory we discourage the
23259 register allocator from using the mmx registers unless needed. */
23264 {
23265 /* SSE1 doesn't have any direct moves from other classes. */
23269 /* If the target says that inter-unit moves are more expensive
23270 than moving through memory, then don't generate them. */
23274 /* Between SSE and general, we have moves no larger than word size. */
23277 }
23280 }
23282 int
23285 {
23287 }
23289 /* Return true if the registers in CLASS cannot represent the change from
23290 modes FROM to TO. */
23292 bool
23295 {
23299 /* x87 registers can't do subreg at all, as all values are reformatted
23300 to extended precision. */
23305 {
23306 /* Vector registers do not support QI or HImode loads. If we don't
23307 disallow a change to these modes, reload will assume it's ok to
23308 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
23309 the vec_dupv4hi pattern. */
23313 /* Vector registers do not support subreg with nonzero offsets, which
23314 are otherwise valid for integer registers. Since we can't see
23315 whether we have a nonzero offset from here, prohibit all
23316 nonparadoxical subregs changing size. */
23319 }
23322 }
23324 /* Return the cost of moving data of mode M between a
23325 register and memory. A value of 2 is the default; this cost is
23326 relative to those in `REGISTER_MOVE_COST'.
23328 This function is used extensively by register_move_cost that is used to
23329 build tables at startup. Make it inline in this case.
23330 When IN is 2, return maximum of in and out move cost.
23332 If moving between registers and memory is more expensive than
23333 between two registers, you should define this macro to express the
23334 relative cost.
23336 Model also increased moving costs of QImode registers in non
23337 Q_REGS classes.
23338 */
23342 {
23345 {
23348 {
23360 }
23364 }
23366 {
23369 {
23381 }
23385 }
23387 {
23390 {
23399 }
23403 }
23405 {
23408 {
23413 else
23418 }
23419 else
23420 {
23425 else
23427 }
23434 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
23441 else
23445 }
23446 }
23448 int
23450 {
23452 }
23455 /* Return the cost of moving data from a register in class CLASS1 to
23456 one in class CLASS2.
23458 It is not required that the cost always equal 2 when FROM is the same as TO;
23459 on some machines it is expensive to move between registers if they are not
23460 general registers. */
23462 int
23465 {
23466 /* In case we require secondary memory, compute cost of the store followed
23467 by load. In order to avoid bad register allocation choices, we need
23468 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
23471 {
23477 /* In case of copying from general_purpose_register we may emit multiple
23478 stores followed by single load causing memory size mismatch stall.
23479 Count this as arbitrarily high cost of 20. */
23483 /* In the case of FP/MMX moves, the registers actually overlap, and we
23484 have to switch modes in order to treat them differently. */
23490 }
23492 /* Moves between SSE/MMX and integer unit are expensive. */
23496 /* ??? By keeping returned value relatively high, we limit the number
23497 of moves between integer and MMX/SSE registers for all targets.
23498 Additionally, high value prevents problem with x86_modes_tieable_p(),
23499 where integer modes in MMX/SSE registers are not tieable
23500 because of missing QImode and HImode moves to, from or between
23501 MMX/SSE registers. */
23511 }
23513 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
23515 bool
23517 {
23518 /* Flags and only flags can only hold CCmode values. */
23528 {
23529 /* We implement the move patterns for all vector modes into and
23530 out of SSE registers, even when no operation instructions
23531 are available. */
23536 }
23538 {
23539 /* We implement the move patterns for 3DNOW modes even in MMX mode,
23540 so if the register is available at all, then we can move data of
23541 the given mode into or out of it. */
23544 }
23547 {
23548 /* Take care for QImode values - they can be in non-QI regs,
23549 but then they do cause partial register stalls. */
23555 }
23556 /* We handle both integer and floats in the general purpose registers. */
23563 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
23564 on to use that value in smaller contexts, this can easily force a
23565 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
23566 supporting DImode, allow it. */
23571 }
23573 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
23574 tieable integer mode. */
23576 static bool
23578 {
23580 {
23593 }
23594 }
23596 /* Return true if MODE1 is accessible in a register that can hold MODE2
23597 without copying. That is, all register classes that can hold MODE2
23598 can also hold MODE1. */
23600 bool
23602 {
23610 /* MODE2 being XFmode implies fp stack or general regs, which means we
23611 can tie any smaller floating point modes to it. Note that we do not
23612 tie this with TFmode. */
23616 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
23617 that we can tie it with SFmode. */
23621 /* If MODE2 is only appropriate for an SSE register, then tie with
23622 any other mode acceptable to SSE registers. */
23628 /* If MODE2 is appropriate for an MMX register, then tie
23629 with any other mode acceptable to MMX registers. */
23636 }
23638 /* Compute a (partial) cost for rtx X. Return true if the complete
23639 cost has been computed, and false if subexpressions should be
23640 scanned. In either case, *TOTAL contains the cost result. */
23642 static bool
23644 {
23649 {
23659 && (!TARGET_64BIT
23664 else
23671 else
23673 {
23682 /* Start with (MEM (SYMBOL_REF)), since that's where
23683 it'll probably end up. Add a penalty for size. */
23688 }
23692 /* The zero extensions is often completely free on x86_64, so make
23693 it as cheap as possible. */
23699 else
23710 {
23713 {
23716 }
23719 {
23722 }
23723 }
23724 /* FALLTHRU */
23731 {
23733 {
23736 else
23738 }
23739 else
23740 {
23743 else
23745 }
23746 }
23747 else
23748 {
23751 else
23753 }
23758 {
23759 /* ??? SSE scalar cost should be used here. */
23762 }
23764 {
23767 }
23769 {
23770 /* ??? SSE vector cost should be used here. */
23773 }
23774 else
23775 {
23780 {
23783 nbits++;
23784 }
23785 else
23786 /* This is arbitrary. */
23789 /* Compute costs correctly for widening multiplication. */
23793 {
23800 {
23804 else
23806 }
23810 }
23817 }
23824 /* ??? SSE cost should be used here. */
23829 /* ??? SSE vector cost should be used here. */
23831 else
23838 {
23843 {
23846 {
23850 outer_code);
23853 }
23854 }
23857 {
23860 {
23865 }
23866 }
23868 {
23874 }
23875 }
23876 /* FALLTHRU */
23880 {
23881 /* ??? SSE cost should be used here. */
23884 }
23886 {
23889 }
23891 {
23892 /* ??? SSE vector cost should be used here. */
23895 }
23896 /* FALLTHRU */
23902 {
23909 }
23910 /* FALLTHRU */
23914 {
23915 /* ??? SSE cost should be used here. */
23918 }
23920 {
23923 }
23925 {
23926 /* ??? SSE vector cost should be used here. */
23929 }
23930 /* FALLTHRU */
23935 else
23944 {
23945 /* This kind of construct is implemented using test[bwl].
23946 Treat it as if we had an AND. */
23951 }
23961 /* ??? SSE cost should be used here. */
23966 /* ??? SSE vector cost should be used here. */
23972 /* ??? SSE cost should be used here. */
23977 /* ??? SSE vector cost should be used here. */
23988 }
23989 }
23991 #if TARGET_MACHO
23995 /* Given a symbol name and its associated stub, write out the
23996 definition of the stub. */
23998 void
24000 {
24005 /* For 64-bit we shouldn't get here. */
24008 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24023 else
24030 {
24034 }
24035 else
24041 {
24044 }
24045 else
24054 }
24056 void
24058 {
24061 }
24064 /* Order the registers for register allocator. */
24066 void
24068 {
24072 /* First allocate the local general purpose registers. */
24077 /* Global general purpose registers. */
24082 /* x87 registers come first in case we are doing FP math
24083 using them. */
24088 /* SSE registers. */
24094 /* x87 registers. */
24102 /* Initialize the rest of array as we do not allocate some registers
24103 at all. */
24106 }
24108 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
24109 struct attribute_spec.handler. */
24110 static tree
24112 tree args ATTRIBUTE_UNUSED,
24114 {
24119 {
24124 }
24126 {
24131 }
24133 /* Can combine regparm with all attributes but fastcall. */
24135 {
24137 {
24139 }
24142 }
24144 {
24146 {
24148 }
24151 }
24154 }
24156 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24157 struct attribute_spec.handler. */
24158 static tree
24160 tree args ATTRIBUTE_UNUSED,
24162 {
24165 {
24168 }
24169 else
24174 {
24178 }
24184 {
24188 }
24191 }
24193 static bool
24195 {
24199 }
24201 /* Returns an expression indicating where the this parameter is
24202 located on entry to the FUNCTION. */
24204 static rtx
24206 {
24212 {
24217 else
24220 }
24225 {
24230 else
24231 {
24234 {
24239 }
24240 }
24242 }
24245 }
24247 /* Determine whether x86_output_mi_thunk can succeed. */
24249 static bool
24251 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
24253 {
24254 /* 64-bit can handle anything. */
24258 /* For 32-bit, everything's fine if we have one free register. */
24262 /* Need a free register for vcall_offset. */
24266 /* Need a free register for GOT references. */
24270 /* Otherwise ok. */
24272 }
24274 /* Output the assembler code for a thunk function. THUNK_DECL is the
24275 declaration for the thunk function itself, FUNCTION is the decl for
24276 the target function. DELTA is an immediate constant offset to be
24277 added to THIS. If VCALL_OFFSET is nonzero, the word at
24278 *(*this + vcall_offset) should be added to THIS. */
24280 static void
24284 {
24289 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
24290 pull it in now and let DELTA benefit. */
24294 {
24295 /* Put the this parameter into %eax. */
24299 }
24300 else
24303 /* Adjust the this parameter by a fixed constant. */
24305 {
24309 {
24311 {
24317 }
24319 }
24320 else
24322 }
24324 /* Adjust the this parameter by a value stored in the vtable. */
24326 {
24329 else
24330 {
24336 }
24342 /* Adjust the this parameter. */
24345 {
24351 }
24354 }
24356 /* If necessary, drop THIS back to its stack slot. */
24358 {
24362 }
24366 {
24369 /* All thunks should be in the same object as their target,
24370 and thus binds_local_p should be true. */
24373 else
24374 {
24380 }
24381 }
24382 else
24383 {
24386 else
24387 #if TARGET_MACHO
24389 {
24391 tmp = (gen_rtx_SYMBOL_REF
24397 }
24398 else
24400 {
24407 }
24408 }
24409 }
24411 static void
24413 {
24415 #if TARGET_MACHO
24417 #endif
24424 }
24426 int
24428 {
24440 }
24442 /* Output assembler code to FILE to increment profiler label # LABELNO
24443 for profiling a function entry. */
24444 void
24446 {
24448 {
24449 #ifndef NO_PROFILE_COUNTERS
24451 #endif
24455 else
24457 }
24459 {
24460 #ifndef NO_PROFILE_COUNTERS
24463 #endif
24465 }
24466 else
24467 {
24468 #ifndef NO_PROFILE_COUNTERS
24470 PROFILE_COUNT_REGISTER);
24471 #endif
24473 }
24474 }
24476 /* We don't have exact information about the insn sizes, but we may assume
24477 quite safely that we are informed about all 1 byte insns and memory
24478 address sizes. This is enough to eliminate unnecessary padding in
24479 99% of cases. */
24481 static int
24483 {
24489 /* Discard alignments we've emit and jump instructions. */
24498 /* Important case - calls are always 5 bytes.
24499 It is common to have many calls in the row. */
24507 /* For normal instructions we may rely on the sizes of addresses
24508 and the presence of symbol to require 4 bytes of encoding.
24509 This is not the case for jumps where references are PC relative. */
24511 {
24515 }
24518 else
24520 }
24522 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
24523 window. */
24525 static void
24527 {
24532 /* Look for all minimal intervals of instructions containing 4 jumps.
24533 The intervals are bounded by START and INSN. NBYTES is the total
24534 size of instructions in the interval including INSN and not including
24535 START. When the NBYTES is smaller than 16 bytes, it is possible
24536 that the end of START and INSN ends up in the same 16byte page.
24538 The smallest offset in the page INSN can start is the case where START
24539 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
24540 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
24541 */
24543 {
24553 njumps++;
24554 else
24558 {
24565 else
24568 }
24575 {
24582 }
24583 }
24584 }
24586 /* AMD Athlon works faster
24587 when RET is not destination of conditional jump or directly preceded
24588 by other jump instruction. We avoid the penalty by inserting NOP just
24589 before the RET instructions in such cases. */
24590 static void
24592 {
24593 edge e;
24594 edge_iterator ei;
24597 {
24600 rtx prev;
24610 {
24611 edge e;
24612 edge_iterator ei;
24618 }
24620 {
24626 /* Empty functions get branch mispredict even when the jump destination
24627 is not visible to us. */
24630 }
24632 {
24635 }
24636 }
24637 }
24639 /* Implement machine specific optimizations. We implement padding of returns
24640 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
24641 static void
24643 {
24648 }
24650 /* Return nonzero when QImode register that must be represented via REX prefix
24651 is used. */
24652 bool
24654 {
24662 }
24664 /* Return nonzero when P points to register encoded via REX prefix.
24665 Called via for_each_rtx. */
24666 static int
24668 {
24674 }
24676 /* Return true when INSN mentions register that must be encoded using REX
24677 prefix. */
24678 bool
24680 {
24682 }
24684 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
24685 optabs would emit if we didn't have TFmode patterns. */
24687 void
24689 {
24723 }
24724 \f
24725 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
24726 with all elements equal to VAR. Return true if successful. */
24728 static bool
24731 {
24733 rtx x;
24736 {
24741 /* FALLTHRU */
24756 {
24762 }
24763 else
24764 {
24769 }
24780 {
24782 /* Extend HImode to SImode using a paradoxical SUBREG. */
24785 /* Insert the SImode value as low element of V4SImode vector. */
24790 const1_rtx);
24792 /* Cast the V4SImode vector back to a V8HImode vector. */
24795 /* Duplicate the low short through the whole low SImode word. */
24797 /* Cast the V8HImode vector back to a V4SImode vector. */
24800 /* Replicate the low element of the V4SImode vector. */
24802 /* Cast the V2SImode back to V8HImode, and store in target. */
24805 }
24812 {
24814 /* Extend QImode to SImode using a paradoxical SUBREG. */
24817 /* Insert the SImode value as low element of V4SImode vector. */
24822 const1_rtx);
24824 /* Cast the V4SImode vector back to a V16QImode vector. */
24827 /* Duplicate the low byte through the whole low SImode word. */
24830 /* Cast the V16QImode vector back to a V4SImode vector. */
24833 /* Replicate the low element of the V4SImode vector. */
24835 /* Cast the V2SImode back to V16QImode, and store in target. */
24838 }
24843 widen:
24844 /* Replicate the value once into the next wider mode and recurse. */
24859 }
24860 }
24862 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
24863 whose ONE_VAR element is VAR, and other elements are zero. Return true
24864 if successful. */
24866 static bool
24869 {
24871 rtx new_target;
24876 {
24893 }
24896 {
24901 }
24904 {
24909 /* FALLTHRU */
24924 else
24931 {
24932 /* We need to shuffle the value to the correct position, so
24933 create a new pseudo to store the intermediate result. */
24935 /* With SSE2, we can use the integer shuffle insns. */
24937 {
24946 }
24948 /* Otherwise convert the intermediate result to V4SFmode and
24949 use the SSE1 shuffle instructions. */
24951 {
24954 }
24955 else
24968 }
24983 widen:
24987 /* Zero extend the variable element to SImode and recurse. */
25000 }
25001 }
25003 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
25004 consisting of the values in VALS. It is known that all elements
25005 except ONE_VAR are constants. Return true if successful. */
25007 static bool
25010 {
25020 {
25025 /* For the two element vectors, it's just as easy to use
25026 the general case. */
25043 widen:
25044 /* There's no way to set one QImode entry easily. Combine
25045 the variable value with its adjacent constant value, and
25046 promote to an HImode set. */
25049 {
25054 }
25055 else
25056 {
25059 }
25073 }
25078 }
25080 /* A subroutine of ix86_expand_vector_init_general. Use vector
25081 concatenate to handle the most general case: all values variable,
25082 and none identical. */
25084 static void
25087 {
25090 rtvec v;
25094 {
25097 {
25118 }
25131 {
25140 }
25143 half:
25144 /* FIXME: We process inputs backward to help RA. PR 36222. */
25148 {
25153 }
25157 {
25160 {
25164 }
25167 }
25168 else
25174 }
25175 }
25177 /* A subroutine of ix86_expand_vector_init_general. Use vector
25178 interleave to handle the most general case: all values variable,
25179 and none identical. */
25181 static void
25184 {
25193 {
25212 }
25215 {
25216 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
25220 /* Insert the SImode value as low element of V4SImode vector. */
25224 op0),
25226 const1_rtx);
25229 /* Cast the V4SImode vector back to a vector in orignal mode. */
25233 /* Load even elements into the second positon. */
25235 const1_rtx));
25237 /* Cast vector to FIRST_IMODE vector. */
25240 }
25242 /* Interleave low FIRST_IMODE vectors. */
25244 {
25248 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
25251 }
25253 /* Interleave low SECOND_IMODE vectors. */
25255 {
25258 {
25263 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
25264 vector. */
25267 }
25270 /* FALLTHRU */
25277 /* Cast the SECOND_IMODE vector back to a vector on original
25278 mode. */
25285 }
25286 }
25288 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
25289 all values variable, and none identical. */
25291 static void
25294 {
25299 {
25304 /* FALLTHRU */
25319 /* FALLTHRU */
25337 }
25339 {
25351 {
25355 {
25361 else
25362 {
25367 }
25368 }
25371 }
25376 {
25382 }
25384 {
25390 }
25391 else
25393 }
25394 }
25396 /* Initialize vector TARGET via VALS. Suppress the use of MMX
25397 instructions unless MMX_OK is true. */
25399 void
25401 {
25408 rtx x;
25411 {
25421 }
25423 /* Constants are best loaded from the constant pool. */
25425 {
25428 }
25430 /* If all values are identical, broadcast the value. */
25436 /* Values where only one field is non-constant are best loaded from
25437 the pool and overwritten via move later. */
25439 {
25443 one_var))
25448 }
25451 }
25453 void
25455 {
25459 rtx tmp;
25462 {
25466 {
25471 else
25475 }
25484 {
25487 /* For the two element vectors, we implement a VEC_CONCAT with
25488 the extraction of the other element. */
25495 else
25500 }
25509 {
25515 /* tmp = target = A B C D */
25517 /* target = A A B B */
25519 /* target = X A B B */
25521 /* target = A X C D */
25528 /* tmp = target = A B C D */
25530 /* tmp = X B C D */
25532 /* target = A B X D */
25539 /* tmp = target = A B C D */
25541 /* tmp = X B C D */
25543 /* target = A B X D */
25551 }
25559 /* Element 0 handled by vec_merge below. */
25561 {
25564 }
25567 {
25568 /* With SSE2, use integer shuffles to swap element 0 and ELT,
25569 store into element 0, then shuffle them back. */
25586 }
25587 else
25588 {
25589 /* For SSE1, we have to reuse the V4SF code. */
25592 }
25609 }
25612 {
25616 }
25617 else
25618 {
25627 }
25628 }
25630 void
25632 {
25636 rtx tmp;
25639 {
25644 /* FALLTHRU */
25657 {
25677 }
25689 {
25691 {
25711 }
25715 }
25716 else
25717 {
25718 /* For SSE1, we have to reuse the V4SF code. */
25722 }
25737 /* ??? Could extract the appropriate HImode element and shift. */
25740 }
25743 {
25747 /* Let the rtl optimizers know about the zero extension performed. */
25749 {
25752 }
25755 }
25756 else
25757 {
25764 }
25765 }
25767 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
25768 pattern to reduce; DEST is the destination; IN is the input vector. */
25770 void
25772 {
25786 }
25787 \f
25788 /* Target hook for scalar_mode_supported_p. */
25789 static bool
25791 {
25796 else
25798 }
25800 /* Implements target hook vector_mode_supported_p. */
25801 static bool
25803 {
25813 }
25815 /* Target hook for c_mode_for_suffix. */
25816 static enum machine_mode
25818 {
25825 }
25827 /* Worker function for TARGET_MD_ASM_CLOBBERS.
25829 We do this in the new i386 backend to maintain source compatibility
25830 with the old cc0-based compiler. */
25832 static tree
25834 tree inputs ATTRIBUTE_UNUSED,
25835 tree clobbers)
25836 {
25838 clobbers);
25840 clobbers);
25842 }
25844 /* Implements target vector targetm.asm.encode_section_info. This
25845 is not used by netware. */
25847 static void ATTRIBUTE_UNUSED
25849 {
25856 }
25858 /* Worker function for REVERSE_CONDITION. */
25860 enum rtx_code
25862 {
25866 }
25868 /* Output code to perform an x87 FP register move, from OPERANDS[1]
25869 to OPERANDS[0]. */
25873 {
25875 {
25878 {
25882 }
25886 }
25888 {
25892 else
25893 {
25894 /* There is no non-popping store to memory for XFmode.
25895 So if we need one, follow the store with a load. */
25898 else
25900 }
25901 }
25902 else
25904 }
25906 /* Output code to perform a conditional jump to LABEL, if C2 flag in
25907 FP status register is set. */
25909 void
25911 {
25913 rtx temp;
25918 {
25923 }
25924 else
25925 {
25930 }
25934 pc_rtx);
25939 }
25941 /* Output code to perform a log1p XFmode calculation. */
25944 {
25955 XFmode)));
25969 }
25971 /* Output code to perform a Newton-Rhapson approximation of a single precision
25972 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
25975 {
25990 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
25992 /* x0 = rcp(b) estimate */
25995 UNSPEC_RCP)));
25996 /* e0 = x0 * b */
25999 /* e1 = 2. - e0 */
26002 /* x1 = x0 * e1 */
26005 /* res = a * x1 */
26008 }
26010 /* Output code to perform a Newton-Rhapson approximation of a
26011 single precision floating point [reciprocal] square root. */
26015 {
26017 REAL_VALUE_TYPE r;
26032 {
26035 }
26037 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
26038 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
26040 /* x0 = rsqrt(a) estimate */
26043 UNSPEC_RSQRT)));
26045 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
26047 {
26059 }
26061 /* e0 = x0 * a */
26064 /* e1 = e0 * x0 */
26068 /* e2 = e1 - 3. */
26075 /* e3 = -.5 * x0 */
26078 else
26079 /* e3 = -.5 * e0 */
26082 /* ret = e2 * e3 */
26085 }
26087 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
26089 static void ATTRIBUTE_UNUSED
26091 tree decl)
26092 {
26093 /* With Binutils 2.15, the "@unwind" marker must be specified on
26094 every occurrence of the ".eh_frame" section, not just the first
26095 one. */
26098 {
26102 }
26104 }
26106 /* Return the mangling of TYPE if it is an extended fundamental type. */
26110 {
26118 {
26120 /* __float128 is "g". */
26123 /* "long double" or __float80 is "e". */
26127 }
26128 }
26130 /* For 32-bit code we can save PIC register setup by using
26131 __stack_chk_fail_local hidden function instead of calling
26132 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
26133 register, so it is better to call __stack_chk_fail directly. */
26135 static tree
26137 {
26138 return TARGET_64BIT
26141 }
26143 /* Select a format to encode pointers in exception handling data. CODE
26144 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
26145 true if the symbol may be affected by dynamic relocations.
26147 ??? All x86 object file formats are capable of representing this.
26148 After all, the relocation needed is the same as for the call insn.
26149 Whether or not a particular assembler allows us to enter such, I
26150 guess we'll have to see. */
26151 int
26153 {
26155 {
26162 }
26167 }
26168 \f
26169 /* Expand copysign from SIGN to the positive value ABS_VALUE
26170 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
26171 the sign-bit. */
26172 static void
26174 {
26178 {
26181 {
26182 /* We need to generate a scalar mode mask in this case. */
26187 }
26188 }
26189 else
26195 }
26197 /* Expand fabs (OP0) and return a new rtx that holds the result. The
26198 mask for masking out the sign-bit is stored in *SMASK, if that is
26199 non-null. */
26200 static rtx
26202 {
26209 {
26210 /* We need to generate a scalar mode mask in this case. */
26215 }
26223 }
26225 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
26226 swapping the operands if SWAP_OPERANDS is true. The expanded
26227 code is a forward jump to a newly created label in case the
26228 comparison is true. The generated label rtx is returned. */
26229 static rtx
26232 {
26236 {
26240 }
26253 }
26255 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
26256 using comparison code CODE. Operands are swapped for the comparison if
26257 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
26258 static rtx
26261 {
26266 {
26270 }
26275 else
26280 }
26282 /* Generate and return a rtx of mode MODE for 2**n where n is the number
26283 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
26284 static rtx
26286 {
26287 REAL_VALUE_TYPE TWO52r;
26288 rtx TWO52;
26295 }
26297 /* Expand SSE sequence for computing lround from OP1 storing
26298 into OP0. */
26299 void
26301 {
26302 /* C code for the stuff we're doing below:
26303 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
26304 return (long)tmp;
26305 */
26309 rtx adj;
26311 /* load nextafter (0.5, 0.0) */
26316 /* adj = copysign (0.5, op1) */
26320 /* adj = op1 + adj */
26323 /* op0 = (imode)adj */
26325 }
26327 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
26328 into OPERAND0. */
26329 void
26331 {
26332 /* C code for the stuff we're doing below (for do_floor):
26333 xi = (long)op1;
26334 xi -= (double)xi > op1 ? 1 : 0;
26335 return xi;
26336 */
26341 /* reg = (long)op1 */
26345 /* freg = (double)reg */
26349 /* ireg = (freg > op1) ? ireg - 1 : ireg */
26360 }
26362 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
26363 result in OPERAND0. */
26364 void
26366 {
26367 /* C code for the stuff we're doing below:
26368 xa = fabs (operand1);
26369 if (!isless (xa, 2**52))
26370 return operand1;
26371 xa = xa + 2**52 - 2**52;
26372 return copysign (xa, operand1);
26373 */
26380 /* xa = abs (operand1) */
26383 /* if (!isless (xa, TWO52)) goto label; */
26396 }
26398 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
26399 into OPERAND0. */
26400 void
26402 {
26403 /* C code for the stuff we expand below.
26404 double xa = fabs (x), x2;
26405 if (!isless (xa, TWO52))
26406 return x;
26407 xa = xa + TWO52 - TWO52;
26408 x2 = copysign (xa, x);
26409 Compensate. Floor:
26410 if (x2 > x)
26411 x2 -= 1;
26412 Compensate. Ceil:
26413 if (x2 < x)
26414 x2 -= -1;
26415 return x2;
26416 */
26422 /* Temporary for holding the result, initialized to the input
26423 operand to ease control flow. */
26427 /* xa = abs (operand1) */
26430 /* if (!isless (xa, TWO52)) goto label; */
26433 /* xa = xa + TWO52 - TWO52; */
26437 /* xa = copysign (xa, operand1) */
26440 /* generate 1.0 or -1.0 */
26445 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
26449 /* We always need to subtract here to preserve signed zero. */
26458 }
26460 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
26461 into OPERAND0. */
26462 void
26464 {
26465 /* C code for the stuff we expand below.
26466 double xa = fabs (x), x2;
26467 if (!isless (xa, TWO52))
26468 return x;
26469 x2 = (double)(long)x;
26470 Compensate. Floor:
26471 if (x2 > x)
26472 x2 -= 1;
26473 Compensate. Ceil:
26474 if (x2 < x)
26475 x2 += 1;
26476 if (HONOR_SIGNED_ZEROS (mode))
26477 return copysign (x2, x);
26478 return x2;
26479 */
26485 /* Temporary for holding the result, initialized to the input
26486 operand to ease control flow. */
26490 /* xa = abs (operand1) */
26493 /* if (!isless (xa, TWO52)) goto label; */
26496 /* xa = (double)(long)x */
26501 /* generate 1.0 */
26504 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
26519 }
26521 /* Expand SSE sequence for computing round from OPERAND1 storing
26522 into OPERAND0. Sequence that works without relying on DImode truncation
26523 via cvttsd2siq that is only available on 64bit targets. */
26524 void
26526 {
26527 /* C code for the stuff we expand below.
26528 double xa = fabs (x), xa2, x2;
26529 if (!isless (xa, TWO52))
26530 return x;
26531 Using the absolute value and copying back sign makes
26532 -0.0 -> -0.0 correct.
26533 xa2 = xa + TWO52 - TWO52;
26534 Compensate.
26535 dxa = xa2 - xa;
26536 if (dxa <= -0.5)
26537 xa2 += 1;
26538 else if (dxa > 0.5)
26539 xa2 -= 1;
26540 x2 = copysign (xa2, x);
26541 return x2;
26542 */
26548 /* Temporary for holding the result, initialized to the input
26549 operand to ease control flow. */
26553 /* xa = abs (operand1) */
26556 /* if (!isless (xa, TWO52)) goto label; */
26559 /* xa2 = xa + TWO52 - TWO52; */
26563 /* dxa = xa2 - xa; */
26566 /* generate 0.5, 1.0 and -0.5 */
26572 /* Compensate. */
26574 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
26579 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
26585 /* res = copysign (xa2, operand1) */
26592 }
26594 /* Expand SSE sequence for computing trunc from OPERAND1 storing
26595 into OPERAND0. */
26596 void
26598 {
26599 /* C code for SSE variant we expand below.
26600 double xa = fabs (x), x2;
26601 if (!isless (xa, TWO52))
26602 return x;
26603 x2 = (double)(long)x;
26604 if (HONOR_SIGNED_ZEROS (mode))
26605 return copysign (x2, x);
26606 return x2;
26607 */
26613 /* Temporary for holding the result, initialized to the input
26614 operand to ease control flow. */
26618 /* xa = abs (operand1) */
26621 /* if (!isless (xa, TWO52)) goto label; */
26624 /* x = (double)(long)x */
26636 }
26638 /* Expand SSE sequence for computing trunc from OPERAND1 storing
26639 into OPERAND0. */
26640 void
26642 {
26646 /* C code for SSE variant we expand below.
26647 double xa = fabs (x), x2;
26648 if (!isless (xa, TWO52))
26649 return x;
26650 xa2 = xa + TWO52 - TWO52;
26651 Compensate:
26652 if (xa2 > xa)
26653 xa2 -= 1.0;
26654 x2 = copysign (xa2, x);
26655 return x2;
26656 */
26660 /* Temporary for holding the result, initialized to the input
26661 operand to ease control flow. */
26665 /* xa = abs (operand1) */
26668 /* if (!isless (xa, TWO52)) goto label; */
26671 /* res = xa + TWO52 - TWO52; */
26676 /* generate 1.0 */
26679 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
26687 /* res = copysign (res, operand1) */
26694 }
26696 /* Expand SSE sequence for computing round from OPERAND1 storing
26697 into OPERAND0. */
26698 void
26700 {
26701 /* C code for the stuff we're doing below:
26702 double xa = fabs (x);
26703 if (!isless (xa, TWO52))
26704 return x;
26705 xa = (double)(long)(xa + nextafter (0.5, 0.0));
26706 return copysign (xa, x);
26707 */
26713 /* Temporary for holding the result, initialized to the input
26714 operand to ease control flow. */
26722 /* load nextafter (0.5, 0.0) */
26727 /* xa = xa + 0.5 */
26731 /* xa = (double)(int64_t)xa */
26736 /* res = copysign (xa, operand1) */
26743 }
26745 \f
26746 /* Validate whether a SSE5 instruction is valid or not.
26747 OPERANDS is the array of operands.
26748 NUM is the number of operands.
26749 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
26750 NUM_MEMORY is the maximum number of memory operands to accept.
26751 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
26753 bool
26756 {
26761 /* Count the number of memory arguments */
26765 {
26768 ;
26771 {
26773 mem_count++;
26774 }
26776 else
26777 {
26780 /* allow 0 for pcmov */
26786 }
26787 }
26789 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
26790 a memory operation. */
26792 {
26795 {
26797 mem_count--;
26798 }
26799 }
26801 /* If there were no memory operations, allow the insn */
26805 /* Do not allow the destination register to be a memory operand. */
26809 /* If there are too many memory operations, disallow the instruction. While
26810 the hardware only allows 1 memory reference, before register allocation
26811 for some insns, we allow two memory operations sometimes in order to allow
26812 code like the following to be optimized:
26814 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
26816 or similar cases that are vectorized into using the fmaddss
26817 instruction. */
26821 /* Don't allow more than one memory operation if not optimizing. */
26826 {
26827 /* formats (destination is the first argument), example fmaddss:
26828 xmm1, xmm1, xmm2, xmm3/mem
26829 xmm1, xmm1, xmm2/mem, xmm3
26830 xmm1, xmm2, xmm3/mem, xmm1
26831 xmm1, xmm2/mem, xmm3, xmm1 */
26837 /* format, example pmacsdd:
26838 xmm1, xmm2, xmm3/mem, xmm1 */
26841 else
26843 }
26846 {
26847 /* If there are two memory operations, we can load one of the memory ops
26848 into the destination register. This is for optimizing the
26849 multiply/add ops, which the combiner has optimized both the multiply
26850 and the add insns to have a memory operation. We have to be careful
26851 that the destination doesn't overlap with the inputs. */
26859 /* formats (destination is the first argument), example fmaddss:
26860 xmm1, xmm1, xmm2, xmm3/mem
26861 xmm1, xmm1, xmm2/mem, xmm3
26862 xmm1, xmm2, xmm3/mem, xmm1
26863 xmm1, xmm2/mem, xmm3, xmm1
26865 For the oc0 case, we will load either operands[1] or operands[3] into
26866 operands[0], so any combination of 2 memory operands is ok. */
26870 /* format, example pmacsdd:
26871 xmm1, xmm2, xmm3/mem, xmm1
26873 For the integer multiply/add instructions be more restrictive and
26874 require operands[2] and operands[3] to be the memory operands. */
26877 else
26879 }
26882 {
26883 /* formats, example protb:
26884 xmm1, xmm2, xmm3/mem
26885 xmm1, xmm2/mem, xmm3 */
26889 /* format, example comeq:
26890 xmm1, xmm2, xmm3/mem */
26891 else
26893 }
26895 else
26899 }
26901 \f
26902 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
26903 hardware will allow by using the destination register to load one of the
26904 memory operations. Presently this is used by the multiply/add routines to
26905 allow 2 memory references. */
26907 void
26911 {
26920 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
26921 the destination register. */
26923 {
26926 }
26928 {
26931 }
26932 else
26936 }
26938 \f
26939 /* Table of valid machine attributes. */
26941 {
26942 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
26943 /* Stdcall attribute says callee is responsible for popping arguments
26944 if they are not variable. */
26946 /* Fastcall attribute says callee is responsible for popping arguments
26947 if they are not variable. */
26949 /* Cdecl attribute says the callee is a normal C declaration */
26951 /* Regparm attribute specifies how many integer arguments are to be
26952 passed in registers. */
26954 /* Sseregparm attribute says we are using x86_64 calling conventions
26955 for FP arguments. */
26957 /* force_align_arg_pointer says this function realigns the stack at entry. */
26960 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
26964 #endif
26967 #ifdef SUBTARGET_ATTRIBUTE_TABLE
26968 SUBTARGET_ATTRIBUTE_TABLE,
26969 #endif
26970 /* ms_abi and sysv_abi calling convention function attributes. */
26973 /* End element. */
26975 };
26977 /* Implement targetm.vectorize.builtin_vectorization_cost. */
26978 static int
26980 {
26981 /* If the branch of the runtime test is taken - i.e. - the vectorized
26982 version is skipped - this incurs a misprediction cost (because the
26983 vectorized version is expected to be the fall-through). So we subtract
26984 the latency of a mispredicted branch from the costs that are incured
26985 when the vectorized version is executed.
26987 TODO: The values in individual target tables have to be tuned or new
26988 fields may be needed. For eg. on K8, the default branch path is the
26989 not-taken path. If the taken path is predicted correctly, the minimum
26990 penalty of going down the taken-path is 1 cycle. If the taken-path is
26991 not predicted correctly, then the minimum penalty is 10 cycles. */
26994 {
26996 }
26997 else
26999 }
27001 /* This function returns the calling abi specific va_list type node.
27002 It returns the FNDECL specific va_list type. */
27004 tree
27006 {
27016 else
27018 }
27020 /* Returns the canonical va_list type specified by TYPE. If there
27021 is no valid TYPE provided, it return NULL_TREE. */
27023 tree
27025 {
27028 /* Resolve references and pointers to va_list type. */
27035 {
27040 {
27041 /* If va_list is an array type, the argument may have decayed
27042 to a pointer type, e.g. by being passed to another function.
27043 In that case, unwrap both types so that we can compare the
27044 underlying records. */
27047 {
27050 }
27051 }
27058 {
27059 /* If va_list is an array type, the argument may have decayed
27060 to a pointer type, e.g. by being passed to another function.
27061 In that case, unwrap both types so that we can compare the
27062 underlying records. */
27065 {
27068 }
27069 }
27076 {
27077 /* If va_list is an array type, the argument may have decayed
27078 to a pointer type, e.g. by being passed to another function.
27079 In that case, unwrap both types so that we can compare the
27080 underlying records. */
27083 {
27086 }
27087 }
27091 }
27093 }
27095 /* Iterate through the target-specific builtin types for va_list.
27096 IDX denotes the iterator, *PTREE is set to the result type of
27097 the va_list builtin, and *PNAME to its internal type.
27098 Returns zero if there is no element for this index, otherwise
27099 IDX should be increased upon the next call.
27100 Note, do not iterate a base builtin's name like __builtin_va_list.
27101 Used from c_common_nodes_and_builtins. */
27103 int
27105 {
27119 }
27121 }
27123 /* Initialize the GCC target structure. */
27124 #undef TARGET_RETURN_IN_MEMORY
27125 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
27127 #undef TARGET_ATTRIBUTE_TABLE
27128 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
27129 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
27130 # undef TARGET_MERGE_DECL_ATTRIBUTES
27131 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
27132 #endif
27134 #undef TARGET_COMP_TYPE_ATTRIBUTES
27135 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
27137 #undef TARGET_INIT_BUILTINS
27138 #define TARGET_INIT_BUILTINS ix86_init_builtins
27139 #undef TARGET_EXPAND_BUILTIN
27140 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
27142 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
27143 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
27144 ix86_builtin_vectorized_function
27146 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
27147 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
27149 #undef TARGET_BUILTIN_RECIPROCAL
27150 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
27152 #undef TARGET_ASM_FUNCTION_EPILOGUE
27153 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
27155 #undef TARGET_ENCODE_SECTION_INFO
27156 #ifndef SUBTARGET_ENCODE_SECTION_INFO
27157 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
27158 #else
27159 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
27160 #endif
27162 #undef TARGET_ASM_OPEN_PAREN
27164 #undef TARGET_ASM_CLOSE_PAREN
27167 #undef TARGET_ASM_ALIGNED_HI_OP
27168 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
27169 #undef TARGET_ASM_ALIGNED_SI_OP
27170 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
27171 #ifdef ASM_QUAD
27172 #undef TARGET_ASM_ALIGNED_DI_OP
27173 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
27174 #endif
27176 #undef TARGET_ASM_UNALIGNED_HI_OP
27177 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
27178 #undef TARGET_ASM_UNALIGNED_SI_OP
27179 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
27180 #undef TARGET_ASM_UNALIGNED_DI_OP
27181 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
27183 #undef TARGET_SCHED_ADJUST_COST
27184 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
27185 #undef TARGET_SCHED_ISSUE_RATE
27186 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
27187 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
27188 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
27189 ia32_multipass_dfa_lookahead
27191 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
27192 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
27194 #ifdef HAVE_AS_TLS
27195 #undef TARGET_HAVE_TLS
27196 #define TARGET_HAVE_TLS true
27197 #endif
27198 #undef TARGET_CANNOT_FORCE_CONST_MEM
27199 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
27200 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
27201 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
27203 #undef TARGET_DELEGITIMIZE_ADDRESS
27204 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
27206 #undef TARGET_MS_BITFIELD_LAYOUT_P
27207 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
27209 #if TARGET_MACHO
27210 #undef TARGET_BINDS_LOCAL_P
27211 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
27212 #endif
27213 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
27214 #undef TARGET_BINDS_LOCAL_P
27215 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
27216 #endif
27218 #undef TARGET_ASM_OUTPUT_MI_THUNK
27219 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
27220 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
27221 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
27223 #undef TARGET_ASM_FILE_START
27224 #define TARGET_ASM_FILE_START x86_file_start
27226 #undef TARGET_DEFAULT_TARGET_FLAGS
27227 #define TARGET_DEFAULT_TARGET_FLAGS \
27228 (TARGET_DEFAULT \
27229 | TARGET_SUBTARGET_DEFAULT \
27230 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
27232 #undef TARGET_HANDLE_OPTION
27233 #define TARGET_HANDLE_OPTION ix86_handle_option
27235 #undef TARGET_RTX_COSTS
27236 #define TARGET_RTX_COSTS ix86_rtx_costs
27237 #undef TARGET_ADDRESS_COST
27238 #define TARGET_ADDRESS_COST ix86_address_cost
27240 #undef TARGET_FIXED_CONDITION_CODE_REGS
27241 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
27242 #undef TARGET_CC_MODES_COMPATIBLE
27243 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
27245 #undef TARGET_MACHINE_DEPENDENT_REORG
27246 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
27248 #undef TARGET_BUILD_BUILTIN_VA_LIST
27249 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
27251 #undef TARGET_FN_ABI_VA_LIST
27252 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
27254 #undef TARGET_CANONICAL_VA_LIST_TYPE
27255 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
27257 #undef TARGET_EXPAND_BUILTIN_VA_START
27258 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
27260 #undef TARGET_MD_ASM_CLOBBERS
27261 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
27263 #undef TARGET_PROMOTE_PROTOTYPES
27264 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
27265 #undef TARGET_STRUCT_VALUE_RTX
27266 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
27267 #undef TARGET_SETUP_INCOMING_VARARGS
27268 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
27269 #undef TARGET_MUST_PASS_IN_STACK
27270 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
27271 #undef TARGET_PASS_BY_REFERENCE
27272 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
27273 #undef TARGET_INTERNAL_ARG_POINTER
27274 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
27275 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
27276 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
27277 #undef TARGET_STRICT_ARGUMENT_NAMING
27278 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
27280 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
27281 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
27283 #undef TARGET_SCALAR_MODE_SUPPORTED_P
27284 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
27286 #undef TARGET_VECTOR_MODE_SUPPORTED_P
27287 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
27289 #undef TARGET_C_MODE_FOR_SUFFIX
27290 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
27292 #ifdef HAVE_AS_TLS
27293 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
27294 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
27295 #endif
27297 #ifdef SUBTARGET_INSERT_ATTRIBUTES
27298 #undef TARGET_INSERT_ATTRIBUTES
27299 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
27300 #endif
27302 #undef TARGET_MANGLE_TYPE
27303 #define TARGET_MANGLE_TYPE ix86_mangle_type
27305 #undef TARGET_STACK_PROTECT_FAIL
27306 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
27308 #undef TARGET_FUNCTION_VALUE
27309 #define TARGET_FUNCTION_VALUE ix86_function_value
27311 #undef TARGET_SECONDARY_RELOAD
27312 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
27314 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
27315 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
27317 #undef TARGET_SET_CURRENT_FUNCTION
27318 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
27320 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
27321 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_option_attribute_p
27323 #undef TARGET_OPTION_SAVE
27324 #define TARGET_OPTION_SAVE ix86_function_specific_save
27326 #undef TARGET_OPTION_RESTORE
27327 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
27329 #undef TARGET_OPTION_PRINT
27330 #define TARGET_OPTION_PRINT ix86_function_specific_print
27332 #undef TARGET_OPTION_CAN_INLINE_P
27333 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
27335 #undef TARGET_OPTION_COLD_ATTRIBUTE_SETS_OPTIMIZATION
27336 #define TARGET_OPTION_COLD_ATTRIBUTE_SETS_OPTIMIZATION true
27338 #undef TARGET_OPTION_HOT_ATTRIBUTE_SETS_OPTIMIZATION
27339 #define TARGET_OPTION_HOT_ATTRIBUTE_SETS_OPTIMIZATION true
27342 \f