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2007-03-01 Paul Brook <paul@codesourcery.com>
[official-gcc.git] / gcc / longlong.h
blob8b512d2f2844102063573d3185e812c5fab1aeb0
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004,
3 2005 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 2, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin Street, Fifth Floor,
18 Boston, MA 02110-1301, USA. */
19
20 /* You have to define the following before including this file:
21
22 UWtype -- An unsigned type, default type for operations (typically a "word")
23 UHWtype -- An unsigned type, at least half the size of UWtype.
24 UDWtype -- An unsigned type, at least twice as large a UWtype
25 W_TYPE_SIZE -- size in bits of UWtype
26
27 UQItype -- Unsigned 8 bit type.
28 SItype, USItype -- Signed and unsigned 32 bit types.
29 DItype, UDItype -- Signed and unsigned 64 bit types.
30
31 On a 32 bit machine UWtype should typically be USItype;
32 on a 64 bit machine, UWtype should typically be UDItype. */
33
34 #define __BITS4 (W_TYPE_SIZE / 4)
35 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
36 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
37 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
38
39 #ifndef W_TYPE_SIZE
40 #define W_TYPE_SIZE 32
41 #define UWtype USItype
42 #define UHWtype USItype
43 #define UDWtype UDItype
44 #endif
45
46 extern const UQItype __clz_tab[256];
47
48 /* Define auxiliary asm macros.
49
50 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
51 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
52 word product in HIGH_PROD and LOW_PROD.
53
54 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
55 UDWtype product. This is just a variant of umul_ppmm.
56
57 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
58 denominator) divides a UDWtype, composed by the UWtype integers
59 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
60 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
61 than DENOMINATOR for correct operation. If, in addition, the most
62 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
63 UDIV_NEEDS_NORMALIZATION is defined to 1.
64
65 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
66 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
67 is rounded towards 0.
68
69 5) count_leading_zeros(count, x) counts the number of zero-bits from the
70 msb to the first nonzero bit in the UWtype X. This is the number of
71 steps X needs to be shifted left to set the msb. Undefined for X == 0,
72 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
73
74 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
75 from the least significant end.
76
77 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
78 high_addend_2, low_addend_2) adds two UWtype integers, composed by
79 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
80 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
81 (i.e. carry out) is not stored anywhere, and is lost.
82
83 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
84 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
85 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
86 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
87 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
88 and is lost.
89
90 If any of these macros are left undefined for a particular CPU,
91 C macros are used. */
92
93 /* The CPUs come in alphabetical order below.
94
95 Please add support for more CPUs here, or improve the current support
96 for the CPUs below!
97 (E.g. WE32100, IBM360.) */
98
99 #if defined (__GNUC__) && !defined (NO_ASM)
100
101 /* We sometimes need to clobber "cc" with gcc2, but that would not be
102 understood by gcc1. Use cpp to avoid major code duplication. */
103 #if __GNUC__ < 2
104 #define __CLOBBER_CC
105 #define __AND_CLOBBER_CC
106 #else /* __GNUC__ >= 2 */
107 #define __CLOBBER_CC : "cc"
108 #define __AND_CLOBBER_CC , "cc"
109 #endif /* __GNUC__ < 2 */
110
111 #if defined (__alpha) && W_TYPE_SIZE == 64
112 #define umul_ppmm(ph, pl, m0, m1) \
113 do { \
114 UDItype __m0 = (m0), __m1 = (m1); \
115 (ph) = __builtin_alpha_umulh (__m0, __m1); \
116 (pl) = __m0 * __m1; \
117 } while (0)
118 #define UMUL_TIME 46
119 #ifndef LONGLONG_STANDALONE
120 #define udiv_qrnnd(q, r, n1, n0, d) \
121 do { UDItype __r; \
122 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
123 (r) = __r; \
124 } while (0)
125 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
126 #define UDIV_TIME 220
127 #endif /* LONGLONG_STANDALONE */
128 #ifdef __alpha_cix__
129 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
130 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
131 #define COUNT_LEADING_ZEROS_0 64
132 #else
133 #define count_leading_zeros(COUNT,X) \
134 do { \
135 UDItype __xr = (X), __t, __a; \
136 __t = __builtin_alpha_cmpbge (0, __xr); \
137 __a = __clz_tab[__t ^ 0xff] - 1; \
138 __t = __builtin_alpha_extbl (__xr, __a); \
139 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
140 } while (0)
141 #define count_trailing_zeros(COUNT,X) \
142 do { \
143 UDItype __xr = (X), __t, __a; \
144 __t = __builtin_alpha_cmpbge (0, __xr); \
145 __t = ~__t & -~__t; \
146 __a = ((__t & 0xCC) != 0) * 2; \
147 __a += ((__t & 0xF0) != 0) * 4; \
148 __a += ((__t & 0xAA) != 0); \
149 __t = __builtin_alpha_extbl (__xr, __a); \
150 __a <<= 3; \
151 __t &= -__t; \
152 __a += ((__t & 0xCC) != 0) * 2; \
153 __a += ((__t & 0xF0) != 0) * 4; \
154 __a += ((__t & 0xAA) != 0); \
155 (COUNT) = __a; \
156 } while (0)
157 #endif /* __alpha_cix__ */
158 #endif /* __alpha */
159
160 #if defined (__arc__) && W_TYPE_SIZE == 32
161 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
162 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
163 : "=r" ((USItype) (sh)), \
164 "=&r" ((USItype) (sl)) \
165 : "%r" ((USItype) (ah)), \
166 "rIJ" ((USItype) (bh)), \
167 "%r" ((USItype) (al)), \
168 "rIJ" ((USItype) (bl)))
169 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
170 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
171 : "=r" ((USItype) (sh)), \
172 "=&r" ((USItype) (sl)) \
173 : "r" ((USItype) (ah)), \
174 "rIJ" ((USItype) (bh)), \
175 "r" ((USItype) (al)), \
176 "rIJ" ((USItype) (bl)))
177 /* Call libgcc routine. */
178 #define umul_ppmm(w1, w0, u, v) \
179 do { \
180 DWunion __w; \
181 __w.ll = __umulsidi3 (u, v); \
182 w1 = __w.s.high; \
183 w0 = __w.s.low; \
184 } while (0)
185 #define __umulsidi3 __umulsidi3
186 UDItype __umulsidi3 (USItype, USItype);
187 #endif
188
189 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
190 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
191 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
192 : "=r" ((USItype) (sh)), \
193 "=&r" ((USItype) (sl)) \
194 : "%r" ((USItype) (ah)), \
195 "rI" ((USItype) (bh)), \
196 "%r" ((USItype) (al)), \
197 "rI" ((USItype) (bl)) __CLOBBER_CC)
198 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
199 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
200 : "=r" ((USItype) (sh)), \
201 "=&r" ((USItype) (sl)) \
202 : "r" ((USItype) (ah)), \
203 "rI" ((USItype) (bh)), \
204 "r" ((USItype) (al)), \
205 "rI" ((USItype) (bl)) __CLOBBER_CC)
206 #define umul_ppmm(xh, xl, a, b) \
207 {register USItype __t0, __t1, __t2; \
208 __asm__ ("%@ Inlined umul_ppmm\n" \
209 " mov %2, %5, lsr #16\n" \
210 " mov %0, %6, lsr #16\n" \
211 " bic %3, %5, %2, lsl #16\n" \
212 " bic %4, %6, %0, lsl #16\n" \
213 " mul %1, %3, %4\n" \
214 " mul %4, %2, %4\n" \
215 " mul %3, %0, %3\n" \
216 " mul %0, %2, %0\n" \
217 " adds %3, %4, %3\n" \
218 " addcs %0, %0, #65536\n" \
219 " adds %1, %1, %3, lsl #16\n" \
220 " adc %0, %0, %3, lsr #16" \
221 : "=&r" ((USItype) (xh)), \
222 "=r" ((USItype) (xl)), \
223 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
224 : "r" ((USItype) (a)), \
225 "r" ((USItype) (b)) __CLOBBER_CC );}
226 #define UMUL_TIME 20
227 #define UDIV_TIME 100
228 #endif /* __arm__ */
229
230 #if defined (__hppa) && W_TYPE_SIZE == 32
231 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
232 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
233 : "=r" ((USItype) (sh)), \
234 "=&r" ((USItype) (sl)) \
235 : "%rM" ((USItype) (ah)), \
236 "rM" ((USItype) (bh)), \
237 "%rM" ((USItype) (al)), \
238 "rM" ((USItype) (bl)))
239 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
240 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
241 : "=r" ((USItype) (sh)), \
242 "=&r" ((USItype) (sl)) \
243 : "rM" ((USItype) (ah)), \
244 "rM" ((USItype) (bh)), \
245 "rM" ((USItype) (al)), \
246 "rM" ((USItype) (bl)))
247 #if defined (_PA_RISC1_1)
248 #define umul_ppmm(w1, w0, u, v) \
249 do { \
250 union \
251 { \
252 UDItype __f; \
253 struct {USItype __w1, __w0;} __w1w0; \
254 } __t; \
255 __asm__ ("xmpyu %1,%2,%0" \
256 : "=x" (__t.__f) \
257 : "x" ((USItype) (u)), \
258 "x" ((USItype) (v))); \
259 (w1) = __t.__w1w0.__w1; \
260 (w0) = __t.__w1w0.__w0; \
261 } while (0)
262 #define UMUL_TIME 8
263 #else
264 #define UMUL_TIME 30
265 #endif
266 #define UDIV_TIME 40
267 #define count_leading_zeros(count, x) \
268 do { \
269 USItype __tmp; \
270 __asm__ ( \
271 "ldi 1,%0\n" \
272 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
273 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
274 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
275 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
276 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
277 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
278 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
279 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
280 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
281 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
282 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
283 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
284 " extru %1,30,1,%1 ; Extract bit 1.\n" \
285 " sub %0,%1,%0 ; Subtract it.\n" \
286 : "=r" (count), "=r" (__tmp) : "1" (x)); \
287 } while (0)
288 #endif
289
290 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
291 #define smul_ppmm(xh, xl, m0, m1) \
292 do { \
293 union {DItype __ll; \
294 struct {USItype __h, __l;} __i; \
295 } __x; \
296 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
297 : "=&r" (__x.__ll) \
298 : "r" (m0), "r" (m1)); \
299 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
300 } while (0)
301 #define sdiv_qrnnd(q, r, n1, n0, d) \
302 do { \
303 union {DItype __ll; \
304 struct {USItype __h, __l;} __i; \
305 } __x; \
306 __x.__i.__h = n1; __x.__i.__l = n0; \
307 __asm__ ("dr %0,%2" \
308 : "=r" (__x.__ll) \
309 : "0" (__x.__ll), "r" (d)); \
310 (q) = __x.__i.__l; (r) = __x.__i.__h; \
311 } while (0)
312 #endif
313
314 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
315 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
316 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
317 : "=r" ((USItype) (sh)), \
318 "=&r" ((USItype) (sl)) \
319 : "%0" ((USItype) (ah)), \
320 "g" ((USItype) (bh)), \
321 "%1" ((USItype) (al)), \
322 "g" ((USItype) (bl)))
323 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
324 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
325 : "=r" ((USItype) (sh)), \
326 "=&r" ((USItype) (sl)) \
327 : "0" ((USItype) (ah)), \
328 "g" ((USItype) (bh)), \
329 "1" ((USItype) (al)), \
330 "g" ((USItype) (bl)))
331 #define umul_ppmm(w1, w0, u, v) \
332 __asm__ ("mull %3" \
333 : "=a" ((USItype) (w0)), \
334 "=d" ((USItype) (w1)) \
335 : "%0" ((USItype) (u)), \
336 "rm" ((USItype) (v)))
337 #define udiv_qrnnd(q, r, n1, n0, dv) \
338 __asm__ ("divl %4" \
339 : "=a" ((USItype) (q)), \
340 "=d" ((USItype) (r)) \
341 : "0" ((USItype) (n0)), \
342 "1" ((USItype) (n1)), \
343 "rm" ((USItype) (dv)))
344 #define count_leading_zeros(count, x) \
345 do { \
346 USItype __cbtmp; \
347 __asm__ ("bsrl %1,%0" \
348 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
349 (count) = __cbtmp ^ 31; \
350 } while (0)
351 #define count_trailing_zeros(count, x) \
352 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
353 #define UMUL_TIME 40
354 #define UDIV_TIME 40
355 #endif /* 80x86 */
356
357 #if defined (__i960__) && W_TYPE_SIZE == 32
358 #define umul_ppmm(w1, w0, u, v) \
359 ({union {UDItype __ll; \
360 struct {USItype __l, __h;} __i; \
361 } __xx; \
362 __asm__ ("emul %2,%1,%0" \
363 : "=d" (__xx.__ll) \
364 : "%dI" ((USItype) (u)), \
365 "dI" ((USItype) (v))); \
366 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
367 #define __umulsidi3(u, v) \
368 ({UDItype __w; \
369 __asm__ ("emul %2,%1,%0" \
370 : "=d" (__w) \
371 : "%dI" ((USItype) (u)), \
372 "dI" ((USItype) (v))); \
373 __w; })
374 #endif /* __i960__ */
375
376 #if defined (__M32R__) && W_TYPE_SIZE == 32
377 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
378 /* The cmp clears the condition bit. */ \
379 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
380 : "=r" ((USItype) (sh)), \
381 "=&r" ((USItype) (sl)) \
382 : "0" ((USItype) (ah)), \
383 "r" ((USItype) (bh)), \
384 "1" ((USItype) (al)), \
385 "r" ((USItype) (bl)) \
386 : "cbit")
387 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
388 /* The cmp clears the condition bit. */ \
389 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
390 : "=r" ((USItype) (sh)), \
391 "=&r" ((USItype) (sl)) \
392 : "0" ((USItype) (ah)), \
393 "r" ((USItype) (bh)), \
394 "1" ((USItype) (al)), \
395 "r" ((USItype) (bl)) \
396 : "cbit")
397 #endif /* __M32R__ */
398
399 #if defined (__mc68000__) && W_TYPE_SIZE == 32
400 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
401 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
402 : "=d" ((USItype) (sh)), \
403 "=&d" ((USItype) (sl)) \
404 : "%0" ((USItype) (ah)), \
405 "d" ((USItype) (bh)), \
406 "%1" ((USItype) (al)), \
407 "g" ((USItype) (bl)))
408 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
409 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
410 : "=d" ((USItype) (sh)), \
411 "=&d" ((USItype) (sl)) \
412 : "0" ((USItype) (ah)), \
413 "d" ((USItype) (bh)), \
414 "1" ((USItype) (al)), \
415 "g" ((USItype) (bl)))
416
417 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
418 #if (defined (__mc68020__) && !defined (__mc68060__))
419 #define umul_ppmm(w1, w0, u, v) \
420 __asm__ ("mulu%.l %3,%1:%0" \
421 : "=d" ((USItype) (w0)), \
422 "=d" ((USItype) (w1)) \
423 : "%0" ((USItype) (u)), \
424 "dmi" ((USItype) (v)))
425 #define UMUL_TIME 45
426 #define udiv_qrnnd(q, r, n1, n0, d) \
427 __asm__ ("divu%.l %4,%1:%0" \
428 : "=d" ((USItype) (q)), \
429 "=d" ((USItype) (r)) \
430 : "0" ((USItype) (n0)), \
431 "1" ((USItype) (n1)), \
432 "dmi" ((USItype) (d)))
433 #define UDIV_TIME 90
434 #define sdiv_qrnnd(q, r, n1, n0, d) \
435 __asm__ ("divs%.l %4,%1:%0" \
436 : "=d" ((USItype) (q)), \
437 "=d" ((USItype) (r)) \
438 : "0" ((USItype) (n0)), \
439 "1" ((USItype) (n1)), \
440 "dmi" ((USItype) (d)))
441
442 #elif defined (__mcoldfire__) /* not mc68020 */
443
444 #define umul_ppmm(xh, xl, a, b) \
445 __asm__ ("| Inlined umul_ppmm\n" \
446 " move%.l %2,%/d0\n" \
447 " move%.l %3,%/d1\n" \
448 " move%.l %/d0,%/d2\n" \
449 " swap %/d0\n" \
450 " move%.l %/d1,%/d3\n" \
451 " swap %/d1\n" \
452 " move%.w %/d2,%/d4\n" \
453 " mulu %/d3,%/d4\n" \
454 " mulu %/d1,%/d2\n" \
455 " mulu %/d0,%/d3\n" \
456 " mulu %/d0,%/d1\n" \
457 " move%.l %/d4,%/d0\n" \
458 " clr%.w %/d0\n" \
459 " swap %/d0\n" \
460 " add%.l %/d0,%/d2\n" \
461 " add%.l %/d3,%/d2\n" \
462 " jcc 1f\n" \
463 " add%.l %#65536,%/d1\n" \
464 "1: swap %/d2\n" \
465 " moveq %#0,%/d0\n" \
466 " move%.w %/d2,%/d0\n" \
467 " move%.w %/d4,%/d2\n" \
468 " move%.l %/d2,%1\n" \
469 " add%.l %/d1,%/d0\n" \
470 " move%.l %/d0,%0" \
471 : "=g" ((USItype) (xh)), \
472 "=g" ((USItype) (xl)) \
473 : "g" ((USItype) (a)), \
474 "g" ((USItype) (b)) \
475 : "d0", "d1", "d2", "d3", "d4")
476 #define UMUL_TIME 100
477 #define UDIV_TIME 400
478 #else /* not ColdFire */
479 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
480 #define umul_ppmm(xh, xl, a, b) \
481 __asm__ ("| Inlined umul_ppmm\n" \
482 " move%.l %2,%/d0\n" \
483 " move%.l %3,%/d1\n" \
484 " move%.l %/d0,%/d2\n" \
485 " swap %/d0\n" \
486 " move%.l %/d1,%/d3\n" \
487 " swap %/d1\n" \
488 " move%.w %/d2,%/d4\n" \
489 " mulu %/d3,%/d4\n" \
490 " mulu %/d1,%/d2\n" \
491 " mulu %/d0,%/d3\n" \
492 " mulu %/d0,%/d1\n" \
493 " move%.l %/d4,%/d0\n" \
494 " eor%.w %/d0,%/d0\n" \
495 " swap %/d0\n" \
496 " add%.l %/d0,%/d2\n" \
497 " add%.l %/d3,%/d2\n" \
498 " jcc 1f\n" \
499 " add%.l %#65536,%/d1\n" \
500 "1: swap %/d2\n" \
501 " moveq %#0,%/d0\n" \
502 " move%.w %/d2,%/d0\n" \
503 " move%.w %/d4,%/d2\n" \
504 " move%.l %/d2,%1\n" \
505 " add%.l %/d1,%/d0\n" \
506 " move%.l %/d0,%0" \
507 : "=g" ((USItype) (xh)), \
508 "=g" ((USItype) (xl)) \
509 : "g" ((USItype) (a)), \
510 "g" ((USItype) (b)) \
511 : "d0", "d1", "d2", "d3", "d4")
512 #define UMUL_TIME 100
513 #define UDIV_TIME 400
514
515 #endif /* not mc68020 */
516
517 /* The '020, '030, '040 and '060 have bitfield insns.
518 cpu32 disguises as a 68020, but lacks them. */
519 #if defined (__mc68020__) && !defined (__mcpu32__)
520 #define count_leading_zeros(count, x) \
521 __asm__ ("bfffo %1{%b2:%b2},%0" \
522 : "=d" ((USItype) (count)) \
523 : "od" ((USItype) (x)), "n" (0))
524 /* Some ColdFire architectures have a ff1 instruction supported via
525 __builtin_clz. */
526 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
527 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
528 #define COUNT_LEADING_ZEROS_0 32
529 #endif
530 #endif /* mc68000 */
531
532 #if defined (__m88000__) && W_TYPE_SIZE == 32
533 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
534 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
535 : "=r" ((USItype) (sh)), \
536 "=&r" ((USItype) (sl)) \
537 : "%rJ" ((USItype) (ah)), \
538 "rJ" ((USItype) (bh)), \
539 "%rJ" ((USItype) (al)), \
540 "rJ" ((USItype) (bl)))
541 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
542 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
543 : "=r" ((USItype) (sh)), \
544 "=&r" ((USItype) (sl)) \
545 : "rJ" ((USItype) (ah)), \
546 "rJ" ((USItype) (bh)), \
547 "rJ" ((USItype) (al)), \
548 "rJ" ((USItype) (bl)))
549 #define count_leading_zeros(count, x) \
550 do { \
551 USItype __cbtmp; \
552 __asm__ ("ff1 %0,%1" \
553 : "=r" (__cbtmp) \
554 : "r" ((USItype) (x))); \
555 (count) = __cbtmp ^ 31; \
556 } while (0)
557 #define COUNT_LEADING_ZEROS_0 63 /* sic */
558 #if defined (__mc88110__)
559 #define umul_ppmm(wh, wl, u, v) \
560 do { \
561 union {UDItype __ll; \
562 struct {USItype __h, __l;} __i; \
563 } __xx; \
564 __asm__ ("mulu.d %0,%1,%2" \
565 : "=r" (__xx.__ll) \
566 : "r" ((USItype) (u)), \
567 "r" ((USItype) (v))); \
568 (wh) = __xx.__i.__h; \
569 (wl) = __xx.__i.__l; \
570 } while (0)
571 #define udiv_qrnnd(q, r, n1, n0, d) \
572 ({union {UDItype __ll; \
573 struct {USItype __h, __l;} __i; \
574 } __xx; \
575 USItype __q; \
576 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
577 __asm__ ("divu.d %0,%1,%2" \
578 : "=r" (__q) \
579 : "r" (__xx.__ll), \
580 "r" ((USItype) (d))); \
581 (r) = (n0) - __q * (d); (q) = __q; })
582 #define UMUL_TIME 5
583 #define UDIV_TIME 25
584 #else
585 #define UMUL_TIME 17
586 #define UDIV_TIME 150
587 #endif /* __mc88110__ */
588 #endif /* __m88000__ */
589
590 #if defined (__mips__) && W_TYPE_SIZE == 32
591 #define umul_ppmm(w1, w0, u, v) \
592 __asm__ ("multu %2,%3" \
593 : "=l" ((USItype) (w0)), \
594 "=h" ((USItype) (w1)) \
595 : "d" ((USItype) (u)), \
596 "d" ((USItype) (v)))
597 #define UMUL_TIME 10
598 #define UDIV_TIME 100
599 #endif /* __mips__ */
600
601 #if defined (__ns32000__) && W_TYPE_SIZE == 32
602 #define umul_ppmm(w1, w0, u, v) \
603 ({union {UDItype __ll; \
604 struct {USItype __l, __h;} __i; \
605 } __xx; \
606 __asm__ ("meid %2,%0" \
607 : "=g" (__xx.__ll) \
608 : "%0" ((USItype) (u)), \
609 "g" ((USItype) (v))); \
610 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
611 #define __umulsidi3(u, v) \
612 ({UDItype __w; \
613 __asm__ ("meid %2,%0" \
614 : "=g" (__w) \
615 : "%0" ((USItype) (u)), \
616 "g" ((USItype) (v))); \
617 __w; })
618 #define udiv_qrnnd(q, r, n1, n0, d) \
619 ({union {UDItype __ll; \
620 struct {USItype __l, __h;} __i; \
621 } __xx; \
622 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
623 __asm__ ("deid %2,%0" \
624 : "=g" (__xx.__ll) \
625 : "0" (__xx.__ll), \
626 "g" ((USItype) (d))); \
627 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
628 #define count_trailing_zeros(count,x) \
629 do { \
630 __asm__ ("ffsd %2,%0" \
631 : "=r" ((USItype) (count)) \
632 : "0" ((USItype) 0), \
633 "r" ((USItype) (x))); \
634 } while (0)
635 #endif /* __ns32000__ */
636
637 /* FIXME: We should test _IBMR2 here when we add assembly support for the
638 system vendor compilers.
639 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
640 enough, since that hits ARM and m68k too. */
641 #if (defined (_ARCH_PPC) /* AIX */ \
642 || defined (_ARCH_PWR) /* AIX */ \
643 || defined (_ARCH_COM) /* AIX */ \
644 || defined (__powerpc__) /* gcc */ \
645 || defined (__POWERPC__) /* BEOS */ \
646 || defined (__ppc__) /* Darwin */ \
647 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
648 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
649 && CPU_FAMILY == PPC) \
650 ) && W_TYPE_SIZE == 32
651 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
652 do { \
653 if (__builtin_constant_p (bh) && (bh) == 0) \
654 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
655 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
656 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
657 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
658 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
659 else \
660 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
661 : "=r" (sh), "=&r" (sl) \
662 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
663 } while (0)
664 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
665 do { \
666 if (__builtin_constant_p (ah) && (ah) == 0) \
667 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
668 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
669 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
670 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
671 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
672 else if (__builtin_constant_p (bh) && (bh) == 0) \
673 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
674 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
675 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
676 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
677 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
678 else \
679 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
680 : "=r" (sh), "=&r" (sl) \
681 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
682 } while (0)
683 #define count_leading_zeros(count, x) \
684 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
685 #define COUNT_LEADING_ZEROS_0 32
686 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
687 || defined (__ppc__) \
688 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
689 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
690 && CPU_FAMILY == PPC)
691 #define umul_ppmm(ph, pl, m0, m1) \
692 do { \
693 USItype __m0 = (m0), __m1 = (m1); \
694 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
695 (pl) = __m0 * __m1; \
696 } while (0)
697 #define UMUL_TIME 15
698 #define smul_ppmm(ph, pl, m0, m1) \
699 do { \
700 SItype __m0 = (m0), __m1 = (m1); \
701 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
702 (pl) = __m0 * __m1; \
703 } while (0)
704 #define SMUL_TIME 14
705 #define UDIV_TIME 120
706 #elif defined (_ARCH_PWR)
707 #define UMUL_TIME 8
708 #define smul_ppmm(xh, xl, m0, m1) \
709 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
710 #define SMUL_TIME 4
711 #define sdiv_qrnnd(q, r, nh, nl, d) \
712 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
713 #define UDIV_TIME 100
714 #endif
715 #endif /* 32-bit POWER architecture variants. */
716
717 /* We should test _IBMR2 here when we add assembly support for the system
718 vendor compilers. */
719 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
720 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
721 do { \
722 if (__builtin_constant_p (bh) && (bh) == 0) \
723 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
724 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
725 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
726 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
727 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
728 else \
729 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
730 : "=r" (sh), "=&r" (sl) \
731 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
732 } while (0)
733 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
734 do { \
735 if (__builtin_constant_p (ah) && (ah) == 0) \
736 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
737 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
738 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
739 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
740 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
741 else if (__builtin_constant_p (bh) && (bh) == 0) \
742 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
743 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
744 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
745 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
746 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
747 else \
748 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
749 : "=r" (sh), "=&r" (sl) \
750 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
751 } while (0)
752 #define count_leading_zeros(count, x) \
753 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
754 #define COUNT_LEADING_ZEROS_0 64
755 #define umul_ppmm(ph, pl, m0, m1) \
756 do { \
757 UDItype __m0 = (m0), __m1 = (m1); \
758 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
759 (pl) = __m0 * __m1; \
760 } while (0)
761 #define UMUL_TIME 15
762 #define smul_ppmm(ph, pl, m0, m1) \
763 do { \
764 DItype __m0 = (m0), __m1 = (m1); \
765 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
766 (pl) = __m0 * __m1; \
767 } while (0)
768 #define SMUL_TIME 14 /* ??? */
769 #define UDIV_TIME 120 /* ??? */
770 #endif /* 64-bit PowerPC. */
771
772 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
773 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
774 __asm__ ("a %1,%5\n\tae %0,%3" \
775 : "=r" ((USItype) (sh)), \
776 "=&r" ((USItype) (sl)) \
777 : "%0" ((USItype) (ah)), \
778 "r" ((USItype) (bh)), \
779 "%1" ((USItype) (al)), \
780 "r" ((USItype) (bl)))
781 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
782 __asm__ ("s %1,%5\n\tse %0,%3" \
783 : "=r" ((USItype) (sh)), \
784 "=&r" ((USItype) (sl)) \
785 : "0" ((USItype) (ah)), \
786 "r" ((USItype) (bh)), \
787 "1" ((USItype) (al)), \
788 "r" ((USItype) (bl)))
789 #define umul_ppmm(ph, pl, m0, m1) \
790 do { \
791 USItype __m0 = (m0), __m1 = (m1); \
792 __asm__ ( \
793 "s r2,r2\n" \
794 " mts r10,%2\n" \
795 " m r2,%3\n" \
796 " m r2,%3\n" \
797 " m r2,%3\n" \
798 " m r2,%3\n" \
799 " m r2,%3\n" \
800 " m r2,%3\n" \
801 " m r2,%3\n" \
802 " m r2,%3\n" \
803 " m r2,%3\n" \
804 " m r2,%3\n" \
805 " m r2,%3\n" \
806 " m r2,%3\n" \
807 " m r2,%3\n" \
808 " m r2,%3\n" \
809 " m r2,%3\n" \
810 " m r2,%3\n" \
811 " cas %0,r2,r0\n" \
812 " mfs r10,%1" \
813 : "=r" ((USItype) (ph)), \
814 "=r" ((USItype) (pl)) \
815 : "%r" (__m0), \
816 "r" (__m1) \
817 : "r2"); \
818 (ph) += ((((SItype) __m0 >> 31) & __m1) \
819 + (((SItype) __m1 >> 31) & __m0)); \
820 } while (0)
821 #define UMUL_TIME 20
822 #define UDIV_TIME 200
823 #define count_leading_zeros(count, x) \
824 do { \
825 if ((x) >= 0x10000) \
826 __asm__ ("clz %0,%1" \
827 : "=r" ((USItype) (count)) \
828 : "r" ((USItype) (x) >> 16)); \
829 else \
830 { \
831 __asm__ ("clz %0,%1" \
832 : "=r" ((USItype) (count)) \
833 : "r" ((USItype) (x))); \
834 (count) += 16; \
835 } \
836 } while (0)
837 #endif
838
839 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
840 #ifndef __sh1__
841 #define umul_ppmm(w1, w0, u, v) \
842 __asm__ ( \
843 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
844 : "=r<" ((USItype)(w1)), \
845 "=r<" ((USItype)(w0)) \
846 : "r" ((USItype)(u)), \
847 "r" ((USItype)(v)) \
848 : "macl", "mach")
849 #define UMUL_TIME 5
850 #endif
851
852 /* This is the same algorithm as __udiv_qrnnd_c. */
853 #define UDIV_NEEDS_NORMALIZATION 1
854
855 #define udiv_qrnnd(q, r, n1, n0, d) \
856 do { \
857 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
858 __attribute__ ((visibility ("hidden"))); \
859 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
860 __asm__ ( \
861 "mov%M4 %4,r5\n" \
862 " swap.w %3,r4\n" \
863 " swap.w r5,r6\n" \
864 " jsr @%5\n" \
865 " shll16 r6\n" \
866 " swap.w r4,r4\n" \
867 " jsr @%5\n" \
868 " swap.w r1,%0\n" \
869 " or r1,%0" \
870 : "=r" (q), "=&z" (r) \
871 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
872 : "r1", "r2", "r4", "r5", "r6", "pr"); \
873 } while (0)
874
875 #define UDIV_TIME 80
876
877 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
878 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
879 : "=r" (sh), "=r" (sl) \
880 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
881
882 #endif /* __sh__ */
883
884 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
885 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
886 #define count_leading_zeros(count, x) \
887 do \
888 { \
889 UDItype x_ = (USItype)(x); \
890 SItype c_; \
891 \
892 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
893 (count) = c_ - 31; \
894 } \
895 while (0)
896 #define COUNT_LEADING_ZEROS_0 32
897 #endif
898
899 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
900 && W_TYPE_SIZE == 32
901 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
902 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
903 : "=r" ((USItype) (sh)), \
904 "=&r" ((USItype) (sl)) \
905 : "%rJ" ((USItype) (ah)), \
906 "rI" ((USItype) (bh)), \
907 "%rJ" ((USItype) (al)), \
908 "rI" ((USItype) (bl)) \
909 __CLOBBER_CC)
910 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
911 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
912 : "=r" ((USItype) (sh)), \
913 "=&r" ((USItype) (sl)) \
914 : "rJ" ((USItype) (ah)), \
915 "rI" ((USItype) (bh)), \
916 "rJ" ((USItype) (al)), \
917 "rI" ((USItype) (bl)) \
918 __CLOBBER_CC)
919 #if defined (__sparc_v8__)
920 #define umul_ppmm(w1, w0, u, v) \
921 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
922 : "=r" ((USItype) (w1)), \
923 "=r" ((USItype) (w0)) \
924 : "r" ((USItype) (u)), \
925 "r" ((USItype) (v)))
926 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
927 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
928 : "=&r" ((USItype) (__q)), \
929 "=&r" ((USItype) (__r)) \
930 : "r" ((USItype) (__n1)), \
931 "r" ((USItype) (__n0)), \
932 "r" ((USItype) (__d)))
933 #else
934 #if defined (__sparclite__)
935 /* This has hardware multiply but not divide. It also has two additional
936 instructions scan (ffs from high bit) and divscc. */
937 #define umul_ppmm(w1, w0, u, v) \
938 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
939 : "=r" ((USItype) (w1)), \
940 "=r" ((USItype) (w0)) \
941 : "r" ((USItype) (u)), \
942 "r" ((USItype) (v)))
943 #define udiv_qrnnd(q, r, n1, n0, d) \
944 __asm__ ("! Inlined udiv_qrnnd\n" \
945 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
946 " tst %%g0\n" \
947 " divscc %3,%4,%%g1\n" \
948 " divscc %%g1,%4,%%g1\n" \
949 " divscc %%g1,%4,%%g1\n" \
950 " divscc %%g1,%4,%%g1\n" \
951 " divscc %%g1,%4,%%g1\n" \
952 " divscc %%g1,%4,%%g1\n" \
953 " divscc %%g1,%4,%%g1\n" \
954 " divscc %%g1,%4,%%g1\n" \
955 " divscc %%g1,%4,%%g1\n" \
956 " divscc %%g1,%4,%%g1\n" \
957 " divscc %%g1,%4,%%g1\n" \
958 " divscc %%g1,%4,%%g1\n" \
959 " divscc %%g1,%4,%%g1\n" \
960 " divscc %%g1,%4,%%g1\n" \
961 " divscc %%g1,%4,%%g1\n" \
962 " divscc %%g1,%4,%%g1\n" \
963 " divscc %%g1,%4,%%g1\n" \
964 " divscc %%g1,%4,%%g1\n" \
965 " divscc %%g1,%4,%%g1\n" \
966 " divscc %%g1,%4,%%g1\n" \
967 " divscc %%g1,%4,%%g1\n" \
968 " divscc %%g1,%4,%%g1\n" \
969 " divscc %%g1,%4,%%g1\n" \
970 " divscc %%g1,%4,%%g1\n" \
971 " divscc %%g1,%4,%%g1\n" \
972 " divscc %%g1,%4,%%g1\n" \
973 " divscc %%g1,%4,%%g1\n" \
974 " divscc %%g1,%4,%%g1\n" \
975 " divscc %%g1,%4,%%g1\n" \
976 " divscc %%g1,%4,%%g1\n" \
977 " divscc %%g1,%4,%%g1\n" \
978 " divscc %%g1,%4,%0\n" \
979 " rd %%y,%1\n" \
980 " bl,a 1f\n" \
981 " add %1,%4,%1\n" \
982 "1: ! End of inline udiv_qrnnd" \
983 : "=r" ((USItype) (q)), \
984 "=r" ((USItype) (r)) \
985 : "r" ((USItype) (n1)), \
986 "r" ((USItype) (n0)), \
987 "rI" ((USItype) (d)) \
988 : "g1" __AND_CLOBBER_CC)
989 #define UDIV_TIME 37
990 #define count_leading_zeros(count, x) \
991 do { \
992 __asm__ ("scan %1,1,%0" \
993 : "=r" ((USItype) (count)) \
994 : "r" ((USItype) (x))); \
995 } while (0)
996 /* Early sparclites return 63 for an argument of 0, but they warn that future
997 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
998 undefined. */
999 #else
1000 /* SPARC without integer multiplication and divide instructions.
1001 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1002 #define umul_ppmm(w1, w0, u, v) \
1003 __asm__ ("! Inlined umul_ppmm\n" \
1004 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1005 " sra %3,31,%%o5 ! Don't move this insn\n" \
1006 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1007 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1008 " mulscc %%g1,%3,%%g1\n" \
1009 " mulscc %%g1,%3,%%g1\n" \
1010 " mulscc %%g1,%3,%%g1\n" \
1011 " mulscc %%g1,%3,%%g1\n" \
1012 " mulscc %%g1,%3,%%g1\n" \
1013 " mulscc %%g1,%3,%%g1\n" \
1014 " mulscc %%g1,%3,%%g1\n" \
1015 " mulscc %%g1,%3,%%g1\n" \
1016 " mulscc %%g1,%3,%%g1\n" \
1017 " mulscc %%g1,%3,%%g1\n" \
1018 " mulscc %%g1,%3,%%g1\n" \
1019 " mulscc %%g1,%3,%%g1\n" \
1020 " mulscc %%g1,%3,%%g1\n" \
1021 " mulscc %%g1,%3,%%g1\n" \
1022 " mulscc %%g1,%3,%%g1\n" \
1023 " mulscc %%g1,%3,%%g1\n" \
1024 " mulscc %%g1,%3,%%g1\n" \
1025 " mulscc %%g1,%3,%%g1\n" \
1026 " mulscc %%g1,%3,%%g1\n" \
1027 " mulscc %%g1,%3,%%g1\n" \
1028 " mulscc %%g1,%3,%%g1\n" \
1029 " mulscc %%g1,%3,%%g1\n" \
1030 " mulscc %%g1,%3,%%g1\n" \
1031 " mulscc %%g1,%3,%%g1\n" \
1032 " mulscc %%g1,%3,%%g1\n" \
1033 " mulscc %%g1,%3,%%g1\n" \
1034 " mulscc %%g1,%3,%%g1\n" \
1035 " mulscc %%g1,%3,%%g1\n" \
1036 " mulscc %%g1,%3,%%g1\n" \
1037 " mulscc %%g1,%3,%%g1\n" \
1038 " mulscc %%g1,%3,%%g1\n" \
1039 " mulscc %%g1,%3,%%g1\n" \
1040 " mulscc %%g1,0,%%g1\n" \
1041 " add %%g1,%%o5,%0\n" \
1042 " rd %%y,%1" \
1043 : "=r" ((USItype) (w1)), \
1044 "=r" ((USItype) (w0)) \
1045 : "%rI" ((USItype) (u)), \
1046 "r" ((USItype) (v)) \
1047 : "g1", "o5" __AND_CLOBBER_CC)
1048 #define UMUL_TIME 39 /* 39 instructions */
1049 /* It's quite necessary to add this much assembler for the sparc.
1050 The default udiv_qrnnd (in C) is more than 10 times slower! */
1051 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1052 __asm__ ("! Inlined udiv_qrnnd\n" \
1053 " mov 32,%%g1\n" \
1054 " subcc %1,%2,%%g0\n" \
1055 "1: bcs 5f\n" \
1056 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1057 " sub %1,%2,%1 ! this kills msb of n\n" \
1058 " addx %1,%1,%1 ! so this can't give carry\n" \
1059 " subcc %%g1,1,%%g1\n" \
1060 "2: bne 1b\n" \
1061 " subcc %1,%2,%%g0\n" \
1062 " bcs 3f\n" \
1063 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1064 " b 3f\n" \
1065 " sub %1,%2,%1 ! this kills msb of n\n" \
1066 "4: sub %1,%2,%1\n" \
1067 "5: addxcc %1,%1,%1\n" \
1068 " bcc 2b\n" \
1069 " subcc %%g1,1,%%g1\n" \
1070 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1071 " bne 4b\n" \
1072 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1073 " sub %1,%2,%1\n" \
1074 "3: xnor %0,0,%0\n" \
1075 " ! End of inline udiv_qrnnd" \
1076 : "=&r" ((USItype) (__q)), \
1077 "=&r" ((USItype) (__r)) \
1078 : "r" ((USItype) (__d)), \
1079 "1" ((USItype) (__n1)), \
1080 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1081 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1082 #endif /* __sparclite__ */
1083 #endif /* __sparc_v8__ */
1084 #endif /* sparc32 */
1085
1086 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1087 && W_TYPE_SIZE == 64
1088 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1089 __asm__ ("addcc %r4,%5,%1\n\t" \
1090 "add %r2,%3,%0\n\t" \
1091 "bcs,a,pn %%xcc, 1f\n\t" \
1092 "add %0, 1, %0\n" \
1093 "1:" \
1094 : "=r" ((UDItype)(sh)), \
1095 "=&r" ((UDItype)(sl)) \
1096 : "%rJ" ((UDItype)(ah)), \
1097 "rI" ((UDItype)(bh)), \
1098 "%rJ" ((UDItype)(al)), \
1099 "rI" ((UDItype)(bl)) \
1100 __CLOBBER_CC)
1101
1102 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1103 __asm__ ("subcc %r4,%5,%1\n\t" \
1104 "sub %r2,%3,%0\n\t" \
1105 "bcs,a,pn %%xcc, 1f\n\t" \
1106 "sub %0, 1, %0\n\t" \
1107 "1:" \
1108 : "=r" ((UDItype)(sh)), \
1109 "=&r" ((UDItype)(sl)) \
1110 : "rJ" ((UDItype)(ah)), \
1111 "rI" ((UDItype)(bh)), \
1112 "rJ" ((UDItype)(al)), \
1113 "rI" ((UDItype)(bl)) \
1114 __CLOBBER_CC)
1115
1116 #define umul_ppmm(wh, wl, u, v) \
1117 do { \
1118 UDItype tmp1, tmp2, tmp3, tmp4; \
1119 __asm__ __volatile__ ( \
1120 "srl %7,0,%3\n\t" \
1121 "mulx %3,%6,%1\n\t" \
1122 "srlx %6,32,%2\n\t" \
1123 "mulx %2,%3,%4\n\t" \
1124 "sllx %4,32,%5\n\t" \
1125 "srl %6,0,%3\n\t" \
1126 "sub %1,%5,%5\n\t" \
1127 "srlx %5,32,%5\n\t" \
1128 "addcc %4,%5,%4\n\t" \
1129 "srlx %7,32,%5\n\t" \
1130 "mulx %3,%5,%3\n\t" \
1131 "mulx %2,%5,%5\n\t" \
1132 "sethi %%hi(0x80000000),%2\n\t" \
1133 "addcc %4,%3,%4\n\t" \
1134 "srlx %4,32,%4\n\t" \
1135 "add %2,%2,%2\n\t" \
1136 "movcc %%xcc,%%g0,%2\n\t" \
1137 "addcc %5,%4,%5\n\t" \
1138 "sllx %3,32,%3\n\t" \
1139 "add %1,%3,%1\n\t" \
1140 "add %5,%2,%0" \
1141 : "=r" ((UDItype)(wh)), \
1142 "=&r" ((UDItype)(wl)), \
1143 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1144 : "r" ((UDItype)(u)), \
1145 "r" ((UDItype)(v)) \
1146 __CLOBBER_CC); \
1147 } while (0)
1148 #define UMUL_TIME 96
1149 #define UDIV_TIME 230
1150 #endif /* sparc64 */
1151
1152 #if defined (__vax__) && W_TYPE_SIZE == 32
1153 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1154 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1155 : "=g" ((USItype) (sh)), \
1156 "=&g" ((USItype) (sl)) \
1157 : "%0" ((USItype) (ah)), \
1158 "g" ((USItype) (bh)), \
1159 "%1" ((USItype) (al)), \
1160 "g" ((USItype) (bl)))
1161 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1162 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1163 : "=g" ((USItype) (sh)), \
1164 "=&g" ((USItype) (sl)) \
1165 : "0" ((USItype) (ah)), \
1166 "g" ((USItype) (bh)), \
1167 "1" ((USItype) (al)), \
1168 "g" ((USItype) (bl)))
1169 #define umul_ppmm(xh, xl, m0, m1) \
1170 do { \
1171 union { \
1172 UDItype __ll; \
1173 struct {USItype __l, __h;} __i; \
1174 } __xx; \
1175 USItype __m0 = (m0), __m1 = (m1); \
1176 __asm__ ("emul %1,%2,$0,%0" \
1177 : "=r" (__xx.__ll) \
1178 : "g" (__m0), \
1179 "g" (__m1)); \
1180 (xh) = __xx.__i.__h; \
1181 (xl) = __xx.__i.__l; \
1182 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1183 + (((SItype) __m1 >> 31) & __m0)); \
1184 } while (0)
1185 #define sdiv_qrnnd(q, r, n1, n0, d) \
1186 do { \
1187 union {DItype __ll; \
1188 struct {SItype __l, __h;} __i; \
1189 } __xx; \
1190 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1191 __asm__ ("ediv %3,%2,%0,%1" \
1192 : "=g" (q), "=g" (r) \
1193 : "g" (__xx.__ll), "g" (d)); \
1194 } while (0)
1195 #endif /* __vax__ */
1196
1197 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1198 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1199 to expand builtin functions depending on what configuration features
1200 are available. This avoids library calls when the operation can be
1201 performed in-line. */
1202 #define umul_ppmm(w1, w0, u, v) \
1203 do { \
1204 DWunion __w; \
1205 __w.ll = __builtin_umulsidi3 (u, v); \
1206 w1 = __w.s.high; \
1207 w0 = __w.s.low; \
1208 } while (0)
1209 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1210 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1211 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1212 #endif /* __xtensa__ */
1213
1214 #if defined (__z8000__) && W_TYPE_SIZE == 16
1215 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1216 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1217 : "=r" ((unsigned int)(sh)), \
1218 "=&r" ((unsigned int)(sl)) \
1219 : "%0" ((unsigned int)(ah)), \
1220 "r" ((unsigned int)(bh)), \
1221 "%1" ((unsigned int)(al)), \
1222 "rQR" ((unsigned int)(bl)))
1223 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1224 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1225 : "=r" ((unsigned int)(sh)), \
1226 "=&r" ((unsigned int)(sl)) \
1227 : "0" ((unsigned int)(ah)), \
1228 "r" ((unsigned int)(bh)), \
1229 "1" ((unsigned int)(al)), \
1230 "rQR" ((unsigned int)(bl)))
1231 #define umul_ppmm(xh, xl, m0, m1) \
1232 do { \
1233 union {long int __ll; \
1234 struct {unsigned int __h, __l;} __i; \
1235 } __xx; \
1236 unsigned int __m0 = (m0), __m1 = (m1); \
1237 __asm__ ("mult %S0,%H3" \
1238 : "=r" (__xx.__i.__h), \
1239 "=r" (__xx.__i.__l) \
1240 : "%1" (__m0), \
1241 "rQR" (__m1)); \
1242 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1243 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1244 + (((signed int) __m1 >> 15) & __m0)); \
1245 } while (0)
1246 #endif /* __z8000__ */
1247
1248 #endif /* __GNUC__ */
1249
1250 /* If this machine has no inline assembler, use C macros. */
1251
1252 #if !defined (add_ssaaaa)
1253 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1254 do { \
1255 UWtype __x; \
1256 __x = (al) + (bl); \
1257 (sh) = (ah) + (bh) + (__x < (al)); \
1258 (sl) = __x; \
1259 } while (0)
1260 #endif
1261
1262 #if !defined (sub_ddmmss)
1263 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1264 do { \
1265 UWtype __x; \
1266 __x = (al) - (bl); \
1267 (sh) = (ah) - (bh) - (__x > (al)); \
1268 (sl) = __x; \
1269 } while (0)
1270 #endif
1271
1272 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1273 smul_ppmm. */
1274 #if !defined (umul_ppmm) && defined (smul_ppmm)
1275 #define umul_ppmm(w1, w0, u, v) \
1276 do { \
1277 UWtype __w1; \
1278 UWtype __xm0 = (u), __xm1 = (v); \
1279 smul_ppmm (__w1, w0, __xm0, __xm1); \
1280 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1281 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1282 } while (0)
1283 #endif
1284
1285 /* If we still don't have umul_ppmm, define it using plain C. */
1286 #if !defined (umul_ppmm)
1287 #define umul_ppmm(w1, w0, u, v) \
1288 do { \
1289 UWtype __x0, __x1, __x2, __x3; \
1290 UHWtype __ul, __vl, __uh, __vh; \
1291 \
1292 __ul = __ll_lowpart (u); \
1293 __uh = __ll_highpart (u); \
1294 __vl = __ll_lowpart (v); \
1295 __vh = __ll_highpart (v); \
1296 \
1297 __x0 = (UWtype) __ul * __vl; \
1298 __x1 = (UWtype) __ul * __vh; \
1299 __x2 = (UWtype) __uh * __vl; \
1300 __x3 = (UWtype) __uh * __vh; \
1301 \
1302 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1303 __x1 += __x2; /* but this indeed can */ \
1304 if (__x1 < __x2) /* did we get it? */ \
1305 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1306 \
1307 (w1) = __x3 + __ll_highpart (__x1); \
1308 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1309 } while (0)
1310 #endif
1311
1312 #if !defined (__umulsidi3)
1313 #define __umulsidi3(u, v) \
1314 ({DWunion __w; \
1315 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1316 __w.ll; })
1317 #endif
1318
1319 /* Define this unconditionally, so it can be used for debugging. */
1320 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1321 do { \
1322 UWtype __d1, __d0, __q1, __q0; \
1323 UWtype __r1, __r0, __m; \
1324 __d1 = __ll_highpart (d); \
1325 __d0 = __ll_lowpart (d); \
1326 \
1327 __r1 = (n1) % __d1; \
1328 __q1 = (n1) / __d1; \
1329 __m = (UWtype) __q1 * __d0; \
1330 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1331 if (__r1 < __m) \
1332 { \
1333 __q1--, __r1 += (d); \
1334 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1335 if (__r1 < __m) \
1336 __q1--, __r1 += (d); \
1337 } \
1338 __r1 -= __m; \
1339 \
1340 __r0 = __r1 % __d1; \
1341 __q0 = __r1 / __d1; \
1342 __m = (UWtype) __q0 * __d0; \
1343 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1344 if (__r0 < __m) \
1345 { \
1346 __q0--, __r0 += (d); \
1347 if (__r0 >= (d)) \
1348 if (__r0 < __m) \
1349 __q0--, __r0 += (d); \
1350 } \
1351 __r0 -= __m; \
1352 \
1353 (q) = (UWtype) __q1 * __ll_B | __q0; \
1354 (r) = __r0; \
1355 } while (0)
1356
1357 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1358 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1359 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1360 #define udiv_qrnnd(q, r, nh, nl, d) \
1361 do { \
1362 USItype __r; \
1363 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1364 (r) = __r; \
1365 } while (0)
1366 #endif
1367
1368 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1369 #if !defined (udiv_qrnnd)
1370 #define UDIV_NEEDS_NORMALIZATION 1
1371 #define udiv_qrnnd __udiv_qrnnd_c
1372 #endif
1373
1374 #if !defined (count_leading_zeros)
1375 #define count_leading_zeros(count, x) \
1376 do { \
1377 UWtype __xr = (x); \
1378 UWtype __a; \
1379 \
1380 if (W_TYPE_SIZE <= 32) \
1381 { \
1382 __a = __xr < ((UWtype)1<<2*__BITS4) \
1383 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1384 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1385 } \
1386 else \
1387 { \
1388 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1389 if (((__xr >> __a) & 0xff) != 0) \
1390 break; \
1391 } \
1392 \
1393 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1394 } while (0)
1395 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1396 #endif
1397
1398 #if !defined (count_trailing_zeros)
1399 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1400 defined in asm, but if it is not, the C version above is good enough. */
1401 #define count_trailing_zeros(count, x) \
1402 do { \
1403 UWtype __ctz_x = (x); \
1404 UWtype __ctz_c; \
1405 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1406 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1407 } while (0)
1408 #endif
1409
1410 #ifndef UDIV_NEEDS_NORMALIZATION
1411 #define UDIV_NEEDS_NORMALIZATION 0
1412 #endif
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