1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb2_legitimate_index_p (enum machine_mode
, rtx
, int);
71 static int thumb1_base_register_rtx_p (rtx
, enum machine_mode
, int);
72 inline static int thumb1_index_register_rtx_p (rtx
, int);
73 static int thumb_far_jump_used_p (void);
74 static bool thumb_force_lr_save (void);
75 static unsigned long thumb1_compute_save_reg_mask (void);
76 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
77 static rtx
emit_sfm (int, int);
78 static int arm_size_return_regs (void);
80 static bool arm_assemble_integer (rtx
, unsigned int, int);
82 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
83 static arm_cc
get_arm_condition_code (rtx
);
84 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
85 static rtx
is_jump_table (rtx
);
86 static const char *output_multi_immediate (rtx
*, const char *, const char *,
88 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
89 static struct machine_function
*arm_init_machine_status (void);
90 static void thumb_exit (FILE *, int);
91 static rtx
is_jump_table (rtx
);
92 static HOST_WIDE_INT
get_jump_table_size (rtx
);
93 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_forward_ref (Mfix
*);
95 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
96 static Mnode
*add_minipool_backward_ref (Mfix
*);
97 static void assign_minipool_offsets (Mfix
*);
98 static void arm_print_value (FILE *, rtx
);
99 static void dump_minipool (rtx
);
100 static int arm_barrier_cost (rtx
);
101 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
102 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
103 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
107 static int current_file_function_operand (rtx
);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree
);
111 static unsigned long arm_compute_func_type (void);
112 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
113 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
115 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
119 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT
);
120 static int arm_comp_type_attributes (tree
, tree
);
121 static void arm_set_default_type_attributes (tree
);
122 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
123 static int count_insns_for_constant (HOST_WIDE_INT
, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree
, tree
);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
129 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
130 static bool arm_size_rtx_costs (rtx
, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
135 static int arm_address_cost (rtx
);
136 static bool arm_memory_load_p (rtx
);
137 static bool arm_cirrus_insn_p (rtx
);
138 static void cirrus_reorg (rtx
);
139 static void arm_init_builtins (void);
140 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
143 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
144 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
145 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
146 static void emit_constant_insn (rtx cond
, rtx pattern
);
147 static rtx
emit_set_insn (rtx
, rtx
);
148 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
151 #ifdef OBJECT_FORMAT_ELF
152 static void arm_elf_asm_constructor (rtx
, int);
155 static void arm_encode_section_info (tree
, rtx
, int);
158 static void arm_file_end (void);
159 static void arm_file_start (void);
162 static void aof_globalize_label (FILE *, const char *);
163 static void aof_dump_imports (FILE *);
164 static void aof_dump_pic_table (FILE *);
165 static void aof_file_start (void);
166 static void aof_file_end (void);
167 static void aof_asm_init_sections (void);
169 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
171 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
172 enum machine_mode
, tree
, bool);
173 static bool arm_promote_prototypes (tree
);
174 static bool arm_default_short_enums (void);
175 static bool arm_align_anon_bitfield (void);
176 static bool arm_return_in_msb (tree
);
177 static bool arm_must_pass_in_stack (enum machine_mode
, tree
);
178 #ifdef TARGET_UNWIND_INFO
179 static void arm_unwind_emit (FILE *, rtx
);
180 static bool arm_output_ttype (rtx
);
182 static void arm_dwarf_handle_frame_unspec (const char *, rtx
, int);
184 static tree
arm_cxx_guard_type (void);
185 static bool arm_cxx_guard_mask_bit (void);
186 static tree
arm_get_cookie_size (tree
);
187 static bool arm_cookie_has_size (void);
188 static bool arm_cxx_cdtor_returns_this (void);
189 static bool arm_cxx_key_method_may_be_inline (void);
190 static void arm_cxx_determine_class_data_visibility (tree
);
191 static bool arm_cxx_class_data_always_comdat (void);
192 static bool arm_cxx_use_aeabi_atexit (void);
193 static void arm_init_libfuncs (void);
194 static bool arm_handle_option (size_t, const char *, int);
195 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
196 static bool arm_cannot_copy_insn_p (rtx
);
197 static bool arm_tls_symbol_p (rtx x
);
200 /* Initialize the GCC target structure. */
201 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
202 #undef TARGET_MERGE_DECL_ATTRIBUTES
203 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
209 #undef TARGET_ASM_FILE_START
210 #define TARGET_ASM_FILE_START arm_file_start
211 #undef TARGET_ASM_FILE_END
212 #define TARGET_ASM_FILE_END arm_file_end
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tDCB\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
223 #undef TARGET_ASM_FILE_START
224 #define TARGET_ASM_FILE_START aof_file_start
225 #undef TARGET_ASM_FILE_END
226 #define TARGET_ASM_FILE_END aof_file_end
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP NULL
230 #undef TARGET_ASM_INTEGER
231 #define TARGET_ASM_INTEGER arm_assemble_integer
234 #undef TARGET_ASM_FUNCTION_PROLOGUE
235 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
237 #undef TARGET_ASM_FUNCTION_EPILOGUE
238 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
240 #undef TARGET_DEFAULT_TARGET_FLAGS
241 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
242 #undef TARGET_HANDLE_OPTION
243 #define TARGET_HANDLE_OPTION arm_handle_option
245 #undef TARGET_COMP_TYPE_ATTRIBUTES
246 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
248 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
249 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
251 #undef TARGET_SCHED_ADJUST_COST
252 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
254 #undef TARGET_ENCODE_SECTION_INFO
256 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
258 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
261 #undef TARGET_STRIP_NAME_ENCODING
262 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
264 #undef TARGET_ASM_INTERNAL_LABEL
265 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
267 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
268 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
275 /* This will be overridden in arm_override_options. */
276 #undef TARGET_RTX_COSTS
277 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
278 #undef TARGET_ADDRESS_COST
279 #define TARGET_ADDRESS_COST arm_address_cost
281 #undef TARGET_SHIFT_TRUNCATION_MASK
282 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
283 #undef TARGET_VECTOR_MODE_SUPPORTED_P
284 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
286 #undef TARGET_MACHINE_DEPENDENT_REORG
287 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS arm_init_builtins
291 #undef TARGET_EXPAND_BUILTIN
292 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
294 #undef TARGET_INIT_LIBFUNCS
295 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
297 #undef TARGET_PROMOTE_FUNCTION_ARGS
298 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
299 #undef TARGET_PROMOTE_FUNCTION_RETURN
300 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
301 #undef TARGET_PROMOTE_PROTOTYPES
302 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
303 #undef TARGET_PASS_BY_REFERENCE
304 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
305 #undef TARGET_ARG_PARTIAL_BYTES
306 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
308 #undef TARGET_SETUP_INCOMING_VARARGS
309 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
311 #undef TARGET_DEFAULT_SHORT_ENUMS
312 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
314 #undef TARGET_ALIGN_ANON_BITFIELD
315 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
317 #undef TARGET_NARROW_VOLATILE_BITFIELD
318 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
320 #undef TARGET_CXX_GUARD_TYPE
321 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
323 #undef TARGET_CXX_GUARD_MASK_BIT
324 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
326 #undef TARGET_CXX_GET_COOKIE_SIZE
327 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
329 #undef TARGET_CXX_COOKIE_HAS_SIZE
330 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
332 #undef TARGET_CXX_CDTOR_RETURNS_THIS
333 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
335 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
336 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
338 #undef TARGET_CXX_USE_AEABI_ATEXIT
339 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
341 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
342 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
343 arm_cxx_determine_class_data_visibility
345 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
346 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
348 #undef TARGET_RETURN_IN_MSB
349 #define TARGET_RETURN_IN_MSB arm_return_in_msb
351 #undef TARGET_MUST_PASS_IN_STACK
352 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
354 #ifdef TARGET_UNWIND_INFO
355 #undef TARGET_UNWIND_EMIT
356 #define TARGET_UNWIND_EMIT arm_unwind_emit
358 /* EABI unwinding tables use a different format for the typeinfo tables. */
359 #undef TARGET_ASM_TTYPE
360 #define TARGET_ASM_TTYPE arm_output_ttype
362 #undef TARGET_ARM_EABI_UNWINDER
363 #define TARGET_ARM_EABI_UNWINDER true
364 #endif /* TARGET_UNWIND_INFO */
366 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
367 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
369 #undef TARGET_CANNOT_COPY_INSN_P
370 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
373 #undef TARGET_HAVE_TLS
374 #define TARGET_HAVE_TLS true
377 #undef TARGET_CANNOT_FORCE_CONST_MEM
378 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
380 struct gcc_target targetm
= TARGET_INITIALIZER
;
382 /* Obstack for minipool constant handling. */
383 static struct obstack minipool_obstack
;
384 static char * minipool_startobj
;
386 /* The maximum number of insns skipped which
387 will be conditionalised if possible. */
388 static int max_insns_skipped
= 5;
390 extern FILE * asm_out_file
;
392 /* True if we are currently building a constant table. */
393 int making_const_table
;
395 /* Define the information needed to generate branch insns. This is
396 stored from the compare operation. */
397 rtx arm_compare_op0
, arm_compare_op1
;
399 /* The processor for which instructions should be scheduled. */
400 enum processor_type arm_tune
= arm_none
;
402 /* The default processor used if not overridden by commandline. */
403 static enum processor_type arm_default_cpu
= arm_none
;
405 /* Which floating point model to use. */
406 enum arm_fp_model arm_fp_model
;
408 /* Which floating point hardware is available. */
409 enum fputype arm_fpu_arch
;
411 /* Which floating point hardware to schedule for. */
412 enum fputype arm_fpu_tune
;
414 /* Whether to use floating point hardware. */
415 enum float_abi_type arm_float_abi
;
417 /* Which ABI to use. */
418 enum arm_abi_type arm_abi
;
420 /* Which thread pointer model to use. */
421 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
423 /* Used to parse -mstructure_size_boundary command line option. */
424 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
426 /* Used for Thumb call_via trampolines. */
427 rtx thumb_call_via_label
[14];
428 static int thumb_call_reg_needed
;
430 /* Bit values used to identify processor capabilities. */
431 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
432 #define FL_ARCH3M (1 << 1) /* Extended multiply */
433 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
434 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
435 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
436 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
437 #define FL_THUMB (1 << 6) /* Thumb aware */
438 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
439 #define FL_STRONG (1 << 8) /* StrongARM */
440 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
441 #define FL_XSCALE (1 << 10) /* XScale */
442 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
443 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
444 media instructions. */
445 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
446 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
447 Note: ARM6 & 7 derivatives only. */
448 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
449 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
450 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
452 #define FL_DIV (1 << 18) /* Hardware divide. */
454 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
456 #define FL_FOR_ARCH2 FL_NOTM
457 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
458 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
459 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
460 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
461 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
462 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
463 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
464 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
465 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
466 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
467 #define FL_FOR_ARCH6J FL_FOR_ARCH6
468 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
469 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
470 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
471 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
472 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
473 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
474 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
475 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
477 /* The bits in this mask specify which
478 instructions we are allowed to generate. */
479 static unsigned long insn_flags
= 0;
481 /* The bits in this mask specify which instruction scheduling options should
483 static unsigned long tune_flags
= 0;
485 /* The following are used in the arm.md file as equivalents to bits
486 in the above two flag variables. */
488 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
491 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
494 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
497 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
500 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
503 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
506 /* Nonzero if this chip supports the ARM 6K extensions. */
509 /* Nonzero if instructions not present in the 'M' profile can be used. */
510 int arm_arch_notm
= 0;
512 /* Nonzero if this chip can benefit from load scheduling. */
513 int arm_ld_sched
= 0;
515 /* Nonzero if this chip is a StrongARM. */
516 int arm_tune_strongarm
= 0;
518 /* Nonzero if this chip is a Cirrus variant. */
519 int arm_arch_cirrus
= 0;
521 /* Nonzero if this chip supports Intel Wireless MMX technology. */
522 int arm_arch_iwmmxt
= 0;
524 /* Nonzero if this chip is an XScale. */
525 int arm_arch_xscale
= 0;
527 /* Nonzero if tuning for XScale */
528 int arm_tune_xscale
= 0;
530 /* Nonzero if we want to tune for stores that access the write-buffer.
531 This typically means an ARM6 or ARM7 with MMU or MPU. */
532 int arm_tune_wbuf
= 0;
534 /* Nonzero if generating Thumb instructions. */
537 /* Nonzero if we should define __THUMB_INTERWORK__ in the
539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542 int arm_cpp_interwork
= 0;
544 /* Nonzero if chip supports Thumb 2. */
547 /* Nonzero if chip supports integer division instruction. */
550 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
551 must report the mode of the memory reference from PRINT_OPERAND to
552 PRINT_OPERAND_ADDRESS. */
553 enum machine_mode output_memory_reference_mode
;
555 /* The register number to be used for the PIC offset register. */
556 unsigned arm_pic_register
= INVALID_REGNUM
;
558 /* Set to 1 when a return insn is output, this means that the epilogue
560 int return_used_this_function
;
562 /* Set to 1 after arm_reorg has started. Reset to start at the start of
563 the next function. */
564 static int after_arm_reorg
= 0;
566 /* The maximum number of insns to be used when loading a constant. */
567 static int arm_constant_limit
= 3;
569 /* For an explanation of these variables, see final_prescan_insn below. */
571 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
572 enum arm_cond_code arm_current_cc
;
574 int arm_target_label
;
575 /* The number of conditionally executed insns, including the current insn. */
576 int arm_condexec_count
= 0;
577 /* A bitmask specifying the patterns for the IT block.
578 Zero means do not output an IT block before this insn. */
579 int arm_condexec_mask
= 0;
580 /* The number of bits used in arm_condexec_mask. */
581 int arm_condexec_masklen
= 0;
583 /* The condition codes of the ARM, and the inverse function. */
584 static const char * const arm_condition_codes
[] =
586 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
587 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
590 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
591 #define streq(string1, string2) (strcmp (string1, string2) == 0)
593 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
594 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
595 | (1 << PIC_OFFSET_TABLE_REGNUM)))
597 /* Initialization code. */
601 const char *const name
;
602 enum processor_type core
;
604 const unsigned long flags
;
605 bool (* rtx_costs
) (rtx
, int, int, int *);
608 /* Not all of these give usefully different compilation alternatives,
609 but there is no simple way of generalizing them. */
610 static const struct processors all_cores
[] =
613 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
614 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
615 #include "arm-cores.def"
617 {NULL
, arm_none
, NULL
, 0, NULL
}
620 static const struct processors all_architectures
[] =
622 /* ARM Architectures */
623 /* We don't specify rtx_costs here as it will be figured out
626 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
627 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
628 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
629 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
630 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
631 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
632 implementations that support it, so we will leave it out for now. */
633 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
634 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
635 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
636 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
637 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
638 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
639 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
640 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
641 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
642 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
643 {"armv6t2", arm1156t2s
, "6T2", FL_CO_PROC
| FL_FOR_ARCH6T2
, NULL
},
644 {"armv7", cortexa8
, "7", FL_CO_PROC
| FL_FOR_ARCH7
, NULL
},
645 {"armv7-a", cortexa8
, "7A", FL_CO_PROC
| FL_FOR_ARCH7A
, NULL
},
646 {"armv7-r", cortexr4
, "7R", FL_CO_PROC
| FL_FOR_ARCH7R
, NULL
},
647 {"armv7-m", cortexm3
, "7M", FL_CO_PROC
| FL_FOR_ARCH7M
, NULL
},
648 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
649 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
650 {NULL
, arm_none
, NULL
, 0 , NULL
}
653 struct arm_cpu_select
657 const struct processors
* processors
;
660 /* This is a magic structure. The 'string' field is magically filled in
661 with a pointer to the value specified by the user on the command line
662 assuming that the user has specified such a value. */
664 static struct arm_cpu_select arm_select
[] =
666 /* string name processors */
667 { NULL
, "-mcpu=", all_cores
},
668 { NULL
, "-march=", all_architectures
},
669 { NULL
, "-mtune=", all_cores
}
672 /* Defines representing the indexes into the above table. */
673 #define ARM_OPT_SET_CPU 0
674 #define ARM_OPT_SET_ARCH 1
675 #define ARM_OPT_SET_TUNE 2
677 /* The name of the preprocessor macro to define for this architecture. */
679 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
688 /* Available values for -mfpu=. */
690 static const struct fpu_desc all_fpus
[] =
692 {"fpa", FPUTYPE_FPA
},
693 {"fpe2", FPUTYPE_FPA_EMU2
},
694 {"fpe3", FPUTYPE_FPA_EMU2
},
695 {"maverick", FPUTYPE_MAVERICK
},
700 /* Floating point models used by the different hardware.
701 See fputype in arm.h. */
703 static const enum fputype fp_model_for_fpu
[] =
705 /* No FP hardware. */
706 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
707 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
708 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
709 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
710 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
711 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
718 enum float_abi_type abi_type
;
722 /* Available values for -mfloat-abi=. */
724 static const struct float_abi all_float_abis
[] =
726 {"soft", ARM_FLOAT_ABI_SOFT
},
727 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
728 {"hard", ARM_FLOAT_ABI_HARD
}
735 enum arm_abi_type abi_type
;
739 /* Available values for -mabi=. */
741 static const struct abi_name arm_all_abis
[] =
743 {"apcs-gnu", ARM_ABI_APCS
},
744 {"atpcs", ARM_ABI_ATPCS
},
745 {"aapcs", ARM_ABI_AAPCS
},
746 {"iwmmxt", ARM_ABI_IWMMXT
},
747 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
750 /* Supported TLS relocations. */
760 /* Emit an insn that's a simple single-set. Both the operands must be known
763 emit_set_insn (rtx x
, rtx y
)
765 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
768 /* Return the number of bits set in VALUE. */
770 bit_count (unsigned long value
)
772 unsigned long count
= 0;
777 value
&= value
- 1; /* Clear the least-significant set bit. */
783 /* Set up library functions unique to ARM. */
786 arm_init_libfuncs (void)
788 /* There are no special library functions unless we are using the
793 /* The functions below are described in Section 4 of the "Run-Time
794 ABI for the ARM architecture", Version 1.0. */
796 /* Double-precision floating-point arithmetic. Table 2. */
797 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
798 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
799 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
800 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
801 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
803 /* Double-precision comparisons. Table 3. */
804 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
805 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
806 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
807 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
808 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
809 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
810 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
812 /* Single-precision floating-point arithmetic. Table 4. */
813 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
814 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
815 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
816 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
817 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
819 /* Single-precision comparisons. Table 5. */
820 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
821 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
822 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
823 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
824 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
825 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
826 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
828 /* Floating-point to integer conversions. Table 6. */
829 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
830 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
831 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
832 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
833 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
834 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
835 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
836 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
838 /* Conversions between floating types. Table 7. */
839 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
840 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
842 /* Integer to floating-point conversions. Table 8. */
843 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
844 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
845 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
846 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
847 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
848 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
849 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
850 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
852 /* Long long. Table 9. */
853 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
854 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
855 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
856 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
857 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
858 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
859 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
860 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
862 /* Integer (32/32->32) division. \S 4.3.1. */
863 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
864 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
866 /* The divmod functions are designed so that they can be used for
867 plain division, even though they return both the quotient and the
868 remainder. The quotient is returned in the usual location (i.e.,
869 r0 for SImode, {r0, r1} for DImode), just as would be expected
870 for an ordinary division routine. Because the AAPCS calling
871 conventions specify that all of { r0, r1, r2, r3 } are
872 callee-saved registers, there is no need to tell the compiler
873 explicitly that those registers are clobbered by these
875 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
876 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
878 /* For SImode division the ABI provides div-without-mod routines,
880 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
881 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
883 /* We don't have mod libcalls. Fortunately gcc knows how to use the
884 divmod libcalls instead. */
885 set_optab_libfunc (smod_optab
, DImode
, NULL
);
886 set_optab_libfunc (umod_optab
, DImode
, NULL
);
887 set_optab_libfunc (smod_optab
, SImode
, NULL
);
888 set_optab_libfunc (umod_optab
, SImode
, NULL
);
891 /* Implement TARGET_HANDLE_OPTION. */
894 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
899 arm_select
[1].string
= arg
;
903 arm_select
[0].string
= arg
;
906 case OPT_mhard_float
:
907 target_float_abi_name
= "hard";
910 case OPT_msoft_float
:
911 target_float_abi_name
= "soft";
915 arm_select
[2].string
= arg
;
923 /* Fix up any incompatible options that the user has specified.
924 This has now turned into a maze. */
926 arm_override_options (void)
929 enum processor_type target_arch_cpu
= arm_none
;
931 /* Set up the flags based on the cpu/architecture selected by the user. */
932 for (i
= ARRAY_SIZE (arm_select
); i
--;)
934 struct arm_cpu_select
* ptr
= arm_select
+ i
;
936 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
938 const struct processors
* sel
;
940 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
941 if (streq (ptr
->string
, sel
->name
))
943 /* Set the architecture define. */
944 if (i
!= ARM_OPT_SET_TUNE
)
945 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
947 /* Determine the processor core for which we should
948 tune code-generation. */
949 if (/* -mcpu= is a sensible default. */
951 /* -mtune= overrides -mcpu= and -march=. */
952 || i
== ARM_OPT_SET_TUNE
)
953 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
955 /* Remember the CPU associated with this architecture.
956 If no other option is used to set the CPU type,
957 we'll use this to guess the most suitable tuning
959 if (i
== ARM_OPT_SET_ARCH
)
960 target_arch_cpu
= sel
->core
;
962 if (i
!= ARM_OPT_SET_TUNE
)
964 /* If we have been given an architecture and a processor
965 make sure that they are compatible. We only generate
966 a warning though, and we prefer the CPU over the
968 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
969 warning (0, "switch -mcpu=%s conflicts with -march= switch",
972 insn_flags
= sel
->flags
;
978 if (sel
->name
== NULL
)
979 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
983 /* Guess the tuning options from the architecture if necessary. */
984 if (arm_tune
== arm_none
)
985 arm_tune
= target_arch_cpu
;
987 /* If the user did not specify a processor, choose one for them. */
990 const struct processors
* sel
;
992 enum processor_type cpu
;
994 cpu
= TARGET_CPU_DEFAULT
;
997 #ifdef SUBTARGET_CPU_DEFAULT
998 /* Use the subtarget default CPU if none was specified by
1000 cpu
= SUBTARGET_CPU_DEFAULT
;
1002 /* Default to ARM6. */
1003 if (cpu
== arm_none
)
1006 sel
= &all_cores
[cpu
];
1008 insn_flags
= sel
->flags
;
1010 /* Now check to see if the user has specified some command line
1011 switch that require certain abilities from the cpu. */
1014 if (TARGET_INTERWORK
|| TARGET_THUMB
)
1016 sought
|= (FL_THUMB
| FL_MODE32
);
1018 /* There are no ARM processors that support both APCS-26 and
1019 interworking. Therefore we force FL_MODE26 to be removed
1020 from insn_flags here (if it was set), so that the search
1021 below will always be able to find a compatible processor. */
1022 insn_flags
&= ~FL_MODE26
;
1025 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
1027 /* Try to locate a CPU type that supports all of the abilities
1028 of the default CPU, plus the extra abilities requested by
1030 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1031 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
1034 if (sel
->name
== NULL
)
1036 unsigned current_bit_count
= 0;
1037 const struct processors
* best_fit
= NULL
;
1039 /* Ideally we would like to issue an error message here
1040 saying that it was not possible to find a CPU compatible
1041 with the default CPU, but which also supports the command
1042 line options specified by the programmer, and so they
1043 ought to use the -mcpu=<name> command line option to
1044 override the default CPU type.
1046 If we cannot find a cpu that has both the
1047 characteristics of the default cpu and the given
1048 command line options we scan the array again looking
1049 for a best match. */
1050 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1051 if ((sel
->flags
& sought
) == sought
)
1055 count
= bit_count (sel
->flags
& insn_flags
);
1057 if (count
>= current_bit_count
)
1060 current_bit_count
= count
;
1064 gcc_assert (best_fit
);
1068 insn_flags
= sel
->flags
;
1070 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1071 arm_default_cpu
= (enum processor_type
) (sel
- all_cores
);
1072 if (arm_tune
== arm_none
)
1073 arm_tune
= arm_default_cpu
;
1076 /* The processor for which we should tune should now have been
1078 gcc_assert (arm_tune
!= arm_none
);
1080 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1082 targetm
.rtx_costs
= arm_size_rtx_costs
;
1084 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
1086 /* Make sure that the processor choice does not conflict with any of the
1087 other command line choices. */
1088 if (TARGET_ARM
&& !(insn_flags
& FL_NOTM
))
1089 error ("target CPU does not support ARM mode");
1091 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
1093 warning (0, "target CPU does not support interworking" );
1094 target_flags
&= ~MASK_INTERWORK
;
1097 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1099 warning (0, "target CPU does not support THUMB instructions");
1100 target_flags
&= ~MASK_THUMB
;
1103 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1105 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1106 target_flags
&= ~MASK_APCS_FRAME
;
1109 /* Callee super interworking implies thumb interworking. Adding
1110 this to the flags here simplifies the logic elsewhere. */
1111 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1112 target_flags
|= MASK_INTERWORK
;
1114 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1115 from here where no function is being compiled currently. */
1116 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1117 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1119 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1120 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1122 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1123 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1125 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1127 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1128 target_flags
|= MASK_APCS_FRAME
;
1131 if (TARGET_POKE_FUNCTION_NAME
)
1132 target_flags
|= MASK_APCS_FRAME
;
1134 if (TARGET_APCS_REENT
&& flag_pic
)
1135 error ("-fpic and -mapcs-reent are incompatible");
1137 if (TARGET_APCS_REENT
)
1138 warning (0, "APCS reentrant code not supported. Ignored");
1140 /* If this target is normally configured to use APCS frames, warn if they
1141 are turned off and debugging is turned on. */
1143 && write_symbols
!= NO_DEBUG
1144 && !TARGET_APCS_FRAME
1145 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1146 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1148 if (TARGET_APCS_FLOAT
)
1149 warning (0, "passing floating point arguments in fp regs not yet supported");
1151 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1152 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1153 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1154 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1155 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1156 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1157 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1158 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1159 arm_arch_notm
= (insn_flags
& FL_NOTM
) != 0;
1160 arm_arch_thumb2
= (insn_flags
& FL_THUMB2
) != 0;
1161 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1162 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1164 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1165 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1166 thumb_code
= (TARGET_ARM
== 0);
1167 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1168 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1169 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1170 arm_arch_hwdiv
= (insn_flags
& FL_DIV
) != 0;
1172 /* V5 code we generate is completely interworking capable, so we turn off
1173 TARGET_INTERWORK here to avoid many tests later on. */
1175 /* XXX However, we must pass the right pre-processor defines to CPP
1176 or GLD can get confused. This is a hack. */
1177 if (TARGET_INTERWORK
)
1178 arm_cpp_interwork
= 1;
1181 target_flags
&= ~MASK_INTERWORK
;
1183 if (target_abi_name
)
1185 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1187 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1189 arm_abi
= arm_all_abis
[i
].abi_type
;
1193 if (i
== ARRAY_SIZE (arm_all_abis
))
1194 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1197 arm_abi
= ARM_DEFAULT_ABI
;
1199 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1200 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1202 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1203 error ("iwmmxt abi requires an iwmmxt capable cpu");
1205 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
1206 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1208 if (streq (target_fpe_name
, "2"))
1209 target_fpu_name
= "fpe2";
1210 else if (streq (target_fpe_name
, "3"))
1211 target_fpu_name
= "fpe3";
1213 error ("invalid floating point emulation option: -mfpe=%s",
1216 if (target_fpu_name
!= NULL
)
1218 /* The user specified a FPU. */
1219 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1221 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1223 arm_fpu_arch
= all_fpus
[i
].fpu
;
1224 arm_fpu_tune
= arm_fpu_arch
;
1225 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1229 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1230 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1234 #ifdef FPUTYPE_DEFAULT
1235 /* Use the default if it is specified for this platform. */
1236 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1237 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1239 /* Pick one based on CPU type. */
1240 /* ??? Some targets assume FPA is the default.
1241 if ((insn_flags & FL_VFP) != 0)
1242 arm_fpu_arch = FPUTYPE_VFP;
1245 if (arm_arch_cirrus
)
1246 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1248 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1250 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1251 arm_fpu_tune
= FPUTYPE_FPA
;
1253 arm_fpu_tune
= arm_fpu_arch
;
1254 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1255 gcc_assert (arm_fp_model
!= ARM_FP_MODEL_UNKNOWN
);
1258 if (target_float_abi_name
!= NULL
)
1260 /* The user specified a FP ABI. */
1261 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1263 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1265 arm_float_abi
= all_float_abis
[i
].abi_type
;
1269 if (i
== ARRAY_SIZE (all_float_abis
))
1270 error ("invalid floating point abi: -mfloat-abi=%s",
1271 target_float_abi_name
);
1274 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1276 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1277 sorry ("-mfloat-abi=hard and VFP");
1279 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1280 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1281 will ever exist. GCC makes no attempt to support this combination. */
1282 if (TARGET_IWMMXT
&& !TARGET_SOFT_FLOAT
)
1283 sorry ("iWMMXt and hardware floating point");
1285 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1286 if (TARGET_THUMB2
&& TARGET_IWMMXT
)
1287 sorry ("Thumb-2 iWMMXt");
1289 /* If soft-float is specified then don't use FPU. */
1290 if (TARGET_SOFT_FLOAT
)
1291 arm_fpu_arch
= FPUTYPE_NONE
;
1293 /* For arm2/3 there is no need to do any scheduling if there is only
1294 a floating point emulator, or we are doing software floating-point. */
1295 if ((TARGET_SOFT_FLOAT
1296 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1297 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1298 && (tune_flags
& FL_MODE32
) == 0)
1299 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1301 if (target_thread_switch
)
1303 if (strcmp (target_thread_switch
, "soft") == 0)
1304 target_thread_pointer
= TP_SOFT
;
1305 else if (strcmp (target_thread_switch
, "auto") == 0)
1306 target_thread_pointer
= TP_AUTO
;
1307 else if (strcmp (target_thread_switch
, "cp15") == 0)
1308 target_thread_pointer
= TP_CP15
;
1310 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1313 /* Use the cp15 method if it is available. */
1314 if (target_thread_pointer
== TP_AUTO
)
1316 if (arm_arch6k
&& !TARGET_THUMB
)
1317 target_thread_pointer
= TP_CP15
;
1319 target_thread_pointer
= TP_SOFT
;
1322 if (TARGET_HARD_TP
&& TARGET_THUMB1
)
1323 error ("can not use -mtp=cp15 with 16-bit Thumb");
1325 /* Override the default structure alignment for AAPCS ABI. */
1326 if (TARGET_AAPCS_BASED
)
1327 arm_structure_size_boundary
= 8;
1329 if (structure_size_string
!= NULL
)
1331 int size
= strtol (structure_size_string
, NULL
, 0);
1333 if (size
== 8 || size
== 32
1334 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1335 arm_structure_size_boundary
= size
;
1337 warning (0, "structure size boundary can only be set to %s",
1338 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1341 /* If stack checking is disabled, we can use r10 as the PIC register,
1342 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1343 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1344 arm_pic_register
= (TARGET_APCS_STACK
|| TARGET_AAPCS_BASED
) ? 9 : 10;
1346 if (arm_pic_register_string
!= NULL
)
1348 int pic_register
= decode_reg_name (arm_pic_register_string
);
1351 warning (0, "-mpic-register= is useless without -fpic");
1353 /* Prevent the user from choosing an obviously stupid PIC register. */
1354 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1355 || pic_register
== HARD_FRAME_POINTER_REGNUM
1356 || pic_register
== STACK_POINTER_REGNUM
1357 || pic_register
>= PC_REGNUM
)
1358 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1360 arm_pic_register
= pic_register
;
1363 /* ??? We might want scheduling for thumb2. */
1364 if (TARGET_THUMB
&& flag_schedule_insns
)
1366 /* Don't warn since it's on by default in -O2. */
1367 flag_schedule_insns
= 0;
1372 arm_constant_limit
= 1;
1374 /* If optimizing for size, bump the number of instructions that we
1375 are prepared to conditionally execute (even on a StrongARM). */
1376 max_insns_skipped
= 6;
1380 /* For processors with load scheduling, it never costs more than
1381 2 cycles to load a constant, and the load scheduler may well
1382 reduce that to 1. */
1384 arm_constant_limit
= 1;
1386 /* On XScale the longer latency of a load makes it more difficult
1387 to achieve a good schedule, so it's faster to synthesize
1388 constants that can be done in two insns. */
1389 if (arm_tune_xscale
)
1390 arm_constant_limit
= 2;
1392 /* StrongARM has early execution of branches, so a sequence
1393 that is worth skipping is shorter. */
1394 if (arm_tune_strongarm
)
1395 max_insns_skipped
= 3;
1398 /* Register global variables with the garbage collector. */
1399 arm_add_gc_roots ();
1403 arm_add_gc_roots (void)
1405 gcc_obstack_init(&minipool_obstack
);
1406 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1409 /* A table of known ARM exception types.
1410 For use with the interrupt function attribute. */
1414 const char *const arg
;
1415 const unsigned long return_value
;
1419 static const isr_attribute_arg isr_attribute_args
[] =
1421 { "IRQ", ARM_FT_ISR
},
1422 { "irq", ARM_FT_ISR
},
1423 { "FIQ", ARM_FT_FIQ
},
1424 { "fiq", ARM_FT_FIQ
},
1425 { "ABORT", ARM_FT_ISR
},
1426 { "abort", ARM_FT_ISR
},
1427 { "ABORT", ARM_FT_ISR
},
1428 { "abort", ARM_FT_ISR
},
1429 { "UNDEF", ARM_FT_EXCEPTION
},
1430 { "undef", ARM_FT_EXCEPTION
},
1431 { "SWI", ARM_FT_EXCEPTION
},
1432 { "swi", ARM_FT_EXCEPTION
},
1433 { NULL
, ARM_FT_NORMAL
}
1436 /* Returns the (interrupt) function type of the current
1437 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1439 static unsigned long
1440 arm_isr_value (tree argument
)
1442 const isr_attribute_arg
* ptr
;
1446 return ARM_FT_NORMAL
| ARM_FT_STACKALIGN
;
1448 /* No argument - default to IRQ. */
1449 if (argument
== NULL_TREE
)
1452 /* Get the value of the argument. */
1453 if (TREE_VALUE (argument
) == NULL_TREE
1454 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1455 return ARM_FT_UNKNOWN
;
1457 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1459 /* Check it against the list of known arguments. */
1460 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1461 if (streq (arg
, ptr
->arg
))
1462 return ptr
->return_value
;
1464 /* An unrecognized interrupt type. */
1465 return ARM_FT_UNKNOWN
;
1468 /* Computes the type of the current function. */
1470 static unsigned long
1471 arm_compute_func_type (void)
1473 unsigned long type
= ARM_FT_UNKNOWN
;
1477 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1479 /* Decide if the current function is volatile. Such functions
1480 never return, and many memory cycles can be saved by not storing
1481 register values that will never be needed again. This optimization
1482 was added to speed up context switching in a kernel application. */
1484 && (TREE_NOTHROW (current_function_decl
)
1485 || !(flag_unwind_tables
1486 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
)))
1487 && TREE_THIS_VOLATILE (current_function_decl
))
1488 type
|= ARM_FT_VOLATILE
;
1490 if (cfun
->static_chain_decl
!= NULL
)
1491 type
|= ARM_FT_NESTED
;
1493 attr
= DECL_ATTRIBUTES (current_function_decl
);
1495 a
= lookup_attribute ("naked", attr
);
1497 type
|= ARM_FT_NAKED
;
1499 a
= lookup_attribute ("isr", attr
);
1501 a
= lookup_attribute ("interrupt", attr
);
1504 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1506 type
|= arm_isr_value (TREE_VALUE (a
));
1511 /* Returns the type of the current function. */
1514 arm_current_func_type (void)
1516 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1517 cfun
->machine
->func_type
= arm_compute_func_type ();
1519 return cfun
->machine
->func_type
;
1522 /* Return 1 if it is possible to return using a single instruction.
1523 If SIBLING is non-null, this is a test for a return before a sibling
1524 call. SIBLING is the call insn, so we can examine its register usage. */
1527 use_return_insn (int iscond
, rtx sibling
)
1530 unsigned int func_type
;
1531 unsigned long saved_int_regs
;
1532 unsigned HOST_WIDE_INT stack_adjust
;
1533 arm_stack_offsets
*offsets
;
1535 /* Never use a return instruction before reload has run. */
1536 if (!reload_completed
)
1539 func_type
= arm_current_func_type ();
1541 /* Naked, volatile and stack alignment functions need special
1543 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
| ARM_FT_STACKALIGN
))
1546 /* So do interrupt functions that use the frame pointer and Thumb
1547 interrupt functions. */
1548 if (IS_INTERRUPT (func_type
) && (frame_pointer_needed
|| TARGET_THUMB
))
1551 offsets
= arm_get_frame_offsets ();
1552 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1554 /* As do variadic functions. */
1555 if (current_function_pretend_args_size
1556 || cfun
->machine
->uses_anonymous_args
1557 /* Or if the function calls __builtin_eh_return () */
1558 || current_function_calls_eh_return
1559 /* Or if the function calls alloca */
1560 || current_function_calls_alloca
1561 /* Or if there is a stack adjustment. However, if the stack pointer
1562 is saved on the stack, we can use a pre-incrementing stack load. */
1563 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1566 saved_int_regs
= arm_compute_save_reg_mask ();
1568 /* Unfortunately, the insn
1570 ldmib sp, {..., sp, ...}
1572 triggers a bug on most SA-110 based devices, such that the stack
1573 pointer won't be correctly restored if the instruction takes a
1574 page fault. We work around this problem by popping r3 along with
1575 the other registers, since that is never slower than executing
1576 another instruction.
1578 We test for !arm_arch5 here, because code for any architecture
1579 less than this could potentially be run on one of the buggy
1581 if (stack_adjust
== 4 && !arm_arch5
&& TARGET_ARM
)
1583 /* Validate that r3 is a call-clobbered register (always true in
1584 the default abi) ... */
1585 if (!call_used_regs
[3])
1588 /* ... that it isn't being used for a return value ... */
1589 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
1592 /* ... or for a tail-call argument ... */
1595 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
1597 if (find_regno_fusage (sibling
, USE
, 3))
1601 /* ... and that there are no call-saved registers in r0-r2
1602 (always true in the default ABI). */
1603 if (saved_int_regs
& 0x7)
1607 /* Can't be done if interworking with Thumb, and any registers have been
1609 if (TARGET_INTERWORK
&& saved_int_regs
!= 0 && !IS_INTERRUPT(func_type
))
1612 /* On StrongARM, conditional returns are expensive if they aren't
1613 taken and multiple registers have been stacked. */
1614 if (iscond
&& arm_tune_strongarm
)
1616 /* Conditional return when just the LR is stored is a simple
1617 conditional-load instruction, that's not expensive. */
1618 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1622 && arm_pic_register
!= INVALID_REGNUM
1623 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1627 /* If there are saved registers but the LR isn't saved, then we need
1628 two instructions for the return. */
1629 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1632 /* Can't be done if any of the FPA regs are pushed,
1633 since this also requires an insn. */
1634 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1635 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1636 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1639 /* Likewise VFP regs. */
1640 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1641 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1642 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1645 if (TARGET_REALLY_IWMMXT
)
1646 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1647 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1653 /* Return TRUE if int I is a valid immediate ARM constant. */
1656 const_ok_for_arm (HOST_WIDE_INT i
)
1660 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1661 be all zero, or all one. */
1662 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1663 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1664 != ((~(unsigned HOST_WIDE_INT
) 0)
1665 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1668 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
1670 /* Fast return for 0 and small values. We must do this for zero, since
1671 the code below can't handle that one case. */
1672 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
1675 /* Get the number of trailing zeros. */
1676 lowbit
= ffs((int) i
) - 1;
1678 /* Only even shifts are allowed in ARM mode so round down to the
1679 nearest even number. */
1683 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
1688 /* Allow rotated constants in ARM mode. */
1690 && ((i
& ~0xc000003f) == 0
1691 || (i
& ~0xf000000f) == 0
1692 || (i
& ~0xfc000003) == 0))
1699 /* Allow repeated pattern. */
1702 if (i
== v
|| i
== (v
| (v
<< 8)))
1709 /* Return true if I is a valid constant for the operation CODE. */
1711 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1713 if (const_ok_for_arm (i
))
1719 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1721 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1727 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1734 /* Emit a sequence of insns to handle a large constant.
1735 CODE is the code of the operation required, it can be any of SET, PLUS,
1736 IOR, AND, XOR, MINUS;
1737 MODE is the mode in which the operation is being performed;
1738 VAL is the integer to operate on;
1739 SOURCE is the other operand (a register, or a null-pointer for SET);
1740 SUBTARGETS means it is safe to create scratch registers if that will
1741 either produce a simpler sequence, or we will want to cse the values.
1742 Return value is the number of insns emitted. */
1744 /* ??? Tweak this for thumb2. */
1746 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1747 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1751 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1752 cond
= COND_EXEC_TEST (PATTERN (insn
));
1756 if (subtargets
|| code
== SET
1757 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1758 && REGNO (target
) != REGNO (source
)))
1760 /* After arm_reorg has been called, we can't fix up expensive
1761 constants by pushing them into memory so we must synthesize
1762 them in-line, regardless of the cost. This is only likely to
1763 be more costly on chips that have load delay slots and we are
1764 compiling without running the scheduler (so no splitting
1765 occurred before the final instruction emission).
1767 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1769 if (!after_arm_reorg
1771 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1773 > arm_constant_limit
+ (code
!= SET
)))
1777 /* Currently SET is the only monadic value for CODE, all
1778 the rest are diadic. */
1779 emit_set_insn (target
, GEN_INT (val
));
1784 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1786 emit_set_insn (temp
, GEN_INT (val
));
1787 /* For MINUS, the value is subtracted from, since we never
1788 have subtraction of a constant. */
1790 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
1792 emit_set_insn (target
,
1793 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
1799 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1803 /* Return the number of ARM instructions required to synthesize the given
1806 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1808 HOST_WIDE_INT temp1
;
1816 if (remainder
& (3 << (i
- 2)))
1821 temp1
= remainder
& ((0x0ff << end
)
1822 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1823 remainder
&= ~temp1
;
1828 } while (remainder
);
1832 /* Emit an instruction with the indicated PATTERN. If COND is
1833 non-NULL, conditionalize the execution of the instruction on COND
1837 emit_constant_insn (rtx cond
, rtx pattern
)
1840 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1841 emit_insn (pattern
);
1844 /* As above, but extra parameter GENERATE which, if clear, suppresses
1846 /* ??? This needs more work for thumb2. */
1849 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1850 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1855 int can_negate_initial
= 0;
1858 int num_bits_set
= 0;
1859 int set_sign_bit_copies
= 0;
1860 int clear_sign_bit_copies
= 0;
1861 int clear_zero_bit_copies
= 0;
1862 int set_zero_bit_copies
= 0;
1864 unsigned HOST_WIDE_INT temp1
, temp2
;
1865 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1867 /* Find out which operations are safe for a given CODE. Also do a quick
1868 check for degenerate cases; these can occur when DImode operations
1880 can_negate_initial
= 1;
1884 if (remainder
== 0xffffffff)
1887 emit_constant_insn (cond
,
1888 gen_rtx_SET (VOIDmode
, target
,
1889 GEN_INT (ARM_SIGN_EXTEND (val
))));
1894 if (reload_completed
&& rtx_equal_p (target
, source
))
1897 emit_constant_insn (cond
,
1898 gen_rtx_SET (VOIDmode
, target
, source
));
1907 emit_constant_insn (cond
,
1908 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1911 if (remainder
== 0xffffffff)
1913 if (reload_completed
&& rtx_equal_p (target
, source
))
1916 emit_constant_insn (cond
,
1917 gen_rtx_SET (VOIDmode
, target
, source
));
1926 if (reload_completed
&& rtx_equal_p (target
, source
))
1929 emit_constant_insn (cond
,
1930 gen_rtx_SET (VOIDmode
, target
, source
));
1934 /* We don't know how to handle other cases yet. */
1935 gcc_assert (remainder
== 0xffffffff);
1938 emit_constant_insn (cond
,
1939 gen_rtx_SET (VOIDmode
, target
,
1940 gen_rtx_NOT (mode
, source
)));
1944 /* We treat MINUS as (val - source), since (source - val) is always
1945 passed as (source + (-val)). */
1949 emit_constant_insn (cond
,
1950 gen_rtx_SET (VOIDmode
, target
,
1951 gen_rtx_NEG (mode
, source
)));
1954 if (const_ok_for_arm (val
))
1957 emit_constant_insn (cond
,
1958 gen_rtx_SET (VOIDmode
, target
,
1959 gen_rtx_MINUS (mode
, GEN_INT (val
),
1971 /* If we can do it in one insn get out quickly. */
1972 if (const_ok_for_arm (val
)
1973 || (can_negate_initial
&& const_ok_for_arm (-val
))
1974 || (can_invert
&& const_ok_for_arm (~val
)))
1977 emit_constant_insn (cond
,
1978 gen_rtx_SET (VOIDmode
, target
,
1980 ? gen_rtx_fmt_ee (code
, mode
, source
,
1986 /* Calculate a few attributes that may be useful for specific
1988 for (i
= 31; i
>= 0; i
--)
1990 if ((remainder
& (1 << i
)) == 0)
1991 clear_sign_bit_copies
++;
1996 for (i
= 31; i
>= 0; i
--)
1998 if ((remainder
& (1 << i
)) != 0)
1999 set_sign_bit_copies
++;
2004 for (i
= 0; i
<= 31; i
++)
2006 if ((remainder
& (1 << i
)) == 0)
2007 clear_zero_bit_copies
++;
2012 for (i
= 0; i
<= 31; i
++)
2014 if ((remainder
& (1 << i
)) != 0)
2015 set_zero_bit_copies
++;
2023 /* See if we can use movw. */
2024 if (arm_arch_thumb2
&& (remainder
& 0xffff0000) == 0)
2027 emit_constant_insn (cond
, gen_rtx_SET (VOIDmode
, target
,
2032 /* See if we can do this by sign_extending a constant that is known
2033 to be negative. This is a good, way of doing it, since the shift
2034 may well merge into a subsequent insn. */
2035 if (set_sign_bit_copies
> 1)
2037 if (const_ok_for_arm
2038 (temp1
= ARM_SIGN_EXTEND (remainder
2039 << (set_sign_bit_copies
- 1))))
2043 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2044 emit_constant_insn (cond
,
2045 gen_rtx_SET (VOIDmode
, new_src
,
2047 emit_constant_insn (cond
,
2048 gen_ashrsi3 (target
, new_src
,
2049 GEN_INT (set_sign_bit_copies
- 1)));
2053 /* For an inverted constant, we will need to set the low bits,
2054 these will be shifted out of harm's way. */
2055 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
2056 if (const_ok_for_arm (~temp1
))
2060 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2061 emit_constant_insn (cond
,
2062 gen_rtx_SET (VOIDmode
, new_src
,
2064 emit_constant_insn (cond
,
2065 gen_ashrsi3 (target
, new_src
,
2066 GEN_INT (set_sign_bit_copies
- 1)));
2072 /* See if we can calculate the value as the difference between two
2073 valid immediates. */
2074 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
2076 int topshift
= clear_sign_bit_copies
& ~1;
2078 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
2079 & (0xff000000 >> topshift
));
2081 /* If temp1 is zero, then that means the 9 most significant
2082 bits of remainder were 1 and we've caused it to overflow.
2083 When topshift is 0 we don't need to do anything since we
2084 can borrow from 'bit 32'. */
2085 if (temp1
== 0 && topshift
!= 0)
2086 temp1
= 0x80000000 >> (topshift
- 1);
2088 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
2090 if (const_ok_for_arm (temp2
))
2094 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2095 emit_constant_insn (cond
,
2096 gen_rtx_SET (VOIDmode
, new_src
,
2098 emit_constant_insn (cond
,
2099 gen_addsi3 (target
, new_src
,
2107 /* See if we can generate this by setting the bottom (or the top)
2108 16 bits, and then shifting these into the other half of the
2109 word. We only look for the simplest cases, to do more would cost
2110 too much. Be careful, however, not to generate this when the
2111 alternative would take fewer insns. */
2112 if (val
& 0xffff0000)
2114 temp1
= remainder
& 0xffff0000;
2115 temp2
= remainder
& 0x0000ffff;
2117 /* Overlaps outside this range are best done using other methods. */
2118 for (i
= 9; i
< 24; i
++)
2120 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2121 && !const_ok_for_arm (temp2
))
2123 rtx new_src
= (subtargets
2124 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2126 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2127 source
, subtargets
, generate
);
2135 gen_rtx_ASHIFT (mode
, source
,
2142 /* Don't duplicate cases already considered. */
2143 for (i
= 17; i
< 24; i
++)
2145 if (((temp1
| (temp1
>> i
)) == remainder
)
2146 && !const_ok_for_arm (temp1
))
2148 rtx new_src
= (subtargets
2149 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2151 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2152 source
, subtargets
, generate
);
2157 gen_rtx_SET (VOIDmode
, target
,
2160 gen_rtx_LSHIFTRT (mode
, source
,
2171 /* If we have IOR or XOR, and the constant can be loaded in a
2172 single instruction, and we can find a temporary to put it in,
2173 then this can be done in two instructions instead of 3-4. */
2175 /* TARGET can't be NULL if SUBTARGETS is 0 */
2176 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2178 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2182 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2184 emit_constant_insn (cond
,
2185 gen_rtx_SET (VOIDmode
, sub
,
2187 emit_constant_insn (cond
,
2188 gen_rtx_SET (VOIDmode
, target
,
2189 gen_rtx_fmt_ee (code
, mode
,
2199 if (set_sign_bit_copies
> 8
2200 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2204 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2205 rtx shift
= GEN_INT (set_sign_bit_copies
);
2209 gen_rtx_SET (VOIDmode
, sub
,
2211 gen_rtx_ASHIFT (mode
,
2216 gen_rtx_SET (VOIDmode
, target
,
2218 gen_rtx_LSHIFTRT (mode
, sub
,
2224 if (set_zero_bit_copies
> 8
2225 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2229 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2230 rtx shift
= GEN_INT (set_zero_bit_copies
);
2234 gen_rtx_SET (VOIDmode
, sub
,
2236 gen_rtx_LSHIFTRT (mode
,
2241 gen_rtx_SET (VOIDmode
, target
,
2243 gen_rtx_ASHIFT (mode
, sub
,
2249 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2253 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2254 emit_constant_insn (cond
,
2255 gen_rtx_SET (VOIDmode
, sub
,
2256 gen_rtx_NOT (mode
, source
)));
2259 sub
= gen_reg_rtx (mode
);
2260 emit_constant_insn (cond
,
2261 gen_rtx_SET (VOIDmode
, sub
,
2262 gen_rtx_AND (mode
, source
,
2264 emit_constant_insn (cond
,
2265 gen_rtx_SET (VOIDmode
, target
,
2266 gen_rtx_NOT (mode
, sub
)));
2273 /* See if two shifts will do 2 or more insn's worth of work. */
2274 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2276 HOST_WIDE_INT shift_mask
= ((0xffffffff
2277 << (32 - clear_sign_bit_copies
))
2280 if ((remainder
| shift_mask
) != 0xffffffff)
2284 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2285 insns
= arm_gen_constant (AND
, mode
, cond
,
2286 remainder
| shift_mask
,
2287 new_src
, source
, subtargets
, 1);
2292 rtx targ
= subtargets
? NULL_RTX
: target
;
2293 insns
= arm_gen_constant (AND
, mode
, cond
,
2294 remainder
| shift_mask
,
2295 targ
, source
, subtargets
, 0);
2301 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2302 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2304 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2305 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2311 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2313 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2315 if ((remainder
| shift_mask
) != 0xffffffff)
2319 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2321 insns
= arm_gen_constant (AND
, mode
, cond
,
2322 remainder
| shift_mask
,
2323 new_src
, source
, subtargets
, 1);
2328 rtx targ
= subtargets
? NULL_RTX
: target
;
2330 insns
= arm_gen_constant (AND
, mode
, cond
,
2331 remainder
| shift_mask
,
2332 targ
, source
, subtargets
, 0);
2338 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2339 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2341 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2342 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2354 for (i
= 0; i
< 32; i
++)
2355 if (remainder
& (1 << i
))
2358 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2359 remainder
= (~remainder
) & 0xffffffff;
2360 else if (code
== PLUS
&& num_bits_set
> 16)
2361 remainder
= (-remainder
) & 0xffffffff;
2368 /* Now try and find a way of doing the job in either two or three
2370 We start by looking for the largest block of zeros that are aligned on
2371 a 2-bit boundary, we then fill up the temps, wrapping around to the
2372 top of the word when we drop off the bottom.
2373 In the worst case this code should produce no more than four insns.
2374 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2375 best place to start. */
2377 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2383 int best_consecutive_zeros
= 0;
2385 for (i
= 0; i
< 32; i
+= 2)
2387 int consecutive_zeros
= 0;
2389 if (!(remainder
& (3 << i
)))
2391 while ((i
< 32) && !(remainder
& (3 << i
)))
2393 consecutive_zeros
+= 2;
2396 if (consecutive_zeros
> best_consecutive_zeros
)
2398 best_consecutive_zeros
= consecutive_zeros
;
2399 best_start
= i
- consecutive_zeros
;
2405 /* So long as it won't require any more insns to do so, it's
2406 desirable to emit a small constant (in bits 0...9) in the last
2407 insn. This way there is more chance that it can be combined with
2408 a later addressing insn to form a pre-indexed load or store
2409 operation. Consider:
2411 *((volatile int *)0xe0000100) = 1;
2412 *((volatile int *)0xe0000110) = 2;
2414 We want this to wind up as:
2418 str rB, [rA, #0x100]
2420 str rB, [rA, #0x110]
2422 rather than having to synthesize both large constants from scratch.
2424 Therefore, we calculate how many insns would be required to emit
2425 the constant starting from `best_start', and also starting from
2426 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2427 yield a shorter sequence, we may as well use zero. */
2429 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2430 && (count_insns_for_constant (remainder
, 0) <=
2431 count_insns_for_constant (remainder
, best_start
)))
2435 /* Now start emitting the insns. */
2443 if (remainder
& (3 << (i
- 2)))
2448 temp1
= remainder
& ((0x0ff << end
)
2449 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2450 remainder
&= ~temp1
;
2454 rtx new_src
, temp1_rtx
;
2456 if (code
== SET
|| code
== MINUS
)
2458 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2459 if (can_invert
&& code
!= MINUS
)
2464 if (remainder
&& subtargets
)
2465 new_src
= gen_reg_rtx (mode
);
2470 else if (can_negate
)
2474 temp1
= trunc_int_for_mode (temp1
, mode
);
2475 temp1_rtx
= GEN_INT (temp1
);
2479 else if (code
== MINUS
)
2480 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2482 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2484 emit_constant_insn (cond
,
2485 gen_rtx_SET (VOIDmode
, new_src
,
2495 else if (code
== MINUS
)
2504 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
2517 /* Canonicalize a comparison so that we are more likely to recognize it.
2518 This can be done for a few constant compares, where we can make the
2519 immediate value easier to load. */
2522 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
2525 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2526 unsigned HOST_WIDE_INT maxval
;
2527 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
2538 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2540 *op1
= GEN_INT (i
+ 1);
2541 return code
== GT
? GE
: LT
;
2548 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2550 *op1
= GEN_INT (i
- 1);
2551 return code
== GE
? GT
: LE
;
2557 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2558 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2560 *op1
= GEN_INT (i
+ 1);
2561 return code
== GTU
? GEU
: LTU
;
2568 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2570 *op1
= GEN_INT (i
- 1);
2571 return code
== GEU
? GTU
: LEU
;
2583 /* Define how to find the value returned by a function. */
2586 arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2588 enum machine_mode mode
;
2589 int unsignedp ATTRIBUTE_UNUSED
;
2590 rtx r ATTRIBUTE_UNUSED
;
2592 mode
= TYPE_MODE (type
);
2593 /* Promote integer types. */
2594 if (INTEGRAL_TYPE_P (type
))
2595 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2597 /* Promotes small structs returned in a register to full-word size
2598 for big-endian AAPCS. */
2599 if (arm_return_in_msb (type
))
2601 HOST_WIDE_INT size
= int_size_in_bytes (type
);
2602 if (size
% UNITS_PER_WORD
!= 0)
2604 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
2605 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
2609 return LIBCALL_VALUE(mode
);
2612 /* Determine the amount of memory needed to store the possible return
2613 registers of an untyped call. */
2615 arm_apply_result_size (void)
2621 if (TARGET_HARD_FLOAT_ABI
)
2625 if (TARGET_MAVERICK
)
2628 if (TARGET_IWMMXT_ABI
)
2635 /* Decide whether a type should be returned in memory (true)
2636 or in a register (false). This is called by the macro
2637 RETURN_IN_MEMORY. */
2639 arm_return_in_memory (tree type
)
2643 if (!AGGREGATE_TYPE_P (type
) &&
2644 (TREE_CODE (type
) != VECTOR_TYPE
) &&
2645 !(TARGET_AAPCS_BASED
&& TREE_CODE (type
) == COMPLEX_TYPE
))
2646 /* All simple types are returned in registers.
2647 For AAPCS, complex types are treated the same as aggregates. */
2650 size
= int_size_in_bytes (type
);
2652 if (arm_abi
!= ARM_ABI_APCS
)
2654 /* ATPCS and later return aggregate types in memory only if they are
2655 larger than a word (or are variable size). */
2656 return (size
< 0 || size
> UNITS_PER_WORD
);
2659 /* To maximize backwards compatibility with previous versions of gcc,
2660 return vectors up to 4 words in registers. */
2661 if (TREE_CODE (type
) == VECTOR_TYPE
)
2662 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
2664 /* For the arm-wince targets we choose to be compatible with Microsoft's
2665 ARM and Thumb compilers, which always return aggregates in memory. */
2667 /* All structures/unions bigger than one word are returned in memory.
2668 Also catch the case where int_size_in_bytes returns -1. In this case
2669 the aggregate is either huge or of variable size, and in either case
2670 we will want to return it via memory and not in a register. */
2671 if (size
< 0 || size
> UNITS_PER_WORD
)
2674 if (TREE_CODE (type
) == RECORD_TYPE
)
2678 /* For a struct the APCS says that we only return in a register
2679 if the type is 'integer like' and every addressable element
2680 has an offset of zero. For practical purposes this means
2681 that the structure can have at most one non bit-field element
2682 and that this element must be the first one in the structure. */
2684 /* Find the first field, ignoring non FIELD_DECL things which will
2685 have been created by C++. */
2686 for (field
= TYPE_FIELDS (type
);
2687 field
&& TREE_CODE (field
) != FIELD_DECL
;
2688 field
= TREE_CHAIN (field
))
2692 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2694 /* Check that the first field is valid for returning in a register. */
2696 /* ... Floats are not allowed */
2697 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2700 /* ... Aggregates that are not themselves valid for returning in
2701 a register are not allowed. */
2702 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2705 /* Now check the remaining fields, if any. Only bitfields are allowed,
2706 since they are not addressable. */
2707 for (field
= TREE_CHAIN (field
);
2709 field
= TREE_CHAIN (field
))
2711 if (TREE_CODE (field
) != FIELD_DECL
)
2714 if (!DECL_BIT_FIELD_TYPE (field
))
2721 if (TREE_CODE (type
) == UNION_TYPE
)
2725 /* Unions can be returned in registers if every element is
2726 integral, or can be returned in an integer register. */
2727 for (field
= TYPE_FIELDS (type
);
2729 field
= TREE_CHAIN (field
))
2731 if (TREE_CODE (field
) != FIELD_DECL
)
2734 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2737 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2743 #endif /* not ARM_WINCE */
2745 /* Return all other types in memory. */
2749 /* Indicate whether or not words of a double are in big-endian order. */
2752 arm_float_words_big_endian (void)
2754 if (TARGET_MAVERICK
)
2757 /* For FPA, float words are always big-endian. For VFP, floats words
2758 follow the memory system mode. */
2766 return (TARGET_BIG_END
? 1 : 0);
2771 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2772 for a call to a function whose data type is FNTYPE.
2773 For a library call, FNTYPE is NULL. */
2775 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2776 rtx libname ATTRIBUTE_UNUSED
,
2777 tree fndecl ATTRIBUTE_UNUSED
)
2779 /* On the ARM, the offset starts at 0. */
2781 pcum
->iwmmxt_nregs
= 0;
2782 pcum
->can_split
= true;
2784 pcum
->call_cookie
= CALL_NORMAL
;
2786 if (TARGET_LONG_CALLS
)
2787 pcum
->call_cookie
= CALL_LONG
;
2789 /* Check for long call/short call attributes. The attributes
2790 override any command line option. */
2793 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2794 pcum
->call_cookie
= CALL_SHORT
;
2795 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2796 pcum
->call_cookie
= CALL_LONG
;
2799 /* Varargs vectors are treated the same as long long.
2800 named_count avoids having to change the way arm handles 'named' */
2801 pcum
->named_count
= 0;
2804 if (TARGET_REALLY_IWMMXT
&& fntype
)
2808 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2810 fn_arg
= TREE_CHAIN (fn_arg
))
2811 pcum
->named_count
+= 1;
2813 if (! pcum
->named_count
)
2814 pcum
->named_count
= INT_MAX
;
2819 /* Return true if mode/type need doubleword alignment. */
2821 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2823 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2824 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2828 /* Determine where to put an argument to a function.
2829 Value is zero to push the argument on the stack,
2830 or a hard register in which to store the argument.
2832 MODE is the argument's machine mode.
2833 TYPE is the data type of the argument (as a tree).
2834 This is null for libcalls where that information may
2836 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2837 the preceding args and about the function being called.
2838 NAMED is nonzero if this argument is a named parameter
2839 (otherwise it is an extra parameter matching an ellipsis). */
2842 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2843 tree type
, int named
)
2847 /* Varargs vectors are treated the same as long long.
2848 named_count avoids having to change the way arm handles 'named' */
2849 if (TARGET_IWMMXT_ABI
2850 && arm_vector_mode_supported_p (mode
)
2851 && pcum
->named_count
> pcum
->nargs
+ 1)
2853 if (pcum
->iwmmxt_nregs
<= 9)
2854 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2857 pcum
->can_split
= false;
2862 /* Put doubleword aligned quantities in even register pairs. */
2864 && ARM_DOUBLEWORD_ALIGN
2865 && arm_needs_doubleword_align (mode
, type
))
2868 if (mode
== VOIDmode
)
2869 /* Compute operand 2 of the call insn. */
2870 return GEN_INT (pcum
->call_cookie
);
2872 /* Only allow splitting an arg between regs and memory if all preceding
2873 args were allocated to regs. For args passed by reference we only count
2874 the reference pointer. */
2875 if (pcum
->can_split
)
2878 nregs
= ARM_NUM_REGS2 (mode
, type
);
2880 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2883 return gen_rtx_REG (mode
, pcum
->nregs
);
2887 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2888 tree type
, bool named ATTRIBUTE_UNUSED
)
2890 int nregs
= pcum
->nregs
;
2892 if (arm_vector_mode_supported_p (mode
))
2895 if (NUM_ARG_REGS
> nregs
2896 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
2898 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
2903 /* Variable sized types are passed by reference. This is a GCC
2904 extension to the ARM ABI. */
2907 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2908 enum machine_mode mode ATTRIBUTE_UNUSED
,
2909 tree type
, bool named ATTRIBUTE_UNUSED
)
2911 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2914 /* Encode the current state of the #pragma [no_]long_calls. */
2917 OFF
, /* No #pragma [no_]long_calls is in effect. */
2918 LONG
, /* #pragma long_calls is in effect. */
2919 SHORT
/* #pragma no_long_calls is in effect. */
2922 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2925 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2927 arm_pragma_long_calls
= LONG
;
2931 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2933 arm_pragma_long_calls
= SHORT
;
2937 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2939 arm_pragma_long_calls
= OFF
;
2942 /* Table of machine attributes. */
2943 const struct attribute_spec arm_attribute_table
[] =
2945 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2946 /* Function calls made to this symbol must be done indirectly, because
2947 it may lie outside of the 26 bit addressing range of a normal function
2949 { "long_call", 0, 0, false, true, true, NULL
},
2950 /* Whereas these functions are always known to reside within the 26 bit
2951 addressing range. */
2952 { "short_call", 0, 0, false, true, true, NULL
},
2953 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2954 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2955 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2956 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2958 /* ARM/PE has three new attributes:
2960 dllexport - for exporting a function/variable that will live in a dll
2961 dllimport - for importing a function/variable from a dll
2963 Microsoft allows multiple declspecs in one __declspec, separating
2964 them with spaces. We do NOT support this. Instead, use __declspec
2967 { "dllimport", 0, 0, true, false, false, NULL
},
2968 { "dllexport", 0, 0, true, false, false, NULL
},
2969 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2970 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2971 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2972 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2973 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
2975 { NULL
, 0, 0, false, false, false, NULL
}
2978 /* Handle an attribute requiring a FUNCTION_DECL;
2979 arguments as in struct attribute_spec.handler. */
2981 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2982 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2984 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2986 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
2987 IDENTIFIER_POINTER (name
));
2988 *no_add_attrs
= true;
2994 /* Handle an "interrupt" or "isr" attribute;
2995 arguments as in struct attribute_spec.handler. */
2997 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
3002 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3004 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
3005 IDENTIFIER_POINTER (name
));
3006 *no_add_attrs
= true;
3008 /* FIXME: the argument if any is checked for type attributes;
3009 should it be checked for decl ones? */
3013 if (TREE_CODE (*node
) == FUNCTION_TYPE
3014 || TREE_CODE (*node
) == METHOD_TYPE
)
3016 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
3018 warning (OPT_Wattributes
, "%qs attribute ignored",
3019 IDENTIFIER_POINTER (name
));
3020 *no_add_attrs
= true;
3023 else if (TREE_CODE (*node
) == POINTER_TYPE
3024 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
3025 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
3026 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
3028 *node
= build_variant_type_copy (*node
);
3029 TREE_TYPE (*node
) = build_type_attribute_variant
3031 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
3032 *no_add_attrs
= true;
3036 /* Possibly pass this attribute on from the type to a decl. */
3037 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
3038 | (int) ATTR_FLAG_FUNCTION_NEXT
3039 | (int) ATTR_FLAG_ARRAY_NEXT
))
3041 *no_add_attrs
= true;
3042 return tree_cons (name
, args
, NULL_TREE
);
3046 warning (OPT_Wattributes
, "%qs attribute ignored",
3047 IDENTIFIER_POINTER (name
));
3055 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3056 /* Handle the "notshared" attribute. This attribute is another way of
3057 requesting hidden visibility. ARM's compiler supports
3058 "__declspec(notshared)"; we support the same thing via an
3062 arm_handle_notshared_attribute (tree
*node
,
3063 tree name ATTRIBUTE_UNUSED
,
3064 tree args ATTRIBUTE_UNUSED
,
3065 int flags ATTRIBUTE_UNUSED
,
3068 tree decl
= TYPE_NAME (*node
);
3072 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
3073 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
3074 *no_add_attrs
= false;
3080 /* Return 0 if the attributes for two types are incompatible, 1 if they
3081 are compatible, and 2 if they are nearly compatible (which causes a
3082 warning to be generated). */
3084 arm_comp_type_attributes (tree type1
, tree type2
)
3088 /* Check for mismatch of non-default calling convention. */
3089 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
3092 /* Check for mismatched call attributes. */
3093 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
3094 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
3095 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
3096 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
3098 /* Only bother to check if an attribute is defined. */
3099 if (l1
| l2
| s1
| s2
)
3101 /* If one type has an attribute, the other must have the same attribute. */
3102 if ((l1
!= l2
) || (s1
!= s2
))
3105 /* Disallow mixed attributes. */
3106 if ((l1
& s2
) || (l2
& s1
))
3110 /* Check for mismatched ISR attribute. */
3111 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
3113 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
3114 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
3116 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
3123 /* Encode long_call or short_call attribute by prefixing
3124 symbol name in DECL with a special character FLAG. */
3126 arm_encode_call_attribute (tree decl
, int flag
)
3128 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
3129 int len
= strlen (str
);
3132 /* Do not allow weak functions to be treated as short call. */
3133 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
3136 newstr
= alloca (len
+ 2);
3138 strcpy (newstr
+ 1, str
);
3140 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
3141 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
3144 /* Assigns default attributes to newly defined type. This is used to
3145 set short_call/long_call attributes for function types of
3146 functions defined inside corresponding #pragma scopes. */
3148 arm_set_default_type_attributes (tree type
)
3150 /* Add __attribute__ ((long_call)) to all functions, when
3151 inside #pragma long_calls or __attribute__ ((short_call)),
3152 when inside #pragma no_long_calls. */
3153 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
3155 tree type_attr_list
, attr_name
;
3156 type_attr_list
= TYPE_ATTRIBUTES (type
);
3158 if (arm_pragma_long_calls
== LONG
)
3159 attr_name
= get_identifier ("long_call");
3160 else if (arm_pragma_long_calls
== SHORT
)
3161 attr_name
= get_identifier ("short_call");
3165 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
3166 TYPE_ATTRIBUTES (type
) = type_attr_list
;
3170 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3171 defined within the current compilation unit. If this cannot be
3172 determined, then 0 is returned. */
3174 current_file_function_operand (rtx sym_ref
)
3176 /* This is a bit of a fib. A function will have a short call flag
3177 applied to its name if it has the short call attribute, or it has
3178 already been defined within the current compilation unit. */
3179 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
3182 /* The current function is always defined within the current compilation
3183 unit. If it s a weak definition however, then this may not be the real
3184 definition of the function, and so we have to say no. */
3185 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
3186 && !DECL_WEAK (current_function_decl
))
3189 /* We cannot make the determination - default to returning 0. */
3193 /* Return nonzero if a 32-bit "long_call" should be generated for
3194 this call. We generate a long_call if the function:
3196 a. has an __attribute__((long call))
3197 or b. is within the scope of a #pragma long_calls
3198 or c. the -mlong-calls command line switch has been specified
3200 1. -ffunction-sections is in effect
3201 or 2. the current function has __attribute__ ((section))
3202 or 3. the target function has __attribute__ ((section))
3204 However we do not generate a long call if the function:
3206 d. has an __attribute__ ((short_call))
3207 or e. is inside the scope of a #pragma no_long_calls
3208 or f. is defined within the current compilation unit.
3210 This function will be called by C fragments contained in the machine
3211 description file. SYM_REF and CALL_COOKIE correspond to the matched
3212 rtl operands. CALL_SYMBOL is used to distinguish between
3213 two different callers of the function. It is set to 1 in the
3214 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3215 and "call_value" patterns. This is because of the difference in the
3216 SYM_REFs passed by these patterns. */
3218 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
3222 if (GET_CODE (sym_ref
) != MEM
)
3225 sym_ref
= XEXP (sym_ref
, 0);
3228 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
3231 if (call_cookie
& CALL_SHORT
)
3234 if (TARGET_LONG_CALLS
)
3236 if (flag_function_sections
3237 || DECL_SECTION_NAME (current_function_decl
))
3238 /* c.3 is handled by the definition of the
3239 ARM_DECLARE_FUNCTION_SIZE macro. */
3243 if (current_file_function_operand (sym_ref
))
3246 return (call_cookie
& CALL_LONG
)
3247 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
3248 || TARGET_LONG_CALLS
;
3251 /* Return nonzero if it is ok to make a tail-call to DECL. */
3253 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3255 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
3256 unsigned long func_type
;
3258 if (cfun
->machine
->sibcall_blocked
)
3261 /* Never tailcall something for which we have no decl, or if we
3262 are in Thumb mode. */
3263 if (decl
== NULL
|| TARGET_THUMB
)
3266 /* Get the calling method. */
3267 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3268 call_type
= CALL_SHORT
;
3269 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
3270 call_type
= CALL_LONG
;
3272 /* Cannot tail-call to long calls, since these are out of range of
3273 a branch instruction. However, if not compiling PIC, we know
3274 we can reach the symbol if it is in this compilation unit. */
3275 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
3278 /* If we are interworking and the function is not declared static
3279 then we can't tail-call it unless we know that it exists in this
3280 compilation unit (since it might be a Thumb routine). */
3281 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
3284 func_type
= arm_current_func_type ();
3285 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3286 if (IS_INTERRUPT (func_type
))
3289 /* Never tailcall if function may be called with a misaligned SP. */
3290 if (IS_STACKALIGN (func_type
))
3293 /* Everything else is ok. */
3298 /* Addressing mode support functions. */
3300 /* Return nonzero if X is a legitimate immediate operand when compiling
3301 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3303 legitimate_pic_operand_p (rtx x
)
3305 if (GET_CODE (x
) == SYMBOL_REF
3306 || (GET_CODE (x
) == CONST
3307 && GET_CODE (XEXP (x
, 0)) == PLUS
3308 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3315 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
3317 if (GET_CODE (orig
) == SYMBOL_REF
3318 || GET_CODE (orig
) == LABEL_REF
)
3320 #ifndef AOF_ASSEMBLER
3321 rtx pic_ref
, address
;
3326 /* If this function doesn't have a pic register, create one now.
3327 A lot of the logic here is made obscure by the fact that this
3328 routine gets called as part of the rtx cost estimation
3329 process. We don't want those calls to affect any assumptions
3330 about the real function; and further, we can't call
3331 entry_of_function() until we start the real expansion
3333 if (!current_function_uses_pic_offset_table
)
3335 gcc_assert (!no_new_pseudos
);
3336 if (arm_pic_register
!= INVALID_REGNUM
)
3338 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
3340 /* Play games to avoid marking the function as needing pic
3341 if we are being called as part of the cost-estimation
3343 if (current_ir_type () != IR_GIMPLE
)
3344 current_function_uses_pic_offset_table
= 1;
3350 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
3352 /* Play games to avoid marking the function as needing pic
3353 if we are being called as part of the cost-estimation
3355 if (current_ir_type () != IR_GIMPLE
)
3357 current_function_uses_pic_offset_table
= 1;
3360 arm_load_pic_register (0UL);
3364 emit_insn_after (seq
, entry_of_function ());
3371 gcc_assert (!no_new_pseudos
);
3372 reg
= gen_reg_rtx (Pmode
);
3377 #ifdef AOF_ASSEMBLER
3378 /* The AOF assembler can generate relocations for these directly, and
3379 understands that the PIC register has to be added into the offset. */
3380 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
3383 address
= gen_reg_rtx (Pmode
);
3388 emit_insn (gen_pic_load_addr_arm (address
, orig
));
3389 else if (TARGET_THUMB2
)
3390 emit_insn (gen_pic_load_addr_thumb2 (address
, orig
));
3391 else /* TARGET_THUMB1 */
3392 emit_insn (gen_pic_load_addr_thumb1 (address
, orig
));
3394 if ((GET_CODE (orig
) == LABEL_REF
3395 || (GET_CODE (orig
) == SYMBOL_REF
&&
3396 SYMBOL_REF_LOCAL_P (orig
)))
3398 pic_ref
= gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
, address
);
3401 pic_ref
= gen_const_mem (Pmode
,
3402 gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
,
3406 insn
= emit_move_insn (reg
, pic_ref
);
3408 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3410 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3414 else if (GET_CODE (orig
) == CONST
)
3418 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3419 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
3422 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
3423 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
3428 gcc_assert (!no_new_pseudos
);
3429 reg
= gen_reg_rtx (Pmode
);
3432 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3434 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3435 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3436 base
== reg
? 0 : reg
);
3438 if (GET_CODE (offset
) == CONST_INT
)
3440 /* The base register doesn't really matter, we only want to
3441 test the index for the appropriate mode. */
3442 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
3444 gcc_assert (!no_new_pseudos
);
3445 offset
= force_reg (Pmode
, offset
);
3448 if (GET_CODE (offset
) == CONST_INT
)
3449 return plus_constant (base
, INTVAL (offset
));
3452 if (GET_MODE_SIZE (mode
) > 4
3453 && (GET_MODE_CLASS (mode
) == MODE_INT
3454 || TARGET_SOFT_FLOAT
))
3456 emit_insn (gen_addsi3 (reg
, base
, offset
));
3460 return gen_rtx_PLUS (Pmode
, base
, offset
);
3467 /* Find a spare register to use during the prolog of a function. */
3470 thumb_find_work_register (unsigned long pushed_regs_mask
)
3474 /* Check the argument registers first as these are call-used. The
3475 register allocation order means that sometimes r3 might be used
3476 but earlier argument registers might not, so check them all. */
3477 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
3478 if (!regs_ever_live
[reg
])
3481 /* Before going on to check the call-saved registers we can try a couple
3482 more ways of deducing that r3 is available. The first is when we are
3483 pushing anonymous arguments onto the stack and we have less than 4
3484 registers worth of fixed arguments(*). In this case r3 will be part of
3485 the variable argument list and so we can be sure that it will be
3486 pushed right at the start of the function. Hence it will be available
3487 for the rest of the prologue.
3488 (*): ie current_function_pretend_args_size is greater than 0. */
3489 if (cfun
->machine
->uses_anonymous_args
3490 && current_function_pretend_args_size
> 0)
3491 return LAST_ARG_REGNUM
;
3493 /* The other case is when we have fixed arguments but less than 4 registers
3494 worth. In this case r3 might be used in the body of the function, but
3495 it is not being used to convey an argument into the function. In theory
3496 we could just check current_function_args_size to see how many bytes are
3497 being passed in argument registers, but it seems that it is unreliable.
3498 Sometimes it will have the value 0 when in fact arguments are being
3499 passed. (See testcase execute/20021111-1.c for an example). So we also
3500 check the args_info.nregs field as well. The problem with this field is
3501 that it makes no allowances for arguments that are passed to the
3502 function but which are not used. Hence we could miss an opportunity
3503 when a function has an unused argument in r3. But it is better to be
3504 safe than to be sorry. */
3505 if (! cfun
->machine
->uses_anonymous_args
3506 && current_function_args_size
>= 0
3507 && current_function_args_size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
3508 && cfun
->args_info
.nregs
< 4)
3509 return LAST_ARG_REGNUM
;
3511 /* Otherwise look for a call-saved register that is going to be pushed. */
3512 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
3513 if (pushed_regs_mask
& (1 << reg
))
3518 /* Thumb-2 can use high regs. */
3519 for (reg
= FIRST_HI_REGNUM
; reg
< 15; reg
++)
3520 if (pushed_regs_mask
& (1 << reg
))
3523 /* Something went wrong - thumb_compute_save_reg_mask()
3524 should have arranged for a suitable register to be pushed. */
3528 static GTY(()) int pic_labelno
;
3530 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3534 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
3536 #ifndef AOF_ASSEMBLER
3537 rtx l1
, labelno
, pic_tmp
, pic_tmp2
, pic_rtx
;
3538 rtx global_offset_table
;
3540 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3543 gcc_assert (flag_pic
);
3545 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3546 in the code stream. */
3548 labelno
= GEN_INT (pic_labelno
++);
3549 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
3550 l1
= gen_rtx_CONST (VOIDmode
, l1
);
3552 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3553 /* On the ARM the PC register contains 'dot + 8' at the time of the
3554 addition, on the Thumb it is 'dot + 4'. */
3555 pic_tmp
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
3557 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3558 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3560 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3562 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3566 emit_insn (gen_pic_load_addr_arm (cfun
->machine
->pic_reg
, pic_rtx
));
3567 emit_insn (gen_pic_add_dot_plus_eight (cfun
->machine
->pic_reg
,
3568 cfun
->machine
->pic_reg
, labelno
));
3570 else if (TARGET_THUMB2
)
3572 /* Thumb-2 only allows very limited access to the PC. Calculate the
3573 address in a temporary register. */
3574 if (arm_pic_register
!= INVALID_REGNUM
)
3576 pic_tmp
= gen_rtx_REG (SImode
,
3577 thumb_find_work_register (saved_regs
));
3581 gcc_assert (!no_new_pseudos
);
3582 pic_tmp
= gen_reg_rtx (Pmode
);
3585 emit_insn (gen_pic_load_addr_thumb2 (cfun
->machine
->pic_reg
, pic_rtx
));
3586 emit_insn (gen_pic_load_dot_plus_four (pic_tmp
, labelno
));
3587 emit_insn (gen_addsi3(cfun
->machine
->pic_reg
, cfun
->machine
->pic_reg
,
3590 else /* TARGET_THUMB1 */
3592 if (arm_pic_register
!= INVALID_REGNUM
3593 && REGNO (cfun
->machine
->pic_reg
) > LAST_LO_REGNUM
)
3595 /* We will have pushed the pic register, so we should always be
3596 able to find a work register. */
3597 pic_tmp
= gen_rtx_REG (SImode
,
3598 thumb_find_work_register (saved_regs
));
3599 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp
, pic_rtx
));
3600 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
3603 emit_insn (gen_pic_load_addr_thumb1 (cfun
->machine
->pic_reg
, pic_rtx
));
3604 emit_insn (gen_pic_add_dot_plus_four (cfun
->machine
->pic_reg
,
3605 cfun
->machine
->pic_reg
, labelno
));
3608 /* Need to emit this whether or not we obey regdecls,
3609 since setjmp/longjmp can cause life info to screw up. */
3610 emit_insn (gen_rtx_USE (VOIDmode
, cfun
->machine
->pic_reg
));
3611 #endif /* AOF_ASSEMBLER */
3615 /* Return nonzero if X is valid as an ARM state addressing register. */
3617 arm_address_register_rtx_p (rtx x
, int strict_p
)
3621 if (GET_CODE (x
) != REG
)
3627 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3629 return (regno
<= LAST_ARM_REGNUM
3630 || regno
>= FIRST_PSEUDO_REGISTER
3631 || regno
== FRAME_POINTER_REGNUM
3632 || regno
== ARG_POINTER_REGNUM
);
3635 /* Return TRUE if this rtx is the difference of a symbol and a label,
3636 and will reduce to a PC-relative relocation in the object file.
3637 Expressions like this can be left alone when generating PIC, rather
3638 than forced through the GOT. */
3640 pcrel_constant_p (rtx x
)
3642 if (GET_CODE (x
) == MINUS
)
3643 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
3648 /* Return nonzero if X is a valid ARM state address operand. */
3650 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3654 enum rtx_code code
= GET_CODE (x
);
3656 if (arm_address_register_rtx_p (x
, strict_p
))
3659 use_ldrd
= (TARGET_LDRD
3661 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3663 if (code
== POST_INC
|| code
== PRE_DEC
3664 || ((code
== PRE_INC
|| code
== POST_DEC
)
3665 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3666 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3668 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3669 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3670 && GET_CODE (XEXP (x
, 1)) == PLUS
3671 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3673 rtx addend
= XEXP (XEXP (x
, 1), 1);
3675 /* Don't allow ldrd post increment by register because it's hard
3676 to fixup invalid register choices. */
3678 && GET_CODE (x
) == POST_MODIFY
3679 && GET_CODE (addend
) == REG
)
3682 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3683 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3686 /* After reload constants split into minipools will have addresses
3687 from a LABEL_REF. */
3688 else if (reload_completed
3689 && (code
== LABEL_REF
3691 && GET_CODE (XEXP (x
, 0)) == PLUS
3692 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3693 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3696 else if (mode
== TImode
)
3699 else if (code
== PLUS
)
3701 rtx xop0
= XEXP (x
, 0);
3702 rtx xop1
= XEXP (x
, 1);
3704 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3705 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3706 || (arm_address_register_rtx_p (xop1
, strict_p
)
3707 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3711 /* Reload currently can't handle MINUS, so disable this for now */
3712 else if (GET_CODE (x
) == MINUS
)
3714 rtx xop0
= XEXP (x
, 0);
3715 rtx xop1
= XEXP (x
, 1);
3717 return (arm_address_register_rtx_p (xop0
, strict_p
)
3718 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3722 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3723 && code
== SYMBOL_REF
3724 && CONSTANT_POOL_ADDRESS_P (x
)
3726 && symbol_mentioned_p (get_pool_constant (x
))
3727 && ! pcrel_constant_p (get_pool_constant (x
))))
3733 /* Return nonzero if X is a valid Thumb-2 address operand. */
3735 thumb2_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3738 enum rtx_code code
= GET_CODE (x
);
3740 if (arm_address_register_rtx_p (x
, strict_p
))
3743 use_ldrd
= (TARGET_LDRD
3745 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3747 if (code
== POST_INC
|| code
== PRE_DEC
3748 || ((code
== PRE_INC
|| code
== POST_DEC
)
3749 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3750 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3752 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3753 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3754 && GET_CODE (XEXP (x
, 1)) == PLUS
3755 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3757 /* Thumb-2 only has autoincrement by constant. */
3758 rtx addend
= XEXP (XEXP (x
, 1), 1);
3759 HOST_WIDE_INT offset
;
3761 if (GET_CODE (addend
) != CONST_INT
)
3764 offset
= INTVAL(addend
);
3765 if (GET_MODE_SIZE (mode
) <= 4)
3766 return (offset
> -256 && offset
< 256);
3768 return (use_ldrd
&& offset
> -1024 && offset
< 1024
3769 && (offset
& 3) == 0);
3772 /* After reload constants split into minipools will have addresses
3773 from a LABEL_REF. */
3774 else if (reload_completed
3775 && (code
== LABEL_REF
3777 && GET_CODE (XEXP (x
, 0)) == PLUS
3778 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3779 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3782 else if (mode
== TImode
)
3785 else if (code
== PLUS
)
3787 rtx xop0
= XEXP (x
, 0);
3788 rtx xop1
= XEXP (x
, 1);
3790 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3791 && thumb2_legitimate_index_p (mode
, xop1
, strict_p
))
3792 || (arm_address_register_rtx_p (xop1
, strict_p
)
3793 && thumb2_legitimate_index_p (mode
, xop0
, strict_p
)));
3796 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3797 && code
== SYMBOL_REF
3798 && CONSTANT_POOL_ADDRESS_P (x
)
3800 && symbol_mentioned_p (get_pool_constant (x
))
3801 && ! pcrel_constant_p (get_pool_constant (x
))))
3807 /* Return nonzero if INDEX is valid for an address index operand in
3810 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3813 HOST_WIDE_INT range
;
3814 enum rtx_code code
= GET_CODE (index
);
3816 /* Standard coprocessor addressing modes. */
3817 if (TARGET_HARD_FLOAT
3818 && (TARGET_FPA
|| TARGET_MAVERICK
)
3819 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3820 || (TARGET_MAVERICK
&& mode
== DImode
)))
3821 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3822 && INTVAL (index
) > -1024
3823 && (INTVAL (index
) & 3) == 0);
3825 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3826 return (code
== CONST_INT
3827 && INTVAL (index
) < 1024
3828 && INTVAL (index
) > -1024
3829 && (INTVAL (index
) & 3) == 0);
3831 if (arm_address_register_rtx_p (index
, strict_p
)
3832 && (GET_MODE_SIZE (mode
) <= 4))
3835 if (mode
== DImode
|| mode
== DFmode
)
3837 if (code
== CONST_INT
)
3839 HOST_WIDE_INT val
= INTVAL (index
);
3842 return val
> -256 && val
< 256;
3844 return val
> -4096 && val
< 4092;
3847 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3850 if (GET_MODE_SIZE (mode
) <= 4
3853 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3857 rtx xiop0
= XEXP (index
, 0);
3858 rtx xiop1
= XEXP (index
, 1);
3860 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3861 && power_of_two_operand (xiop1
, SImode
))
3862 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3863 && power_of_two_operand (xiop0
, SImode
)));
3865 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3866 || code
== ASHIFT
|| code
== ROTATERT
)
3868 rtx op
= XEXP (index
, 1);
3870 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3871 && GET_CODE (op
) == CONST_INT
3873 && INTVAL (op
) <= 31);
3877 /* For ARM v4 we may be doing a sign-extend operation during the
3881 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3887 range
= (mode
== HImode
) ? 4095 : 4096;
3889 return (code
== CONST_INT
3890 && INTVAL (index
) < range
3891 && INTVAL (index
) > -range
);
3894 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3895 index operand. i.e. 1, 2, 4 or 8. */
3897 thumb2_index_mul_operand (rtx op
)
3901 if (GET_CODE(op
) != CONST_INT
)
3905 return (val
== 1 || val
== 2 || val
== 4 || val
== 8);
3908 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
3910 thumb2_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
3912 enum rtx_code code
= GET_CODE (index
);
3914 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
3915 /* Standard coprocessor addressing modes. */
3916 if (TARGET_HARD_FLOAT
3917 && (TARGET_FPA
|| TARGET_MAVERICK
)
3918 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3919 || (TARGET_MAVERICK
&& mode
== DImode
)))
3920 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3921 && INTVAL (index
) > -1024
3922 && (INTVAL (index
) & 3) == 0);
3924 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3926 /* For DImode assume values will usually live in core regs
3927 and only allow LDRD addressing modes. */
3928 if (!TARGET_LDRD
|| mode
!= DImode
)
3929 return (code
== CONST_INT
3930 && INTVAL (index
) < 1024
3931 && INTVAL (index
) > -1024
3932 && (INTVAL (index
) & 3) == 0);
3935 if (arm_address_register_rtx_p (index
, strict_p
)
3936 && (GET_MODE_SIZE (mode
) <= 4))
3939 if (mode
== DImode
|| mode
== DFmode
)
3941 HOST_WIDE_INT val
= INTVAL (index
);
3942 /* ??? Can we assume ldrd for thumb2? */
3943 /* Thumb-2 ldrd only has reg+const addressing modes. */
3944 if (code
!= CONST_INT
)
3947 /* ldrd supports offsets of +-1020.
3948 However the ldr fallback does not. */
3949 return val
> -256 && val
< 256 && (val
& 3) == 0;
3954 rtx xiop0
= XEXP (index
, 0);
3955 rtx xiop1
= XEXP (index
, 1);
3957 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3958 && thumb2_index_mul_operand (xiop1
))
3959 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3960 && thumb2_index_mul_operand (xiop0
)));
3962 else if (code
== ASHIFT
)
3964 rtx op
= XEXP (index
, 1);
3966 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3967 && GET_CODE (op
) == CONST_INT
3969 && INTVAL (op
) <= 3);
3972 return (code
== CONST_INT
3973 && INTVAL (index
) < 4096
3974 && INTVAL (index
) > -256);
3977 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
3979 thumb1_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3983 if (GET_CODE (x
) != REG
)
3989 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3991 return (regno
<= LAST_LO_REGNUM
3992 || regno
> LAST_VIRTUAL_REGISTER
3993 || regno
== FRAME_POINTER_REGNUM
3994 || (GET_MODE_SIZE (mode
) >= 4
3995 && (regno
== STACK_POINTER_REGNUM
3996 || regno
>= FIRST_PSEUDO_REGISTER
3997 || x
== hard_frame_pointer_rtx
3998 || x
== arg_pointer_rtx
)));
4001 /* Return nonzero if x is a legitimate index register. This is the case
4002 for any base register that can access a QImode object. */
4004 thumb1_index_register_rtx_p (rtx x
, int strict_p
)
4006 return thumb1_base_register_rtx_p (x
, QImode
, strict_p
);
4009 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4011 The AP may be eliminated to either the SP or the FP, so we use the
4012 least common denominator, e.g. SImode, and offsets from 0 to 64.
4014 ??? Verify whether the above is the right approach.
4016 ??? Also, the FP may be eliminated to the SP, so perhaps that
4017 needs special handling also.
4019 ??? Look at how the mips16 port solves this problem. It probably uses
4020 better ways to solve some of these problems.
4022 Although it is not incorrect, we don't accept QImode and HImode
4023 addresses based on the frame pointer or arg pointer until the
4024 reload pass starts. This is so that eliminating such addresses
4025 into stack based ones won't produce impossible code. */
4027 thumb1_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
4029 /* ??? Not clear if this is right. Experiment. */
4030 if (GET_MODE_SIZE (mode
) < 4
4031 && !(reload_in_progress
|| reload_completed
)
4032 && (reg_mentioned_p (frame_pointer_rtx
, x
)
4033 || reg_mentioned_p (arg_pointer_rtx
, x
)
4034 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
4035 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
4036 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
4037 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
4040 /* Accept any base register. SP only in SImode or larger. */
4041 else if (thumb1_base_register_rtx_p (x
, mode
, strict_p
))
4044 /* This is PC relative data before arm_reorg runs. */
4045 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
4046 && GET_CODE (x
) == SYMBOL_REF
4047 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
4050 /* This is PC relative data after arm_reorg runs. */
4051 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
4052 && (GET_CODE (x
) == LABEL_REF
4053 || (GET_CODE (x
) == CONST
4054 && GET_CODE (XEXP (x
, 0)) == PLUS
4055 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
4056 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
4059 /* Post-inc indexing only supported for SImode and larger. */
4060 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
4061 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
))
4064 else if (GET_CODE (x
) == PLUS
)
4066 /* REG+REG address can be any two index registers. */
4067 /* We disallow FRAME+REG addressing since we know that FRAME
4068 will be replaced with STACK, and SP relative addressing only
4069 permits SP+OFFSET. */
4070 if (GET_MODE_SIZE (mode
) <= 4
4071 && XEXP (x
, 0) != frame_pointer_rtx
4072 && XEXP (x
, 1) != frame_pointer_rtx
4073 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
4074 && thumb1_index_register_rtx_p (XEXP (x
, 1), strict_p
))
4077 /* REG+const has 5-7 bit offset for non-SP registers. */
4078 else if ((thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
4079 || XEXP (x
, 0) == arg_pointer_rtx
)
4080 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4081 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4084 /* REG+const has 10-bit offset for SP, but only SImode and
4085 larger is supported. */
4086 /* ??? Should probably check for DI/DFmode overflow here
4087 just like GO_IF_LEGITIMATE_OFFSET does. */
4088 else if (GET_CODE (XEXP (x
, 0)) == REG
4089 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
4090 && GET_MODE_SIZE (mode
) >= 4
4091 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4092 && INTVAL (XEXP (x
, 1)) >= 0
4093 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
4094 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
4097 else if (GET_CODE (XEXP (x
, 0)) == REG
4098 && (REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
4099 || REGNO (XEXP (x
, 0)) == ARG_POINTER_REGNUM
4100 || (REGNO (XEXP (x
, 0)) >= FIRST_VIRTUAL_REGISTER
4101 && REGNO (XEXP (x
, 0)) <= LAST_VIRTUAL_REGISTER
))
4102 && GET_MODE_SIZE (mode
) >= 4
4103 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4104 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
4108 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
4109 && GET_MODE_SIZE (mode
) == 4
4110 && GET_CODE (x
) == SYMBOL_REF
4111 && CONSTANT_POOL_ADDRESS_P (x
)
4113 && symbol_mentioned_p (get_pool_constant (x
))
4114 && ! pcrel_constant_p (get_pool_constant (x
))))
4120 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4121 instruction of mode MODE. */
4123 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
4125 switch (GET_MODE_SIZE (mode
))
4128 return val
>= 0 && val
< 32;
4131 return val
>= 0 && val
< 64 && (val
& 1) == 0;
4135 && (val
+ GET_MODE_SIZE (mode
)) <= 128
4140 /* Build the SYMBOL_REF for __tls_get_addr. */
4142 static GTY(()) rtx tls_get_addr_libfunc
;
4145 get_tls_get_addr (void)
4147 if (!tls_get_addr_libfunc
)
4148 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
4149 return tls_get_addr_libfunc
;
4153 arm_load_tp (rtx target
)
4156 target
= gen_reg_rtx (SImode
);
4160 /* Can return in any reg. */
4161 emit_insn (gen_load_tp_hard (target
));
4165 /* Always returned in r0. Immediately copy the result into a pseudo,
4166 otherwise other uses of r0 (e.g. setting up function arguments) may
4167 clobber the value. */
4171 emit_insn (gen_load_tp_soft ());
4173 tmp
= gen_rtx_REG (SImode
, 0);
4174 emit_move_insn (target
, tmp
);
4180 load_tls_operand (rtx x
, rtx reg
)
4184 if (reg
== NULL_RTX
)
4185 reg
= gen_reg_rtx (SImode
);
4187 tmp
= gen_rtx_CONST (SImode
, x
);
4189 emit_move_insn (reg
, tmp
);
4195 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
4197 rtx insns
, label
, labelno
, sum
;
4201 labelno
= GEN_INT (pic_labelno
++);
4202 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
4203 label
= gen_rtx_CONST (VOIDmode
, label
);
4205 sum
= gen_rtx_UNSPEC (Pmode
,
4206 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
4207 GEN_INT (TARGET_ARM
? 8 : 4)),
4209 reg
= load_tls_operand (sum
, reg
);
4212 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
4213 else if (TARGET_THUMB2
)
4216 /* Thumb-2 only allows very limited access to the PC. Calculate
4217 the address in a temporary register. */
4218 tmp
= gen_reg_rtx (SImode
);
4219 emit_insn (gen_pic_load_dot_plus_four (tmp
, labelno
));
4220 emit_insn (gen_addsi3(reg
, reg
, tmp
));
4222 else /* TARGET_THUMB1 */
4223 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
4225 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
4226 Pmode
, 1, reg
, Pmode
);
4228 insns
= get_insns ();
4235 legitimize_tls_address (rtx x
, rtx reg
)
4237 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
4238 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
4242 case TLS_MODEL_GLOBAL_DYNAMIC
:
4243 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
4244 dest
= gen_reg_rtx (Pmode
);
4245 emit_libcall_block (insns
, dest
, ret
, x
);
4248 case TLS_MODEL_LOCAL_DYNAMIC
:
4249 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
4251 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4252 share the LDM result with other LD model accesses. */
4253 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
4255 dest
= gen_reg_rtx (Pmode
);
4256 emit_libcall_block (insns
, dest
, ret
, eqv
);
4258 /* Load the addend. */
4259 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
4261 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
4262 return gen_rtx_PLUS (Pmode
, dest
, addend
);
4264 case TLS_MODEL_INITIAL_EXEC
:
4265 labelno
= GEN_INT (pic_labelno
++);
4266 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
4267 label
= gen_rtx_CONST (VOIDmode
, label
);
4268 sum
= gen_rtx_UNSPEC (Pmode
,
4269 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
4270 GEN_INT (TARGET_ARM
? 8 : 4)),
4272 reg
= load_tls_operand (sum
, reg
);
4275 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
4276 else if (TARGET_THUMB2
)
4279 /* Thumb-2 only allows very limited access to the PC. Calculate
4280 the address in a temporary register. */
4281 tmp
= gen_reg_rtx (SImode
);
4282 emit_insn (gen_pic_load_dot_plus_four (tmp
, labelno
));
4283 emit_insn (gen_addsi3(reg
, reg
, tmp
));
4284 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
4288 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
4289 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
4292 tp
= arm_load_tp (NULL_RTX
);
4294 return gen_rtx_PLUS (Pmode
, tp
, reg
);
4296 case TLS_MODEL_LOCAL_EXEC
:
4297 tp
= arm_load_tp (NULL_RTX
);
4299 reg
= gen_rtx_UNSPEC (Pmode
,
4300 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
4302 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
4304 return gen_rtx_PLUS (Pmode
, tp
, reg
);
4311 /* Try machine-dependent ways of modifying an illegitimate address
4312 to be legitimate. If we find one, return the new, valid address. */
4314 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4316 if (arm_tls_symbol_p (x
))
4317 return legitimize_tls_address (x
, NULL_RTX
);
4319 if (GET_CODE (x
) == PLUS
)
4321 rtx xop0
= XEXP (x
, 0);
4322 rtx xop1
= XEXP (x
, 1);
4324 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
4325 xop0
= force_reg (SImode
, xop0
);
4327 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
4328 xop1
= force_reg (SImode
, xop1
);
4330 if (ARM_BASE_REGISTER_RTX_P (xop0
)
4331 && GET_CODE (xop1
) == CONST_INT
)
4333 HOST_WIDE_INT n
, low_n
;
4337 /* VFP addressing modes actually allow greater offsets, but for
4338 now we just stick with the lowest common denominator. */
4340 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
4352 low_n
= ((mode
) == TImode
? 0
4353 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
4357 base_reg
= gen_reg_rtx (SImode
);
4358 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
4359 emit_move_insn (base_reg
, val
);
4360 x
= plus_constant (base_reg
, low_n
);
4362 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4363 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4366 /* XXX We don't allow MINUS any more -- see comment in
4367 arm_legitimate_address_p (). */
4368 else if (GET_CODE (x
) == MINUS
)
4370 rtx xop0
= XEXP (x
, 0);
4371 rtx xop1
= XEXP (x
, 1);
4373 if (CONSTANT_P (xop0
))
4374 xop0
= force_reg (SImode
, xop0
);
4376 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
4377 xop1
= force_reg (SImode
, xop1
);
4379 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
4380 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
4383 /* Make sure to take full advantage of the pre-indexed addressing mode
4384 with absolute addresses which often allows for the base register to
4385 be factorized for multiple adjacent memory references, and it might
4386 even allows for the mini pool to be avoided entirely. */
4387 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
4390 HOST_WIDE_INT mask
, base
, index
;
4393 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4394 use a 8-bit index. So let's use a 12-bit index for SImode only and
4395 hope that arm_gen_constant will enable ldrb to use more bits. */
4396 bits
= (mode
== SImode
) ? 12 : 8;
4397 mask
= (1 << bits
) - 1;
4398 base
= INTVAL (x
) & ~mask
;
4399 index
= INTVAL (x
) & mask
;
4400 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
4402 /* It'll most probably be more efficient to generate the base
4403 with more bits set and use a negative index instead. */
4407 base_reg
= force_reg (SImode
, GEN_INT (base
));
4408 x
= plus_constant (base_reg
, index
);
4413 /* We need to find and carefully transform any SYMBOL and LABEL
4414 references; so go back to the original address expression. */
4415 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4417 if (new_x
!= orig_x
)
4425 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4426 to be legitimate. If we find one, return the new, valid address. */
4428 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
4430 if (arm_tls_symbol_p (x
))
4431 return legitimize_tls_address (x
, NULL_RTX
);
4433 if (GET_CODE (x
) == PLUS
4434 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4435 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
4436 || INTVAL (XEXP (x
, 1)) < 0))
4438 rtx xop0
= XEXP (x
, 0);
4439 rtx xop1
= XEXP (x
, 1);
4440 HOST_WIDE_INT offset
= INTVAL (xop1
);
4442 /* Try and fold the offset into a biasing of the base register and
4443 then offsetting that. Don't do this when optimizing for space
4444 since it can cause too many CSEs. */
4445 if (optimize_size
&& offset
>= 0
4446 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
4448 HOST_WIDE_INT delta
;
4451 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
4452 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
4453 delta
= 31 * GET_MODE_SIZE (mode
);
4455 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
4457 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
4459 x
= plus_constant (xop0
, delta
);
4461 else if (offset
< 0 && offset
> -256)
4462 /* Small negative offsets are best done with a subtract before the
4463 dereference, forcing these into a register normally takes two
4465 x
= force_operand (x
, NULL_RTX
);
4468 /* For the remaining cases, force the constant into a register. */
4469 xop1
= force_reg (SImode
, xop1
);
4470 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
4473 else if (GET_CODE (x
) == PLUS
4474 && s_register_operand (XEXP (x
, 1), SImode
)
4475 && !s_register_operand (XEXP (x
, 0), SImode
))
4477 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
4479 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
4484 /* We need to find and carefully transform any SYMBOL and LABEL
4485 references; so go back to the original address expression. */
4486 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
4488 if (new_x
!= orig_x
)
4496 thumb_legitimize_reload_address (rtx
*x_p
,
4497 enum machine_mode mode
,
4498 int opnum
, int type
,
4499 int ind_levels ATTRIBUTE_UNUSED
)
4503 if (GET_CODE (x
) == PLUS
4504 && GET_MODE_SIZE (mode
) < 4
4505 && REG_P (XEXP (x
, 0))
4506 && XEXP (x
, 0) == stack_pointer_rtx
4507 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4508 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
4513 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4514 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4518 /* If both registers are hi-regs, then it's better to reload the
4519 entire expression rather than each register individually. That
4520 only requires one reload register rather than two. */
4521 if (GET_CODE (x
) == PLUS
4522 && REG_P (XEXP (x
, 0))
4523 && REG_P (XEXP (x
, 1))
4524 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
4525 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
4530 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
4531 Pmode
, VOIDmode
, 0, 0, opnum
, type
);
4538 /* Test for various thread-local symbols. */
4540 /* Return TRUE if X is a thread-local symbol. */
4543 arm_tls_symbol_p (rtx x
)
4545 if (! TARGET_HAVE_TLS
)
4548 if (GET_CODE (x
) != SYMBOL_REF
)
4551 return SYMBOL_REF_TLS_MODEL (x
) != 0;
4554 /* Helper for arm_tls_referenced_p. */
4557 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
4559 if (GET_CODE (*x
) == SYMBOL_REF
)
4560 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
4562 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4563 TLS offsets, not real symbol references. */
4564 if (GET_CODE (*x
) == UNSPEC
4565 && XINT (*x
, 1) == UNSPEC_TLS
)
4571 /* Return TRUE if X contains any TLS symbol references. */
4574 arm_tls_referenced_p (rtx x
)
4576 if (! TARGET_HAVE_TLS
)
4579 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
4582 #define REG_OR_SUBREG_REG(X) \
4583 (GET_CODE (X) == REG \
4584 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4586 #define REG_OR_SUBREG_RTX(X) \
4587 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4589 #ifndef COSTS_N_INSNS
4590 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4593 thumb1_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4595 enum machine_mode mode
= GET_MODE (x
);
4608 return COSTS_N_INSNS (1);
4611 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4614 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
4621 return COSTS_N_INSNS (2) + cycles
;
4623 return COSTS_N_INSNS (1) + 16;
4626 return (COSTS_N_INSNS (1)
4627 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
4628 + GET_CODE (SET_DEST (x
)) == MEM
));
4633 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
4635 if (thumb_shiftable_const (INTVAL (x
)))
4636 return COSTS_N_INSNS (2);
4637 return COSTS_N_INSNS (3);
4639 else if ((outer
== PLUS
|| outer
== COMPARE
)
4640 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
4642 else if (outer
== AND
4643 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
4644 return COSTS_N_INSNS (1);
4645 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
4646 || outer
== LSHIFTRT
)
4648 return COSTS_N_INSNS (2);
4654 return COSTS_N_INSNS (3);
4672 /* XXX another guess. */
4673 /* Memory costs quite a lot for the first word, but subsequent words
4674 load at the equivalent of a single insn each. */
4675 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4676 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4681 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4686 /* XXX still guessing. */
4687 switch (GET_MODE (XEXP (x
, 0)))
4690 return (1 + (mode
== DImode
? 4 : 0)
4691 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4694 return (4 + (mode
== DImode
? 4 : 0)
4695 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4698 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4710 /* Worker routine for arm_rtx_costs. */
4711 /* ??? This needs updating for thumb2. */
4713 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
4715 enum machine_mode mode
= GET_MODE (x
);
4716 enum rtx_code subcode
;
4722 /* Memory costs quite a lot for the first word, but subsequent words
4723 load at the equivalent of a single insn each. */
4724 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
4725 + (GET_CODE (x
) == SYMBOL_REF
4726 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
4732 return optimize_size
? COSTS_N_INSNS (2) : 100;
4735 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4742 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
4744 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
4745 + ((GET_CODE (XEXP (x
, 0)) == REG
4746 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4747 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4749 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
4750 || (GET_CODE (XEXP (x
, 0)) == SUBREG
4751 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
4753 + ((GET_CODE (XEXP (x
, 1)) == REG
4754 || (GET_CODE (XEXP (x
, 1)) == SUBREG
4755 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
4756 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
4760 if (GET_CODE (XEXP (x
, 1)) == MULT
&& mode
== SImode
&& arm_arch_thumb2
)
4762 extra_cost
= rtx_cost (XEXP (x
, 1), code
);
4763 if (!REG_OR_SUBREG_REG (XEXP (x
, 0)))
4764 extra_cost
+= 4 * ARM_NUM_REGS (mode
);
4769 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
4770 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4771 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
4772 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
4775 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4776 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4777 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4778 && arm_const_double_rtx (XEXP (x
, 1))))
4780 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4781 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
4782 && arm_const_double_rtx (XEXP (x
, 0))))
4785 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
4786 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
4787 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
4788 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
4789 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
4790 || subcode
== ROTATE
|| subcode
== ROTATERT
4792 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4793 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
4794 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
4795 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
4796 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
4797 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
4798 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
4803 if (GET_CODE (XEXP (x
, 0)) == MULT
)
4805 extra_cost
= rtx_cost (XEXP (x
, 0), code
);
4806 if (!REG_OR_SUBREG_REG (XEXP (x
, 1)))
4807 extra_cost
+= 4 * ARM_NUM_REGS (mode
);
4811 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4812 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4813 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4814 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
4815 && arm_const_double_rtx (XEXP (x
, 1))))
4819 case AND
: case XOR
: case IOR
:
4822 /* Normally the frame registers will be spilt into reg+const during
4823 reload, so it is a bad idea to combine them with other instructions,
4824 since then they might not be moved outside of loops. As a compromise
4825 we allow integration with ops that have a constant as their second
4827 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
4828 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
4829 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4830 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
4831 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
4835 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
4836 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4837 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4838 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4841 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
4842 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
4843 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
4844 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
4845 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
4848 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
4849 return (1 + extra_cost
4850 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
4851 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
4852 || subcode
== ROTATE
|| subcode
== ROTATERT
4854 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4855 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
4856 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
4857 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
4858 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
4859 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
4865 /* This should have been handled by the CPU specific routines. */
4869 if (arm_arch3m
&& mode
== SImode
4870 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4871 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4872 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4873 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
4874 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4875 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
4880 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4881 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
4885 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4887 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
4890 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
4898 return 4 + (mode
== DImode
? 4 : 0);
4901 /* ??? value extensions are cheaper on armv6. */
4902 if (GET_MODE (XEXP (x
, 0)) == QImode
)
4903 return (4 + (mode
== DImode
? 4 : 0)
4904 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4907 switch (GET_MODE (XEXP (x
, 0)))
4910 return (1 + (mode
== DImode
? 4 : 0)
4911 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4914 return (4 + (mode
== DImode
? 4 : 0)
4915 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4918 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
4933 if (const_ok_for_arm (INTVAL (x
)))
4934 return outer
== SET
? 2 : -1;
4935 else if (outer
== AND
4936 && const_ok_for_arm (~INTVAL (x
)))
4938 else if ((outer
== COMPARE
4939 || outer
== PLUS
|| outer
== MINUS
)
4940 && const_ok_for_arm (-INTVAL (x
)))
4951 if (arm_const_double_rtx (x
))
4952 return outer
== SET
? 2 : -1;
4953 else if ((outer
== COMPARE
|| outer
== PLUS
)
4954 && neg_const_double_rtx_ok_for_fpa (x
))
4963 /* RTX costs when optimizing for size. */
4965 arm_size_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4967 enum machine_mode mode
= GET_MODE (x
);
4971 /* XXX TBD. For now, use the standard costs. */
4972 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
4979 /* A memory access costs 1 insn if the mode is small, or the address is
4980 a single register, otherwise it costs one insn per word. */
4981 if (REG_P (XEXP (x
, 0)))
4982 *total
= COSTS_N_INSNS (1);
4984 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
4991 /* Needs a libcall, so it costs about this. */
4992 *total
= COSTS_N_INSNS (2);
4996 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
4998 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
);
5006 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5008 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
);
5011 else if (mode
== SImode
)
5013 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
);
5014 /* Slightly disparage register shifts, but not by much. */
5015 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
5016 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
);
5020 /* Needs a libcall. */
5021 *total
= COSTS_N_INSNS (2);
5025 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5027 *total
= COSTS_N_INSNS (1);
5033 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
5034 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
5036 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
5037 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
5038 || subcode1
== ROTATE
|| subcode1
== ROTATERT
5039 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
5040 || subcode1
== ASHIFTRT
)
5042 /* It's just the cost of the two operands. */
5047 *total
= COSTS_N_INSNS (1);
5051 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5055 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5057 *total
= COSTS_N_INSNS (1);
5062 case AND
: case XOR
: case IOR
:
5065 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
5067 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
5068 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
5069 || (code
== AND
&& subcode
== NOT
))
5071 /* It's just the cost of the two operands. */
5077 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5081 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5085 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5086 *total
= COSTS_N_INSNS (1);
5089 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5098 if (cc_register (XEXP (x
, 0), VOIDmode
))
5101 *total
= COSTS_N_INSNS (1);
5105 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5106 *total
= COSTS_N_INSNS (1);
5108 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
5113 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
5115 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
5116 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
5119 *total
+= COSTS_N_INSNS (1);
5124 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
5126 switch (GET_MODE (XEXP (x
, 0)))
5129 *total
+= COSTS_N_INSNS (1);
5133 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
5139 *total
+= COSTS_N_INSNS (2);
5144 *total
+= COSTS_N_INSNS (1);
5149 if (const_ok_for_arm (INTVAL (x
)))
5150 *total
= COSTS_N_INSNS (outer_code
== SET
? 1 : 0);
5151 else if (const_ok_for_arm (~INTVAL (x
)))
5152 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
5153 else if (const_ok_for_arm (-INTVAL (x
)))
5155 if (outer_code
== COMPARE
|| outer_code
== PLUS
5156 || outer_code
== MINUS
)
5159 *total
= COSTS_N_INSNS (1);
5162 *total
= COSTS_N_INSNS (2);
5168 *total
= COSTS_N_INSNS (2);
5172 *total
= COSTS_N_INSNS (4);
5176 if (mode
!= VOIDmode
)
5177 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
5179 *total
= COSTS_N_INSNS (4); /* How knows? */
5184 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5185 supported on any "slowmul" cores, so it can be ignored. */
5188 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5190 enum machine_mode mode
= GET_MODE (x
);
5194 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5201 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5208 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5210 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5211 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5212 int cost
, const_ok
= const_ok_for_arm (i
);
5213 int j
, booth_unit_size
;
5215 /* Tune as appropriate. */
5216 cost
= const_ok
? 4 : 8;
5217 booth_unit_size
= 2;
5218 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
5220 i
>>= booth_unit_size
;
5228 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5229 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5233 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5239 /* RTX cost for cores with a fast multiply unit (M variants). */
5242 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5244 enum machine_mode mode
= GET_MODE (x
);
5248 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5252 /* ??? should thumb2 use different costs? */
5256 /* There is no point basing this on the tuning, since it is always the
5257 fast variant if it exists at all. */
5259 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5260 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5261 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5268 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5275 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5277 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5278 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5279 int cost
, const_ok
= const_ok_for_arm (i
);
5280 int j
, booth_unit_size
;
5282 /* Tune as appropriate. */
5283 cost
= const_ok
? 4 : 8;
5284 booth_unit_size
= 8;
5285 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
5287 i
>>= booth_unit_size
;
5295 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5296 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5300 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5306 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5307 so it can be ignored. */
5310 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5312 enum machine_mode mode
= GET_MODE (x
);
5316 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5323 /* There is no point basing this on the tuning, since it is always the
5324 fast variant if it exists at all. */
5326 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5327 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5328 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5335 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
5342 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5344 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
5345 & (unsigned HOST_WIDE_INT
) 0xffffffff);
5346 int cost
, const_ok
= const_ok_for_arm (i
);
5347 unsigned HOST_WIDE_INT masked_const
;
5349 /* The cost will be related to two insns.
5350 First a load of the constant (MOV or LDR), then a multiply. */
5353 cost
+= 1; /* LDR is probably more expensive because
5354 of longer result latency. */
5355 masked_const
= i
& 0xffff8000;
5356 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
5358 masked_const
= i
& 0xf8000000;
5359 if (masked_const
== 0 || masked_const
== 0xf8000000)
5368 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
5369 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
5373 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5374 will stall until the multiplication is complete. */
5375 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5376 *total
= 4 + rtx_cost (XEXP (x
, 0), code
);
5378 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5382 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5388 /* RTX costs for 9e (and later) cores. */
5391 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
5393 enum machine_mode mode
= GET_MODE (x
);
5402 *total
= COSTS_N_INSNS (3);
5406 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
5414 /* There is no point basing this on the tuning, since it is always the
5415 fast variant if it exists at all. */
5417 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
5418 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5419 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
5426 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5443 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
5444 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
5448 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
5452 /* All address computations that can be done are free, but rtx cost returns
5453 the same for practically all of them. So we weight the different types
5454 of address here in the order (most pref first):
5455 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5457 arm_arm_address_cost (rtx x
)
5459 enum rtx_code c
= GET_CODE (x
);
5461 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
5463 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
5466 if (c
== PLUS
|| c
== MINUS
)
5468 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5471 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
5481 arm_thumb_address_cost (rtx x
)
5483 enum rtx_code c
= GET_CODE (x
);
5488 && GET_CODE (XEXP (x
, 0)) == REG
5489 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5496 arm_address_cost (rtx x
)
5498 return TARGET_32BIT
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
5502 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
5506 /* Some true dependencies can have a higher cost depending
5507 on precisely how certain input operands are used. */
5509 && REG_NOTE_KIND (link
) == 0
5510 && recog_memoized (insn
) >= 0
5511 && recog_memoized (dep
) >= 0)
5513 int shift_opnum
= get_attr_shift (insn
);
5514 enum attr_type attr_type
= get_attr_type (dep
);
5516 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5517 operand for INSN. If we have a shifted input operand and the
5518 instruction we depend on is another ALU instruction, then we may
5519 have to account for an additional stall. */
5520 if (shift_opnum
!= 0
5521 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
5523 rtx shifted_operand
;
5526 /* Get the shifted operand. */
5527 extract_insn (insn
);
5528 shifted_operand
= recog_data
.operand
[shift_opnum
];
5530 /* Iterate over all the operands in DEP. If we write an operand
5531 that overlaps with SHIFTED_OPERAND, then we have increase the
5532 cost of this dependency. */
5534 preprocess_constraints ();
5535 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
5537 /* We can ignore strict inputs. */
5538 if (recog_data
.operand_type
[opno
] == OP_IN
)
5541 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
5548 /* XXX This is not strictly true for the FPA. */
5549 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
5550 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
5553 /* Call insns don't incur a stall, even if they follow a load. */
5554 if (REG_NOTE_KIND (link
) == 0
5555 && GET_CODE (insn
) == CALL_INSN
)
5558 if ((i_pat
= single_set (insn
)) != NULL
5559 && GET_CODE (SET_SRC (i_pat
)) == MEM
5560 && (d_pat
= single_set (dep
)) != NULL
5561 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
5563 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
5564 /* This is a load after a store, there is no conflict if the load reads
5565 from a cached area. Assume that loads from the stack, and from the
5566 constant pool are cached, and that others will miss. This is a
5569 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
5570 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
5571 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
5572 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
5579 static int fp_consts_inited
= 0;
5581 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5582 static const char * const strings_fp
[8] =
5585 "4", "5", "0.5", "10"
5588 static REAL_VALUE_TYPE values_fp
[8];
5591 init_fp_table (void)
5597 fp_consts_inited
= 1;
5599 fp_consts_inited
= 8;
5601 for (i
= 0; i
< fp_consts_inited
; i
++)
5603 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
5608 /* Return TRUE if rtx X is a valid immediate FP constant. */
5610 arm_const_double_rtx (rtx x
)
5615 if (!fp_consts_inited
)
5618 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5619 if (REAL_VALUE_MINUS_ZERO (r
))
5622 for (i
= 0; i
< fp_consts_inited
; i
++)
5623 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5629 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5631 neg_const_double_rtx_ok_for_fpa (rtx x
)
5636 if (!fp_consts_inited
)
5639 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
5640 r
= REAL_VALUE_NEGATE (r
);
5641 if (REAL_VALUE_MINUS_ZERO (r
))
5644 for (i
= 0; i
< 8; i
++)
5645 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
5651 /* Predicates for `match_operand' and `match_operator'. */
5653 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5655 cirrus_memory_offset (rtx op
)
5657 /* Reject eliminable registers. */
5658 if (! (reload_in_progress
|| reload_completed
)
5659 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5660 || reg_mentioned_p (arg_pointer_rtx
, op
)
5661 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5662 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5663 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5664 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5667 if (GET_CODE (op
) == MEM
)
5673 /* Match: (mem (reg)). */
5674 if (GET_CODE (ind
) == REG
)
5680 if (GET_CODE (ind
) == PLUS
5681 && GET_CODE (XEXP (ind
, 0)) == REG
5682 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5683 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
5690 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5691 WB is true if full writeback address modes are allowed and is false
5692 if limited writeback address modes (POST_INC and PRE_DEC) are
5696 arm_coproc_mem_operand (rtx op
, bool wb
)
5700 /* Reject eliminable registers. */
5701 if (! (reload_in_progress
|| reload_completed
)
5702 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
5703 || reg_mentioned_p (arg_pointer_rtx
, op
)
5704 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
5705 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
5706 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
5707 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
5710 /* Constants are converted into offsets from labels. */
5711 if (GET_CODE (op
) != MEM
)
5716 if (reload_completed
5717 && (GET_CODE (ind
) == LABEL_REF
5718 || (GET_CODE (ind
) == CONST
5719 && GET_CODE (XEXP (ind
, 0)) == PLUS
5720 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
5721 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
5724 /* Match: (mem (reg)). */
5725 if (GET_CODE (ind
) == REG
)
5726 return arm_address_register_rtx_p (ind
, 0);
5728 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5729 acceptable in any case (subject to verification by
5730 arm_address_register_rtx_p). We need WB to be true to accept
5731 PRE_INC and POST_DEC. */
5732 if (GET_CODE (ind
) == POST_INC
5733 || GET_CODE (ind
) == PRE_DEC
5735 && (GET_CODE (ind
) == PRE_INC
5736 || GET_CODE (ind
) == POST_DEC
)))
5737 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
5740 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
5741 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
5742 && GET_CODE (XEXP (ind
, 1)) == PLUS
5743 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
5744 ind
= XEXP (ind
, 1);
5749 if (GET_CODE (ind
) == PLUS
5750 && GET_CODE (XEXP (ind
, 0)) == REG
5751 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
5752 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
5753 && INTVAL (XEXP (ind
, 1)) > -1024
5754 && INTVAL (XEXP (ind
, 1)) < 1024
5755 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
5761 /* Return true if X is a register that will be eliminated later on. */
5763 arm_eliminable_register (rtx x
)
5765 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
5766 || REGNO (x
) == ARG_POINTER_REGNUM
5767 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
5768 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
5771 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5772 coprocessor registers. Otherwise return NO_REGS. */
5775 coproc_secondary_reload_class (enum machine_mode mode
, rtx x
, bool wb
)
5777 if (arm_coproc_mem_operand (x
, wb
) || s_register_operand (x
, mode
))
5780 return GENERAL_REGS
;
5783 /* Values which must be returned in the most-significant end of the return
5787 arm_return_in_msb (tree valtype
)
5789 return (TARGET_AAPCS_BASED
5791 && (AGGREGATE_TYPE_P (valtype
)
5792 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
5795 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5796 Use by the Cirrus Maverick code which has to workaround
5797 a hardware bug triggered by such instructions. */
5799 arm_memory_load_p (rtx insn
)
5801 rtx body
, lhs
, rhs
;;
5803 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
5806 body
= PATTERN (insn
);
5808 if (GET_CODE (body
) != SET
)
5811 lhs
= XEXP (body
, 0);
5812 rhs
= XEXP (body
, 1);
5814 lhs
= REG_OR_SUBREG_RTX (lhs
);
5816 /* If the destination is not a general purpose
5817 register we do not have to worry. */
5818 if (GET_CODE (lhs
) != REG
5819 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
5822 /* As well as loads from memory we also have to react
5823 to loads of invalid constants which will be turned
5824 into loads from the minipool. */
5825 return (GET_CODE (rhs
) == MEM
5826 || GET_CODE (rhs
) == SYMBOL_REF
5827 || note_invalid_constants (insn
, -1, false));
5830 /* Return TRUE if INSN is a Cirrus instruction. */
5832 arm_cirrus_insn_p (rtx insn
)
5834 enum attr_cirrus attr
;
5836 /* get_attr cannot accept USE or CLOBBER. */
5838 || GET_CODE (insn
) != INSN
5839 || GET_CODE (PATTERN (insn
)) == USE
5840 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5843 attr
= get_attr_cirrus (insn
);
5845 return attr
!= CIRRUS_NOT
;
5848 /* Cirrus reorg for invalid instruction combinations. */
5850 cirrus_reorg (rtx first
)
5852 enum attr_cirrus attr
;
5853 rtx body
= PATTERN (first
);
5857 /* Any branch must be followed by 2 non Cirrus instructions. */
5858 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
5861 t
= next_nonnote_insn (first
);
5863 if (arm_cirrus_insn_p (t
))
5866 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5870 emit_insn_after (gen_nop (), first
);
5875 /* (float (blah)) is in parallel with a clobber. */
5876 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
5877 body
= XVECEXP (body
, 0, 0);
5879 if (GET_CODE (body
) == SET
)
5881 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
5883 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5884 be followed by a non Cirrus insn. */
5885 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
5887 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
5888 emit_insn_after (gen_nop (), first
);
5892 else if (arm_memory_load_p (first
))
5894 unsigned int arm_regno
;
5896 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5897 ldr/cfmv64hr combination where the Rd field is the same
5898 in both instructions must be split with a non Cirrus
5905 /* Get Arm register number for ldr insn. */
5906 if (GET_CODE (lhs
) == REG
)
5907 arm_regno
= REGNO (lhs
);
5910 gcc_assert (GET_CODE (rhs
) == REG
);
5911 arm_regno
= REGNO (rhs
);
5915 first
= next_nonnote_insn (first
);
5917 if (! arm_cirrus_insn_p (first
))
5920 body
= PATTERN (first
);
5922 /* (float (blah)) is in parallel with a clobber. */
5923 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
5924 body
= XVECEXP (body
, 0, 0);
5926 if (GET_CODE (body
) == FLOAT
)
5927 body
= XEXP (body
, 0);
5929 if (get_attr_cirrus (first
) == CIRRUS_MOVE
5930 && GET_CODE (XEXP (body
, 1)) == REG
5931 && arm_regno
== REGNO (XEXP (body
, 1)))
5932 emit_insn_after (gen_nop (), first
);
5938 /* get_attr cannot accept USE or CLOBBER. */
5940 || GET_CODE (first
) != INSN
5941 || GET_CODE (PATTERN (first
)) == USE
5942 || GET_CODE (PATTERN (first
)) == CLOBBER
)
5945 attr
= get_attr_cirrus (first
);
5947 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5948 must be followed by a non-coprocessor instruction. */
5949 if (attr
== CIRRUS_COMPARE
)
5953 t
= next_nonnote_insn (first
);
5955 if (arm_cirrus_insn_p (t
))
5958 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
5962 emit_insn_after (gen_nop (), first
);
5968 /* Return TRUE if X references a SYMBOL_REF. */
5970 symbol_mentioned_p (rtx x
)
5975 if (GET_CODE (x
) == SYMBOL_REF
)
5978 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5979 are constant offsets, not symbols. */
5980 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
5983 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5985 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5991 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5992 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5995 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
6002 /* Return TRUE if X references a LABEL_REF. */
6004 label_mentioned_p (rtx x
)
6009 if (GET_CODE (x
) == LABEL_REF
)
6012 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6013 instruction, but they are constant offsets, not symbols. */
6014 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
6017 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6018 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6024 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6025 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
6028 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
6036 tls_mentioned_p (rtx x
)
6038 switch (GET_CODE (x
))
6041 return tls_mentioned_p (XEXP (x
, 0));
6044 if (XINT (x
, 1) == UNSPEC_TLS
)
6052 /* Must not copy a SET whose source operand is PC-relative. */
6055 arm_cannot_copy_insn_p (rtx insn
)
6057 rtx pat
= PATTERN (insn
);
6059 if (GET_CODE (pat
) == PARALLEL
6060 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
)
6062 rtx rhs
= SET_SRC (XVECEXP (pat
, 0, 0));
6064 if (GET_CODE (rhs
) == UNSPEC
6065 && XINT (rhs
, 1) == UNSPEC_PIC_BASE
)
6068 if (GET_CODE (rhs
) == MEM
6069 && GET_CODE (XEXP (rhs
, 0)) == UNSPEC
6070 && XINT (XEXP (rhs
, 0), 1) == UNSPEC_PIC_BASE
)
6080 enum rtx_code code
= GET_CODE (x
);
6097 /* Return 1 if memory locations are adjacent. */
6099 adjacent_mem_locations (rtx a
, rtx b
)
6101 /* We don't guarantee to preserve the order of these memory refs. */
6102 if (volatile_refs_p (a
) || volatile_refs_p (b
))
6105 if ((GET_CODE (XEXP (a
, 0)) == REG
6106 || (GET_CODE (XEXP (a
, 0)) == PLUS
6107 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
6108 && (GET_CODE (XEXP (b
, 0)) == REG
6109 || (GET_CODE (XEXP (b
, 0)) == PLUS
6110 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
6112 HOST_WIDE_INT val0
= 0, val1
= 0;
6116 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
6118 reg0
= XEXP (XEXP (a
, 0), 0);
6119 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
6124 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
6126 reg1
= XEXP (XEXP (b
, 0), 0);
6127 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
6132 /* Don't accept any offset that will require multiple
6133 instructions to handle, since this would cause the
6134 arith_adjacentmem pattern to output an overlong sequence. */
6135 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
6138 /* Don't allow an eliminable register: register elimination can make
6139 the offset too large. */
6140 if (arm_eliminable_register (reg0
))
6143 val_diff
= val1
- val0
;
6147 /* If the target has load delay slots, then there's no benefit
6148 to using an ldm instruction unless the offset is zero and
6149 we are optimizing for size. */
6150 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
6151 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
6152 && (val_diff
== 4 || val_diff
== -4));
6155 return ((REGNO (reg0
) == REGNO (reg1
))
6156 && (val_diff
== 4 || val_diff
== -4));
6163 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6164 HOST_WIDE_INT
*load_offset
)
6166 int unsorted_regs
[4];
6167 HOST_WIDE_INT unsorted_offsets
[4];
6172 /* Can only handle 2, 3, or 4 insns at present,
6173 though could be easily extended if required. */
6174 gcc_assert (nops
>= 2 && nops
<= 4);
6176 /* Loop over the operands and check that the memory references are
6177 suitable (i.e. immediate offsets from the same base register). At
6178 the same time, extract the target register, and the memory
6180 for (i
= 0; i
< nops
; i
++)
6185 /* Convert a subreg of a mem into the mem itself. */
6186 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6187 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6189 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6191 /* Don't reorder volatile memory references; it doesn't seem worth
6192 looking for the case where the order is ok anyway. */
6193 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6196 offset
= const0_rtx
;
6198 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6199 || (GET_CODE (reg
) == SUBREG
6200 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6201 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6202 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6204 || (GET_CODE (reg
) == SUBREG
6205 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6206 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6211 base_reg
= REGNO (reg
);
6212 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6213 ? REGNO (operands
[i
])
6214 : REGNO (SUBREG_REG (operands
[i
])));
6219 if (base_reg
!= (int) REGNO (reg
))
6220 /* Not addressed from the same base register. */
6223 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6224 ? REGNO (operands
[i
])
6225 : REGNO (SUBREG_REG (operands
[i
])));
6226 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6230 /* If it isn't an integer register, or if it overwrites the
6231 base register but isn't the last insn in the list, then
6232 we can't do this. */
6233 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
6234 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
6237 unsorted_offsets
[i
] = INTVAL (offset
);
6240 /* Not a suitable memory address. */
6244 /* All the useful information has now been extracted from the
6245 operands into unsorted_regs and unsorted_offsets; additionally,
6246 order[0] has been set to the lowest numbered register in the
6247 list. Sort the registers into order, and check that the memory
6248 offsets are ascending and adjacent. */
6250 for (i
= 1; i
< nops
; i
++)
6254 order
[i
] = order
[i
- 1];
6255 for (j
= 0; j
< nops
; j
++)
6256 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6257 && (order
[i
] == order
[i
- 1]
6258 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6261 /* Have we found a suitable register? if not, one must be used more
6263 if (order
[i
] == order
[i
- 1])
6266 /* Is the memory address adjacent and ascending? */
6267 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6275 for (i
= 0; i
< nops
; i
++)
6276 regs
[i
] = unsorted_regs
[order
[i
]];
6278 *load_offset
= unsorted_offsets
[order
[0]];
6281 if (unsorted_offsets
[order
[0]] == 0)
6282 return 1; /* ldmia */
6284 if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
6285 return 2; /* ldmib */
6287 if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
6288 return 3; /* ldmda */
6290 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6291 return 4; /* ldmdb */
6293 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6294 if the offset isn't small enough. The reason 2 ldrs are faster
6295 is because these ARMs are able to do more than one cache access
6296 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6297 whilst the ARM8 has a double bandwidth cache. This means that
6298 these cores can do both an instruction fetch and a data fetch in
6299 a single cycle, so the trick of calculating the address into a
6300 scratch register (one of the result regs) and then doing a load
6301 multiple actually becomes slower (and no smaller in code size).
6302 That is the transformation
6304 ldr rd1, [rbase + offset]
6305 ldr rd2, [rbase + offset + 4]
6309 add rd1, rbase, offset
6310 ldmia rd1, {rd1, rd2}
6312 produces worse code -- '3 cycles + any stalls on rd2' instead of
6313 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6314 access per cycle, the first sequence could never complete in less
6315 than 6 cycles, whereas the ldm sequence would only take 5 and
6316 would make better use of sequential accesses if not hitting the
6319 We cheat here and test 'arm_ld_sched' which we currently know to
6320 only be true for the ARM8, ARM9 and StrongARM. If this ever
6321 changes, then the test below needs to be reworked. */
6322 if (nops
== 2 && arm_ld_sched
)
6325 /* Can't do it without setting up the offset, only do this if it takes
6326 no more than one insn. */
6327 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
6328 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
6332 emit_ldm_seq (rtx
*operands
, int nops
)
6336 HOST_WIDE_INT offset
;
6340 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6343 strcpy (buf
, "ldm%(ia%)\t");
6347 strcpy (buf
, "ldm%(ib%)\t");
6351 strcpy (buf
, "ldm%(da%)\t");
6355 strcpy (buf
, "ldm%(db%)\t");
6360 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6361 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6364 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
6365 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
6367 output_asm_insn (buf
, operands
);
6369 strcpy (buf
, "ldm%(ia%)\t");
6376 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6377 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6379 for (i
= 1; i
< nops
; i
++)
6380 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6381 reg_names
[regs
[i
]]);
6383 strcat (buf
, "}\t%@ phole ldm");
6385 output_asm_insn (buf
, operands
);
6390 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
6391 HOST_WIDE_INT
* load_offset
)
6393 int unsorted_regs
[4];
6394 HOST_WIDE_INT unsorted_offsets
[4];
6399 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6400 extended if required. */
6401 gcc_assert (nops
>= 2 && nops
<= 4);
6403 /* Loop over the operands and check that the memory references are
6404 suitable (i.e. immediate offsets from the same base register). At
6405 the same time, extract the target register, and the memory
6407 for (i
= 0; i
< nops
; i
++)
6412 /* Convert a subreg of a mem into the mem itself. */
6413 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
6414 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
6416 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
6418 /* Don't reorder volatile memory references; it doesn't seem worth
6419 looking for the case where the order is ok anyway. */
6420 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
6423 offset
= const0_rtx
;
6425 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
6426 || (GET_CODE (reg
) == SUBREG
6427 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6428 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
6429 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
6431 || (GET_CODE (reg
) == SUBREG
6432 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
6433 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
6438 base_reg
= REGNO (reg
);
6439 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
6440 ? REGNO (operands
[i
])
6441 : REGNO (SUBREG_REG (operands
[i
])));
6446 if (base_reg
!= (int) REGNO (reg
))
6447 /* Not addressed from the same base register. */
6450 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
6451 ? REGNO (operands
[i
])
6452 : REGNO (SUBREG_REG (operands
[i
])));
6453 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
6457 /* If it isn't an integer register, then we can't do this. */
6458 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
6461 unsorted_offsets
[i
] = INTVAL (offset
);
6464 /* Not a suitable memory address. */
6468 /* All the useful information has now been extracted from the
6469 operands into unsorted_regs and unsorted_offsets; additionally,
6470 order[0] has been set to the lowest numbered register in the
6471 list. Sort the registers into order, and check that the memory
6472 offsets are ascending and adjacent. */
6474 for (i
= 1; i
< nops
; i
++)
6478 order
[i
] = order
[i
- 1];
6479 for (j
= 0; j
< nops
; j
++)
6480 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
6481 && (order
[i
] == order
[i
- 1]
6482 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
6485 /* Have we found a suitable register? if not, one must be used more
6487 if (order
[i
] == order
[i
- 1])
6490 /* Is the memory address adjacent and ascending? */
6491 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
6499 for (i
= 0; i
< nops
; i
++)
6500 regs
[i
] = unsorted_regs
[order
[i
]];
6502 *load_offset
= unsorted_offsets
[order
[0]];
6505 if (unsorted_offsets
[order
[0]] == 0)
6506 return 1; /* stmia */
6508 if (unsorted_offsets
[order
[0]] == 4)
6509 return 2; /* stmib */
6511 if (unsorted_offsets
[order
[nops
- 1]] == 0)
6512 return 3; /* stmda */
6514 if (unsorted_offsets
[order
[nops
- 1]] == -4)
6515 return 4; /* stmdb */
6521 emit_stm_seq (rtx
*operands
, int nops
)
6525 HOST_WIDE_INT offset
;
6529 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
6532 strcpy (buf
, "stm%(ia%)\t");
6536 strcpy (buf
, "stm%(ib%)\t");
6540 strcpy (buf
, "stm%(da%)\t");
6544 strcpy (buf
, "stm%(db%)\t");
6551 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
6552 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
6554 for (i
= 1; i
< nops
; i
++)
6555 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
6556 reg_names
[regs
[i
]]);
6558 strcat (buf
, "}\t%@ phole stm");
6560 output_asm_insn (buf
, operands
);
6564 /* Routines for use in generating RTL. */
6567 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
6568 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6570 HOST_WIDE_INT offset
= *offsetp
;
6573 int sign
= up
? 1 : -1;
6576 /* XScale has load-store double instructions, but they have stricter
6577 alignment requirements than load-store multiple, so we cannot
6580 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6581 the pipeline until completion.
6589 An ldr instruction takes 1-3 cycles, but does not block the
6598 Best case ldr will always win. However, the more ldr instructions
6599 we issue, the less likely we are to be able to schedule them well.
6600 Using ldr instructions also increases code size.
6602 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6603 for counts of 3 or 4 regs. */
6604 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6610 for (i
= 0; i
< count
; i
++)
6612 addr
= plus_constant (from
, i
* 4 * sign
);
6613 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6614 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
6620 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
6630 result
= gen_rtx_PARALLEL (VOIDmode
,
6631 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6634 XVECEXP (result
, 0, 0)
6635 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
6640 for (j
= 0; i
< count
; i
++, j
++)
6642 addr
= plus_constant (from
, j
* 4 * sign
);
6643 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6644 XVECEXP (result
, 0, i
)
6645 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
6656 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
6657 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
6659 HOST_WIDE_INT offset
= *offsetp
;
6662 int sign
= up
? 1 : -1;
6665 /* See arm_gen_load_multiple for discussion of
6666 the pros/cons of ldm/stm usage for XScale. */
6667 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
6673 for (i
= 0; i
< count
; i
++)
6675 addr
= plus_constant (to
, i
* 4 * sign
);
6676 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
6677 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
6683 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
6693 result
= gen_rtx_PARALLEL (VOIDmode
,
6694 rtvec_alloc (count
+ (write_back
? 1 : 0)));
6697 XVECEXP (result
, 0, 0)
6698 = gen_rtx_SET (VOIDmode
, to
,
6699 plus_constant (to
, count
* 4 * sign
));
6704 for (j
= 0; i
< count
; i
++, j
++)
6706 addr
= plus_constant (to
, j
* 4 * sign
);
6707 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
6708 XVECEXP (result
, 0, i
)
6709 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6720 arm_gen_movmemqi (rtx
*operands
)
6722 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6723 HOST_WIDE_INT srcoffset
, dstoffset
;
6725 rtx src
, dst
, srcbase
, dstbase
;
6726 rtx part_bytes_reg
= NULL
;
6729 if (GET_CODE (operands
[2]) != CONST_INT
6730 || GET_CODE (operands
[3]) != CONST_INT
6731 || INTVAL (operands
[2]) > 64
6732 || INTVAL (operands
[3]) & 3)
6735 dstbase
= operands
[0];
6736 srcbase
= operands
[1];
6738 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
6739 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
6741 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6742 out_words_to_go
= INTVAL (operands
[2]) / 4;
6743 last_bytes
= INTVAL (operands
[2]) & 3;
6744 dstoffset
= srcoffset
= 0;
6746 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6747 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6749 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6751 if (in_words_to_go
> 4)
6752 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6753 srcbase
, &srcoffset
));
6755 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6756 FALSE
, srcbase
, &srcoffset
));
6758 if (out_words_to_go
)
6760 if (out_words_to_go
> 4)
6761 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6762 dstbase
, &dstoffset
));
6763 else if (out_words_to_go
!= 1)
6764 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6768 dstbase
, &dstoffset
));
6771 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6772 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6773 if (last_bytes
!= 0)
6775 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6781 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6782 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6785 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6786 if (out_words_to_go
)
6790 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6791 sreg
= copy_to_reg (mem
);
6793 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
6794 emit_move_insn (mem
, sreg
);
6797 gcc_assert (!in_words_to_go
); /* Sanity check */
6802 gcc_assert (in_words_to_go
> 0);
6804 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
6805 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6808 gcc_assert (!last_bytes
|| part_bytes_reg
);
6810 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6812 rtx tmp
= gen_reg_rtx (SImode
);
6814 /* The bytes we want are in the top end of the word. */
6815 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6816 GEN_INT (8 * (4 - last_bytes
))));
6817 part_bytes_reg
= tmp
;
6821 mem
= adjust_automodify_address (dstbase
, QImode
,
6822 plus_constant (dst
, last_bytes
- 1),
6823 dstoffset
+ last_bytes
- 1);
6824 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6828 tmp
= gen_reg_rtx (SImode
);
6829 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6830 part_bytes_reg
= tmp
;
6839 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
6840 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6844 rtx tmp
= gen_reg_rtx (SImode
);
6845 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6846 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6847 part_bytes_reg
= tmp
;
6854 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
6855 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6862 /* Select a dominance comparison mode if possible for a test of the general
6863 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6864 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6865 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6866 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6867 In all cases OP will be either EQ or NE, but we don't need to know which
6868 here. If we are unable to support a dominance comparison we return
6869 CC mode. This will then fail to match for the RTL expressions that
6870 generate this call. */
6872 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6874 enum rtx_code cond1
, cond2
;
6877 /* Currently we will probably get the wrong result if the individual
6878 comparisons are not simple. This also ensures that it is safe to
6879 reverse a comparison if necessary. */
6880 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6882 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6886 /* The if_then_else variant of this tests the second condition if the
6887 first passes, but is true if the first fails. Reverse the first
6888 condition to get a true "inclusive-or" expression. */
6889 if (cond_or
== DOM_CC_NX_OR_Y
)
6890 cond1
= reverse_condition (cond1
);
6892 /* If the comparisons are not equal, and one doesn't dominate the other,
6893 then we can't do this. */
6895 && !comparison_dominates_p (cond1
, cond2
)
6896 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6901 enum rtx_code temp
= cond1
;
6909 if (cond_or
== DOM_CC_X_AND_Y
)
6914 case EQ
: return CC_DEQmode
;
6915 case LE
: return CC_DLEmode
;
6916 case LEU
: return CC_DLEUmode
;
6917 case GE
: return CC_DGEmode
;
6918 case GEU
: return CC_DGEUmode
;
6919 default: gcc_unreachable ();
6923 if (cond_or
== DOM_CC_X_AND_Y
)
6939 if (cond_or
== DOM_CC_X_AND_Y
)
6955 if (cond_or
== DOM_CC_X_AND_Y
)
6971 if (cond_or
== DOM_CC_X_AND_Y
)
6986 /* The remaining cases only occur when both comparisons are the
6989 gcc_assert (cond1
== cond2
);
6993 gcc_assert (cond1
== cond2
);
6997 gcc_assert (cond1
== cond2
);
7001 gcc_assert (cond1
== cond2
);
7005 gcc_assert (cond1
== cond2
);
7014 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
7016 /* All floating point compares return CCFP if it is an equality
7017 comparison, and CCFPE otherwise. */
7018 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
7038 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
7047 /* A compare with a shifted operand. Because of canonicalization, the
7048 comparison will have to be swapped when we emit the assembler. */
7049 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
7050 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
7051 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
7052 || GET_CODE (x
) == ROTATERT
))
7055 /* This operation is performed swapped, but since we only rely on the Z
7056 flag we don't need an additional mode. */
7057 if (GET_MODE (y
) == SImode
&& REG_P (y
)
7058 && GET_CODE (x
) == NEG
7059 && (op
== EQ
|| op
== NE
))
7062 /* This is a special case that is used by combine to allow a
7063 comparison of a shifted byte load to be split into a zero-extend
7064 followed by a comparison of the shifted integer (only valid for
7065 equalities and unsigned inequalities). */
7066 if (GET_MODE (x
) == SImode
7067 && GET_CODE (x
) == ASHIFT
7068 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
7069 && GET_CODE (XEXP (x
, 0)) == SUBREG
7070 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
7071 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
7072 && (op
== EQ
|| op
== NE
7073 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
7074 && GET_CODE (y
) == CONST_INT
)
7077 /* A construct for a conditional compare, if the false arm contains
7078 0, then both conditions must be true, otherwise either condition
7079 must be true. Not all conditions are possible, so CCmode is
7080 returned if it can't be done. */
7081 if (GET_CODE (x
) == IF_THEN_ELSE
7082 && (XEXP (x
, 2) == const0_rtx
7083 || XEXP (x
, 2) == const1_rtx
)
7084 && COMPARISON_P (XEXP (x
, 0))
7085 && COMPARISON_P (XEXP (x
, 1)))
7086 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
7087 INTVAL (XEXP (x
, 2)));
7089 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7090 if (GET_CODE (x
) == AND
7091 && COMPARISON_P (XEXP (x
, 0))
7092 && COMPARISON_P (XEXP (x
, 1)))
7093 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
7096 if (GET_CODE (x
) == IOR
7097 && COMPARISON_P (XEXP (x
, 0))
7098 && COMPARISON_P (XEXP (x
, 1)))
7099 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
7102 /* An operation (on Thumb) where we want to test for a single bit.
7103 This is done by shifting that bit up into the top bit of a
7104 scratch register; we can then branch on the sign bit. */
7106 && GET_MODE (x
) == SImode
7107 && (op
== EQ
|| op
== NE
)
7108 && GET_CODE (x
) == ZERO_EXTRACT
7109 && XEXP (x
, 1) == const1_rtx
)
7112 /* An operation that sets the condition codes as a side-effect, the
7113 V flag is not set correctly, so we can only use comparisons where
7114 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7116 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7117 if (GET_MODE (x
) == SImode
7119 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
7120 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
7121 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
7122 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
7123 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
7124 || GET_CODE (x
) == LSHIFTRT
7125 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
7126 || GET_CODE (x
) == ROTATERT
7127 || (TARGET_32BIT
&& GET_CODE (x
) == ZERO_EXTRACT
)))
7130 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
7133 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
7134 && GET_CODE (x
) == PLUS
7135 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
7141 /* X and Y are two things to compare using CODE. Emit the compare insn and
7142 return the rtx for register 0 in the proper mode. FP means this is a
7143 floating point compare: I don't think that it is needed on the arm. */
7145 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
7147 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
7148 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
7150 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
7155 /* Generate a sequence of insns that will generate the correct return
7156 address mask depending on the physical architecture that the program
7159 arm_gen_return_addr_mask (void)
7161 rtx reg
= gen_reg_rtx (Pmode
);
7163 emit_insn (gen_return_addr_mask (reg
));
7168 arm_reload_in_hi (rtx
*operands
)
7170 rtx ref
= operands
[1];
7172 HOST_WIDE_INT offset
= 0;
7174 if (GET_CODE (ref
) == SUBREG
)
7176 offset
= SUBREG_BYTE (ref
);
7177 ref
= SUBREG_REG (ref
);
7180 if (GET_CODE (ref
) == REG
)
7182 /* We have a pseudo which has been spilt onto the stack; there
7183 are two cases here: the first where there is a simple
7184 stack-slot replacement and a second where the stack-slot is
7185 out of range, or is used as a subreg. */
7186 if (reg_equiv_mem
[REGNO (ref
)])
7188 ref
= reg_equiv_mem
[REGNO (ref
)];
7189 base
= find_replacement (&XEXP (ref
, 0));
7192 /* The slot is out of range, or was dressed up in a SUBREG. */
7193 base
= reg_equiv_address
[REGNO (ref
)];
7196 base
= find_replacement (&XEXP (ref
, 0));
7198 /* Handle the case where the address is too complex to be offset by 1. */
7199 if (GET_CODE (base
) == MINUS
7200 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
7202 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7204 emit_set_insn (base_plus
, base
);
7207 else if (GET_CODE (base
) == PLUS
)
7209 /* The addend must be CONST_INT, or we would have dealt with it above. */
7210 HOST_WIDE_INT hi
, lo
;
7212 offset
+= INTVAL (XEXP (base
, 1));
7213 base
= XEXP (base
, 0);
7215 /* Rework the address into a legal sequence of insns. */
7216 /* Valid range for lo is -4095 -> 4095 */
7219 : -((-offset
) & 0xfff));
7221 /* Corner case, if lo is the max offset then we would be out of range
7222 once we have added the additional 1 below, so bump the msb into the
7223 pre-loading insn(s). */
7227 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7228 ^ (HOST_WIDE_INT
) 0x80000000)
7229 - (HOST_WIDE_INT
) 0x80000000);
7231 gcc_assert (hi
+ lo
== offset
);
7235 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7237 /* Get the base address; addsi3 knows how to handle constants
7238 that require more than one insn. */
7239 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7245 /* Operands[2] may overlap operands[0] (though it won't overlap
7246 operands[1]), that's why we asked for a DImode reg -- so we can
7247 use the bit that does not overlap. */
7248 if (REGNO (operands
[2]) == REGNO (operands
[0]))
7249 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7251 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
7253 emit_insn (gen_zero_extendqisi2 (scratch
,
7254 gen_rtx_MEM (QImode
,
7255 plus_constant (base
,
7257 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
7258 gen_rtx_MEM (QImode
,
7259 plus_constant (base
,
7261 if (!BYTES_BIG_ENDIAN
)
7262 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
7263 gen_rtx_IOR (SImode
,
7266 gen_rtx_SUBREG (SImode
, operands
[0], 0),
7270 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
7271 gen_rtx_IOR (SImode
,
7272 gen_rtx_ASHIFT (SImode
, scratch
,
7274 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
7277 /* Handle storing a half-word to memory during reload by synthesizing as two
7278 byte stores. Take care not to clobber the input values until after we
7279 have moved them somewhere safe. This code assumes that if the DImode
7280 scratch in operands[2] overlaps either the input value or output address
7281 in some way, then that value must die in this insn (we absolutely need
7282 two scratch registers for some corner cases). */
7284 arm_reload_out_hi (rtx
*operands
)
7286 rtx ref
= operands
[0];
7287 rtx outval
= operands
[1];
7289 HOST_WIDE_INT offset
= 0;
7291 if (GET_CODE (ref
) == SUBREG
)
7293 offset
= SUBREG_BYTE (ref
);
7294 ref
= SUBREG_REG (ref
);
7297 if (GET_CODE (ref
) == REG
)
7299 /* We have a pseudo which has been spilt onto the stack; there
7300 are two cases here: the first where there is a simple
7301 stack-slot replacement and a second where the stack-slot is
7302 out of range, or is used as a subreg. */
7303 if (reg_equiv_mem
[REGNO (ref
)])
7305 ref
= reg_equiv_mem
[REGNO (ref
)];
7306 base
= find_replacement (&XEXP (ref
, 0));
7309 /* The slot is out of range, or was dressed up in a SUBREG. */
7310 base
= reg_equiv_address
[REGNO (ref
)];
7313 base
= find_replacement (&XEXP (ref
, 0));
7315 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
7317 /* Handle the case where the address is too complex to be offset by 1. */
7318 if (GET_CODE (base
) == MINUS
7319 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
7321 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7323 /* Be careful not to destroy OUTVAL. */
7324 if (reg_overlap_mentioned_p (base_plus
, outval
))
7326 /* Updating base_plus might destroy outval, see if we can
7327 swap the scratch and base_plus. */
7328 if (!reg_overlap_mentioned_p (scratch
, outval
))
7331 scratch
= base_plus
;
7336 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7338 /* Be conservative and copy OUTVAL into the scratch now,
7339 this should only be necessary if outval is a subreg
7340 of something larger than a word. */
7341 /* XXX Might this clobber base? I can't see how it can,
7342 since scratch is known to overlap with OUTVAL, and
7343 must be wider than a word. */
7344 emit_insn (gen_movhi (scratch_hi
, outval
));
7345 outval
= scratch_hi
;
7349 emit_set_insn (base_plus
, base
);
7352 else if (GET_CODE (base
) == PLUS
)
7354 /* The addend must be CONST_INT, or we would have dealt with it above. */
7355 HOST_WIDE_INT hi
, lo
;
7357 offset
+= INTVAL (XEXP (base
, 1));
7358 base
= XEXP (base
, 0);
7360 /* Rework the address into a legal sequence of insns. */
7361 /* Valid range for lo is -4095 -> 4095 */
7364 : -((-offset
) & 0xfff));
7366 /* Corner case, if lo is the max offset then we would be out of range
7367 once we have added the additional 1 below, so bump the msb into the
7368 pre-loading insn(s). */
7372 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
7373 ^ (HOST_WIDE_INT
) 0x80000000)
7374 - (HOST_WIDE_INT
) 0x80000000);
7376 gcc_assert (hi
+ lo
== offset
);
7380 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
7382 /* Be careful not to destroy OUTVAL. */
7383 if (reg_overlap_mentioned_p (base_plus
, outval
))
7385 /* Updating base_plus might destroy outval, see if we
7386 can swap the scratch and base_plus. */
7387 if (!reg_overlap_mentioned_p (scratch
, outval
))
7390 scratch
= base_plus
;
7395 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
7397 /* Be conservative and copy outval into scratch now,
7398 this should only be necessary if outval is a
7399 subreg of something larger than a word. */
7400 /* XXX Might this clobber base? I can't see how it
7401 can, since scratch is known to overlap with
7403 emit_insn (gen_movhi (scratch_hi
, outval
));
7404 outval
= scratch_hi
;
7408 /* Get the base address; addsi3 knows how to handle constants
7409 that require more than one insn. */
7410 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
7416 if (BYTES_BIG_ENDIAN
)
7418 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7419 plus_constant (base
, offset
+ 1)),
7420 gen_lowpart (QImode
, outval
)));
7421 emit_insn (gen_lshrsi3 (scratch
,
7422 gen_rtx_SUBREG (SImode
, outval
, 0),
7424 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7425 gen_lowpart (QImode
, scratch
)));
7429 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
7430 gen_lowpart (QImode
, outval
)));
7431 emit_insn (gen_lshrsi3 (scratch
,
7432 gen_rtx_SUBREG (SImode
, outval
, 0),
7434 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
7435 plus_constant (base
, offset
+ 1)),
7436 gen_lowpart (QImode
, scratch
)));
7440 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7441 (padded to the size of a word) should be passed in a register. */
7444 arm_must_pass_in_stack (enum machine_mode mode
, tree type
)
7446 if (TARGET_AAPCS_BASED
)
7447 return must_pass_in_stack_var_size (mode
, type
);
7449 return must_pass_in_stack_var_size_or_pad (mode
, type
);
7453 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7454 Return true if an argument passed on the stack should be padded upwards,
7455 i.e. if the least-significant byte has useful data.
7456 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7457 aggregate types are placed in the lowest memory address. */
7460 arm_pad_arg_upward (enum machine_mode mode
, tree type
)
7462 if (!TARGET_AAPCS_BASED
)
7463 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
7465 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
7472 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7473 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7474 byte of the register has useful data, and return the opposite if the
7475 most significant byte does.
7476 For AAPCS, small aggregates and small complex types are always padded
7480 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
7481 tree type
, int first ATTRIBUTE_UNUSED
)
7483 if (TARGET_AAPCS_BASED
7485 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
7486 && int_size_in_bytes (type
) <= 4)
7489 /* Otherwise, use default padding. */
7490 return !BYTES_BIG_ENDIAN
;
7494 /* Print a symbolic form of X to the debug file, F. */
7496 arm_print_value (FILE *f
, rtx x
)
7498 switch (GET_CODE (x
))
7501 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
7505 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
7513 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
7515 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
7516 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
7524 fprintf (f
, "\"%s\"", XSTR (x
, 0));
7528 fprintf (f
, "`%s'", XSTR (x
, 0));
7532 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
7536 arm_print_value (f
, XEXP (x
, 0));
7540 arm_print_value (f
, XEXP (x
, 0));
7542 arm_print_value (f
, XEXP (x
, 1));
7550 fprintf (f
, "????");
7555 /* Routines for manipulation of the constant pool. */
7557 /* Arm instructions cannot load a large constant directly into a
7558 register; they have to come from a pc relative load. The constant
7559 must therefore be placed in the addressable range of the pc
7560 relative load. Depending on the precise pc relative load
7561 instruction the range is somewhere between 256 bytes and 4k. This
7562 means that we often have to dump a constant inside a function, and
7563 generate code to branch around it.
7565 It is important to minimize this, since the branches will slow
7566 things down and make the code larger.
7568 Normally we can hide the table after an existing unconditional
7569 branch so that there is no interruption of the flow, but in the
7570 worst case the code looks like this:
7588 We fix this by performing a scan after scheduling, which notices
7589 which instructions need to have their operands fetched from the
7590 constant table and builds the table.
7592 The algorithm starts by building a table of all the constants that
7593 need fixing up and all the natural barriers in the function (places
7594 where a constant table can be dropped without breaking the flow).
7595 For each fixup we note how far the pc-relative replacement will be
7596 able to reach and the offset of the instruction into the function.
7598 Having built the table we then group the fixes together to form
7599 tables that are as large as possible (subject to addressing
7600 constraints) and emit each table of constants after the last
7601 barrier that is within range of all the instructions in the group.
7602 If a group does not contain a barrier, then we forcibly create one
7603 by inserting a jump instruction into the flow. Once the table has
7604 been inserted, the insns are then modified to reference the
7605 relevant entry in the pool.
7607 Possible enhancements to the algorithm (not implemented) are:
7609 1) For some processors and object formats, there may be benefit in
7610 aligning the pools to the start of cache lines; this alignment
7611 would need to be taken into account when calculating addressability
7614 /* These typedefs are located at the start of this file, so that
7615 they can be used in the prototypes there. This comment is to
7616 remind readers of that fact so that the following structures
7617 can be understood more easily.
7619 typedef struct minipool_node Mnode;
7620 typedef struct minipool_fixup Mfix; */
7622 struct minipool_node
7624 /* Doubly linked chain of entries. */
7627 /* The maximum offset into the code that this entry can be placed. While
7628 pushing fixes for forward references, all entries are sorted in order
7629 of increasing max_address. */
7630 HOST_WIDE_INT max_address
;
7631 /* Similarly for an entry inserted for a backwards ref. */
7632 HOST_WIDE_INT min_address
;
7633 /* The number of fixes referencing this entry. This can become zero
7634 if we "unpush" an entry. In this case we ignore the entry when we
7635 come to emit the code. */
7637 /* The offset from the start of the minipool. */
7638 HOST_WIDE_INT offset
;
7639 /* The value in table. */
7641 /* The mode of value. */
7642 enum machine_mode mode
;
7643 /* The size of the value. With iWMMXt enabled
7644 sizes > 4 also imply an alignment of 8-bytes. */
7648 struct minipool_fixup
7652 HOST_WIDE_INT address
;
7654 enum machine_mode mode
;
7658 HOST_WIDE_INT forwards
;
7659 HOST_WIDE_INT backwards
;
7662 /* Fixes less than a word need padding out to a word boundary. */
7663 #define MINIPOOL_FIX_SIZE(mode) \
7664 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7666 static Mnode
* minipool_vector_head
;
7667 static Mnode
* minipool_vector_tail
;
7668 static rtx minipool_vector_label
;
7669 static int minipool_pad
;
7671 /* The linked list of all minipool fixes required for this function. */
7672 Mfix
* minipool_fix_head
;
7673 Mfix
* minipool_fix_tail
;
7674 /* The fix entry for the current minipool, once it has been placed. */
7675 Mfix
* minipool_barrier
;
7677 /* Determines if INSN is the start of a jump table. Returns the end
7678 of the TABLE or NULL_RTX. */
7680 is_jump_table (rtx insn
)
7684 if (GET_CODE (insn
) == JUMP_INSN
7685 && JUMP_LABEL (insn
) != NULL
7686 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
7687 == next_real_insn (insn
))
7689 && GET_CODE (table
) == JUMP_INSN
7690 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
7691 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
7697 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7698 #define JUMP_TABLES_IN_TEXT_SECTION 0
7701 static HOST_WIDE_INT
7702 get_jump_table_size (rtx insn
)
7704 /* ADDR_VECs only take room if read-only data does into the text
7706 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
7708 rtx body
= PATTERN (insn
);
7709 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
7711 HOST_WIDE_INT modesize
;
7713 modesize
= GET_MODE_SIZE (GET_MODE (body
));
7714 size
= modesize
* XVECLEN (body
, elt
);
7718 /* Round up size of TBB table to a halfword boundary. */
7719 size
= (size
+ 1) & ~(HOST_WIDE_INT
)1;
7722 /* No padding necessary for TBH. */
7725 /* Add two bytes for alignment on Thumb. */
7738 /* Move a minipool fix MP from its current location to before MAX_MP.
7739 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7740 constraints may need updating. */
7742 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
7743 HOST_WIDE_INT max_address
)
7745 /* The code below assumes these are different. */
7746 gcc_assert (mp
!= max_mp
);
7750 if (max_address
< mp
->max_address
)
7751 mp
->max_address
= max_address
;
7755 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7756 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7758 mp
->max_address
= max_address
;
7760 /* Unlink MP from its current position. Since max_mp is non-null,
7761 mp->prev must be non-null. */
7762 mp
->prev
->next
= mp
->next
;
7763 if (mp
->next
!= NULL
)
7764 mp
->next
->prev
= mp
->prev
;
7766 minipool_vector_tail
= mp
->prev
;
7768 /* Re-insert it before MAX_MP. */
7770 mp
->prev
= max_mp
->prev
;
7773 if (mp
->prev
!= NULL
)
7774 mp
->prev
->next
= mp
;
7776 minipool_vector_head
= mp
;
7779 /* Save the new entry. */
7782 /* Scan over the preceding entries and adjust their addresses as
7784 while (mp
->prev
!= NULL
7785 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7787 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7794 /* Add a constant to the minipool for a forward reference. Returns the
7795 node added or NULL if the constant will not fit in this pool. */
7797 add_minipool_forward_ref (Mfix
*fix
)
7799 /* If set, max_mp is the first pool_entry that has a lower
7800 constraint than the one we are trying to add. */
7801 Mnode
* max_mp
= NULL
;
7802 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
7805 /* If the minipool starts before the end of FIX->INSN then this FIX
7806 can not be placed into the current pool. Furthermore, adding the
7807 new constant pool entry may cause the pool to start FIX_SIZE bytes
7809 if (minipool_vector_head
&&
7810 (fix
->address
+ get_attr_length (fix
->insn
)
7811 >= minipool_vector_head
->max_address
- fix
->fix_size
))
7814 /* Scan the pool to see if a constant with the same value has
7815 already been added. While we are doing this, also note the
7816 location where we must insert the constant if it doesn't already
7818 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7820 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7821 && fix
->mode
== mp
->mode
7822 && (GET_CODE (fix
->value
) != CODE_LABEL
7823 || (CODE_LABEL_NUMBER (fix
->value
)
7824 == CODE_LABEL_NUMBER (mp
->value
)))
7825 && rtx_equal_p (fix
->value
, mp
->value
))
7827 /* More than one fix references this entry. */
7829 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7832 /* Note the insertion point if necessary. */
7834 && mp
->max_address
> max_address
)
7837 /* If we are inserting an 8-bytes aligned quantity and
7838 we have not already found an insertion point, then
7839 make sure that all such 8-byte aligned quantities are
7840 placed at the start of the pool. */
7841 if (ARM_DOUBLEWORD_ALIGN
7843 && fix
->fix_size
== 8
7844 && mp
->fix_size
!= 8)
7847 max_address
= mp
->max_address
;
7851 /* The value is not currently in the minipool, so we need to create
7852 a new entry for it. If MAX_MP is NULL, the entry will be put on
7853 the end of the list since the placement is less constrained than
7854 any existing entry. Otherwise, we insert the new fix before
7855 MAX_MP and, if necessary, adjust the constraints on the other
7858 mp
->fix_size
= fix
->fix_size
;
7859 mp
->mode
= fix
->mode
;
7860 mp
->value
= fix
->value
;
7862 /* Not yet required for a backwards ref. */
7863 mp
->min_address
= -65536;
7867 mp
->max_address
= max_address
;
7869 mp
->prev
= minipool_vector_tail
;
7871 if (mp
->prev
== NULL
)
7873 minipool_vector_head
= mp
;
7874 minipool_vector_label
= gen_label_rtx ();
7877 mp
->prev
->next
= mp
;
7879 minipool_vector_tail
= mp
;
7883 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7884 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7886 mp
->max_address
= max_address
;
7889 mp
->prev
= max_mp
->prev
;
7891 if (mp
->prev
!= NULL
)
7892 mp
->prev
->next
= mp
;
7894 minipool_vector_head
= mp
;
7897 /* Save the new entry. */
7900 /* Scan over the preceding entries and adjust their addresses as
7902 while (mp
->prev
!= NULL
7903 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7905 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7913 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7914 HOST_WIDE_INT min_address
)
7916 HOST_WIDE_INT offset
;
7918 /* The code below assumes these are different. */
7919 gcc_assert (mp
!= min_mp
);
7923 if (min_address
> mp
->min_address
)
7924 mp
->min_address
= min_address
;
7928 /* We will adjust this below if it is too loose. */
7929 mp
->min_address
= min_address
;
7931 /* Unlink MP from its current position. Since min_mp is non-null,
7932 mp->next must be non-null. */
7933 mp
->next
->prev
= mp
->prev
;
7934 if (mp
->prev
!= NULL
)
7935 mp
->prev
->next
= mp
->next
;
7937 minipool_vector_head
= mp
->next
;
7939 /* Reinsert it after MIN_MP. */
7941 mp
->next
= min_mp
->next
;
7943 if (mp
->next
!= NULL
)
7944 mp
->next
->prev
= mp
;
7946 minipool_vector_tail
= mp
;
7952 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7954 mp
->offset
= offset
;
7955 if (mp
->refcount
> 0)
7956 offset
+= mp
->fix_size
;
7958 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7959 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7965 /* Add a constant to the minipool for a backward reference. Returns the
7966 node added or NULL if the constant will not fit in this pool.
7968 Note that the code for insertion for a backwards reference can be
7969 somewhat confusing because the calculated offsets for each fix do
7970 not take into account the size of the pool (which is still under
7973 add_minipool_backward_ref (Mfix
*fix
)
7975 /* If set, min_mp is the last pool_entry that has a lower constraint
7976 than the one we are trying to add. */
7977 Mnode
*min_mp
= NULL
;
7978 /* This can be negative, since it is only a constraint. */
7979 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7982 /* If we can't reach the current pool from this insn, or if we can't
7983 insert this entry at the end of the pool without pushing other
7984 fixes out of range, then we don't try. This ensures that we
7985 can't fail later on. */
7986 if (min_address
>= minipool_barrier
->address
7987 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7988 >= minipool_barrier
->address
))
7991 /* Scan the pool to see if a constant with the same value has
7992 already been added. While we are doing this, also note the
7993 location where we must insert the constant if it doesn't already
7995 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7997 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7998 && fix
->mode
== mp
->mode
7999 && (GET_CODE (fix
->value
) != CODE_LABEL
8000 || (CODE_LABEL_NUMBER (fix
->value
)
8001 == CODE_LABEL_NUMBER (mp
->value
)))
8002 && rtx_equal_p (fix
->value
, mp
->value
)
8003 /* Check that there is enough slack to move this entry to the
8004 end of the table (this is conservative). */
8006 > (minipool_barrier
->address
8007 + minipool_vector_tail
->offset
8008 + minipool_vector_tail
->fix_size
)))
8011 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
8015 mp
->min_address
+= fix
->fix_size
;
8018 /* Note the insertion point if necessary. */
8019 if (mp
->min_address
< min_address
)
8021 /* For now, we do not allow the insertion of 8-byte alignment
8022 requiring nodes anywhere but at the start of the pool. */
8023 if (ARM_DOUBLEWORD_ALIGN
8024 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
8029 else if (mp
->max_address
8030 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
8032 /* Inserting before this entry would push the fix beyond
8033 its maximum address (which can happen if we have
8034 re-located a forwards fix); force the new fix to come
8037 min_address
= mp
->min_address
+ fix
->fix_size
;
8039 /* If we are inserting an 8-bytes aligned quantity and
8040 we have not already found an insertion point, then
8041 make sure that all such 8-byte aligned quantities are
8042 placed at the start of the pool. */
8043 else if (ARM_DOUBLEWORD_ALIGN
8045 && fix
->fix_size
== 8
8046 && mp
->fix_size
< 8)
8049 min_address
= mp
->min_address
+ fix
->fix_size
;
8054 /* We need to create a new entry. */
8056 mp
->fix_size
= fix
->fix_size
;
8057 mp
->mode
= fix
->mode
;
8058 mp
->value
= fix
->value
;
8060 mp
->max_address
= minipool_barrier
->address
+ 65536;
8062 mp
->min_address
= min_address
;
8067 mp
->next
= minipool_vector_head
;
8069 if (mp
->next
== NULL
)
8071 minipool_vector_tail
= mp
;
8072 minipool_vector_label
= gen_label_rtx ();
8075 mp
->next
->prev
= mp
;
8077 minipool_vector_head
= mp
;
8081 mp
->next
= min_mp
->next
;
8085 if (mp
->next
!= NULL
)
8086 mp
->next
->prev
= mp
;
8088 minipool_vector_tail
= mp
;
8091 /* Save the new entry. */
8099 /* Scan over the following entries and adjust their offsets. */
8100 while (mp
->next
!= NULL
)
8102 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
8103 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
8106 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
8108 mp
->next
->offset
= mp
->offset
;
8117 assign_minipool_offsets (Mfix
*barrier
)
8119 HOST_WIDE_INT offset
= 0;
8122 minipool_barrier
= barrier
;
8124 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
8126 mp
->offset
= offset
;
8128 if (mp
->refcount
> 0)
8129 offset
+= mp
->fix_size
;
8133 /* Output the literal table */
8135 dump_minipool (rtx scan
)
8141 if (ARM_DOUBLEWORD_ALIGN
)
8142 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
8143 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
8151 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8152 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
8154 scan
= emit_label_after (gen_label_rtx (), scan
);
8155 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
8156 scan
= emit_label_after (minipool_vector_label
, scan
);
8158 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
8160 if (mp
->refcount
> 0)
8165 ";; Offset %u, min %ld, max %ld ",
8166 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
8167 (unsigned long) mp
->max_address
);
8168 arm_print_value (dump_file
, mp
->value
);
8169 fputc ('\n', dump_file
);
8172 switch (mp
->fix_size
)
8174 #ifdef HAVE_consttable_1
8176 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
8180 #ifdef HAVE_consttable_2
8182 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
8186 #ifdef HAVE_consttable_4
8188 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
8192 #ifdef HAVE_consttable_8
8194 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
8207 minipool_vector_head
= minipool_vector_tail
= NULL
;
8208 scan
= emit_insn_after (gen_consttable_end (), scan
);
8209 scan
= emit_barrier_after (scan
);
8212 /* Return the cost of forcibly inserting a barrier after INSN. */
8214 arm_barrier_cost (rtx insn
)
8216 /* Basing the location of the pool on the loop depth is preferable,
8217 but at the moment, the basic block information seems to be
8218 corrupt by this stage of the compilation. */
8220 rtx next
= next_nonnote_insn (insn
);
8222 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
8225 switch (GET_CODE (insn
))
8228 /* It will always be better to place the table before the label, rather
8237 return base_cost
- 10;
8240 return base_cost
+ 10;
8244 /* Find the best place in the insn stream in the range
8245 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8246 Create the barrier by inserting a jump and add a new fix entry for
8249 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
8251 HOST_WIDE_INT count
= 0;
8253 rtx from
= fix
->insn
;
8254 /* The instruction after which we will insert the jump. */
8255 rtx selected
= NULL
;
8257 /* The address at which the jump instruction will be placed. */
8258 HOST_WIDE_INT selected_address
;
8260 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
8261 rtx label
= gen_label_rtx ();
8263 selected_cost
= arm_barrier_cost (from
);
8264 selected_address
= fix
->address
;
8266 while (from
&& count
< max_count
)
8271 /* This code shouldn't have been called if there was a natural barrier
8273 gcc_assert (GET_CODE (from
) != BARRIER
);
8275 /* Count the length of this insn. */
8276 count
+= get_attr_length (from
);
8278 /* If there is a jump table, add its length. */
8279 tmp
= is_jump_table (from
);
8282 count
+= get_jump_table_size (tmp
);
8284 /* Jump tables aren't in a basic block, so base the cost on
8285 the dispatch insn. If we select this location, we will
8286 still put the pool after the table. */
8287 new_cost
= arm_barrier_cost (from
);
8289 if (count
< max_count
8290 && (!selected
|| new_cost
<= selected_cost
))
8293 selected_cost
= new_cost
;
8294 selected_address
= fix
->address
+ count
;
8297 /* Continue after the dispatch table. */
8298 from
= NEXT_INSN (tmp
);
8302 new_cost
= arm_barrier_cost (from
);
8304 if (count
< max_count
8305 && (!selected
|| new_cost
<= selected_cost
))
8308 selected_cost
= new_cost
;
8309 selected_address
= fix
->address
+ count
;
8312 from
= NEXT_INSN (from
);
8315 /* Make sure that we found a place to insert the jump. */
8316 gcc_assert (selected
);
8318 /* Create a new JUMP_INSN that branches around a barrier. */
8319 from
= emit_jump_insn_after (gen_jump (label
), selected
);
8320 JUMP_LABEL (from
) = label
;
8321 barrier
= emit_barrier_after (from
);
8322 emit_label_after (label
, barrier
);
8324 /* Create a minipool barrier entry for the new barrier. */
8325 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
8326 new_fix
->insn
= barrier
;
8327 new_fix
->address
= selected_address
;
8328 new_fix
->next
= fix
->next
;
8329 fix
->next
= new_fix
;
8334 /* Record that there is a natural barrier in the insn stream at
8337 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
8339 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
8342 fix
->address
= address
;
8345 if (minipool_fix_head
!= NULL
)
8346 minipool_fix_tail
->next
= fix
;
8348 minipool_fix_head
= fix
;
8350 minipool_fix_tail
= fix
;
8353 /* Record INSN, which will need fixing up to load a value from the
8354 minipool. ADDRESS is the offset of the insn since the start of the
8355 function; LOC is a pointer to the part of the insn which requires
8356 fixing; VALUE is the constant that must be loaded, which is of type
8359 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
8360 enum machine_mode mode
, rtx value
)
8362 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
8364 #ifdef AOF_ASSEMBLER
8365 /* PIC symbol references need to be converted into offsets into the
8367 /* XXX This shouldn't be done here. */
8368 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
8369 value
= aof_pic_entry (value
);
8370 #endif /* AOF_ASSEMBLER */
8373 fix
->address
= address
;
8376 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
8378 fix
->forwards
= get_attr_pool_range (insn
);
8379 fix
->backwards
= get_attr_neg_pool_range (insn
);
8380 fix
->minipool
= NULL
;
8382 /* If an insn doesn't have a range defined for it, then it isn't
8383 expecting to be reworked by this code. Better to stop now than
8384 to generate duff assembly code. */
8385 gcc_assert (fix
->forwards
|| fix
->backwards
);
8387 /* If an entry requires 8-byte alignment then assume all constant pools
8388 require 4 bytes of padding. Trying to do this later on a per-pool
8389 basis is awkward because existing pool entries have to be modified. */
8390 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
8396 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8397 GET_MODE_NAME (mode
),
8398 INSN_UID (insn
), (unsigned long) address
,
8399 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
8400 arm_print_value (dump_file
, fix
->value
);
8401 fprintf (dump_file
, "\n");
8404 /* Add it to the chain of fixes. */
8407 if (minipool_fix_head
!= NULL
)
8408 minipool_fix_tail
->next
= fix
;
8410 minipool_fix_head
= fix
;
8412 minipool_fix_tail
= fix
;
8415 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8416 Returns the number of insns needed, or 99 if we don't know how to
8419 arm_const_double_inline_cost (rtx val
)
8421 rtx lowpart
, highpart
;
8422 enum machine_mode mode
;
8424 mode
= GET_MODE (val
);
8426 if (mode
== VOIDmode
)
8429 gcc_assert (GET_MODE_SIZE (mode
) == 8);
8431 lowpart
= gen_lowpart (SImode
, val
);
8432 highpart
= gen_highpart_mode (SImode
, mode
, val
);
8434 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
8435 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
8437 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
8438 NULL_RTX
, NULL_RTX
, 0, 0)
8439 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
8440 NULL_RTX
, NULL_RTX
, 0, 0));
8443 /* Return true if it is worthwhile to split a 64-bit constant into two
8444 32-bit operations. This is the case if optimizing for size, or
8445 if we have load delay slots, or if one 32-bit part can be done with
8446 a single data operation. */
8448 arm_const_double_by_parts (rtx val
)
8450 enum machine_mode mode
= GET_MODE (val
);
8453 if (optimize_size
|| arm_ld_sched
)
8456 if (mode
== VOIDmode
)
8459 part
= gen_highpart_mode (SImode
, mode
, val
);
8461 gcc_assert (GET_CODE (part
) == CONST_INT
);
8463 if (const_ok_for_arm (INTVAL (part
))
8464 || const_ok_for_arm (~INTVAL (part
)))
8467 part
= gen_lowpart (SImode
, val
);
8469 gcc_assert (GET_CODE (part
) == CONST_INT
);
8471 if (const_ok_for_arm (INTVAL (part
))
8472 || const_ok_for_arm (~INTVAL (part
)))
8478 /* Scan INSN and note any of its operands that need fixing.
8479 If DO_PUSHES is false we do not actually push any of the fixups
8480 needed. The function returns TRUE if any fixups were needed/pushed.
8481 This is used by arm_memory_load_p() which needs to know about loads
8482 of constants that will be converted into minipool loads. */
8484 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
8486 bool result
= false;
8489 extract_insn (insn
);
8491 if (!constrain_operands (1))
8492 fatal_insn_not_found (insn
);
8494 if (recog_data
.n_alternatives
== 0)
8497 /* Fill in recog_op_alt with information about the constraints of
8499 preprocess_constraints ();
8501 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
8503 /* Things we need to fix can only occur in inputs. */
8504 if (recog_data
.operand_type
[opno
] != OP_IN
)
8507 /* If this alternative is a memory reference, then any mention
8508 of constants in this alternative is really to fool reload
8509 into allowing us to accept one there. We need to fix them up
8510 now so that we output the right code. */
8511 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
8513 rtx op
= recog_data
.operand
[opno
];
8515 if (CONSTANT_P (op
))
8518 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
8519 recog_data
.operand_mode
[opno
], op
);
8522 else if (GET_CODE (op
) == MEM
8523 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
8524 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
8528 rtx cop
= avoid_constant_pool_reference (op
);
8530 /* Casting the address of something to a mode narrower
8531 than a word can cause avoid_constant_pool_reference()
8532 to return the pool reference itself. That's no good to
8533 us here. Lets just hope that we can use the
8534 constant pool value directly. */
8536 cop
= get_pool_constant (XEXP (op
, 0));
8538 push_minipool_fix (insn
, address
,
8539 recog_data
.operand_loc
[opno
],
8540 recog_data
.operand_mode
[opno
], cop
);
8551 /* Gcc puts the pool in the wrong place for ARM, since we can only
8552 load addresses a limited distance around the pc. We do some
8553 special munging to move the constant pool values to the correct
8554 point in the code. */
8559 HOST_WIDE_INT address
= 0;
8562 minipool_fix_head
= minipool_fix_tail
= NULL
;
8564 /* The first insn must always be a note, or the code below won't
8565 scan it properly. */
8566 insn
= get_insns ();
8567 gcc_assert (GET_CODE (insn
) == NOTE
);
8570 /* Scan all the insns and record the operands that will need fixing. */
8571 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
8573 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8574 && (arm_cirrus_insn_p (insn
)
8575 || GET_CODE (insn
) == JUMP_INSN
8576 || arm_memory_load_p (insn
)))
8577 cirrus_reorg (insn
);
8579 if (GET_CODE (insn
) == BARRIER
)
8580 push_minipool_barrier (insn
, address
);
8581 else if (INSN_P (insn
))
8585 note_invalid_constants (insn
, address
, true);
8586 address
+= get_attr_length (insn
);
8588 /* If the insn is a vector jump, add the size of the table
8589 and skip the table. */
8590 if ((table
= is_jump_table (insn
)) != NULL
)
8592 address
+= get_jump_table_size (table
);
8598 fix
= minipool_fix_head
;
8600 /* Now scan the fixups and perform the required changes. */
8605 Mfix
* last_added_fix
;
8606 Mfix
* last_barrier
= NULL
;
8609 /* Skip any further barriers before the next fix. */
8610 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
8613 /* No more fixes. */
8617 last_added_fix
= NULL
;
8619 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
8621 if (GET_CODE (ftmp
->insn
) == BARRIER
)
8623 if (ftmp
->address
>= minipool_vector_head
->max_address
)
8626 last_barrier
= ftmp
;
8628 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
8631 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
8634 /* If we found a barrier, drop back to that; any fixes that we
8635 could have reached but come after the barrier will now go in
8636 the next mini-pool. */
8637 if (last_barrier
!= NULL
)
8639 /* Reduce the refcount for those fixes that won't go into this
8641 for (fdel
= last_barrier
->next
;
8642 fdel
&& fdel
!= ftmp
;
8645 fdel
->minipool
->refcount
--;
8646 fdel
->minipool
= NULL
;
8649 ftmp
= last_barrier
;
8653 /* ftmp is first fix that we can't fit into this pool and
8654 there no natural barriers that we could use. Insert a
8655 new barrier in the code somewhere between the previous
8656 fix and this one, and arrange to jump around it. */
8657 HOST_WIDE_INT max_address
;
8659 /* The last item on the list of fixes must be a barrier, so
8660 we can never run off the end of the list of fixes without
8661 last_barrier being set. */
8664 max_address
= minipool_vector_head
->max_address
;
8665 /* Check that there isn't another fix that is in range that
8666 we couldn't fit into this pool because the pool was
8667 already too large: we need to put the pool before such an
8668 instruction. The pool itself may come just after the
8669 fix because create_fix_barrier also allows space for a
8670 jump instruction. */
8671 if (ftmp
->address
< max_address
)
8672 max_address
= ftmp
->address
+ 1;
8674 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
8677 assign_minipool_offsets (last_barrier
);
8681 if (GET_CODE (ftmp
->insn
) != BARRIER
8682 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
8689 /* Scan over the fixes we have identified for this pool, fixing them
8690 up and adding the constants to the pool itself. */
8691 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
8692 this_fix
= this_fix
->next
)
8693 if (GET_CODE (this_fix
->insn
) != BARRIER
)
8696 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
8697 minipool_vector_label
),
8698 this_fix
->minipool
->offset
);
8699 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
8702 dump_minipool (last_barrier
->insn
);
8706 /* From now on we must synthesize any constants that we can't handle
8707 directly. This can happen if the RTL gets split during final
8708 instruction generation. */
8709 after_arm_reorg
= 1;
8711 /* Free the minipool memory. */
8712 obstack_free (&minipool_obstack
, minipool_startobj
);
8715 /* Routines to output assembly language. */
8717 /* If the rtx is the correct value then return the string of the number.
8718 In this way we can ensure that valid double constants are generated even
8719 when cross compiling. */
8721 fp_immediate_constant (rtx x
)
8726 if (!fp_consts_inited
)
8729 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8730 for (i
= 0; i
< 8; i
++)
8731 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8732 return strings_fp
[i
];
8737 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8739 fp_const_from_val (REAL_VALUE_TYPE
*r
)
8743 if (!fp_consts_inited
)
8746 for (i
= 0; i
< 8; i
++)
8747 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
8748 return strings_fp
[i
];
8753 /* Output the operands of a LDM/STM instruction to STREAM.
8754 MASK is the ARM register set mask of which only bits 0-15 are important.
8755 REG is the base register, either the frame pointer or the stack pointer,
8756 INSTR is the possibly suffixed load or store instruction.
8757 RFE is nonzero if the instruction should also copy spsr to cpsr. */
8760 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
8761 unsigned long mask
, int rfe
)
8764 bool not_first
= FALSE
;
8766 gcc_assert (!rfe
|| (mask
& (1 << PC_REGNUM
)));
8767 fputc ('\t', stream
);
8768 asm_fprintf (stream
, instr
, reg
);
8769 fputc ('{', stream
);
8771 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8772 if (mask
& (1 << i
))
8775 fprintf (stream
, ", ");
8777 asm_fprintf (stream
, "%r", i
);
8782 fprintf (stream
, "}^\n");
8784 fprintf (stream
, "}\n");
8788 /* Output a FLDMD instruction to STREAM.
8789 BASE if the register containing the address.
8790 REG and COUNT specify the register range.
8791 Extra registers may be added to avoid hardware bugs.
8793 We output FLDMD even for ARMv5 VFP implementations. Although
8794 FLDMD is technically not supported until ARMv6, it is believed
8795 that all VFP implementations support its use in this context. */
8798 vfp_output_fldmd (FILE * stream
, unsigned int base
, int reg
, int count
)
8802 /* Workaround ARM10 VFPr1 bug. */
8803 if (count
== 2 && !arm_arch6
)
8810 fputc ('\t', stream
);
8811 asm_fprintf (stream
, "fldmfdd\t%r!, {", base
);
8813 for (i
= reg
; i
< reg
+ count
; i
++)
8816 fputs (", ", stream
);
8817 asm_fprintf (stream
, "d%d", i
);
8819 fputs ("}\n", stream
);
8824 /* Output the assembly for a store multiple. */
8827 vfp_output_fstmd (rtx
* operands
)
8834 strcpy (pattern
, "fstmfdd\t%m0!, {%P1");
8835 p
= strlen (pattern
);
8837 gcc_assert (GET_CODE (operands
[1]) == REG
);
8839 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8840 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8842 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8844 strcpy (&pattern
[p
], "}");
8846 output_asm_insn (pattern
, operands
);
8851 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8852 number of bytes pushed. */
8855 vfp_emit_fstmd (int base_reg
, int count
)
8862 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8863 register pairs are stored by a store multiple insn. We avoid this
8864 by pushing an extra pair. */
8865 if (count
== 2 && !arm_arch6
)
8867 if (base_reg
== LAST_VFP_REGNUM
- 3)
8872 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8873 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8875 reg
= gen_rtx_REG (DFmode
, base_reg
);
8879 = gen_rtx_SET (VOIDmode
,
8880 gen_frame_mem (BLKmode
,
8881 gen_rtx_PRE_DEC (BLKmode
,
8882 stack_pointer_rtx
)),
8883 gen_rtx_UNSPEC (BLKmode
,
8887 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8888 plus_constant (stack_pointer_rtx
, -(count
* 8)));
8889 RTX_FRAME_RELATED_P (tmp
) = 1;
8890 XVECEXP (dwarf
, 0, 0) = tmp
;
8892 tmp
= gen_rtx_SET (VOIDmode
,
8893 gen_frame_mem (DFmode
, stack_pointer_rtx
),
8895 RTX_FRAME_RELATED_P (tmp
) = 1;
8896 XVECEXP (dwarf
, 0, 1) = tmp
;
8898 for (i
= 1; i
< count
; i
++)
8900 reg
= gen_rtx_REG (DFmode
, base_reg
);
8902 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8904 tmp
= gen_rtx_SET (VOIDmode
,
8905 gen_frame_mem (DFmode
,
8906 plus_constant (stack_pointer_rtx
,
8909 RTX_FRAME_RELATED_P (tmp
) = 1;
8910 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8913 par
= emit_insn (par
);
8914 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8916 RTX_FRAME_RELATED_P (par
) = 1;
8922 /* Output a 'call' insn. */
8924 output_call (rtx
*operands
)
8926 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
8928 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8929 if (REGNO (operands
[0]) == LR_REGNUM
)
8931 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8932 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8935 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8937 if (TARGET_INTERWORK
|| arm_arch4t
)
8938 output_asm_insn ("bx%?\t%0", operands
);
8940 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8945 /* Output a 'call' insn that is a reference in memory. */
8947 output_call_mem (rtx
*operands
)
8949 if (TARGET_INTERWORK
&& !arm_arch5
)
8951 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8952 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8953 output_asm_insn ("bx%?\t%|ip", operands
);
8955 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8957 /* LR is used in the memory address. We load the address in the
8958 first instruction. It's safe to use IP as the target of the
8959 load since the call will kill it anyway. */
8960 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8962 output_asm_insn ("blx%?\t%|ip", operands
);
8965 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8967 output_asm_insn ("bx%?\t%|ip", operands
);
8969 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8974 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8975 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8982 /* Output a move from arm registers to an fpa registers.
8983 OPERANDS[0] is an fpa register.
8984 OPERANDS[1] is the first registers of an arm register pair. */
8986 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8988 int arm_reg0
= REGNO (operands
[1]);
8991 gcc_assert (arm_reg0
!= IP_REGNUM
);
8993 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8994 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8995 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8997 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
8998 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
9003 /* Output a move from an fpa register to arm registers.
9004 OPERANDS[0] is the first registers of an arm register pair.
9005 OPERANDS[1] is an fpa register. */
9007 output_mov_long_double_arm_from_fpa (rtx
*operands
)
9009 int arm_reg0
= REGNO (operands
[0]);
9012 gcc_assert (arm_reg0
!= IP_REGNUM
);
9014 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
9015 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
9016 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
9018 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
9019 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
9023 /* Output a move from arm registers to arm registers of a long double
9024 OPERANDS[0] is the destination.
9025 OPERANDS[1] is the source. */
9027 output_mov_long_double_arm_from_arm (rtx
*operands
)
9029 /* We have to be careful here because the two might overlap. */
9030 int dest_start
= REGNO (operands
[0]);
9031 int src_start
= REGNO (operands
[1]);
9035 if (dest_start
< src_start
)
9037 for (i
= 0; i
< 3; i
++)
9039 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
9040 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
9041 output_asm_insn ("mov%?\t%0, %1", ops
);
9046 for (i
= 2; i
>= 0; i
--)
9048 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
9049 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
9050 output_asm_insn ("mov%?\t%0, %1", ops
);
9058 /* Output a move from arm registers to an fpa registers.
9059 OPERANDS[0] is an fpa register.
9060 OPERANDS[1] is the first registers of an arm register pair. */
9062 output_mov_double_fpa_from_arm (rtx
*operands
)
9064 int arm_reg0
= REGNO (operands
[1]);
9067 gcc_assert (arm_reg0
!= IP_REGNUM
);
9069 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
9070 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
9071 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops
);
9072 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
9076 /* Output a move from an fpa register to arm registers.
9077 OPERANDS[0] is the first registers of an arm register pair.
9078 OPERANDS[1] is an fpa register. */
9080 output_mov_double_arm_from_fpa (rtx
*operands
)
9082 int arm_reg0
= REGNO (operands
[0]);
9085 gcc_assert (arm_reg0
!= IP_REGNUM
);
9087 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
9088 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
9089 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
9090 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops
);
9094 /* Output a move between double words.
9095 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9096 or MEM<-REG and all MEMs must be offsettable addresses. */
9098 output_move_double (rtx
*operands
)
9100 enum rtx_code code0
= GET_CODE (operands
[0]);
9101 enum rtx_code code1
= GET_CODE (operands
[1]);
9106 int reg0
= REGNO (operands
[0]);
9108 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
9110 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
9112 switch (GET_CODE (XEXP (operands
[1], 0)))
9115 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
9119 gcc_assert (TARGET_LDRD
);
9120 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands
);
9125 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands
);
9127 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands
);
9131 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands
);
9135 gcc_assert (TARGET_LDRD
);
9136 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands
);
9141 otherops
[0] = operands
[0];
9142 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
9143 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
9145 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
9147 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
9149 /* Registers overlap so split out the increment. */
9150 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
9151 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops
);
9155 /* IWMMXT allows offsets larger than ldrd can handle,
9156 fix these up with a pair of ldr. */
9157 if (GET_CODE (otherops
[2]) == CONST_INT
9158 && (INTVAL(otherops
[2]) <= -256
9159 || INTVAL(otherops
[2]) >= 256))
9161 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
9162 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
9163 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops
);
9166 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops
);
9171 /* IWMMXT allows offsets larger than ldrd can handle,
9172 fix these up with a pair of ldr. */
9173 if (GET_CODE (otherops
[2]) == CONST_INT
9174 && (INTVAL(otherops
[2]) <= -256
9175 || INTVAL(otherops
[2]) >= 256))
9177 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
9178 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops
);
9179 otherops
[0] = operands
[0];
9180 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
9183 /* We only allow constant increments, so this is safe. */
9184 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops
);
9190 output_asm_insn ("adr%?\t%0, %1", operands
);
9191 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands
);
9194 /* ??? This needs checking for thumb2. */
9196 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
9197 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
9199 otherops
[0] = operands
[0];
9200 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
9201 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
9203 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
9205 if (GET_CODE (otherops
[2]) == CONST_INT
)
9207 switch ((int) INTVAL (otherops
[2]))
9210 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops
);
9215 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops
);
9220 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops
);
9225 && (GET_CODE (otherops
[2]) == REG
9226 || (GET_CODE (otherops
[2]) == CONST_INT
9227 && INTVAL (otherops
[2]) > -256
9228 && INTVAL (otherops
[2]) < 256)))
9230 if (reg_overlap_mentioned_p (otherops
[0],
9233 /* Swap base and index registers over to
9234 avoid a conflict. */
9235 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
9236 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
9238 /* If both registers conflict, it will usually
9239 have been fixed by a splitter. */
9240 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
9242 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
9243 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9247 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops
);
9251 if (GET_CODE (otherops
[2]) == CONST_INT
)
9253 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
9254 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
9256 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
9259 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
9262 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
9264 return "ldm%(ia%)\t%0, %M0";
9268 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
9269 /* Take care of overlapping base/data reg. */
9270 if (reg_mentioned_p (operands
[0], operands
[1]))
9272 output_asm_insn ("ldr%?\t%0, %1", otherops
);
9273 output_asm_insn ("ldr%?\t%0, %1", operands
);
9277 output_asm_insn ("ldr%?\t%0, %1", operands
);
9278 output_asm_insn ("ldr%?\t%0, %1", otherops
);
9285 /* Constraints should ensure this. */
9286 gcc_assert (code0
== MEM
&& code1
== REG
);
9287 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
9289 switch (GET_CODE (XEXP (operands
[0], 0)))
9292 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
9296 gcc_assert (TARGET_LDRD
);
9297 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands
);
9302 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands
);
9304 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands
);
9308 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands
);
9312 gcc_assert (TARGET_LDRD
);
9313 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands
);
9318 otherops
[0] = operands
[1];
9319 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
9320 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
9322 /* IWMMXT allows offsets larger than ldrd can handle,
9323 fix these up with a pair of ldr. */
9324 if (GET_CODE (otherops
[2]) == CONST_INT
9325 && (INTVAL(otherops
[2]) <= -256
9326 || INTVAL(otherops
[2]) >= 256))
9329 reg1
= gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
9330 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
9332 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
9334 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops
);
9339 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops
);
9340 otherops
[0] = operands
[1];
9341 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
9344 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
9345 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops
);
9347 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops
);
9351 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
9352 if (GET_CODE (otherops
[2]) == CONST_INT
)
9354 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
9357 output_asm_insn ("stm%(db%)\t%m0, %M1", operands
);
9363 output_asm_insn ("stm%(da%)\t%m0, %M1", operands
);
9369 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands
);
9374 && (GET_CODE (otherops
[2]) == REG
9375 || (GET_CODE (otherops
[2]) == CONST_INT
9376 && INTVAL (otherops
[2]) > -256
9377 && INTVAL (otherops
[2]) < 256)))
9379 otherops
[0] = operands
[1];
9380 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
9381 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops
);
9387 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
9388 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
9389 output_asm_insn ("str%?\t%1, %0", operands
);
9390 output_asm_insn ("str%?\t%1, %0", otherops
);
9397 /* Output a VFP load or store instruction. */
9400 output_move_vfp (rtx
*operands
)
9402 rtx reg
, mem
, addr
, ops
[2];
9403 int load
= REG_P (operands
[0]);
9404 int dp
= GET_MODE_SIZE (GET_MODE (operands
[0])) == 8;
9405 int integer_p
= GET_MODE_CLASS (GET_MODE (operands
[0])) == MODE_INT
;
9406 const char *template;
9409 reg
= operands
[!load
];
9410 mem
= operands
[load
];
9412 gcc_assert (REG_P (reg
));
9413 gcc_assert (IS_VFP_REGNUM (REGNO (reg
)));
9414 gcc_assert (GET_MODE (reg
) == SFmode
9415 || GET_MODE (reg
) == DFmode
9416 || GET_MODE (reg
) == SImode
9417 || GET_MODE (reg
) == DImode
);
9418 gcc_assert (MEM_P (mem
));
9420 addr
= XEXP (mem
, 0);
9422 switch (GET_CODE (addr
))
9425 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9426 ops
[0] = XEXP (addr
, 0);
9431 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9432 ops
[0] = XEXP (addr
, 0);
9437 template = "f%s%c%%?\t%%%s0, %%1%s";
9443 sprintf (buff
, template,
9447 integer_p
? "\t%@ int" : "");
9448 output_asm_insn (buff
, ops
);
9453 /* Output an ADD r, s, #n where n may be too big for one instruction.
9454 If adding zero to one register, output nothing. */
9456 output_add_immediate (rtx
*operands
)
9458 HOST_WIDE_INT n
= INTVAL (operands
[2]);
9460 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
9463 output_multi_immediate (operands
,
9464 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9467 output_multi_immediate (operands
,
9468 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9475 /* Output a multiple immediate operation.
9476 OPERANDS is the vector of operands referred to in the output patterns.
9477 INSTR1 is the output pattern to use for the first constant.
9478 INSTR2 is the output pattern to use for subsequent constants.
9479 IMMED_OP is the index of the constant slot in OPERANDS.
9480 N is the constant value. */
9482 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
9483 int immed_op
, HOST_WIDE_INT n
)
9485 #if HOST_BITS_PER_WIDE_INT > 32
9491 /* Quick and easy output. */
9492 operands
[immed_op
] = const0_rtx
;
9493 output_asm_insn (instr1
, operands
);
9498 const char * instr
= instr1
;
9500 /* Note that n is never zero here (which would give no output). */
9501 for (i
= 0; i
< 32; i
+= 2)
9505 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
9506 output_asm_insn (instr
, operands
);
9516 /* Return the name of a shifter operation. */
9518 arm_shift_nmem(enum rtx_code code
)
9523 return ARM_LSL_NAME
;
9539 /* Return the appropriate ARM instruction for the operation code.
9540 The returned result should not be overwritten. OP is the rtx of the
9541 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9544 arithmetic_instr (rtx op
, int shift_first_arg
)
9546 switch (GET_CODE (op
))
9552 return shift_first_arg
? "rsb" : "sub";
9567 return arm_shift_nmem(GET_CODE(op
));
9574 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9575 for the operation code. The returned result should not be overwritten.
9576 OP is the rtx code of the shift.
9577 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9580 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
9583 enum rtx_code code
= GET_CODE (op
);
9585 switch (GET_CODE (XEXP (op
, 1)))
9593 *amountp
= INTVAL (XEXP (op
, 1));
9603 gcc_assert (*amountp
!= -1);
9604 *amountp
= 32 - *amountp
;
9613 mnem
= arm_shift_nmem(code
);
9617 /* We never have to worry about the amount being other than a
9618 power of 2, since this case can never be reloaded from a reg. */
9619 gcc_assert (*amountp
!= -1);
9620 *amountp
= int_log2 (*amountp
);
9621 return ARM_LSL_NAME
;
9629 /* This is not 100% correct, but follows from the desire to merge
9630 multiplication by a power of 2 with the recognizer for a
9631 shift. >=32 is not a valid shift for "lsl", so we must try and
9632 output a shift that produces the correct arithmetical result.
9633 Using lsr #32 is identical except for the fact that the carry bit
9634 is not set correctly if we set the flags; but we never use the
9635 carry bit from such an operation, so we can ignore that. */
9636 if (code
== ROTATERT
)
9637 /* Rotate is just modulo 32. */
9639 else if (*amountp
!= (*amountp
& 31))
9646 /* Shifts of 0 are no-ops. */
9654 /* Obtain the shift from the POWER of two. */
9656 static HOST_WIDE_INT
9657 int_log2 (HOST_WIDE_INT power
)
9659 HOST_WIDE_INT shift
= 0;
9661 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
9663 gcc_assert (shift
<= 31);
9670 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9671 because /bin/as is horribly restrictive. The judgement about
9672 whether or not each character is 'printable' (and can be output as
9673 is) or not (and must be printed with an octal escape) must be made
9674 with reference to the *host* character set -- the situation is
9675 similar to that discussed in the comments above pp_c_char in
9676 c-pretty-print.c. */
9678 #define MAX_ASCII_LEN 51
9681 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
9686 fputs ("\t.ascii\t\"", stream
);
9688 for (i
= 0; i
< len
; i
++)
9692 if (len_so_far
>= MAX_ASCII_LEN
)
9694 fputs ("\"\n\t.ascii\t\"", stream
);
9700 if (c
== '\\' || c
== '\"')
9702 putc ('\\', stream
);
9710 fprintf (stream
, "\\%03o", c
);
9715 fputs ("\"\n", stream
);
9718 /* Compute the register save mask for registers 0 through 12
9719 inclusive. This code is used by arm_compute_save_reg_mask. */
9721 static unsigned long
9722 arm_compute_save_reg0_reg12_mask (void)
9724 unsigned long func_type
= arm_current_func_type ();
9725 unsigned long save_reg_mask
= 0;
9728 if (IS_INTERRUPT (func_type
))
9730 unsigned int max_reg
;
9731 /* Interrupt functions must not corrupt any registers,
9732 even call clobbered ones. If this is a leaf function
9733 we can just examine the registers used by the RTL, but
9734 otherwise we have to assume that whatever function is
9735 called might clobber anything, and so we have to save
9736 all the call-clobbered registers as well. */
9737 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9738 /* FIQ handlers have registers r8 - r12 banked, so
9739 we only need to check r0 - r7, Normal ISRs only
9740 bank r14 and r15, so we must check up to r12.
9741 r13 is the stack pointer which is always preserved,
9742 so we do not need to consider it here. */
9747 for (reg
= 0; reg
<= max_reg
; reg
++)
9748 if (regs_ever_live
[reg
]
9749 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9750 save_reg_mask
|= (1 << reg
);
9752 /* Also save the pic base register if necessary. */
9754 && !TARGET_SINGLE_PIC_BASE
9755 && arm_pic_register
!= INVALID_REGNUM
9756 && current_function_uses_pic_offset_table
)
9757 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9761 /* In arm mode we handle r11 (FP) as a special case. */
9762 unsigned last_reg
= TARGET_ARM
? 10 : 11;
9764 /* In the normal case we only need to save those registers
9765 which are call saved and which are used by this function. */
9766 for (reg
= 0; reg
<= last_reg
; reg
++)
9767 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9768 save_reg_mask
|= (1 << reg
);
9770 /* Handle the frame pointer as a special case. */
9771 if (TARGET_THUMB2
&& frame_pointer_needed
)
9772 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9773 else if (! TARGET_APCS_FRAME
9774 && ! frame_pointer_needed
9775 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9776 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9777 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9779 /* If we aren't loading the PIC register,
9780 don't stack it even though it may be live. */
9782 && !TARGET_SINGLE_PIC_BASE
9783 && arm_pic_register
!= INVALID_REGNUM
9784 && (regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
]
9785 || current_function_uses_pic_offset_table
))
9786 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9788 /* The prologue will copy SP into R0, so save it. */
9789 if (IS_STACKALIGN (func_type
))
9793 /* Save registers so the exception handler can modify them. */
9794 if (current_function_calls_eh_return
)
9800 reg
= EH_RETURN_DATA_REGNO (i
);
9801 if (reg
== INVALID_REGNUM
)
9803 save_reg_mask
|= 1 << reg
;
9807 return save_reg_mask
;
9811 /* Compute a bit mask of which registers need to be
9812 saved on the stack for the current function. */
9814 static unsigned long
9815 arm_compute_save_reg_mask (void)
9817 unsigned int save_reg_mask
= 0;
9818 unsigned long func_type
= arm_current_func_type ();
9821 if (IS_NAKED (func_type
))
9822 /* This should never really happen. */
9825 /* If we are creating a stack frame, then we must save the frame pointer,
9826 IP (which will hold the old stack pointer), LR and the PC. */
9827 if (frame_pointer_needed
&& TARGET_ARM
)
9829 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9834 /* Volatile functions do not return, so there
9835 is no need to save any other registers. */
9836 if (IS_VOLATILE (func_type
))
9837 return save_reg_mask
;
9839 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9841 /* Decide if we need to save the link register.
9842 Interrupt routines have their own banked link register,
9843 so they never need to save it.
9844 Otherwise if we do not use the link register we do not need to save
9845 it. If we are pushing other registers onto the stack however, we
9846 can save an instruction in the epilogue by pushing the link register
9847 now and then popping it back into the PC. This incurs extra memory
9848 accesses though, so we only do it when optimizing for size, and only
9849 if we know that we will not need a fancy return sequence. */
9850 if (regs_ever_live
[LR_REGNUM
]
9853 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9854 && !current_function_calls_eh_return
))
9855 save_reg_mask
|= 1 << LR_REGNUM
;
9857 if (cfun
->machine
->lr_save_eliminated
)
9858 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9860 if (TARGET_REALLY_IWMMXT
9861 && ((bit_count (save_reg_mask
)
9862 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9864 /* The total number of registers that are going to be pushed
9865 onto the stack is odd. We need to ensure that the stack
9866 is 64-bit aligned before we start to save iWMMXt registers,
9867 and also before we start to create locals. (A local variable
9868 might be a double or long long which we will load/store using
9869 an iWMMXt instruction). Therefore we need to push another
9870 ARM register, so that the stack will be 64-bit aligned. We
9871 try to avoid using the arg registers (r0 -r3) as they might be
9872 used to pass values in a tail call. */
9873 for (reg
= 4; reg
<= 12; reg
++)
9874 if ((save_reg_mask
& (1 << reg
)) == 0)
9878 save_reg_mask
|= (1 << reg
);
9881 cfun
->machine
->sibcall_blocked
= 1;
9882 save_reg_mask
|= (1 << 3);
9886 /* We may need to push an additional register for use initializing the
9887 PIC base register. */
9888 if (TARGET_THUMB2
&& IS_NESTED (func_type
) && flag_pic
9889 && (save_reg_mask
& THUMB2_WORK_REGS
) == 0)
9891 reg
= thumb_find_work_register (1 << 4);
9892 if (!call_used_regs
[reg
])
9893 save_reg_mask
|= (1 << reg
);
9896 return save_reg_mask
;
9900 /* Compute a bit mask of which registers need to be
9901 saved on the stack for the current function. */
9902 static unsigned long
9903 thumb1_compute_save_reg_mask (void)
9909 for (reg
= 0; reg
< 12; reg
++)
9910 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9914 && !TARGET_SINGLE_PIC_BASE
9915 && arm_pic_register
!= INVALID_REGNUM
9916 && current_function_uses_pic_offset_table
)
9917 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9919 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9920 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
9921 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
9923 /* LR will also be pushed if any lo regs are pushed. */
9924 if (mask
& 0xff || thumb_force_lr_save ())
9925 mask
|= (1 << LR_REGNUM
);
9927 /* Make sure we have a low work register if we need one.
9928 We will need one if we are going to push a high register,
9929 but we are not currently intending to push a low register. */
9930 if ((mask
& 0xff) == 0
9931 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
9933 /* Use thumb_find_work_register to choose which register
9934 we will use. If the register is live then we will
9935 have to push it. Use LAST_LO_REGNUM as our fallback
9936 choice for the register to select. */
9937 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
9939 if (! call_used_regs
[reg
])
9947 /* Return the number of bytes required to save VFP registers. */
9949 arm_get_vfp_saved_size (void)
9956 /* Space for saved VFP registers. */
9957 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9960 for (regno
= FIRST_VFP_REGNUM
;
9961 regno
< LAST_VFP_REGNUM
;
9964 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9965 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9969 /* Workaround ARM10 VFPr1 bug. */
9970 if (count
== 2 && !arm_arch6
)
9981 if (count
== 2 && !arm_arch6
)
9990 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9991 everything bar the final return instruction. */
9993 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9995 char conditional
[10];
9998 unsigned long live_regs_mask
;
9999 unsigned long func_type
;
10000 arm_stack_offsets
*offsets
;
10002 func_type
= arm_current_func_type ();
10004 if (IS_NAKED (func_type
))
10007 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
10009 /* If this function was declared non-returning, and we have
10010 found a tail call, then we have to trust that the called
10011 function won't return. */
10016 /* Otherwise, trap an attempted return by aborting. */
10018 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
10020 assemble_external_libcall (ops
[1]);
10021 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
10027 gcc_assert (!current_function_calls_alloca
|| really_return
);
10029 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
10031 return_used_this_function
= 1;
10033 live_regs_mask
= arm_compute_save_reg_mask ();
10035 if (live_regs_mask
)
10037 const char * return_reg
;
10039 /* If we do not have any special requirements for function exit
10040 (e.g. interworking) then we can load the return address
10041 directly into the PC. Otherwise we must load it into LR. */
10043 && (IS_INTERRUPT (func_type
) || !TARGET_INTERWORK
))
10044 return_reg
= reg_names
[PC_REGNUM
];
10046 return_reg
= reg_names
[LR_REGNUM
];
10048 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
10050 /* There are three possible reasons for the IP register
10051 being saved. 1) a stack frame was created, in which case
10052 IP contains the old stack pointer, or 2) an ISR routine
10053 corrupted it, or 3) it was saved to align the stack on
10054 iWMMXt. In case 1, restore IP into SP, otherwise just
10056 if (frame_pointer_needed
)
10058 live_regs_mask
&= ~ (1 << IP_REGNUM
);
10059 live_regs_mask
|= (1 << SP_REGNUM
);
10062 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
10065 /* On some ARM architectures it is faster to use LDR rather than
10066 LDM to load a single register. On other architectures, the
10067 cost is the same. In 26 bit mode, or for exception handlers,
10068 we have to use LDM to load the PC so that the CPSR is also
10070 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
10071 if (live_regs_mask
== (1U << reg
))
10074 if (reg
<= LAST_ARM_REGNUM
10075 && (reg
!= LR_REGNUM
10077 || ! IS_INTERRUPT (func_type
)))
10079 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
10080 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
10087 /* Generate the load multiple instruction to restore the
10088 registers. Note we can get here, even if
10089 frame_pointer_needed is true, but only if sp already
10090 points to the base of the saved core registers. */
10091 if (live_regs_mask
& (1 << SP_REGNUM
))
10093 unsigned HOST_WIDE_INT stack_adjust
;
10095 offsets
= arm_get_frame_offsets ();
10096 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
10097 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
10099 if (stack_adjust
&& arm_arch5
&& TARGET_ARM
)
10100 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
10103 /* If we can't use ldmib (SA110 bug),
10104 then try to pop r3 instead. */
10106 live_regs_mask
|= 1 << 3;
10107 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
10111 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
10113 p
= instr
+ strlen (instr
);
10115 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
10116 if (live_regs_mask
& (1 << reg
))
10118 int l
= strlen (reg_names
[reg
]);
10124 memcpy (p
, ", ", 2);
10128 memcpy (p
, "%|", 2);
10129 memcpy (p
+ 2, reg_names
[reg
], l
);
10133 if (live_regs_mask
& (1 << LR_REGNUM
))
10135 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
10136 /* If returning from an interrupt, restore the CPSR. */
10137 if (IS_INTERRUPT (func_type
))
10144 output_asm_insn (instr
, & operand
);
10146 /* See if we need to generate an extra instruction to
10147 perform the actual function return. */
10149 && func_type
!= ARM_FT_INTERWORKED
10150 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
10152 /* The return has already been handled
10153 by loading the LR into the PC. */
10160 switch ((int) ARM_FUNC_TYPE (func_type
))
10164 /* ??? This is wrong for unified assembly syntax. */
10165 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
10168 case ARM_FT_INTERWORKED
:
10169 sprintf (instr
, "bx%s\t%%|lr", conditional
);
10172 case ARM_FT_EXCEPTION
:
10173 /* ??? This is wrong for unified assembly syntax. */
10174 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
10178 /* Use bx if it's available. */
10179 if (arm_arch5
|| arm_arch4t
)
10180 sprintf (instr
, "bx%s\t%%|lr", conditional
);
10182 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
10186 output_asm_insn (instr
, & operand
);
10192 /* Write the function name into the code section, directly preceding
10193 the function prologue.
10195 Code will be output similar to this:
10197 .ascii "arm_poke_function_name", 0
10200 .word 0xff000000 + (t1 - t0)
10201 arm_poke_function_name
10203 stmfd sp!, {fp, ip, lr, pc}
10206 When performing a stack backtrace, code can inspect the value
10207 of 'pc' stored at 'fp' + 0. If the trace function then looks
10208 at location pc - 12 and the top 8 bits are set, then we know
10209 that there is a function name embedded immediately preceding this
10210 location and has length ((pc[-3]) & 0xff000000).
10212 We assume that pc is declared as a pointer to an unsigned long.
10214 It is of no benefit to output the function name if we are assembling
10215 a leaf function. These function types will not contain a stack
10216 backtrace structure, therefore it is not possible to determine the
10219 arm_poke_function_name (FILE *stream
, const char *name
)
10221 unsigned long alignlength
;
10222 unsigned long length
;
10225 length
= strlen (name
) + 1;
10226 alignlength
= ROUND_UP_WORD (length
);
10228 ASM_OUTPUT_ASCII (stream
, name
, length
);
10229 ASM_OUTPUT_ALIGN (stream
, 2);
10230 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
10231 assemble_aligned_integer (UNITS_PER_WORD
, x
);
10234 /* Place some comments into the assembler stream
10235 describing the current function. */
10237 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
10239 unsigned long func_type
;
10243 thumb1_output_function_prologue (f
, frame_size
);
10247 /* Sanity check. */
10248 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
10250 func_type
= arm_current_func_type ();
10252 switch ((int) ARM_FUNC_TYPE (func_type
))
10255 case ARM_FT_NORMAL
:
10257 case ARM_FT_INTERWORKED
:
10258 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
10261 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
10264 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
10266 case ARM_FT_EXCEPTION
:
10267 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
10271 if (IS_NAKED (func_type
))
10272 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10274 if (IS_VOLATILE (func_type
))
10275 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
10277 if (IS_NESTED (func_type
))
10278 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
10279 if (IS_STACKALIGN (func_type
))
10280 asm_fprintf (f
, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10282 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10283 current_function_args_size
,
10284 current_function_pretend_args_size
, frame_size
);
10286 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10287 frame_pointer_needed
,
10288 cfun
->machine
->uses_anonymous_args
);
10290 if (cfun
->machine
->lr_save_eliminated
)
10291 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
10293 if (current_function_calls_eh_return
)
10294 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
10296 #ifdef AOF_ASSEMBLER
10298 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
10301 return_used_this_function
= 0;
10305 arm_output_epilogue (rtx sibling
)
10308 unsigned long saved_regs_mask
;
10309 unsigned long func_type
;
10310 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10311 frame that is $fp + 4 for a non-variadic function. */
10312 int floats_offset
= 0;
10314 FILE * f
= asm_out_file
;
10315 unsigned int lrm_count
= 0;
10316 int really_return
= (sibling
== NULL
);
10318 arm_stack_offsets
*offsets
;
10320 /* If we have already generated the return instruction
10321 then it is futile to generate anything else. */
10322 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
10325 func_type
= arm_current_func_type ();
10327 if (IS_NAKED (func_type
))
10328 /* Naked functions don't have epilogues. */
10331 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
10335 /* A volatile function should never return. Call abort. */
10336 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
10337 assemble_external_libcall (op
);
10338 output_asm_insn ("bl\t%a0", &op
);
10343 /* If we are throwing an exception, then we really must be doing a
10344 return, so we can't tail-call. */
10345 gcc_assert (!current_function_calls_eh_return
|| really_return
);
10347 offsets
= arm_get_frame_offsets ();
10348 saved_regs_mask
= arm_compute_save_reg_mask ();
10351 lrm_count
= bit_count (saved_regs_mask
);
10353 floats_offset
= offsets
->saved_args
;
10354 /* Compute how far away the floats will be. */
10355 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
10356 if (saved_regs_mask
& (1 << reg
))
10357 floats_offset
+= 4;
10359 if (frame_pointer_needed
&& TARGET_ARM
)
10361 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10362 int vfp_offset
= offsets
->frame
;
10364 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10366 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10367 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10369 floats_offset
+= 12;
10370 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
10371 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
10376 start_reg
= LAST_FPA_REGNUM
;
10378 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10380 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10382 floats_offset
+= 12;
10384 /* We can't unstack more than four registers at once. */
10385 if (start_reg
- reg
== 3)
10387 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
10388 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
10389 start_reg
= reg
- 1;
10394 if (reg
!= start_reg
)
10395 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
10396 reg
+ 1, start_reg
- reg
,
10397 FP_REGNUM
, floats_offset
- vfp_offset
);
10398 start_reg
= reg
- 1;
10402 /* Just in case the last register checked also needs unstacking. */
10403 if (reg
!= start_reg
)
10404 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
10405 reg
+ 1, start_reg
- reg
,
10406 FP_REGNUM
, floats_offset
- vfp_offset
);
10409 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10413 /* The fldmd insns do not have base+offset addressing
10414 modes, so we use IP to hold the address. */
10415 saved_size
= arm_get_vfp_saved_size ();
10417 if (saved_size
> 0)
10419 floats_offset
+= saved_size
;
10420 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
10421 FP_REGNUM
, floats_offset
- vfp_offset
);
10423 start_reg
= FIRST_VFP_REGNUM
;
10424 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10426 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10427 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10429 if (start_reg
!= reg
)
10430 vfp_output_fldmd (f
, IP_REGNUM
,
10431 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10432 (reg
- start_reg
) / 2);
10433 start_reg
= reg
+ 2;
10436 if (start_reg
!= reg
)
10437 vfp_output_fldmd (f
, IP_REGNUM
,
10438 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10439 (reg
- start_reg
) / 2);
10444 /* The frame pointer is guaranteed to be non-double-word aligned.
10445 This is because it is set to (old_stack_pointer - 4) and the
10446 old_stack_pointer was double word aligned. Thus the offset to
10447 the iWMMXt registers to be loaded must also be non-double-word
10448 sized, so that the resultant address *is* double-word aligned.
10449 We can ignore floats_offset since that was already included in
10450 the live_regs_mask. */
10451 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
10453 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10454 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10456 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
10457 reg
, FP_REGNUM
, lrm_count
* 4);
10462 /* saved_regs_mask should contain the IP, which at the time of stack
10463 frame generation actually contains the old stack pointer. So a
10464 quick way to unwind the stack is just pop the IP register directly
10465 into the stack pointer. */
10466 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
10467 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
10468 saved_regs_mask
|= (1 << SP_REGNUM
);
10470 /* There are two registers left in saved_regs_mask - LR and PC. We
10471 only need to restore the LR register (the return address), but to
10472 save time we can load it directly into the PC, unless we need a
10473 special function exit sequence, or we are not really returning. */
10475 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
10476 && !current_function_calls_eh_return
)
10477 /* Delete the LR from the register mask, so that the LR on
10478 the stack is loaded into the PC in the register mask. */
10479 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10481 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
10483 /* We must use SP as the base register, because SP is one of the
10484 registers being restored. If an interrupt or page fault
10485 happens in the ldm instruction, the SP might or might not
10486 have been restored. That would be bad, as then SP will no
10487 longer indicate the safe area of stack, and we can get stack
10488 corruption. Using SP as the base register means that it will
10489 be reset correctly to the original value, should an interrupt
10490 occur. If the stack pointer already points at the right
10491 place, then omit the subtraction. */
10492 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
10493 || current_function_calls_alloca
)
10494 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
10495 4 * bit_count (saved_regs_mask
));
10496 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
, 0);
10498 if (IS_INTERRUPT (func_type
))
10499 /* Interrupt handlers will have pushed the
10500 IP onto the stack, so restore it now. */
10501 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, 1 << IP_REGNUM
, 0);
10505 HOST_WIDE_INT amount
;
10507 /* Restore stack pointer if necessary. */
10508 if (frame_pointer_needed
)
10510 /* For Thumb-2 restore sp from the frame pointer.
10511 Operand restrictions mean we have to increment FP, then copy
10513 amount
= offsets
->locals_base
- offsets
->saved_regs
;
10514 operands
[0] = hard_frame_pointer_rtx
;
10518 operands
[0] = stack_pointer_rtx
;
10519 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
10524 operands
[1] = operands
[0];
10525 operands
[2] = GEN_INT (amount
);
10526 output_add_immediate (operands
);
10528 if (frame_pointer_needed
)
10529 asm_fprintf (f
, "\tmov\t%r, %r\n",
10530 SP_REGNUM
, HARD_FRAME_POINTER_REGNUM
);
10532 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10534 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
10535 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10536 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
10541 start_reg
= FIRST_FPA_REGNUM
;
10543 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
10545 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10547 if (reg
- start_reg
== 3)
10549 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
10550 start_reg
, SP_REGNUM
);
10551 start_reg
= reg
+ 1;
10556 if (reg
!= start_reg
)
10557 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
10558 start_reg
, reg
- start_reg
,
10561 start_reg
= reg
+ 1;
10565 /* Just in case the last register checked also needs unstacking. */
10566 if (reg
!= start_reg
)
10567 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
10568 start_reg
, reg
- start_reg
, SP_REGNUM
);
10571 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10573 start_reg
= FIRST_VFP_REGNUM
;
10574 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10576 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10577 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10579 if (start_reg
!= reg
)
10580 vfp_output_fldmd (f
, SP_REGNUM
,
10581 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10582 (reg
- start_reg
) / 2);
10583 start_reg
= reg
+ 2;
10586 if (start_reg
!= reg
)
10587 vfp_output_fldmd (f
, SP_REGNUM
,
10588 (start_reg
- FIRST_VFP_REGNUM
) / 2,
10589 (reg
- start_reg
) / 2);
10592 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
10593 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10594 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
10596 /* If we can, restore the LR into the PC. */
10597 if (ARM_FUNC_TYPE (func_type
) != ARM_FT_INTERWORKED
10598 && (TARGET_ARM
|| ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
10599 && !IS_STACKALIGN (func_type
)
10601 && current_function_pretend_args_size
== 0
10602 && saved_regs_mask
& (1 << LR_REGNUM
)
10603 && !current_function_calls_eh_return
)
10605 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
10606 saved_regs_mask
|= (1 << PC_REGNUM
);
10607 rfe
= IS_INTERRUPT (func_type
);
10612 /* Load the registers off the stack. If we only have one register
10613 to load use the LDR instruction - it is faster. For Thumb-2
10614 always use pop and the assembler will pick the best instruction.*/
10615 if (TARGET_ARM
&& saved_regs_mask
== (1 << LR_REGNUM
)
10616 && !IS_INTERRUPT(func_type
))
10618 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
10620 else if (saved_regs_mask
)
10622 if (saved_regs_mask
& (1 << SP_REGNUM
))
10623 /* Note - write back to the stack register is not enabled
10624 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10625 in the list of registers and if we add writeback the
10626 instruction becomes UNPREDICTABLE. */
10627 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
,
10629 else if (TARGET_ARM
)
10630 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, saved_regs_mask
,
10633 print_multi_reg (f
, "pop\t", SP_REGNUM
, saved_regs_mask
, 0);
10636 if (current_function_pretend_args_size
)
10638 /* Unwind the pre-pushed regs. */
10639 operands
[0] = operands
[1] = stack_pointer_rtx
;
10640 operands
[2] = GEN_INT (current_function_pretend_args_size
);
10641 output_add_immediate (operands
);
10645 /* We may have already restored PC directly from the stack. */
10646 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
10649 /* Stack adjustment for exception handler. */
10650 if (current_function_calls_eh_return
)
10651 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
10652 ARM_EH_STACKADJ_REGNUM
);
10654 /* Generate the return instruction. */
10655 switch ((int) ARM_FUNC_TYPE (func_type
))
10659 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
10662 case ARM_FT_EXCEPTION
:
10663 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10666 case ARM_FT_INTERWORKED
:
10667 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10671 if (IS_STACKALIGN (func_type
))
10673 /* See comment in arm_expand_prologue. */
10674 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, 0);
10676 if (arm_arch5
|| arm_arch4t
)
10677 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
10679 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
10687 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10688 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
10690 arm_stack_offsets
*offsets
;
10696 /* Emit any call-via-reg trampolines that are needed for v4t support
10697 of call_reg and call_value_reg type insns. */
10698 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
10700 rtx label
= cfun
->machine
->call_via
[regno
];
10704 switch_to_section (function_section (current_function_decl
));
10705 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10706 CODE_LABEL_NUMBER (label
));
10707 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
10711 /* ??? Probably not safe to set this here, since it assumes that a
10712 function will be emitted as assembly immediately after we generate
10713 RTL for it. This does not happen for inline functions. */
10714 return_used_this_function
= 0;
10716 else /* TARGET_32BIT */
10718 /* We need to take into account any stack-frame rounding. */
10719 offsets
= arm_get_frame_offsets ();
10721 gcc_assert (!use_return_insn (FALSE
, NULL
)
10722 || !return_used_this_function
10723 || offsets
->saved_regs
== offsets
->outgoing_args
10724 || frame_pointer_needed
);
10726 /* Reset the ARM-specific per-function variables. */
10727 after_arm_reorg
= 0;
10731 /* Generate and emit an insn that we will recognize as a push_multi.
10732 Unfortunately, since this insn does not reflect very well the actual
10733 semantics of the operation, we need to annotate the insn for the benefit
10734 of DWARF2 frame unwind information. */
10736 emit_multi_reg_push (unsigned long mask
)
10739 int num_dwarf_regs
;
10743 int dwarf_par_index
;
10746 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10747 if (mask
& (1 << i
))
10750 gcc_assert (num_regs
&& num_regs
<= 16);
10752 /* We don't record the PC in the dwarf frame information. */
10753 num_dwarf_regs
= num_regs
;
10754 if (mask
& (1 << PC_REGNUM
))
10757 /* For the body of the insn we are going to generate an UNSPEC in
10758 parallel with several USEs. This allows the insn to be recognized
10759 by the push_multi pattern in the arm.md file. The insn looks
10760 something like this:
10763 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10764 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10765 (use (reg:SI 11 fp))
10766 (use (reg:SI 12 ip))
10767 (use (reg:SI 14 lr))
10768 (use (reg:SI 15 pc))
10771 For the frame note however, we try to be more explicit and actually
10772 show each register being stored into the stack frame, plus a (single)
10773 decrement of the stack pointer. We do it this way in order to be
10774 friendly to the stack unwinding code, which only wants to see a single
10775 stack decrement per instruction. The RTL we generate for the note looks
10776 something like this:
10779 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10780 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10781 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10782 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10783 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10786 This sequence is used both by the code to support stack unwinding for
10787 exceptions handlers and the code to generate dwarf2 frame debugging. */
10789 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
10790 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
10791 dwarf_par_index
= 1;
10793 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
10795 if (mask
& (1 << i
))
10797 reg
= gen_rtx_REG (SImode
, i
);
10799 XVECEXP (par
, 0, 0)
10800 = gen_rtx_SET (VOIDmode
,
10801 gen_frame_mem (BLKmode
,
10802 gen_rtx_PRE_DEC (BLKmode
,
10803 stack_pointer_rtx
)),
10804 gen_rtx_UNSPEC (BLKmode
,
10805 gen_rtvec (1, reg
),
10806 UNSPEC_PUSH_MULT
));
10808 if (i
!= PC_REGNUM
)
10810 tmp
= gen_rtx_SET (VOIDmode
,
10811 gen_frame_mem (SImode
, stack_pointer_rtx
),
10813 RTX_FRAME_RELATED_P (tmp
) = 1;
10814 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
10822 for (j
= 1, i
++; j
< num_regs
; i
++)
10824 if (mask
& (1 << i
))
10826 reg
= gen_rtx_REG (SImode
, i
);
10828 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
10830 if (i
!= PC_REGNUM
)
10833 = gen_rtx_SET (VOIDmode
,
10834 gen_frame_mem (SImode
,
10835 plus_constant (stack_pointer_rtx
,
10838 RTX_FRAME_RELATED_P (tmp
) = 1;
10839 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10846 par
= emit_insn (par
);
10848 tmp
= gen_rtx_SET (VOIDmode
,
10850 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
10851 RTX_FRAME_RELATED_P (tmp
) = 1;
10852 XVECEXP (dwarf
, 0, 0) = tmp
;
10854 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10859 /* Calculate the size of the return value that is passed in registers. */
10861 arm_size_return_regs (void)
10863 enum machine_mode mode
;
10865 if (current_function_return_rtx
!= 0)
10866 mode
= GET_MODE (current_function_return_rtx
);
10868 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10870 return GET_MODE_SIZE (mode
);
10874 emit_sfm (int base_reg
, int count
)
10881 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10882 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10884 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10886 XVECEXP (par
, 0, 0)
10887 = gen_rtx_SET (VOIDmode
,
10888 gen_frame_mem (BLKmode
,
10889 gen_rtx_PRE_DEC (BLKmode
,
10890 stack_pointer_rtx
)),
10891 gen_rtx_UNSPEC (BLKmode
,
10892 gen_rtvec (1, reg
),
10893 UNSPEC_PUSH_MULT
));
10894 tmp
= gen_rtx_SET (VOIDmode
,
10895 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
10896 RTX_FRAME_RELATED_P (tmp
) = 1;
10897 XVECEXP (dwarf
, 0, 1) = tmp
;
10899 for (i
= 1; i
< count
; i
++)
10901 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10902 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10904 tmp
= gen_rtx_SET (VOIDmode
,
10905 gen_frame_mem (XFmode
,
10906 plus_constant (stack_pointer_rtx
,
10909 RTX_FRAME_RELATED_P (tmp
) = 1;
10910 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10913 tmp
= gen_rtx_SET (VOIDmode
,
10915 plus_constant (stack_pointer_rtx
, -12 * count
));
10917 RTX_FRAME_RELATED_P (tmp
) = 1;
10918 XVECEXP (dwarf
, 0, 0) = tmp
;
10920 par
= emit_insn (par
);
10921 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10927 /* Return true if the current function needs to save/restore LR. */
10930 thumb_force_lr_save (void)
10932 return !cfun
->machine
->lr_save_eliminated
10933 && (!leaf_function_p ()
10934 || thumb_far_jump_used_p ()
10935 || regs_ever_live
[LR_REGNUM
]);
10939 /* Compute the distance from register FROM to register TO.
10940 These can be the arg pointer (26), the soft frame pointer (25),
10941 the stack pointer (13) or the hard frame pointer (11).
10942 In thumb mode r7 is used as the soft frame pointer, if needed.
10943 Typical stack layout looks like this:
10945 old stack pointer -> | |
10948 | | saved arguments for
10949 | | vararg functions
10952 hard FP & arg pointer -> | | \
10960 soft frame pointer -> | | /
10965 locals base pointer -> | | /
10970 current stack pointer -> | | /
10973 For a given function some or all of these stack components
10974 may not be needed, giving rise to the possibility of
10975 eliminating some of the registers.
10977 The values returned by this function must reflect the behavior
10978 of arm_expand_prologue() and arm_compute_save_reg_mask().
10980 The sign of the number returned reflects the direction of stack
10981 growth, so the values are positive for all eliminations except
10982 from the soft frame pointer to the hard frame pointer.
10984 SFP may point just inside the local variables block to ensure correct
10988 /* Calculate stack offsets. These are used to calculate register elimination
10989 offsets and in prologue/epilogue code. */
10991 static arm_stack_offsets
*
10992 arm_get_frame_offsets (void)
10994 struct arm_stack_offsets
*offsets
;
10995 unsigned long func_type
;
10998 HOST_WIDE_INT frame_size
;
11000 offsets
= &cfun
->machine
->stack_offsets
;
11002 /* We need to know if we are a leaf function. Unfortunately, it
11003 is possible to be called after start_sequence has been called,
11004 which causes get_insns to return the insns for the sequence,
11005 not the function, which will cause leaf_function_p to return
11006 the incorrect result.
11008 to know about leaf functions once reload has completed, and the
11009 frame size cannot be changed after that time, so we can safely
11010 use the cached value. */
11012 if (reload_completed
)
11015 /* Initially this is the size of the local variables. It will translated
11016 into an offset once we have determined the size of preceding data. */
11017 frame_size
= ROUND_UP_WORD (get_frame_size ());
11019 leaf
= leaf_function_p ();
11021 /* Space for variadic functions. */
11022 offsets
->saved_args
= current_function_pretend_args_size
;
11024 /* In Thumb mode this is incorrect, but never used. */
11025 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
11029 unsigned int regno
;
11031 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
11033 /* We know that SP will be doubleword aligned on entry, and we must
11034 preserve that condition at any subroutine call. We also require the
11035 soft frame pointer to be doubleword aligned. */
11037 if (TARGET_REALLY_IWMMXT
)
11039 /* Check for the call-saved iWMMXt registers. */
11040 for (regno
= FIRST_IWMMXT_REGNUM
;
11041 regno
<= LAST_IWMMXT_REGNUM
;
11043 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
11047 func_type
= arm_current_func_type ();
11048 if (! IS_VOLATILE (func_type
))
11050 /* Space for saved FPA registers. */
11051 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
11052 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
11055 /* Space for saved VFP registers. */
11056 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
11057 saved
+= arm_get_vfp_saved_size ();
11060 else /* TARGET_THUMB1 */
11062 saved
= bit_count (thumb1_compute_save_reg_mask ()) * 4;
11063 if (TARGET_BACKTRACE
)
11067 /* Saved registers include the stack frame. */
11068 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
11069 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
11070 /* A leaf function does not need any stack alignment if it has nothing
11072 if (leaf
&& frame_size
== 0)
11074 offsets
->outgoing_args
= offsets
->soft_frame
;
11078 /* Ensure SFP has the correct alignment. */
11079 if (ARM_DOUBLEWORD_ALIGN
11080 && (offsets
->soft_frame
& 7))
11081 offsets
->soft_frame
+= 4;
11083 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
11084 offsets
->outgoing_args
= (offsets
->locals_base
11085 + current_function_outgoing_args_size
);
11087 if (ARM_DOUBLEWORD_ALIGN
)
11089 /* Ensure SP remains doubleword aligned. */
11090 if (offsets
->outgoing_args
& 7)
11091 offsets
->outgoing_args
+= 4;
11092 gcc_assert (!(offsets
->outgoing_args
& 7));
11099 /* Calculate the relative offsets for the different stack pointers. Positive
11100 offsets are in the direction of stack growth. */
11103 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
11105 arm_stack_offsets
*offsets
;
11107 offsets
= arm_get_frame_offsets ();
11109 /* OK, now we have enough information to compute the distances.
11110 There must be an entry in these switch tables for each pair
11111 of registers in ELIMINABLE_REGS, even if some of the entries
11112 seem to be redundant or useless. */
11115 case ARG_POINTER_REGNUM
:
11118 case THUMB_HARD_FRAME_POINTER_REGNUM
:
11121 case FRAME_POINTER_REGNUM
:
11122 /* This is the reverse of the soft frame pointer
11123 to hard frame pointer elimination below. */
11124 return offsets
->soft_frame
- offsets
->saved_args
;
11126 case ARM_HARD_FRAME_POINTER_REGNUM
:
11127 /* If there is no stack frame then the hard
11128 frame pointer and the arg pointer coincide. */
11129 if (offsets
->frame
== offsets
->saved_regs
)
11131 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11132 return (frame_pointer_needed
11133 && cfun
->static_chain_decl
!= NULL
11134 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
11136 case STACK_POINTER_REGNUM
:
11137 /* If nothing has been pushed on the stack at all
11138 then this will return -4. This *is* correct! */
11139 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
11142 gcc_unreachable ();
11144 gcc_unreachable ();
11146 case FRAME_POINTER_REGNUM
:
11149 case THUMB_HARD_FRAME_POINTER_REGNUM
:
11152 case ARM_HARD_FRAME_POINTER_REGNUM
:
11153 /* The hard frame pointer points to the top entry in the
11154 stack frame. The soft frame pointer to the bottom entry
11155 in the stack frame. If there is no stack frame at all,
11156 then they are identical. */
11158 return offsets
->frame
- offsets
->soft_frame
;
11160 case STACK_POINTER_REGNUM
:
11161 return offsets
->outgoing_args
- offsets
->soft_frame
;
11164 gcc_unreachable ();
11166 gcc_unreachable ();
11169 /* You cannot eliminate from the stack pointer.
11170 In theory you could eliminate from the hard frame
11171 pointer to the stack pointer, but this will never
11172 happen, since if a stack frame is not needed the
11173 hard frame pointer will never be used. */
11174 gcc_unreachable ();
11179 /* Emit RTL to save coprocessor registers on function entry. Returns the
11180 number of bytes pushed. */
11183 arm_save_coproc_regs(void)
11185 int saved_size
= 0;
11187 unsigned start_reg
;
11190 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
11191 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
11193 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
11194 insn
= gen_rtx_MEM (V2SImode
, insn
);
11195 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
11196 RTX_FRAME_RELATED_P (insn
) = 1;
11200 /* Save any floating point call-saved registers used by this
11202 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
11204 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
11205 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
11207 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
11208 insn
= gen_rtx_MEM (XFmode
, insn
);
11209 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
11210 RTX_FRAME_RELATED_P (insn
) = 1;
11216 start_reg
= LAST_FPA_REGNUM
;
11218 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
11220 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
11222 if (start_reg
- reg
== 3)
11224 insn
= emit_sfm (reg
, 4);
11225 RTX_FRAME_RELATED_P (insn
) = 1;
11227 start_reg
= reg
- 1;
11232 if (start_reg
!= reg
)
11234 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
11235 RTX_FRAME_RELATED_P (insn
) = 1;
11236 saved_size
+= (start_reg
- reg
) * 12;
11238 start_reg
= reg
- 1;
11242 if (start_reg
!= reg
)
11244 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
11245 saved_size
+= (start_reg
- reg
) * 12;
11246 RTX_FRAME_RELATED_P (insn
) = 1;
11249 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
11251 start_reg
= FIRST_VFP_REGNUM
;
11253 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
11255 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
11256 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
11258 if (start_reg
!= reg
)
11259 saved_size
+= vfp_emit_fstmd (start_reg
,
11260 (reg
- start_reg
) / 2);
11261 start_reg
= reg
+ 2;
11264 if (start_reg
!= reg
)
11265 saved_size
+= vfp_emit_fstmd (start_reg
,
11266 (reg
- start_reg
) / 2);
11272 /* Set the Thumb frame pointer from the stack pointer. */
11275 thumb_set_frame_pointer (arm_stack_offsets
*offsets
)
11277 HOST_WIDE_INT amount
;
11280 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
11282 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
11283 stack_pointer_rtx
, GEN_INT (amount
)));
11286 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
11287 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
11288 hard_frame_pointer_rtx
,
11289 stack_pointer_rtx
));
11290 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11291 plus_constant (stack_pointer_rtx
, amount
));
11292 RTX_FRAME_RELATED_P (dwarf
) = 1;
11293 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
11297 RTX_FRAME_RELATED_P (insn
) = 1;
11300 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11303 arm_expand_prologue (void)
11308 unsigned long live_regs_mask
;
11309 unsigned long func_type
;
11311 int saved_pretend_args
= 0;
11312 int saved_regs
= 0;
11313 unsigned HOST_WIDE_INT args_to_push
;
11314 arm_stack_offsets
*offsets
;
11316 func_type
= arm_current_func_type ();
11318 /* Naked functions don't have prologues. */
11319 if (IS_NAKED (func_type
))
11322 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11323 args_to_push
= current_function_pretend_args_size
;
11325 /* Compute which register we will have to save onto the stack. */
11326 live_regs_mask
= arm_compute_save_reg_mask ();
11328 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
11330 if (IS_STACKALIGN (func_type
))
11335 /* Handle a word-aligned stack pointer. We generate the following:
11340 <save and restore r0 in normal prologue/epilogue>
11344 The unwinder doesn't need to know about the stack realignment.
11345 Just tell it we saved SP in r0. */
11346 gcc_assert (TARGET_THUMB2
&& !arm_arch_notm
&& args_to_push
== 0);
11348 r0
= gen_rtx_REG (SImode
, 0);
11349 r1
= gen_rtx_REG (SImode
, 1);
11350 dwarf
= gen_rtx_UNSPEC (SImode
, NULL_RTVEC
, UNSPEC_STACK_ALIGN
);
11351 dwarf
= gen_rtx_SET (VOIDmode
, r0
, dwarf
);
11352 insn
= gen_movsi (r0
, stack_pointer_rtx
);
11353 RTX_FRAME_RELATED_P (insn
) = 1;
11354 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
11355 dwarf
, REG_NOTES (insn
));
11357 emit_insn (gen_andsi3 (r1
, r0
, GEN_INT (~(HOST_WIDE_INT
)7)));
11358 emit_insn (gen_movsi (stack_pointer_rtx
, r1
));
11361 if (frame_pointer_needed
&& TARGET_ARM
)
11363 if (IS_INTERRUPT (func_type
))
11365 /* Interrupt functions must not corrupt any registers.
11366 Creating a frame pointer however, corrupts the IP
11367 register, so we must push it first. */
11368 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
11370 /* Do not set RTX_FRAME_RELATED_P on this insn.
11371 The dwarf stack unwinding code only wants to see one
11372 stack decrement per function, and this is not it. If
11373 this instruction is labeled as being part of the frame
11374 creation sequence then dwarf2out_frame_debug_expr will
11375 die when it encounters the assignment of IP to FP
11376 later on, since the use of SP here establishes SP as
11377 the CFA register and not IP.
11379 Anyway this instruction is not really part of the stack
11380 frame creation although it is part of the prologue. */
11382 else if (IS_NESTED (func_type
))
11384 /* The Static chain register is the same as the IP register
11385 used as a scratch register during stack frame creation.
11386 To get around this need to find somewhere to store IP
11387 whilst the frame is being created. We try the following
11390 1. The last argument register.
11391 2. A slot on the stack above the frame. (This only
11392 works if the function is not a varargs function).
11393 3. Register r3, after pushing the argument registers
11396 Note - we only need to tell the dwarf2 backend about the SP
11397 adjustment in the second variant; the static chain register
11398 doesn't need to be unwound, as it doesn't contain a value
11399 inherited from the caller. */
11401 if (regs_ever_live
[3] == 0)
11402 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
11403 else if (args_to_push
== 0)
11407 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
11408 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
11411 /* Just tell the dwarf backend that we adjusted SP. */
11412 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11413 plus_constant (stack_pointer_rtx
,
11415 RTX_FRAME_RELATED_P (insn
) = 1;
11416 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
11417 dwarf
, REG_NOTES (insn
));
11421 /* Store the args on the stack. */
11422 if (cfun
->machine
->uses_anonymous_args
)
11423 insn
= emit_multi_reg_push
11424 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
11427 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11428 GEN_INT (- args_to_push
)));
11430 RTX_FRAME_RELATED_P (insn
) = 1;
11432 saved_pretend_args
= 1;
11433 fp_offset
= args_to_push
;
11436 /* Now reuse r3 to preserve IP. */
11437 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
11441 insn
= emit_set_insn (ip_rtx
,
11442 plus_constant (stack_pointer_rtx
, fp_offset
));
11443 RTX_FRAME_RELATED_P (insn
) = 1;
11448 /* Push the argument registers, or reserve space for them. */
11449 if (cfun
->machine
->uses_anonymous_args
)
11450 insn
= emit_multi_reg_push
11451 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
11454 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11455 GEN_INT (- args_to_push
)));
11456 RTX_FRAME_RELATED_P (insn
) = 1;
11459 /* If this is an interrupt service routine, and the link register
11460 is going to be pushed, and we are not creating a stack frame,
11461 (which would involve an extra push of IP and a pop in the epilogue)
11462 subtracting four from LR now will mean that the function return
11463 can be done with a single instruction. */
11464 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
11465 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
11466 && ! frame_pointer_needed
11469 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
11471 emit_set_insn (lr
, plus_constant (lr
, -4));
11474 if (live_regs_mask
)
11476 insn
= emit_multi_reg_push (live_regs_mask
);
11477 saved_regs
+= bit_count (live_regs_mask
) * 4;
11478 RTX_FRAME_RELATED_P (insn
) = 1;
11481 if (! IS_VOLATILE (func_type
))
11482 saved_regs
+= arm_save_coproc_regs ();
11484 if (frame_pointer_needed
&& TARGET_ARM
)
11486 /* Create the new frame pointer. */
11488 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
11489 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
11490 RTX_FRAME_RELATED_P (insn
) = 1;
11492 if (IS_NESTED (func_type
))
11494 /* Recover the static chain register. */
11495 if (regs_ever_live
[3] == 0
11496 || saved_pretend_args
)
11497 insn
= gen_rtx_REG (SImode
, 3);
11498 else /* if (current_function_pretend_args_size == 0) */
11500 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
11501 insn
= gen_frame_mem (SImode
, insn
);
11503 emit_set_insn (ip_rtx
, insn
);
11504 /* Add a USE to stop propagate_one_insn() from barfing. */
11505 emit_insn (gen_prologue_use (ip_rtx
));
11510 offsets
= arm_get_frame_offsets ();
11511 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
11513 /* This add can produce multiple insns for a large constant, so we
11514 need to get tricky. */
11515 rtx last
= get_last_insn ();
11517 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
11518 - offsets
->outgoing_args
);
11520 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
11524 last
= last
? NEXT_INSN (last
) : get_insns ();
11525 RTX_FRAME_RELATED_P (last
) = 1;
11527 while (last
!= insn
);
11529 /* If the frame pointer is needed, emit a special barrier that
11530 will prevent the scheduler from moving stores to the frame
11531 before the stack adjustment. */
11532 if (frame_pointer_needed
)
11533 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
11534 hard_frame_pointer_rtx
));
11538 if (frame_pointer_needed
&& TARGET_THUMB2
)
11539 thumb_set_frame_pointer (offsets
);
11541 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
11543 unsigned long mask
;
11545 mask
= live_regs_mask
;
11546 mask
&= THUMB2_WORK_REGS
;
11547 if (!IS_NESTED (func_type
))
11548 mask
|= (1 << IP_REGNUM
);
11549 arm_load_pic_register (mask
);
11552 /* If we are profiling, make sure no instructions are scheduled before
11553 the call to mcount. Similarly if the user has requested no
11554 scheduling in the prolog. Similarly if we want non-call exceptions
11555 using the EABI unwinder, to prevent faulting instructions from being
11556 swapped with a stack adjustment. */
11557 if (current_function_profile
|| !TARGET_SCHED_PROLOG
11558 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
11559 emit_insn (gen_blockage ());
11561 /* If the link register is being kept alive, with the return address in it,
11562 then make sure that it does not get reused by the ce2 pass. */
11563 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
11565 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
11566 cfun
->machine
->lr_save_eliminated
= 1;
11570 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11572 arm_print_condition (FILE *stream
)
11574 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
11576 /* Branch conversion is not implemented for Thumb-2. */
11579 output_operand_lossage ("predicated Thumb instruction");
11582 if (current_insn_predicate
!= NULL
)
11584 output_operand_lossage
11585 ("predicated instruction in conditional sequence");
11589 fputs (arm_condition_codes
[arm_current_cc
], stream
);
11591 else if (current_insn_predicate
)
11593 enum arm_cond_code code
;
11597 output_operand_lossage ("predicated Thumb instruction");
11601 code
= get_arm_condition_code (current_insn_predicate
);
11602 fputs (arm_condition_codes
[code
], stream
);
11607 /* If CODE is 'd', then the X is a condition operand and the instruction
11608 should only be executed if the condition is true.
11609 if CODE is 'D', then the X is a condition operand and the instruction
11610 should only be executed if the condition is false: however, if the mode
11611 of the comparison is CCFPEmode, then always execute the instruction -- we
11612 do this because in these circumstances !GE does not necessarily imply LT;
11613 in these cases the instruction pattern will take care to make sure that
11614 an instruction containing %d will follow, thereby undoing the effects of
11615 doing this instruction unconditionally.
11616 If CODE is 'N' then X is a floating point operand that must be negated
11618 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11619 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11621 arm_print_operand (FILE *stream
, rtx x
, int code
)
11626 fputs (ASM_COMMENT_START
, stream
);
11630 fputs (user_label_prefix
, stream
);
11634 fputs (REGISTER_PREFIX
, stream
);
11638 arm_print_condition (stream
);
11642 /* Nothing in unified syntax, otherwise the current condition code. */
11643 if (!TARGET_UNIFIED_ASM
)
11644 arm_print_condition (stream
);
11648 /* The current condition code in unified syntax, otherwise nothing. */
11649 if (TARGET_UNIFIED_ASM
)
11650 arm_print_condition (stream
);
11654 /* The current condition code for a condition code setting instruction.
11655 Preceded by 's' in unified syntax, otherwise followed by 's'. */
11656 if (TARGET_UNIFIED_ASM
)
11658 fputc('s', stream
);
11659 arm_print_condition (stream
);
11663 arm_print_condition (stream
);
11664 fputc('s', stream
);
11669 /* If the instruction is conditionally executed then print
11670 the current condition code, otherwise print 's'. */
11671 gcc_assert (TARGET_THUMB2
&& TARGET_UNIFIED_ASM
);
11672 if (current_insn_predicate
)
11673 arm_print_condition (stream
);
11675 fputc('s', stream
);
11681 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
11682 r
= REAL_VALUE_NEGATE (r
);
11683 fprintf (stream
, "%s", fp_const_from_val (&r
));
11688 if (GET_CODE (x
) == CONST_INT
)
11691 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
11692 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
11696 putc ('~', stream
);
11697 output_addr_const (stream
, x
);
11702 /* The low 16 bits of an immediate constant. */
11703 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL(x
) & 0xffff);
11707 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
11710 /* Truncate Cirrus shift counts. */
11712 if (GET_CODE (x
) == CONST_INT
)
11714 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
11717 arm_print_operand (stream
, x
, 0);
11721 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
11729 if (!shift_operator (x
, SImode
))
11731 output_operand_lossage ("invalid shift operand");
11735 shift
= shift_op (x
, &val
);
11739 fprintf (stream
, ", %s ", shift
);
11741 arm_print_operand (stream
, XEXP (x
, 1), 0);
11743 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
11748 /* An explanation of the 'Q', 'R' and 'H' register operands:
11750 In a pair of registers containing a DI or DF value the 'Q'
11751 operand returns the register number of the register containing
11752 the least significant part of the value. The 'R' operand returns
11753 the register number of the register containing the most
11754 significant part of the value.
11756 The 'H' operand returns the higher of the two register numbers.
11757 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11758 same as the 'Q' operand, since the most significant part of the
11759 value is held in the lower number register. The reverse is true
11760 on systems where WORDS_BIG_ENDIAN is false.
11762 The purpose of these operands is to distinguish between cases
11763 where the endian-ness of the values is important (for example
11764 when they are added together), and cases where the endian-ness
11765 is irrelevant, but the order of register operations is important.
11766 For example when loading a value from memory into a register
11767 pair, the endian-ness does not matter. Provided that the value
11768 from the lower memory address is put into the lower numbered
11769 register, and the value from the higher address is put into the
11770 higher numbered register, the load will work regardless of whether
11771 the value being loaded is big-wordian or little-wordian. The
11772 order of the two register loads can matter however, if the address
11773 of the memory location is actually held in one of the registers
11774 being overwritten by the load. */
11776 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11778 output_operand_lossage ("invalid operand for code '%c'", code
);
11782 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
11786 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11788 output_operand_lossage ("invalid operand for code '%c'", code
);
11792 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
11796 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
11798 output_operand_lossage ("invalid operand for code '%c'", code
);
11802 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
11806 asm_fprintf (stream
, "%r",
11807 GET_CODE (XEXP (x
, 0)) == REG
11808 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
11812 asm_fprintf (stream
, "{%r-%r}",
11814 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
11818 /* CONST_TRUE_RTX means always -- that's the default. */
11819 if (x
== const_true_rtx
)
11822 if (!COMPARISON_P (x
))
11824 output_operand_lossage ("invalid operand for code '%c'", code
);
11828 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
11833 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11834 want to do that. */
11835 if (x
== const_true_rtx
)
11837 output_operand_lossage ("instruction never exectued");
11840 if (!COMPARISON_P (x
))
11842 output_operand_lossage ("invalid operand for code '%c'", code
);
11846 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
11847 (get_arm_condition_code (x
))],
11851 /* Cirrus registers can be accessed in a variety of ways:
11852 single floating point (f)
11853 double floating point (d)
11855 64bit integer (dx). */
11856 case 'W': /* Cirrus register in F mode. */
11857 case 'X': /* Cirrus register in D mode. */
11858 case 'Y': /* Cirrus register in FX mode. */
11859 case 'Z': /* Cirrus register in DX mode. */
11860 gcc_assert (GET_CODE (x
) == REG
11861 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
11863 fprintf (stream
, "mv%s%s",
11865 : code
== 'X' ? "d"
11866 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
11870 /* Print cirrus register in the mode specified by the register's mode. */
11873 int mode
= GET_MODE (x
);
11875 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
11877 output_operand_lossage ("invalid operand for code '%c'", code
);
11881 fprintf (stream
, "mv%s%s",
11882 mode
== DFmode
? "d"
11883 : mode
== SImode
? "fx"
11884 : mode
== DImode
? "dx"
11885 : "f", reg_names
[REGNO (x
)] + 2);
11891 if (GET_CODE (x
) != REG
11892 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
11893 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
11894 /* Bad value for wCG register number. */
11896 output_operand_lossage ("invalid operand for code '%c'", code
);
11901 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
11904 /* Print an iWMMXt control register name. */
11906 if (GET_CODE (x
) != CONST_INT
11908 || INTVAL (x
) >= 16)
11909 /* Bad value for wC register number. */
11911 output_operand_lossage ("invalid operand for code '%c'", code
);
11917 static const char * wc_reg_names
[16] =
11919 "wCID", "wCon", "wCSSF", "wCASF",
11920 "wC4", "wC5", "wC6", "wC7",
11921 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11922 "wC12", "wC13", "wC14", "wC15"
11925 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
11929 /* Print a VFP double precision register name. */
11932 int mode
= GET_MODE (x
);
11935 if (mode
!= DImode
&& mode
!= DFmode
)
11937 output_operand_lossage ("invalid operand for code '%c'", code
);
11941 if (GET_CODE (x
) != REG
11942 || !IS_VFP_REGNUM (REGNO (x
)))
11944 output_operand_lossage ("invalid operand for code '%c'", code
);
11948 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
11951 output_operand_lossage ("invalid operand for code '%c'", code
);
11955 fprintf (stream
, "d%d", num
>> 1);
11962 output_operand_lossage ("missing operand");
11966 switch (GET_CODE (x
))
11969 asm_fprintf (stream
, "%r", REGNO (x
));
11973 output_memory_reference_mode
= GET_MODE (x
);
11974 output_address (XEXP (x
, 0));
11978 fprintf (stream
, "#%s", fp_immediate_constant (x
));
11982 gcc_assert (GET_CODE (x
) != NEG
);
11983 fputc ('#', stream
);
11984 output_addr_const (stream
, x
);
11990 #ifndef AOF_ASSEMBLER
11991 /* Target hook for assembling integer objects. The ARM version needs to
11992 handle word-sized values specially. */
11994 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11996 if (size
== UNITS_PER_WORD
&& aligned_p
)
11998 fputs ("\t.word\t", asm_out_file
);
11999 output_addr_const (asm_out_file
, x
);
12001 /* Mark symbols as position independent. We only do this in the
12002 .text segment, not in the .data segment. */
12003 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
12004 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
12006 if (GET_CODE (x
) == SYMBOL_REF
12007 && (CONSTANT_POOL_ADDRESS_P (x
)
12008 || SYMBOL_REF_LOCAL_P (x
)))
12009 fputs ("(GOTOFF)", asm_out_file
);
12010 else if (GET_CODE (x
) == LABEL_REF
)
12011 fputs ("(GOTOFF)", asm_out_file
);
12013 fputs ("(GOT)", asm_out_file
);
12015 fputc ('\n', asm_out_file
);
12019 if (arm_vector_mode_supported_p (GET_MODE (x
)))
12023 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
12025 units
= CONST_VECTOR_NUNITS (x
);
12027 switch (GET_MODE (x
))
12029 case V2SImode
: size
= 4; break;
12030 case V4HImode
: size
= 2; break;
12031 case V8QImode
: size
= 1; break;
12033 gcc_unreachable ();
12036 for (i
= 0; i
< units
; i
++)
12040 elt
= CONST_VECTOR_ELT (x
, i
);
12042 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
12048 return default_assemble_integer (x
, size
, aligned_p
);
12052 /* Add a function to the list of static constructors. */
12055 arm_elf_asm_constructor (rtx symbol
, int priority
)
12059 if (!TARGET_AAPCS_BASED
)
12061 default_named_section_asm_out_constructor (symbol
, priority
);
12065 /* Put these in the .init_array section, using a special relocation. */
12066 if (priority
!= DEFAULT_INIT_PRIORITY
)
12069 sprintf (buf
, ".init_array.%.5u", priority
);
12070 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
12075 switch_to_section (s
);
12076 assemble_align (POINTER_SIZE
);
12077 fputs ("\t.word\t", asm_out_file
);
12078 output_addr_const (asm_out_file
, symbol
);
12079 fputs ("(target1)\n", asm_out_file
);
12083 /* A finite state machine takes care of noticing whether or not instructions
12084 can be conditionally executed, and thus decrease execution time and code
12085 size by deleting branch instructions. The fsm is controlled by
12086 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12088 /* The state of the fsm controlling condition codes are:
12089 0: normal, do nothing special
12090 1: make ASM_OUTPUT_OPCODE not output this instruction
12091 2: make ASM_OUTPUT_OPCODE not output this instruction
12092 3: make instructions conditional
12093 4: make instructions conditional
12095 State transitions (state->state by whom under condition):
12096 0 -> 1 final_prescan_insn if the `target' is a label
12097 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12098 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12099 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12100 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12101 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12102 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12103 (the target insn is arm_target_insn).
12105 If the jump clobbers the conditions then we use states 2 and 4.
12107 A similar thing can be done with conditional return insns.
12109 XXX In case the `target' is an unconditional branch, this conditionalising
12110 of the instructions always reduces code size, but not always execution
12111 time. But then, I want to reduce the code size to somewhere near what
12112 /bin/cc produces. */
12114 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12115 instructions. When a COND_EXEC instruction is seen the subsequent
12116 instructions are scanned so that multiple conditional instructions can be
12117 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12118 specify the length and true/false mask for the IT block. These will be
12119 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12121 /* Returns the index of the ARM condition code string in
12122 `arm_condition_codes'. COMPARISON should be an rtx like
12123 `(eq (...) (...))'. */
12124 static enum arm_cond_code
12125 get_arm_condition_code (rtx comparison
)
12127 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
12129 enum rtx_code comp_code
= GET_CODE (comparison
);
12131 if (GET_MODE_CLASS (mode
) != MODE_CC
)
12132 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
12133 XEXP (comparison
, 1));
12137 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
12138 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
12139 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
12140 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
12141 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
12142 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
12143 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
12144 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
12145 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
12146 case CC_DLTUmode
: code
= ARM_CC
;
12149 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
12151 if (comp_code
== EQ
)
12152 return ARM_INVERSE_CONDITION_CODE (code
);
12158 case NE
: return ARM_NE
;
12159 case EQ
: return ARM_EQ
;
12160 case GE
: return ARM_PL
;
12161 case LT
: return ARM_MI
;
12162 default: gcc_unreachable ();
12168 case NE
: return ARM_NE
;
12169 case EQ
: return ARM_EQ
;
12170 default: gcc_unreachable ();
12176 case NE
: return ARM_MI
;
12177 case EQ
: return ARM_PL
;
12178 default: gcc_unreachable ();
12183 /* These encodings assume that AC=1 in the FPA system control
12184 byte. This allows us to handle all cases except UNEQ and
12188 case GE
: return ARM_GE
;
12189 case GT
: return ARM_GT
;
12190 case LE
: return ARM_LS
;
12191 case LT
: return ARM_MI
;
12192 case NE
: return ARM_NE
;
12193 case EQ
: return ARM_EQ
;
12194 case ORDERED
: return ARM_VC
;
12195 case UNORDERED
: return ARM_VS
;
12196 case UNLT
: return ARM_LT
;
12197 case UNLE
: return ARM_LE
;
12198 case UNGT
: return ARM_HI
;
12199 case UNGE
: return ARM_PL
;
12200 /* UNEQ and LTGT do not have a representation. */
12201 case UNEQ
: /* Fall through. */
12202 case LTGT
: /* Fall through. */
12203 default: gcc_unreachable ();
12209 case NE
: return ARM_NE
;
12210 case EQ
: return ARM_EQ
;
12211 case GE
: return ARM_LE
;
12212 case GT
: return ARM_LT
;
12213 case LE
: return ARM_GE
;
12214 case LT
: return ARM_GT
;
12215 case GEU
: return ARM_LS
;
12216 case GTU
: return ARM_CC
;
12217 case LEU
: return ARM_CS
;
12218 case LTU
: return ARM_HI
;
12219 default: gcc_unreachable ();
12225 case LTU
: return ARM_CS
;
12226 case GEU
: return ARM_CC
;
12227 default: gcc_unreachable ();
12233 case NE
: return ARM_NE
;
12234 case EQ
: return ARM_EQ
;
12235 case GE
: return ARM_GE
;
12236 case GT
: return ARM_GT
;
12237 case LE
: return ARM_LE
;
12238 case LT
: return ARM_LT
;
12239 case GEU
: return ARM_CS
;
12240 case GTU
: return ARM_HI
;
12241 case LEU
: return ARM_LS
;
12242 case LTU
: return ARM_CC
;
12243 default: gcc_unreachable ();
12246 default: gcc_unreachable ();
12250 /* Tell arm_asm_ouput_opcode to output IT blocks for conditionally executed
12253 thumb2_final_prescan_insn (rtx insn
)
12255 rtx first_insn
= insn
;
12256 rtx body
= PATTERN (insn
);
12258 enum arm_cond_code code
;
12262 /* Remove the previous insn from the count of insns to be output. */
12263 if (arm_condexec_count
)
12264 arm_condexec_count
--;
12266 /* Nothing to do if we are already inside a conditional block. */
12267 if (arm_condexec_count
)
12270 if (GET_CODE (body
) != COND_EXEC
)
12273 /* Conditional jumps are implemented directly. */
12274 if (GET_CODE (insn
) == JUMP_INSN
)
12277 predicate
= COND_EXEC_TEST (body
);
12278 arm_current_cc
= get_arm_condition_code (predicate
);
12280 n
= get_attr_ce_count (insn
);
12281 arm_condexec_count
= 1;
12282 arm_condexec_mask
= (1 << n
) - 1;
12283 arm_condexec_masklen
= n
;
12284 /* See if subsequent instructions can be combined into the same block. */
12287 insn
= next_nonnote_insn (insn
);
12289 /* Jumping into the middle of an IT block is illegal, so a label or
12290 barrier terminates the block. */
12291 if (GET_CODE (insn
) != INSN
&& GET_CODE(insn
) != JUMP_INSN
)
12294 body
= PATTERN (insn
);
12295 /* USE and CLOBBER aren't really insns, so just skip them. */
12296 if (GET_CODE (body
) == USE
12297 || GET_CODE (body
) == CLOBBER
)
12300 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
12301 if (GET_CODE (body
) != COND_EXEC
)
12303 /* Allow up to 4 conditionally executed instructions in a block. */
12304 n
= get_attr_ce_count (insn
);
12305 if (arm_condexec_masklen
+ n
> 4)
12308 predicate
= COND_EXEC_TEST (body
);
12309 code
= get_arm_condition_code (predicate
);
12310 mask
= (1 << n
) - 1;
12311 if (arm_current_cc
== code
)
12312 arm_condexec_mask
|= (mask
<< arm_condexec_masklen
);
12313 else if (arm_current_cc
!= ARM_INVERSE_CONDITION_CODE(code
))
12316 arm_condexec_count
++;
12317 arm_condexec_masklen
+= n
;
12319 /* A jump must be the last instruction in a conditional block. */
12320 if (GET_CODE(insn
) == JUMP_INSN
)
12323 /* Restore recog_data (getting the attributes of other insns can
12324 destroy this array, but final.c assumes that it remains intact
12325 across this call). */
12326 extract_constrain_insn_cached (first_insn
);
12330 arm_final_prescan_insn (rtx insn
)
12332 /* BODY will hold the body of INSN. */
12333 rtx body
= PATTERN (insn
);
12335 /* This will be 1 if trying to repeat the trick, and things need to be
12336 reversed if it appears to fail. */
12339 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12340 taken are clobbered, even if the rtl suggests otherwise. It also
12341 means that we have to grub around within the jump expression to find
12342 out what the conditions are when the jump isn't taken. */
12343 int jump_clobbers
= 0;
12345 /* If we start with a return insn, we only succeed if we find another one. */
12346 int seeking_return
= 0;
12348 /* START_INSN will hold the insn from where we start looking. This is the
12349 first insn after the following code_label if REVERSE is true. */
12350 rtx start_insn
= insn
;
12352 /* If in state 4, check if the target branch is reached, in order to
12353 change back to state 0. */
12354 if (arm_ccfsm_state
== 4)
12356 if (insn
== arm_target_insn
)
12358 arm_target_insn
= NULL
;
12359 arm_ccfsm_state
= 0;
12364 /* If in state 3, it is possible to repeat the trick, if this insn is an
12365 unconditional branch to a label, and immediately following this branch
12366 is the previous target label which is only used once, and the label this
12367 branch jumps to is not too far off. */
12368 if (arm_ccfsm_state
== 3)
12370 if (simplejump_p (insn
))
12372 start_insn
= next_nonnote_insn (start_insn
);
12373 if (GET_CODE (start_insn
) == BARRIER
)
12375 /* XXX Isn't this always a barrier? */
12376 start_insn
= next_nonnote_insn (start_insn
);
12378 if (GET_CODE (start_insn
) == CODE_LABEL
12379 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
12380 && LABEL_NUSES (start_insn
) == 1)
12385 else if (GET_CODE (body
) == RETURN
)
12387 start_insn
= next_nonnote_insn (start_insn
);
12388 if (GET_CODE (start_insn
) == BARRIER
)
12389 start_insn
= next_nonnote_insn (start_insn
);
12390 if (GET_CODE (start_insn
) == CODE_LABEL
12391 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
12392 && LABEL_NUSES (start_insn
) == 1)
12395 seeking_return
= 1;
12404 gcc_assert (!arm_ccfsm_state
|| reverse
);
12405 if (GET_CODE (insn
) != JUMP_INSN
)
12408 /* This jump might be paralleled with a clobber of the condition codes
12409 the jump should always come first */
12410 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
12411 body
= XVECEXP (body
, 0, 0);
12414 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
12415 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
12418 int fail
= FALSE
, succeed
= FALSE
;
12419 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12420 int then_not_else
= TRUE
;
12421 rtx this_insn
= start_insn
, label
= 0;
12423 /* If the jump cannot be done with one instruction, we cannot
12424 conditionally execute the instruction in the inverse case. */
12425 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
12431 /* Register the insn jumped to. */
12434 if (!seeking_return
)
12435 label
= XEXP (SET_SRC (body
), 0);
12437 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
12438 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
12439 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
12441 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
12442 then_not_else
= FALSE
;
12444 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
12445 seeking_return
= 1;
12446 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
12448 seeking_return
= 1;
12449 then_not_else
= FALSE
;
12452 gcc_unreachable ();
12454 /* See how many insns this branch skips, and what kind of insns. If all
12455 insns are okay, and the label or unconditional branch to the same
12456 label is not too far away, succeed. */
12457 for (insns_skipped
= 0;
12458 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
12462 this_insn
= next_nonnote_insn (this_insn
);
12466 switch (GET_CODE (this_insn
))
12469 /* Succeed if it is the target label, otherwise fail since
12470 control falls in from somewhere else. */
12471 if (this_insn
== label
)
12475 arm_ccfsm_state
= 2;
12476 this_insn
= next_nonnote_insn (this_insn
);
12479 arm_ccfsm_state
= 1;
12487 /* Succeed if the following insn is the target label.
12489 If return insns are used then the last insn in a function
12490 will be a barrier. */
12491 this_insn
= next_nonnote_insn (this_insn
);
12492 if (this_insn
&& this_insn
== label
)
12496 arm_ccfsm_state
= 2;
12497 this_insn
= next_nonnote_insn (this_insn
);
12500 arm_ccfsm_state
= 1;
12508 /* The AAPCS says that conditional calls should not be
12509 used since they make interworking inefficient (the
12510 linker can't transform BL<cond> into BLX). That's
12511 only a problem if the machine has BLX. */
12518 /* Succeed if the following insn is the target label, or
12519 if the following two insns are a barrier and the
12521 this_insn
= next_nonnote_insn (this_insn
);
12522 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
12523 this_insn
= next_nonnote_insn (this_insn
);
12525 if (this_insn
&& this_insn
== label
12526 && insns_skipped
< max_insns_skipped
)
12530 arm_ccfsm_state
= 2;
12531 this_insn
= next_nonnote_insn (this_insn
);
12534 arm_ccfsm_state
= 1;
12542 /* If this is an unconditional branch to the same label, succeed.
12543 If it is to another label, do nothing. If it is conditional,
12545 /* XXX Probably, the tests for SET and the PC are
12548 scanbody
= PATTERN (this_insn
);
12549 if (GET_CODE (scanbody
) == SET
12550 && GET_CODE (SET_DEST (scanbody
)) == PC
)
12552 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
12553 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
12555 arm_ccfsm_state
= 2;
12558 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
12561 /* Fail if a conditional return is undesirable (e.g. on a
12562 StrongARM), but still allow this if optimizing for size. */
12563 else if (GET_CODE (scanbody
) == RETURN
12564 && !use_return_insn (TRUE
, NULL
)
12567 else if (GET_CODE (scanbody
) == RETURN
12570 arm_ccfsm_state
= 2;
12573 else if (GET_CODE (scanbody
) == PARALLEL
)
12575 switch (get_attr_conds (this_insn
))
12585 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
12590 /* Instructions using or affecting the condition codes make it
12592 scanbody
= PATTERN (this_insn
);
12593 if (!(GET_CODE (scanbody
) == SET
12594 || GET_CODE (scanbody
) == PARALLEL
)
12595 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
12598 /* A conditional cirrus instruction must be followed by
12599 a non Cirrus instruction. However, since we
12600 conditionalize instructions in this function and by
12601 the time we get here we can't add instructions
12602 (nops), because shorten_branches() has already been
12603 called, we will disable conditionalizing Cirrus
12604 instructions to be safe. */
12605 if (GET_CODE (scanbody
) != USE
12606 && GET_CODE (scanbody
) != CLOBBER
12607 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
12617 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
12618 arm_target_label
= CODE_LABEL_NUMBER (label
);
12621 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
12623 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
12625 this_insn
= next_nonnote_insn (this_insn
);
12626 gcc_assert (!this_insn
12627 || (GET_CODE (this_insn
) != BARRIER
12628 && GET_CODE (this_insn
) != CODE_LABEL
));
12632 /* Oh, dear! we ran off the end.. give up. */
12633 extract_constrain_insn_cached (insn
);
12634 arm_ccfsm_state
= 0;
12635 arm_target_insn
= NULL
;
12638 arm_target_insn
= this_insn
;
12642 gcc_assert (!reverse
);
12644 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
12646 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
12647 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
12648 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
12649 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
12653 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12656 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
12660 if (reverse
|| then_not_else
)
12661 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
12664 /* Restore recog_data (getting the attributes of other insns can
12665 destroy this array, but final.c assumes that it remains intact
12666 across this call. */
12667 extract_constrain_insn_cached (insn
);
12671 /* Output IT instructions. */
12673 thumb2_asm_output_opcode (FILE * stream
)
12678 if (arm_condexec_mask
)
12680 for (n
= 0; n
< arm_condexec_masklen
; n
++)
12681 buff
[n
] = (arm_condexec_mask
& (1 << n
)) ? 't' : 'e';
12683 asm_fprintf(stream
, "i%s\t%s\n\t", buff
,
12684 arm_condition_codes
[arm_current_cc
]);
12685 arm_condexec_mask
= 0;
12689 /* Returns true if REGNO is a valid register
12690 for holding a quantity of type MODE. */
12692 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
12694 if (GET_MODE_CLASS (mode
) == MODE_CC
)
12695 return (regno
== CC_REGNUM
12696 || (TARGET_HARD_FLOAT
&& TARGET_VFP
12697 && regno
== VFPCC_REGNUM
));
12700 /* For the Thumb we only allow values bigger than SImode in
12701 registers 0 - 6, so that there is always a second low
12702 register available to hold the upper part of the value.
12703 We probably we ought to ensure that the register is the
12704 start of an even numbered register pair. */
12705 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
12707 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
12708 && IS_CIRRUS_REGNUM (regno
))
12709 /* We have outlawed SI values in Cirrus registers because they
12710 reside in the lower 32 bits, but SF values reside in the
12711 upper 32 bits. This causes gcc all sorts of grief. We can't
12712 even split the registers into pairs because Cirrus SI values
12713 get sign extended to 64bits-- aldyh. */
12714 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
12716 if (TARGET_HARD_FLOAT
&& TARGET_VFP
12717 && IS_VFP_REGNUM (regno
))
12719 if (mode
== SFmode
|| mode
== SImode
)
12722 /* DFmode values are only valid in even register pairs. */
12723 if (mode
== DFmode
)
12724 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
12728 if (TARGET_REALLY_IWMMXT
)
12730 if (IS_IWMMXT_GR_REGNUM (regno
))
12731 return mode
== SImode
;
12733 if (IS_IWMMXT_REGNUM (regno
))
12734 return VALID_IWMMXT_REG_MODE (mode
);
12737 /* We allow any value to be stored in the general registers.
12738 Restrict doubleword quantities to even register pairs so that we can
12740 if (regno
<= LAST_ARM_REGNUM
)
12741 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
12743 if (regno
== FRAME_POINTER_REGNUM
12744 || regno
== ARG_POINTER_REGNUM
)
12745 /* We only allow integers in the fake hard registers. */
12746 return GET_MODE_CLASS (mode
) == MODE_INT
;
12748 /* The only registers left are the FPA registers
12749 which we only allow to hold FP values. */
12750 return (TARGET_HARD_FLOAT
&& TARGET_FPA
12751 && GET_MODE_CLASS (mode
) == MODE_FLOAT
12752 && regno
>= FIRST_FPA_REGNUM
12753 && regno
<= LAST_FPA_REGNUM
);
12756 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
12757 not used in arm mode. */
12759 arm_regno_class (int regno
)
12763 if (regno
== STACK_POINTER_REGNUM
)
12765 if (regno
== CC_REGNUM
)
12772 if (TARGET_THUMB2
&& regno
< 8)
12775 if ( regno
<= LAST_ARM_REGNUM
12776 || regno
== FRAME_POINTER_REGNUM
12777 || regno
== ARG_POINTER_REGNUM
)
12778 return TARGET_THUMB2
? HI_REGS
: GENERAL_REGS
;
12780 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
12781 return TARGET_THUMB2
? CC_REG
: NO_REGS
;
12783 if (IS_CIRRUS_REGNUM (regno
))
12784 return CIRRUS_REGS
;
12786 if (IS_VFP_REGNUM (regno
))
12789 if (IS_IWMMXT_REGNUM (regno
))
12790 return IWMMXT_REGS
;
12792 if (IS_IWMMXT_GR_REGNUM (regno
))
12793 return IWMMXT_GR_REGS
;
12798 /* Handle a special case when computing the offset
12799 of an argument from the frame pointer. */
12801 arm_debugger_arg_offset (int value
, rtx addr
)
12805 /* We are only interested if dbxout_parms() failed to compute the offset. */
12809 /* We can only cope with the case where the address is held in a register. */
12810 if (GET_CODE (addr
) != REG
)
12813 /* If we are using the frame pointer to point at the argument, then
12814 an offset of 0 is correct. */
12815 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
12818 /* If we are using the stack pointer to point at the
12819 argument, then an offset of 0 is correct. */
12820 /* ??? Check this is consistent with thumb2 frame layout. */
12821 if ((TARGET_THUMB
|| !frame_pointer_needed
)
12822 && REGNO (addr
) == SP_REGNUM
)
12825 /* Oh dear. The argument is pointed to by a register rather
12826 than being held in a register, or being stored at a known
12827 offset from the frame pointer. Since GDB only understands
12828 those two kinds of argument we must translate the address
12829 held in the register into an offset from the frame pointer.
12830 We do this by searching through the insns for the function
12831 looking to see where this register gets its value. If the
12832 register is initialized from the frame pointer plus an offset
12833 then we are in luck and we can continue, otherwise we give up.
12835 This code is exercised by producing debugging information
12836 for a function with arguments like this:
12838 double func (double a, double b, int c, double d) {return d;}
12840 Without this code the stab for parameter 'd' will be set to
12841 an offset of 0 from the frame pointer, rather than 8. */
12843 /* The if() statement says:
12845 If the insn is a normal instruction
12846 and if the insn is setting the value in a register
12847 and if the register being set is the register holding the address of the argument
12848 and if the address is computing by an addition
12849 that involves adding to a register
12850 which is the frame pointer
12855 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12857 if ( GET_CODE (insn
) == INSN
12858 && GET_CODE (PATTERN (insn
)) == SET
12859 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
12860 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
12861 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
12862 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12863 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
12866 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
12875 warning (0, "unable to compute real location of stacked parameter");
12876 value
= 8; /* XXX magic hack */
12882 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12885 if ((MASK) & insn_flags) \
12886 add_builtin_function ((NAME), (TYPE), (CODE), \
12887 BUILT_IN_MD, NULL, NULL_TREE); \
12891 struct builtin_description
12893 const unsigned int mask
;
12894 const enum insn_code icode
;
12895 const char * const name
;
12896 const enum arm_builtins code
;
12897 const enum rtx_code comparison
;
12898 const unsigned int flag
;
12901 static const struct builtin_description bdesc_2arg
[] =
12903 #define IWMMXT_BUILTIN(code, string, builtin) \
12904 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12905 ARM_BUILTIN_##builtin, 0, 0 },
12907 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
12908 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
12909 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
12910 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
12911 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
12912 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
12913 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
12914 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
12915 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
12916 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
12917 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
12918 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
12919 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
12920 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
12921 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
12922 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
12923 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
12924 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
12925 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
12926 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
12927 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
12928 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
12929 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
12930 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
12931 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
12932 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
12933 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
12934 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
12935 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
12936 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
12937 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
12938 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
12939 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
12940 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
12941 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
12942 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
12943 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
12944 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
12945 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
12946 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
12947 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
12948 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
12949 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
12950 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
12951 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
12952 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
12953 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
12954 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
12955 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
12956 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
12957 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
12958 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
12959 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
12960 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
12961 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
12962 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
12963 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
12964 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
12966 #define IWMMXT_BUILTIN2(code, builtin) \
12967 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12969 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
12970 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
12971 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
12972 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
12973 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
12974 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
12975 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
12976 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
12977 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
12978 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
12979 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
12980 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
12981 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
12982 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
12983 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
12984 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
12985 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
12986 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
12987 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
12988 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
12989 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
12990 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
12991 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
12992 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
12993 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
12994 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
12995 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
12996 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
12997 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
12998 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
12999 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
13000 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
13003 static const struct builtin_description bdesc_1arg
[] =
13005 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
13006 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
13007 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
13008 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
13009 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
13010 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
13011 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
13012 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
13013 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
13014 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
13015 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
13016 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
13017 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
13018 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
13019 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
13020 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
13021 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
13022 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
13025 /* Set up all the iWMMXt builtins. This is
13026 not called if TARGET_IWMMXT is zero. */
13029 arm_init_iwmmxt_builtins (void)
13031 const struct builtin_description
* d
;
13033 tree endlink
= void_list_node
;
13035 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
13036 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
13037 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
13040 = build_function_type (integer_type_node
,
13041 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
13042 tree v8qi_ftype_v8qi_v8qi_int
13043 = build_function_type (V8QI_type_node
,
13044 tree_cons (NULL_TREE
, V8QI_type_node
,
13045 tree_cons (NULL_TREE
, V8QI_type_node
,
13046 tree_cons (NULL_TREE
,
13049 tree v4hi_ftype_v4hi_int
13050 = build_function_type (V4HI_type_node
,
13051 tree_cons (NULL_TREE
, V4HI_type_node
,
13052 tree_cons (NULL_TREE
, integer_type_node
,
13054 tree v2si_ftype_v2si_int
13055 = build_function_type (V2SI_type_node
,
13056 tree_cons (NULL_TREE
, V2SI_type_node
,
13057 tree_cons (NULL_TREE
, integer_type_node
,
13059 tree v2si_ftype_di_di
13060 = build_function_type (V2SI_type_node
,
13061 tree_cons (NULL_TREE
, long_long_integer_type_node
,
13062 tree_cons (NULL_TREE
, long_long_integer_type_node
,
13064 tree di_ftype_di_int
13065 = build_function_type (long_long_integer_type_node
,
13066 tree_cons (NULL_TREE
, long_long_integer_type_node
,
13067 tree_cons (NULL_TREE
, integer_type_node
,
13069 tree di_ftype_di_int_int
13070 = build_function_type (long_long_integer_type_node
,
13071 tree_cons (NULL_TREE
, long_long_integer_type_node
,
13072 tree_cons (NULL_TREE
, integer_type_node
,
13073 tree_cons (NULL_TREE
,
13076 tree int_ftype_v8qi
13077 = build_function_type (integer_type_node
,
13078 tree_cons (NULL_TREE
, V8QI_type_node
,
13080 tree int_ftype_v4hi
13081 = build_function_type (integer_type_node
,
13082 tree_cons (NULL_TREE
, V4HI_type_node
,
13084 tree int_ftype_v2si
13085 = build_function_type (integer_type_node
,
13086 tree_cons (NULL_TREE
, V2SI_type_node
,
13088 tree int_ftype_v8qi_int
13089 = build_function_type (integer_type_node
,
13090 tree_cons (NULL_TREE
, V8QI_type_node
,
13091 tree_cons (NULL_TREE
, integer_type_node
,
13093 tree int_ftype_v4hi_int
13094 = build_function_type (integer_type_node
,
13095 tree_cons (NULL_TREE
, V4HI_type_node
,
13096 tree_cons (NULL_TREE
, integer_type_node
,
13098 tree int_ftype_v2si_int
13099 = build_function_type (integer_type_node
,
13100 tree_cons (NULL_TREE
, V2SI_type_node
,
13101 tree_cons (NULL_TREE
, integer_type_node
,
13103 tree v8qi_ftype_v8qi_int_int
13104 = build_function_type (V8QI_type_node
,
13105 tree_cons (NULL_TREE
, V8QI_type_node
,
13106 tree_cons (NULL_TREE
, integer_type_node
,
13107 tree_cons (NULL_TREE
,
13110 tree v4hi_ftype_v4hi_int_int
13111 = build_function_type (V4HI_type_node
,
13112 tree_cons (NULL_TREE
, V4HI_type_node
,
13113 tree_cons (NULL_TREE
, integer_type_node
,
13114 tree_cons (NULL_TREE
,
13117 tree v2si_ftype_v2si_int_int
13118 = build_function_type (V2SI_type_node
,
13119 tree_cons (NULL_TREE
, V2SI_type_node
,
13120 tree_cons (NULL_TREE
, integer_type_node
,
13121 tree_cons (NULL_TREE
,
13124 /* Miscellaneous. */
13125 tree v8qi_ftype_v4hi_v4hi
13126 = build_function_type (V8QI_type_node
,
13127 tree_cons (NULL_TREE
, V4HI_type_node
,
13128 tree_cons (NULL_TREE
, V4HI_type_node
,
13130 tree v4hi_ftype_v2si_v2si
13131 = build_function_type (V4HI_type_node
,
13132 tree_cons (NULL_TREE
, V2SI_type_node
,
13133 tree_cons (NULL_TREE
, V2SI_type_node
,
13135 tree v2si_ftype_v4hi_v4hi
13136 = build_function_type (V2SI_type_node
,
13137 tree_cons (NULL_TREE
, V4HI_type_node
,
13138 tree_cons (NULL_TREE
, V4HI_type_node
,
13140 tree v2si_ftype_v8qi_v8qi
13141 = build_function_type (V2SI_type_node
,
13142 tree_cons (NULL_TREE
, V8QI_type_node
,
13143 tree_cons (NULL_TREE
, V8QI_type_node
,
13145 tree v4hi_ftype_v4hi_di
13146 = build_function_type (V4HI_type_node
,
13147 tree_cons (NULL_TREE
, V4HI_type_node
,
13148 tree_cons (NULL_TREE
,
13149 long_long_integer_type_node
,
13151 tree v2si_ftype_v2si_di
13152 = build_function_type (V2SI_type_node
,
13153 tree_cons (NULL_TREE
, V2SI_type_node
,
13154 tree_cons (NULL_TREE
,
13155 long_long_integer_type_node
,
13157 tree void_ftype_int_int
13158 = build_function_type (void_type_node
,
13159 tree_cons (NULL_TREE
, integer_type_node
,
13160 tree_cons (NULL_TREE
, integer_type_node
,
13163 = build_function_type (long_long_unsigned_type_node
, endlink
);
13165 = build_function_type (long_long_integer_type_node
,
13166 tree_cons (NULL_TREE
, V8QI_type_node
,
13169 = build_function_type (long_long_integer_type_node
,
13170 tree_cons (NULL_TREE
, V4HI_type_node
,
13173 = build_function_type (long_long_integer_type_node
,
13174 tree_cons (NULL_TREE
, V2SI_type_node
,
13176 tree v2si_ftype_v4hi
13177 = build_function_type (V2SI_type_node
,
13178 tree_cons (NULL_TREE
, V4HI_type_node
,
13180 tree v4hi_ftype_v8qi
13181 = build_function_type (V4HI_type_node
,
13182 tree_cons (NULL_TREE
, V8QI_type_node
,
13185 tree di_ftype_di_v4hi_v4hi
13186 = build_function_type (long_long_unsigned_type_node
,
13187 tree_cons (NULL_TREE
,
13188 long_long_unsigned_type_node
,
13189 tree_cons (NULL_TREE
, V4HI_type_node
,
13190 tree_cons (NULL_TREE
,
13194 tree di_ftype_v4hi_v4hi
13195 = build_function_type (long_long_unsigned_type_node
,
13196 tree_cons (NULL_TREE
, V4HI_type_node
,
13197 tree_cons (NULL_TREE
, V4HI_type_node
,
13200 /* Normal vector binops. */
13201 tree v8qi_ftype_v8qi_v8qi
13202 = build_function_type (V8QI_type_node
,
13203 tree_cons (NULL_TREE
, V8QI_type_node
,
13204 tree_cons (NULL_TREE
, V8QI_type_node
,
13206 tree v4hi_ftype_v4hi_v4hi
13207 = build_function_type (V4HI_type_node
,
13208 tree_cons (NULL_TREE
, V4HI_type_node
,
13209 tree_cons (NULL_TREE
, V4HI_type_node
,
13211 tree v2si_ftype_v2si_v2si
13212 = build_function_type (V2SI_type_node
,
13213 tree_cons (NULL_TREE
, V2SI_type_node
,
13214 tree_cons (NULL_TREE
, V2SI_type_node
,
13216 tree di_ftype_di_di
13217 = build_function_type (long_long_unsigned_type_node
,
13218 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
13219 tree_cons (NULL_TREE
,
13220 long_long_unsigned_type_node
,
13223 /* Add all builtins that are more or less simple operations on two
13225 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13227 /* Use one of the operands; the target can have a different mode for
13228 mask-generating compares. */
13229 enum machine_mode mode
;
13235 mode
= insn_data
[d
->icode
].operand
[1].mode
;
13240 type
= v8qi_ftype_v8qi_v8qi
;
13243 type
= v4hi_ftype_v4hi_v4hi
;
13246 type
= v2si_ftype_v2si_v2si
;
13249 type
= di_ftype_di_di
;
13253 gcc_unreachable ();
13256 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
13259 /* Add the remaining MMX insns with somewhat more complicated types. */
13260 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
13261 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
13262 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
13264 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
13265 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
13266 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
13267 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
13268 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
13269 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
13271 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
13272 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
13273 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
13274 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
13275 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
13276 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
13278 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
13279 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
13280 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
13281 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
13282 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
13283 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
13285 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
13286 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
13287 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
13288 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
13289 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
13290 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
13292 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
13294 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
13295 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
13296 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
13297 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
13299 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
13300 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
13301 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
13302 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
13303 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
13304 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
13305 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
13306 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
13307 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
13309 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
13310 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
13311 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
13313 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
13314 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
13315 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
13317 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
13318 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
13319 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
13320 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
13321 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
13322 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
13324 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
13325 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
13326 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
13327 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
13328 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
13329 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
13330 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
13331 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
13332 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
13333 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
13334 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
13335 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
13337 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
13338 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
13339 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
13340 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
13342 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
13343 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
13344 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
13345 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
13346 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
13347 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
13348 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
13352 arm_init_tls_builtins (void)
13355 tree nothrow
= tree_cons (get_identifier ("nothrow"), NULL
, NULL
);
13356 tree const_nothrow
= tree_cons (get_identifier ("const"), NULL
, nothrow
);
13358 ftype
= build_function_type (ptr_type_node
, void_list_node
);
13359 add_builtin_function ("__builtin_thread_pointer", ftype
,
13360 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
13361 NULL
, const_nothrow
);
13365 arm_init_builtins (void)
13367 arm_init_tls_builtins ();
13369 if (TARGET_REALLY_IWMMXT
)
13370 arm_init_iwmmxt_builtins ();
13373 /* Errors in the source file can cause expand_expr to return const0_rtx
13374 where we expect a vector. To avoid crashing, use one of the vector
13375 clear instructions. */
13378 safe_vector_operand (rtx x
, enum machine_mode mode
)
13380 if (x
!= const0_rtx
)
13382 x
= gen_reg_rtx (mode
);
13384 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
13385 : gen_rtx_SUBREG (DImode
, x
, 0)));
13389 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13392 arm_expand_binop_builtin (enum insn_code icode
,
13393 tree exp
, rtx target
)
13396 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13397 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13398 rtx op0
= expand_normal (arg0
);
13399 rtx op1
= expand_normal (arg1
);
13400 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13401 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13402 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13404 if (VECTOR_MODE_P (mode0
))
13405 op0
= safe_vector_operand (op0
, mode0
);
13406 if (VECTOR_MODE_P (mode1
))
13407 op1
= safe_vector_operand (op1
, mode1
);
13410 || GET_MODE (target
) != tmode
13411 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13412 target
= gen_reg_rtx (tmode
);
13414 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
13416 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13417 op0
= copy_to_mode_reg (mode0
, op0
);
13418 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13419 op1
= copy_to_mode_reg (mode1
, op1
);
13421 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13428 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13431 arm_expand_unop_builtin (enum insn_code icode
,
13432 tree exp
, rtx target
, int do_load
)
13435 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13436 rtx op0
= expand_normal (arg0
);
13437 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13438 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13441 || GET_MODE (target
) != tmode
13442 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13443 target
= gen_reg_rtx (tmode
);
13445 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13448 if (VECTOR_MODE_P (mode0
))
13449 op0
= safe_vector_operand (op0
, mode0
);
13451 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13452 op0
= copy_to_mode_reg (mode0
, op0
);
13455 pat
= GEN_FCN (icode
) (target
, op0
);
13462 /* Expand an expression EXP that calls a built-in function,
13463 with result going to TARGET if that's convenient
13464 (and in mode MODE if that's convenient).
13465 SUBTARGET may be used as the target for computing one of EXP's operands.
13466 IGNORE is nonzero if the value is to be ignored. */
13469 arm_expand_builtin (tree exp
,
13471 rtx subtarget ATTRIBUTE_UNUSED
,
13472 enum machine_mode mode ATTRIBUTE_UNUSED
,
13473 int ignore ATTRIBUTE_UNUSED
)
13475 const struct builtin_description
* d
;
13476 enum insn_code icode
;
13477 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13485 int fcode
= DECL_FUNCTION_CODE (fndecl
);
13487 enum machine_mode tmode
;
13488 enum machine_mode mode0
;
13489 enum machine_mode mode1
;
13490 enum machine_mode mode2
;
13494 case ARM_BUILTIN_TEXTRMSB
:
13495 case ARM_BUILTIN_TEXTRMUB
:
13496 case ARM_BUILTIN_TEXTRMSH
:
13497 case ARM_BUILTIN_TEXTRMUH
:
13498 case ARM_BUILTIN_TEXTRMSW
:
13499 case ARM_BUILTIN_TEXTRMUW
:
13500 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
13501 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
13502 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
13503 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
13504 : CODE_FOR_iwmmxt_textrmw
);
13506 arg0
= CALL_EXPR_ARG (exp
, 0);
13507 arg1
= CALL_EXPR_ARG (exp
, 1);
13508 op0
= expand_normal (arg0
);
13509 op1
= expand_normal (arg1
);
13510 tmode
= insn_data
[icode
].operand
[0].mode
;
13511 mode0
= insn_data
[icode
].operand
[1].mode
;
13512 mode1
= insn_data
[icode
].operand
[2].mode
;
13514 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13515 op0
= copy_to_mode_reg (mode0
, op0
);
13516 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13518 /* @@@ better error message */
13519 error ("selector must be an immediate");
13520 return gen_reg_rtx (tmode
);
13523 || GET_MODE (target
) != tmode
13524 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13525 target
= gen_reg_rtx (tmode
);
13526 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13532 case ARM_BUILTIN_TINSRB
:
13533 case ARM_BUILTIN_TINSRH
:
13534 case ARM_BUILTIN_TINSRW
:
13535 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
13536 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
13537 : CODE_FOR_iwmmxt_tinsrw
);
13538 arg0
= CALL_EXPR_ARG (exp
, 0);
13539 arg1
= CALL_EXPR_ARG (exp
, 1);
13540 arg2
= CALL_EXPR_ARG (exp
, 2);
13541 op0
= expand_normal (arg0
);
13542 op1
= expand_normal (arg1
);
13543 op2
= expand_normal (arg2
);
13544 tmode
= insn_data
[icode
].operand
[0].mode
;
13545 mode0
= insn_data
[icode
].operand
[1].mode
;
13546 mode1
= insn_data
[icode
].operand
[2].mode
;
13547 mode2
= insn_data
[icode
].operand
[3].mode
;
13549 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13550 op0
= copy_to_mode_reg (mode0
, op0
);
13551 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13552 op1
= copy_to_mode_reg (mode1
, op1
);
13553 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13555 /* @@@ better error message */
13556 error ("selector must be an immediate");
13560 || GET_MODE (target
) != tmode
13561 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13562 target
= gen_reg_rtx (tmode
);
13563 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13569 case ARM_BUILTIN_SETWCX
:
13570 arg0
= CALL_EXPR_ARG (exp
, 0);
13571 arg1
= CALL_EXPR_ARG (exp
, 1);
13572 op0
= force_reg (SImode
, expand_normal (arg0
));
13573 op1
= expand_normal (arg1
);
13574 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
13577 case ARM_BUILTIN_GETWCX
:
13578 arg0
= CALL_EXPR_ARG (exp
, 0);
13579 op0
= expand_normal (arg0
);
13580 target
= gen_reg_rtx (SImode
);
13581 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
13584 case ARM_BUILTIN_WSHUFH
:
13585 icode
= CODE_FOR_iwmmxt_wshufh
;
13586 arg0
= CALL_EXPR_ARG (exp
, 0);
13587 arg1
= CALL_EXPR_ARG (exp
, 1);
13588 op0
= expand_normal (arg0
);
13589 op1
= expand_normal (arg1
);
13590 tmode
= insn_data
[icode
].operand
[0].mode
;
13591 mode1
= insn_data
[icode
].operand
[1].mode
;
13592 mode2
= insn_data
[icode
].operand
[2].mode
;
13594 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
13595 op0
= copy_to_mode_reg (mode1
, op0
);
13596 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
13598 /* @@@ better error message */
13599 error ("mask must be an immediate");
13603 || GET_MODE (target
) != tmode
13604 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13605 target
= gen_reg_rtx (tmode
);
13606 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13612 case ARM_BUILTIN_WSADB
:
13613 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, exp
, target
);
13614 case ARM_BUILTIN_WSADH
:
13615 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, exp
, target
);
13616 case ARM_BUILTIN_WSADBZ
:
13617 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, exp
, target
);
13618 case ARM_BUILTIN_WSADHZ
:
13619 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, exp
, target
);
13621 /* Several three-argument builtins. */
13622 case ARM_BUILTIN_WMACS
:
13623 case ARM_BUILTIN_WMACU
:
13624 case ARM_BUILTIN_WALIGN
:
13625 case ARM_BUILTIN_TMIA
:
13626 case ARM_BUILTIN_TMIAPH
:
13627 case ARM_BUILTIN_TMIATT
:
13628 case ARM_BUILTIN_TMIATB
:
13629 case ARM_BUILTIN_TMIABT
:
13630 case ARM_BUILTIN_TMIABB
:
13631 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
13632 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
13633 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
13634 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
13635 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
13636 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
13637 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
13638 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
13639 : CODE_FOR_iwmmxt_walign
);
13640 arg0
= CALL_EXPR_ARG (exp
, 0);
13641 arg1
= CALL_EXPR_ARG (exp
, 1);
13642 arg2
= CALL_EXPR_ARG (exp
, 2);
13643 op0
= expand_normal (arg0
);
13644 op1
= expand_normal (arg1
);
13645 op2
= expand_normal (arg2
);
13646 tmode
= insn_data
[icode
].operand
[0].mode
;
13647 mode0
= insn_data
[icode
].operand
[1].mode
;
13648 mode1
= insn_data
[icode
].operand
[2].mode
;
13649 mode2
= insn_data
[icode
].operand
[3].mode
;
13651 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13652 op0
= copy_to_mode_reg (mode0
, op0
);
13653 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13654 op1
= copy_to_mode_reg (mode1
, op1
);
13655 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13656 op2
= copy_to_mode_reg (mode2
, op2
);
13658 || GET_MODE (target
) != tmode
13659 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13660 target
= gen_reg_rtx (tmode
);
13661 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13667 case ARM_BUILTIN_WZERO
:
13668 target
= gen_reg_rtx (DImode
);
13669 emit_insn (gen_iwmmxt_clrdi (target
));
13672 case ARM_BUILTIN_THREAD_POINTER
:
13673 return arm_load_tp (target
);
13679 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13680 if (d
->code
== (const enum arm_builtins
) fcode
)
13681 return arm_expand_binop_builtin (d
->icode
, exp
, target
);
13683 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13684 if (d
->code
== (const enum arm_builtins
) fcode
)
13685 return arm_expand_unop_builtin (d
->icode
, exp
, target
, 0);
13687 /* @@@ Should really do something sensible here. */
13691 /* Return the number (counting from 0) of
13692 the least significant set bit in MASK. */
13695 number_of_first_bit_set (unsigned mask
)
13700 (mask
& (1 << bit
)) == 0;
13707 /* Emit code to push or pop registers to or from the stack. F is the
13708 assembly file. MASK is the registers to push or pop. PUSH is
13709 nonzero if we should push, and zero if we should pop. For debugging
13710 output, if pushing, adjust CFA_OFFSET by the amount of space added
13711 to the stack. REAL_REGS should have the same number of bits set as
13712 MASK, and will be used instead (in the same order) to describe which
13713 registers were saved - this is used to mark the save slots when we
13714 push high registers after moving them to low registers. */
13716 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
13717 unsigned long real_regs
)
13720 int lo_mask
= mask
& 0xFF;
13721 int pushed_words
= 0;
13725 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
13727 /* Special case. Do not generate a POP PC statement here, do it in
13729 thumb_exit (f
, -1);
13733 if (ARM_EABI_UNWIND_TABLES
&& push
)
13735 fprintf (f
, "\t.save\t{");
13736 for (regno
= 0; regno
< 15; regno
++)
13738 if (real_regs
& (1 << regno
))
13740 if (real_regs
& ((1 << regno
) -1))
13742 asm_fprintf (f
, "%r", regno
);
13745 fprintf (f
, "}\n");
13748 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
13750 /* Look at the low registers first. */
13751 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
13755 asm_fprintf (f
, "%r", regno
);
13757 if ((lo_mask
& ~1) != 0)
13764 if (push
&& (mask
& (1 << LR_REGNUM
)))
13766 /* Catch pushing the LR. */
13770 asm_fprintf (f
, "%r", LR_REGNUM
);
13774 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
13776 /* Catch popping the PC. */
13777 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
13778 || current_function_calls_eh_return
)
13780 /* The PC is never poped directly, instead
13781 it is popped into r3 and then BX is used. */
13782 fprintf (f
, "}\n");
13784 thumb_exit (f
, -1);
13793 asm_fprintf (f
, "%r", PC_REGNUM
);
13797 fprintf (f
, "}\n");
13799 if (push
&& pushed_words
&& dwarf2out_do_frame ())
13801 char *l
= dwarf2out_cfi_label ();
13802 int pushed_mask
= real_regs
;
13804 *cfa_offset
+= pushed_words
* 4;
13805 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
13808 pushed_mask
= real_regs
;
13809 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
13811 if (pushed_mask
& 1)
13812 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
13817 /* Generate code to return from a thumb function.
13818 If 'reg_containing_return_addr' is -1, then the return address is
13819 actually on the stack, at the stack pointer. */
13821 thumb_exit (FILE *f
, int reg_containing_return_addr
)
13823 unsigned regs_available_for_popping
;
13824 unsigned regs_to_pop
;
13826 unsigned available
;
13830 int restore_a4
= FALSE
;
13832 /* Compute the registers we need to pop. */
13836 if (reg_containing_return_addr
== -1)
13838 regs_to_pop
|= 1 << LR_REGNUM
;
13842 if (TARGET_BACKTRACE
)
13844 /* Restore the (ARM) frame pointer and stack pointer. */
13845 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
13849 /* If there is nothing to pop then just emit the BX instruction and
13851 if (pops_needed
== 0)
13853 if (current_function_calls_eh_return
)
13854 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
13856 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
13859 /* Otherwise if we are not supporting interworking and we have not created
13860 a backtrace structure and the function was not entered in ARM mode then
13861 just pop the return address straight into the PC. */
13862 else if (!TARGET_INTERWORK
13863 && !TARGET_BACKTRACE
13864 && !is_called_in_ARM_mode (current_function_decl
)
13865 && !current_function_calls_eh_return
)
13867 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
13871 /* Find out how many of the (return) argument registers we can corrupt. */
13872 regs_available_for_popping
= 0;
13874 /* If returning via __builtin_eh_return, the bottom three registers
13875 all contain information needed for the return. */
13876 if (current_function_calls_eh_return
)
13880 /* If we can deduce the registers used from the function's
13881 return value. This is more reliable that examining
13882 regs_ever_live[] because that will be set if the register is
13883 ever used in the function, not just if the register is used
13884 to hold a return value. */
13886 if (current_function_return_rtx
!= 0)
13887 mode
= GET_MODE (current_function_return_rtx
);
13889 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13891 size
= GET_MODE_SIZE (mode
);
13895 /* In a void function we can use any argument register.
13896 In a function that returns a structure on the stack
13897 we can use the second and third argument registers. */
13898 if (mode
== VOIDmode
)
13899 regs_available_for_popping
=
13900 (1 << ARG_REGISTER (1))
13901 | (1 << ARG_REGISTER (2))
13902 | (1 << ARG_REGISTER (3));
13904 regs_available_for_popping
=
13905 (1 << ARG_REGISTER (2))
13906 | (1 << ARG_REGISTER (3));
13908 else if (size
<= 4)
13909 regs_available_for_popping
=
13910 (1 << ARG_REGISTER (2))
13911 | (1 << ARG_REGISTER (3));
13912 else if (size
<= 8)
13913 regs_available_for_popping
=
13914 (1 << ARG_REGISTER (3));
13917 /* Match registers to be popped with registers into which we pop them. */
13918 for (available
= regs_available_for_popping
,
13919 required
= regs_to_pop
;
13920 required
!= 0 && available
!= 0;
13921 available
&= ~(available
& - available
),
13922 required
&= ~(required
& - required
))
13925 /* If we have any popping registers left over, remove them. */
13927 regs_available_for_popping
&= ~available
;
13929 /* Otherwise if we need another popping register we can use
13930 the fourth argument register. */
13931 else if (pops_needed
)
13933 /* If we have not found any free argument registers and
13934 reg a4 contains the return address, we must move it. */
13935 if (regs_available_for_popping
== 0
13936 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
13938 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
13939 reg_containing_return_addr
= LR_REGNUM
;
13941 else if (size
> 12)
13943 /* Register a4 is being used to hold part of the return value,
13944 but we have dire need of a free, low register. */
13947 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
13950 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
13952 /* The fourth argument register is available. */
13953 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
13959 /* Pop as many registers as we can. */
13960 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
13961 regs_available_for_popping
);
13963 /* Process the registers we popped. */
13964 if (reg_containing_return_addr
== -1)
13966 /* The return address was popped into the lowest numbered register. */
13967 regs_to_pop
&= ~(1 << LR_REGNUM
);
13969 reg_containing_return_addr
=
13970 number_of_first_bit_set (regs_available_for_popping
);
13972 /* Remove this register for the mask of available registers, so that
13973 the return address will not be corrupted by further pops. */
13974 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
13977 /* If we popped other registers then handle them here. */
13978 if (regs_available_for_popping
)
13982 /* Work out which register currently contains the frame pointer. */
13983 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
13985 /* Move it into the correct place. */
13986 asm_fprintf (f
, "\tmov\t%r, %r\n",
13987 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
13989 /* (Temporarily) remove it from the mask of popped registers. */
13990 regs_available_for_popping
&= ~(1 << frame_pointer
);
13991 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
13993 if (regs_available_for_popping
)
13997 /* We popped the stack pointer as well,
13998 find the register that contains it. */
13999 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
14001 /* Move it into the stack register. */
14002 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
14004 /* At this point we have popped all necessary registers, so
14005 do not worry about restoring regs_available_for_popping
14006 to its correct value:
14008 assert (pops_needed == 0)
14009 assert (regs_available_for_popping == (1 << frame_pointer))
14010 assert (regs_to_pop == (1 << STACK_POINTER)) */
14014 /* Since we have just move the popped value into the frame
14015 pointer, the popping register is available for reuse, and
14016 we know that we still have the stack pointer left to pop. */
14017 regs_available_for_popping
|= (1 << frame_pointer
);
14021 /* If we still have registers left on the stack, but we no longer have
14022 any registers into which we can pop them, then we must move the return
14023 address into the link register and make available the register that
14025 if (regs_available_for_popping
== 0 && pops_needed
> 0)
14027 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
14029 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
14030 reg_containing_return_addr
);
14032 reg_containing_return_addr
= LR_REGNUM
;
14035 /* If we have registers left on the stack then pop some more.
14036 We know that at most we will want to pop FP and SP. */
14037 if (pops_needed
> 0)
14042 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
14043 regs_available_for_popping
);
14045 /* We have popped either FP or SP.
14046 Move whichever one it is into the correct register. */
14047 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
14048 move_to
= number_of_first_bit_set (regs_to_pop
);
14050 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
14052 regs_to_pop
&= ~(1 << move_to
);
14057 /* If we still have not popped everything then we must have only
14058 had one register available to us and we are now popping the SP. */
14059 if (pops_needed
> 0)
14063 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
14064 regs_available_for_popping
);
14066 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
14068 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
14070 assert (regs_to_pop == (1 << STACK_POINTER))
14071 assert (pops_needed == 1)
14075 /* If necessary restore the a4 register. */
14078 if (reg_containing_return_addr
!= LR_REGNUM
)
14080 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
14081 reg_containing_return_addr
= LR_REGNUM
;
14084 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
14087 if (current_function_calls_eh_return
)
14088 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
14090 /* Return to caller. */
14091 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
14096 thumb1_final_prescan_insn (rtx insn
)
14098 if (flag_print_asm_name
)
14099 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
14100 INSN_ADDRESSES (INSN_UID (insn
)));
14104 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
14106 unsigned HOST_WIDE_INT mask
= 0xff;
14109 if (val
== 0) /* XXX */
14112 for (i
= 0; i
< 25; i
++)
14113 if ((val
& (mask
<< i
)) == val
)
14119 /* Returns nonzero if the current function contains,
14120 or might contain a far jump. */
14122 thumb_far_jump_used_p (void)
14126 /* This test is only important for leaf functions. */
14127 /* assert (!leaf_function_p ()); */
14129 /* If we have already decided that far jumps may be used,
14130 do not bother checking again, and always return true even if
14131 it turns out that they are not being used. Once we have made
14132 the decision that far jumps are present (and that hence the link
14133 register will be pushed onto the stack) we cannot go back on it. */
14134 if (cfun
->machine
->far_jump_used
)
14137 /* If this function is not being called from the prologue/epilogue
14138 generation code then it must be being called from the
14139 INITIAL_ELIMINATION_OFFSET macro. */
14140 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
14142 /* In this case we know that we are being asked about the elimination
14143 of the arg pointer register. If that register is not being used,
14144 then there are no arguments on the stack, and we do not have to
14145 worry that a far jump might force the prologue to push the link
14146 register, changing the stack offsets. In this case we can just
14147 return false, since the presence of far jumps in the function will
14148 not affect stack offsets.
14150 If the arg pointer is live (or if it was live, but has now been
14151 eliminated and so set to dead) then we do have to test to see if
14152 the function might contain a far jump. This test can lead to some
14153 false negatives, since before reload is completed, then length of
14154 branch instructions is not known, so gcc defaults to returning their
14155 longest length, which in turn sets the far jump attribute to true.
14157 A false negative will not result in bad code being generated, but it
14158 will result in a needless push and pop of the link register. We
14159 hope that this does not occur too often.
14161 If we need doubleword stack alignment this could affect the other
14162 elimination offsets so we can't risk getting it wrong. */
14163 if (regs_ever_live
[ARG_POINTER_REGNUM
])
14164 cfun
->machine
->arg_pointer_live
= 1;
14165 else if (!cfun
->machine
->arg_pointer_live
)
14169 /* Check to see if the function contains a branch
14170 insn with the far jump attribute set. */
14171 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14173 if (GET_CODE (insn
) == JUMP_INSN
14174 /* Ignore tablejump patterns. */
14175 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
14176 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
14177 && get_attr_far_jump (insn
) == FAR_JUMP_YES
14180 /* Record the fact that we have decided that
14181 the function does use far jumps. */
14182 cfun
->machine
->far_jump_used
= 1;
14190 /* Return nonzero if FUNC must be entered in ARM mode. */
14192 is_called_in_ARM_mode (tree func
)
14194 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
14196 /* Ignore the problem about functions whose address is taken. */
14197 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
14201 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
14207 /* The bits which aren't usefully expanded as rtl. */
14209 thumb_unexpanded_epilogue (void)
14212 unsigned long live_regs_mask
= 0;
14213 int high_regs_pushed
= 0;
14214 int had_to_push_lr
;
14217 if (return_used_this_function
)
14220 if (IS_NAKED (arm_current_func_type ()))
14223 live_regs_mask
= thumb1_compute_save_reg_mask ();
14224 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
14226 /* If we can deduce the registers used from the function's return value.
14227 This is more reliable that examining regs_ever_live[] because that
14228 will be set if the register is ever used in the function, not just if
14229 the register is used to hold a return value. */
14230 size
= arm_size_return_regs ();
14232 /* The prolog may have pushed some high registers to use as
14233 work registers. e.g. the testsuite file:
14234 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14235 compiles to produce:
14236 push {r4, r5, r6, r7, lr}
14240 as part of the prolog. We have to undo that pushing here. */
14242 if (high_regs_pushed
)
14244 unsigned long mask
= live_regs_mask
& 0xff;
14247 /* The available low registers depend on the size of the value we are
14255 /* Oh dear! We have no low registers into which we can pop
14258 ("no low registers available for popping high registers");
14260 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
14261 if (live_regs_mask
& (1 << next_hi_reg
))
14264 while (high_regs_pushed
)
14266 /* Find lo register(s) into which the high register(s) can
14268 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
14270 if (mask
& (1 << regno
))
14271 high_regs_pushed
--;
14272 if (high_regs_pushed
== 0)
14276 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
14278 /* Pop the values into the low register(s). */
14279 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
14281 /* Move the value(s) into the high registers. */
14282 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
14284 if (mask
& (1 << regno
))
14286 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
14289 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
14290 if (live_regs_mask
& (1 << next_hi_reg
))
14295 live_regs_mask
&= ~0x0f00;
14298 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
14299 live_regs_mask
&= 0xff;
14301 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
14303 /* Pop the return address into the PC. */
14304 if (had_to_push_lr
)
14305 live_regs_mask
|= 1 << PC_REGNUM
;
14307 /* Either no argument registers were pushed or a backtrace
14308 structure was created which includes an adjusted stack
14309 pointer, so just pop everything. */
14310 if (live_regs_mask
)
14311 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
14314 /* We have either just popped the return address into the
14315 PC or it is was kept in LR for the entire function. */
14316 if (!had_to_push_lr
)
14317 thumb_exit (asm_out_file
, LR_REGNUM
);
14321 /* Pop everything but the return address. */
14322 if (live_regs_mask
)
14323 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
14326 if (had_to_push_lr
)
14330 /* We have no free low regs, so save one. */
14331 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
14335 /* Get the return address into a temporary register. */
14336 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
14337 1 << LAST_ARG_REGNUM
);
14341 /* Move the return address to lr. */
14342 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
14344 /* Restore the low register. */
14345 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
14350 regno
= LAST_ARG_REGNUM
;
14355 /* Remove the argument registers that were pushed onto the stack. */
14356 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
14357 SP_REGNUM
, SP_REGNUM
,
14358 current_function_pretend_args_size
);
14360 thumb_exit (asm_out_file
, regno
);
14366 /* Functions to save and restore machine-specific function data. */
14367 static struct machine_function
*
14368 arm_init_machine_status (void)
14370 struct machine_function
*machine
;
14371 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
14373 #if ARM_FT_UNKNOWN != 0
14374 machine
->func_type
= ARM_FT_UNKNOWN
;
14379 /* Return an RTX indicating where the return address to the
14380 calling function can be found. */
14382 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
14387 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
14390 /* Do anything needed before RTL is emitted for each function. */
14392 arm_init_expanders (void)
14394 /* Arrange to initialize and mark the machine per-function status. */
14395 init_machine_status
= arm_init_machine_status
;
14397 /* This is to stop the combine pass optimizing away the alignment
14398 adjustment of va_arg. */
14399 /* ??? It is claimed that this should not be necessary. */
14401 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
14405 /* Like arm_compute_initial_elimination offset. Simpler because there
14406 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14407 to point at the base of the local variables after static stack
14408 space for a function has been allocated. */
14411 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
14413 arm_stack_offsets
*offsets
;
14415 offsets
= arm_get_frame_offsets ();
14419 case ARG_POINTER_REGNUM
:
14422 case STACK_POINTER_REGNUM
:
14423 return offsets
->outgoing_args
- offsets
->saved_args
;
14425 case FRAME_POINTER_REGNUM
:
14426 return offsets
->soft_frame
- offsets
->saved_args
;
14428 case ARM_HARD_FRAME_POINTER_REGNUM
:
14429 return offsets
->saved_regs
- offsets
->saved_args
;
14431 case THUMB_HARD_FRAME_POINTER_REGNUM
:
14432 return offsets
->locals_base
- offsets
->saved_args
;
14435 gcc_unreachable ();
14439 case FRAME_POINTER_REGNUM
:
14442 case STACK_POINTER_REGNUM
:
14443 return offsets
->outgoing_args
- offsets
->soft_frame
;
14445 case ARM_HARD_FRAME_POINTER_REGNUM
:
14446 return offsets
->saved_regs
- offsets
->soft_frame
;
14448 case THUMB_HARD_FRAME_POINTER_REGNUM
:
14449 return offsets
->locals_base
- offsets
->soft_frame
;
14452 gcc_unreachable ();
14457 gcc_unreachable ();
14461 /* Generate the rest of a function's prologue. */
14463 thumb1_expand_prologue (void)
14467 HOST_WIDE_INT amount
;
14468 arm_stack_offsets
*offsets
;
14469 unsigned long func_type
;
14471 unsigned long live_regs_mask
;
14473 func_type
= arm_current_func_type ();
14475 /* Naked functions don't have prologues. */
14476 if (IS_NAKED (func_type
))
14479 if (IS_INTERRUPT (func_type
))
14481 error ("interrupt Service Routines cannot be coded in Thumb mode");
14485 live_regs_mask
= thumb1_compute_save_reg_mask ();
14486 /* Load the pic register before setting the frame pointer,
14487 so we can use r7 as a temporary work register. */
14488 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
14489 arm_load_pic_register (live_regs_mask
);
14491 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
14492 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
14493 stack_pointer_rtx
);
14495 offsets
= arm_get_frame_offsets ();
14496 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
14501 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14502 GEN_INT (- amount
)));
14503 RTX_FRAME_RELATED_P (insn
) = 1;
14509 /* The stack decrement is too big for an immediate value in a single
14510 insn. In theory we could issue multiple subtracts, but after
14511 three of them it becomes more space efficient to place the full
14512 value in the constant pool and load into a register. (Also the
14513 ARM debugger really likes to see only one stack decrement per
14514 function). So instead we look for a scratch register into which
14515 we can load the decrement, and then we subtract this from the
14516 stack pointer. Unfortunately on the thumb the only available
14517 scratch registers are the argument registers, and we cannot use
14518 these as they may hold arguments to the function. Instead we
14519 attempt to locate a call preserved register which is used by this
14520 function. If we can find one, then we know that it will have
14521 been pushed at the start of the prologue and so we can corrupt
14523 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
14524 if (live_regs_mask
& (1 << regno
)
14525 && !(frame_pointer_needed
14526 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
14529 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
14531 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
14533 /* Choose an arbitrary, non-argument low register. */
14534 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
14536 /* Save it by copying it into a high, scratch register. */
14537 emit_insn (gen_movsi (spare
, reg
));
14538 /* Add a USE to stop propagate_one_insn() from barfing. */
14539 emit_insn (gen_prologue_use (spare
));
14541 /* Decrement the stack. */
14542 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
14543 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
14544 stack_pointer_rtx
, reg
));
14545 RTX_FRAME_RELATED_P (insn
) = 1;
14546 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
14547 plus_constant (stack_pointer_rtx
,
14549 RTX_FRAME_RELATED_P (dwarf
) = 1;
14551 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
14554 /* Restore the low register's original value. */
14555 emit_insn (gen_movsi (reg
, spare
));
14557 /* Emit a USE of the restored scratch register, so that flow
14558 analysis will not consider the restore redundant. The
14559 register won't be used again in this function and isn't
14560 restored by the epilogue. */
14561 emit_insn (gen_prologue_use (reg
));
14565 reg
= gen_rtx_REG (SImode
, regno
);
14567 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
14569 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
14570 stack_pointer_rtx
, reg
));
14571 RTX_FRAME_RELATED_P (insn
) = 1;
14572 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
14573 plus_constant (stack_pointer_rtx
,
14575 RTX_FRAME_RELATED_P (dwarf
) = 1;
14577 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
14583 if (frame_pointer_needed
)
14584 thumb_set_frame_pointer (offsets
);
14586 /* If we are profiling, make sure no instructions are scheduled before
14587 the call to mcount. Similarly if the user has requested no
14588 scheduling in the prolog. Similarly if we want non-call exceptions
14589 using the EABI unwinder, to prevent faulting instructions from being
14590 swapped with a stack adjustment. */
14591 if (current_function_profile
|| !TARGET_SCHED_PROLOG
14592 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
14593 emit_insn (gen_blockage ());
14595 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
14596 if (live_regs_mask
& 0xff)
14597 cfun
->machine
->lr_save_eliminated
= 0;
14599 /* If the link register is being kept alive, with the return address in it,
14600 then make sure that it does not get reused by the ce2 pass. */
14601 if (cfun
->machine
->lr_save_eliminated
)
14602 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
14607 thumb1_expand_epilogue (void)
14609 HOST_WIDE_INT amount
;
14610 arm_stack_offsets
*offsets
;
14613 /* Naked functions don't have prologues. */
14614 if (IS_NAKED (arm_current_func_type ()))
14617 offsets
= arm_get_frame_offsets ();
14618 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
14620 if (frame_pointer_needed
)
14622 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
14623 amount
= offsets
->locals_base
- offsets
->saved_regs
;
14629 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14630 GEN_INT (amount
)));
14633 /* r3 is always free in the epilogue. */
14634 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
14636 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
14637 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
14641 /* Emit a USE (stack_pointer_rtx), so that
14642 the stack adjustment will not be deleted. */
14643 emit_insn (gen_prologue_use (stack_pointer_rtx
));
14645 if (current_function_profile
|| !TARGET_SCHED_PROLOG
)
14646 emit_insn (gen_blockage ());
14648 /* Emit a clobber for each insn that will be restored in the epilogue,
14649 so that flow2 will get register lifetimes correct. */
14650 for (regno
= 0; regno
< 13; regno
++)
14651 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
14652 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
14654 if (! regs_ever_live
[LR_REGNUM
])
14655 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
14659 thumb1_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
14661 unsigned long live_regs_mask
= 0;
14662 unsigned long l_mask
;
14663 unsigned high_regs_pushed
= 0;
14664 int cfa_offset
= 0;
14667 if (IS_NAKED (arm_current_func_type ()))
14670 if (is_called_in_ARM_mode (current_function_decl
))
14674 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
14675 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
14677 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
14679 /* Generate code sequence to switch us into Thumb mode. */
14680 /* The .code 32 directive has already been emitted by
14681 ASM_DECLARE_FUNCTION_NAME. */
14682 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
14683 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
14685 /* Generate a label, so that the debugger will notice the
14686 change in instruction sets. This label is also used by
14687 the assembler to bypass the ARM code when this function
14688 is called from a Thumb encoded function elsewhere in the
14689 same file. Hence the definition of STUB_NAME here must
14690 agree with the definition in gas/config/tc-arm.c. */
14692 #define STUB_NAME ".real_start_of"
14694 fprintf (f
, "\t.code\t16\n");
14696 if (arm_dllexport_name_p (name
))
14697 name
= arm_strip_name_encoding (name
);
14699 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
14700 fprintf (f
, "\t.thumb_func\n");
14701 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
14704 if (current_function_pretend_args_size
)
14706 /* Output unwind directive for the stack adjustment. */
14707 if (ARM_EABI_UNWIND_TABLES
)
14708 fprintf (f
, "\t.pad #%d\n",
14709 current_function_pretend_args_size
);
14711 if (cfun
->machine
->uses_anonymous_args
)
14715 fprintf (f
, "\tpush\t{");
14717 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
14719 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
14720 regno
<= LAST_ARG_REGNUM
;
14722 asm_fprintf (f
, "%r%s", regno
,
14723 regno
== LAST_ARG_REGNUM
? "" : ", ");
14725 fprintf (f
, "}\n");
14728 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
14729 SP_REGNUM
, SP_REGNUM
,
14730 current_function_pretend_args_size
);
14732 /* We don't need to record the stores for unwinding (would it
14733 help the debugger any if we did?), but record the change in
14734 the stack pointer. */
14735 if (dwarf2out_do_frame ())
14737 char *l
= dwarf2out_cfi_label ();
14739 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
14740 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
14744 /* Get the registers we are going to push. */
14745 live_regs_mask
= thumb1_compute_save_reg_mask ();
14746 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
14747 l_mask
= live_regs_mask
& 0x40ff;
14748 /* Then count how many other high registers will need to be pushed. */
14749 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
14751 if (TARGET_BACKTRACE
)
14754 unsigned work_register
;
14756 /* We have been asked to create a stack backtrace structure.
14757 The code looks like this:
14761 0 sub SP, #16 Reserve space for 4 registers.
14762 2 push {R7} Push low registers.
14763 4 add R7, SP, #20 Get the stack pointer before the push.
14764 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14765 8 mov R7, PC Get hold of the start of this code plus 12.
14766 10 str R7, [SP, #16] Store it.
14767 12 mov R7, FP Get hold of the current frame pointer.
14768 14 str R7, [SP, #4] Store it.
14769 16 mov R7, LR Get hold of the current return address.
14770 18 str R7, [SP, #12] Store it.
14771 20 add R7, SP, #16 Point at the start of the backtrace structure.
14772 22 mov FP, R7 Put this value into the frame pointer. */
14774 work_register
= thumb_find_work_register (live_regs_mask
);
14776 if (ARM_EABI_UNWIND_TABLES
)
14777 asm_fprintf (f
, "\t.pad #16\n");
14780 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14781 SP_REGNUM
, SP_REGNUM
);
14783 if (dwarf2out_do_frame ())
14785 char *l
= dwarf2out_cfi_label ();
14787 cfa_offset
= cfa_offset
+ 16;
14788 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
14793 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14794 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
14799 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14800 offset
+ 16 + current_function_pretend_args_size
);
14802 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14805 /* Make sure that the instruction fetching the PC is in the right place
14806 to calculate "start of backtrace creation code + 12". */
14809 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
14810 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14812 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
14813 ARM_HARD_FRAME_POINTER_REGNUM
);
14814 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14819 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
14820 ARM_HARD_FRAME_POINTER_REGNUM
);
14821 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14823 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
14824 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14828 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
14829 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
14831 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
14833 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14834 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
14836 /* Optimization: If we are not pushing any low registers but we are going
14837 to push some high registers then delay our first push. This will just
14838 be a push of LR and we can combine it with the push of the first high
14840 else if ((l_mask
& 0xff) != 0
14841 || (high_regs_pushed
== 0 && l_mask
))
14842 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
14844 if (high_regs_pushed
)
14846 unsigned pushable_regs
;
14847 unsigned next_hi_reg
;
14849 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
14850 if (live_regs_mask
& (1 << next_hi_reg
))
14853 pushable_regs
= l_mask
& 0xff;
14855 if (pushable_regs
== 0)
14856 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
14858 while (high_regs_pushed
> 0)
14860 unsigned long real_regs_mask
= 0;
14862 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
14864 if (pushable_regs
& (1 << regno
))
14866 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
14868 high_regs_pushed
--;
14869 real_regs_mask
|= (1 << next_hi_reg
);
14871 if (high_regs_pushed
)
14873 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
14875 if (live_regs_mask
& (1 << next_hi_reg
))
14880 pushable_regs
&= ~((1 << regno
) - 1);
14886 /* If we had to find a work register and we have not yet
14887 saved the LR then add it to the list of regs to push. */
14888 if (l_mask
== (1 << LR_REGNUM
))
14890 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
14892 real_regs_mask
| (1 << LR_REGNUM
));
14896 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
14901 /* Handle the case of a double word load into a low register from
14902 a computed memory address. The computed address may involve a
14903 register which is overwritten by the load. */
14905 thumb_load_double_from_address (rtx
*operands
)
14913 gcc_assert (GET_CODE (operands
[0]) == REG
);
14914 gcc_assert (GET_CODE (operands
[1]) == MEM
);
14916 /* Get the memory address. */
14917 addr
= XEXP (operands
[1], 0);
14919 /* Work out how the memory address is computed. */
14920 switch (GET_CODE (addr
))
14923 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14925 if (REGNO (operands
[0]) == REGNO (addr
))
14927 output_asm_insn ("ldr\t%H0, %2", operands
);
14928 output_asm_insn ("ldr\t%0, %1", operands
);
14932 output_asm_insn ("ldr\t%0, %1", operands
);
14933 output_asm_insn ("ldr\t%H0, %2", operands
);
14938 /* Compute <address> + 4 for the high order load. */
14939 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14941 output_asm_insn ("ldr\t%0, %1", operands
);
14942 output_asm_insn ("ldr\t%H0, %2", operands
);
14946 arg1
= XEXP (addr
, 0);
14947 arg2
= XEXP (addr
, 1);
14949 if (CONSTANT_P (arg1
))
14950 base
= arg2
, offset
= arg1
;
14952 base
= arg1
, offset
= arg2
;
14954 gcc_assert (GET_CODE (base
) == REG
);
14956 /* Catch the case of <address> = <reg> + <reg> */
14957 if (GET_CODE (offset
) == REG
)
14959 int reg_offset
= REGNO (offset
);
14960 int reg_base
= REGNO (base
);
14961 int reg_dest
= REGNO (operands
[0]);
14963 /* Add the base and offset registers together into the
14964 higher destination register. */
14965 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
14966 reg_dest
+ 1, reg_base
, reg_offset
);
14968 /* Load the lower destination register from the address in
14969 the higher destination register. */
14970 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
14971 reg_dest
, reg_dest
+ 1);
14973 /* Load the higher destination register from its own address
14975 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
14976 reg_dest
+ 1, reg_dest
+ 1);
14980 /* Compute <address> + 4 for the high order load. */
14981 operands
[2] = adjust_address (operands
[1], SImode
, 4);
14983 /* If the computed address is held in the low order register
14984 then load the high order register first, otherwise always
14985 load the low order register first. */
14986 if (REGNO (operands
[0]) == REGNO (base
))
14988 output_asm_insn ("ldr\t%H0, %2", operands
);
14989 output_asm_insn ("ldr\t%0, %1", operands
);
14993 output_asm_insn ("ldr\t%0, %1", operands
);
14994 output_asm_insn ("ldr\t%H0, %2", operands
);
15000 /* With no registers to worry about we can just load the value
15002 operands
[2] = adjust_address (operands
[1], SImode
, 4);
15004 output_asm_insn ("ldr\t%H0, %2", operands
);
15005 output_asm_insn ("ldr\t%0, %1", operands
);
15009 gcc_unreachable ();
15016 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
15023 if (REGNO (operands
[4]) > REGNO (operands
[5]))
15026 operands
[4] = operands
[5];
15029 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
15030 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
15034 if (REGNO (operands
[4]) > REGNO (operands
[5]))
15037 operands
[4] = operands
[5];
15040 if (REGNO (operands
[5]) > REGNO (operands
[6]))
15043 operands
[5] = operands
[6];
15046 if (REGNO (operands
[4]) > REGNO (operands
[5]))
15049 operands
[4] = operands
[5];
15053 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
15054 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
15058 gcc_unreachable ();
15064 /* Output a call-via instruction for thumb state. */
15066 thumb_call_via_reg (rtx reg
)
15068 int regno
= REGNO (reg
);
15071 gcc_assert (regno
< LR_REGNUM
);
15073 /* If we are in the normal text section we can use a single instance
15074 per compilation unit. If we are doing function sections, then we need
15075 an entry per section, since we can't rely on reachability. */
15076 if (in_section
== text_section
)
15078 thumb_call_reg_needed
= 1;
15080 if (thumb_call_via_label
[regno
] == NULL
)
15081 thumb_call_via_label
[regno
] = gen_label_rtx ();
15082 labelp
= thumb_call_via_label
+ regno
;
15086 if (cfun
->machine
->call_via
[regno
] == NULL
)
15087 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
15088 labelp
= cfun
->machine
->call_via
+ regno
;
15091 output_asm_insn ("bl\t%a0", labelp
);
15095 /* Routines for generating rtl. */
15097 thumb_expand_movmemqi (rtx
*operands
)
15099 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
15100 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
15101 HOST_WIDE_INT len
= INTVAL (operands
[2]);
15102 HOST_WIDE_INT offset
= 0;
15106 emit_insn (gen_movmem12b (out
, in
, out
, in
));
15112 emit_insn (gen_movmem8b (out
, in
, out
, in
));
15118 rtx reg
= gen_reg_rtx (SImode
);
15119 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
15120 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
15127 rtx reg
= gen_reg_rtx (HImode
);
15128 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
15129 plus_constant (in
, offset
))));
15130 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
15138 rtx reg
= gen_reg_rtx (QImode
);
15139 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
15140 plus_constant (in
, offset
))));
15141 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
15147 thumb_reload_out_hi (rtx
*operands
)
15149 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
15152 /* Handle reading a half-word from memory during reload. */
15154 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
15156 gcc_unreachable ();
15159 /* Return the length of a function name prefix
15160 that starts with the character 'c'. */
15162 arm_get_strip_length (int c
)
15166 ARM_NAME_ENCODING_LENGTHS
15171 /* Return a pointer to a function's name with any
15172 and all prefix encodings stripped from it. */
15174 arm_strip_name_encoding (const char *name
)
15178 while ((skip
= arm_get_strip_length (* name
)))
15184 /* If there is a '*' anywhere in the name's prefix, then
15185 emit the stripped name verbatim, otherwise prepend an
15186 underscore if leading underscores are being used. */
15188 arm_asm_output_labelref (FILE *stream
, const char *name
)
15193 while ((skip
= arm_get_strip_length (* name
)))
15195 verbatim
|= (*name
== '*');
15200 fputs (name
, stream
);
15202 asm_fprintf (stream
, "%U%s", name
);
15206 arm_file_start (void)
15210 if (TARGET_UNIFIED_ASM
)
15211 asm_fprintf (asm_out_file
, "\t.syntax unified\n");
15215 const char *fpu_name
;
15216 if (arm_select
[0].string
)
15217 asm_fprintf (asm_out_file
, "\t.cpu %s\n", arm_select
[0].string
);
15218 else if (arm_select
[1].string
)
15219 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_select
[1].string
);
15221 asm_fprintf (asm_out_file
, "\t.cpu %s\n",
15222 all_cores
[arm_default_cpu
].name
);
15224 if (TARGET_SOFT_FLOAT
)
15227 fpu_name
= "softvfp";
15229 fpu_name
= "softfpa";
15233 switch (arm_fpu_arch
)
15238 case FPUTYPE_FPA_EMU2
:
15241 case FPUTYPE_FPA_EMU3
:
15244 case FPUTYPE_MAVERICK
:
15245 fpu_name
= "maverick";
15248 if (TARGET_HARD_FLOAT
)
15249 asm_fprintf (asm_out_file
, "\t.eabi_attribute 27, 3\n");
15250 if (TARGET_HARD_FLOAT_ABI
)
15251 asm_fprintf (asm_out_file
, "\t.eabi_attribute 28, 1\n");
15258 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_name
);
15260 /* Some of these attributes only apply when the corresponding features
15261 are used. However we don't have any easy way of figuring this out.
15262 Conservatively record the setting that would have been used. */
15264 /* Tag_ABI_PCS_wchar_t. */
15265 asm_fprintf (asm_out_file
, "\t.eabi_attribute 18, %d\n",
15266 (int)WCHAR_TYPE_SIZE
/ BITS_PER_UNIT
);
15268 /* Tag_ABI_FP_rounding. */
15269 if (flag_rounding_math
)
15270 asm_fprintf (asm_out_file
, "\t.eabi_attribute 19, 1\n");
15271 if (!flag_unsafe_math_optimizations
)
15273 /* Tag_ABI_FP_denomal. */
15274 asm_fprintf (asm_out_file
, "\t.eabi_attribute 20, 1\n");
15275 /* Tag_ABI_FP_exceptions. */
15276 asm_fprintf (asm_out_file
, "\t.eabi_attribute 21, 1\n");
15278 /* Tag_ABI_FP_user_exceptions. */
15279 if (flag_signaling_nans
)
15280 asm_fprintf (asm_out_file
, "\t.eabi_attribute 22, 1\n");
15281 /* Tag_ABI_FP_number_model. */
15282 asm_fprintf (asm_out_file
, "\t.eabi_attribute 23, %d\n",
15283 flag_finite_math_only
? 1 : 3);
15285 /* Tag_ABI_align8_needed. */
15286 asm_fprintf (asm_out_file
, "\t.eabi_attribute 24, 1\n");
15287 /* Tag_ABI_align8_preserved. */
15288 asm_fprintf (asm_out_file
, "\t.eabi_attribute 25, 1\n");
15289 /* Tag_ABI_enum_size. */
15290 asm_fprintf (asm_out_file
, "\t.eabi_attribute 26, %d\n",
15291 flag_short_enums
? 1 : 2);
15293 /* Tag_ABI_optimization_goals. */
15296 else if (optimize
>= 2)
15302 asm_fprintf (asm_out_file
, "\t.eabi_attribute 30, %d\n", val
);
15304 default_file_start();
15308 arm_file_end (void)
15312 if (NEED_INDICATE_EXEC_STACK
)
15313 /* Add .note.GNU-stack. */
15314 file_end_indicate_exec_stack ();
15316 if (! thumb_call_reg_needed
)
15319 switch_to_section (text_section
);
15320 asm_fprintf (asm_out_file
, "\t.code 16\n");
15321 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
15323 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
15325 rtx label
= thumb_call_via_label
[regno
];
15329 targetm
.asm_out
.internal_label (asm_out_file
, "L",
15330 CODE_LABEL_NUMBER (label
));
15331 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
15338 #ifdef AOF_ASSEMBLER
15339 /* Special functions only needed when producing AOF syntax assembler. */
15343 struct pic_chain
* next
;
15344 const char * symname
;
15347 static struct pic_chain
* aof_pic_chain
= NULL
;
15350 aof_pic_entry (rtx x
)
15352 struct pic_chain
** chainp
;
15355 if (aof_pic_label
== NULL_RTX
)
15357 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
15360 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
15361 offset
+= 4, chainp
= &(*chainp
)->next
)
15362 if ((*chainp
)->symname
== XSTR (x
, 0))
15363 return plus_constant (aof_pic_label
, offset
);
15365 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
15366 (*chainp
)->next
= NULL
;
15367 (*chainp
)->symname
= XSTR (x
, 0);
15368 return plus_constant (aof_pic_label
, offset
);
15372 aof_dump_pic_table (FILE *f
)
15374 struct pic_chain
* chain
;
15376 if (aof_pic_chain
== NULL
)
15379 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
15380 PIC_OFFSET_TABLE_REGNUM
,
15381 PIC_OFFSET_TABLE_REGNUM
);
15382 fputs ("|x$adcons|\n", f
);
15384 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
15386 fputs ("\tDCD\t", f
);
15387 assemble_name (f
, chain
->symname
);
15392 int arm_text_section_count
= 1;
15394 /* A get_unnamed_section callback for switching to the text section. */
15397 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
15399 fprintf (asm_out_file
, "\tAREA |C$$code%d|, CODE, READONLY",
15400 arm_text_section_count
++);
15402 fprintf (asm_out_file
, ", PIC, REENTRANT");
15403 fprintf (asm_out_file
, "\n");
15406 static int arm_data_section_count
= 1;
15408 /* A get_unnamed_section callback for switching to the data section. */
15411 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
15413 fprintf (asm_out_file
, "\tAREA |C$$data%d|, DATA\n",
15414 arm_data_section_count
++);
15417 /* Implement TARGET_ASM_INIT_SECTIONS.
15419 AOF Assembler syntax is a nightmare when it comes to areas, since once
15420 we change from one area to another, we can't go back again. Instead,
15421 we must create a new area with the same attributes and add the new output
15422 to that. Unfortunately, there is nothing we can do here to guarantee that
15423 two areas with the same attributes will be linked adjacently in the
15424 resulting executable, so we have to be careful not to do pc-relative
15425 addressing across such boundaries. */
15428 aof_asm_init_sections (void)
15430 text_section
= get_unnamed_section (SECTION_CODE
,
15431 aof_output_text_section_asm_op
, NULL
);
15432 data_section
= get_unnamed_section (SECTION_WRITE
,
15433 aof_output_data_section_asm_op
, NULL
);
15434 readonly_data_section
= text_section
;
15438 zero_init_section (void)
15440 static int zero_init_count
= 1;
15442 fprintf (asm_out_file
, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count
++);
15446 /* The AOF assembler is religiously strict about declarations of
15447 imported and exported symbols, so that it is impossible to declare
15448 a function as imported near the beginning of the file, and then to
15449 export it later on. It is, however, possible to delay the decision
15450 until all the functions in the file have been compiled. To get
15451 around this, we maintain a list of the imports and exports, and
15452 delete from it any that are subsequently defined. At the end of
15453 compilation we spit the remainder of the list out before the END
15458 struct import
* next
;
15462 static struct import
* imports_list
= NULL
;
15465 aof_add_import (const char *name
)
15467 struct import
* new;
15469 for (new = imports_list
; new; new = new->next
)
15470 if (new->name
== name
)
15473 new = (struct import
*) xmalloc (sizeof (struct import
));
15474 new->next
= imports_list
;
15475 imports_list
= new;
15480 aof_delete_import (const char *name
)
15482 struct import
** old
;
15484 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
15486 if ((*old
)->name
== name
)
15488 *old
= (*old
)->next
;
15494 int arm_main_function
= 0;
15497 aof_dump_imports (FILE *f
)
15499 /* The AOF assembler needs this to cause the startup code to be extracted
15500 from the library. Brining in __main causes the whole thing to work
15502 if (arm_main_function
)
15504 switch_to_section (text_section
);
15505 fputs ("\tIMPORT __main\n", f
);
15506 fputs ("\tDCD __main\n", f
);
15509 /* Now dump the remaining imports. */
15510 while (imports_list
)
15512 fprintf (f
, "\tIMPORT\t");
15513 assemble_name (f
, imports_list
->name
);
15515 imports_list
= imports_list
->next
;
15520 aof_globalize_label (FILE *stream
, const char *name
)
15522 default_globalize_label (stream
, name
);
15523 if (! strcmp (name
, "main"))
15524 arm_main_function
= 1;
15528 aof_file_start (void)
15530 fputs ("__r0\tRN\t0\n", asm_out_file
);
15531 fputs ("__a1\tRN\t0\n", asm_out_file
);
15532 fputs ("__a2\tRN\t1\n", asm_out_file
);
15533 fputs ("__a3\tRN\t2\n", asm_out_file
);
15534 fputs ("__a4\tRN\t3\n", asm_out_file
);
15535 fputs ("__v1\tRN\t4\n", asm_out_file
);
15536 fputs ("__v2\tRN\t5\n", asm_out_file
);
15537 fputs ("__v3\tRN\t6\n", asm_out_file
);
15538 fputs ("__v4\tRN\t7\n", asm_out_file
);
15539 fputs ("__v5\tRN\t8\n", asm_out_file
);
15540 fputs ("__v6\tRN\t9\n", asm_out_file
);
15541 fputs ("__sl\tRN\t10\n", asm_out_file
);
15542 fputs ("__fp\tRN\t11\n", asm_out_file
);
15543 fputs ("__ip\tRN\t12\n", asm_out_file
);
15544 fputs ("__sp\tRN\t13\n", asm_out_file
);
15545 fputs ("__lr\tRN\t14\n", asm_out_file
);
15546 fputs ("__pc\tRN\t15\n", asm_out_file
);
15547 fputs ("__f0\tFN\t0\n", asm_out_file
);
15548 fputs ("__f1\tFN\t1\n", asm_out_file
);
15549 fputs ("__f2\tFN\t2\n", asm_out_file
);
15550 fputs ("__f3\tFN\t3\n", asm_out_file
);
15551 fputs ("__f4\tFN\t4\n", asm_out_file
);
15552 fputs ("__f5\tFN\t5\n", asm_out_file
);
15553 fputs ("__f6\tFN\t6\n", asm_out_file
);
15554 fputs ("__f7\tFN\t7\n", asm_out_file
);
15555 switch_to_section (text_section
);
15559 aof_file_end (void)
15562 aof_dump_pic_table (asm_out_file
);
15564 aof_dump_imports (asm_out_file
);
15565 fputs ("\tEND\n", asm_out_file
);
15567 #endif /* AOF_ASSEMBLER */
15570 /* Symbols in the text segment can be accessed without indirecting via the
15571 constant pool; it may take an extra binary operation, but this is still
15572 faster than indirecting via memory. Don't do this when not optimizing,
15573 since we won't be calculating al of the offsets necessary to do this
15577 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
15579 /* This doesn't work with AOF syntax, since the string table may be in
15580 a different AREA. */
15581 #ifndef AOF_ASSEMBLER
15582 if (optimize
> 0 && TREE_CONSTANT (decl
))
15583 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
15586 /* If we are referencing a function that is weak then encode a long call
15587 flag in the function name, otherwise if the function is static or
15588 or known to be defined in this file then encode a short call flag. */
15589 if (first
&& DECL_P (decl
))
15591 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
15592 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
15593 else if (! TREE_PUBLIC (decl
))
15594 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
15597 default_encode_section_info (decl
, rtl
, first
);
15599 #endif /* !ARM_PE */
15602 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
15604 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
15605 && !strcmp (prefix
, "L"))
15607 arm_ccfsm_state
= 0;
15608 arm_target_insn
= NULL
;
15610 default_internal_label (stream
, prefix
, labelno
);
15613 /* Output code to add DELTA to the first argument, and then jump
15614 to FUNCTION. Used for C++ multiple inheritance. */
15616 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
15617 HOST_WIDE_INT delta
,
15618 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
15621 static int thunk_label
= 0;
15624 int mi_delta
= delta
;
15625 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
15627 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
15630 mi_delta
= - mi_delta
;
15631 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15634 int labelno
= thunk_label
++;
15635 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
15636 fputs ("\tldr\tr12, ", file
);
15637 assemble_name (file
, label
);
15638 fputc ('\n', file
);
15641 /* If we are generating PIC, the ldr instruction below loads
15642 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15643 the address of the add + 8, so we have:
15645 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15648 Note that we have "+ 1" because some versions of GNU ld
15649 don't set the low bit of the result for R_ARM_REL32
15650 relocations against thumb function symbols. */
15651 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
15652 assemble_name (file
, labelpc
);
15653 fputs (":\n", file
);
15654 fputs ("\tadd\tr12, pc, r12\n", file
);
15657 /* TODO: Use movw/movt for large constants when available. */
15658 while (mi_delta
!= 0)
15660 if ((mi_delta
& (3 << shift
)) == 0)
15664 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
15665 mi_op
, this_regno
, this_regno
,
15666 mi_delta
& (0xff << shift
));
15667 mi_delta
&= ~(0xff << shift
);
15673 fprintf (file
, "\tbx\tr12\n");
15674 ASM_OUTPUT_ALIGN (file
, 2);
15675 assemble_name (file
, label
);
15676 fputs (":\n", file
);
15679 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15680 rtx tem
= XEXP (DECL_RTL (function
), 0);
15681 tem
= gen_rtx_PLUS (GET_MODE (tem
), tem
, GEN_INT (-7));
15682 tem
= gen_rtx_MINUS (GET_MODE (tem
),
15684 gen_rtx_SYMBOL_REF (Pmode
,
15685 ggc_strdup (labelpc
)));
15686 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
15689 /* Output ".word .LTHUNKn". */
15690 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
15694 fputs ("\tb\t", file
);
15695 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
15696 if (NEED_PLT_RELOC
)
15697 fputs ("(PLT)", file
);
15698 fputc ('\n', file
);
15703 arm_emit_vector_const (FILE *file
, rtx x
)
15706 const char * pattern
;
15708 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
15710 switch (GET_MODE (x
))
15712 case V2SImode
: pattern
= "%08x"; break;
15713 case V4HImode
: pattern
= "%04x"; break;
15714 case V8QImode
: pattern
= "%02x"; break;
15715 default: gcc_unreachable ();
15718 fprintf (file
, "0x");
15719 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
15723 element
= CONST_VECTOR_ELT (x
, i
);
15724 fprintf (file
, pattern
, INTVAL (element
));
15731 arm_output_load_gr (rtx
*operands
)
15738 if (GET_CODE (operands
[1]) != MEM
15739 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
15740 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
15741 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
15742 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
15743 return "wldrw%?\t%0, %1";
15745 /* Fix up an out-of-range load of a GR register. */
15746 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
15747 wcgr
= operands
[0];
15749 output_asm_insn ("ldr%?\t%0, %1", operands
);
15751 operands
[0] = wcgr
;
15753 output_asm_insn ("tmcr%?\t%0, %1", operands
);
15754 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
15759 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
15761 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
15762 named arg and all anonymous args onto the stack.
15763 XXX I know the prologue shouldn't be pushing registers, but it is faster
15767 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
15768 enum machine_mode mode ATTRIBUTE_UNUSED
,
15769 tree type ATTRIBUTE_UNUSED
,
15771 int second_time ATTRIBUTE_UNUSED
)
15773 cfun
->machine
->uses_anonymous_args
= 1;
15774 if (cum
->nregs
< NUM_ARG_REGS
)
15775 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
15778 /* Return nonzero if the CONSUMER instruction (a store) does not need
15779 PRODUCER's value to calculate the address. */
15782 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
15784 rtx value
= PATTERN (producer
);
15785 rtx addr
= PATTERN (consumer
);
15787 if (GET_CODE (value
) == COND_EXEC
)
15788 value
= COND_EXEC_CODE (value
);
15789 if (GET_CODE (value
) == PARALLEL
)
15790 value
= XVECEXP (value
, 0, 0);
15791 value
= XEXP (value
, 0);
15792 if (GET_CODE (addr
) == COND_EXEC
)
15793 addr
= COND_EXEC_CODE (addr
);
15794 if (GET_CODE (addr
) == PARALLEL
)
15795 addr
= XVECEXP (addr
, 0, 0);
15796 addr
= XEXP (addr
, 0);
15798 return !reg_overlap_mentioned_p (value
, addr
);
15801 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15802 have an early register shift value or amount dependency on the
15803 result of PRODUCER. */
15806 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
15808 rtx value
= PATTERN (producer
);
15809 rtx op
= PATTERN (consumer
);
15812 if (GET_CODE (value
) == COND_EXEC
)
15813 value
= COND_EXEC_CODE (value
);
15814 if (GET_CODE (value
) == PARALLEL
)
15815 value
= XVECEXP (value
, 0, 0);
15816 value
= XEXP (value
, 0);
15817 if (GET_CODE (op
) == COND_EXEC
)
15818 op
= COND_EXEC_CODE (op
);
15819 if (GET_CODE (op
) == PARALLEL
)
15820 op
= XVECEXP (op
, 0, 0);
15823 early_op
= XEXP (op
, 0);
15824 /* This is either an actual independent shift, or a shift applied to
15825 the first operand of another operation. We want the whole shift
15827 if (GET_CODE (early_op
) == REG
)
15830 return !reg_overlap_mentioned_p (value
, early_op
);
15833 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
15834 have an early register shift value dependency on the result of
15838 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
15840 rtx value
= PATTERN (producer
);
15841 rtx op
= PATTERN (consumer
);
15844 if (GET_CODE (value
) == COND_EXEC
)
15845 value
= COND_EXEC_CODE (value
);
15846 if (GET_CODE (value
) == PARALLEL
)
15847 value
= XVECEXP (value
, 0, 0);
15848 value
= XEXP (value
, 0);
15849 if (GET_CODE (op
) == COND_EXEC
)
15850 op
= COND_EXEC_CODE (op
);
15851 if (GET_CODE (op
) == PARALLEL
)
15852 op
= XVECEXP (op
, 0, 0);
15855 early_op
= XEXP (op
, 0);
15857 /* This is either an actual independent shift, or a shift applied to
15858 the first operand of another operation. We want the value being
15859 shifted, in either case. */
15860 if (GET_CODE (early_op
) != REG
)
15861 early_op
= XEXP (early_op
, 0);
15863 return !reg_overlap_mentioned_p (value
, early_op
);
15866 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15867 have an early register mult dependency on the result of
15871 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
15873 rtx value
= PATTERN (producer
);
15874 rtx op
= PATTERN (consumer
);
15876 if (GET_CODE (value
) == COND_EXEC
)
15877 value
= COND_EXEC_CODE (value
);
15878 if (GET_CODE (value
) == PARALLEL
)
15879 value
= XVECEXP (value
, 0, 0);
15880 value
= XEXP (value
, 0);
15881 if (GET_CODE (op
) == COND_EXEC
)
15882 op
= COND_EXEC_CODE (op
);
15883 if (GET_CODE (op
) == PARALLEL
)
15884 op
= XVECEXP (op
, 0, 0);
15887 return (GET_CODE (op
) == PLUS
15888 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
15892 /* We can't rely on the caller doing the proper promotion when
15893 using APCS or ATPCS. */
15896 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
15898 return !TARGET_AAPCS_BASED
;
15902 /* AAPCS based ABIs use short enums by default. */
15905 arm_default_short_enums (void)
15907 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
15911 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15914 arm_align_anon_bitfield (void)
15916 return TARGET_AAPCS_BASED
;
15920 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15923 arm_cxx_guard_type (void)
15925 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
15929 /* The EABI says test the least significant bit of a guard variable. */
15932 arm_cxx_guard_mask_bit (void)
15934 return TARGET_AAPCS_BASED
;
15938 /* The EABI specifies that all array cookies are 8 bytes long. */
15941 arm_get_cookie_size (tree type
)
15945 if (!TARGET_AAPCS_BASED
)
15946 return default_cxx_get_cookie_size (type
);
15948 size
= build_int_cst (sizetype
, 8);
15953 /* The EABI says that array cookies should also contain the element size. */
15956 arm_cookie_has_size (void)
15958 return TARGET_AAPCS_BASED
;
15962 /* The EABI says constructors and destructors should return a pointer to
15963 the object constructed/destroyed. */
15966 arm_cxx_cdtor_returns_this (void)
15968 return TARGET_AAPCS_BASED
;
15971 /* The EABI says that an inline function may never be the key
15975 arm_cxx_key_method_may_be_inline (void)
15977 return !TARGET_AAPCS_BASED
;
15981 arm_cxx_determine_class_data_visibility (tree decl
)
15983 if (!TARGET_AAPCS_BASED
)
15986 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15987 is exported. However, on systems without dynamic vague linkage,
15988 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15989 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
15990 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
15992 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
15993 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
15997 arm_cxx_class_data_always_comdat (void)
15999 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
16000 vague linkage if the class has no key function. */
16001 return !TARGET_AAPCS_BASED
;
16005 /* The EABI says __aeabi_atexit should be used to register static
16009 arm_cxx_use_aeabi_atexit (void)
16011 return TARGET_AAPCS_BASED
;
16016 arm_set_return_address (rtx source
, rtx scratch
)
16018 arm_stack_offsets
*offsets
;
16019 HOST_WIDE_INT delta
;
16021 unsigned long saved_regs
;
16023 saved_regs
= arm_compute_save_reg_mask ();
16025 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
16026 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
16029 if (frame_pointer_needed
)
16030 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
16033 /* LR will be the first saved register. */
16034 offsets
= arm_get_frame_offsets ();
16035 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
16040 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
16041 GEN_INT (delta
& ~4095)));
16046 addr
= stack_pointer_rtx
;
16048 addr
= plus_constant (addr
, delta
);
16050 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
16056 thumb_set_return_address (rtx source
, rtx scratch
)
16058 arm_stack_offsets
*offsets
;
16059 HOST_WIDE_INT delta
;
16060 HOST_WIDE_INT limit
;
16063 unsigned long mask
;
16065 emit_insn (gen_rtx_USE (VOIDmode
, source
));
16067 mask
= thumb1_compute_save_reg_mask ();
16068 if (mask
& (1 << LR_REGNUM
))
16070 offsets
= arm_get_frame_offsets ();
16073 /* Find the saved regs. */
16074 if (frame_pointer_needed
)
16076 delta
= offsets
->soft_frame
- offsets
->saved_args
;
16077 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
16083 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
16086 /* Allow for the stack frame. */
16087 if (TARGET_THUMB1
&& TARGET_BACKTRACE
)
16089 /* The link register is always the first saved register. */
16092 /* Construct the address. */
16093 addr
= gen_rtx_REG (SImode
, reg
);
16096 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
16097 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
16101 addr
= plus_constant (addr
, delta
);
16103 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
16106 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
16109 /* Implements target hook vector_mode_supported_p. */
16111 arm_vector_mode_supported_p (enum machine_mode mode
)
16113 if ((mode
== V2SImode
)
16114 || (mode
== V4HImode
)
16115 || (mode
== V8QImode
))
16121 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16122 ARM insns and therefore guarantee that the shift count is modulo 256.
16123 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16124 guarantee no particular behavior for out-of-range counts. */
16126 static unsigned HOST_WIDE_INT
16127 arm_shift_truncation_mask (enum machine_mode mode
)
16129 return mode
== SImode
? 255 : 0;
16133 /* Map internal gcc register numbers to DWARF2 register numbers. */
16136 arm_dbx_register_number (unsigned int regno
)
16141 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16142 compatibility. The EABI defines them as registers 96-103. */
16143 if (IS_FPA_REGNUM (regno
))
16144 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
16146 if (IS_VFP_REGNUM (regno
))
16147 return 64 + regno
- FIRST_VFP_REGNUM
;
16149 if (IS_IWMMXT_GR_REGNUM (regno
))
16150 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
16152 if (IS_IWMMXT_REGNUM (regno
))
16153 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
16155 gcc_unreachable ();
16159 #ifdef TARGET_UNWIND_INFO
16160 /* Emit unwind directives for a store-multiple instruction or stack pointer
16161 push during alignment.
16162 These should only ever be generated by the function prologue code, so
16163 expect them to have a particular form. */
16166 arm_unwind_emit_sequence (FILE * asm_out_file
, rtx p
)
16169 HOST_WIDE_INT offset
;
16170 HOST_WIDE_INT nregs
;
16176 e
= XVECEXP (p
, 0, 0);
16177 if (GET_CODE (e
) != SET
)
16180 /* First insn will adjust the stack pointer. */
16181 if (GET_CODE (e
) != SET
16182 || GET_CODE (XEXP (e
, 0)) != REG
16183 || REGNO (XEXP (e
, 0)) != SP_REGNUM
16184 || GET_CODE (XEXP (e
, 1)) != PLUS
)
16187 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
16188 nregs
= XVECLEN (p
, 0) - 1;
16190 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
16193 /* The function prologue may also push pc, but not annotate it as it is
16194 never restored. We turn this into a stack pointer adjustment. */
16195 if (nregs
* 4 == offset
- 4)
16197 fprintf (asm_out_file
, "\t.pad #4\n");
16201 fprintf (asm_out_file
, "\t.save {");
16203 else if (IS_VFP_REGNUM (reg
))
16206 fprintf (asm_out_file
, "\t.vsave {");
16208 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
16210 /* FPA registers are done differently. */
16211 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
16215 /* Unknown register type. */
16218 /* If the stack increment doesn't match the size of the saved registers,
16219 something has gone horribly wrong. */
16220 if (offset
!= nregs
* reg_size
)
16225 /* The remaining insns will describe the stores. */
16226 for (i
= 1; i
<= nregs
; i
++)
16228 /* Expect (set (mem <addr>) (reg)).
16229 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16230 e
= XVECEXP (p
, 0, i
);
16231 if (GET_CODE (e
) != SET
16232 || GET_CODE (XEXP (e
, 0)) != MEM
16233 || GET_CODE (XEXP (e
, 1)) != REG
)
16236 reg
= REGNO (XEXP (e
, 1));
16241 fprintf (asm_out_file
, ", ");
16242 /* We can't use %r for vfp because we need to use the
16243 double precision register names. */
16244 if (IS_VFP_REGNUM (reg
))
16245 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
16247 asm_fprintf (asm_out_file
, "%r", reg
);
16249 #ifdef ENABLE_CHECKING
16250 /* Check that the addresses are consecutive. */
16251 e
= XEXP (XEXP (e
, 0), 0);
16252 if (GET_CODE (e
) == PLUS
)
16254 offset
+= reg_size
;
16255 if (GET_CODE (XEXP (e
, 0)) != REG
16256 || REGNO (XEXP (e
, 0)) != SP_REGNUM
16257 || GET_CODE (XEXP (e
, 1)) != CONST_INT
16258 || offset
!= INTVAL (XEXP (e
, 1)))
16262 || GET_CODE (e
) != REG
16263 || REGNO (e
) != SP_REGNUM
)
16267 fprintf (asm_out_file
, "}\n");
16270 /* Emit unwind directives for a SET. */
16273 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
16281 switch (GET_CODE (e0
))
16284 /* Pushing a single register. */
16285 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
16286 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
16287 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
16290 asm_fprintf (asm_out_file
, "\t.save ");
16291 if (IS_VFP_REGNUM (REGNO (e1
)))
16292 asm_fprintf(asm_out_file
, "{d%d}\n",
16293 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
16295 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
16299 if (REGNO (e0
) == SP_REGNUM
)
16301 /* A stack increment. */
16302 if (GET_CODE (e1
) != PLUS
16303 || GET_CODE (XEXP (e1
, 0)) != REG
16304 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
16305 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
16308 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
16309 -INTVAL (XEXP (e1
, 1)));
16311 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
16313 HOST_WIDE_INT offset
;
16315 if (GET_CODE (e1
) == PLUS
)
16317 if (GET_CODE (XEXP (e1
, 0)) != REG
16318 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
16320 reg
= REGNO (XEXP (e1
, 0));
16321 offset
= INTVAL (XEXP (e1
, 1));
16322 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
16323 HARD_FRAME_POINTER_REGNUM
, reg
,
16324 INTVAL (XEXP (e1
, 1)));
16326 else if (GET_CODE (e1
) == REG
)
16329 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
16330 HARD_FRAME_POINTER_REGNUM
, reg
);
16335 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
16337 /* Move from sp to reg. */
16338 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
16340 else if (GET_CODE (e1
) == PLUS
16341 && GET_CODE (XEXP (e1
, 0)) == REG
16342 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
16343 && GET_CODE (XEXP (e1
, 1)) == CONST_INT
)
16345 /* Set reg to offset from sp. */
16346 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
16347 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
16349 else if (GET_CODE (e1
) == UNSPEC
&& XINT (e1
, 1) == UNSPEC_STACK_ALIGN
)
16351 /* Stack pointer save before alignment. */
16353 asm_fprintf (asm_out_file
, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16366 /* Emit unwind directives for the given insn. */
16369 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
16373 if (!ARM_EABI_UNWIND_TABLES
)
16376 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
16379 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
16381 pat
= XEXP (pat
, 0);
16383 pat
= PATTERN (insn
);
16385 switch (GET_CODE (pat
))
16388 arm_unwind_emit_set (asm_out_file
, pat
);
16392 /* Store multiple. */
16393 arm_unwind_emit_sequence (asm_out_file
, pat
);
16402 /* Output a reference from a function exception table to the type_info
16403 object X. The EABI specifies that the symbol should be relocated by
16404 an R_ARM_TARGET2 relocation. */
16407 arm_output_ttype (rtx x
)
16409 fputs ("\t.word\t", asm_out_file
);
16410 output_addr_const (asm_out_file
, x
);
16411 /* Use special relocations for symbol references. */
16412 if (GET_CODE (x
) != CONST_INT
)
16413 fputs ("(TARGET2)", asm_out_file
);
16414 fputc ('\n', asm_out_file
);
16418 #endif /* TARGET_UNWIND_INFO */
16421 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16422 stack alignment. */
16425 arm_dwarf_handle_frame_unspec (const char *label
, rtx pattern
, int index
)
16427 rtx unspec
= SET_SRC (pattern
);
16428 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
16432 case UNSPEC_STACK_ALIGN
:
16433 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16434 put anything on the stack, so hopefully it won't matter.
16435 CFA = SP will be correct after alignment. */
16436 dwarf2out_reg_save_reg (label
, stack_pointer_rtx
,
16437 SET_DEST (pattern
));
16440 gcc_unreachable ();
16445 /* Output unwind directives for the start/end of a function. */
16448 arm_output_fn_unwind (FILE * f
, bool prologue
)
16450 if (!ARM_EABI_UNWIND_TABLES
)
16454 fputs ("\t.fnstart\n", f
);
16456 fputs ("\t.fnend\n", f
);
16460 arm_emit_tls_decoration (FILE *fp
, rtx x
)
16462 enum tls_reloc reloc
;
16465 val
= XVECEXP (x
, 0, 0);
16466 reloc
= INTVAL (XVECEXP (x
, 0, 1));
16468 output_addr_const (fp
, val
);
16473 fputs ("(tlsgd)", fp
);
16476 fputs ("(tlsldm)", fp
);
16479 fputs ("(tlsldo)", fp
);
16482 fputs ("(gottpoff)", fp
);
16485 fputs ("(tpoff)", fp
);
16488 gcc_unreachable ();
16496 fputs (" + (. - ", fp
);
16497 output_addr_const (fp
, XVECEXP (x
, 0, 2));
16499 output_addr_const (fp
, XVECEXP (x
, 0, 3));
16510 arm_output_addr_const_extra (FILE *fp
, rtx x
)
16512 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
16513 return arm_emit_tls_decoration (fp
, x
);
16514 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
16517 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
16519 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
16520 assemble_name_raw (fp
, label
);
16524 else if (GET_CODE (x
) == CONST_VECTOR
)
16525 return arm_emit_vector_const (fp
, x
);
16530 /* Output assembly for a shift instruction.
16531 SET_FLAGS determines how the instruction modifies the condition codes.
16532 0 - Do not set condition codes.
16533 1 - Set condition codes.
16534 2 - Use smallest instruction. */
16536 arm_output_shift(rtx
* operands
, int set_flags
)
16539 static const char flag_chars
[3] = {'?', '.', '!'};
16544 c
= flag_chars
[set_flags
];
16545 if (TARGET_UNIFIED_ASM
)
16547 shift
= shift_op(operands
[3], &val
);
16551 operands
[2] = GEN_INT(val
);
16552 sprintf (pattern
, "%s%%%c\t%%0, %%1, %%2", shift
, c
);
16555 sprintf (pattern
, "mov%%%c\t%%0, %%1", c
);
16558 sprintf (pattern
, "mov%%%c\t%%0, %%1%%S3", c
);
16559 output_asm_insn (pattern
, operands
);
16563 /* Output a Thumb-2 casesi instruction. */
16565 thumb2_output_casesi (rtx
*operands
)
16567 rtx diff_vec
= PATTERN (next_real_insn (operands
[2]));
16569 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
16571 output_asm_insn ("cmp\t%0, %1", operands
);
16572 output_asm_insn ("bhi\t%l3", operands
);
16573 switch (GET_MODE(diff_vec
))
16576 return "tbb\t[%|pc, %0]";
16578 return "tbh\t[%|pc, %0, lsl #1]";
16582 output_asm_insn ("adr\t%4, %l2", operands
);
16583 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands
);
16584 output_asm_insn ("add\t%4, %4, %5", operands
);
16589 output_asm_insn ("adr\t%4, %l2", operands
);
16590 return "ldr\t%|pc, [%4, %0, lsl #2]";
16593 gcc_unreachable ();
16597 #include "gt-arm.h"