gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 /* combine_instructions may try to replace the right hand side of the
 127    second instruction with the value of an associated REG_EQUAL note
 128    before throwing it at try_combine.  That is problematic when there
 129    is a REG_DEAD note for a register used in the old right hand side
 130    and can cause distribute_notes to do wrong things.  This is the
 131    second instruction if it has been so modified, null otherwise.  */
 132
 133 static rtx i2mod;
 134
 135 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 136
 137 static rtx i2mod_old_rhs;
 138
 139 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 140
 141 static rtx i2mod_new_rhs;
 142 \f
 143 /* Vector mapping INSN_UIDs to cuids.
 144    The cuids are like uids but increase monotonically always.
 145    Combine always uses cuids so that it can compare them.
 146    But actually renumbering the uids, which we used to do,
 147    proves to be a bad idea because it makes it hard to compare
 148    the dumps produced by earlier passes with those from later passes.  */
 149
 150 static int *uid_cuid;
 151 static int max_uid_cuid;
 152
 153 /* Get the cuid of an insn.  */
 154
 155 #define INSN_CUID(INSN) \
 156 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 157
 158 /* Maximum register number, which is the size of the tables below.  */
 159
 160 static unsigned int combine_max_regno;
 161
 162 struct reg_stat {
 163   /* Record last point of death of (hard or pseudo) register n.  */
 164   rtx                           last_death;
 165
 166   /* Record last point of modification of (hard or pseudo) register n.  */
 167   rtx                           last_set;
 168
 169   /* The next group of fields allows the recording of the last value assigned
 170      to (hard or pseudo) register n.  We use this information to see if an
 171      operation being processed is redundant given a prior operation performed
 172      on the register.  For example, an `and' with a constant is redundant if
 173      all the zero bits are already known to be turned off.
 174
 175      We use an approach similar to that used by cse, but change it in the
 176      following ways:
 177
 178      (1) We do not want to reinitialize at each label.
 179      (2) It is useful, but not critical, to know the actual value assigned
 180          to a register.  Often just its form is helpful.
 181
 182      Therefore, we maintain the following fields:
 183
 184      last_set_value             the last value assigned
 185      last_set_label             records the value of label_tick when the
 186                                 register was assigned
 187      last_set_table_tick        records the value of label_tick when a
 188                                 value using the register is assigned
 189      last_set_invalid           set to nonzero when it is not valid
 190                                 to use the value of this register in some
 191                                 register's value
 192
 193      To understand the usage of these tables, it is important to understand
 194      the distinction between the value in last_set_value being valid and
 195      the register being validly contained in some other expression in the
 196      table.
 197
 198      (The next two parameters are out of date).
 199
 200      reg_stat[i].last_set_value is valid if it is nonzero, and either
 201      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 202
 203      Register I may validly appear in any expression returned for the value
 204      of another register if reg_n_sets[i] is 1.  It may also appear in the
 205      value for register J if reg_stat[j].last_set_invalid is zero, or
 206      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 207
 208      If an expression is found in the table containing a register which may
 209      not validly appear in an expression, the register is replaced by
 210      something that won't match, (clobber (const_int 0)).  */
 211
 212   /* Record last value assigned to (hard or pseudo) register n.  */
 213
 214   rtx                           last_set_value;
 215
 216   /* Record the value of label_tick when an expression involving register n
 217      is placed in last_set_value.  */
 218
 219   int                           last_set_table_tick;
 220
 221   /* Record the value of label_tick when the value for register n is placed in
 222      last_set_value.  */
 223
 224   int                           last_set_label;
 225
 226   /* These fields are maintained in parallel with last_set_value and are
 227      used to store the mode in which the register was last set, the bits
 228      that were known to be zero when it was last set, and the number of
 229      sign bits copies it was known to have when it was last set.  */
 230
 231   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 232   char                          last_set_sign_bit_copies;
 233   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 234
 235   /* Set nonzero if references to register n in expressions should not be
 236      used.  last_set_invalid is set nonzero when this register is being
 237      assigned to and last_set_table_tick == label_tick.  */
 238
 239   char                          last_set_invalid;
 240
 241   /* Some registers that are set more than once and used in more than one
 242      basic block are nevertheless always set in similar ways.  For example,
 243      a QImode register may be loaded from memory in two places on a machine
 244      where byte loads zero extend.
 245
 246      We record in the following fields if a register has some leading bits
 247      that are always equal to the sign bit, and what we know about the
 248      nonzero bits of a register, specifically which bits are known to be
 249      zero.
 250
 251      If an entry is zero, it means that we don't know anything special.  */
 252
 253   unsigned char                 sign_bit_copies;
 254
 255   unsigned HOST_WIDE_INT        nonzero_bits;
 256
 257   /* Record the value of the label_tick when the last truncation
 258      happened.  The field truncated_to_mode is only valid if
 259      truncation_label == label_tick.  */
 260
 261   int                           truncation_label;
 262
 263   /* Record the last truncation seen for this register.  If truncation
 264      is not a nop to this mode we might be able to save an explicit
 265      truncation if we know that value already contains a truncated
 266      value.  */
 267
 268   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 269 };
 270
 271 static struct reg_stat *reg_stat;
 272
 273 /* Record the cuid of the last insn that invalidated memory
 274    (anything that writes memory, and subroutine calls, but not pushes).  */
 275
 276 static int mem_last_set;
 277
 278 /* Record the cuid of the last CALL_INSN
 279    so we can tell whether a potential combination crosses any calls.  */
 280
 281 static int last_call_cuid;
 282
 283 /* When `subst' is called, this is the insn that is being modified
 284    (by combining in a previous insn).  The PATTERN of this insn
 285    is still the old pattern partially modified and it should not be
 286    looked at, but this may be used to examine the successors of the insn
 287    to judge whether a simplification is valid.  */
 288
 289 static rtx subst_insn;
 290
 291 /* This is the lowest CUID that `subst' is currently dealing with.
 292    get_last_value will not return a value if the register was set at or
 293    after this CUID.  If not for this mechanism, we could get confused if
 294    I2 or I1 in try_combine were an insn that used the old value of a register
 295    to obtain a new value.  In that case, we might erroneously get the
 296    new value of the register when we wanted the old one.  */
 297
 298 static int subst_low_cuid;
 299
 300 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 301    must consider all these registers to be always live.  */
 302
 303 static HARD_REG_SET newpat_used_regs;
 304
 305 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 306    insn is the earlier than I2 or I3, combine should rescan starting at
 307    that location.  */
 308
 309 static rtx added_links_insn;
 310
 311 /* Basic block in which we are performing combines.  */
 312 static basic_block this_basic_block;
 313
 314 /* A bitmap indicating which blocks had registers go dead at entry.
 315    After combine, we'll need to re-do global life analysis with
 316    those blocks as starting points.  */
 317 static sbitmap refresh_blocks;
 318 \f
 319 /* The following array records the insn_rtx_cost for every insn
 320    in the instruction stream.  */
 321
 322 static int *uid_insn_cost;
 323
 324 /* Length of the currently allocated uid_insn_cost array.  */
 325
 326 static int last_insn_cost;
 327
 328 /* Incremented for each label.  */
 329
 330 static int label_tick;
 331
 332 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 333    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 334
 335 static enum machine_mode nonzero_bits_mode;
 336
 337 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 338    be safely used.  It is zero while computing them and after combine has
 339    completed.  This former test prevents propagating values based on
 340    previously set values, which can be incorrect if a variable is modified
 341    in a loop.  */
 342
 343 static int nonzero_sign_valid;
 344
 345 \f
 346 /* Record one modification to rtl structure
 347    to be undone by storing old_contents into *where.  */
 348
 349 struct undo
 350 {
 351   struct undo *next;
 352   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 353   union { rtx r; int i; enum machine_mode m; } old_contents;
 354   union { rtx *r; int *i; } where;
 355 };
 356
 357 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 358    num_undo says how many are currently recorded.
 359
 360    other_insn is nonzero if we have modified some other insn in the process
 361    of working on subst_insn.  It must be verified too.  */
 362
 363 struct undobuf
 364 {
 365   struct undo *undos;
 366   struct undo *frees;
 367   rtx other_insn;
 368 };
 369
 370 static struct undobuf undobuf;
 371
 372 /* Number of times the pseudo being substituted for
 373    was found and replaced.  */
 374
 375 static int n_occurrences;
 376
 377 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 378                                          enum machine_mode,
 379                                          unsigned HOST_WIDE_INT,
 380                                          unsigned HOST_WIDE_INT *);
 381 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 382                                                 enum machine_mode,
 383                                                 unsigned int, unsigned int *);
 384 static void do_SUBST (rtx *, rtx);
 385 static void do_SUBST_INT (int *, int);
 386 static void init_reg_last (void);
 387 static void setup_incoming_promotions (void);
 388 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 389 static int cant_combine_insn_p (rtx);
 390 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 391 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 392 static int contains_muldiv (rtx);
 393 static rtx try_combine (rtx, rtx, rtx, int *);
 394 static void undo_all (void);
 395 static void undo_commit (void);
 396 static rtx *find_split_point (rtx *, rtx);
 397 static rtx subst (rtx, rtx, rtx, int, int);
 398 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 399 static rtx simplify_if_then_else (rtx);
 400 static rtx simplify_set (rtx);
 401 static rtx simplify_logical (rtx);
 402 static rtx expand_compound_operation (rtx);
 403 static rtx expand_field_assignment (rtx);
 404 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 405                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 406 static rtx extract_left_shift (rtx, int);
 407 static rtx make_compound_operation (rtx, enum rtx_code);
 408 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 409                               unsigned HOST_WIDE_INT *);
 410 static rtx canon_reg_for_combine (rtx, rtx);
 411 static rtx force_to_mode (rtx, enum machine_mode,
 412                           unsigned HOST_WIDE_INT, int);
 413 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 414 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 415 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 416 static rtx make_field_assignment (rtx);
 417 static rtx apply_distributive_law (rtx);
 418 static rtx distribute_and_simplify_rtx (rtx, int);
 419 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 420                                      unsigned HOST_WIDE_INT);
 421 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 422                                    unsigned HOST_WIDE_INT);
 423 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 424                             HOST_WIDE_INT, enum machine_mode, int *);
 425 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 426 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 427                                  int);
 428 static int recog_for_combine (rtx *, rtx, rtx *);
 429 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 430 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 431 static void update_table_tick (rtx);
 432 static void record_value_for_reg (rtx, rtx, rtx);
 433 static void check_conversions (rtx, rtx);
 434 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 435 static void record_dead_and_set_regs (rtx);
 436 static int get_last_value_validate (rtx *, rtx, int, int);
 437 static rtx get_last_value (rtx);
 438 static int use_crosses_set_p (rtx, int);
 439 static void reg_dead_at_p_1 (rtx, rtx, void *);
 440 static int reg_dead_at_p (rtx, rtx);
 441 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 442 static int reg_bitfield_target_p (rtx, rtx);
 443 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 444 static void distribute_links (rtx);
 445 static void mark_used_regs_combine (rtx);
 446 static int insn_cuid (rtx);
 447 static void record_promoted_value (rtx, rtx);
 448 static int unmentioned_reg_p_1 (rtx *, void *);
 449 static bool unmentioned_reg_p (rtx, rtx);
 450 static void record_truncated_value (rtx);
 451 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 452 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 453 \f
 454
 455 /* It is not safe to use ordinary gen_lowpart in combine.
 456    See comments in gen_lowpart_for_combine.  */
 457 #undef RTL_HOOKS_GEN_LOWPART
 458 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 459
 460 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 461 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 462 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 463
 464 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 465 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 466
 467 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 468 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 469
 470 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 471 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 472
 473 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 474
 475 \f
 476 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 477    insn.  The substitution can be undone by undo_all.  If INTO is already
 478    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 479    also call SUBST, we have to compute it before we put anything into
 480    the undo table.  */
 481
 482 static void
 483 do_SUBST (rtx *into, rtx newval)
 484 {
 485   struct undo *buf;
 486   rtx oldval = *into;
 487
 488   if (oldval == newval)
 489     return;
 490
 491   /* We'd like to catch as many invalid transformations here as
 492      possible.  Unfortunately, there are way too many mode changes
 493      that are perfectly valid, so we'd waste too much effort for
 494      little gain doing the checks here.  Focus on catching invalid
 495      transformations involving integer constants.  */
 496   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 497       && GET_CODE (newval) == CONST_INT)
 498     {
 499       /* Sanity check that we're replacing oldval with a CONST_INT
 500          that is a valid sign-extension for the original mode.  */
 501       gcc_assert (INTVAL (newval)
 502                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 503
 504       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 505          CONST_INT is not valid, because after the replacement, the
 506          original mode would be gone.  Unfortunately, we can't tell
 507          when do_SUBST is called to replace the operand thereof, so we
 508          perform this test on oldval instead, checking whether an
 509          invalid replacement took place before we got here.  */
 510       gcc_assert (!(GET_CODE (oldval) == SUBREG
 511                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 512       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 513                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 514     }
 515
 516   if (undobuf.frees)
 517     buf = undobuf.frees, undobuf.frees = buf->next;
 518   else
 519     buf = XNEW (struct undo);
 520
 521   buf->kind = UNDO_RTX;
 522   buf->where.r = into;
 523   buf->old_contents.r = oldval;
 524   *into = newval;
 525
 526   buf->next = undobuf.undos, undobuf.undos = buf;
 527 }
 528
 529 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 530
 531 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 532    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 533    not safe.  */
 534
 535 static void
 536 do_SUBST_INT (int *into, int newval)
 537 {
 538   struct undo *buf;
 539   int oldval = *into;
 540
 541   if (oldval == newval)
 542     return;
 543
 544   if (undobuf.frees)
 545     buf = undobuf.frees, undobuf.frees = buf->next;
 546   else
 547     buf = XNEW (struct undo);
 548
 549   buf->kind = UNDO_INT;
 550   buf->where.i = into;
 551   buf->old_contents.i = oldval;
 552   *into = newval;
 553
 554   buf->next = undobuf.undos, undobuf.undos = buf;
 555 }
 556
 557 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 558
 559 /* Similar to SUBST, but just substitute the mode.  This is used when
 560    changing the mode of a pseudo-register, so that any other
 561    references to the entry in the regno_reg_rtx array will change as
 562    well.  */
 563
 564 static void
 565 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 566 {
 567   struct undo *buf;
 568   enum machine_mode oldval = GET_MODE (*into);
 569
 570   if (oldval == newval)
 571     return;
 572
 573   if (undobuf.frees)
 574     buf = undobuf.frees, undobuf.frees = buf->next;
 575   else
 576     buf = XNEW (struct undo);
 577
 578   buf->kind = UNDO_MODE;
 579   buf->where.r = into;
 580   buf->old_contents.m = oldval;
 581   PUT_MODE (*into, newval);
 582
 583   buf->next = undobuf.undos, undobuf.undos = buf;
 584 }
 585
 586 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 587 \f
 588 /* Subroutine of try_combine.  Determine whether the combine replacement
 589    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 590    that the original instruction sequence I1, I2 and I3.  Note that I1
 591    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 592    costs of all instructions can be estimated, and the replacements are
 593    more expensive than the original sequence.  */
 594
 595 static bool
 596 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 597 {
 598   int i1_cost, i2_cost, i3_cost;
 599   int new_i2_cost, new_i3_cost;
 600   int old_cost, new_cost;
 601
 602   /* Lookup the original insn_rtx_costs.  */
 603   i2_cost = INSN_UID (i2) <= last_insn_cost
 604             ? uid_insn_cost[INSN_UID (i2)] : 0;
 605   i3_cost = INSN_UID (i3) <= last_insn_cost
 606             ? uid_insn_cost[INSN_UID (i3)] : 0;
 607
 608   if (i1)
 609     {
 610       i1_cost = INSN_UID (i1) <= last_insn_cost
 611                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 612       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 613                  ? i1_cost + i2_cost + i3_cost : 0;
 614     }
 615   else
 616     {
 617       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 618       i1_cost = 0;
 619     }
 620
 621   /* Calculate the replacement insn_rtx_costs.  */
 622   new_i3_cost = insn_rtx_cost (newpat);
 623   if (newi2pat)
 624     {
 625       new_i2_cost = insn_rtx_cost (newi2pat);
 626       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 627                  ? new_i2_cost + new_i3_cost : 0;
 628     }
 629   else
 630     {
 631       new_cost = new_i3_cost;
 632       new_i2_cost = 0;
 633     }
 634
 635   if (undobuf.other_insn)
 636     {
 637       int old_other_cost, new_other_cost;
 638
 639       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 640                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 641       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 642       if (old_other_cost > 0 && new_other_cost > 0)
 643         {
 644           old_cost += old_other_cost;
 645           new_cost += new_other_cost;
 646         }
 647       else
 648         old_cost = 0;
 649     }
 650
 651   /* Disallow this recombination if both new_cost and old_cost are
 652      greater than zero, and new_cost is greater than old cost.  */
 653   if (old_cost > 0
 654       && new_cost > old_cost)
 655     {
 656       if (dump_file)
 657         {
 658           if (i1)
 659             {
 660               fprintf (dump_file,
 661                        "rejecting combination of insns %d, %d and %d\n",
 662                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 663               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 664                        i1_cost, i2_cost, i3_cost, old_cost);
 665             }
 666           else
 667             {
 668               fprintf (dump_file,
 669                        "rejecting combination of insns %d and %d\n",
 670                        INSN_UID (i2), INSN_UID (i3));
 671               fprintf (dump_file, "original costs %d + %d = %d\n",
 672                        i2_cost, i3_cost, old_cost);
 673             }
 674
 675           if (newi2pat)
 676             {
 677               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 678                        new_i2_cost, new_i3_cost, new_cost);
 679             }
 680           else
 681             fprintf (dump_file, "replacement cost %d\n", new_cost);
 682         }
 683
 684       return false;
 685     }
 686
 687   /* Update the uid_insn_cost array with the replacement costs.  */
 688   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 689   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 690   if (i1)
 691     uid_insn_cost[INSN_UID (i1)] = 0;
 692
 693   return true;
 694 }
 695 \f
 696 /* Main entry point for combiner.  F is the first insn of the function.
 697    NREGS is the first unused pseudo-reg number.
 698
 699    Return nonzero if the combiner has turned an indirect jump
 700    instruction into a direct jump.  */
 701 static int
 702 combine_instructions (rtx f, unsigned int nregs)
 703 {
 704   rtx insn, next;
 705 #ifdef HAVE_cc0
 706   rtx prev;
 707 #endif
 708   int i;
 709   unsigned int j = 0;
 710   rtx links, nextlinks;
 711   sbitmap_iterator sbi;
 712
 713   int new_direct_jump_p = 0;
 714
 715   combine_attempts = 0;
 716   combine_merges = 0;
 717   combine_extras = 0;
 718   combine_successes = 0;
 719
 720   combine_max_regno = nregs;
 721
 722   rtl_hooks = combine_rtl_hooks;
 723
 724   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 725
 726   init_recog_no_volatile ();
 727
 728   /* Compute maximum uid value so uid_cuid can be allocated.  */
 729
 730   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 731     if (INSN_UID (insn) > i)
 732       i = INSN_UID (insn);
 733
 734   uid_cuid = XNEWVEC (int, i + 1);
 735   max_uid_cuid = i;
 736
 737   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 738
 739   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 740      problems when, for example, we have j <<= 1 in a loop.  */
 741
 742   nonzero_sign_valid = 0;
 743
 744   /* Compute the mapping from uids to cuids.
 745      Cuids are numbers assigned to insns, like uids,
 746      except that cuids increase monotonically through the code.
 747
 748      Scan all SETs and see if we can deduce anything about what
 749      bits are known to be zero for some registers and how many copies
 750      of the sign bit are known to exist for those registers.
 751
 752      Also set any known values so that we can use it while searching
 753      for what bits are known to be set.  */
 754
 755   label_tick = 1;
 756
 757   setup_incoming_promotions ();
 758
 759   refresh_blocks = sbitmap_alloc (last_basic_block);
 760   sbitmap_zero (refresh_blocks);
 761
 762   /* Allocate array of current insn_rtx_costs.  */
 763   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 764   last_insn_cost = max_uid_cuid;
 765
 766   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 767     {
 768       uid_cuid[INSN_UID (insn)] = ++i;
 769       subst_low_cuid = i;
 770       subst_insn = insn;
 771
 772       if (INSN_P (insn))
 773         {
 774           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 775                        NULL);
 776           record_dead_and_set_regs (insn);
 777
 778 #ifdef AUTO_INC_DEC
 779           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 780             if (REG_NOTE_KIND (links) == REG_INC)
 781               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 782                                                 NULL);
 783 #endif
 784
 785           /* Record the current insn_rtx_cost of this instruction.  */
 786           if (NONJUMP_INSN_P (insn))
 787             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 788           if (dump_file)
 789             fprintf(dump_file, "insn_cost %d: %d\n",
 790                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 791         }
 792
 793       if (LABEL_P (insn))
 794         label_tick++;
 795     }
 796
 797   nonzero_sign_valid = 1;
 798
 799   /* Now scan all the insns in forward order.  */
 800
 801   label_tick = 1;
 802   last_call_cuid = 0;
 803   mem_last_set = 0;
 804   init_reg_last ();
 805   setup_incoming_promotions ();
 806
 807   FOR_EACH_BB (this_basic_block)
 808     {
 809       for (insn = BB_HEAD (this_basic_block);
 810            insn != NEXT_INSN (BB_END (this_basic_block));
 811            insn = next ? next : NEXT_INSN (insn))
 812         {
 813           next = 0;
 814
 815           if (LABEL_P (insn))
 816             label_tick++;
 817
 818           else if (INSN_P (insn))
 819             {
 820               /* See if we know about function return values before this
 821                  insn based upon SUBREG flags.  */
 822               check_conversions (insn, PATTERN (insn));
 823
 824               /* Try this insn with each insn it links back to.  */
 825
 826               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 827                 if ((next = try_combine (insn, XEXP (links, 0),
 828                                          NULL_RTX, &new_direct_jump_p)) != 0)
 829                   goto retry;
 830
 831               /* Try each sequence of three linked insns ending with this one.  */
 832
 833               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 834                 {
 835                   rtx link = XEXP (links, 0);
 836
 837                   /* If the linked insn has been replaced by a note, then there
 838                      is no point in pursuing this chain any further.  */
 839                   if (NOTE_P (link))
 840                     continue;
 841
 842                   for (nextlinks = LOG_LINKS (link);
 843                        nextlinks;
 844                        nextlinks = XEXP (nextlinks, 1))
 845                     if ((next = try_combine (insn, link,
 846                                              XEXP (nextlinks, 0),
 847                                              &new_direct_jump_p)) != 0)
 848                       goto retry;
 849                 }
 850
 851 #ifdef HAVE_cc0
 852               /* Try to combine a jump insn that uses CC0
 853                  with a preceding insn that sets CC0, and maybe with its
 854                  logical predecessor as well.
 855                  This is how we make decrement-and-branch insns.
 856                  We need this special code because data flow connections
 857                  via CC0 do not get entered in LOG_LINKS.  */
 858
 859               if (JUMP_P (insn)
 860                   && (prev = prev_nonnote_insn (insn)) != 0
 861                   && NONJUMP_INSN_P (prev)
 862                   && sets_cc0_p (PATTERN (prev)))
 863                 {
 864                   if ((next = try_combine (insn, prev,
 865                                            NULL_RTX, &new_direct_jump_p)) != 0)
 866                     goto retry;
 867
 868                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 869                        nextlinks = XEXP (nextlinks, 1))
 870                     if ((next = try_combine (insn, prev,
 871                                              XEXP (nextlinks, 0),
 872                                              &new_direct_jump_p)) != 0)
 873                       goto retry;
 874                 }
 875
 876               /* Do the same for an insn that explicitly references CC0.  */
 877               if (NONJUMP_INSN_P (insn)
 878                   && (prev = prev_nonnote_insn (insn)) != 0
 879                   && NONJUMP_INSN_P (prev)
 880                   && sets_cc0_p (PATTERN (prev))
 881                   && GET_CODE (PATTERN (insn)) == SET
 882                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 883                 {
 884                   if ((next = try_combine (insn, prev,
 885                                            NULL_RTX, &new_direct_jump_p)) != 0)
 886                     goto retry;
 887
 888                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 889                        nextlinks = XEXP (nextlinks, 1))
 890                     if ((next = try_combine (insn, prev,
 891                                              XEXP (nextlinks, 0),
 892                                              &new_direct_jump_p)) != 0)
 893                       goto retry;
 894                 }
 895
 896               /* Finally, see if any of the insns that this insn links to
 897                  explicitly references CC0.  If so, try this insn, that insn,
 898                  and its predecessor if it sets CC0.  */
 899               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 900                 if (NONJUMP_INSN_P (XEXP (links, 0))
 901                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 902                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 903                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 904                     && NONJUMP_INSN_P (prev)
 905                     && sets_cc0_p (PATTERN (prev))
 906                     && (next = try_combine (insn, XEXP (links, 0),
 907                                             prev, &new_direct_jump_p)) != 0)
 908                   goto retry;
 909 #endif
 910
 911               /* Try combining an insn with two different insns whose results it
 912                  uses.  */
 913               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 914                 for (nextlinks = XEXP (links, 1); nextlinks;
 915                      nextlinks = XEXP (nextlinks, 1))
 916                   if ((next = try_combine (insn, XEXP (links, 0),
 917                                            XEXP (nextlinks, 0),
 918                                            &new_direct_jump_p)) != 0)
 919                     goto retry;
 920
 921               /* Try this insn with each REG_EQUAL note it links back to.  */
 922               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 923                 {
 924                   rtx set, note;
 925                   rtx temp = XEXP (links, 0);
 926                   if ((set = single_set (temp)) != 0
 927                       && (note = find_reg_equal_equiv_note (temp)) != 0
 928                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 929                       /* Avoid using a register that may already been marked
 930                          dead by an earlier instruction.  */
 931                       && ! unmentioned_reg_p (note, SET_SRC (set))
 932                       && (GET_MODE (note) == VOIDmode
 933                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 934                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 935                     {
 936                       /* Temporarily replace the set's source with the
 937                          contents of the REG_EQUAL note.  The insn will
 938                          be deleted or recognized by try_combine.  */
 939                       rtx orig = SET_SRC (set);
 940                       SET_SRC (set) = note;
 941                       i2mod = temp;
 942                       i2mod_old_rhs = copy_rtx (orig);
 943                       i2mod_new_rhs = copy_rtx (note);
 944                       next = try_combine (insn, i2mod, NULL_RTX,
 945                                           &new_direct_jump_p);
 946                       i2mod = NULL_RTX;
 947                       if (next)
 948                         goto retry;
 949                       SET_SRC (set) = orig;
 950                     }
 951                 }
 952
 953               if (!NOTE_P (insn))
 954                 record_dead_and_set_regs (insn);
 955
 956             retry:
 957               ;
 958             }
 959         }
 960     }
 961   clear_bb_flags ();
 962
 963   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 964     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 965   new_direct_jump_p |= purge_all_dead_edges ();
 966   delete_noop_moves ();
 967
 968   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 969                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 970                                     | PROP_KILL_DEAD_CODE);
 971
 972   /* Clean up.  */
 973   sbitmap_free (refresh_blocks);
 974   free (uid_insn_cost);
 975   free (reg_stat);
 976   free (uid_cuid);
 977
 978   {
 979     struct undo *undo, *next;
 980     for (undo = undobuf.frees; undo; undo = next)
 981       {
 982         next = undo->next;
 983         free (undo);
 984       }
 985     undobuf.frees = 0;
 986   }
 987
 988   total_attempts += combine_attempts;
 989   total_merges += combine_merges;
 990   total_extras += combine_extras;
 991   total_successes += combine_successes;
 992
 993   nonzero_sign_valid = 0;
 994   rtl_hooks = general_rtl_hooks;
 995
 996   /* Make recognizer allow volatile MEMs again.  */
 997   init_recog ();
 998
 999   return new_direct_jump_p;
1000 }
1001
1002 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1003
1004 static void
1005 init_reg_last (void)
1006 {
1007   unsigned int i;
1008   for (i = 0; i < combine_max_regno; i++)
1009     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
1010 }
1011 \f
1012 /* Set up any promoted values for incoming argument registers.  */
1013
1014 static void
1015 setup_incoming_promotions (void)
1016 {
1017   unsigned int regno;
1018   rtx reg;
1019   enum machine_mode mode;
1020   int unsignedp;
1021   rtx first = get_insns ();
1022
1023   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1024     {
1025       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1026         /* Check whether this register can hold an incoming pointer
1027            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1028            numbers, so translate if necessary due to register windows.  */
1029         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1030             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1031           {
1032             record_value_for_reg
1033               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1034                                            : SIGN_EXTEND),
1035                                           GET_MODE (reg),
1036                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1037           }
1038     }
1039 }
1040 \f
1041 /* Called via note_stores.  If X is a pseudo that is narrower than
1042    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1043
1044    If we are setting only a portion of X and we can't figure out what
1045    portion, assume all bits will be used since we don't know what will
1046    be happening.
1047
1048    Similarly, set how many bits of X are known to be copies of the sign bit
1049    at all locations in the function.  This is the smallest number implied
1050    by any set of X.  */
1051
1052 static void
1053 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1054                                   void *data ATTRIBUTE_UNUSED)
1055 {
1056   unsigned int num;
1057
1058   if (REG_P (x)
1059       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1060       /* If this register is undefined at the start of the file, we can't
1061          say what its contents were.  */
1062       && ! REGNO_REG_SET_P
1063          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1064       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1065     {
1066       if (set == 0 || GET_CODE (set) == CLOBBER)
1067         {
1068           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1069           reg_stat[REGNO (x)].sign_bit_copies = 1;
1070           return;
1071         }
1072
1073       /* If this is a complex assignment, see if we can convert it into a
1074          simple assignment.  */
1075       set = expand_field_assignment (set);
1076
1077       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1078          set what we know about X.  */
1079
1080       if (SET_DEST (set) == x
1081           || (GET_CODE (SET_DEST (set)) == SUBREG
1082               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1083                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1084               && SUBREG_REG (SET_DEST (set)) == x))
1085         {
1086           rtx src = SET_SRC (set);
1087
1088 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1089           /* If X is narrower than a word and SRC is a non-negative
1090              constant that would appear negative in the mode of X,
1091              sign-extend it for use in reg_stat[].nonzero_bits because some
1092              machines (maybe most) will actually do the sign-extension
1093              and this is the conservative approach.
1094
1095              ??? For 2.5, try to tighten up the MD files in this regard
1096              instead of this kludge.  */
1097
1098           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1099               && GET_CODE (src) == CONST_INT
1100               && INTVAL (src) > 0
1101               && 0 != (INTVAL (src)
1102                        & ((HOST_WIDE_INT) 1
1103                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1104             src = GEN_INT (INTVAL (src)
1105                            | ((HOST_WIDE_INT) (-1)
1106                               << GET_MODE_BITSIZE (GET_MODE (x))));
1107 #endif
1108
1109           /* Don't call nonzero_bits if it cannot change anything.  */
1110           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1111             reg_stat[REGNO (x)].nonzero_bits
1112               |= nonzero_bits (src, nonzero_bits_mode);
1113           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1114           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1115               || reg_stat[REGNO (x)].sign_bit_copies > num)
1116             reg_stat[REGNO (x)].sign_bit_copies = num;
1117         }
1118       else
1119         {
1120           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1121           reg_stat[REGNO (x)].sign_bit_copies = 1;
1122         }
1123     }
1124 }
1125 \f
1126 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1127    insns that were previously combined into I3 or that will be combined
1128    into the merger of INSN and I3.
1129
1130    Return 0 if the combination is not allowed for any reason.
1131
1132    If the combination is allowed, *PDEST will be set to the single
1133    destination of INSN and *PSRC to the single source, and this function
1134    will return 1.  */
1135
1136 static int
1137 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1138                rtx *pdest, rtx *psrc)
1139 {
1140   int i;
1141   rtx set = 0, src, dest;
1142   rtx p;
1143 #ifdef AUTO_INC_DEC
1144   rtx link;
1145 #endif
1146   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1147                               && next_active_insn (succ) == i3)
1148                       : next_active_insn (insn) == i3);
1149
1150   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1151      or a PARALLEL consisting of such a SET and CLOBBERs.
1152
1153      If INSN has CLOBBER parallel parts, ignore them for our processing.
1154      By definition, these happen during the execution of the insn.  When it
1155      is merged with another insn, all bets are off.  If they are, in fact,
1156      needed and aren't also supplied in I3, they may be added by
1157      recog_for_combine.  Otherwise, it won't match.
1158
1159      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1160      note.
1161
1162      Get the source and destination of INSN.  If more than one, can't
1163      combine.  */
1164
1165   if (GET_CODE (PATTERN (insn)) == SET)
1166     set = PATTERN (insn);
1167   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1168            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1169     {
1170       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1171         {
1172           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1173           rtx note;
1174
1175           switch (GET_CODE (elt))
1176             {
1177             /* This is important to combine floating point insns
1178                for the SH4 port.  */
1179             case USE:
1180               /* Combining an isolated USE doesn't make sense.
1181                  We depend here on combinable_i3pat to reject them.  */
1182               /* The code below this loop only verifies that the inputs of
1183                  the SET in INSN do not change.  We call reg_set_between_p
1184                  to verify that the REG in the USE does not change between
1185                  I3 and INSN.
1186                  If the USE in INSN was for a pseudo register, the matching
1187                  insn pattern will likely match any register; combining this
1188                  with any other USE would only be safe if we knew that the
1189                  used registers have identical values, or if there was
1190                  something to tell them apart, e.g. different modes.  For
1191                  now, we forgo such complicated tests and simply disallow
1192                  combining of USES of pseudo registers with any other USE.  */
1193               if (REG_P (XEXP (elt, 0))
1194                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1195                 {
1196                   rtx i3pat = PATTERN (i3);
1197                   int i = XVECLEN (i3pat, 0) - 1;
1198                   unsigned int regno = REGNO (XEXP (elt, 0));
1199
1200                   do
1201                     {
1202                       rtx i3elt = XVECEXP (i3pat, 0, i);
1203
1204                       if (GET_CODE (i3elt) == USE
1205                           && REG_P (XEXP (i3elt, 0))
1206                           && (REGNO (XEXP (i3elt, 0)) == regno
1207                               ? reg_set_between_p (XEXP (elt, 0),
1208                                                    PREV_INSN (insn), i3)
1209                               : regno >= FIRST_PSEUDO_REGISTER))
1210                         return 0;
1211                     }
1212                   while (--i >= 0);
1213                 }
1214               break;
1215
1216               /* We can ignore CLOBBERs.  */
1217             case CLOBBER:
1218               break;
1219
1220             case SET:
1221               /* Ignore SETs whose result isn't used but not those that
1222                  have side-effects.  */
1223               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1224                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1225                       || INTVAL (XEXP (note, 0)) <= 0)
1226                   && ! side_effects_p (elt))
1227                 break;
1228
1229               /* If we have already found a SET, this is a second one and
1230                  so we cannot combine with this insn.  */
1231               if (set)
1232                 return 0;
1233
1234               set = elt;
1235               break;
1236
1237             default:
1238               /* Anything else means we can't combine.  */
1239               return 0;
1240             }
1241         }
1242
1243       if (set == 0
1244           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1245              so don't do anything with it.  */
1246           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1247         return 0;
1248     }
1249   else
1250     return 0;
1251
1252   if (set == 0)
1253     return 0;
1254
1255   set = expand_field_assignment (set);
1256   src = SET_SRC (set), dest = SET_DEST (set);
1257
1258   /* Don't eliminate a store in the stack pointer.  */
1259   if (dest == stack_pointer_rtx
1260       /* Don't combine with an insn that sets a register to itself if it has
1261          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1262       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1263       /* Can't merge an ASM_OPERANDS.  */
1264       || GET_CODE (src) == ASM_OPERANDS
1265       /* Can't merge a function call.  */
1266       || GET_CODE (src) == CALL
1267       /* Don't eliminate a function call argument.  */
1268       || (CALL_P (i3)
1269           && (find_reg_fusage (i3, USE, dest)
1270               || (REG_P (dest)
1271                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1272                   && global_regs[REGNO (dest)])))
1273       /* Don't substitute into an incremented register.  */
1274       || FIND_REG_INC_NOTE (i3, dest)
1275       || (succ && FIND_REG_INC_NOTE (succ, dest))
1276       /* Don't substitute into a non-local goto, this confuses CFG.  */
1277       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1278 #if 0
1279       /* Don't combine the end of a libcall into anything.  */
1280       /* ??? This gives worse code, and appears to be unnecessary, since no
1281          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1282          use REG_RETVAL notes for noconflict blocks, but other code here
1283          makes sure that those insns don't disappear.  */
1284       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1285 #endif
1286       /* Make sure that DEST is not used after SUCC but before I3.  */
1287       || (succ && ! all_adjacent
1288           && reg_used_between_p (dest, succ, i3))
1289       /* Make sure that the value that is to be substituted for the register
1290          does not use any registers whose values alter in between.  However,
1291          If the insns are adjacent, a use can't cross a set even though we
1292          think it might (this can happen for a sequence of insns each setting
1293          the same destination; last_set of that register might point to
1294          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1295          equivalent to the memory so the substitution is valid even if there
1296          are intervening stores.  Also, don't move a volatile asm or
1297          UNSPEC_VOLATILE across any other insns.  */
1298       || (! all_adjacent
1299           && (((!MEM_P (src)
1300                 || ! find_reg_note (insn, REG_EQUIV, src))
1301                && use_crosses_set_p (src, INSN_CUID (insn)))
1302               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1303               || GET_CODE (src) == UNSPEC_VOLATILE))
1304       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1305          better register allocation by not doing the combine.  */
1306       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1307       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1308       /* Don't combine across a CALL_INSN, because that would possibly
1309          change whether the life span of some REGs crosses calls or not,
1310          and it is a pain to update that information.
1311          Exception: if source is a constant, moving it later can't hurt.
1312          Accept that special case, because it helps -fforce-addr a lot.  */
1313       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1314     return 0;
1315
1316   /* DEST must either be a REG or CC0.  */
1317   if (REG_P (dest))
1318     {
1319       /* If register alignment is being enforced for multi-word items in all
1320          cases except for parameters, it is possible to have a register copy
1321          insn referencing a hard register that is not allowed to contain the
1322          mode being copied and which would not be valid as an operand of most
1323          insns.  Eliminate this problem by not combining with such an insn.
1324
1325          Also, on some machines we don't want to extend the life of a hard
1326          register.  */
1327
1328       if (REG_P (src)
1329           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1330                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1331               /* Don't extend the life of a hard register unless it is
1332                  user variable (if we have few registers) or it can't
1333                  fit into the desired register (meaning something special
1334                  is going on).
1335                  Also avoid substituting a return register into I3, because
1336                  reload can't handle a conflict with constraints of other
1337                  inputs.  */
1338               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1339                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1340         return 0;
1341     }
1342   else if (GET_CODE (dest) != CC0)
1343     return 0;
1344
1345
1346   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1347     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1348       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1349         {
1350           /* Don't substitute for a register intended as a clobberable
1351              operand.  */
1352           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1353           if (rtx_equal_p (reg, dest))
1354             return 0;
1355
1356           /* If the clobber represents an earlyclobber operand, we must not
1357              substitute an expression containing the clobbered register.
1358              As we do not analyze the constraint strings here, we have to
1359              make the conservative assumption.  However, if the register is
1360              a fixed hard reg, the clobber cannot represent any operand;
1361              we leave it up to the machine description to either accept or
1362              reject use-and-clobber patterns.  */
1363           if (!REG_P (reg)
1364               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1365               || !fixed_regs[REGNO (reg)])
1366             if (reg_overlap_mentioned_p (reg, src))
1367               return 0;
1368         }
1369
1370   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1371      or not), reject, unless nothing volatile comes between it and I3 */
1372
1373   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1374     {
1375       /* Make sure succ doesn't contain a volatile reference.  */
1376       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1377         return 0;
1378
1379       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1380         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1381           return 0;
1382     }
1383
1384   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1385      to be an explicit register variable, and was chosen for a reason.  */
1386
1387   if (GET_CODE (src) == ASM_OPERANDS
1388       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1389     return 0;
1390
1391   /* If there are any volatile insns between INSN and I3, reject, because
1392      they might affect machine state.  */
1393
1394   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1395     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1396       return 0;
1397
1398   /* If INSN contains an autoincrement or autodecrement, make sure that
1399      register is not used between there and I3, and not already used in
1400      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1401      Also insist that I3 not be a jump; if it were one
1402      and the incremented register were spilled, we would lose.  */
1403
1404 #ifdef AUTO_INC_DEC
1405   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1406     if (REG_NOTE_KIND (link) == REG_INC
1407         && (JUMP_P (i3)
1408             || reg_used_between_p (XEXP (link, 0), insn, i3)
1409             || (pred != NULL_RTX
1410                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1411             || (succ != NULL_RTX
1412                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1413             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1414       return 0;
1415 #endif
1416
1417 #ifdef HAVE_cc0
1418   /* Don't combine an insn that follows a CC0-setting insn.
1419      An insn that uses CC0 must not be separated from the one that sets it.
1420      We do, however, allow I2 to follow a CC0-setting insn if that insn
1421      is passed as I1; in that case it will be deleted also.
1422      We also allow combining in this case if all the insns are adjacent
1423      because that would leave the two CC0 insns adjacent as well.
1424      It would be more logical to test whether CC0 occurs inside I1 or I2,
1425      but that would be much slower, and this ought to be equivalent.  */
1426
1427   p = prev_nonnote_insn (insn);
1428   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1429       && ! all_adjacent)
1430     return 0;
1431 #endif
1432
1433   /* If we get here, we have passed all the tests and the combination is
1434      to be allowed.  */
1435
1436   *pdest = dest;
1437   *psrc = src;
1438
1439   return 1;
1440 }
1441 \f
1442 /* LOC is the location within I3 that contains its pattern or the component
1443    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1444
1445    One problem is if I3 modifies its output, as opposed to replacing it
1446    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1447    so would produce an insn that is not equivalent to the original insns.
1448
1449    Consider:
1450
1451          (set (reg:DI 101) (reg:DI 100))
1452          (set (subreg:SI (reg:DI 101) 0) <foo>)
1453
1454    This is NOT equivalent to:
1455
1456          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1457                     (set (reg:DI 101) (reg:DI 100))])
1458
1459    Not only does this modify 100 (in which case it might still be valid
1460    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1461
1462    We can also run into a problem if I2 sets a register that I1
1463    uses and I1 gets directly substituted into I3 (not via I2).  In that
1464    case, we would be getting the wrong value of I2DEST into I3, so we
1465    must reject the combination.  This case occurs when I2 and I1 both
1466    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1467    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1468    of a SET must prevent combination from occurring.
1469
1470    Before doing the above check, we first try to expand a field assignment
1471    into a set of logical operations.
1472
1473    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1474    we place a register that is both set and used within I3.  If more than one
1475    such register is detected, we fail.
1476
1477    Return 1 if the combination is valid, zero otherwise.  */
1478
1479 static int
1480 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1481                   int i1_not_in_src, rtx *pi3dest_killed)
1482 {
1483   rtx x = *loc;
1484
1485   if (GET_CODE (x) == SET)
1486     {
1487       rtx set = x ;
1488       rtx dest = SET_DEST (set);
1489       rtx src = SET_SRC (set);
1490       rtx inner_dest = dest;
1491       rtx subdest;
1492
1493       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1494              || GET_CODE (inner_dest) == SUBREG
1495              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1496         inner_dest = XEXP (inner_dest, 0);
1497
1498       /* Check for the case where I3 modifies its output, as discussed
1499          above.  We don't want to prevent pseudos from being combined
1500          into the address of a MEM, so only prevent the combination if
1501          i1 or i2 set the same MEM.  */
1502       if ((inner_dest != dest &&
1503            (!MEM_P (inner_dest)
1504             || rtx_equal_p (i2dest, inner_dest)
1505             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1506            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1507                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1508
1509           /* This is the same test done in can_combine_p except we can't test
1510              all_adjacent; we don't have to, since this instruction will stay
1511              in place, thus we are not considering increasing the lifetime of
1512              INNER_DEST.
1513
1514              Also, if this insn sets a function argument, combining it with
1515              something that might need a spill could clobber a previous
1516              function argument; the all_adjacent test in can_combine_p also
1517              checks this; here, we do a more specific test for this case.  */
1518
1519           || (REG_P (inner_dest)
1520               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1521               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1522                                         GET_MODE (inner_dest))))
1523           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1524         return 0;
1525
1526       /* If DEST is used in I3, it is being killed in this insn, so
1527          record that for later.  We have to consider paradoxical
1528          subregs here, since they kill the whole register, but we
1529          ignore partial subregs, STRICT_LOW_PART, etc.
1530          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1531          STACK_POINTER_REGNUM, since these are always considered to be
1532          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1533       subdest = dest;
1534       if (GET_CODE (subdest) == SUBREG
1535           && (GET_MODE_SIZE (GET_MODE (subdest))
1536               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1537         subdest = SUBREG_REG (subdest);
1538       if (pi3dest_killed
1539           && REG_P (subdest)
1540           && reg_referenced_p (subdest, PATTERN (i3))
1541           && REGNO (subdest) != FRAME_POINTER_REGNUM
1542 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1543           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1544 #endif
1545 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1546           && (REGNO (subdest) != ARG_POINTER_REGNUM
1547               || ! fixed_regs [REGNO (subdest)])
1548 #endif
1549           && REGNO (subdest) != STACK_POINTER_REGNUM)
1550         {
1551           if (*pi3dest_killed)
1552             return 0;
1553
1554           *pi3dest_killed = subdest;
1555         }
1556     }
1557
1558   else if (GET_CODE (x) == PARALLEL)
1559     {
1560       int i;
1561
1562       for (i = 0; i < XVECLEN (x, 0); i++)
1563         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1564                                 i1_not_in_src, pi3dest_killed))
1565           return 0;
1566     }
1567
1568   return 1;
1569 }
1570 \f
1571 /* Return 1 if X is an arithmetic expression that contains a multiplication
1572    and division.  We don't count multiplications by powers of two here.  */
1573
1574 static int
1575 contains_muldiv (rtx x)
1576 {
1577   switch (GET_CODE (x))
1578     {
1579     case MOD:  case DIV:  case UMOD:  case UDIV:
1580       return 1;
1581
1582     case MULT:
1583       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1584                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1585     default:
1586       if (BINARY_P (x))
1587         return contains_muldiv (XEXP (x, 0))
1588             || contains_muldiv (XEXP (x, 1));
1589
1590       if (UNARY_P (x))
1591         return contains_muldiv (XEXP (x, 0));
1592
1593       return 0;
1594     }
1595 }
1596 \f
1597 /* Determine whether INSN can be used in a combination.  Return nonzero if
1598    not.  This is used in try_combine to detect early some cases where we
1599    can't perform combinations.  */
1600
1601 static int
1602 cant_combine_insn_p (rtx insn)
1603 {
1604   rtx set;
1605   rtx src, dest;
1606
1607   /* If this isn't really an insn, we can't do anything.
1608      This can occur when flow deletes an insn that it has merged into an
1609      auto-increment address.  */
1610   if (! INSN_P (insn))
1611     return 1;
1612
1613   /* Never combine loads and stores involving hard regs that are likely
1614      to be spilled.  The register allocator can usually handle such
1615      reg-reg moves by tying.  If we allow the combiner to make
1616      substitutions of likely-spilled regs, reload might die.
1617      As an exception, we allow combinations involving fixed regs; these are
1618      not available to the register allocator so there's no risk involved.  */
1619
1620   set = single_set (insn);
1621   if (! set)
1622     return 0;
1623   src = SET_SRC (set);
1624   dest = SET_DEST (set);
1625   if (GET_CODE (src) == SUBREG)
1626     src = SUBREG_REG (src);
1627   if (GET_CODE (dest) == SUBREG)
1628     dest = SUBREG_REG (dest);
1629   if (REG_P (src) && REG_P (dest)
1630       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1631            && ! fixed_regs[REGNO (src)]
1632            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1633           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1634               && ! fixed_regs[REGNO (dest)]
1635               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1636     return 1;
1637
1638   return 0;
1639 }
1640
1641 struct likely_spilled_retval_info
1642 {
1643   unsigned regno, nregs;
1644   unsigned mask;
1645 };
1646
1647 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1648    hard registers that are known to be written to / clobbered in full.  */
1649 static void
1650 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1651 {
1652   struct likely_spilled_retval_info *info = data;
1653   unsigned regno, nregs;
1654   unsigned new_mask;
1655
1656   if (!REG_P (XEXP (set, 0)))
1657     return;
1658   regno = REGNO (x);
1659   if (regno >= info->regno + info->nregs)
1660     return;
1661   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1662   if (regno + nregs <= info->regno)
1663     return;
1664   new_mask = (2U << (nregs - 1)) - 1;
1665   if (regno < info->regno)
1666     new_mask >>= info->regno - regno;
1667   else
1668     new_mask <<= regno - info->regno;
1669   info->mask &= ~new_mask;
1670 }
1671
1672 /* Return nonzero iff part of the return value is live during INSN, and
1673    it is likely spilled.  This can happen when more than one insn is needed
1674    to copy the return value, e.g. when we consider to combine into the
1675    second copy insn for a complex value.  */
1676
1677 static int
1678 likely_spilled_retval_p (rtx insn)
1679 {
1680   rtx use = BB_END (this_basic_block);
1681   rtx reg, p;
1682   unsigned regno, nregs;
1683   /* We assume here that no machine mode needs more than
1684      32 hard registers when the value overlaps with a register
1685      for which FUNCTION_VALUE_REGNO_P is true.  */
1686   unsigned mask;
1687   struct likely_spilled_retval_info info;
1688
1689   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1690     return 0;
1691   reg = XEXP (PATTERN (use), 0);
1692   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1693     return 0;
1694   regno = REGNO (reg);
1695   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1696   if (nregs == 1)
1697     return 0;
1698   mask = (2U << (nregs - 1)) - 1;
1699
1700   /* Disregard parts of the return value that are set later.  */
1701   info.regno = regno;
1702   info.nregs = nregs;
1703   info.mask = mask;
1704   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1705     if (INSN_P (p))
1706       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
1707   mask = info.mask;
1708
1709   /* Check if any of the (probably) live return value registers is
1710      likely spilled.  */
1711   nregs --;
1712   do
1713     {
1714       if ((mask & 1 << nregs)
1715           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1716         return 1;
1717     } while (nregs--);
1718   return 0;
1719 }
1720
1721 /* Adjust INSN after we made a change to its destination.
1722
1723    Changing the destination can invalidate notes that say something about
1724    the results of the insn and a LOG_LINK pointing to the insn.  */
1725
1726 static void
1727 adjust_for_new_dest (rtx insn)
1728 {
1729   /* For notes, be conservative and simply remove them.  */
1730   remove_reg_equal_equiv_notes (insn);
1731
1732   /* The new insn will have a destination that was previously the destination
1733      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1734      the next use of that destination.  */
1735   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1736 }
1737
1738 /* Return TRUE if combine can reuse reg X in mode MODE.
1739    ADDED_SETS is nonzero if the original set is still required.  */
1740 static bool
1741 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1742 {
1743   unsigned int regno;
1744
1745   if (!REG_P(x))
1746     return false;
1747
1748   regno = REGNO (x);
1749   /* Allow hard registers if the new mode is legal, and occupies no more
1750      registers than the old mode.  */
1751   if (regno < FIRST_PSEUDO_REGISTER)
1752     return (HARD_REGNO_MODE_OK (regno, mode)
1753             && (hard_regno_nregs[regno][GET_MODE (x)]
1754                 >= hard_regno_nregs[regno][mode]));
1755
1756   /* Or a pseudo that is only used once.  */
1757   return (REG_N_SETS (regno) == 1 && !added_sets
1758           && !REG_USERVAR_P (x));
1759 }
1760
1761
1762 /* Check whether X, the destination of a set, refers to part of
1763    the register specified by REG.  */
1764
1765 static bool
1766 reg_subword_p (rtx x, rtx reg)
1767 {
1768   /* Check that reg is an integer mode register.  */
1769   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1770     return false;
1771
1772   if (GET_CODE (x) == STRICT_LOW_PART
1773       || GET_CODE (x) == ZERO_EXTRACT)
1774     x = XEXP (x, 0);
1775
1776   return GET_CODE (x) == SUBREG
1777          && SUBREG_REG (x) == reg
1778          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1779 }
1780
1781
1782 /* Try to combine the insns I1 and I2 into I3.
1783    Here I1 and I2 appear earlier than I3.
1784    I1 can be zero; then we combine just I2 into I3.
1785
1786    If we are combining three insns and the resulting insn is not recognized,
1787    try splitting it into two insns.  If that happens, I2 and I3 are retained
1788    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1789    are pseudo-deleted.
1790
1791    Return 0 if the combination does not work.  Then nothing is changed.
1792    If we did the combination, return the insn at which combine should
1793    resume scanning.
1794
1795    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1796    new direct jump instruction.  */
1797
1798 static rtx
1799 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1800 {
1801   /* New patterns for I3 and I2, respectively.  */
1802   rtx newpat, newi2pat = 0;
1803   rtvec newpat_vec_with_clobbers = 0;
1804   int substed_i2 = 0, substed_i1 = 0;
1805   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1806   int added_sets_1, added_sets_2;
1807   /* Total number of SETs to put into I3.  */
1808   int total_sets;
1809   /* Nonzero if I2's body now appears in I3.  */
1810   int i2_is_used;
1811   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1812   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1813   /* Contains I3 if the destination of I3 is used in its source, which means
1814      that the old life of I3 is being killed.  If that usage is placed into
1815      I2 and not in I3, a REG_DEAD note must be made.  */
1816   rtx i3dest_killed = 0;
1817   /* SET_DEST and SET_SRC of I2 and I1.  */
1818   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1819   /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
1820   rtx i1pat = 0, i2pat = 0;
1821   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1822   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1823   int i2dest_killed = 0, i1dest_killed = 0;
1824   int i1_feeds_i3 = 0;
1825   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1826   rtx new_i3_notes, new_i2_notes;
1827   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1828   int i3_subst_into_i2 = 0;
1829   /* Notes that I1, I2 or I3 is a MULT operation.  */
1830   int have_mult = 0;
1831   int swap_i2i3 = 0;
1832
1833   int maxreg;
1834   rtx temp;
1835   rtx link;
1836   int i;
1837
1838   /* Exit early if one of the insns involved can't be used for
1839      combinations.  */
1840   if (cant_combine_insn_p (i3)
1841       || cant_combine_insn_p (i2)
1842       || (i1 && cant_combine_insn_p (i1))
1843       || likely_spilled_retval_p (i3)
1844       /* We also can't do anything if I3 has a
1845          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1846          libcall.  */
1847 #if 0
1848       /* ??? This gives worse code, and appears to be unnecessary, since no
1849          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1850       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1851 #endif
1852       )
1853     return 0;
1854
1855   combine_attempts++;
1856   undobuf.other_insn = 0;
1857
1858   /* Reset the hard register usage information.  */
1859   CLEAR_HARD_REG_SET (newpat_used_regs);
1860
1861   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1862      code below, set I1 to be the earlier of the two insns.  */
1863   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1864     temp = i1, i1 = i2, i2 = temp;
1865
1866   added_links_insn = 0;
1867
1868   /* First check for one important special-case that the code below will
1869      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1870      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1871      we may be able to replace that destination with the destination of I3.
1872      This occurs in the common code where we compute both a quotient and
1873      remainder into a structure, in which case we want to do the computation
1874      directly into the structure to avoid register-register copies.
1875
1876      Note that this case handles both multiple sets in I2 and also
1877      cases where I2 has a number of CLOBBER or PARALLELs.
1878
1879      We make very conservative checks below and only try to handle the
1880      most common cases of this.  For example, we only handle the case
1881      where I2 and I3 are adjacent to avoid making difficult register
1882      usage tests.  */
1883
1884   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1885       && REG_P (SET_SRC (PATTERN (i3)))
1886       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1887       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1888       && GET_CODE (PATTERN (i2)) == PARALLEL
1889       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1890       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1891          below would need to check what is inside (and reg_overlap_mentioned_p
1892          doesn't support those codes anyway).  Don't allow those destinations;
1893          the resulting insn isn't likely to be recognized anyway.  */
1894       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1895       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1896       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1897                                     SET_DEST (PATTERN (i3)))
1898       && next_real_insn (i2) == i3)
1899     {
1900       rtx p2 = PATTERN (i2);
1901
1902       /* Make sure that the destination of I3,
1903          which we are going to substitute into one output of I2,
1904          is not used within another output of I2.  We must avoid making this:
1905          (parallel [(set (mem (reg 69)) ...)
1906                     (set (reg 69) ...)])
1907          which is not well-defined as to order of actions.
1908          (Besides, reload can't handle output reloads for this.)
1909
1910          The problem can also happen if the dest of I3 is a memory ref,
1911          if another dest in I2 is an indirect memory ref.  */
1912       for (i = 0; i < XVECLEN (p2, 0); i++)
1913         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1914              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1915             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1916                                         SET_DEST (XVECEXP (p2, 0, i))))
1917           break;
1918
1919       if (i == XVECLEN (p2, 0))
1920         for (i = 0; i < XVECLEN (p2, 0); i++)
1921           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1922                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1923               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1924             {
1925               combine_merges++;
1926
1927               subst_insn = i3;
1928               subst_low_cuid = INSN_CUID (i2);
1929
1930               added_sets_2 = added_sets_1 = 0;
1931               i2dest = SET_SRC (PATTERN (i3));
1932               i2dest_killed = dead_or_set_p (i2, i2dest);
1933
1934               /* Replace the dest in I2 with our dest and make the resulting
1935                  insn the new pattern for I3.  Then skip to where we
1936                  validate the pattern.  Everything was set up above.  */
1937               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1938                      SET_DEST (PATTERN (i3)));
1939
1940               newpat = p2;
1941               i3_subst_into_i2 = 1;
1942               goto validate_replacement;
1943             }
1944     }
1945
1946   /* If I2 is setting a pseudo to a constant and I3 is setting some
1947      sub-part of it to another constant, merge them by making a new
1948      constant.  */
1949   if (i1 == 0
1950       && (temp = single_set (i2)) != 0
1951       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1952           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1953       && GET_CODE (PATTERN (i3)) == SET
1954       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1955           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1956       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1957     {
1958       rtx dest = SET_DEST (PATTERN (i3));
1959       int offset = -1;
1960       int width = 0;
1961
1962       if (GET_CODE (dest) == ZERO_EXTRACT)
1963         {
1964           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1965               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1966             {
1967               width = INTVAL (XEXP (dest, 1));
1968               offset = INTVAL (XEXP (dest, 2));
1969               dest = XEXP (dest, 0);
1970               if (BITS_BIG_ENDIAN)
1971                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1972             }
1973         }
1974       else
1975         {
1976           if (GET_CODE (dest) == STRICT_LOW_PART)
1977             dest = XEXP (dest, 0);
1978           width = GET_MODE_BITSIZE (GET_MODE (dest));
1979           offset = 0;
1980         }
1981
1982       if (offset >= 0)
1983         {
1984           /* If this is the low part, we're done.  */
1985           if (subreg_lowpart_p (dest))
1986             ;
1987           /* Handle the case where inner is twice the size of outer.  */
1988           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1989                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1990             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1991           /* Otherwise give up for now.  */
1992           else
1993             offset = -1;
1994         }
1995
1996       if (offset >= 0
1997           && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1998               <= HOST_BITS_PER_WIDE_INT * 2))
1999         {
2000           HOST_WIDE_INT mhi, ohi, ihi;
2001           HOST_WIDE_INT mlo, olo, ilo;
2002           rtx inner = SET_SRC (PATTERN (i3));
2003           rtx outer = SET_SRC (temp);
2004
2005           if (GET_CODE (outer) == CONST_INT)
2006             {
2007               olo = INTVAL (outer);
2008               ohi = olo < 0 ? -1 : 0;
2009             }
2010           else
2011             {
2012               olo = CONST_DOUBLE_LOW (outer);
2013               ohi = CONST_DOUBLE_HIGH (outer);
2014             }
2015
2016           if (GET_CODE (inner) == CONST_INT)
2017             {
2018               ilo = INTVAL (inner);
2019               ihi = ilo < 0 ? -1 : 0;
2020             }
2021           else
2022             {
2023               ilo = CONST_DOUBLE_LOW (inner);
2024               ihi = CONST_DOUBLE_HIGH (inner);
2025             }
2026
2027           if (width < HOST_BITS_PER_WIDE_INT)
2028             {
2029               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2030               mhi = 0;
2031             }
2032           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2033             {
2034               mhi = ((unsigned HOST_WIDE_INT) 1
2035                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2036               mlo = -1;
2037             }
2038           else
2039             {
2040               mlo = -1;
2041               mhi = -1;
2042             }
2043
2044           ilo &= mlo;
2045           ihi &= mhi;
2046
2047           if (offset >= HOST_BITS_PER_WIDE_INT)
2048             {
2049               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2050               mlo = 0;
2051               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2052               ilo = 0;
2053             }
2054           else if (offset > 0)
2055             {
2056               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2057                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2058               mlo = mlo << offset;
2059               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2060                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2061               ilo = ilo << offset;
2062             }
2063
2064           olo = (olo & ~mlo) | ilo;
2065           ohi = (ohi & ~mhi) | ihi;
2066
2067           combine_merges++;
2068           subst_insn = i3;
2069           subst_low_cuid = INSN_CUID (i2);
2070           added_sets_2 = added_sets_1 = 0;
2071           i2dest = SET_DEST (temp);
2072           i2dest_killed = dead_or_set_p (i2, i2dest);
2073
2074           SUBST (SET_SRC (temp),
2075                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2076
2077           newpat = PATTERN (i2);
2078           goto validate_replacement;
2079         }
2080     }
2081
2082 #ifndef HAVE_cc0
2083   /* If we have no I1 and I2 looks like:
2084         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2085                    (set Y OP)])
2086      make up a dummy I1 that is
2087         (set Y OP)
2088      and change I2 to be
2089         (set (reg:CC X) (compare:CC Y (const_int 0)))
2090
2091      (We can ignore any trailing CLOBBERs.)
2092
2093      This undoes a previous combination and allows us to match a branch-and-
2094      decrement insn.  */
2095
2096   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2097       && XVECLEN (PATTERN (i2), 0) >= 2
2098       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2099       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2100           == MODE_CC)
2101       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2102       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2103       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2104       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2105       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2106                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2107     {
2108       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2109         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2110           break;
2111
2112       if (i == 1)
2113         {
2114           /* We make I1 with the same INSN_UID as I2.  This gives it
2115              the same INSN_CUID for value tracking.  Our fake I1 will
2116              never appear in the insn stream so giving it the same INSN_UID
2117              as I2 will not cause a problem.  */
2118
2119           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2120                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2121                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2122                              NULL_RTX);
2123
2124           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2125           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2126                  SET_DEST (PATTERN (i1)));
2127         }
2128     }
2129 #endif
2130
2131   /* Verify that I2 and I1 are valid for combining.  */
2132   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2133       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2134     {
2135       undo_all ();
2136       return 0;
2137     }
2138
2139   /* Record whether I2DEST is used in I2SRC and similarly for the other
2140      cases.  Knowing this will help in register status updating below.  */
2141   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2142   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2143   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2144   i2dest_killed = dead_or_set_p (i2, i2dest);
2145   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2146
2147   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2148      in I2SRC.  */
2149   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2150
2151   /* Ensure that I3's pattern can be the destination of combines.  */
2152   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2153                           i1 && i2dest_in_i1src && i1_feeds_i3,
2154                           &i3dest_killed))
2155     {
2156       undo_all ();
2157       return 0;
2158     }
2159
2160   /* See if any of the insns is a MULT operation.  Unless one is, we will
2161      reject a combination that is, since it must be slower.  Be conservative
2162      here.  */
2163   if (GET_CODE (i2src) == MULT
2164       || (i1 != 0 && GET_CODE (i1src) == MULT)
2165       || (GET_CODE (PATTERN (i3)) == SET
2166           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2167     have_mult = 1;
2168
2169   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2170      We used to do this EXCEPT in one case: I3 has a post-inc in an
2171      output operand.  However, that exception can give rise to insns like
2172         mov r3,(r3)+
2173      which is a famous insn on the PDP-11 where the value of r3 used as the
2174      source was model-dependent.  Avoid this sort of thing.  */
2175
2176 #if 0
2177   if (!(GET_CODE (PATTERN (i3)) == SET
2178         && REG_P (SET_SRC (PATTERN (i3)))
2179         && MEM_P (SET_DEST (PATTERN (i3)))
2180         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2181             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2182     /* It's not the exception.  */
2183 #endif
2184 #ifdef AUTO_INC_DEC
2185     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2186       if (REG_NOTE_KIND (link) == REG_INC
2187           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2188               || (i1 != 0
2189                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2190         {
2191           undo_all ();
2192           return 0;
2193         }
2194 #endif
2195
2196   /* See if the SETs in I1 or I2 need to be kept around in the merged
2197      instruction: whenever the value set there is still needed past I3.
2198      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2199
2200      For the SET in I1, we have two cases:  If I1 and I2 independently
2201      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2202      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2203      in I1 needs to be kept around unless I1DEST dies or is set in either
2204      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2205      I1DEST.  If so, we know I1 feeds into I2.  */
2206
2207   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2208
2209   added_sets_1
2210     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2211                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2212
2213   /* If the set in I2 needs to be kept around, we must make a copy of
2214      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2215      PATTERN (I2), we are only substituting for the original I1DEST, not into
2216      an already-substituted copy.  This also prevents making self-referential
2217      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2218      I2DEST.  */
2219
2220   if (added_sets_2)
2221     {
2222       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2223         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2224       else
2225         i2pat = copy_rtx (PATTERN (i2));
2226     }
2227
2228   if (added_sets_1)
2229     {
2230       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2231         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2232       else
2233         i1pat = copy_rtx (PATTERN (i1));
2234     }
2235
2236   combine_merges++;
2237
2238   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2239
2240   maxreg = max_reg_num ();
2241
2242   subst_insn = i3;
2243
2244 #ifndef HAVE_cc0
2245   /* Many machines that don't use CC0 have insns that can both perform an
2246      arithmetic operation and set the condition code.  These operations will
2247      be represented as a PARALLEL with the first element of the vector
2248      being a COMPARE of an arithmetic operation with the constant zero.
2249      The second element of the vector will set some pseudo to the result
2250      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2251      match such a pattern and so will generate an extra insn.   Here we test
2252      for this case, where both the comparison and the operation result are
2253      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2254      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2255
2256   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2257       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2258       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2259       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2260     {
2261 #ifdef SELECT_CC_MODE
2262       rtx *cc_use;
2263       enum machine_mode compare_mode;
2264 #endif
2265
2266       newpat = PATTERN (i3);
2267       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2268
2269       i2_is_used = 1;
2270
2271 #ifdef SELECT_CC_MODE
2272       /* See if a COMPARE with the operand we substituted in should be done
2273          with the mode that is currently being used.  If not, do the same
2274          processing we do in `subst' for a SET; namely, if the destination
2275          is used only once, try to replace it with a register of the proper
2276          mode and also replace the COMPARE.  */
2277       if (undobuf.other_insn == 0
2278           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2279                                         &undobuf.other_insn))
2280           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2281                                               i2src, const0_rtx))
2282               != GET_MODE (SET_DEST (newpat))))
2283         {
2284           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2285                                    compare_mode))
2286             {
2287               unsigned int regno = REGNO (SET_DEST (newpat));
2288               rtx new_dest;
2289
2290               if (regno < FIRST_PSEUDO_REGISTER)
2291                 new_dest = gen_rtx_REG (compare_mode, regno);
2292               else
2293                 {
2294                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2295                   new_dest = regno_reg_rtx[regno];
2296                 }
2297
2298               SUBST (SET_DEST (newpat), new_dest);
2299               SUBST (XEXP (*cc_use, 0), new_dest);
2300               SUBST (SET_SRC (newpat),
2301                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2302             }
2303           else
2304             undobuf.other_insn = 0;
2305         }
2306 #endif
2307     }
2308   else
2309 #endif
2310     {
2311       /* It is possible that the source of I2 or I1 may be performing
2312          an unneeded operation, such as a ZERO_EXTEND of something
2313          that is known to have the high part zero.  Handle that case
2314          by letting subst look at the innermost one of them.
2315
2316          Another way to do this would be to have a function that tries
2317          to simplify a single insn instead of merging two or more
2318          insns.  We don't do this because of the potential of infinite
2319          loops and because of the potential extra memory required.
2320          However, doing it the way we are is a bit of a kludge and
2321          doesn't catch all cases.
2322
2323          But only do this if -fexpensive-optimizations since it slows
2324          things down and doesn't usually win.
2325
2326          This is not done in the COMPARE case above because the
2327          unmodified I2PAT is used in the PARALLEL and so a pattern
2328          with a modified I2SRC would not match.  */
2329
2330       if (flag_expensive_optimizations)
2331         {
2332           /* Pass pc_rtx so no substitutions are done, just
2333              simplifications.  */
2334           if (i1)
2335             {
2336               subst_low_cuid = INSN_CUID (i1);
2337               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2338             }
2339           else
2340             {
2341               subst_low_cuid = INSN_CUID (i2);
2342               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2343             }
2344         }
2345
2346       n_occurrences = 0;                /* `subst' counts here */
2347
2348       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2349          need to make a unique copy of I2SRC each time we substitute it
2350          to avoid self-referential rtl.  */
2351
2352       subst_low_cuid = INSN_CUID (i2);
2353       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2354                       ! i1_feeds_i3 && i1dest_in_i1src);
2355       substed_i2 = 1;
2356
2357       /* Record whether i2's body now appears within i3's body.  */
2358       i2_is_used = n_occurrences;
2359     }
2360
2361   /* If we already got a failure, don't try to do more.  Otherwise,
2362      try to substitute in I1 if we have it.  */
2363
2364   if (i1 && GET_CODE (newpat) != CLOBBER)
2365     {
2366       /* Before we can do this substitution, we must redo the test done
2367          above (see detailed comments there) that ensures  that I1DEST
2368          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2369
2370       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2371                               0, (rtx*) 0))
2372         {
2373           undo_all ();
2374           return 0;
2375         }
2376
2377       n_occurrences = 0;
2378       subst_low_cuid = INSN_CUID (i1);
2379       newpat = subst (newpat, i1dest, i1src, 0, 0);
2380       substed_i1 = 1;
2381     }
2382
2383   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2384      to count all the ways that I2SRC and I1SRC can be used.  */
2385   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2386        && i2_is_used + added_sets_2 > 1)
2387       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2388           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2389               > 1))
2390       /* Fail if we tried to make a new register.  */
2391       || max_reg_num () != maxreg
2392       /* Fail if we couldn't do something and have a CLOBBER.  */
2393       || GET_CODE (newpat) == CLOBBER
2394       /* Fail if this new pattern is a MULT and we didn't have one before
2395          at the outer level.  */
2396       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2397           && ! have_mult))
2398     {
2399       undo_all ();
2400       return 0;
2401     }
2402
2403   /* If the actions of the earlier insns must be kept
2404      in addition to substituting them into the latest one,
2405      we must make a new PARALLEL for the latest insn
2406      to hold additional the SETs.  */
2407
2408   if (added_sets_1 || added_sets_2)
2409     {
2410       combine_extras++;
2411
2412       if (GET_CODE (newpat) == PARALLEL)
2413         {
2414           rtvec old = XVEC (newpat, 0);
2415           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2416           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2417           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2418                   sizeof (old->elem[0]) * old->num_elem);
2419         }
2420       else
2421         {
2422           rtx old = newpat;
2423           total_sets = 1 + added_sets_1 + added_sets_2;
2424           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2425           XVECEXP (newpat, 0, 0) = old;
2426         }
2427
2428       if (added_sets_1)
2429         XVECEXP (newpat, 0, --total_sets) = i1pat;
2430
2431       if (added_sets_2)
2432         {
2433           /* If there is no I1, use I2's body as is.  We used to also not do
2434              the subst call below if I2 was substituted into I3,
2435              but that could lose a simplification.  */
2436           if (i1 == 0)
2437             XVECEXP (newpat, 0, --total_sets) = i2pat;
2438           else
2439             /* See comment where i2pat is assigned.  */
2440             XVECEXP (newpat, 0, --total_sets)
2441               = subst (i2pat, i1dest, i1src, 0, 0);
2442         }
2443     }
2444
2445   /* We come here when we are replacing a destination in I2 with the
2446      destination of I3.  */
2447  validate_replacement:
2448
2449   /* Note which hard regs this insn has as inputs.  */
2450   mark_used_regs_combine (newpat);
2451
2452   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2453      consider splitting this pattern, we might need these clobbers.  */
2454   if (i1 && GET_CODE (newpat) == PARALLEL
2455       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2456     {
2457       int len = XVECLEN (newpat, 0);
2458
2459       newpat_vec_with_clobbers = rtvec_alloc (len);
2460       for (i = 0; i < len; i++)
2461         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2462     }
2463
2464   /* Is the result of combination a valid instruction?  */
2465   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2466
2467   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2468      the second SET's destination is a register that is unused and isn't
2469      marked as an instruction that might trap in an EH region.  In that case,
2470      we just need the first SET.   This can occur when simplifying a divmod
2471      insn.  We *must* test for this case here because the code below that
2472      splits two independent SETs doesn't handle this case correctly when it
2473      updates the register status.
2474
2475      It's pointless doing this if we originally had two sets, one from
2476      i3, and one from i2.  Combining then splitting the parallel results
2477      in the original i2 again plus an invalid insn (which we delete).
2478      The net effect is only to move instructions around, which makes
2479      debug info less accurate.
2480
2481      Also check the case where the first SET's destination is unused.
2482      That would not cause incorrect code, but does cause an unneeded
2483      insn to remain.  */
2484
2485   if (insn_code_number < 0
2486       && !(added_sets_2 && i1 == 0)
2487       && GET_CODE (newpat) == PARALLEL
2488       && XVECLEN (newpat, 0) == 2
2489       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2490       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2491       && asm_noperands (newpat) < 0)
2492     {
2493       rtx set0 = XVECEXP (newpat, 0, 0);
2494       rtx set1 = XVECEXP (newpat, 0, 1);
2495       rtx note;
2496
2497       if (((REG_P (SET_DEST (set1))
2498             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2499            || (GET_CODE (SET_DEST (set1)) == SUBREG
2500                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2501           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2502               || INTVAL (XEXP (note, 0)) <= 0)
2503           && ! side_effects_p (SET_SRC (set1)))
2504         {
2505           newpat = set0;
2506           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2507         }
2508
2509       else if (((REG_P (SET_DEST (set0))
2510                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2511                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2512                     && find_reg_note (i3, REG_UNUSED,
2513                                       SUBREG_REG (SET_DEST (set0)))))
2514                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2515                    || INTVAL (XEXP (note, 0)) <= 0)
2516                && ! side_effects_p (SET_SRC (set0)))
2517         {
2518           newpat = set1;
2519           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2520
2521           if (insn_code_number >= 0)
2522             {
2523               /* If we will be able to accept this, we have made a
2524                  change to the destination of I3.  This requires us to
2525                  do a few adjustments.  */
2526
2527               PATTERN (i3) = newpat;
2528               adjust_for_new_dest (i3);
2529             }
2530         }
2531     }
2532
2533   /* If we were combining three insns and the result is a simple SET
2534      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2535      insns.  There are two ways to do this.  It can be split using a
2536      machine-specific method (like when you have an addition of a large
2537      constant) or by combine in the function find_split_point.  */
2538
2539   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2540       && asm_noperands (newpat) < 0)
2541     {
2542       rtx m_split, *split;
2543
2544       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2545          use I2DEST as a scratch register will help.  In the latter case,
2546          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2547
2548       m_split = split_insns (newpat, i3);
2549
2550       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2551          inputs of NEWPAT.  */
2552
2553       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2554          possible to try that as a scratch reg.  This would require adding
2555          more code to make it work though.  */
2556
2557       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2558         {
2559           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2560
2561           /* First try to split using the original register as a
2562              scratch register.  */
2563           m_split = split_insns (gen_rtx_PARALLEL
2564                                  (VOIDmode,
2565                                   gen_rtvec (2, newpat,
2566                                              gen_rtx_CLOBBER (VOIDmode,
2567                                                               i2dest))),
2568                                  i3);
2569
2570           /* If that didn't work, try changing the mode of I2DEST if
2571              we can.  */
2572           if (m_split == 0
2573               && new_mode != GET_MODE (i2dest)
2574               && new_mode != VOIDmode
2575               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2576             {
2577               enum machine_mode old_mode = GET_MODE (i2dest);
2578               rtx ni2dest;
2579
2580               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2581                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2582               else
2583                 {
2584                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2585                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2586                 }
2587
2588               m_split = split_insns (gen_rtx_PARALLEL
2589                                      (VOIDmode,
2590                                       gen_rtvec (2, newpat,
2591                                                  gen_rtx_CLOBBER (VOIDmode,
2592                                                                   ni2dest))),
2593                                      i3);
2594
2595               if (m_split == 0
2596                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2597                 {
2598                   struct undo *buf;
2599
2600                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2601                   buf = undobuf.undos;
2602                   undobuf.undos = buf->next;
2603                   buf->next = undobuf.frees;
2604                   undobuf.frees = buf;
2605                 }
2606             }
2607         }
2608
2609       /* If recog_for_combine has discarded clobbers, try to use them
2610          again for the split.  */
2611       if (m_split == 0 && newpat_vec_with_clobbers)
2612         m_split
2613           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2614                                            newpat_vec_with_clobbers), i3);
2615
2616       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2617         {
2618           m_split = PATTERN (m_split);
2619           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2620           if (insn_code_number >= 0)
2621             newpat = m_split;
2622         }
2623       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2624                && (next_real_insn (i2) == i3
2625                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2626         {
2627           rtx i2set, i3set;
2628           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2629           newi2pat = PATTERN (m_split);
2630
2631           i3set = single_set (NEXT_INSN (m_split));
2632           i2set = single_set (m_split);
2633
2634           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2635
2636           /* If I2 or I3 has multiple SETs, we won't know how to track
2637              register status, so don't use these insns.  If I2's destination
2638              is used between I2 and I3, we also can't use these insns.  */
2639
2640           if (i2_code_number >= 0 && i2set && i3set
2641               && (next_real_insn (i2) == i3
2642                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2643             insn_code_number = recog_for_combine (&newi3pat, i3,
2644                                                   &new_i3_notes);
2645           if (insn_code_number >= 0)
2646             newpat = newi3pat;
2647
2648           /* It is possible that both insns now set the destination of I3.
2649              If so, we must show an extra use of it.  */
2650
2651           if (insn_code_number >= 0)
2652             {
2653               rtx new_i3_dest = SET_DEST (i3set);
2654               rtx new_i2_dest = SET_DEST (i2set);
2655
2656               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2657                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2658                      || GET_CODE (new_i3_dest) == SUBREG)
2659                 new_i3_dest = XEXP (new_i3_dest, 0);
2660
2661               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2662                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2663                      || GET_CODE (new_i2_dest) == SUBREG)
2664                 new_i2_dest = XEXP (new_i2_dest, 0);
2665
2666               if (REG_P (new_i3_dest)
2667                   && REG_P (new_i2_dest)
2668                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2669                 REG_N_SETS (REGNO (new_i2_dest))++;
2670             }
2671         }
2672
2673       /* If we can split it and use I2DEST, go ahead and see if that
2674          helps things be recognized.  Verify that none of the registers
2675          are set between I2 and I3.  */
2676       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2677 #ifdef HAVE_cc0
2678           && REG_P (i2dest)
2679 #endif
2680           /* We need I2DEST in the proper mode.  If it is a hard register
2681              or the only use of a pseudo, we can change its mode.
2682              Make sure we don't change a hard register to have a mode that
2683              isn't valid for it, or change the number of registers.  */
2684           && (GET_MODE (*split) == GET_MODE (i2dest)
2685               || GET_MODE (*split) == VOIDmode
2686               || can_change_dest_mode (i2dest, added_sets_2,
2687                                        GET_MODE (*split)))
2688           && (next_real_insn (i2) == i3
2689               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2690           /* We can't overwrite I2DEST if its value is still used by
2691              NEWPAT.  */
2692           && ! reg_referenced_p (i2dest, newpat))
2693         {
2694           rtx newdest = i2dest;
2695           enum rtx_code split_code = GET_CODE (*split);
2696           enum machine_mode split_mode = GET_MODE (*split);
2697           bool subst_done = false;
2698           newi2pat = NULL_RTX;
2699
2700           /* Get NEWDEST as a register in the proper mode.  We have already
2701              validated that we can do this.  */
2702           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2703             {
2704               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2705                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2706               else
2707                 {
2708                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2709                   newdest = regno_reg_rtx[REGNO (i2dest)];
2710                 }
2711             }
2712
2713           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2714              an ASHIFT.  This can occur if it was inside a PLUS and hence
2715              appeared to be a memory address.  This is a kludge.  */
2716           if (split_code == MULT
2717               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2718               && INTVAL (XEXP (*split, 1)) > 0
2719               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2720             {
2721               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2722                                              XEXP (*split, 0), GEN_INT (i)));
2723               /* Update split_code because we may not have a multiply
2724                  anymore.  */
2725               split_code = GET_CODE (*split);
2726             }
2727
2728 #ifdef INSN_SCHEDULING
2729           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2730              be written as a ZERO_EXTEND.  */
2731           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2732             {
2733 #ifdef LOAD_EXTEND_OP
2734               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2735                  what it really is.  */
2736               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2737                   == SIGN_EXTEND)
2738                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2739                                                     SUBREG_REG (*split)));
2740               else
2741 #endif
2742                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2743                                                     SUBREG_REG (*split)));
2744             }
2745 #endif
2746
2747           /* Attempt to split binary operators using arithmetic identities.  */
2748           if (BINARY_P (SET_SRC (newpat))
2749               && split_mode == GET_MODE (SET_SRC (newpat))
2750               && ! side_effects_p (SET_SRC (newpat)))
2751             {
2752               rtx setsrc = SET_SRC (newpat);
2753               enum machine_mode mode = GET_MODE (setsrc);
2754               enum rtx_code code = GET_CODE (setsrc);
2755               rtx src_op0 = XEXP (setsrc, 0);
2756               rtx src_op1 = XEXP (setsrc, 1);
2757
2758               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2759               if (rtx_equal_p (src_op0, src_op1))
2760                 {
2761                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2762                   SUBST (XEXP (setsrc, 0), newdest);
2763                   SUBST (XEXP (setsrc, 1), newdest);
2764                   subst_done = true;
2765                 }
2766               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2767               else if ((code == PLUS || code == MULT)
2768                        && GET_CODE (src_op0) == code
2769                        && GET_CODE (XEXP (src_op0, 0)) == code
2770                        && (INTEGRAL_MODE_P (mode)
2771                            || (FLOAT_MODE_P (mode)
2772                                && flag_unsafe_math_optimizations)))
2773                 {
2774                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2775                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2776                   rtx r = XEXP (src_op0, 1);
2777                   rtx s = src_op1;
2778
2779                   /* Split both "((X op Y) op X) op Y" and
2780                      "((X op Y) op Y) op X" as "T op T" where T is
2781                      "X op Y".  */
2782                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2783                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2784                     {
2785                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2786                                               XEXP (src_op0, 0));
2787                       SUBST (XEXP (setsrc, 0), newdest);
2788                       SUBST (XEXP (setsrc, 1), newdest);
2789                       subst_done = true;
2790                     }
2791                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2792                      T is "X op Y".  */
2793                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2794                     {
2795                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2796                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2797                       SUBST (XEXP (setsrc, 0), newdest);
2798                       SUBST (XEXP (setsrc, 1), newdest);
2799                       subst_done = true;
2800                     }
2801                 }
2802             }
2803
2804           if (!subst_done)
2805             {
2806               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2807               SUBST (*split, newdest);
2808             }
2809
2810           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2811
2812           /* recog_for_combine might have added CLOBBERs to newi2pat.
2813              Make sure NEWPAT does not depend on the clobbered regs.  */
2814           if (GET_CODE (newi2pat) == PARALLEL)
2815             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2816               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2817                 {
2818                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2819                   if (reg_overlap_mentioned_p (reg, newpat))
2820                     {
2821                       undo_all ();
2822                       return 0;
2823                     }
2824                 }
2825
2826           /* If the split point was a MULT and we didn't have one before,
2827              don't use one now.  */
2828           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2829             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2830         }
2831     }
2832
2833   /* Check for a case where we loaded from memory in a narrow mode and
2834      then sign extended it, but we need both registers.  In that case,
2835      we have a PARALLEL with both loads from the same memory location.
2836      We can split this into a load from memory followed by a register-register
2837      copy.  This saves at least one insn, more if register allocation can
2838      eliminate the copy.
2839
2840      We cannot do this if the destination of the first assignment is a
2841      condition code register or cc0.  We eliminate this case by making sure
2842      the SET_DEST and SET_SRC have the same mode.
2843
2844      We cannot do this if the destination of the second assignment is
2845      a register that we have already assumed is zero-extended.  Similarly
2846      for a SUBREG of such a register.  */
2847
2848   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2849            && GET_CODE (newpat) == PARALLEL
2850            && XVECLEN (newpat, 0) == 2
2851            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2852            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2853            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2854                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2855            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2856            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2857                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2858            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2859                                    INSN_CUID (i2))
2860            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2861            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2862            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2863                  (REG_P (temp)
2864                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2865                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2866                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2867                   && (reg_stat[REGNO (temp)].nonzero_bits
2868                       != GET_MODE_MASK (word_mode))))
2869            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2870                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2871                      (REG_P (temp)
2872                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2873                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2874                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2875                       && (reg_stat[REGNO (temp)].nonzero_bits
2876                           != GET_MODE_MASK (word_mode)))))
2877            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2878                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2879            && ! find_reg_note (i3, REG_UNUSED,
2880                                SET_DEST (XVECEXP (newpat, 0, 0))))
2881     {
2882       rtx ni2dest;
2883
2884       newi2pat = XVECEXP (newpat, 0, 0);
2885       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2886       newpat = XVECEXP (newpat, 0, 1);
2887       SUBST (SET_SRC (newpat),
2888              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2889       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2890
2891       if (i2_code_number >= 0)
2892         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2893
2894       if (insn_code_number >= 0)
2895         swap_i2i3 = 1;
2896     }
2897
2898   /* Similarly, check for a case where we have a PARALLEL of two independent
2899      SETs but we started with three insns.  In this case, we can do the sets
2900      as two separate insns.  This case occurs when some SET allows two
2901      other insns to combine, but the destination of that SET is still live.  */
2902
2903   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2904            && GET_CODE (newpat) == PARALLEL
2905            && XVECLEN (newpat, 0) == 2
2906            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2907            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2908            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2909            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2910            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2911            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2912            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2913                                    INSN_CUID (i2))
2914            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2915                                   XVECEXP (newpat, 0, 0))
2916            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2917                                   XVECEXP (newpat, 0, 1))
2918            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2919                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2920 #ifdef HAVE_cc0
2921            /* We cannot split the parallel into two sets if both sets
2922               reference cc0.  */
2923            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2924                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2925 #endif
2926            )
2927     {
2928       /* Normally, it doesn't matter which of the two is done first,
2929          but it does if one references cc0.  In that case, it has to
2930          be first.  */
2931 #ifdef HAVE_cc0
2932       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2933         {
2934           newi2pat = XVECEXP (newpat, 0, 0);
2935           newpat = XVECEXP (newpat, 0, 1);
2936         }
2937       else
2938 #endif
2939         {
2940           newi2pat = XVECEXP (newpat, 0, 1);
2941           newpat = XVECEXP (newpat, 0, 0);
2942         }
2943
2944       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2945
2946       if (i2_code_number >= 0)
2947         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2948     }
2949
2950   /* If it still isn't recognized, fail and change things back the way they
2951      were.  */
2952   if ((insn_code_number < 0
2953        /* Is the result a reasonable ASM_OPERANDS?  */
2954        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2955     {
2956       undo_all ();
2957       return 0;
2958     }
2959
2960   /* If we had to change another insn, make sure it is valid also.  */
2961   if (undobuf.other_insn)
2962     {
2963       rtx other_pat = PATTERN (undobuf.other_insn);
2964       rtx new_other_notes;
2965       rtx note, next;
2966
2967       CLEAR_HARD_REG_SET (newpat_used_regs);
2968
2969       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2970                                              &new_other_notes);
2971
2972       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2973         {
2974           undo_all ();
2975           return 0;
2976         }
2977
2978       PATTERN (undobuf.other_insn) = other_pat;
2979
2980       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2981          are still valid.  Then add any non-duplicate notes added by
2982          recog_for_combine.  */
2983       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2984         {
2985           next = XEXP (note, 1);
2986
2987           if (REG_NOTE_KIND (note) == REG_UNUSED
2988               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2989             {
2990               if (REG_P (XEXP (note, 0)))
2991                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2992
2993               remove_note (undobuf.other_insn, note);
2994             }
2995         }
2996
2997       for (note = new_other_notes; note; note = XEXP (note, 1))
2998         if (REG_P (XEXP (note, 0)))
2999           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
3000
3001       distribute_notes (new_other_notes, undobuf.other_insn,
3002                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3003     }
3004 #ifdef HAVE_cc0
3005   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3006      they are adjacent to each other or not.  */
3007   {
3008     rtx p = prev_nonnote_insn (i3);
3009     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3010         && sets_cc0_p (newi2pat))
3011       {
3012         undo_all ();
3013         return 0;
3014       }
3015   }
3016 #endif
3017
3018   /* Only allow this combination if insn_rtx_costs reports that the
3019      replacement instructions are cheaper than the originals.  */
3020   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3021     {
3022       undo_all ();
3023       return 0;
3024     }
3025
3026   /* We now know that we can do this combination.  Merge the insns and
3027      update the status of registers and LOG_LINKS.  */
3028
3029   if (swap_i2i3)
3030     {
3031       rtx insn;
3032       rtx link;
3033       rtx ni2dest;
3034
3035       /* I3 now uses what used to be its destination and which is now
3036          I2's destination.  This requires us to do a few adjustments.  */
3037       PATTERN (i3) = newpat;
3038       adjust_for_new_dest (i3);
3039
3040       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3041          so we still will.
3042
3043          However, some later insn might be using I2's dest and have
3044          a LOG_LINK pointing at I3.  We must remove this link.
3045          The simplest way to remove the link is to point it at I1,
3046          which we know will be a NOTE.  */
3047
3048       /* newi2pat is usually a SET here; however, recog_for_combine might
3049          have added some clobbers.  */
3050       if (GET_CODE (newi2pat) == PARALLEL)
3051         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3052       else
3053         ni2dest = SET_DEST (newi2pat);
3054
3055       for (insn = NEXT_INSN (i3);
3056            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3057                     || insn != BB_HEAD (this_basic_block->next_bb));
3058            insn = NEXT_INSN (insn))
3059         {
3060           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3061             {
3062               for (link = LOG_LINKS (insn); link;
3063                    link = XEXP (link, 1))
3064                 if (XEXP (link, 0) == i3)
3065                   XEXP (link, 0) = i1;
3066
3067               break;
3068             }
3069         }
3070     }
3071
3072   {
3073     rtx i3notes, i2notes, i1notes = 0;
3074     rtx i3links, i2links, i1links = 0;
3075     rtx midnotes = 0;
3076     unsigned int regno;
3077     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3078        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3079        same as i3dest, in which case newi2pat may be setting i1dest.  */
3080     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3081                    || i2dest_in_i2src || i2dest_in_i1src
3082                    || !i2dest_killed
3083                    ? 0 : i2dest);
3084     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3085                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3086                    || !i1dest_killed
3087                    ? 0 : i1dest);
3088
3089     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3090        clear them.  */
3091     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3092     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3093     if (i1)
3094       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3095
3096     /* Ensure that we do not have something that should not be shared but
3097        occurs multiple times in the new insns.  Check this by first
3098        resetting all the `used' flags and then copying anything is shared.  */
3099
3100     reset_used_flags (i3notes);
3101     reset_used_flags (i2notes);
3102     reset_used_flags (i1notes);
3103     reset_used_flags (newpat);
3104     reset_used_flags (newi2pat);
3105     if (undobuf.other_insn)
3106       reset_used_flags (PATTERN (undobuf.other_insn));
3107
3108     i3notes = copy_rtx_if_shared (i3notes);
3109     i2notes = copy_rtx_if_shared (i2notes);
3110     i1notes = copy_rtx_if_shared (i1notes);
3111     newpat = copy_rtx_if_shared (newpat);
3112     newi2pat = copy_rtx_if_shared (newi2pat);
3113     if (undobuf.other_insn)
3114       reset_used_flags (PATTERN (undobuf.other_insn));
3115
3116     INSN_CODE (i3) = insn_code_number;
3117     PATTERN (i3) = newpat;
3118
3119     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3120       {
3121         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3122
3123         reset_used_flags (call_usage);
3124         call_usage = copy_rtx (call_usage);
3125
3126         if (substed_i2)
3127           replace_rtx (call_usage, i2dest, i2src);
3128
3129         if (substed_i1)
3130           replace_rtx (call_usage, i1dest, i1src);
3131
3132         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3133       }
3134
3135     if (undobuf.other_insn)
3136       INSN_CODE (undobuf.other_insn) = other_code_number;
3137
3138     /* We had one special case above where I2 had more than one set and
3139        we replaced a destination of one of those sets with the destination
3140        of I3.  In that case, we have to update LOG_LINKS of insns later
3141        in this basic block.  Note that this (expensive) case is rare.
3142
3143        Also, in this case, we must pretend that all REG_NOTEs for I2
3144        actually came from I3, so that REG_UNUSED notes from I2 will be
3145        properly handled.  */
3146
3147     if (i3_subst_into_i2)
3148       {
3149         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3150           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3151                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3152               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3153               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3154               && ! find_reg_note (i2, REG_UNUSED,
3155                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3156             for (temp = NEXT_INSN (i2);
3157                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3158                           || BB_HEAD (this_basic_block) != temp);
3159                  temp = NEXT_INSN (temp))
3160               if (temp != i3 && INSN_P (temp))
3161                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3162                   if (XEXP (link, 0) == i2)
3163                     XEXP (link, 0) = i3;
3164
3165         if (i3notes)
3166           {
3167             rtx link = i3notes;
3168             while (XEXP (link, 1))
3169               link = XEXP (link, 1);
3170             XEXP (link, 1) = i2notes;
3171           }
3172         else
3173           i3notes = i2notes;
3174         i2notes = 0;
3175       }
3176
3177     LOG_LINKS (i3) = 0;
3178     REG_NOTES (i3) = 0;
3179     LOG_LINKS (i2) = 0;
3180     REG_NOTES (i2) = 0;
3181
3182     if (newi2pat)
3183       {
3184         INSN_CODE (i2) = i2_code_number;
3185         PATTERN (i2) = newi2pat;
3186       }
3187     else
3188       SET_INSN_DELETED (i2);
3189
3190     if (i1)
3191       {
3192         LOG_LINKS (i1) = 0;
3193         REG_NOTES (i1) = 0;
3194         SET_INSN_DELETED (i1);
3195       }
3196
3197     /* Get death notes for everything that is now used in either I3 or
3198        I2 and used to die in a previous insn.  If we built two new
3199        patterns, move from I1 to I2 then I2 to I3 so that we get the
3200        proper movement on registers that I2 modifies.  */
3201
3202     if (newi2pat)
3203       {
3204         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3205         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3206       }
3207     else
3208       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3209                    i3, &midnotes);
3210
3211     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3212     if (i3notes)
3213       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3214                         elim_i2, elim_i1);
3215     if (i2notes)
3216       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3217                         elim_i2, elim_i1);
3218     if (i1notes)
3219       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3220                         elim_i2, elim_i1);
3221     if (midnotes)
3222       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3223                         elim_i2, elim_i1);
3224
3225     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3226        know these are REG_UNUSED and want them to go to the desired insn,
3227        so we always pass it as i3.  We have not counted the notes in
3228        reg_n_deaths yet, so we need to do so now.  */
3229
3230     if (newi2pat && new_i2_notes)
3231       {
3232         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3233           if (REG_P (XEXP (temp, 0)))
3234             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3235
3236         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3237       }
3238
3239     if (new_i3_notes)
3240       {
3241         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3242           if (REG_P (XEXP (temp, 0)))
3243             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3244
3245         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3246       }
3247
3248     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3249        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3250        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3251        in that case, it might delete I2.  Similarly for I2 and I1.
3252        Show an additional death due to the REG_DEAD note we make here.  If
3253        we discard it in distribute_notes, we will decrement it again.  */
3254
3255     if (i3dest_killed)
3256       {
3257         if (REG_P (i3dest_killed))
3258           REG_N_DEATHS (REGNO (i3dest_killed))++;
3259
3260         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3261           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3262                                                NULL_RTX),
3263                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3264         else
3265           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3266                                                NULL_RTX),
3267                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3268                             elim_i2, elim_i1);
3269       }
3270
3271     if (i2dest_in_i2src)
3272       {
3273         if (REG_P (i2dest))
3274           REG_N_DEATHS (REGNO (i2dest))++;
3275
3276         if (newi2pat && reg_set_p (i2dest, newi2pat))
3277           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3278                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3279         else
3280           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3281                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3282                             NULL_RTX, NULL_RTX);
3283       }
3284
3285     if (i1dest_in_i1src)
3286       {
3287         if (REG_P (i1dest))
3288           REG_N_DEATHS (REGNO (i1dest))++;
3289
3290         if (newi2pat && reg_set_p (i1dest, newi2pat))
3291           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3292                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3293         else
3294           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3295                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3296                             NULL_RTX, NULL_RTX);
3297       }
3298
3299     distribute_links (i3links);
3300     distribute_links (i2links);
3301     distribute_links (i1links);
3302
3303     if (REG_P (i2dest))
3304       {
3305         rtx link;
3306         rtx i2_insn = 0, i2_val = 0, set;
3307
3308         /* The insn that used to set this register doesn't exist, and
3309            this life of the register may not exist either.  See if one of
3310            I3's links points to an insn that sets I2DEST.  If it does,
3311            that is now the last known value for I2DEST. If we don't update
3312            this and I2 set the register to a value that depended on its old
3313            contents, we will get confused.  If this insn is used, thing
3314            will be set correctly in combine_instructions.  */
3315
3316         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3317           if ((set = single_set (XEXP (link, 0))) != 0
3318               && rtx_equal_p (i2dest, SET_DEST (set)))
3319             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3320
3321         record_value_for_reg (i2dest, i2_insn, i2_val);
3322
3323         /* If the reg formerly set in I2 died only once and that was in I3,
3324            zero its use count so it won't make `reload' do any work.  */
3325         if (! added_sets_2
3326             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3327             && ! i2dest_in_i2src)
3328           {
3329             regno = REGNO (i2dest);
3330             REG_N_SETS (regno)--;
3331           }
3332       }
3333
3334     if (i1 && REG_P (i1dest))
3335       {
3336         rtx link;
3337         rtx i1_insn = 0, i1_val = 0, set;
3338
3339         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3340           if ((set = single_set (XEXP (link, 0))) != 0
3341               && rtx_equal_p (i1dest, SET_DEST (set)))
3342             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3343
3344         record_value_for_reg (i1dest, i1_insn, i1_val);
3345
3346         regno = REGNO (i1dest);
3347         if (! added_sets_1 && ! i1dest_in_i1src)
3348           REG_N_SETS (regno)--;
3349       }
3350
3351     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3352        been made to this insn.  The order of
3353        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3354        can affect nonzero_bits of newpat */
3355     if (newi2pat)
3356       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3357     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3358
3359     /* Set new_direct_jump_p if a new return or simple jump instruction
3360        has been created.
3361
3362        If I3 is now an unconditional jump, ensure that it has a
3363        BARRIER following it since it may have initially been a
3364        conditional jump.  It may also be the last nonnote insn.  */
3365
3366     if (returnjump_p (i3) || any_uncondjump_p (i3))
3367       {
3368         *new_direct_jump_p = 1;
3369         mark_jump_label (PATTERN (i3), i3, 0);
3370
3371         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3372             || !BARRIER_P (temp))
3373           emit_barrier_after (i3);
3374       }
3375
3376     if (undobuf.other_insn != NULL_RTX
3377         && (returnjump_p (undobuf.other_insn)
3378             || any_uncondjump_p (undobuf.other_insn)))
3379       {
3380         *new_direct_jump_p = 1;
3381
3382         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3383             || !BARRIER_P (temp))
3384           emit_barrier_after (undobuf.other_insn);
3385       }
3386
3387     /* An NOOP jump does not need barrier, but it does need cleaning up
3388        of CFG.  */
3389     if (GET_CODE (newpat) == SET
3390         && SET_SRC (newpat) == pc_rtx
3391         && SET_DEST (newpat) == pc_rtx)
3392       *new_direct_jump_p = 1;
3393   }
3394
3395   combine_successes++;
3396   undo_commit ();
3397
3398   if (added_links_insn
3399       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3400       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3401     return added_links_insn;
3402   else
3403     return newi2pat ? i2 : i3;
3404 }
3405 \f
3406 /* Undo all the modifications recorded in undobuf.  */
3407
3408 static void
3409 undo_all (void)
3410 {
3411   struct undo *undo, *next;
3412
3413   for (undo = undobuf.undos; undo; undo = next)
3414     {
3415       next = undo->next;
3416       switch (undo->kind)
3417         {
3418         case UNDO_RTX:
3419           *undo->where.r = undo->old_contents.r;
3420           break;
3421         case UNDO_INT:
3422           *undo->where.i = undo->old_contents.i;
3423           break;
3424         case UNDO_MODE:
3425           PUT_MODE (*undo->where.r, undo->old_contents.m);
3426           break;
3427         default:
3428           gcc_unreachable ();
3429         }
3430
3431       undo->next = undobuf.frees;
3432       undobuf.frees = undo;
3433     }
3434
3435   undobuf.undos = 0;
3436 }
3437
3438 /* We've committed to accepting the changes we made.  Move all
3439    of the undos to the free list.  */
3440
3441 static void
3442 undo_commit (void)
3443 {
3444   struct undo *undo, *next;
3445
3446   for (undo = undobuf.undos; undo; undo = next)
3447     {
3448       next = undo->next;
3449       undo->next = undobuf.frees;
3450       undobuf.frees = undo;
3451     }
3452   undobuf.undos = 0;
3453 }
3454 \f
3455 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3456    where we have an arithmetic expression and return that point.  LOC will
3457    be inside INSN.
3458
3459    try_combine will call this function to see if an insn can be split into
3460    two insns.  */
3461
3462 static rtx *
3463 find_split_point (rtx *loc, rtx insn)
3464 {
3465   rtx x = *loc;
3466   enum rtx_code code = GET_CODE (x);
3467   rtx *split;
3468   unsigned HOST_WIDE_INT len = 0;
3469   HOST_WIDE_INT pos = 0;
3470   int unsignedp = 0;
3471   rtx inner = NULL_RTX;
3472
3473   /* First special-case some codes.  */
3474   switch (code)
3475     {
3476     case SUBREG:
3477 #ifdef INSN_SCHEDULING
3478       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3479          point.  */
3480       if (MEM_P (SUBREG_REG (x)))
3481         return loc;
3482 #endif
3483       return find_split_point (&SUBREG_REG (x), insn);
3484
3485     case MEM:
3486 #ifdef HAVE_lo_sum
3487       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3488          using LO_SUM and HIGH.  */
3489       if (GET_CODE (XEXP (x, 0)) == CONST
3490           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3491         {
3492           SUBST (XEXP (x, 0),
3493                  gen_rtx_LO_SUM (Pmode,
3494                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3495                                  XEXP (x, 0)));
3496           return &XEXP (XEXP (x, 0), 0);
3497         }
3498 #endif
3499
3500       /* If we have a PLUS whose second operand is a constant and the
3501          address is not valid, perhaps will can split it up using
3502          the machine-specific way to split large constants.  We use
3503          the first pseudo-reg (one of the virtual regs) as a placeholder;
3504          it will not remain in the result.  */
3505       if (GET_CODE (XEXP (x, 0)) == PLUS
3506           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3507           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3508         {
3509           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3510           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3511                                  subst_insn);
3512
3513           /* This should have produced two insns, each of which sets our
3514              placeholder.  If the source of the second is a valid address,
3515              we can make put both sources together and make a split point
3516              in the middle.  */
3517
3518           if (seq
3519               && NEXT_INSN (seq) != NULL_RTX
3520               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3521               && NONJUMP_INSN_P (seq)
3522               && GET_CODE (PATTERN (seq)) == SET
3523               && SET_DEST (PATTERN (seq)) == reg
3524               && ! reg_mentioned_p (reg,
3525                                     SET_SRC (PATTERN (seq)))
3526               && NONJUMP_INSN_P (NEXT_INSN (seq))
3527               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3528               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3529               && memory_address_p (GET_MODE (x),
3530                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3531             {
3532               rtx src1 = SET_SRC (PATTERN (seq));
3533               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3534
3535               /* Replace the placeholder in SRC2 with SRC1.  If we can
3536                  find where in SRC2 it was placed, that can become our
3537                  split point and we can replace this address with SRC2.
3538                  Just try two obvious places.  */
3539
3540               src2 = replace_rtx (src2, reg, src1);
3541               split = 0;
3542               if (XEXP (src2, 0) == src1)
3543                 split = &XEXP (src2, 0);
3544               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3545                        && XEXP (XEXP (src2, 0), 0) == src1)
3546                 split = &XEXP (XEXP (src2, 0), 0);
3547
3548               if (split)
3549                 {
3550                   SUBST (XEXP (x, 0), src2);
3551                   return split;
3552                 }
3553             }
3554
3555           /* If that didn't work, perhaps the first operand is complex and
3556              needs to be computed separately, so make a split point there.
3557              This will occur on machines that just support REG + CONST
3558              and have a constant moved through some previous computation.  */
3559
3560           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3561                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3562                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3563             return &XEXP (XEXP (x, 0), 0);
3564         }
3565       break;
3566
3567     case SET:
3568 #ifdef HAVE_cc0
3569       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3570          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3571          we need to put the operand into a register.  So split at that
3572          point.  */
3573
3574       if (SET_DEST (x) == cc0_rtx
3575           && GET_CODE (SET_SRC (x)) != COMPARE
3576           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3577           && !OBJECT_P (SET_SRC (x))
3578           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3579                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3580         return &SET_SRC (x);
3581 #endif
3582
3583       /* See if we can split SET_SRC as it stands.  */
3584       split = find_split_point (&SET_SRC (x), insn);
3585       if (split && split != &SET_SRC (x))
3586         return split;
3587
3588       /* See if we can split SET_DEST as it stands.  */
3589       split = find_split_point (&SET_DEST (x), insn);
3590       if (split && split != &SET_DEST (x))
3591         return split;
3592
3593       /* See if this is a bitfield assignment with everything constant.  If
3594          so, this is an IOR of an AND, so split it into that.  */
3595       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3596           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3597               <= HOST_BITS_PER_WIDE_INT)
3598           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3599           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3600           && GET_CODE (SET_SRC (x)) == CONST_INT
3601           && ((INTVAL (XEXP (SET_DEST (x), 1))
3602                + INTVAL (XEXP (SET_DEST (x), 2)))
3603               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3604           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3605         {
3606           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3607           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3608           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3609           rtx dest = XEXP (SET_DEST (x), 0);
3610           enum machine_mode mode = GET_MODE (dest);
3611           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3612           rtx or_mask;
3613
3614           if (BITS_BIG_ENDIAN)
3615             pos = GET_MODE_BITSIZE (mode) - len - pos;
3616
3617           or_mask = gen_int_mode (src << pos, mode);
3618           if (src == mask)
3619             SUBST (SET_SRC (x),
3620                    simplify_gen_binary (IOR, mode, dest, or_mask));
3621           else
3622             {
3623               rtx negmask = gen_int_mode (~(mask << pos), mode);
3624               SUBST (SET_SRC (x),
3625                      simplify_gen_binary (IOR, mode,
3626                                           simplify_gen_binary (AND, mode,
3627                                                                dest, negmask),
3628                                           or_mask));
3629             }
3630
3631           SUBST (SET_DEST (x), dest);
3632
3633           split = find_split_point (&SET_SRC (x), insn);
3634           if (split && split != &SET_SRC (x))
3635             return split;
3636         }
3637
3638       /* Otherwise, see if this is an operation that we can split into two.
3639          If so, try to split that.  */
3640       code = GET_CODE (SET_SRC (x));
3641
3642       switch (code)
3643         {
3644         case AND:
3645           /* If we are AND'ing with a large constant that is only a single
3646              bit and the result is only being used in a context where we
3647              need to know if it is zero or nonzero, replace it with a bit
3648              extraction.  This will avoid the large constant, which might
3649              have taken more than one insn to make.  If the constant were
3650              not a valid argument to the AND but took only one insn to make,
3651              this is no worse, but if it took more than one insn, it will
3652              be better.  */
3653
3654           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3655               && REG_P (XEXP (SET_SRC (x), 0))
3656               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3657               && REG_P (SET_DEST (x))
3658               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3659               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3660               && XEXP (*split, 0) == SET_DEST (x)
3661               && XEXP (*split, 1) == const0_rtx)
3662             {
3663               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3664                                                 XEXP (SET_SRC (x), 0),
3665                                                 pos, NULL_RTX, 1, 1, 0, 0);
3666               if (extraction != 0)
3667                 {
3668                   SUBST (SET_SRC (x), extraction);
3669                   return find_split_point (loc, insn);
3670                 }
3671             }
3672           break;
3673
3674         case NE:
3675           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3676              is known to be on, this can be converted into a NEG of a shift.  */
3677           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3678               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3679               && 1 <= (pos = exact_log2
3680                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3681                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3682             {
3683               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3684
3685               SUBST (SET_SRC (x),
3686                      gen_rtx_NEG (mode,
3687                                   gen_rtx_LSHIFTRT (mode,
3688                                                     XEXP (SET_SRC (x), 0),
3689                                                     GEN_INT (pos))));
3690
3691               split = find_split_point (&SET_SRC (x), insn);
3692               if (split && split != &SET_SRC (x))
3693                 return split;
3694             }
3695           break;
3696
3697         case SIGN_EXTEND:
3698           inner = XEXP (SET_SRC (x), 0);
3699
3700           /* We can't optimize if either mode is a partial integer
3701              mode as we don't know how many bits are significant
3702              in those modes.  */
3703           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3704               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3705             break;
3706
3707           pos = 0;
3708           len = GET_MODE_BITSIZE (GET_MODE (inner));
3709           unsignedp = 0;
3710           break;
3711
3712         case SIGN_EXTRACT:
3713         case ZERO_EXTRACT:
3714           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3715               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3716             {
3717               inner = XEXP (SET_SRC (x), 0);
3718               len = INTVAL (XEXP (SET_SRC (x), 1));
3719               pos = INTVAL (XEXP (SET_SRC (x), 2));
3720
3721               if (BITS_BIG_ENDIAN)
3722                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3723               unsignedp = (code == ZERO_EXTRACT);
3724             }
3725           break;
3726
3727         default:
3728           break;
3729         }
3730
3731       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3732         {
3733           enum machine_mode mode = GET_MODE (SET_SRC (x));
3734
3735           /* For unsigned, we have a choice of a shift followed by an
3736              AND or two shifts.  Use two shifts for field sizes where the
3737              constant might be too large.  We assume here that we can
3738              always at least get 8-bit constants in an AND insn, which is
3739              true for every current RISC.  */
3740
3741           if (unsignedp && len <= 8)
3742             {
3743               SUBST (SET_SRC (x),
3744                      gen_rtx_AND (mode,
3745                                   gen_rtx_LSHIFTRT
3746                                   (mode, gen_lowpart (mode, inner),
3747                                    GEN_INT (pos)),
3748                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3749
3750               split = find_split_point (&SET_SRC (x), insn);
3751               if (split && split != &SET_SRC (x))
3752                 return split;
3753             }
3754           else
3755             {
3756               SUBST (SET_SRC (x),
3757                      gen_rtx_fmt_ee
3758                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3759                       gen_rtx_ASHIFT (mode,
3760                                       gen_lowpart (mode, inner),
3761                                       GEN_INT (GET_MODE_BITSIZE (mode)
3762                                                - len - pos)),
3763                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3764
3765               split = find_split_point (&SET_SRC (x), insn);
3766               if (split && split != &SET_SRC (x))
3767                 return split;
3768             }
3769         }
3770
3771       /* See if this is a simple operation with a constant as the second
3772          operand.  It might be that this constant is out of range and hence
3773          could be used as a split point.  */
3774       if (BINARY_P (SET_SRC (x))
3775           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3776           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3777               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3778                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3779         return &XEXP (SET_SRC (x), 1);
3780
3781       /* Finally, see if this is a simple operation with its first operand
3782          not in a register.  The operation might require this operand in a
3783          register, so return it as a split point.  We can always do this
3784          because if the first operand were another operation, we would have
3785          already found it as a split point.  */
3786       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3787           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3788         return &XEXP (SET_SRC (x), 0);
3789
3790       return 0;
3791
3792     case AND:
3793     case IOR:
3794       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3795          it is better to write this as (not (ior A B)) so we can split it.
3796          Similarly for IOR.  */
3797       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3798         {
3799           SUBST (*loc,
3800                  gen_rtx_NOT (GET_MODE (x),
3801                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3802                                               GET_MODE (x),
3803                                               XEXP (XEXP (x, 0), 0),
3804                                               XEXP (XEXP (x, 1), 0))));
3805           return find_split_point (loc, insn);
3806         }
3807
3808       /* Many RISC machines have a large set of logical insns.  If the
3809          second operand is a NOT, put it first so we will try to split the
3810          other operand first.  */
3811       if (GET_CODE (XEXP (x, 1)) == NOT)
3812         {
3813           rtx tem = XEXP (x, 0);
3814           SUBST (XEXP (x, 0), XEXP (x, 1));
3815           SUBST (XEXP (x, 1), tem);
3816         }
3817       break;
3818
3819     default:
3820       break;
3821     }
3822
3823   /* Otherwise, select our actions depending on our rtx class.  */
3824   switch (GET_RTX_CLASS (code))
3825     {
3826     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3827     case RTX_TERNARY:
3828       split = find_split_point (&XEXP (x, 2), insn);
3829       if (split)
3830         return split;
3831       /* ... fall through ...  */
3832     case RTX_BIN_ARITH:
3833     case RTX_COMM_ARITH:
3834     case RTX_COMPARE:
3835     case RTX_COMM_COMPARE:
3836       split = find_split_point (&XEXP (x, 1), insn);
3837       if (split)
3838         return split;
3839       /* ... fall through ...  */
3840     case RTX_UNARY:
3841       /* Some machines have (and (shift ...) ...) insns.  If X is not
3842          an AND, but XEXP (X, 0) is, use it as our split point.  */
3843       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3844         return &XEXP (x, 0);
3845
3846       split = find_split_point (&XEXP (x, 0), insn);
3847       if (split)
3848         return split;
3849       return loc;
3850
3851     default:
3852       /* Otherwise, we don't have a split point.  */
3853       return 0;
3854     }
3855 }
3856 \f
3857 /* Throughout X, replace FROM with TO, and return the result.
3858    The result is TO if X is FROM;
3859    otherwise the result is X, but its contents may have been modified.
3860    If they were modified, a record was made in undobuf so that
3861    undo_all will (among other things) return X to its original state.
3862
3863    If the number of changes necessary is too much to record to undo,
3864    the excess changes are not made, so the result is invalid.
3865    The changes already made can still be undone.
3866    undobuf.num_undo is incremented for such changes, so by testing that
3867    the caller can tell whether the result is valid.
3868
3869    `n_occurrences' is incremented each time FROM is replaced.
3870
3871    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3872
3873    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3874    by copying if `n_occurrences' is nonzero.  */
3875
3876 static rtx
3877 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3878 {
3879   enum rtx_code code = GET_CODE (x);
3880   enum machine_mode op0_mode = VOIDmode;
3881   const char *fmt;
3882   int len, i;
3883   rtx new;
3884
3885 /* Two expressions are equal if they are identical copies of a shared
3886    RTX or if they are both registers with the same register number
3887    and mode.  */
3888
3889 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3890   ((X) == (Y)                                           \
3891    || (REG_P (X) && REG_P (Y)   \
3892        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3893
3894   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3895     {
3896       n_occurrences++;
3897       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3898     }
3899
3900   /* If X and FROM are the same register but different modes, they will
3901      not have been seen as equal above.  However, flow.c will make a
3902      LOG_LINKS entry for that case.  If we do nothing, we will try to
3903      rerecognize our original insn and, when it succeeds, we will
3904      delete the feeding insn, which is incorrect.
3905
3906      So force this insn not to match in this (rare) case.  */
3907   if (! in_dest && code == REG && REG_P (from)
3908       && REGNO (x) == REGNO (from))
3909     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3910
3911   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3912      of which may contain things that can be combined.  */
3913   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3914     return x;
3915
3916   /* It is possible to have a subexpression appear twice in the insn.
3917      Suppose that FROM is a register that appears within TO.
3918      Then, after that subexpression has been scanned once by `subst',
3919      the second time it is scanned, TO may be found.  If we were
3920      to scan TO here, we would find FROM within it and create a
3921      self-referent rtl structure which is completely wrong.  */
3922   if (COMBINE_RTX_EQUAL_P (x, to))
3923     return to;
3924
3925   /* Parallel asm_operands need special attention because all of the
3926      inputs are shared across the arms.  Furthermore, unsharing the
3927      rtl results in recognition failures.  Failure to handle this case
3928      specially can result in circular rtl.
3929
3930      Solve this by doing a normal pass across the first entry of the
3931      parallel, and only processing the SET_DESTs of the subsequent
3932      entries.  Ug.  */
3933
3934   if (code == PARALLEL
3935       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3936       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3937     {
3938       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3939
3940       /* If this substitution failed, this whole thing fails.  */
3941       if (GET_CODE (new) == CLOBBER
3942           && XEXP (new, 0) == const0_rtx)
3943         return new;
3944
3945       SUBST (XVECEXP (x, 0, 0), new);
3946
3947       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3948         {
3949           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3950
3951           if (!REG_P (dest)
3952               && GET_CODE (dest) != CC0
3953               && GET_CODE (dest) != PC)
3954             {
3955               new = subst (dest, from, to, 0, unique_copy);
3956
3957               /* If this substitution failed, this whole thing fails.  */
3958               if (GET_CODE (new) == CLOBBER
3959                   && XEXP (new, 0) == const0_rtx)
3960                 return new;
3961
3962               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3963             }
3964         }
3965     }
3966   else
3967     {
3968       len = GET_RTX_LENGTH (code);
3969       fmt = GET_RTX_FORMAT (code);
3970
3971       /* We don't need to process a SET_DEST that is a register, CC0,
3972          or PC, so set up to skip this common case.  All other cases
3973          where we want to suppress replacing something inside a
3974          SET_SRC are handled via the IN_DEST operand.  */
3975       if (code == SET
3976           && (REG_P (SET_DEST (x))
3977               || GET_CODE (SET_DEST (x)) == CC0
3978               || GET_CODE (SET_DEST (x)) == PC))
3979         fmt = "ie";
3980
3981       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3982          constant.  */
3983       if (fmt[0] == 'e')
3984         op0_mode = GET_MODE (XEXP (x, 0));
3985
3986       for (i = 0; i < len; i++)
3987         {
3988           if (fmt[i] == 'E')
3989             {
3990               int j;
3991               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3992                 {
3993                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3994                     {
3995                       new = (unique_copy && n_occurrences
3996                              ? copy_rtx (to) : to);
3997                       n_occurrences++;
3998                     }
3999                   else
4000                     {
4001                       new = subst (XVECEXP (x, i, j), from, to, 0,
4002                                    unique_copy);
4003
4004                       /* If this substitution failed, this whole thing
4005                          fails.  */
4006                       if (GET_CODE (new) == CLOBBER
4007                           && XEXP (new, 0) == const0_rtx)
4008                         return new;
4009                     }
4010
4011                   SUBST (XVECEXP (x, i, j), new);
4012                 }
4013             }
4014           else if (fmt[i] == 'e')
4015             {
4016               /* If this is a register being set, ignore it.  */
4017               new = XEXP (x, i);
4018               if (in_dest
4019                   && i == 0
4020                   && (((code == SUBREG || code == ZERO_EXTRACT)
4021                        && REG_P (new))
4022                       || code == STRICT_LOW_PART))
4023                 ;
4024
4025               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4026                 {
4027                   /* In general, don't install a subreg involving two
4028                      modes not tieable.  It can worsen register
4029                      allocation, and can even make invalid reload
4030                      insns, since the reg inside may need to be copied
4031                      from in the outside mode, and that may be invalid
4032                      if it is an fp reg copied in integer mode.
4033
4034                      We allow two exceptions to this: It is valid if
4035                      it is inside another SUBREG and the mode of that
4036                      SUBREG and the mode of the inside of TO is
4037                      tieable and it is valid if X is a SET that copies
4038                      FROM to CC0.  */
4039
4040                   if (GET_CODE (to) == SUBREG
4041                       && ! MODES_TIEABLE_P (GET_MODE (to),
4042                                             GET_MODE (SUBREG_REG (to)))
4043                       && ! (code == SUBREG
4044                             && MODES_TIEABLE_P (GET_MODE (x),
4045                                                 GET_MODE (SUBREG_REG (to))))
4046 #ifdef HAVE_cc0
4047                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4048 #endif
4049                       )
4050                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4051
4052 #ifdef CANNOT_CHANGE_MODE_CLASS
4053                   if (code == SUBREG
4054                       && REG_P (to)
4055                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4056                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4057                                                    GET_MODE (to),
4058                                                    GET_MODE (x)))
4059                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4060 #endif
4061
4062                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4063                   n_occurrences++;
4064                 }
4065               else
4066                 /* If we are in a SET_DEST, suppress most cases unless we
4067                    have gone inside a MEM, in which case we want to
4068                    simplify the address.  We assume here that things that
4069                    are actually part of the destination have their inner
4070                    parts in the first expression.  This is true for SUBREG,
4071                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4072                    things aside from REG and MEM that should appear in a
4073                    SET_DEST.  */
4074                 new = subst (XEXP (x, i), from, to,
4075                              (((in_dest
4076                                 && (code == SUBREG || code == STRICT_LOW_PART
4077                                     || code == ZERO_EXTRACT))
4078                                || code == SET)
4079                               && i == 0), unique_copy);
4080
4081               /* If we found that we will have to reject this combination,
4082                  indicate that by returning the CLOBBER ourselves, rather than
4083                  an expression containing it.  This will speed things up as
4084                  well as prevent accidents where two CLOBBERs are considered
4085                  to be equal, thus producing an incorrect simplification.  */
4086
4087               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4088                 return new;
4089
4090               if (GET_CODE (x) == SUBREG
4091                   && (GET_CODE (new) == CONST_INT
4092                       || GET_CODE (new) == CONST_DOUBLE))
4093                 {
4094                   enum machine_mode mode = GET_MODE (x);
4095
4096                   x = simplify_subreg (GET_MODE (x), new,
4097                                        GET_MODE (SUBREG_REG (x)),
4098                                        SUBREG_BYTE (x));
4099                   if (! x)
4100                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4101                 }
4102               else if (GET_CODE (new) == CONST_INT
4103                        && GET_CODE (x) == ZERO_EXTEND)
4104                 {
4105                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4106                                                 new, GET_MODE (XEXP (x, 0)));
4107                   gcc_assert (x);
4108                 }
4109               else
4110                 SUBST (XEXP (x, i), new);
4111             }
4112         }
4113     }
4114
4115   /* Try to simplify X.  If the simplification changed the code, it is likely
4116      that further simplification will help, so loop, but limit the number
4117      of repetitions that will be performed.  */
4118
4119   for (i = 0; i < 4; i++)
4120     {
4121       /* If X is sufficiently simple, don't bother trying to do anything
4122          with it.  */
4123       if (code != CONST_INT && code != REG && code != CLOBBER)
4124         x = combine_simplify_rtx (x, op0_mode, in_dest);
4125
4126       if (GET_CODE (x) == code)
4127         break;
4128
4129       code = GET_CODE (x);
4130
4131       /* We no longer know the original mode of operand 0 since we
4132          have changed the form of X)  */
4133       op0_mode = VOIDmode;
4134     }
4135
4136   return x;
4137 }
4138 \f
4139 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4140    outer level; call `subst' to simplify recursively.  Return the new
4141    expression.
4142
4143    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4144    if we are inside a SET_DEST.  */
4145
4146 static rtx
4147 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4148 {
4149   enum rtx_code code = GET_CODE (x);
4150   enum machine_mode mode = GET_MODE (x);
4151   rtx temp;
4152   int i;
4153
4154   /* If this is a commutative operation, put a constant last and a complex
4155      expression first.  We don't need to do this for comparisons here.  */
4156   if (COMMUTATIVE_ARITH_P (x)
4157       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4158     {
4159       temp = XEXP (x, 0);
4160       SUBST (XEXP (x, 0), XEXP (x, 1));
4161       SUBST (XEXP (x, 1), temp);
4162     }
4163
4164   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4165      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4166      things.  Check for cases where both arms are testing the same
4167      condition.
4168
4169      Don't do anything if all operands are very simple.  */
4170
4171   if ((BINARY_P (x)
4172        && ((!OBJECT_P (XEXP (x, 0))
4173             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4174                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4175            || (!OBJECT_P (XEXP (x, 1))
4176                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4177                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4178       || (UNARY_P (x)
4179           && (!OBJECT_P (XEXP (x, 0))
4180                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4181                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4182     {
4183       rtx cond, true_rtx, false_rtx;
4184
4185       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4186       if (cond != 0
4187           /* If everything is a comparison, what we have is highly unlikely
4188              to be simpler, so don't use it.  */
4189           && ! (COMPARISON_P (x)
4190                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4191         {
4192           rtx cop1 = const0_rtx;
4193           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4194
4195           if (cond_code == NE && COMPARISON_P (cond))
4196             return x;
4197
4198           /* Simplify the alternative arms; this may collapse the true and
4199              false arms to store-flag values.  Be careful to use copy_rtx
4200              here since true_rtx or false_rtx might share RTL with x as a
4201              result of the if_then_else_cond call above.  */
4202           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4203           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4204
4205           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4206              is unlikely to be simpler.  */
4207           if (general_operand (true_rtx, VOIDmode)
4208               && general_operand (false_rtx, VOIDmode))
4209             {
4210               enum rtx_code reversed;
4211
4212               /* Restarting if we generate a store-flag expression will cause
4213                  us to loop.  Just drop through in this case.  */
4214
4215               /* If the result values are STORE_FLAG_VALUE and zero, we can
4216                  just make the comparison operation.  */
4217               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4218                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4219                                              cond, cop1);
4220               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4221                        && ((reversed = reversed_comparison_code_parts
4222                                         (cond_code, cond, cop1, NULL))
4223                            != UNKNOWN))
4224                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4225                                              cond, cop1);
4226
4227               /* Likewise, we can make the negate of a comparison operation
4228                  if the result values are - STORE_FLAG_VALUE and zero.  */
4229               else if (GET_CODE (true_rtx) == CONST_INT
4230                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4231                        && false_rtx == const0_rtx)
4232                 x = simplify_gen_unary (NEG, mode,
4233                                         simplify_gen_relational (cond_code,
4234                                                                  mode, VOIDmode,
4235                                                                  cond, cop1),
4236                                         mode);
4237               else if (GET_CODE (false_rtx) == CONST_INT
4238                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4239                        && true_rtx == const0_rtx
4240                        && ((reversed = reversed_comparison_code_parts
4241                                         (cond_code, cond, cop1, NULL))
4242                            != UNKNOWN))
4243                 x = simplify_gen_unary (NEG, mode,
4244                                         simplify_gen_relational (reversed,
4245                                                                  mode, VOIDmode,
4246                                                                  cond, cop1),
4247                                         mode);
4248               else
4249                 return gen_rtx_IF_THEN_ELSE (mode,
4250                                              simplify_gen_relational (cond_code,
4251                                                                       mode,
4252                                                                       VOIDmode,
4253                                                                       cond,
4254                                                                       cop1),
4255                                              true_rtx, false_rtx);
4256
4257               code = GET_CODE (x);
4258               op0_mode = VOIDmode;
4259             }
4260         }
4261     }
4262
4263   /* Try to fold this expression in case we have constants that weren't
4264      present before.  */
4265   temp = 0;
4266   switch (GET_RTX_CLASS (code))
4267     {
4268     case RTX_UNARY:
4269       if (op0_mode == VOIDmode)
4270         op0_mode = GET_MODE (XEXP (x, 0));
4271       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4272       break;
4273     case RTX_COMPARE:
4274     case RTX_COMM_COMPARE:
4275       {
4276         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4277         if (cmp_mode == VOIDmode)
4278           {
4279             cmp_mode = GET_MODE (XEXP (x, 1));
4280             if (cmp_mode == VOIDmode)
4281               cmp_mode = op0_mode;
4282           }
4283         temp = simplify_relational_operation (code, mode, cmp_mode,
4284                                               XEXP (x, 0), XEXP (x, 1));
4285       }
4286       break;
4287     case RTX_COMM_ARITH:
4288     case RTX_BIN_ARITH:
4289       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4290       break;
4291     case RTX_BITFIELD_OPS:
4292     case RTX_TERNARY:
4293       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4294                                          XEXP (x, 1), XEXP (x, 2));
4295       break;
4296     default:
4297       break;
4298     }
4299
4300   if (temp)
4301     {
4302       x = temp;
4303       code = GET_CODE (temp);
4304       op0_mode = VOIDmode;
4305       mode = GET_MODE (temp);
4306     }
4307
4308   /* First see if we can apply the inverse distributive law.  */
4309   if (code == PLUS || code == MINUS
4310       || code == AND || code == IOR || code == XOR)
4311     {
4312       x = apply_distributive_law (x);
4313       code = GET_CODE (x);
4314       op0_mode = VOIDmode;
4315     }
4316
4317   /* If CODE is an associative operation not otherwise handled, see if we
4318      can associate some operands.  This can win if they are constants or
4319      if they are logically related (i.e. (a & b) & a).  */
4320   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4321        || code == AND || code == IOR || code == XOR
4322        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4323       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4324           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4325     {
4326       if (GET_CODE (XEXP (x, 0)) == code)
4327         {
4328           rtx other = XEXP (XEXP (x, 0), 0);
4329           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4330           rtx inner_op1 = XEXP (x, 1);
4331           rtx inner;
4332
4333           /* Make sure we pass the constant operand if any as the second
4334              one if this is a commutative operation.  */
4335           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4336             {
4337               rtx tem = inner_op0;
4338               inner_op0 = inner_op1;
4339               inner_op1 = tem;
4340             }
4341           inner = simplify_binary_operation (code == MINUS ? PLUS
4342                                              : code == DIV ? MULT
4343                                              : code,
4344                                              mode, inner_op0, inner_op1);
4345
4346           /* For commutative operations, try the other pair if that one
4347              didn't simplify.  */
4348           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4349             {
4350               other = XEXP (XEXP (x, 0), 1);
4351               inner = simplify_binary_operation (code, mode,
4352                                                  XEXP (XEXP (x, 0), 0),
4353                                                  XEXP (x, 1));
4354             }
4355
4356           if (inner)
4357             return simplify_gen_binary (code, mode, other, inner);
4358         }
4359     }
4360
4361   /* A little bit of algebraic simplification here.  */
4362   switch (code)
4363     {
4364     case MEM:
4365       /* Ensure that our address has any ASHIFTs converted to MULT in case
4366          address-recognizing predicates are called later.  */
4367       temp = make_compound_operation (XEXP (x, 0), MEM);
4368       SUBST (XEXP (x, 0), temp);
4369       break;
4370
4371     case SUBREG:
4372       if (op0_mode == VOIDmode)
4373         op0_mode = GET_MODE (SUBREG_REG (x));
4374
4375       /* See if this can be moved to simplify_subreg.  */
4376       if (CONSTANT_P (SUBREG_REG (x))
4377           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4378              /* Don't call gen_lowpart if the inner mode
4379                 is VOIDmode and we cannot simplify it, as SUBREG without
4380                 inner mode is invalid.  */
4381           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4382               || gen_lowpart_common (mode, SUBREG_REG (x))))
4383         return gen_lowpart (mode, SUBREG_REG (x));
4384
4385       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4386         break;
4387       {
4388         rtx temp;
4389         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4390                                 SUBREG_BYTE (x));
4391         if (temp)
4392           return temp;
4393       }
4394
4395       /* Don't change the mode of the MEM if that would change the meaning
4396          of the address.  */
4397       if (MEM_P (SUBREG_REG (x))
4398           && (MEM_VOLATILE_P (SUBREG_REG (x))
4399               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4400         return gen_rtx_CLOBBER (mode, const0_rtx);
4401
4402       /* Note that we cannot do any narrowing for non-constants since
4403          we might have been counting on using the fact that some bits were
4404          zero.  We now do this in the SET.  */
4405
4406       break;
4407
4408     case NEG:
4409       temp = expand_compound_operation (XEXP (x, 0));
4410
4411       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4412          replaced by (lshiftrt X C).  This will convert
4413          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4414
4415       if (GET_CODE (temp) == ASHIFTRT
4416           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4417           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4418         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4419                                      INTVAL (XEXP (temp, 1)));
4420
4421       /* If X has only a single bit that might be nonzero, say, bit I, convert
4422          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4423          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4424          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4425          or a SUBREG of one since we'd be making the expression more
4426          complex if it was just a register.  */
4427
4428       if (!REG_P (temp)
4429           && ! (GET_CODE (temp) == SUBREG
4430                 && REG_P (SUBREG_REG (temp)))
4431           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4432         {
4433           rtx temp1 = simplify_shift_const
4434             (NULL_RTX, ASHIFTRT, mode,
4435              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4436                                    GET_MODE_BITSIZE (mode) - 1 - i),
4437              GET_MODE_BITSIZE (mode) - 1 - i);
4438
4439           /* If all we did was surround TEMP with the two shifts, we
4440              haven't improved anything, so don't use it.  Otherwise,
4441              we are better off with TEMP1.  */
4442           if (GET_CODE (temp1) != ASHIFTRT
4443               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4444               || XEXP (XEXP (temp1, 0), 0) != temp)
4445             return temp1;
4446         }
4447       break;
4448
4449     case TRUNCATE:
4450       /* We can't handle truncation to a partial integer mode here
4451          because we don't know the real bitsize of the partial
4452          integer mode.  */
4453       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4454         break;
4455
4456       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4457           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4458                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4459         SUBST (XEXP (x, 0),
4460                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4461                               GET_MODE_MASK (mode), 0));
4462
4463       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4464          whose value is a comparison can be replaced with a subreg if
4465          STORE_FLAG_VALUE permits.  */
4466       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4467           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4468           && (temp = get_last_value (XEXP (x, 0)))
4469           && COMPARISON_P (temp))
4470         return gen_lowpart (mode, XEXP (x, 0));
4471       break;
4472
4473 #ifdef HAVE_cc0
4474     case COMPARE:
4475       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4476          using cc0, in which case we want to leave it as a COMPARE
4477          so we can distinguish it from a register-register-copy.  */
4478       if (XEXP (x, 1) == const0_rtx)
4479         return XEXP (x, 0);
4480
4481       /* x - 0 is the same as x unless x's mode has signed zeros and
4482          allows rounding towards -infinity.  Under those conditions,
4483          0 - 0 is -0.  */
4484       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4485             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4486           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4487         return XEXP (x, 0);
4488       break;
4489 #endif
4490
4491     case CONST:
4492       /* (const (const X)) can become (const X).  Do it this way rather than
4493          returning the inner CONST since CONST can be shared with a
4494          REG_EQUAL note.  */
4495       if (GET_CODE (XEXP (x, 0)) == CONST)
4496         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4497       break;
4498
4499 #ifdef HAVE_lo_sum
4500     case LO_SUM:
4501       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4502          can add in an offset.  find_split_point will split this address up
4503          again if it doesn't match.  */
4504       if (GET_CODE (XEXP (x, 0)) == HIGH
4505           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4506         return XEXP (x, 1);
4507       break;
4508 #endif
4509
4510     case PLUS:
4511       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4512          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4513          bit-field and can be replaced by either a sign_extend or a
4514          sign_extract.  The `and' may be a zero_extend and the two
4515          <c>, -<c> constants may be reversed.  */
4516       if (GET_CODE (XEXP (x, 0)) == XOR
4517           && GET_CODE (XEXP (x, 1)) == CONST_INT
4518           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4519           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4520           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4521               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4522           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4523           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4524                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4525                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4526                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4527               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4528                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4529                       == (unsigned int) i + 1))))
4530         return simplify_shift_const
4531           (NULL_RTX, ASHIFTRT, mode,
4532            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4533                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4534                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4535            GET_MODE_BITSIZE (mode) - (i + 1));
4536
4537       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4538          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4539          the bitsize of the mode - 1.  This allows simplification of
4540          "a = (b & 8) == 0;"  */
4541       if (XEXP (x, 1) == constm1_rtx
4542           && !REG_P (XEXP (x, 0))
4543           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4544                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4545           && nonzero_bits (XEXP (x, 0), mode) == 1)
4546         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4547            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4548                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4549                                  GET_MODE_BITSIZE (mode) - 1),
4550            GET_MODE_BITSIZE (mode) - 1);
4551
4552       /* If we are adding two things that have no bits in common, convert
4553          the addition into an IOR.  This will often be further simplified,
4554          for example in cases like ((a & 1) + (a & 2)), which can
4555          become a & 3.  */
4556
4557       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4558           && (nonzero_bits (XEXP (x, 0), mode)
4559               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4560         {
4561           /* Try to simplify the expression further.  */
4562           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4563           temp = combine_simplify_rtx (tor, mode, in_dest);
4564
4565           /* If we could, great.  If not, do not go ahead with the IOR
4566              replacement, since PLUS appears in many special purpose
4567              address arithmetic instructions.  */
4568           if (GET_CODE (temp) != CLOBBER && temp != tor)
4569             return temp;
4570         }
4571       break;
4572
4573     case MINUS:
4574       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4575          (and <foo> (const_int pow2-1))  */
4576       if (GET_CODE (XEXP (x, 1)) == AND
4577           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4578           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4579           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4580         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4581                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4582       break;
4583
4584     case MULT:
4585       /* If we have (mult (plus A B) C), apply the distributive law and then
4586          the inverse distributive law to see if things simplify.  This
4587          occurs mostly in addresses, often when unrolling loops.  */
4588
4589       if (GET_CODE (XEXP (x, 0)) == PLUS)
4590         {
4591           rtx result = distribute_and_simplify_rtx (x, 0);
4592           if (result)
4593             return result;
4594         }
4595
4596       /* Try simplify a*(b/c) as (a*b)/c.  */
4597       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4598           && GET_CODE (XEXP (x, 0)) == DIV)
4599         {
4600           rtx tem = simplify_binary_operation (MULT, mode,
4601                                                XEXP (XEXP (x, 0), 0),
4602                                                XEXP (x, 1));
4603           if (tem)
4604             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4605         }
4606       break;
4607
4608     case UDIV:
4609       /* If this is a divide by a power of two, treat it as a shift if
4610          its first operand is a shift.  */
4611       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4612           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4613           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4614               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4615               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4616               || GET_CODE (XEXP (x, 0)) == ROTATE
4617               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4618         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4619       break;
4620
4621     case EQ:  case NE:
4622     case GT:  case GTU:  case GE:  case GEU:
4623     case LT:  case LTU:  case LE:  case LEU:
4624     case UNEQ:  case LTGT:
4625     case UNGT:  case UNGE:
4626     case UNLT:  case UNLE:
4627     case UNORDERED: case ORDERED:
4628       /* If the first operand is a condition code, we can't do anything
4629          with it.  */
4630       if (GET_CODE (XEXP (x, 0)) == COMPARE
4631           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4632               && ! CC0_P (XEXP (x, 0))))
4633         {
4634           rtx op0 = XEXP (x, 0);
4635           rtx op1 = XEXP (x, 1);
4636           enum rtx_code new_code;
4637
4638           if (GET_CODE (op0) == COMPARE)
4639             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4640
4641           /* Simplify our comparison, if possible.  */
4642           new_code = simplify_comparison (code, &op0, &op1);
4643
4644           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4645              if only the low-order bit is possibly nonzero in X (such as when
4646              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4647              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4648              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4649              (plus X 1).
4650
4651              Remove any ZERO_EXTRACT we made when thinking this was a
4652              comparison.  It may now be simpler to use, e.g., an AND.  If a
4653              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4654              the call to make_compound_operation in the SET case.  */
4655
4656           if (STORE_FLAG_VALUE == 1
4657               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4658               && op1 == const0_rtx
4659               && mode == GET_MODE (op0)
4660               && nonzero_bits (op0, mode) == 1)
4661             return gen_lowpart (mode,
4662                                 expand_compound_operation (op0));
4663
4664           else if (STORE_FLAG_VALUE == 1
4665                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4666                    && op1 == const0_rtx
4667                    && mode == GET_MODE (op0)
4668                    && (num_sign_bit_copies (op0, mode)
4669                        == GET_MODE_BITSIZE (mode)))
4670             {
4671               op0 = expand_compound_operation (op0);
4672               return simplify_gen_unary (NEG, mode,
4673                                          gen_lowpart (mode, op0),
4674                                          mode);
4675             }
4676
4677           else if (STORE_FLAG_VALUE == 1
4678                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4679                    && op1 == const0_rtx
4680                    && mode == GET_MODE (op0)
4681                    && nonzero_bits (op0, mode) == 1)
4682             {
4683               op0 = expand_compound_operation (op0);
4684               return simplify_gen_binary (XOR, mode,
4685                                           gen_lowpart (mode, op0),
4686                                           const1_rtx);
4687             }
4688
4689           else if (STORE_FLAG_VALUE == 1
4690                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4691                    && op1 == const0_rtx
4692                    && mode == GET_MODE (op0)
4693                    && (num_sign_bit_copies (op0, mode)
4694                        == GET_MODE_BITSIZE (mode)))
4695             {
4696               op0 = expand_compound_operation (op0);
4697               return plus_constant (gen_lowpart (mode, op0), 1);
4698             }
4699
4700           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4701              those above.  */
4702           if (STORE_FLAG_VALUE == -1
4703               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4704               && op1 == const0_rtx
4705               && (num_sign_bit_copies (op0, mode)
4706                   == GET_MODE_BITSIZE (mode)))
4707             return gen_lowpart (mode,
4708                                 expand_compound_operation (op0));
4709
4710           else if (STORE_FLAG_VALUE == -1
4711                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4712                    && op1 == const0_rtx
4713                    && mode == GET_MODE (op0)
4714                    && nonzero_bits (op0, mode) == 1)
4715             {
4716               op0 = expand_compound_operation (op0);
4717               return simplify_gen_unary (NEG, mode,
4718                                          gen_lowpart (mode, op0),
4719                                          mode);
4720             }
4721
4722           else if (STORE_FLAG_VALUE == -1
4723                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4724                    && op1 == const0_rtx
4725                    && mode == GET_MODE (op0)
4726                    && (num_sign_bit_copies (op0, mode)
4727                        == GET_MODE_BITSIZE (mode)))
4728             {
4729               op0 = expand_compound_operation (op0);
4730               return simplify_gen_unary (NOT, mode,
4731                                          gen_lowpart (mode, op0),
4732                                          mode);
4733             }
4734
4735           /* If X is 0/1, (eq X 0) is X-1.  */
4736           else if (STORE_FLAG_VALUE == -1
4737                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4738                    && op1 == const0_rtx
4739                    && mode == GET_MODE (op0)
4740                    && nonzero_bits (op0, mode) == 1)
4741             {
4742               op0 = expand_compound_operation (op0);
4743               return plus_constant (gen_lowpart (mode, op0), -1);
4744             }
4745
4746           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4747              one bit that might be nonzero, we can convert (ne x 0) to
4748              (ashift x c) where C puts the bit in the sign bit.  Remove any
4749              AND with STORE_FLAG_VALUE when we are done, since we are only
4750              going to test the sign bit.  */
4751           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4752               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4753               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4754                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4755               && op1 == const0_rtx
4756               && mode == GET_MODE (op0)
4757               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4758             {
4759               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4760                                         expand_compound_operation (op0),
4761                                         GET_MODE_BITSIZE (mode) - 1 - i);
4762               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4763                 return XEXP (x, 0);
4764               else
4765                 return x;
4766             }
4767
4768           /* If the code changed, return a whole new comparison.  */
4769           if (new_code != code)
4770             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4771
4772           /* Otherwise, keep this operation, but maybe change its operands.
4773              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4774           SUBST (XEXP (x, 0), op0);
4775           SUBST (XEXP (x, 1), op1);
4776         }
4777       break;
4778
4779     case IF_THEN_ELSE:
4780       return simplify_if_then_else (x);
4781
4782     case ZERO_EXTRACT:
4783     case SIGN_EXTRACT:
4784     case ZERO_EXTEND:
4785     case SIGN_EXTEND:
4786       /* If we are processing SET_DEST, we are done.  */
4787       if (in_dest)
4788         return x;
4789
4790       return expand_compound_operation (x);
4791
4792     case SET:
4793       return simplify_set (x);
4794
4795     case AND:
4796     case IOR:
4797       return simplify_logical (x);
4798
4799     case ASHIFT:
4800     case LSHIFTRT:
4801     case ASHIFTRT:
4802     case ROTATE:
4803     case ROTATERT:
4804       /* If this is a shift by a constant amount, simplify it.  */
4805       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4806         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4807                                      INTVAL (XEXP (x, 1)));
4808
4809       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4810         SUBST (XEXP (x, 1),
4811                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4812                               ((HOST_WIDE_INT) 1
4813                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4814                               - 1,
4815                               0));
4816       break;
4817
4818     default:
4819       break;
4820     }
4821
4822   return x;
4823 }
4824 \f
4825 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4826
4827 static rtx
4828 simplify_if_then_else (rtx x)
4829 {
4830   enum machine_mode mode = GET_MODE (x);
4831   rtx cond = XEXP (x, 0);
4832   rtx true_rtx = XEXP (x, 1);
4833   rtx false_rtx = XEXP (x, 2);
4834   enum rtx_code true_code = GET_CODE (cond);
4835   int comparison_p = COMPARISON_P (cond);
4836   rtx temp;
4837   int i;
4838   enum rtx_code false_code;
4839   rtx reversed;
4840
4841   /* Simplify storing of the truth value.  */
4842   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4843     return simplify_gen_relational (true_code, mode, VOIDmode,
4844                                     XEXP (cond, 0), XEXP (cond, 1));
4845
4846   /* Also when the truth value has to be reversed.  */
4847   if (comparison_p
4848       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4849       && (reversed = reversed_comparison (cond, mode)))
4850     return reversed;
4851
4852   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4853      in it is being compared against certain values.  Get the true and false
4854      comparisons and see if that says anything about the value of each arm.  */
4855
4856   if (comparison_p
4857       && ((false_code = reversed_comparison_code (cond, NULL))
4858           != UNKNOWN)
4859       && REG_P (XEXP (cond, 0)))
4860     {
4861       HOST_WIDE_INT nzb;
4862       rtx from = XEXP (cond, 0);
4863       rtx true_val = XEXP (cond, 1);
4864       rtx false_val = true_val;
4865       int swapped = 0;
4866
4867       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4868
4869       if (false_code == EQ)
4870         {
4871           swapped = 1, true_code = EQ, false_code = NE;
4872           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4873         }
4874
4875       /* If we are comparing against zero and the expression being tested has
4876          only a single bit that might be nonzero, that is its value when it is
4877          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4878
4879       if (true_code == EQ && true_val == const0_rtx
4880           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4881         false_code = EQ, false_val = GEN_INT (nzb);
4882       else if (true_code == EQ && true_val == const0_rtx
4883                && (num_sign_bit_copies (from, GET_MODE (from))
4884                    == GET_MODE_BITSIZE (GET_MODE (from))))
4885         false_code = EQ, false_val = constm1_rtx;
4886
4887       /* Now simplify an arm if we know the value of the register in the
4888          branch and it is used in the arm.  Be careful due to the potential
4889          of locally-shared RTL.  */
4890
4891       if (reg_mentioned_p (from, true_rtx))
4892         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4893                                       from, true_val),
4894                       pc_rtx, pc_rtx, 0, 0);
4895       if (reg_mentioned_p (from, false_rtx))
4896         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4897                                    from, false_val),
4898                        pc_rtx, pc_rtx, 0, 0);
4899
4900       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4901       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4902
4903       true_rtx = XEXP (x, 1);
4904       false_rtx = XEXP (x, 2);
4905       true_code = GET_CODE (cond);
4906     }
4907
4908   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4909      reversed, do so to avoid needing two sets of patterns for
4910      subtract-and-branch insns.  Similarly if we have a constant in the true
4911      arm, the false arm is the same as the first operand of the comparison, or
4912      the false arm is more complicated than the true arm.  */
4913
4914   if (comparison_p
4915       && reversed_comparison_code (cond, NULL) != UNKNOWN
4916       && (true_rtx == pc_rtx
4917           || (CONSTANT_P (true_rtx)
4918               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4919           || true_rtx == const0_rtx
4920           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4921           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4922               && !OBJECT_P (false_rtx))
4923           || reg_mentioned_p (true_rtx, false_rtx)
4924           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4925     {
4926       true_code = reversed_comparison_code (cond, NULL);
4927       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4928       SUBST (XEXP (x, 1), false_rtx);
4929       SUBST (XEXP (x, 2), true_rtx);
4930
4931       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4932       cond = XEXP (x, 0);
4933
4934       /* It is possible that the conditional has been simplified out.  */
4935       true_code = GET_CODE (cond);
4936       comparison_p = COMPARISON_P (cond);
4937     }
4938
4939   /* If the two arms are identical, we don't need the comparison.  */
4940
4941   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4942     return true_rtx;
4943
4944   /* Convert a == b ? b : a to "a".  */
4945   if (true_code == EQ && ! side_effects_p (cond)
4946       && !HONOR_NANS (mode)
4947       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4948       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4949     return false_rtx;
4950   else if (true_code == NE && ! side_effects_p (cond)
4951            && !HONOR_NANS (mode)
4952            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4953            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4954     return true_rtx;
4955
4956   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4957
4958   if (GET_MODE_CLASS (mode) == MODE_INT
4959       && GET_CODE (false_rtx) == NEG
4960       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4961       && comparison_p
4962       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4963       && ! side_effects_p (true_rtx))
4964     switch (true_code)
4965       {
4966       case GT:
4967       case GE:
4968         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4969       case LT:
4970       case LE:
4971         return
4972           simplify_gen_unary (NEG, mode,
4973                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4974                               mode);
4975       default:
4976         break;
4977       }
4978
4979   /* Look for MIN or MAX.  */
4980
4981   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4982       && comparison_p
4983       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4984       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4985       && ! side_effects_p (cond))
4986     switch (true_code)
4987       {
4988       case GE:
4989       case GT:
4990         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4991       case LE:
4992       case LT:
4993         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4994       case GEU:
4995       case GTU:
4996         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4997       case LEU:
4998       case LTU:
4999         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5000       default:
5001         break;
5002       }
5003
5004   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5005      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5006      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5007      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5008      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5009      neither 1 or -1, but it isn't worth checking for.  */
5010
5011   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5012       && comparison_p
5013       && GET_MODE_CLASS (mode) == MODE_INT
5014       && ! side_effects_p (x))
5015     {
5016       rtx t = make_compound_operation (true_rtx, SET);
5017       rtx f = make_compound_operation (false_rtx, SET);
5018       rtx cond_op0 = XEXP (cond, 0);
5019       rtx cond_op1 = XEXP (cond, 1);
5020       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5021       enum machine_mode m = mode;
5022       rtx z = 0, c1 = NULL_RTX;
5023
5024       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5025            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5026            || GET_CODE (t) == ASHIFT
5027            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5028           && rtx_equal_p (XEXP (t, 0), f))
5029         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5030
5031       /* If an identity-zero op is commutative, check whether there
5032          would be a match if we swapped the operands.  */
5033       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5034                 || GET_CODE (t) == XOR)
5035                && rtx_equal_p (XEXP (t, 1), f))
5036         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5037       else if (GET_CODE (t) == SIGN_EXTEND
5038                && (GET_CODE (XEXP (t, 0)) == PLUS
5039                    || GET_CODE (XEXP (t, 0)) == MINUS
5040                    || GET_CODE (XEXP (t, 0)) == IOR
5041                    || GET_CODE (XEXP (t, 0)) == XOR
5042                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5043                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5044                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5045                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5046                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5047                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5048                && (num_sign_bit_copies (f, GET_MODE (f))
5049                    > (unsigned int)
5050                      (GET_MODE_BITSIZE (mode)
5051                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5052         {
5053           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5054           extend_op = SIGN_EXTEND;
5055           m = GET_MODE (XEXP (t, 0));
5056         }
5057       else if (GET_CODE (t) == SIGN_EXTEND
5058                && (GET_CODE (XEXP (t, 0)) == PLUS
5059                    || GET_CODE (XEXP (t, 0)) == IOR
5060                    || GET_CODE (XEXP (t, 0)) == XOR)
5061                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5062                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5063                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5064                && (num_sign_bit_copies (f, GET_MODE (f))
5065                    > (unsigned int)
5066                      (GET_MODE_BITSIZE (mode)
5067                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5068         {
5069           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5070           extend_op = SIGN_EXTEND;
5071           m = GET_MODE (XEXP (t, 0));
5072         }
5073       else if (GET_CODE (t) == ZERO_EXTEND
5074                && (GET_CODE (XEXP (t, 0)) == PLUS
5075                    || GET_CODE (XEXP (t, 0)) == MINUS
5076                    || GET_CODE (XEXP (t, 0)) == IOR
5077                    || GET_CODE (XEXP (t, 0)) == XOR
5078                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5079                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5080                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5081                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5082                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5083                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5084                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5085                && ((nonzero_bits (f, GET_MODE (f))
5086                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5087                    == 0))
5088         {
5089           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5090           extend_op = ZERO_EXTEND;
5091           m = GET_MODE (XEXP (t, 0));
5092         }
5093       else if (GET_CODE (t) == ZERO_EXTEND
5094                && (GET_CODE (XEXP (t, 0)) == PLUS
5095                    || GET_CODE (XEXP (t, 0)) == IOR
5096                    || GET_CODE (XEXP (t, 0)) == XOR)
5097                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5098                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5099                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5100                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5101                && ((nonzero_bits (f, GET_MODE (f))
5102                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5103                    == 0))
5104         {
5105           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5106           extend_op = ZERO_EXTEND;
5107           m = GET_MODE (XEXP (t, 0));
5108         }
5109
5110       if (z)
5111         {
5112           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5113                                                  cond_op0, cond_op1),
5114                         pc_rtx, pc_rtx, 0, 0);
5115           temp = simplify_gen_binary (MULT, m, temp,
5116                                       simplify_gen_binary (MULT, m, c1,
5117                                                            const_true_rtx));
5118           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5119           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5120
5121           if (extend_op != UNKNOWN)
5122             temp = simplify_gen_unary (extend_op, mode, temp, m);
5123
5124           return temp;
5125         }
5126     }
5127
5128   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5129      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5130      negation of a single bit, we can convert this operation to a shift.  We
5131      can actually do this more generally, but it doesn't seem worth it.  */
5132
5133   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5134       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5135       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5136            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5137           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5138                == GET_MODE_BITSIZE (mode))
5139               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5140     return
5141       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5142                             gen_lowpart (mode, XEXP (cond, 0)), i);
5143
5144   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5145   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5146       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5147       && GET_MODE (XEXP (cond, 0)) == mode
5148       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5149           == nonzero_bits (XEXP (cond, 0), mode)
5150       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5151     return XEXP (cond, 0);
5152
5153   return x;
5154 }
5155 \f
5156 /* Simplify X, a SET expression.  Return the new expression.  */
5157
5158 static rtx
5159 simplify_set (rtx x)
5160 {
5161   rtx src = SET_SRC (x);
5162   rtx dest = SET_DEST (x);
5163   enum machine_mode mode
5164     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5165   rtx other_insn;
5166   rtx *cc_use;
5167
5168   /* (set (pc) (return)) gets written as (return).  */
5169   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5170     return src;
5171
5172   /* Now that we know for sure which bits of SRC we are using, see if we can
5173      simplify the expression for the object knowing that we only need the
5174      low-order bits.  */
5175
5176   if (GET_MODE_CLASS (mode) == MODE_INT
5177       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5178     {
5179       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5180       SUBST (SET_SRC (x), src);
5181     }
5182
5183   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5184      the comparison result and try to simplify it unless we already have used
5185      undobuf.other_insn.  */
5186   if ((GET_MODE_CLASS (mode) == MODE_CC
5187        || GET_CODE (src) == COMPARE
5188        || CC0_P (dest))
5189       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5190       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5191       && COMPARISON_P (*cc_use)
5192       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5193     {
5194       enum rtx_code old_code = GET_CODE (*cc_use);
5195       enum rtx_code new_code;
5196       rtx op0, op1, tmp;
5197       int other_changed = 0;
5198       enum machine_mode compare_mode = GET_MODE (dest);
5199
5200       if (GET_CODE (src) == COMPARE)
5201         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5202       else
5203         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5204
5205       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5206                                            op0, op1);
5207       if (!tmp)
5208         new_code = old_code;
5209       else if (!CONSTANT_P (tmp))
5210         {
5211           new_code = GET_CODE (tmp);
5212           op0 = XEXP (tmp, 0);
5213           op1 = XEXP (tmp, 1);
5214         }
5215       else
5216         {
5217           rtx pat = PATTERN (other_insn);
5218           undobuf.other_insn = other_insn;
5219           SUBST (*cc_use, tmp);
5220
5221           /* Attempt to simplify CC user.  */
5222           if (GET_CODE (pat) == SET)
5223             {
5224               rtx new = simplify_rtx (SET_SRC (pat));
5225               if (new != NULL_RTX)
5226                 SUBST (SET_SRC (pat), new);
5227             }
5228
5229           /* Convert X into a no-op move.  */
5230           SUBST (SET_DEST (x), pc_rtx);
5231           SUBST (SET_SRC (x), pc_rtx);
5232           return x;
5233         }
5234
5235       /* Simplify our comparison, if possible.  */
5236       new_code = simplify_comparison (new_code, &op0, &op1);
5237
5238 #ifdef SELECT_CC_MODE
5239       /* If this machine has CC modes other than CCmode, check to see if we
5240          need to use a different CC mode here.  */
5241       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5242         compare_mode = GET_MODE (op0);
5243       else
5244         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5245
5246 #ifndef HAVE_cc0
5247       /* If the mode changed, we have to change SET_DEST, the mode in the
5248          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5249          a hard register, just build new versions with the proper mode.  If it
5250          is a pseudo, we lose unless it is only time we set the pseudo, in
5251          which case we can safely change its mode.  */
5252       if (compare_mode != GET_MODE (dest))
5253         {
5254           if (can_change_dest_mode (dest, 0, compare_mode))
5255             {
5256               unsigned int regno = REGNO (dest);
5257               rtx new_dest;
5258
5259               if (regno < FIRST_PSEUDO_REGISTER)
5260                 new_dest = gen_rtx_REG (compare_mode, regno);
5261               else
5262                 {
5263                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5264                   new_dest = regno_reg_rtx[regno];
5265                 }
5266
5267               SUBST (SET_DEST (x), new_dest);
5268               SUBST (XEXP (*cc_use, 0), new_dest);
5269               other_changed = 1;
5270
5271               dest = new_dest;
5272             }
5273         }
5274 #endif  /* cc0 */
5275 #endif  /* SELECT_CC_MODE */
5276
5277       /* If the code changed, we have to build a new comparison in
5278          undobuf.other_insn.  */
5279       if (new_code != old_code)
5280         {
5281           int other_changed_previously = other_changed;
5282           unsigned HOST_WIDE_INT mask;
5283
5284           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5285                                           dest, const0_rtx));
5286           other_changed = 1;
5287
5288           /* If the only change we made was to change an EQ into an NE or
5289              vice versa, OP0 has only one bit that might be nonzero, and OP1
5290              is zero, check if changing the user of the condition code will
5291              produce a valid insn.  If it won't, we can keep the original code
5292              in that insn by surrounding our operation with an XOR.  */
5293
5294           if (((old_code == NE && new_code == EQ)
5295                || (old_code == EQ && new_code == NE))
5296               && ! other_changed_previously && op1 == const0_rtx
5297               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5298               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5299             {
5300               rtx pat = PATTERN (other_insn), note = 0;
5301
5302               if ((recog_for_combine (&pat, other_insn, &note) < 0
5303                    && ! check_asm_operands (pat)))
5304                 {
5305                   PUT_CODE (*cc_use, old_code);
5306                   other_changed = 0;
5307
5308                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5309                                              op0, GEN_INT (mask));
5310                 }
5311             }
5312         }
5313
5314       if (other_changed)
5315         undobuf.other_insn = other_insn;
5316
5317 #ifdef HAVE_cc0
5318       /* If we are now comparing against zero, change our source if
5319          needed.  If we do not use cc0, we always have a COMPARE.  */
5320       if (op1 == const0_rtx && dest == cc0_rtx)
5321         {
5322           SUBST (SET_SRC (x), op0);
5323           src = op0;
5324         }
5325       else
5326 #endif
5327
5328       /* Otherwise, if we didn't previously have a COMPARE in the
5329          correct mode, we need one.  */
5330       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5331         {
5332           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5333           src = SET_SRC (x);
5334         }
5335       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5336         {
5337           SUBST(SET_SRC (x), op0);
5338           src = SET_SRC (x);
5339         }
5340       else
5341         {
5342           /* Otherwise, update the COMPARE if needed.  */
5343           SUBST (XEXP (src, 0), op0);
5344           SUBST (XEXP (src, 1), op1);
5345         }
5346     }
5347   else
5348     {
5349       /* Get SET_SRC in a form where we have placed back any
5350          compound expressions.  Then do the checks below.  */
5351       src = make_compound_operation (src, SET);
5352       SUBST (SET_SRC (x), src);
5353     }
5354
5355   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5356      and X being a REG or (subreg (reg)), we may be able to convert this to
5357      (set (subreg:m2 x) (op)).
5358
5359      We can always do this if M1 is narrower than M2 because that means that
5360      we only care about the low bits of the result.
5361
5362      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5363      perform a narrower operation than requested since the high-order bits will
5364      be undefined.  On machine where it is defined, this transformation is safe
5365      as long as M1 and M2 have the same number of words.  */
5366
5367   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5368       && !OBJECT_P (SUBREG_REG (src))
5369       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5370            / UNITS_PER_WORD)
5371           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5372                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5373 #ifndef WORD_REGISTER_OPERATIONS
5374       && (GET_MODE_SIZE (GET_MODE (src))
5375         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5376 #endif
5377 #ifdef CANNOT_CHANGE_MODE_CLASS
5378       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5379             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5380                                          GET_MODE (SUBREG_REG (src)),
5381                                          GET_MODE (src)))
5382 #endif
5383       && (REG_P (dest)
5384           || (GET_CODE (dest) == SUBREG
5385               && REG_P (SUBREG_REG (dest)))))
5386     {
5387       SUBST (SET_DEST (x),
5388              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5389                                       dest));
5390       SUBST (SET_SRC (x), SUBREG_REG (src));
5391
5392       src = SET_SRC (x), dest = SET_DEST (x);
5393     }
5394
5395 #ifdef HAVE_cc0
5396   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5397      in SRC.  */
5398   if (dest == cc0_rtx
5399       && GET_CODE (src) == SUBREG
5400       && subreg_lowpart_p (src)
5401       && (GET_MODE_BITSIZE (GET_MODE (src))
5402           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5403     {
5404       rtx inner = SUBREG_REG (src);
5405       enum machine_mode inner_mode = GET_MODE (inner);
5406
5407       /* Here we make sure that we don't have a sign bit on.  */
5408       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5409           && (nonzero_bits (inner, inner_mode)
5410               < ((unsigned HOST_WIDE_INT) 1
5411                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5412         {
5413           SUBST (SET_SRC (x), inner);
5414           src = SET_SRC (x);
5415         }
5416     }
5417 #endif
5418
5419 #ifdef LOAD_EXTEND_OP
5420   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5421      would require a paradoxical subreg.  Replace the subreg with a
5422      zero_extend to avoid the reload that would otherwise be required.  */
5423
5424   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5425       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5426       && SUBREG_BYTE (src) == 0
5427       && (GET_MODE_SIZE (GET_MODE (src))
5428           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5429       && MEM_P (SUBREG_REG (src)))
5430     {
5431       SUBST (SET_SRC (x),
5432              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5433                             GET_MODE (src), SUBREG_REG (src)));
5434
5435       src = SET_SRC (x);
5436     }
5437 #endif
5438
5439   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5440      are comparing an item known to be 0 or -1 against 0, use a logical
5441      operation instead. Check for one of the arms being an IOR of the other
5442      arm with some value.  We compute three terms to be IOR'ed together.  In
5443      practice, at most two will be nonzero.  Then we do the IOR's.  */
5444
5445   if (GET_CODE (dest) != PC
5446       && GET_CODE (src) == IF_THEN_ELSE
5447       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5448       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5449       && XEXP (XEXP (src, 0), 1) == const0_rtx
5450       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5451 #ifdef HAVE_conditional_move
5452       && ! can_conditionally_move_p (GET_MODE (src))
5453 #endif
5454       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5455                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5456           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5457       && ! side_effects_p (src))
5458     {
5459       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5460                       ? XEXP (src, 1) : XEXP (src, 2));
5461       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5462                    ? XEXP (src, 2) : XEXP (src, 1));
5463       rtx term1 = const0_rtx, term2, term3;
5464
5465       if (GET_CODE (true_rtx) == IOR
5466           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5467         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5468       else if (GET_CODE (true_rtx) == IOR
5469                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5470         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5471       else if (GET_CODE (false_rtx) == IOR
5472                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5473         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5474       else if (GET_CODE (false_rtx) == IOR
5475                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5476         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5477
5478       term2 = simplify_gen_binary (AND, GET_MODE (src),
5479                                    XEXP (XEXP (src, 0), 0), true_rtx);
5480       term3 = simplify_gen_binary (AND, GET_MODE (src),
5481                                    simplify_gen_unary (NOT, GET_MODE (src),
5482                                                        XEXP (XEXP (src, 0), 0),
5483                                                        GET_MODE (src)),
5484                                    false_rtx);
5485
5486       SUBST (SET_SRC (x),
5487              simplify_gen_binary (IOR, GET_MODE (src),
5488                                   simplify_gen_binary (IOR, GET_MODE (src),
5489                                                        term1, term2),
5490                                   term3));
5491
5492       src = SET_SRC (x);
5493     }
5494
5495   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5496      whole thing fail.  */
5497   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5498     return src;
5499   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5500     return dest;
5501   else
5502     /* Convert this into a field assignment operation, if possible.  */
5503     return make_field_assignment (x);
5504 }
5505 \f
5506 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5507    result.  */
5508
5509 static rtx
5510 simplify_logical (rtx x)
5511 {
5512   enum machine_mode mode = GET_MODE (x);
5513   rtx op0 = XEXP (x, 0);
5514   rtx op1 = XEXP (x, 1);
5515
5516   switch (GET_CODE (x))
5517     {
5518     case AND:
5519       /* We can call simplify_and_const_int only if we don't lose
5520          any (sign) bits when converting INTVAL (op1) to
5521          "unsigned HOST_WIDE_INT".  */
5522       if (GET_CODE (op1) == CONST_INT
5523           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5524               || INTVAL (op1) > 0))
5525         {
5526           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5527           if (GET_CODE (x) != AND)
5528             return x;
5529
5530           op0 = XEXP (x, 0);
5531           op1 = XEXP (x, 1);
5532         }
5533
5534       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5535          apply the distributive law and then the inverse distributive
5536          law to see if things simplify.  */
5537       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5538         {
5539           rtx result = distribute_and_simplify_rtx (x, 0);
5540           if (result)
5541             return result;
5542         }
5543       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5544         {
5545           rtx result = distribute_and_simplify_rtx (x, 1);
5546           if (result)
5547             return result;
5548         }
5549       break;
5550
5551     case IOR:
5552       /* If we have (ior (and A B) C), apply the distributive law and then
5553          the inverse distributive law to see if things simplify.  */
5554
5555       if (GET_CODE (op0) == AND)
5556         {
5557           rtx result = distribute_and_simplify_rtx (x, 0);
5558           if (result)
5559             return result;
5560         }
5561
5562       if (GET_CODE (op1) == AND)
5563         {
5564           rtx result = distribute_and_simplify_rtx (x, 1);
5565           if (result)
5566             return result;
5567         }
5568       break;
5569
5570     default:
5571       gcc_unreachable ();
5572     }
5573
5574   return x;
5575 }
5576 \f
5577 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5578    operations" because they can be replaced with two more basic operations.
5579    ZERO_EXTEND is also considered "compound" because it can be replaced with
5580    an AND operation, which is simpler, though only one operation.
5581
5582    The function expand_compound_operation is called with an rtx expression
5583    and will convert it to the appropriate shifts and AND operations,
5584    simplifying at each stage.
5585
5586    The function make_compound_operation is called to convert an expression
5587    consisting of shifts and ANDs into the equivalent compound expression.
5588    It is the inverse of this function, loosely speaking.  */
5589
5590 static rtx
5591 expand_compound_operation (rtx x)
5592 {
5593   unsigned HOST_WIDE_INT pos = 0, len;
5594   int unsignedp = 0;
5595   unsigned int modewidth;
5596   rtx tem;
5597
5598   switch (GET_CODE (x))
5599     {
5600     case ZERO_EXTEND:
5601       unsignedp = 1;
5602     case SIGN_EXTEND:
5603       /* We can't necessarily use a const_int for a multiword mode;
5604          it depends on implicitly extending the value.
5605          Since we don't know the right way to extend it,
5606          we can't tell whether the implicit way is right.
5607
5608          Even for a mode that is no wider than a const_int,
5609          we can't win, because we need to sign extend one of its bits through
5610          the rest of it, and we don't know which bit.  */
5611       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5612         return x;
5613
5614       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5615          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5616          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5617          reloaded. If not for that, MEM's would very rarely be safe.
5618
5619          Reject MODEs bigger than a word, because we might not be able
5620          to reference a two-register group starting with an arbitrary register
5621          (and currently gen_lowpart might crash for a SUBREG).  */
5622
5623       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5624         return x;
5625
5626       /* Reject MODEs that aren't scalar integers because turning vector
5627          or complex modes into shifts causes problems.  */
5628
5629       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5630         return x;
5631
5632       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5633       /* If the inner object has VOIDmode (the only way this can happen
5634          is if it is an ASM_OPERANDS), we can't do anything since we don't
5635          know how much masking to do.  */
5636       if (len == 0)
5637         return x;
5638
5639       break;
5640
5641     case ZERO_EXTRACT:
5642       unsignedp = 1;
5643
5644       /* ... fall through ...  */
5645
5646     case SIGN_EXTRACT:
5647       /* If the operand is a CLOBBER, just return it.  */
5648       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5649         return XEXP (x, 0);
5650
5651       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5652           || GET_CODE (XEXP (x, 2)) != CONST_INT
5653           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5654         return x;
5655
5656       /* Reject MODEs that aren't scalar integers because turning vector
5657          or complex modes into shifts causes problems.  */
5658
5659       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5660         return x;
5661
5662       len = INTVAL (XEXP (x, 1));
5663       pos = INTVAL (XEXP (x, 2));
5664
5665       /* This should stay within the object being extracted, fail otherwise.  */
5666       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5667         return x;
5668
5669       if (BITS_BIG_ENDIAN)
5670         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5671
5672       break;
5673
5674     default:
5675       return x;
5676     }
5677   /* Convert sign extension to zero extension, if we know that the high
5678      bit is not set, as this is easier to optimize.  It will be converted
5679      back to cheaper alternative in make_extraction.  */
5680   if (GET_CODE (x) == SIGN_EXTEND
5681       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5682           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5683                 & ~(((unsigned HOST_WIDE_INT)
5684                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5685                      >> 1))
5686                == 0)))
5687     {
5688       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5689       rtx temp2 = expand_compound_operation (temp);
5690
5691       /* Make sure this is a profitable operation.  */
5692       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5693        return temp2;
5694       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5695        return temp;
5696       else
5697        return x;
5698     }
5699
5700   /* We can optimize some special cases of ZERO_EXTEND.  */
5701   if (GET_CODE (x) == ZERO_EXTEND)
5702     {
5703       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5704          know that the last value didn't have any inappropriate bits
5705          set.  */
5706       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5707           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5708           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5709           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5710               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5711         return XEXP (XEXP (x, 0), 0);
5712
5713       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5714       if (GET_CODE (XEXP (x, 0)) == SUBREG
5715           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5716           && subreg_lowpart_p (XEXP (x, 0))
5717           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5718           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5719               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5720         return SUBREG_REG (XEXP (x, 0));
5721
5722       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5723          is a comparison and STORE_FLAG_VALUE permits.  This is like
5724          the first case, but it works even when GET_MODE (x) is larger
5725          than HOST_WIDE_INT.  */
5726       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5727           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5728           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5729           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5730               <= HOST_BITS_PER_WIDE_INT)
5731           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5732               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5733         return XEXP (XEXP (x, 0), 0);
5734
5735       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5736       if (GET_CODE (XEXP (x, 0)) == SUBREG
5737           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5738           && subreg_lowpart_p (XEXP (x, 0))
5739           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5740           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5741               <= HOST_BITS_PER_WIDE_INT)
5742           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5743               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5744         return SUBREG_REG (XEXP (x, 0));
5745
5746     }
5747
5748   /* If we reach here, we want to return a pair of shifts.  The inner
5749      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5750      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5751      logical depending on the value of UNSIGNEDP.
5752
5753      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5754      converted into an AND of a shift.
5755
5756      We must check for the case where the left shift would have a negative
5757      count.  This can happen in a case like (x >> 31) & 255 on machines
5758      that can't shift by a constant.  On those machines, we would first
5759      combine the shift with the AND to produce a variable-position
5760      extraction.  Then the constant of 31 would be substituted in to produce
5761      a such a position.  */
5762
5763   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5764   if (modewidth + len >= pos)
5765     {
5766       enum machine_mode mode = GET_MODE (x);
5767       tem = gen_lowpart (mode, XEXP (x, 0));
5768       if (!tem || GET_CODE (tem) == CLOBBER)
5769         return x;
5770       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5771                                   tem, modewidth - pos - len);
5772       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5773                                   mode, tem, modewidth - len);
5774     }
5775   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5776     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5777                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5778                                                         GET_MODE (x),
5779                                                         XEXP (x, 0), pos),
5780                                   ((HOST_WIDE_INT) 1 << len) - 1);
5781   else
5782     /* Any other cases we can't handle.  */
5783     return x;
5784
5785   /* If we couldn't do this for some reason, return the original
5786      expression.  */
5787   if (GET_CODE (tem) == CLOBBER)
5788     return x;
5789
5790   return tem;
5791 }
5792 \f
5793 /* X is a SET which contains an assignment of one object into
5794    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5795    or certain SUBREGS). If possible, convert it into a series of
5796    logical operations.
5797
5798    We half-heartedly support variable positions, but do not at all
5799    support variable lengths.  */
5800
5801 static rtx
5802 expand_field_assignment (rtx x)
5803 {
5804   rtx inner;
5805   rtx pos;                      /* Always counts from low bit.  */
5806   int len;
5807   rtx mask, cleared, masked;
5808   enum machine_mode compute_mode;
5809
5810   /* Loop until we find something we can't simplify.  */
5811   while (1)
5812     {
5813       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5814           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5815         {
5816           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5817           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5818           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5819         }
5820       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5821                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5822         {
5823           inner = XEXP (SET_DEST (x), 0);
5824           len = INTVAL (XEXP (SET_DEST (x), 1));
5825           pos = XEXP (SET_DEST (x), 2);
5826
5827           /* A constant position should stay within the width of INNER.  */
5828           if (GET_CODE (pos) == CONST_INT
5829               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5830             break;
5831
5832           if (BITS_BIG_ENDIAN)
5833             {
5834               if (GET_CODE (pos) == CONST_INT)
5835                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5836                                - INTVAL (pos));
5837               else if (GET_CODE (pos) == MINUS
5838                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5839                        && (INTVAL (XEXP (pos, 1))
5840                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5841                 /* If position is ADJUST - X, new position is X.  */
5842                 pos = XEXP (pos, 0);
5843               else
5844                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5845                                            GEN_INT (GET_MODE_BITSIZE (
5846                                                     GET_MODE (inner))
5847                                                     - len),
5848                                            pos);
5849             }
5850         }
5851
5852       /* A SUBREG between two modes that occupy the same numbers of words
5853          can be done by moving the SUBREG to the source.  */
5854       else if (GET_CODE (SET_DEST (x)) == SUBREG
5855                /* We need SUBREGs to compute nonzero_bits properly.  */
5856                && nonzero_sign_valid
5857                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5858                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5859                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5860                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5861         {
5862           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5863                            gen_lowpart
5864                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5865                             SET_SRC (x)));
5866           continue;
5867         }
5868       else
5869         break;
5870
5871       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5872         inner = SUBREG_REG (inner);
5873
5874       compute_mode = GET_MODE (inner);
5875
5876       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5877       if (! SCALAR_INT_MODE_P (compute_mode))
5878         {
5879           enum machine_mode imode;
5880
5881           /* Don't do anything for vector or complex integral types.  */
5882           if (! FLOAT_MODE_P (compute_mode))
5883             break;
5884
5885           /* Try to find an integral mode to pun with.  */
5886           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5887           if (imode == BLKmode)
5888             break;
5889
5890           compute_mode = imode;
5891           inner = gen_lowpart (imode, inner);
5892         }
5893
5894       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5895       if (len >= HOST_BITS_PER_WIDE_INT)
5896         break;
5897
5898       /* Now compute the equivalent expression.  Make a copy of INNER
5899          for the SET_DEST in case it is a MEM into which we will substitute;
5900          we don't want shared RTL in that case.  */
5901       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5902       cleared = simplify_gen_binary (AND, compute_mode,
5903                                      simplify_gen_unary (NOT, compute_mode,
5904                                        simplify_gen_binary (ASHIFT,
5905                                                             compute_mode,
5906                                                             mask, pos),
5907                                        compute_mode),
5908                                      inner);
5909       masked = simplify_gen_binary (ASHIFT, compute_mode,
5910                                     simplify_gen_binary (
5911                                       AND, compute_mode,
5912                                       gen_lowpart (compute_mode, SET_SRC (x)),
5913                                       mask),
5914                                     pos);
5915
5916       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5917                        simplify_gen_binary (IOR, compute_mode,
5918                                             cleared, masked));
5919     }
5920
5921   return x;
5922 }
5923 \f
5924 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5925    it is an RTX that represents a variable starting position; otherwise,
5926    POS is the (constant) starting bit position (counted from the LSB).
5927
5928    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5929    signed reference.
5930
5931    IN_DEST is nonzero if this is a reference in the destination of a
5932    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5933    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5934    be used.
5935
5936    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5937    ZERO_EXTRACT should be built even for bits starting at bit 0.
5938
5939    MODE is the desired mode of the result (if IN_DEST == 0).
5940
5941    The result is an RTX for the extraction or NULL_RTX if the target
5942    can't handle it.  */
5943
5944 static rtx
5945 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5946                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5947                  int in_dest, int in_compare)
5948 {
5949   /* This mode describes the size of the storage area
5950      to fetch the overall value from.  Within that, we
5951      ignore the POS lowest bits, etc.  */
5952   enum machine_mode is_mode = GET_MODE (inner);
5953   enum machine_mode inner_mode;
5954   enum machine_mode wanted_inner_mode;
5955   enum machine_mode wanted_inner_reg_mode = word_mode;
5956   enum machine_mode pos_mode = word_mode;
5957   enum machine_mode extraction_mode = word_mode;
5958   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5959   rtx new = 0;
5960   rtx orig_pos_rtx = pos_rtx;
5961   HOST_WIDE_INT orig_pos;
5962
5963   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5964     {
5965       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5966          consider just the QI as the memory to extract from.
5967          The subreg adds or removes high bits; its mode is
5968          irrelevant to the meaning of this extraction,
5969          since POS and LEN count from the lsb.  */
5970       if (MEM_P (SUBREG_REG (inner)))
5971         is_mode = GET_MODE (SUBREG_REG (inner));
5972       inner = SUBREG_REG (inner);
5973     }
5974   else if (GET_CODE (inner) == ASHIFT
5975            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5976            && pos_rtx == 0 && pos == 0
5977            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5978     {
5979       /* We're extracting the least significant bits of an rtx
5980          (ashift X (const_int C)), where LEN > C.  Extract the
5981          least significant (LEN - C) bits of X, giving an rtx
5982          whose mode is MODE, then shift it left C times.  */
5983       new = make_extraction (mode, XEXP (inner, 0),
5984                              0, 0, len - INTVAL (XEXP (inner, 1)),
5985                              unsignedp, in_dest, in_compare);
5986       if (new != 0)
5987         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5988     }
5989
5990   inner_mode = GET_MODE (inner);
5991
5992   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5993     pos = INTVAL (pos_rtx), pos_rtx = 0;
5994
5995   /* See if this can be done without an extraction.  We never can if the
5996      width of the field is not the same as that of some integer mode. For
5997      registers, we can only avoid the extraction if the position is at the
5998      low-order bit and this is either not in the destination or we have the
5999      appropriate STRICT_LOW_PART operation available.
6000
6001      For MEM, we can avoid an extract if the field starts on an appropriate
6002      boundary and we can change the mode of the memory reference.  */
6003
6004   if (tmode != BLKmode
6005       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6006            && !MEM_P (inner)
6007            && (inner_mode == tmode
6008                || !REG_P (inner)
6009                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6010                                          GET_MODE_BITSIZE (inner_mode))
6011                || reg_truncated_to_mode (tmode, inner))
6012            && (! in_dest
6013                || (REG_P (inner)
6014                    && have_insn_for (STRICT_LOW_PART, tmode))))
6015           || (MEM_P (inner) && pos_rtx == 0
6016               && (pos
6017                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6018                      : BITS_PER_UNIT)) == 0
6019               /* We can't do this if we are widening INNER_MODE (it
6020                  may not be aligned, for one thing).  */
6021               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6022               && (inner_mode == tmode
6023                   || (! mode_dependent_address_p (XEXP (inner, 0))
6024                       && ! MEM_VOLATILE_P (inner))))))
6025     {
6026       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6027          field.  If the original and current mode are the same, we need not
6028          adjust the offset.  Otherwise, we do if bytes big endian.
6029
6030          If INNER is not a MEM, get a piece consisting of just the field
6031          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6032
6033       if (MEM_P (inner))
6034         {
6035           HOST_WIDE_INT offset;
6036
6037           /* POS counts from lsb, but make OFFSET count in memory order.  */
6038           if (BYTES_BIG_ENDIAN)
6039             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6040           else
6041             offset = pos / BITS_PER_UNIT;
6042
6043           new = adjust_address_nv (inner, tmode, offset);
6044         }
6045       else if (REG_P (inner))
6046         {
6047           if (tmode != inner_mode)
6048             {
6049               /* We can't call gen_lowpart in a DEST since we
6050                  always want a SUBREG (see below) and it would sometimes
6051                  return a new hard register.  */
6052               if (pos || in_dest)
6053                 {
6054                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6055
6056                   if (WORDS_BIG_ENDIAN
6057                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6058                     final_word = ((GET_MODE_SIZE (inner_mode)
6059                                    - GET_MODE_SIZE (tmode))
6060                                   / UNITS_PER_WORD) - final_word;
6061
6062                   final_word *= UNITS_PER_WORD;
6063                   if (BYTES_BIG_ENDIAN &&
6064                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6065                     final_word += (GET_MODE_SIZE (inner_mode)
6066                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6067
6068                   /* Avoid creating invalid subregs, for example when
6069                      simplifying (x>>32)&255.  */
6070                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6071                     return NULL_RTX;
6072
6073                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6074                 }
6075               else
6076                 new = gen_lowpart (tmode, inner);
6077             }
6078           else
6079             new = inner;
6080         }
6081       else
6082         new = force_to_mode (inner, tmode,
6083                              len >= HOST_BITS_PER_WIDE_INT
6084                              ? ~(unsigned HOST_WIDE_INT) 0
6085                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6086                              0);
6087
6088       /* If this extraction is going into the destination of a SET,
6089          make a STRICT_LOW_PART unless we made a MEM.  */
6090
6091       if (in_dest)
6092         return (MEM_P (new) ? new
6093                 : (GET_CODE (new) != SUBREG
6094                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6095                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6096
6097       if (mode == tmode)
6098         return new;
6099
6100       if (GET_CODE (new) == CONST_INT)
6101         return gen_int_mode (INTVAL (new), mode);
6102
6103       /* If we know that no extraneous bits are set, and that the high
6104          bit is not set, convert the extraction to the cheaper of
6105          sign and zero extension, that are equivalent in these cases.  */
6106       if (flag_expensive_optimizations
6107           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6108               && ((nonzero_bits (new, tmode)
6109                    & ~(((unsigned HOST_WIDE_INT)
6110                         GET_MODE_MASK (tmode))
6111                        >> 1))
6112                   == 0)))
6113         {
6114           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6115           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6116
6117           /* Prefer ZERO_EXTENSION, since it gives more information to
6118              backends.  */
6119           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6120             return temp;
6121           return temp1;
6122         }
6123
6124       /* Otherwise, sign- or zero-extend unless we already are in the
6125          proper mode.  */
6126
6127       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6128                              mode, new));
6129     }
6130
6131   /* Unless this is a COMPARE or we have a funny memory reference,
6132      don't do anything with zero-extending field extracts starting at
6133      the low-order bit since they are simple AND operations.  */
6134   if (pos_rtx == 0 && pos == 0 && ! in_dest
6135       && ! in_compare && unsignedp)
6136     return 0;
6137
6138   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6139      if the position is not a constant and the length is not 1.  In all
6140      other cases, we would only be going outside our object in cases when
6141      an original shift would have been undefined.  */
6142   if (MEM_P (inner)
6143       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6144           || (pos_rtx != 0 && len != 1)))
6145     return 0;
6146
6147   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6148      and the mode for the result.  */
6149   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6150     {
6151       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6152       pos_mode = mode_for_extraction (EP_insv, 2);
6153       extraction_mode = mode_for_extraction (EP_insv, 3);
6154     }
6155
6156   if (! in_dest && unsignedp
6157       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6158     {
6159       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6160       pos_mode = mode_for_extraction (EP_extzv, 3);
6161       extraction_mode = mode_for_extraction (EP_extzv, 0);
6162     }
6163
6164   if (! in_dest && ! unsignedp
6165       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6166     {
6167       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6168       pos_mode = mode_for_extraction (EP_extv, 3);
6169       extraction_mode = mode_for_extraction (EP_extv, 0);
6170     }
6171
6172   /* Never narrow an object, since that might not be safe.  */
6173
6174   if (mode != VOIDmode
6175       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6176     extraction_mode = mode;
6177
6178   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6179       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6180     pos_mode = GET_MODE (pos_rtx);
6181
6182   /* If this is not from memory, the desired mode is the preferred mode
6183      for an extraction pattern's first input operand, or word_mode if there
6184      is none.  */
6185   if (!MEM_P (inner))
6186     wanted_inner_mode = wanted_inner_reg_mode;
6187   else
6188     {
6189       /* Be careful not to go beyond the extracted object and maintain the
6190          natural alignment of the memory.  */
6191       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6192       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6193              > GET_MODE_BITSIZE (wanted_inner_mode))
6194         {
6195           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6196           gcc_assert (wanted_inner_mode != VOIDmode);
6197         }
6198
6199       /* If we have to change the mode of memory and cannot, the desired mode
6200          is EXTRACTION_MODE.  */
6201       if (inner_mode != wanted_inner_mode
6202           && (mode_dependent_address_p (XEXP (inner, 0))
6203               || MEM_VOLATILE_P (inner)
6204               || pos_rtx))
6205         wanted_inner_mode = extraction_mode;
6206     }
6207
6208   orig_pos = pos;
6209
6210   if (BITS_BIG_ENDIAN)
6211     {
6212       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6213          BITS_BIG_ENDIAN style.  If position is constant, compute new
6214          position.  Otherwise, build subtraction.
6215          Note that POS is relative to the mode of the original argument.
6216          If it's a MEM we need to recompute POS relative to that.
6217          However, if we're extracting from (or inserting into) a register,
6218          we want to recompute POS relative to wanted_inner_mode.  */
6219       int width = (MEM_P (inner)
6220                    ? GET_MODE_BITSIZE (is_mode)
6221                    : GET_MODE_BITSIZE (wanted_inner_mode));
6222
6223       if (pos_rtx == 0)
6224         pos = width - len - pos;
6225       else
6226         pos_rtx
6227           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6228       /* POS may be less than 0 now, but we check for that below.
6229          Note that it can only be less than 0 if !MEM_P (inner).  */
6230     }
6231
6232   /* If INNER has a wider mode, and this is a constant extraction, try to
6233      make it smaller and adjust the byte to point to the byte containing
6234      the value.  */
6235   if (wanted_inner_mode != VOIDmode
6236       && inner_mode != wanted_inner_mode
6237       && ! pos_rtx
6238       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6239       && MEM_P (inner)
6240       && ! mode_dependent_address_p (XEXP (inner, 0))
6241       && ! MEM_VOLATILE_P (inner))
6242     {
6243       int offset = 0;
6244
6245       /* The computations below will be correct if the machine is big
6246          endian in both bits and bytes or little endian in bits and bytes.
6247          If it is mixed, we must adjust.  */
6248
6249       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6250          adjust OFFSET to compensate.  */
6251       if (BYTES_BIG_ENDIAN
6252           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6253         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6254
6255       /* We can now move to the desired byte.  */
6256       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6257                 * GET_MODE_SIZE (wanted_inner_mode);
6258       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6259
6260       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6261           && is_mode != wanted_inner_mode)
6262         offset = (GET_MODE_SIZE (is_mode)
6263                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6264
6265       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6266     }
6267
6268   /* If INNER is not memory, we can always get it into the proper mode.  If we
6269      are changing its mode, POS must be a constant and smaller than the size
6270      of the new mode.  */
6271   else if (!MEM_P (inner))
6272     {
6273       if (GET_MODE (inner) != wanted_inner_mode
6274           && (pos_rtx != 0
6275               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6276         return 0;
6277
6278       if (orig_pos < 0)
6279         return 0;
6280
6281       inner = force_to_mode (inner, wanted_inner_mode,
6282                              pos_rtx
6283                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6284                              ? ~(unsigned HOST_WIDE_INT) 0
6285                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6286                                 << orig_pos),
6287                              0);
6288     }
6289
6290   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6291      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6292   if (pos_rtx != 0
6293       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6294     {
6295       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6296
6297       /* If we know that no extraneous bits are set, and that the high
6298          bit is not set, convert extraction to cheaper one - either
6299          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6300          cases.  */
6301       if (flag_expensive_optimizations
6302           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6303               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6304                    & ~(((unsigned HOST_WIDE_INT)
6305                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6306                        >> 1))
6307                   == 0)))
6308         {
6309           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6310
6311           /* Prefer ZERO_EXTENSION, since it gives more information to
6312              backends.  */
6313           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6314             temp = temp1;
6315         }
6316       pos_rtx = temp;
6317     }
6318   else if (pos_rtx != 0
6319            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6320     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6321
6322   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6323      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6324      be a CONST_INT.  */
6325   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6326     pos_rtx = orig_pos_rtx;
6327
6328   else if (pos_rtx == 0)
6329     pos_rtx = GEN_INT (pos);
6330
6331   /* Make the required operation.  See if we can use existing rtx.  */
6332   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6333                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6334   if (! in_dest)
6335     new = gen_lowpart (mode, new);
6336
6337   return new;
6338 }
6339 \f
6340 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6341    with any other operations in X.  Return X without that shift if so.  */
6342
6343 static rtx
6344 extract_left_shift (rtx x, int count)
6345 {
6346   enum rtx_code code = GET_CODE (x);
6347   enum machine_mode mode = GET_MODE (x);
6348   rtx tem;
6349
6350   switch (code)
6351     {
6352     case ASHIFT:
6353       /* This is the shift itself.  If it is wide enough, we will return
6354          either the value being shifted if the shift count is equal to
6355          COUNT or a shift for the difference.  */
6356       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6357           && INTVAL (XEXP (x, 1)) >= count)
6358         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6359                                      INTVAL (XEXP (x, 1)) - count);
6360       break;
6361
6362     case NEG:  case NOT:
6363       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6364         return simplify_gen_unary (code, mode, tem, mode);
6365
6366       break;
6367
6368     case PLUS:  case IOR:  case XOR:  case AND:
6369       /* If we can safely shift this constant and we find the inner shift,
6370          make a new operation.  */
6371       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6372           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6373           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6374         return simplify_gen_binary (code, mode, tem,
6375                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6376
6377       break;
6378
6379     default:
6380       break;
6381     }
6382
6383   return 0;
6384 }
6385 \f
6386 /* Look at the expression rooted at X.  Look for expressions
6387    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6388    Form these expressions.
6389
6390    Return the new rtx, usually just X.
6391
6392    Also, for machines like the VAX that don't have logical shift insns,
6393    try to convert logical to arithmetic shift operations in cases where
6394    they are equivalent.  This undoes the canonicalizations to logical
6395    shifts done elsewhere.
6396
6397    We try, as much as possible, to re-use rtl expressions to save memory.
6398
6399    IN_CODE says what kind of expression we are processing.  Normally, it is
6400    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6401    being kludges), it is MEM.  When processing the arguments of a comparison
6402    or a COMPARE against zero, it is COMPARE.  */
6403
6404 static rtx
6405 make_compound_operation (rtx x, enum rtx_code in_code)
6406 {
6407   enum rtx_code code = GET_CODE (x);
6408   enum machine_mode mode = GET_MODE (x);
6409   int mode_width = GET_MODE_BITSIZE (mode);
6410   rtx rhs, lhs;
6411   enum rtx_code next_code;
6412   int i;
6413   rtx new = 0;
6414   rtx tem;
6415   const char *fmt;
6416
6417   /* Select the code to be used in recursive calls.  Once we are inside an
6418      address, we stay there.  If we have a comparison, set to COMPARE,
6419      but once inside, go back to our default of SET.  */
6420
6421   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6422                : ((code == COMPARE || COMPARISON_P (x))
6423                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6424                : in_code == COMPARE ? SET : in_code);
6425
6426   /* Process depending on the code of this operation.  If NEW is set
6427      nonzero, it will be returned.  */
6428
6429   switch (code)
6430     {
6431     case ASHIFT:
6432       /* Convert shifts by constants into multiplications if inside
6433          an address.  */
6434       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6435           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6436           && INTVAL (XEXP (x, 1)) >= 0)
6437         {
6438           new = make_compound_operation (XEXP (x, 0), next_code);
6439           new = gen_rtx_MULT (mode, new,
6440                               GEN_INT ((HOST_WIDE_INT) 1
6441                                        << INTVAL (XEXP (x, 1))));
6442         }
6443       break;
6444
6445     case AND:
6446       /* If the second operand is not a constant, we can't do anything
6447          with it.  */
6448       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6449         break;
6450
6451       /* If the constant is a power of two minus one and the first operand
6452          is a logical right shift, make an extraction.  */
6453       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6454           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6455         {
6456           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6457           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6458                                  0, in_code == COMPARE);
6459         }
6460
6461       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6462       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6463                && subreg_lowpart_p (XEXP (x, 0))
6464                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6465                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6466         {
6467           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6468                                          next_code);
6469           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6470                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6471                                  0, in_code == COMPARE);
6472         }
6473       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6474       else if ((GET_CODE (XEXP (x, 0)) == XOR
6475                 || GET_CODE (XEXP (x, 0)) == IOR)
6476                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6477                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6478                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6479         {
6480           /* Apply the distributive law, and then try to make extractions.  */
6481           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6482                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6483                                              XEXP (x, 1)),
6484                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6485                                              XEXP (x, 1)));
6486           new = make_compound_operation (new, in_code);
6487         }
6488
6489       /* If we are have (and (rotate X C) M) and C is larger than the number
6490          of bits in M, this is an extraction.  */
6491
6492       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6493                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6494                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6495                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6496         {
6497           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6498           new = make_extraction (mode, new,
6499                                  (GET_MODE_BITSIZE (mode)
6500                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6501                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6502         }
6503
6504       /* On machines without logical shifts, if the operand of the AND is
6505          a logical shift and our mask turns off all the propagated sign
6506          bits, we can replace the logical shift with an arithmetic shift.  */
6507       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6508                && !have_insn_for (LSHIFTRT, mode)
6509                && have_insn_for (ASHIFTRT, mode)
6510                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6511                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6512                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6513                && mode_width <= HOST_BITS_PER_WIDE_INT)
6514         {
6515           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6516
6517           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6518           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6519             SUBST (XEXP (x, 0),
6520                    gen_rtx_ASHIFTRT (mode,
6521                                      make_compound_operation
6522                                      (XEXP (XEXP (x, 0), 0), next_code),
6523                                      XEXP (XEXP (x, 0), 1)));
6524         }
6525
6526       /* If the constant is one less than a power of two, this might be
6527          representable by an extraction even if no shift is present.
6528          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6529          we are in a COMPARE.  */
6530       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6531         new = make_extraction (mode,
6532                                make_compound_operation (XEXP (x, 0),
6533                                                         next_code),
6534                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6535
6536       /* If we are in a comparison and this is an AND with a power of two,
6537          convert this into the appropriate bit extract.  */
6538       else if (in_code == COMPARE
6539                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6540         new = make_extraction (mode,
6541                                make_compound_operation (XEXP (x, 0),
6542                                                         next_code),
6543                                i, NULL_RTX, 1, 1, 0, 1);
6544
6545       break;
6546
6547     case LSHIFTRT:
6548       /* If the sign bit is known to be zero, replace this with an
6549          arithmetic shift.  */
6550       if (have_insn_for (ASHIFTRT, mode)
6551           && ! have_insn_for (LSHIFTRT, mode)
6552           && mode_width <= HOST_BITS_PER_WIDE_INT
6553           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6554         {
6555           new = gen_rtx_ASHIFTRT (mode,
6556                                   make_compound_operation (XEXP (x, 0),
6557                                                            next_code),
6558                                   XEXP (x, 1));
6559           break;
6560         }
6561
6562       /* ... fall through ...  */
6563
6564     case ASHIFTRT:
6565       lhs = XEXP (x, 0);
6566       rhs = XEXP (x, 1);
6567
6568       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6569          this is a SIGN_EXTRACT.  */
6570       if (GET_CODE (rhs) == CONST_INT
6571           && GET_CODE (lhs) == ASHIFT
6572           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6573           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6574         {
6575           new = make_compound_operation (XEXP (lhs, 0), next_code);
6576           new = make_extraction (mode, new,
6577                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6578                                  NULL_RTX, mode_width - INTVAL (rhs),
6579                                  code == LSHIFTRT, 0, in_code == COMPARE);
6580           break;
6581         }
6582
6583       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6584          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6585          also do this for some cases of SIGN_EXTRACT, but it doesn't
6586          seem worth the effort; the case checked for occurs on Alpha.  */
6587
6588       if (!OBJECT_P (lhs)
6589           && ! (GET_CODE (lhs) == SUBREG
6590                 && (OBJECT_P (SUBREG_REG (lhs))))
6591           && GET_CODE (rhs) == CONST_INT
6592           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6593           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6594         new = make_extraction (mode, make_compound_operation (new, next_code),
6595                                0, NULL_RTX, mode_width - INTVAL (rhs),
6596                                code == LSHIFTRT, 0, in_code == COMPARE);
6597
6598       break;
6599
6600     case SUBREG:
6601       /* Call ourselves recursively on the inner expression.  If we are
6602          narrowing the object and it has a different RTL code from
6603          what it originally did, do this SUBREG as a force_to_mode.  */
6604
6605       tem = make_compound_operation (SUBREG_REG (x), in_code);
6606
6607       {
6608         rtx simplified;
6609         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6610                                       SUBREG_BYTE (x));
6611
6612         if (simplified)
6613           tem = simplified;
6614
6615         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6616             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6617             && subreg_lowpart_p (x))
6618           {
6619             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6620                                        0);
6621
6622             /* If we have something other than a SUBREG, we might have
6623                done an expansion, so rerun ourselves.  */
6624             if (GET_CODE (newer) != SUBREG)
6625               newer = make_compound_operation (newer, in_code);
6626
6627             return newer;
6628           }
6629
6630         if (simplified)
6631           return tem;
6632       }
6633       break;
6634
6635     default:
6636       break;
6637     }
6638
6639   if (new)
6640     {
6641       x = gen_lowpart (mode, new);
6642       code = GET_CODE (x);
6643     }
6644
6645   /* Now recursively process each operand of this operation.  */
6646   fmt = GET_RTX_FORMAT (code);
6647   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6648     if (fmt[i] == 'e')
6649       {
6650         new = make_compound_operation (XEXP (x, i), next_code);
6651         SUBST (XEXP (x, i), new);
6652       }
6653
6654   /* If this is a commutative operation, the changes to the operands
6655      may have made it noncanonical.  */
6656   if (COMMUTATIVE_ARITH_P (x)
6657       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6658     {
6659       tem = XEXP (x, 0);
6660       SUBST (XEXP (x, 0), XEXP (x, 1));
6661       SUBST (XEXP (x, 1), tem);
6662     }
6663
6664   return x;
6665 }
6666 \f
6667 /* Given M see if it is a value that would select a field of bits
6668    within an item, but not the entire word.  Return -1 if not.
6669    Otherwise, return the starting position of the field, where 0 is the
6670    low-order bit.
6671
6672    *PLEN is set to the length of the field.  */
6673
6674 static int
6675 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6676 {
6677   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6678   int pos = exact_log2 (m & -m);
6679   int len = 0;
6680
6681   if (pos >= 0)
6682     /* Now shift off the low-order zero bits and see if we have a
6683        power of two minus 1.  */
6684     len = exact_log2 ((m >> pos) + 1);
6685
6686   if (len <= 0)
6687     pos = -1;
6688
6689   *plen = len;
6690   return pos;
6691 }
6692 \f
6693 /* If X refers to a register that equals REG in value, replace these
6694    references with REG.  */
6695 static rtx
6696 canon_reg_for_combine (rtx x, rtx reg)
6697 {
6698   rtx op0, op1, op2;
6699   const char *fmt;
6700   int i;
6701   bool copied;
6702
6703   enum rtx_code code = GET_CODE (x);
6704   switch (GET_RTX_CLASS (code))
6705     {
6706     case RTX_UNARY:
6707       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6708       if (op0 != XEXP (x, 0))
6709         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6710                                    GET_MODE (reg));
6711       break;
6712
6713     case RTX_BIN_ARITH:
6714     case RTX_COMM_ARITH:
6715       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6716       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6717       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6718         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6719       break;
6720
6721     case RTX_COMPARE:
6722     case RTX_COMM_COMPARE:
6723       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6724       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6725       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6726         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6727                                         GET_MODE (op0), op0, op1);
6728       break;
6729
6730     case RTX_TERNARY:
6731     case RTX_BITFIELD_OPS:
6732       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6733       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6734       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6735       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6736         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6737                                      GET_MODE (op0), op0, op1, op2);
6738
6739     case RTX_OBJ:
6740       if (REG_P (x))
6741         {
6742           if (rtx_equal_p (get_last_value (reg), x)
6743               || rtx_equal_p (reg, get_last_value (x)))
6744             return reg;
6745           else
6746             break;
6747         }
6748
6749       /* fall through */
6750
6751     default:
6752       fmt = GET_RTX_FORMAT (code);
6753       copied = false;
6754       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6755         if (fmt[i] == 'e')
6756           {
6757             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6758             if (op != XEXP (x, i))
6759               {
6760                 if (!copied)
6761                   {
6762                     copied = true;
6763                     x = copy_rtx (x);
6764                   }
6765                 XEXP (x, i) = op;
6766               }
6767           }
6768         else if (fmt[i] == 'E')
6769           {
6770             int j;
6771             for (j = 0; j < XVECLEN (x, i); j++)
6772               {
6773                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6774                 if (op != XVECEXP (x, i, j))
6775                   {
6776                     if (!copied)
6777                       {
6778                         copied = true;
6779                         x = copy_rtx (x);
6780                       }
6781                     XVECEXP (x, i, j) = op;
6782                   }
6783               }
6784           }
6785
6786       break;
6787     }
6788
6789   return x;
6790 }
6791
6792 /* Return X converted to MODE.  If the value is already truncated to
6793    MODE we can just return a subreg even though in the general case we
6794    would need an explicit truncation.  */
6795
6796 static rtx
6797 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6798 {
6799   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6800       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6801                                 GET_MODE_BITSIZE (GET_MODE (x)))
6802       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6803     return gen_lowpart (mode, x);
6804   else
6805     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6806 }
6807
6808 /* See if X can be simplified knowing that we will only refer to it in
6809    MODE and will only refer to those bits that are nonzero in MASK.
6810    If other bits are being computed or if masking operations are done
6811    that select a superset of the bits in MASK, they can sometimes be
6812    ignored.
6813
6814    Return a possibly simplified expression, but always convert X to
6815    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6816
6817    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6818    are all off in X.  This is used when X will be complemented, by either
6819    NOT, NEG, or XOR.  */
6820
6821 static rtx
6822 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6823                int just_select)
6824 {
6825   enum rtx_code code = GET_CODE (x);
6826   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6827   enum machine_mode op_mode;
6828   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6829   rtx op0, op1, temp;
6830
6831   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6832      code below will do the wrong thing since the mode of such an
6833      expression is VOIDmode.
6834
6835      Also do nothing if X is a CLOBBER; this can happen if X was
6836      the return value from a call to gen_lowpart.  */
6837   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6838     return x;
6839
6840   /* We want to perform the operation is its present mode unless we know
6841      that the operation is valid in MODE, in which case we do the operation
6842      in MODE.  */
6843   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6844               && have_insn_for (code, mode))
6845              ? mode : GET_MODE (x));
6846
6847   /* It is not valid to do a right-shift in a narrower mode
6848      than the one it came in with.  */
6849   if ((code == LSHIFTRT || code == ASHIFTRT)
6850       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6851     op_mode = GET_MODE (x);
6852
6853   /* Truncate MASK to fit OP_MODE.  */
6854   if (op_mode)
6855     mask &= GET_MODE_MASK (op_mode);
6856
6857   /* When we have an arithmetic operation, or a shift whose count we
6858      do not know, we need to assume that all bits up to the highest-order
6859      bit in MASK will be needed.  This is how we form such a mask.  */
6860   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6861     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6862   else
6863     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6864                    - 1);
6865
6866   /* Determine what bits of X are guaranteed to be (non)zero.  */
6867   nonzero = nonzero_bits (x, mode);
6868
6869   /* If none of the bits in X are needed, return a zero.  */
6870   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
6871     x = const0_rtx;
6872
6873   /* If X is a CONST_INT, return a new one.  Do this here since the
6874      test below will fail.  */
6875   if (GET_CODE (x) == CONST_INT)
6876     {
6877       if (SCALAR_INT_MODE_P (mode))
6878         return gen_int_mode (INTVAL (x) & mask, mode);
6879       else
6880         {
6881           x = GEN_INT (INTVAL (x) & mask);
6882           return gen_lowpart_common (mode, x);
6883         }
6884     }
6885
6886   /* If X is narrower than MODE and we want all the bits in X's mode, just
6887      get X in the proper mode.  */
6888   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6889       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6890     return gen_lowpart (mode, x);
6891
6892   switch (code)
6893     {
6894     case CLOBBER:
6895       /* If X is a (clobber (const_int)), return it since we know we are
6896          generating something that won't match.  */
6897       return x;
6898
6899     case SIGN_EXTEND:
6900     case ZERO_EXTEND:
6901     case ZERO_EXTRACT:
6902     case SIGN_EXTRACT:
6903       x = expand_compound_operation (x);
6904       if (GET_CODE (x) != code)
6905         return force_to_mode (x, mode, mask, next_select);
6906       break;
6907
6908     case SUBREG:
6909       if (subreg_lowpart_p (x)
6910           /* We can ignore the effect of this SUBREG if it narrows the mode or
6911              if the constant masks to zero all the bits the mode doesn't
6912              have.  */
6913           && ((GET_MODE_SIZE (GET_MODE (x))
6914                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6915               || (0 == (mask
6916                         & GET_MODE_MASK (GET_MODE (x))
6917                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6918         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6919       break;
6920
6921     case AND:
6922       /* If this is an AND with a constant, convert it into an AND
6923          whose constant is the AND of that constant with MASK.  If it
6924          remains an AND of MASK, delete it since it is redundant.  */
6925
6926       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6927         {
6928           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6929                                       mask & INTVAL (XEXP (x, 1)));
6930
6931           /* If X is still an AND, see if it is an AND with a mask that
6932              is just some low-order bits.  If so, and it is MASK, we don't
6933              need it.  */
6934
6935           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6936               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6937                   == mask))
6938             x = XEXP (x, 0);
6939
6940           /* If it remains an AND, try making another AND with the bits
6941              in the mode mask that aren't in MASK turned on.  If the
6942              constant in the AND is wide enough, this might make a
6943              cheaper constant.  */
6944
6945           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6946               && GET_MODE_MASK (GET_MODE (x)) != mask
6947               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6948             {
6949               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6950                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6951               int width = GET_MODE_BITSIZE (GET_MODE (x));
6952               rtx y;
6953
6954               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6955                  number, sign extend it.  */
6956               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6957                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6958                 cval |= (HOST_WIDE_INT) -1 << width;
6959
6960               y = simplify_gen_binary (AND, GET_MODE (x),
6961                                        XEXP (x, 0), GEN_INT (cval));
6962               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6963                 x = y;
6964             }
6965
6966           break;
6967         }
6968
6969       goto binop;
6970
6971     case PLUS:
6972       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6973          low-order bits (as in an alignment operation) and FOO is already
6974          aligned to that boundary, mask C1 to that boundary as well.
6975          This may eliminate that PLUS and, later, the AND.  */
6976
6977       {
6978         unsigned int width = GET_MODE_BITSIZE (mode);
6979         unsigned HOST_WIDE_INT smask = mask;
6980
6981         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6982            number, sign extend it.  */
6983
6984         if (width < HOST_BITS_PER_WIDE_INT
6985             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6986           smask |= (HOST_WIDE_INT) -1 << width;
6987
6988         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6989             && exact_log2 (- smask) >= 0
6990             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6991             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6992           return force_to_mode (plus_constant (XEXP (x, 0),
6993                                                (INTVAL (XEXP (x, 1)) & smask)),
6994                                 mode, smask, next_select);
6995       }
6996
6997       /* ... fall through ...  */
6998
6999     case MULT:
7000       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7001          most significant bit in MASK since carries from those bits will
7002          affect the bits we are interested in.  */
7003       mask = fuller_mask;
7004       goto binop;
7005
7006     case MINUS:
7007       /* If X is (minus C Y) where C's least set bit is larger than any bit
7008          in the mask, then we may replace with (neg Y).  */
7009       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7010           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7011                                         & -INTVAL (XEXP (x, 0))))
7012               > mask))
7013         {
7014           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7015                                   GET_MODE (x));
7016           return force_to_mode (x, mode, mask, next_select);
7017         }
7018
7019       /* Similarly, if C contains every bit in the fuller_mask, then we may
7020          replace with (not Y).  */
7021       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7022           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7023               == INTVAL (XEXP (x, 0))))
7024         {
7025           x = simplify_gen_unary (NOT, GET_MODE (x),
7026                                   XEXP (x, 1), GET_MODE (x));
7027           return force_to_mode (x, mode, mask, next_select);
7028         }
7029
7030       mask = fuller_mask;
7031       goto binop;
7032
7033     case IOR:
7034     case XOR:
7035       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7036          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7037          operation which may be a bitfield extraction.  Ensure that the
7038          constant we form is not wider than the mode of X.  */
7039
7040       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7041           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7042           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7043           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7044           && GET_CODE (XEXP (x, 1)) == CONST_INT
7045           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7046                + floor_log2 (INTVAL (XEXP (x, 1))))
7047               < GET_MODE_BITSIZE (GET_MODE (x)))
7048           && (INTVAL (XEXP (x, 1))
7049               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7050         {
7051           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7052                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7053           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7054                                       XEXP (XEXP (x, 0), 0), temp);
7055           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7056                                    XEXP (XEXP (x, 0), 1));
7057           return force_to_mode (x, mode, mask, next_select);
7058         }
7059
7060     binop:
7061       /* For most binary operations, just propagate into the operation and
7062          change the mode if we have an operation of that mode.  */
7063
7064       op0 = gen_lowpart_or_truncate (op_mode,
7065                                      force_to_mode (XEXP (x, 0), mode, mask,
7066                                                     next_select));
7067       op1 = gen_lowpart_or_truncate (op_mode,
7068                                      force_to_mode (XEXP (x, 1), mode, mask,
7069                                         next_select));
7070
7071       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7072         x = simplify_gen_binary (code, op_mode, op0, op1);
7073       break;
7074
7075     case ASHIFT:
7076       /* For left shifts, do the same, but just for the first operand.
7077          However, we cannot do anything with shifts where we cannot
7078          guarantee that the counts are smaller than the size of the mode
7079          because such a count will have a different meaning in a
7080          wider mode.  */
7081
7082       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7083              && INTVAL (XEXP (x, 1)) >= 0
7084              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7085           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7086                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7087                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7088         break;
7089
7090       /* If the shift count is a constant and we can do arithmetic in
7091          the mode of the shift, refine which bits we need.  Otherwise, use the
7092          conservative form of the mask.  */
7093       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7094           && INTVAL (XEXP (x, 1)) >= 0
7095           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7096           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7097         mask >>= INTVAL (XEXP (x, 1));
7098       else
7099         mask = fuller_mask;
7100
7101       op0 = gen_lowpart_or_truncate (op_mode,
7102                                      force_to_mode (XEXP (x, 0), op_mode,
7103                                                     mask, next_select));
7104
7105       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7106         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7107       break;
7108
7109     case LSHIFTRT:
7110       /* Here we can only do something if the shift count is a constant,
7111          this shift constant is valid for the host, and we can do arithmetic
7112          in OP_MODE.  */
7113
7114       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7115           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7116           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7117         {
7118           rtx inner = XEXP (x, 0);
7119           unsigned HOST_WIDE_INT inner_mask;
7120
7121           /* Select the mask of the bits we need for the shift operand.  */
7122           inner_mask = mask << INTVAL (XEXP (x, 1));
7123
7124           /* We can only change the mode of the shift if we can do arithmetic
7125              in the mode of the shift and INNER_MASK is no wider than the
7126              width of X's mode.  */
7127           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7128             op_mode = GET_MODE (x);
7129
7130           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7131
7132           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7133             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7134         }
7135
7136       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7137          shift and AND produces only copies of the sign bit (C2 is one less
7138          than a power of two), we can do this with just a shift.  */
7139
7140       if (GET_CODE (x) == LSHIFTRT
7141           && GET_CODE (XEXP (x, 1)) == CONST_INT
7142           /* The shift puts one of the sign bit copies in the least significant
7143              bit.  */
7144           && ((INTVAL (XEXP (x, 1))
7145                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7146               >= GET_MODE_BITSIZE (GET_MODE (x)))
7147           && exact_log2 (mask + 1) >= 0
7148           /* Number of bits left after the shift must be more than the mask
7149              needs.  */
7150           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7151               <= GET_MODE_BITSIZE (GET_MODE (x)))
7152           /* Must be more sign bit copies than the mask needs.  */
7153           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7154               >= exact_log2 (mask + 1)))
7155         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7156                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7157                                           - exact_log2 (mask + 1)));
7158
7159       goto shiftrt;
7160
7161     case ASHIFTRT:
7162       /* If we are just looking for the sign bit, we don't need this shift at
7163          all, even if it has a variable count.  */
7164       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7165           && (mask == ((unsigned HOST_WIDE_INT) 1
7166                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7167         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7168
7169       /* If this is a shift by a constant, get a mask that contains those bits
7170          that are not copies of the sign bit.  We then have two cases:  If
7171          MASK only includes those bits, this can be a logical shift, which may
7172          allow simplifications.  If MASK is a single-bit field not within
7173          those bits, we are requesting a copy of the sign bit and hence can
7174          shift the sign bit to the appropriate location.  */
7175
7176       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7177           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7178         {
7179           int i;
7180
7181           /* If the considered data is wider than HOST_WIDE_INT, we can't
7182              represent a mask for all its bits in a single scalar.
7183              But we only care about the lower bits, so calculate these.  */
7184
7185           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7186             {
7187               nonzero = ~(HOST_WIDE_INT) 0;
7188
7189               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7190                  is the number of bits a full-width mask would have set.
7191                  We need only shift if these are fewer than nonzero can
7192                  hold.  If not, we must keep all bits set in nonzero.  */
7193
7194               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7195                   < HOST_BITS_PER_WIDE_INT)
7196                 nonzero >>= INTVAL (XEXP (x, 1))
7197                             + HOST_BITS_PER_WIDE_INT
7198                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7199             }
7200           else
7201             {
7202               nonzero = GET_MODE_MASK (GET_MODE (x));
7203               nonzero >>= INTVAL (XEXP (x, 1));
7204             }
7205
7206           if ((mask & ~nonzero) == 0)
7207             {
7208               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7209                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7210               if (GET_CODE (x) != ASHIFTRT)
7211                 return force_to_mode (x, mode, mask, next_select);
7212             }
7213
7214           else if ((i = exact_log2 (mask)) >= 0)
7215             {
7216               x = simplify_shift_const
7217                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7218                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7219
7220               if (GET_CODE (x) != ASHIFTRT)
7221                 return force_to_mode (x, mode, mask, next_select);
7222             }
7223         }
7224
7225       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7226          even if the shift count isn't a constant.  */
7227       if (mask == 1)
7228         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7229                                  XEXP (x, 0), XEXP (x, 1));
7230
7231     shiftrt:
7232
7233       /* If this is a zero- or sign-extension operation that just affects bits
7234          we don't care about, remove it.  Be sure the call above returned
7235          something that is still a shift.  */
7236
7237       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7238           && GET_CODE (XEXP (x, 1)) == CONST_INT
7239           && INTVAL (XEXP (x, 1)) >= 0
7240           && (INTVAL (XEXP (x, 1))
7241               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7242           && GET_CODE (XEXP (x, 0)) == ASHIFT
7243           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7244         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7245                               next_select);
7246
7247       break;
7248
7249     case ROTATE:
7250     case ROTATERT:
7251       /* If the shift count is constant and we can do computations
7252          in the mode of X, compute where the bits we care about are.
7253          Otherwise, we can't do anything.  Don't change the mode of
7254          the shift or propagate MODE into the shift, though.  */
7255       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7256           && INTVAL (XEXP (x, 1)) >= 0)
7257         {
7258           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7259                                             GET_MODE (x), GEN_INT (mask),
7260                                             XEXP (x, 1));
7261           if (temp && GET_CODE (temp) == CONST_INT)
7262             SUBST (XEXP (x, 0),
7263                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7264                                   INTVAL (temp), next_select));
7265         }
7266       break;
7267
7268     case NEG:
7269       /* If we just want the low-order bit, the NEG isn't needed since it
7270          won't change the low-order bit.  */
7271       if (mask == 1)
7272         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7273
7274       /* We need any bits less significant than the most significant bit in
7275          MASK since carries from those bits will affect the bits we are
7276          interested in.  */
7277       mask = fuller_mask;
7278       goto unop;
7279
7280     case NOT:
7281       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7282          same as the XOR case above.  Ensure that the constant we form is not
7283          wider than the mode of X.  */
7284
7285       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7286           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7287           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7288           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7289               < GET_MODE_BITSIZE (GET_MODE (x)))
7290           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7291         {
7292           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7293                                GET_MODE (x));
7294           temp = simplify_gen_binary (XOR, GET_MODE (x),
7295                                       XEXP (XEXP (x, 0), 0), temp);
7296           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7297                                    temp, XEXP (XEXP (x, 0), 1));
7298
7299           return force_to_mode (x, mode, mask, next_select);
7300         }
7301
7302       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7303          use the full mask inside the NOT.  */
7304       mask = fuller_mask;
7305
7306     unop:
7307       op0 = gen_lowpart_or_truncate (op_mode,
7308                                      force_to_mode (XEXP (x, 0), mode, mask,
7309                                                     next_select));
7310       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7311         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7312       break;
7313
7314     case NE:
7315       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7316          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7317          which is equal to STORE_FLAG_VALUE.  */
7318       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7319           && GET_MODE (XEXP (x, 0)) == mode
7320           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7321           && (nonzero_bits (XEXP (x, 0), mode)
7322               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7323         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7324
7325       break;
7326
7327     case IF_THEN_ELSE:
7328       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7329          written in a narrower mode.  We play it safe and do not do so.  */
7330
7331       SUBST (XEXP (x, 1),
7332              gen_lowpart_or_truncate (GET_MODE (x),
7333                                       force_to_mode (XEXP (x, 1), mode,
7334                                                      mask, next_select)));
7335       SUBST (XEXP (x, 2),
7336              gen_lowpart_or_truncate (GET_MODE (x),
7337                                       force_to_mode (XEXP (x, 2), mode,
7338                                                      mask, next_select)));
7339       break;
7340
7341     default:
7342       break;
7343     }
7344
7345   /* Ensure we return a value of the proper mode.  */
7346   return gen_lowpart_or_truncate (mode, x);
7347 }
7348 \f
7349 /* Return nonzero if X is an expression that has one of two values depending on
7350    whether some other value is zero or nonzero.  In that case, we return the
7351    value that is being tested, *PTRUE is set to the value if the rtx being
7352    returned has a nonzero value, and *PFALSE is set to the other alternative.
7353
7354    If we return zero, we set *PTRUE and *PFALSE to X.  */
7355
7356 static rtx
7357 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7358 {
7359   enum machine_mode mode = GET_MODE (x);
7360   enum rtx_code code = GET_CODE (x);
7361   rtx cond0, cond1, true0, true1, false0, false1;
7362   unsigned HOST_WIDE_INT nz;
7363
7364   /* If we are comparing a value against zero, we are done.  */
7365   if ((code == NE || code == EQ)
7366       && XEXP (x, 1) == const0_rtx)
7367     {
7368       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7369       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7370       return XEXP (x, 0);
7371     }
7372
7373   /* If this is a unary operation whose operand has one of two values, apply
7374      our opcode to compute those values.  */
7375   else if (UNARY_P (x)
7376            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7377     {
7378       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7379       *pfalse = simplify_gen_unary (code, mode, false0,
7380                                     GET_MODE (XEXP (x, 0)));
7381       return cond0;
7382     }
7383
7384   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7385      make can't possibly match and would suppress other optimizations.  */
7386   else if (code == COMPARE)
7387     ;
7388
7389   /* If this is a binary operation, see if either side has only one of two
7390      values.  If either one does or if both do and they are conditional on
7391      the same value, compute the new true and false values.  */
7392   else if (BINARY_P (x))
7393     {
7394       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7395       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7396
7397       if ((cond0 != 0 || cond1 != 0)
7398           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7399         {
7400           /* If if_then_else_cond returned zero, then true/false are the
7401              same rtl.  We must copy one of them to prevent invalid rtl
7402              sharing.  */
7403           if (cond0 == 0)
7404             true0 = copy_rtx (true0);
7405           else if (cond1 == 0)
7406             true1 = copy_rtx (true1);
7407
7408           if (COMPARISON_P (x))
7409             {
7410               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7411                                                 true0, true1);
7412               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7413                                                  false0, false1);
7414              }
7415           else
7416             {
7417               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7418               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7419             }
7420
7421           return cond0 ? cond0 : cond1;
7422         }
7423
7424       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7425          operands is zero when the other is nonzero, and vice-versa,
7426          and STORE_FLAG_VALUE is 1 or -1.  */
7427
7428       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7429           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7430               || code == UMAX)
7431           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7432         {
7433           rtx op0 = XEXP (XEXP (x, 0), 1);
7434           rtx op1 = XEXP (XEXP (x, 1), 1);
7435
7436           cond0 = XEXP (XEXP (x, 0), 0);
7437           cond1 = XEXP (XEXP (x, 1), 0);
7438
7439           if (COMPARISON_P (cond0)
7440               && COMPARISON_P (cond1)
7441               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7442                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7443                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7444                   || ((swap_condition (GET_CODE (cond0))
7445                        == reversed_comparison_code (cond1, NULL))
7446                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7447                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7448               && ! side_effects_p (x))
7449             {
7450               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7451               *pfalse = simplify_gen_binary (MULT, mode,
7452                                              (code == MINUS
7453                                               ? simplify_gen_unary (NEG, mode,
7454                                                                     op1, mode)
7455                                               : op1),
7456                                               const_true_rtx);
7457               return cond0;
7458             }
7459         }
7460
7461       /* Similarly for MULT, AND and UMIN, except that for these the result
7462          is always zero.  */
7463       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7464           && (code == MULT || code == AND || code == UMIN)
7465           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7466         {
7467           cond0 = XEXP (XEXP (x, 0), 0);
7468           cond1 = XEXP (XEXP (x, 1), 0);
7469
7470           if (COMPARISON_P (cond0)
7471               && COMPARISON_P (cond1)
7472               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7473                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7474                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7475                   || ((swap_condition (GET_CODE (cond0))
7476                        == reversed_comparison_code (cond1, NULL))
7477                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7478                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7479               && ! side_effects_p (x))
7480             {
7481               *ptrue = *pfalse = const0_rtx;
7482               return cond0;
7483             }
7484         }
7485     }
7486
7487   else if (code == IF_THEN_ELSE)
7488     {
7489       /* If we have IF_THEN_ELSE already, extract the condition and
7490          canonicalize it if it is NE or EQ.  */
7491       cond0 = XEXP (x, 0);
7492       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7493       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7494         return XEXP (cond0, 0);
7495       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7496         {
7497           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7498           return XEXP (cond0, 0);
7499         }
7500       else
7501         return cond0;
7502     }
7503
7504   /* If X is a SUBREG, we can narrow both the true and false values
7505      if the inner expression, if there is a condition.  */
7506   else if (code == SUBREG
7507            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7508                                                &true0, &false0)))
7509     {
7510       true0 = simplify_gen_subreg (mode, true0,
7511                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7512       false0 = simplify_gen_subreg (mode, false0,
7513                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7514       if (true0 && false0)
7515         {
7516           *ptrue = true0;
7517           *pfalse = false0;
7518           return cond0;
7519         }
7520     }
7521
7522   /* If X is a constant, this isn't special and will cause confusions
7523      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7524   else if (CONSTANT_P (x)
7525            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7526     ;
7527
7528   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7529      will be least confusing to the rest of the compiler.  */
7530   else if (mode == BImode)
7531     {
7532       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7533       return x;
7534     }
7535
7536   /* If X is known to be either 0 or -1, those are the true and
7537      false values when testing X.  */
7538   else if (x == constm1_rtx || x == const0_rtx
7539            || (mode != VOIDmode
7540                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7541     {
7542       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7543       return x;
7544     }
7545
7546   /* Likewise for 0 or a single bit.  */
7547   else if (SCALAR_INT_MODE_P (mode)
7548            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7549            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7550     {
7551       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7552       return x;
7553     }
7554
7555   /* Otherwise fail; show no condition with true and false values the same.  */
7556   *ptrue = *pfalse = x;
7557   return 0;
7558 }
7559 \f
7560 /* Return the value of expression X given the fact that condition COND
7561    is known to be true when applied to REG as its first operand and VAL
7562    as its second.  X is known to not be shared and so can be modified in
7563    place.
7564
7565    We only handle the simplest cases, and specifically those cases that
7566    arise with IF_THEN_ELSE expressions.  */
7567
7568 static rtx
7569 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7570 {
7571   enum rtx_code code = GET_CODE (x);
7572   rtx temp;
7573   const char *fmt;
7574   int i, j;
7575
7576   if (side_effects_p (x))
7577     return x;
7578
7579   /* If either operand of the condition is a floating point value,
7580      then we have to avoid collapsing an EQ comparison.  */
7581   if (cond == EQ
7582       && rtx_equal_p (x, reg)
7583       && ! FLOAT_MODE_P (GET_MODE (x))
7584       && ! FLOAT_MODE_P (GET_MODE (val)))
7585     return val;
7586
7587   if (cond == UNEQ && rtx_equal_p (x, reg))
7588     return val;
7589
7590   /* If X is (abs REG) and we know something about REG's relationship
7591      with zero, we may be able to simplify this.  */
7592
7593   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7594     switch (cond)
7595       {
7596       case GE:  case GT:  case EQ:
7597         return XEXP (x, 0);
7598       case LT:  case LE:
7599         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7600                                    XEXP (x, 0),
7601                                    GET_MODE (XEXP (x, 0)));
7602       default:
7603         break;
7604       }
7605
7606   /* The only other cases we handle are MIN, MAX, and comparisons if the
7607      operands are the same as REG and VAL.  */
7608
7609   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7610     {
7611       if (rtx_equal_p (XEXP (x, 0), val))
7612         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7613
7614       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7615         {
7616           if (COMPARISON_P (x))
7617             {
7618               if (comparison_dominates_p (cond, code))
7619                 return const_true_rtx;
7620
7621               code = reversed_comparison_code (x, NULL);
7622               if (code != UNKNOWN
7623                   && comparison_dominates_p (cond, code))
7624                 return const0_rtx;
7625               else
7626                 return x;
7627             }
7628           else if (code == SMAX || code == SMIN
7629                    || code == UMIN || code == UMAX)
7630             {
7631               int unsignedp = (code == UMIN || code == UMAX);
7632
7633               /* Do not reverse the condition when it is NE or EQ.
7634                  This is because we cannot conclude anything about
7635                  the value of 'SMAX (x, y)' when x is not equal to y,
7636                  but we can when x equals y.  */
7637               if ((code == SMAX || code == UMAX)
7638                   && ! (cond == EQ || cond == NE))
7639                 cond = reverse_condition (cond);
7640
7641               switch (cond)
7642                 {
7643                 case GE:   case GT:
7644                   return unsignedp ? x : XEXP (x, 1);
7645                 case LE:   case LT:
7646                   return unsignedp ? x : XEXP (x, 0);
7647                 case GEU:  case GTU:
7648                   return unsignedp ? XEXP (x, 1) : x;
7649                 case LEU:  case LTU:
7650                   return unsignedp ? XEXP (x, 0) : x;
7651                 default:
7652                   break;
7653                 }
7654             }
7655         }
7656     }
7657   else if (code == SUBREG)
7658     {
7659       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7660       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7661
7662       if (SUBREG_REG (x) != r)
7663         {
7664           /* We must simplify subreg here, before we lose track of the
7665              original inner_mode.  */
7666           new = simplify_subreg (GET_MODE (x), r,
7667                                  inner_mode, SUBREG_BYTE (x));
7668           if (new)
7669             return new;
7670           else
7671             SUBST (SUBREG_REG (x), r);
7672         }
7673
7674       return x;
7675     }
7676   /* We don't have to handle SIGN_EXTEND here, because even in the
7677      case of replacing something with a modeless CONST_INT, a
7678      CONST_INT is already (supposed to be) a valid sign extension for
7679      its narrower mode, which implies it's already properly
7680      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7681      story is different.  */
7682   else if (code == ZERO_EXTEND)
7683     {
7684       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7685       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7686
7687       if (XEXP (x, 0) != r)
7688         {
7689           /* We must simplify the zero_extend here, before we lose
7690              track of the original inner_mode.  */
7691           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7692                                           r, inner_mode);
7693           if (new)
7694             return new;
7695           else
7696             SUBST (XEXP (x, 0), r);
7697         }
7698
7699       return x;
7700     }
7701
7702   fmt = GET_RTX_FORMAT (code);
7703   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7704     {
7705       if (fmt[i] == 'e')
7706         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7707       else if (fmt[i] == 'E')
7708         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7709           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7710                                                 cond, reg, val));
7711     }
7712
7713   return x;
7714 }
7715 \f
7716 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7717    assignment as a field assignment.  */
7718
7719 static int
7720 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7721 {
7722   if (x == y || rtx_equal_p (x, y))
7723     return 1;
7724
7725   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7726     return 0;
7727
7728   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7729      Note that all SUBREGs of MEM are paradoxical; otherwise they
7730      would have been rewritten.  */
7731   if (MEM_P (x) && GET_CODE (y) == SUBREG
7732       && MEM_P (SUBREG_REG (y))
7733       && rtx_equal_p (SUBREG_REG (y),
7734                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7735     return 1;
7736
7737   if (MEM_P (y) && GET_CODE (x) == SUBREG
7738       && MEM_P (SUBREG_REG (x))
7739       && rtx_equal_p (SUBREG_REG (x),
7740                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7741     return 1;
7742
7743   /* We used to see if get_last_value of X and Y were the same but that's
7744      not correct.  In one direction, we'll cause the assignment to have
7745      the wrong destination and in the case, we'll import a register into this
7746      insn that might have already have been dead.   So fail if none of the
7747      above cases are true.  */
7748   return 0;
7749 }
7750 \f
7751 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7752    Return that assignment if so.
7753
7754    We only handle the most common cases.  */
7755
7756 static rtx
7757 make_field_assignment (rtx x)
7758 {
7759   rtx dest = SET_DEST (x);
7760   rtx src = SET_SRC (x);
7761   rtx assign;
7762   rtx rhs, lhs;
7763   HOST_WIDE_INT c1;
7764   HOST_WIDE_INT pos;
7765   unsigned HOST_WIDE_INT len;
7766   rtx other;
7767   enum machine_mode mode;
7768
7769   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7770      a clear of a one-bit field.  We will have changed it to
7771      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7772      for a SUBREG.  */
7773
7774   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7775       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7776       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7777       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7778     {
7779       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7780                                 1, 1, 1, 0);
7781       if (assign != 0)
7782         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7783       return x;
7784     }
7785
7786   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7787       && subreg_lowpart_p (XEXP (src, 0))
7788       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7789           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7790       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7791       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7792       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7793       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7794     {
7795       assign = make_extraction (VOIDmode, dest, 0,
7796                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7797                                 1, 1, 1, 0);
7798       if (assign != 0)
7799         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7800       return x;
7801     }
7802
7803   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7804      one-bit field.  */
7805   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7806       && XEXP (XEXP (src, 0), 0) == const1_rtx
7807       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7808     {
7809       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7810                                 1, 1, 1, 0);
7811       if (assign != 0)
7812         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7813       return x;
7814     }
7815
7816   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7817      SRC is an AND with all bits of that field set, then we can discard
7818      the AND.  */
7819   if (GET_CODE (dest) == ZERO_EXTRACT
7820       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7821       && GET_CODE (src) == AND
7822       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7823     {
7824       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7825       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7826       unsigned HOST_WIDE_INT ze_mask;
7827
7828       if (width >= HOST_BITS_PER_WIDE_INT)
7829         ze_mask = -1;
7830       else
7831         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7832
7833       /* Complete overlap.  We can remove the source AND.  */
7834       if ((and_mask & ze_mask) == ze_mask)
7835         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7836
7837       /* Partial overlap.  We can reduce the source AND.  */
7838       if ((and_mask & ze_mask) != and_mask)
7839         {
7840           mode = GET_MODE (src);
7841           src = gen_rtx_AND (mode, XEXP (src, 0),
7842                              gen_int_mode (and_mask & ze_mask, mode));
7843           return gen_rtx_SET (VOIDmode, dest, src);
7844         }
7845     }
7846
7847   /* The other case we handle is assignments into a constant-position
7848      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7849      a mask that has all one bits except for a group of zero bits and
7850      OTHER is known to have zeros where C1 has ones, this is such an
7851      assignment.  Compute the position and length from C1.  Shift OTHER
7852      to the appropriate position, force it to the required mode, and
7853      make the extraction.  Check for the AND in both operands.  */
7854
7855   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7856     return x;
7857
7858   rhs = expand_compound_operation (XEXP (src, 0));
7859   lhs = expand_compound_operation (XEXP (src, 1));
7860
7861   if (GET_CODE (rhs) == AND
7862       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7863       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7864     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7865   else if (GET_CODE (lhs) == AND
7866            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7867            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7868     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7869   else
7870     return x;
7871
7872   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7873   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7874       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7875       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7876     return x;
7877
7878   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7879   if (assign == 0)
7880     return x;
7881
7882   /* The mode to use for the source is the mode of the assignment, or of
7883      what is inside a possible STRICT_LOW_PART.  */
7884   mode = (GET_CODE (assign) == STRICT_LOW_PART
7885           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7886
7887   /* Shift OTHER right POS places and make it the source, restricting it
7888      to the proper length and mode.  */
7889
7890   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7891                                                      GET_MODE (src),
7892                                                      other, pos),
7893                                dest);
7894   src = force_to_mode (src, mode,
7895                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7896                        ? ~(unsigned HOST_WIDE_INT) 0
7897                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7898                        0);
7899
7900   /* If SRC is masked by an AND that does not make a difference in
7901      the value being stored, strip it.  */
7902   if (GET_CODE (assign) == ZERO_EXTRACT
7903       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7904       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7905       && GET_CODE (src) == AND
7906       && GET_CODE (XEXP (src, 1)) == CONST_INT
7907       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7908           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7909     src = XEXP (src, 0);
7910
7911   return gen_rtx_SET (VOIDmode, assign, src);
7912 }
7913 \f
7914 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7915    if so.  */
7916
7917 static rtx
7918 apply_distributive_law (rtx x)
7919 {
7920   enum rtx_code code = GET_CODE (x);
7921   enum rtx_code inner_code;
7922   rtx lhs, rhs, other;
7923   rtx tem;
7924
7925   /* Distributivity is not true for floating point as it can change the
7926      value.  So we don't do it unless -funsafe-math-optimizations.  */
7927   if (FLOAT_MODE_P (GET_MODE (x))
7928       && ! flag_unsafe_math_optimizations)
7929     return x;
7930
7931   /* The outer operation can only be one of the following:  */
7932   if (code != IOR && code != AND && code != XOR
7933       && code != PLUS && code != MINUS)
7934     return x;
7935
7936   lhs = XEXP (x, 0);
7937   rhs = XEXP (x, 1);
7938
7939   /* If either operand is a primitive we can't do anything, so get out
7940      fast.  */
7941   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7942     return x;
7943
7944   lhs = expand_compound_operation (lhs);
7945   rhs = expand_compound_operation (rhs);
7946   inner_code = GET_CODE (lhs);
7947   if (inner_code != GET_CODE (rhs))
7948     return x;
7949
7950   /* See if the inner and outer operations distribute.  */
7951   switch (inner_code)
7952     {
7953     case LSHIFTRT:
7954     case ASHIFTRT:
7955     case AND:
7956     case IOR:
7957       /* These all distribute except over PLUS.  */
7958       if (code == PLUS || code == MINUS)
7959         return x;
7960       break;
7961
7962     case MULT:
7963       if (code != PLUS && code != MINUS)
7964         return x;
7965       break;
7966
7967     case ASHIFT:
7968       /* This is also a multiply, so it distributes over everything.  */
7969       break;
7970
7971     case SUBREG:
7972       /* Non-paradoxical SUBREGs distributes over all operations,
7973          provided the inner modes and byte offsets are the same, this
7974          is an extraction of a low-order part, we don't convert an fp
7975          operation to int or vice versa, this is not a vector mode,
7976          and we would not be converting a single-word operation into a
7977          multi-word operation.  The latter test is not required, but
7978          it prevents generating unneeded multi-word operations.  Some
7979          of the previous tests are redundant given the latter test,
7980          but are retained because they are required for correctness.
7981
7982          We produce the result slightly differently in this case.  */
7983
7984       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7985           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7986           || ! subreg_lowpart_p (lhs)
7987           || (GET_MODE_CLASS (GET_MODE (lhs))
7988               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7989           || (GET_MODE_SIZE (GET_MODE (lhs))
7990               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7991           || VECTOR_MODE_P (GET_MODE (lhs))
7992           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7993           /* Result might need to be truncated.  Don't change mode if
7994              explicit truncation is needed.  */
7995           || !TRULY_NOOP_TRUNCATION
7996                (GET_MODE_BITSIZE (GET_MODE (x)),
7997                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7998         return x;
7999
8000       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8001                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8002       return gen_lowpart (GET_MODE (x), tem);
8003
8004     default:
8005       return x;
8006     }
8007
8008   /* Set LHS and RHS to the inner operands (A and B in the example
8009      above) and set OTHER to the common operand (C in the example).
8010      There is only one way to do this unless the inner operation is
8011      commutative.  */
8012   if (COMMUTATIVE_ARITH_P (lhs)
8013       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8014     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8015   else if (COMMUTATIVE_ARITH_P (lhs)
8016            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8017     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8018   else if (COMMUTATIVE_ARITH_P (lhs)
8019            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8020     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8021   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8022     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8023   else
8024     return x;
8025
8026   /* Form the new inner operation, seeing if it simplifies first.  */
8027   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8028
8029   /* There is one exception to the general way of distributing:
8030      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8031   if (code == XOR && inner_code == IOR)
8032     {
8033       inner_code = AND;
8034       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8035     }
8036
8037   /* We may be able to continuing distributing the result, so call
8038      ourselves recursively on the inner operation before forming the
8039      outer operation, which we return.  */
8040   return simplify_gen_binary (inner_code, GET_MODE (x),
8041                               apply_distributive_law (tem), other);
8042 }
8043
8044 /* See if X is of the form (* (+ A B) C), and if so convert to
8045    (+ (* A C) (* B C)) and try to simplify.
8046
8047    Most of the time, this results in no change.  However, if some of
8048    the operands are the same or inverses of each other, simplifications
8049    will result.
8050
8051    For example, (and (ior A B) (not B)) can occur as the result of
8052    expanding a bit field assignment.  When we apply the distributive
8053    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8054    which then simplifies to (and (A (not B))).
8055
8056    Note that no checks happen on the validity of applying the inverse
8057    distributive law.  This is pointless since we can do it in the
8058    few places where this routine is called.
8059
8060    N is the index of the term that is decomposed (the arithmetic operation,
8061    i.e. (+ A B) in the first example above).  !N is the index of the term that
8062    is distributed, i.e. of C in the first example above.  */
8063 static rtx
8064 distribute_and_simplify_rtx (rtx x, int n)
8065 {
8066   enum machine_mode mode;
8067   enum rtx_code outer_code, inner_code;
8068   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8069
8070   decomposed = XEXP (x, n);
8071   if (!ARITHMETIC_P (decomposed))
8072     return NULL_RTX;
8073
8074   mode = GET_MODE (x);
8075   outer_code = GET_CODE (x);
8076   distributed = XEXP (x, !n);
8077
8078   inner_code = GET_CODE (decomposed);
8079   inner_op0 = XEXP (decomposed, 0);
8080   inner_op1 = XEXP (decomposed, 1);
8081
8082   /* Special case (and (xor B C) (not A)), which is equivalent to
8083      (xor (ior A B) (ior A C))  */
8084   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8085     {
8086       distributed = XEXP (distributed, 0);
8087       outer_code = IOR;
8088     }
8089
8090   if (n == 0)
8091     {
8092       /* Distribute the second term.  */
8093       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8094       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8095     }
8096   else
8097     {
8098       /* Distribute the first term.  */
8099       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8100       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8101     }
8102
8103   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8104                                                      new_op0, new_op1));
8105   if (GET_CODE (tmp) != outer_code
8106       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8107     return tmp;
8108
8109   return NULL_RTX;
8110 }
8111 \f
8112 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8113    in MODE.  Return an equivalent form, if different from (and VAROP
8114    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8115
8116 static rtx
8117 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8118                           unsigned HOST_WIDE_INT constop)
8119 {
8120   unsigned HOST_WIDE_INT nonzero;
8121   unsigned HOST_WIDE_INT orig_constop;
8122   rtx orig_varop;
8123   int i;
8124
8125   orig_varop = varop;
8126   orig_constop = constop;
8127   if (GET_CODE (varop) == CLOBBER)
8128     return NULL_RTX;
8129
8130   /* Simplify VAROP knowing that we will be only looking at some of the
8131      bits in it.
8132
8133      Note by passing in CONSTOP, we guarantee that the bits not set in
8134      CONSTOP are not significant and will never be examined.  We must
8135      ensure that is the case by explicitly masking out those bits
8136      before returning.  */
8137   varop = force_to_mode (varop, mode, constop, 0);
8138
8139   /* If VAROP is a CLOBBER, we will fail so return it.  */
8140   if (GET_CODE (varop) == CLOBBER)
8141     return varop;
8142
8143   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8144      to VAROP and return the new constant.  */
8145   if (GET_CODE (varop) == CONST_INT)
8146     return gen_int_mode (INTVAL (varop) & constop, mode);
8147
8148   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8149      a call to nonzero_bits, here we don't care about bits outside
8150      MODE.  */
8151
8152   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8153
8154   /* Turn off all bits in the constant that are known to already be zero.
8155      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8156      which is tested below.  */
8157
8158   constop &= nonzero;
8159
8160   /* If we don't have any bits left, return zero.  */
8161   if (constop == 0)
8162     return const0_rtx;
8163
8164   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8165      a power of two, we can replace this with an ASHIFT.  */
8166   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8167       && (i = exact_log2 (constop)) >= 0)
8168     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8169
8170   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8171      or XOR, then try to apply the distributive law.  This may eliminate
8172      operations if either branch can be simplified because of the AND.
8173      It may also make some cases more complex, but those cases probably
8174      won't match a pattern either with or without this.  */
8175
8176   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8177     return
8178       gen_lowpart
8179         (mode,
8180          apply_distributive_law
8181          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8182                                simplify_and_const_int (NULL_RTX,
8183                                                        GET_MODE (varop),
8184                                                        XEXP (varop, 0),
8185                                                        constop),
8186                                simplify_and_const_int (NULL_RTX,
8187                                                        GET_MODE (varop),
8188                                                        XEXP (varop, 1),
8189                                                        constop))));
8190
8191   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8192      the AND and see if one of the operands simplifies to zero.  If so, we
8193      may eliminate it.  */
8194
8195   if (GET_CODE (varop) == PLUS
8196       && exact_log2 (constop + 1) >= 0)
8197     {
8198       rtx o0, o1;
8199
8200       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8201       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8202       if (o0 == const0_rtx)
8203         return o1;
8204       if (o1 == const0_rtx)
8205         return o0;
8206     }
8207
8208   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8209   varop = gen_lowpart (mode, varop);
8210   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8211     return NULL_RTX;
8212
8213   /* If we are only masking insignificant bits, return VAROP.  */
8214   if (constop == nonzero)
8215     return varop;
8216
8217   if (varop == orig_varop && constop == orig_constop)
8218     return NULL_RTX;
8219
8220   /* Otherwise, return an AND.  */
8221   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8222 }
8223
8224
8225 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8226    in MODE.
8227
8228    Return an equivalent form, if different from X.  Otherwise, return X.  If
8229    X is zero, we are to always construct the equivalent form.  */
8230
8231 static rtx
8232 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8233                         unsigned HOST_WIDE_INT constop)
8234 {
8235   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8236   if (tem)
8237     return tem;
8238
8239   if (!x)
8240     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8241                              gen_int_mode (constop, mode));
8242   if (GET_MODE (x) != mode)
8243     x = gen_lowpart (mode, x);
8244   return x;
8245 }
8246 \f
8247 /* Given a REG, X, compute which bits in X can be nonzero.
8248    We don't care about bits outside of those defined in MODE.
8249
8250    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8251    a shift, AND, or zero_extract, we can do better.  */
8252
8253 static rtx
8254 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8255                               rtx known_x ATTRIBUTE_UNUSED,
8256                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8257                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8258                               unsigned HOST_WIDE_INT *nonzero)
8259 {
8260   rtx tem;
8261
8262   /* If X is a register whose nonzero bits value is current, use it.
8263      Otherwise, if X is a register whose value we can find, use that
8264      value.  Otherwise, use the previously-computed global nonzero bits
8265      for this register.  */
8266
8267   if (reg_stat[REGNO (x)].last_set_value != 0
8268       && (reg_stat[REGNO (x)].last_set_mode == mode
8269           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8270               && GET_MODE_CLASS (mode) == MODE_INT))
8271       && (reg_stat[REGNO (x)].last_set_label == label_tick
8272           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8273               && REG_N_SETS (REGNO (x)) == 1
8274               && ! REGNO_REG_SET_P
8275                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8276                   REGNO (x))))
8277       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8278     {
8279       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8280       return NULL;
8281     }
8282
8283   tem = get_last_value (x);
8284
8285   if (tem)
8286     {
8287 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8288       /* If X is narrower than MODE and TEM is a non-negative
8289          constant that would appear negative in the mode of X,
8290          sign-extend it for use in reg_nonzero_bits because some
8291          machines (maybe most) will actually do the sign-extension
8292          and this is the conservative approach.
8293
8294          ??? For 2.5, try to tighten up the MD files in this regard
8295          instead of this kludge.  */
8296
8297       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8298           && GET_CODE (tem) == CONST_INT
8299           && INTVAL (tem) > 0
8300           && 0 != (INTVAL (tem)
8301                    & ((HOST_WIDE_INT) 1
8302                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8303         tem = GEN_INT (INTVAL (tem)
8304                        | ((HOST_WIDE_INT) (-1)
8305                           << GET_MODE_BITSIZE (GET_MODE (x))));
8306 #endif
8307       return tem;
8308     }
8309   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8310     {
8311       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8312
8313       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8314         /* We don't know anything about the upper bits.  */
8315         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8316       *nonzero &= mask;
8317     }
8318
8319   return NULL;
8320 }
8321
8322 /* Return the number of bits at the high-order end of X that are known to
8323    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8324    VOIDmode, X will be used in its own mode.  The returned value  will always
8325    be between 1 and the number of bits in MODE.  */
8326
8327 static rtx
8328 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8329                                      rtx known_x ATTRIBUTE_UNUSED,
8330                                      enum machine_mode known_mode
8331                                      ATTRIBUTE_UNUSED,
8332                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8333                                      unsigned int *result)
8334 {
8335   rtx tem;
8336
8337   if (reg_stat[REGNO (x)].last_set_value != 0
8338       && reg_stat[REGNO (x)].last_set_mode == mode
8339       && (reg_stat[REGNO (x)].last_set_label == label_tick
8340           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8341               && REG_N_SETS (REGNO (x)) == 1
8342               && ! REGNO_REG_SET_P
8343                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8344                   REGNO (x))))
8345       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8346     {
8347       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8348       return NULL;
8349     }
8350
8351   tem = get_last_value (x);
8352   if (tem != 0)
8353     return tem;
8354
8355   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8356       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8357     *result = reg_stat[REGNO (x)].sign_bit_copies;
8358
8359   return NULL;
8360 }
8361 \f
8362 /* Return the number of "extended" bits there are in X, when interpreted
8363    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8364    unsigned quantities, this is the number of high-order zero bits.
8365    For signed quantities, this is the number of copies of the sign bit
8366    minus 1.  In both case, this function returns the number of "spare"
8367    bits.  For example, if two quantities for which this function returns
8368    at least 1 are added, the addition is known not to overflow.
8369
8370    This function will always return 0 unless called during combine, which
8371    implies that it must be called from a define_split.  */
8372
8373 unsigned int
8374 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8375 {
8376   if (nonzero_sign_valid == 0)
8377     return 0;
8378
8379   return (unsignedp
8380           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8381              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8382                                - floor_log2 (nonzero_bits (x, mode)))
8383              : 0)
8384           : num_sign_bit_copies (x, mode) - 1);
8385 }
8386 \f
8387 /* This function is called from `simplify_shift_const' to merge two
8388    outer operations.  Specifically, we have already found that we need
8389    to perform operation *POP0 with constant *PCONST0 at the outermost
8390    position.  We would now like to also perform OP1 with constant CONST1
8391    (with *POP0 being done last).
8392
8393    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8394    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8395    complement the innermost operand, otherwise it is unchanged.
8396
8397    MODE is the mode in which the operation will be done.  No bits outside
8398    the width of this mode matter.  It is assumed that the width of this mode
8399    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8400
8401    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8402    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8403    result is simply *PCONST0.
8404
8405    If the resulting operation cannot be expressed as one operation, we
8406    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8407
8408 static int
8409 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8410 {
8411   enum rtx_code op0 = *pop0;
8412   HOST_WIDE_INT const0 = *pconst0;
8413
8414   const0 &= GET_MODE_MASK (mode);
8415   const1 &= GET_MODE_MASK (mode);
8416
8417   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8418   if (op0 == AND)
8419     const1 &= const0;
8420
8421   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8422      if OP0 is SET.  */
8423
8424   if (op1 == UNKNOWN || op0 == SET)
8425     return 1;
8426
8427   else if (op0 == UNKNOWN)
8428     op0 = op1, const0 = const1;
8429
8430   else if (op0 == op1)
8431     {
8432       switch (op0)
8433         {
8434         case AND:
8435           const0 &= const1;
8436           break;
8437         case IOR:
8438           const0 |= const1;
8439           break;
8440         case XOR:
8441           const0 ^= const1;
8442           break;
8443         case PLUS:
8444           const0 += const1;
8445           break;
8446         case NEG:
8447           op0 = UNKNOWN;
8448           break;
8449         default:
8450           break;
8451         }
8452     }
8453
8454   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8455   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8456     return 0;
8457
8458   /* If the two constants aren't the same, we can't do anything.  The
8459      remaining six cases can all be done.  */
8460   else if (const0 != const1)
8461     return 0;
8462
8463   else
8464     switch (op0)
8465       {
8466       case IOR:
8467         if (op1 == AND)
8468           /* (a & b) | b == b */
8469           op0 = SET;
8470         else /* op1 == XOR */
8471           /* (a ^ b) | b == a | b */
8472           {;}
8473         break;
8474
8475       case XOR:
8476         if (op1 == AND)
8477           /* (a & b) ^ b == (~a) & b */
8478           op0 = AND, *pcomp_p = 1;
8479         else /* op1 == IOR */
8480           /* (a | b) ^ b == a & ~b */
8481           op0 = AND, const0 = ~const0;
8482         break;
8483
8484       case AND:
8485         if (op1 == IOR)
8486           /* (a | b) & b == b */
8487         op0 = SET;
8488         else /* op1 == XOR */
8489           /* (a ^ b) & b) == (~a) & b */
8490           *pcomp_p = 1;
8491         break;
8492       default:
8493         break;
8494       }
8495
8496   /* Check for NO-OP cases.  */
8497   const0 &= GET_MODE_MASK (mode);
8498   if (const0 == 0
8499       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8500     op0 = UNKNOWN;
8501   else if (const0 == 0 && op0 == AND)
8502     op0 = SET;
8503   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8504            && op0 == AND)
8505     op0 = UNKNOWN;
8506
8507   /* ??? Slightly redundant with the above mask, but not entirely.
8508      Moving this above means we'd have to sign-extend the mode mask
8509      for the final test.  */
8510   const0 = trunc_int_for_mode (const0, mode);
8511
8512   *pop0 = op0;
8513   *pconst0 = const0;
8514
8515   return 1;
8516 }
8517 \f
8518 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8519    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8520    simplify it.  Otherwise, return a simplified value.
8521
8522    The shift is normally computed in the widest mode we find in VAROP, as
8523    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8524    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8525
8526 static rtx
8527 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8528                         rtx varop, int orig_count)
8529 {
8530   enum rtx_code orig_code = code;
8531   rtx orig_varop = varop;
8532   int count;
8533   enum machine_mode mode = result_mode;
8534   enum machine_mode shift_mode, tmode;
8535   unsigned int mode_words
8536     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8537   /* We form (outer_op (code varop count) (outer_const)).  */
8538   enum rtx_code outer_op = UNKNOWN;
8539   HOST_WIDE_INT outer_const = 0;
8540   int complement_p = 0;
8541   rtx new, x;
8542
8543   /* Make sure and truncate the "natural" shift on the way in.  We don't
8544      want to do this inside the loop as it makes it more difficult to
8545      combine shifts.  */
8546   if (SHIFT_COUNT_TRUNCATED)
8547     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8548
8549   /* If we were given an invalid count, don't do anything except exactly
8550      what was requested.  */
8551
8552   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8553     return NULL_RTX;
8554
8555   count = orig_count;
8556
8557   /* Unless one of the branches of the `if' in this loop does a `continue',
8558      we will `break' the loop after the `if'.  */
8559
8560   while (count != 0)
8561     {
8562       /* If we have an operand of (clobber (const_int 0)), fail.  */
8563       if (GET_CODE (varop) == CLOBBER)
8564         return NULL_RTX;
8565
8566       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8567          here would cause an infinite loop.  */
8568       if (complement_p)
8569         break;
8570
8571       /* Convert ROTATERT to ROTATE.  */
8572       if (code == ROTATERT)
8573         {
8574           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8575           code = ROTATE;
8576           if (VECTOR_MODE_P (result_mode))
8577             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8578           else
8579             count = bitsize - count;
8580         }
8581
8582       /* We need to determine what mode we will do the shift in.  If the
8583          shift is a right shift or a ROTATE, we must always do it in the mode
8584          it was originally done in.  Otherwise, we can do it in MODE, the
8585          widest mode encountered.  */
8586       shift_mode
8587         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8588            ? result_mode : mode);
8589
8590       /* Handle cases where the count is greater than the size of the mode
8591          minus 1.  For ASHIFT, use the size minus one as the count (this can
8592          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8593          take the count modulo the size.  For other shifts, the result is
8594          zero.
8595
8596          Since these shifts are being produced by the compiler by combining
8597          multiple operations, each of which are defined, we know what the
8598          result is supposed to be.  */
8599
8600       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8601         {
8602           if (code == ASHIFTRT)
8603             count = GET_MODE_BITSIZE (shift_mode) - 1;
8604           else if (code == ROTATE || code == ROTATERT)
8605             count %= GET_MODE_BITSIZE (shift_mode);
8606           else
8607             {
8608               /* We can't simply return zero because there may be an
8609                  outer op.  */
8610               varop = const0_rtx;
8611               count = 0;
8612               break;
8613             }
8614         }
8615
8616       /* An arithmetic right shift of a quantity known to be -1 or 0
8617          is a no-op.  */
8618       if (code == ASHIFTRT
8619           && (num_sign_bit_copies (varop, shift_mode)
8620               == GET_MODE_BITSIZE (shift_mode)))
8621         {
8622           count = 0;
8623           break;
8624         }
8625
8626       /* If we are doing an arithmetic right shift and discarding all but
8627          the sign bit copies, this is equivalent to doing a shift by the
8628          bitsize minus one.  Convert it into that shift because it will often
8629          allow other simplifications.  */
8630
8631       if (code == ASHIFTRT
8632           && (count + num_sign_bit_copies (varop, shift_mode)
8633               >= GET_MODE_BITSIZE (shift_mode)))
8634         count = GET_MODE_BITSIZE (shift_mode) - 1;
8635
8636       /* We simplify the tests below and elsewhere by converting
8637          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8638          `make_compound_operation' will convert it to an ASHIFTRT for
8639          those machines (such as VAX) that don't have an LSHIFTRT.  */
8640       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8641           && code == ASHIFTRT
8642           && ((nonzero_bits (varop, shift_mode)
8643                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8644               == 0))
8645         code = LSHIFTRT;
8646
8647       if (((code == LSHIFTRT
8648             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8649             && !(nonzero_bits (varop, shift_mode) >> count))
8650            || (code == ASHIFT
8651                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8652                && !((nonzero_bits (varop, shift_mode) << count)
8653                     & GET_MODE_MASK (shift_mode))))
8654           && !side_effects_p (varop))
8655         varop = const0_rtx;
8656
8657       switch (GET_CODE (varop))
8658         {
8659         case SIGN_EXTEND:
8660         case ZERO_EXTEND:
8661         case SIGN_EXTRACT:
8662         case ZERO_EXTRACT:
8663           new = expand_compound_operation (varop);
8664           if (new != varop)
8665             {
8666               varop = new;
8667               continue;
8668             }
8669           break;
8670
8671         case MEM:
8672           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8673              minus the width of a smaller mode, we can do this with a
8674              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8675           if ((code == ASHIFTRT || code == LSHIFTRT)
8676               && ! mode_dependent_address_p (XEXP (varop, 0))
8677               && ! MEM_VOLATILE_P (varop)
8678               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8679                                          MODE_INT, 1)) != BLKmode)
8680             {
8681               new = adjust_address_nv (varop, tmode,
8682                                        BYTES_BIG_ENDIAN ? 0
8683                                        : count / BITS_PER_UNIT);
8684
8685               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8686                                      : ZERO_EXTEND, mode, new);
8687               count = 0;
8688               continue;
8689             }
8690           break;
8691
8692         case SUBREG:
8693           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8694              the same number of words as what we've seen so far.  Then store
8695              the widest mode in MODE.  */
8696           if (subreg_lowpart_p (varop)
8697               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8698                   > GET_MODE_SIZE (GET_MODE (varop)))
8699               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8700                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8701                  == mode_words)
8702             {
8703               varop = SUBREG_REG (varop);
8704               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8705                 mode = GET_MODE (varop);
8706               continue;
8707             }
8708           break;
8709
8710         case MULT:
8711           /* Some machines use MULT instead of ASHIFT because MULT
8712              is cheaper.  But it is still better on those machines to
8713              merge two shifts into one.  */
8714           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8715               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8716             {
8717               varop
8718                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8719                                        XEXP (varop, 0),
8720                                        GEN_INT (exact_log2 (
8721                                                 INTVAL (XEXP (varop, 1)))));
8722               continue;
8723             }
8724           break;
8725
8726         case UDIV:
8727           /* Similar, for when divides are cheaper.  */
8728           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8729               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8730             {
8731               varop
8732                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8733                                        XEXP (varop, 0),
8734                                        GEN_INT (exact_log2 (
8735                                                 INTVAL (XEXP (varop, 1)))));
8736               continue;
8737             }
8738           break;
8739
8740         case ASHIFTRT:
8741           /* If we are extracting just the sign bit of an arithmetic
8742              right shift, that shift is not needed.  However, the sign
8743              bit of a wider mode may be different from what would be
8744              interpreted as the sign bit in a narrower mode, so, if
8745              the result is narrower, don't discard the shift.  */
8746           if (code == LSHIFTRT
8747               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8748               && (GET_MODE_BITSIZE (result_mode)
8749                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8750             {
8751               varop = XEXP (varop, 0);
8752               continue;
8753             }
8754
8755           /* ... fall through ...  */
8756
8757         case LSHIFTRT:
8758         case ASHIFT:
8759         case ROTATE:
8760           /* Here we have two nested shifts.  The result is usually the
8761              AND of a new shift with a mask.  We compute the result below.  */
8762           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8763               && INTVAL (XEXP (varop, 1)) >= 0
8764               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8765               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8766               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8767               && !VECTOR_MODE_P (result_mode))
8768             {
8769               enum rtx_code first_code = GET_CODE (varop);
8770               unsigned int first_count = INTVAL (XEXP (varop, 1));
8771               unsigned HOST_WIDE_INT mask;
8772               rtx mask_rtx;
8773
8774               /* We have one common special case.  We can't do any merging if
8775                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8776                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8777                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8778                  we can convert it to
8779                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8780                  This simplifies certain SIGN_EXTEND operations.  */
8781               if (code == ASHIFT && first_code == ASHIFTRT
8782                   && count == (GET_MODE_BITSIZE (result_mode)
8783                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8784                 {
8785                   /* C3 has the low-order C1 bits zero.  */
8786
8787                   mask = (GET_MODE_MASK (mode)
8788                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8789
8790                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8791                                                   XEXP (varop, 0), mask);
8792                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8793                                                 varop, count);
8794                   count = first_count;
8795                   code = ASHIFTRT;
8796                   continue;
8797                 }
8798
8799               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8800                  than C1 high-order bits equal to the sign bit, we can convert
8801                  this to either an ASHIFT or an ASHIFTRT depending on the
8802                  two counts.
8803
8804                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8805
8806               if (code == ASHIFTRT && first_code == ASHIFT
8807                   && GET_MODE (varop) == shift_mode
8808                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8809                       > first_count))
8810                 {
8811                   varop = XEXP (varop, 0);
8812                   count -= first_count;
8813                   if (count < 0)
8814                     {
8815                       count = -count;
8816                       code = ASHIFT;
8817                     }
8818
8819                   continue;
8820                 }
8821
8822               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8823                  we can only do this if FIRST_CODE is also ASHIFTRT.
8824
8825                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8826                  ASHIFTRT.
8827
8828                  If the mode of this shift is not the mode of the outer shift,
8829                  we can't do this if either shift is a right shift or ROTATE.
8830
8831                  Finally, we can't do any of these if the mode is too wide
8832                  unless the codes are the same.
8833
8834                  Handle the case where the shift codes are the same
8835                  first.  */
8836
8837               if (code == first_code)
8838                 {
8839                   if (GET_MODE (varop) != result_mode
8840                       && (code == ASHIFTRT || code == LSHIFTRT
8841                           || code == ROTATE))
8842                     break;
8843
8844                   count += first_count;
8845                   varop = XEXP (varop, 0);
8846                   continue;
8847                 }
8848
8849               if (code == ASHIFTRT
8850                   || (code == ROTATE && first_code == ASHIFTRT)
8851                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8852                   || (GET_MODE (varop) != result_mode
8853                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8854                           || first_code == ROTATE
8855                           || code == ROTATE)))
8856                 break;
8857
8858               /* To compute the mask to apply after the shift, shift the
8859                  nonzero bits of the inner shift the same way the
8860                  outer shift will.  */
8861
8862               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8863
8864               mask_rtx
8865                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8866                                                    GEN_INT (count));
8867
8868               /* Give up if we can't compute an outer operation to use.  */
8869               if (mask_rtx == 0
8870                   || GET_CODE (mask_rtx) != CONST_INT
8871                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8872                                         INTVAL (mask_rtx),
8873                                         result_mode, &complement_p))
8874                 break;
8875
8876               /* If the shifts are in the same direction, we add the
8877                  counts.  Otherwise, we subtract them.  */
8878               if ((code == ASHIFTRT || code == LSHIFTRT)
8879                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8880                 count += first_count;
8881               else
8882                 count -= first_count;
8883
8884               /* If COUNT is positive, the new shift is usually CODE,
8885                  except for the two exceptions below, in which case it is
8886                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8887                  always be used  */
8888               if (count > 0
8889                   && ((first_code == ROTATE && code == ASHIFT)
8890                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8891                 code = first_code;
8892               else if (count < 0)
8893                 code = first_code, count = -count;
8894
8895               varop = XEXP (varop, 0);
8896               continue;
8897             }
8898
8899           /* If we have (A << B << C) for any shift, we can convert this to
8900              (A << C << B).  This wins if A is a constant.  Only try this if
8901              B is not a constant.  */
8902
8903           else if (GET_CODE (varop) == code
8904                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8905                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8906             {
8907               rtx new = simplify_const_binary_operation (code, mode,
8908                                                          XEXP (varop, 0),
8909                                                          GEN_INT (count));
8910               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8911               count = 0;
8912               continue;
8913             }
8914           break;
8915
8916         case NOT:
8917           /* Make this fit the case below.  */
8918           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8919                                GEN_INT (GET_MODE_MASK (mode)));
8920           continue;
8921
8922         case IOR:
8923         case AND:
8924         case XOR:
8925           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8926              with C the size of VAROP - 1 and the shift is logical if
8927              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8928              we have an (le X 0) operation.   If we have an arithmetic shift
8929              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8930              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8931
8932           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8933               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8934               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8935               && (code == LSHIFTRT || code == ASHIFTRT)
8936               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8937               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8938             {
8939               count = 0;
8940               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8941                                   const0_rtx);
8942
8943               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8944                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8945
8946               continue;
8947             }
8948
8949           /* If we have (shift (logical)), move the logical to the outside
8950              to allow it to possibly combine with another logical and the
8951              shift to combine with another shift.  This also canonicalizes to
8952              what a ZERO_EXTRACT looks like.  Also, some machines have
8953              (and (shift)) insns.  */
8954
8955           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8956               /* We can't do this if we have (ashiftrt (xor))  and the
8957                  constant has its sign bit set in shift_mode.  */
8958               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8959                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8960                                               shift_mode))
8961               && (new = simplify_const_binary_operation (code, result_mode,
8962                                                          XEXP (varop, 1),
8963                                                          GEN_INT (count))) != 0
8964               && GET_CODE (new) == CONST_INT
8965               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8966                                   INTVAL (new), result_mode, &complement_p))
8967             {
8968               varop = XEXP (varop, 0);
8969               continue;
8970             }
8971
8972           /* If we can't do that, try to simplify the shift in each arm of the
8973              logical expression, make a new logical expression, and apply
8974              the inverse distributive law.  This also can't be done
8975              for some (ashiftrt (xor)).  */
8976           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8977              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8978                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8979                                              shift_mode)))
8980             {
8981               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8982                                               XEXP (varop, 0), count);
8983               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8984                                               XEXP (varop, 1), count);
8985
8986               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8987                                            lhs, rhs);
8988               varop = apply_distributive_law (varop);
8989
8990               count = 0;
8991               continue;
8992             }
8993           break;
8994
8995         case EQ:
8996           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8997              says that the sign bit can be tested, FOO has mode MODE, C is
8998              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8999              that may be nonzero.  */
9000           if (code == LSHIFTRT
9001               && XEXP (varop, 1) == const0_rtx
9002               && GET_MODE (XEXP (varop, 0)) == result_mode
9003               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9004               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9005               && STORE_FLAG_VALUE == -1
9006               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9007               && merge_outer_ops (&outer_op, &outer_const, XOR,
9008                                   (HOST_WIDE_INT) 1, result_mode,
9009                                   &complement_p))
9010             {
9011               varop = XEXP (varop, 0);
9012               count = 0;
9013               continue;
9014             }
9015           break;
9016
9017         case NEG:
9018           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9019              than the number of bits in the mode is equivalent to A.  */
9020           if (code == LSHIFTRT
9021               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9022               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9023             {
9024               varop = XEXP (varop, 0);
9025               count = 0;
9026               continue;
9027             }
9028
9029           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9030              NEG outside to allow shifts to combine.  */
9031           if (code == ASHIFT
9032               && merge_outer_ops (&outer_op, &outer_const, NEG,
9033                                   (HOST_WIDE_INT) 0, result_mode,
9034                                   &complement_p))
9035             {
9036               varop = XEXP (varop, 0);
9037               continue;
9038             }
9039           break;
9040
9041         case PLUS:
9042           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9043              is one less than the number of bits in the mode is
9044              equivalent to (xor A 1).  */
9045           if (code == LSHIFTRT
9046               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9047               && XEXP (varop, 1) == constm1_rtx
9048               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9049               && merge_outer_ops (&outer_op, &outer_const, XOR,
9050                                   (HOST_WIDE_INT) 1, result_mode,
9051                                   &complement_p))
9052             {
9053               count = 0;
9054               varop = XEXP (varop, 0);
9055               continue;
9056             }
9057
9058           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9059              that might be nonzero in BAR are those being shifted out and those
9060              bits are known zero in FOO, we can replace the PLUS with FOO.
9061              Similarly in the other operand order.  This code occurs when
9062              we are computing the size of a variable-size array.  */
9063
9064           if ((code == ASHIFTRT || code == LSHIFTRT)
9065               && count < HOST_BITS_PER_WIDE_INT
9066               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9067               && (nonzero_bits (XEXP (varop, 1), result_mode)
9068                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9069             {
9070               varop = XEXP (varop, 0);
9071               continue;
9072             }
9073           else if ((code == ASHIFTRT || code == LSHIFTRT)
9074                    && count < HOST_BITS_PER_WIDE_INT
9075                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9076                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9077                             >> count)
9078                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9079                             & nonzero_bits (XEXP (varop, 1),
9080                                                  result_mode)))
9081             {
9082               varop = XEXP (varop, 1);
9083               continue;
9084             }
9085
9086           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9087           if (code == ASHIFT
9088               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9089               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9090                                                          XEXP (varop, 1),
9091                                                          GEN_INT (count))) != 0
9092               && GET_CODE (new) == CONST_INT
9093               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9094                                   INTVAL (new), result_mode, &complement_p))
9095             {
9096               varop = XEXP (varop, 0);
9097               continue;
9098             }
9099
9100           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9101              signbit', and attempt to change the PLUS to an XOR and move it to
9102              the outer operation as is done above in the AND/IOR/XOR case
9103              leg for shift(logical). See details in logical handling above
9104              for reasoning in doing so.  */
9105           if (code == LSHIFTRT
9106               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9107               && mode_signbit_p (result_mode, XEXP (varop, 1))
9108               && (new = simplify_const_binary_operation (code, result_mode,
9109                                                          XEXP (varop, 1),
9110                                                          GEN_INT (count))) != 0
9111               && GET_CODE (new) == CONST_INT
9112               && merge_outer_ops (&outer_op, &outer_const, XOR,
9113                                   INTVAL (new), result_mode, &complement_p))
9114             {
9115               varop = XEXP (varop, 0);
9116               continue;
9117             }
9118
9119           break;
9120
9121         case MINUS:
9122           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9123              with C the size of VAROP - 1 and the shift is logical if
9124              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9125              we have a (gt X 0) operation.  If the shift is arithmetic with
9126              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9127              we have a (neg (gt X 0)) operation.  */
9128
9129           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9130               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9131               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9132               && (code == LSHIFTRT || code == ASHIFTRT)
9133               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9134               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9135               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9136             {
9137               count = 0;
9138               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9139                                   const0_rtx);
9140
9141               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9142                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9143
9144               continue;
9145             }
9146           break;
9147
9148         case TRUNCATE:
9149           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9150              if the truncate does not affect the value.  */
9151           if (code == LSHIFTRT
9152               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9153               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9154               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9155                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9156                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9157             {
9158               rtx varop_inner = XEXP (varop, 0);
9159
9160               varop_inner
9161                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9162                                     XEXP (varop_inner, 0),
9163                                     GEN_INT
9164                                     (count + INTVAL (XEXP (varop_inner, 1))));
9165               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9166               count = 0;
9167               continue;
9168             }
9169           break;
9170
9171         default:
9172           break;
9173         }
9174
9175       break;
9176     }
9177
9178   /* We need to determine what mode to do the shift in.  If the shift is
9179      a right shift or ROTATE, we must always do it in the mode it was
9180      originally done in.  Otherwise, we can do it in MODE, the widest mode
9181      encountered.  The code we care about is that of the shift that will
9182      actually be done, not the shift that was originally requested.  */
9183   shift_mode
9184     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9185        ? result_mode : mode);
9186
9187   /* We have now finished analyzing the shift.  The result should be
9188      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9189      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9190      to the result of the shift.  OUTER_CONST is the relevant constant,
9191      but we must turn off all bits turned off in the shift.  */
9192
9193   if (outer_op == UNKNOWN
9194       && orig_code == code && orig_count == count
9195       && varop == orig_varop
9196       && shift_mode == GET_MODE (varop))
9197     return NULL_RTX;
9198
9199   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9200   varop = gen_lowpart (shift_mode, varop);
9201   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9202     return NULL_RTX;
9203
9204   /* If we have an outer operation and we just made a shift, it is
9205      possible that we could have simplified the shift were it not
9206      for the outer operation.  So try to do the simplification
9207      recursively.  */
9208
9209   if (outer_op != UNKNOWN)
9210     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9211   else
9212     x = NULL_RTX;
9213
9214   if (x == NULL_RTX)
9215     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9216
9217   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9218      turn off all the bits that the shift would have turned off.  */
9219   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9220     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9221                                 GET_MODE_MASK (result_mode) >> orig_count);
9222
9223   /* Do the remainder of the processing in RESULT_MODE.  */
9224   x = gen_lowpart_or_truncate (result_mode, x);
9225
9226   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9227      operation.  */
9228   if (complement_p)
9229     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9230
9231   if (outer_op != UNKNOWN)
9232     {
9233       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9234         outer_const = trunc_int_for_mode (outer_const, result_mode);
9235
9236       if (outer_op == AND)
9237         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9238       else if (outer_op == SET)
9239         {
9240           /* This means that we have determined that the result is
9241              equivalent to a constant.  This should be rare.  */
9242           if (!side_effects_p (x))
9243             x = GEN_INT (outer_const);
9244         }
9245       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9246         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9247       else
9248         x = simplify_gen_binary (outer_op, result_mode, x,
9249                                  GEN_INT (outer_const));
9250     }
9251
9252   return x;
9253 }
9254
9255 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9256    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9257    return X or, if it is NULL, synthesize the expression with
9258    simplify_gen_binary.  Otherwise, return a simplified value.
9259
9260    The shift is normally computed in the widest mode we find in VAROP, as
9261    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9262    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9263
9264 static rtx
9265 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9266                       rtx varop, int count)
9267 {
9268   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9269   if (tem)
9270     return tem;
9271
9272   if (!x)
9273     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9274   if (GET_MODE (x) != result_mode)
9275     x = gen_lowpart (result_mode, x);
9276   return x;
9277 }
9278
9279 \f
9280 /* Like recog, but we receive the address of a pointer to a new pattern.
9281    We try to match the rtx that the pointer points to.
9282    If that fails, we may try to modify or replace the pattern,
9283    storing the replacement into the same pointer object.
9284
9285    Modifications include deletion or addition of CLOBBERs.
9286
9287    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9288    the CLOBBERs are placed.
9289
9290    The value is the final insn code from the pattern ultimately matched,
9291    or -1.  */
9292
9293 static int
9294 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9295 {
9296   rtx pat = *pnewpat;
9297   int insn_code_number;
9298   int num_clobbers_to_add = 0;
9299   int i;
9300   rtx notes = 0;
9301   rtx old_notes, old_pat;
9302
9303   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9304      we use to indicate that something didn't match.  If we find such a
9305      thing, force rejection.  */
9306   if (GET_CODE (pat) == PARALLEL)
9307     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9308       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9309           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9310         return -1;
9311
9312   old_pat = PATTERN (insn);
9313   old_notes = REG_NOTES (insn);
9314   PATTERN (insn) = pat;
9315   REG_NOTES (insn) = 0;
9316
9317   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9318
9319   /* If it isn't, there is the possibility that we previously had an insn
9320      that clobbered some register as a side effect, but the combined
9321      insn doesn't need to do that.  So try once more without the clobbers
9322      unless this represents an ASM insn.  */
9323
9324   if (insn_code_number < 0 && ! check_asm_operands (pat)
9325       && GET_CODE (pat) == PARALLEL)
9326     {
9327       int pos;
9328
9329       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9330         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9331           {
9332             if (i != pos)
9333               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9334             pos++;
9335           }
9336
9337       SUBST_INT (XVECLEN (pat, 0), pos);
9338
9339       if (pos == 1)
9340         pat = XVECEXP (pat, 0, 0);
9341
9342       PATTERN (insn) = pat;
9343       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9344     }
9345   PATTERN (insn) = old_pat;
9346   REG_NOTES (insn) = old_notes;
9347
9348   /* Recognize all noop sets, these will be killed by followup pass.  */
9349   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9350     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9351
9352   /* If we had any clobbers to add, make a new pattern than contains
9353      them.  Then check to make sure that all of them are dead.  */
9354   if (num_clobbers_to_add)
9355     {
9356       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9357                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9358                                                   ? (XVECLEN (pat, 0)
9359                                                      + num_clobbers_to_add)
9360                                                   : num_clobbers_to_add + 1));
9361
9362       if (GET_CODE (pat) == PARALLEL)
9363         for (i = 0; i < XVECLEN (pat, 0); i++)
9364           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9365       else
9366         XVECEXP (newpat, 0, 0) = pat;
9367
9368       add_clobbers (newpat, insn_code_number);
9369
9370       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9371            i < XVECLEN (newpat, 0); i++)
9372         {
9373           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9374               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9375             return -1;
9376           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9377                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9378         }
9379       pat = newpat;
9380     }
9381
9382   *pnewpat = pat;
9383   *pnotes = notes;
9384
9385   return insn_code_number;
9386 }
9387 \f
9388 /* Like gen_lowpart_general but for use by combine.  In combine it
9389    is not possible to create any new pseudoregs.  However, it is
9390    safe to create invalid memory addresses, because combine will
9391    try to recognize them and all they will do is make the combine
9392    attempt fail.
9393
9394    If for some reason this cannot do its job, an rtx
9395    (clobber (const_int 0)) is returned.
9396    An insn containing that will not be recognized.  */
9397
9398 static rtx
9399 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9400 {
9401   enum machine_mode imode = GET_MODE (x);
9402   unsigned int osize = GET_MODE_SIZE (omode);
9403   unsigned int isize = GET_MODE_SIZE (imode);
9404   rtx result;
9405
9406   if (omode == imode)
9407     return x;
9408
9409   /* Return identity if this is a CONST or symbolic reference.  */
9410   if (omode == Pmode
9411       && (GET_CODE (x) == CONST
9412           || GET_CODE (x) == SYMBOL_REF
9413           || GET_CODE (x) == LABEL_REF))
9414     return x;
9415
9416   /* We can only support MODE being wider than a word if X is a
9417      constant integer or has a mode the same size.  */
9418   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9419       && ! ((imode == VOIDmode
9420              && (GET_CODE (x) == CONST_INT
9421                  || GET_CODE (x) == CONST_DOUBLE))
9422             || isize == osize))
9423     goto fail;
9424
9425   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9426      won't know what to do.  So we will strip off the SUBREG here and
9427      process normally.  */
9428   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9429     {
9430       x = SUBREG_REG (x);
9431
9432       /* For use in case we fall down into the address adjustments
9433          further below, we need to adjust the known mode and size of
9434          x; imode and isize, since we just adjusted x.  */
9435       imode = GET_MODE (x);
9436
9437       if (imode == omode)
9438         return x;
9439
9440       isize = GET_MODE_SIZE (imode);
9441     }
9442
9443   result = gen_lowpart_common (omode, x);
9444
9445 #ifdef CANNOT_CHANGE_MODE_CLASS
9446   if (result != 0 && GET_CODE (result) == SUBREG)
9447     record_subregs_of_mode (result);
9448 #endif
9449
9450   if (result)
9451     return result;
9452
9453   if (MEM_P (x))
9454     {
9455       int offset = 0;
9456
9457       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9458          address.  */
9459       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9460         goto fail;
9461
9462       /* If we want to refer to something bigger than the original memref,
9463          generate a paradoxical subreg instead.  That will force a reload
9464          of the original memref X.  */
9465       if (isize < osize)
9466         return gen_rtx_SUBREG (omode, x, 0);
9467
9468       if (WORDS_BIG_ENDIAN)
9469         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9470
9471       /* Adjust the address so that the address-after-the-data is
9472          unchanged.  */
9473       if (BYTES_BIG_ENDIAN)
9474         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9475
9476       return adjust_address_nv (x, omode, offset);
9477     }
9478
9479   /* If X is a comparison operator, rewrite it in a new mode.  This
9480      probably won't match, but may allow further simplifications.  */
9481   else if (COMPARISON_P (x))
9482     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9483
9484   /* If we couldn't simplify X any other way, just enclose it in a
9485      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9486      include an explicit SUBREG or we may simplify it further in combine.  */
9487   else
9488     {
9489       int offset = 0;
9490       rtx res;
9491
9492       offset = subreg_lowpart_offset (omode, imode);
9493       if (imode == VOIDmode)
9494         {
9495           imode = int_mode_for_mode (omode);
9496           x = gen_lowpart_common (imode, x);
9497           if (x == NULL)
9498             goto fail;
9499         }
9500       res = simplify_gen_subreg (omode, x, imode, offset);
9501       if (res)
9502         return res;
9503     }
9504
9505  fail:
9506   return gen_rtx_CLOBBER (imode, const0_rtx);
9507 }
9508 \f
9509 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9510    comparison code that will be tested.
9511
9512    The result is a possibly different comparison code to use.  *POP0 and
9513    *POP1 may be updated.
9514
9515    It is possible that we might detect that a comparison is either always
9516    true or always false.  However, we do not perform general constant
9517    folding in combine, so this knowledge isn't useful.  Such tautologies
9518    should have been detected earlier.  Hence we ignore all such cases.  */
9519
9520 static enum rtx_code
9521 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9522 {
9523   rtx op0 = *pop0;
9524   rtx op1 = *pop1;
9525   rtx tem, tem1;
9526   int i;
9527   enum machine_mode mode, tmode;
9528
9529   /* Try a few ways of applying the same transformation to both operands.  */
9530   while (1)
9531     {
9532 #ifndef WORD_REGISTER_OPERATIONS
9533       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9534          so check specially.  */
9535       if (code != GTU && code != GEU && code != LTU && code != LEU
9536           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9537           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9538           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9539           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9540           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9541           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9542               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9543           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9544           && XEXP (op0, 1) == XEXP (op1, 1)
9545           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9546           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9547           && (INTVAL (XEXP (op0, 1))
9548               == (GET_MODE_BITSIZE (GET_MODE (op0))
9549                   - (GET_MODE_BITSIZE
9550                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9551         {
9552           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9553           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9554         }
9555 #endif
9556
9557       /* If both operands are the same constant shift, see if we can ignore the
9558          shift.  We can if the shift is a rotate or if the bits shifted out of
9559          this shift are known to be zero for both inputs and if the type of
9560          comparison is compatible with the shift.  */
9561       if (GET_CODE (op0) == GET_CODE (op1)
9562           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9563           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9564               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9565                   && (code != GT && code != LT && code != GE && code != LE))
9566               || (GET_CODE (op0) == ASHIFTRT
9567                   && (code != GTU && code != LTU
9568                       && code != GEU && code != LEU)))
9569           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9570           && INTVAL (XEXP (op0, 1)) >= 0
9571           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9572           && XEXP (op0, 1) == XEXP (op1, 1))
9573         {
9574           enum machine_mode mode = GET_MODE (op0);
9575           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9576           int shift_count = INTVAL (XEXP (op0, 1));
9577
9578           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9579             mask &= (mask >> shift_count) << shift_count;
9580           else if (GET_CODE (op0) == ASHIFT)
9581             mask = (mask & (mask << shift_count)) >> shift_count;
9582
9583           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9584               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9585             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9586           else
9587             break;
9588         }
9589
9590       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9591          SUBREGs are of the same mode, and, in both cases, the AND would
9592          be redundant if the comparison was done in the narrower mode,
9593          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9594          and the operand's possibly nonzero bits are 0xffffff01; in that case
9595          if we only care about QImode, we don't need the AND).  This case
9596          occurs if the output mode of an scc insn is not SImode and
9597          STORE_FLAG_VALUE == 1 (e.g., the 386).
9598
9599          Similarly, check for a case where the AND's are ZERO_EXTEND
9600          operations from some narrower mode even though a SUBREG is not
9601          present.  */
9602
9603       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9604                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9605                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9606         {
9607           rtx inner_op0 = XEXP (op0, 0);
9608           rtx inner_op1 = XEXP (op1, 0);
9609           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9610           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9611           int changed = 0;
9612
9613           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9614               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9615                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9616               && (GET_MODE (SUBREG_REG (inner_op0))
9617                   == GET_MODE (SUBREG_REG (inner_op1)))
9618               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9619                   <= HOST_BITS_PER_WIDE_INT)
9620               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9621                                              GET_MODE (SUBREG_REG (inner_op0)))))
9622               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9623                                              GET_MODE (SUBREG_REG (inner_op1))))))
9624             {
9625               op0 = SUBREG_REG (inner_op0);
9626               op1 = SUBREG_REG (inner_op1);
9627
9628               /* The resulting comparison is always unsigned since we masked
9629                  off the original sign bit.  */
9630               code = unsigned_condition (code);
9631
9632               changed = 1;
9633             }
9634
9635           else if (c0 == c1)
9636             for (tmode = GET_CLASS_NARROWEST_MODE
9637                  (GET_MODE_CLASS (GET_MODE (op0)));
9638                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9639               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9640                 {
9641                   op0 = gen_lowpart (tmode, inner_op0);
9642                   op1 = gen_lowpart (tmode, inner_op1);
9643                   code = unsigned_condition (code);
9644                   changed = 1;
9645                   break;
9646                 }
9647
9648           if (! changed)
9649             break;
9650         }
9651
9652       /* If both operands are NOT, we can strip off the outer operation
9653          and adjust the comparison code for swapped operands; similarly for
9654          NEG, except that this must be an equality comparison.  */
9655       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9656                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9657                    && (code == EQ || code == NE)))
9658         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9659
9660       else
9661         break;
9662     }
9663
9664   /* If the first operand is a constant, swap the operands and adjust the
9665      comparison code appropriately, but don't do this if the second operand
9666      is already a constant integer.  */
9667   if (swap_commutative_operands_p (op0, op1))
9668     {
9669       tem = op0, op0 = op1, op1 = tem;
9670       code = swap_condition (code);
9671     }
9672
9673   /* We now enter a loop during which we will try to simplify the comparison.
9674      For the most part, we only are concerned with comparisons with zero,
9675      but some things may really be comparisons with zero but not start
9676      out looking that way.  */
9677
9678   while (GET_CODE (op1) == CONST_INT)
9679     {
9680       enum machine_mode mode = GET_MODE (op0);
9681       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9682       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9683       int equality_comparison_p;
9684       int sign_bit_comparison_p;
9685       int unsigned_comparison_p;
9686       HOST_WIDE_INT const_op;
9687
9688       /* We only want to handle integral modes.  This catches VOIDmode,
9689          CCmode, and the floating-point modes.  An exception is that we
9690          can handle VOIDmode if OP0 is a COMPARE or a comparison
9691          operation.  */
9692
9693       if (GET_MODE_CLASS (mode) != MODE_INT
9694           && ! (mode == VOIDmode
9695                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9696         break;
9697
9698       /* Get the constant we are comparing against and turn off all bits
9699          not on in our mode.  */
9700       const_op = INTVAL (op1);
9701       if (mode != VOIDmode)
9702         const_op = trunc_int_for_mode (const_op, mode);
9703       op1 = GEN_INT (const_op);
9704
9705       /* If we are comparing against a constant power of two and the value
9706          being compared can only have that single bit nonzero (e.g., it was
9707          `and'ed with that bit), we can replace this with a comparison
9708          with zero.  */
9709       if (const_op
9710           && (code == EQ || code == NE || code == GE || code == GEU
9711               || code == LT || code == LTU)
9712           && mode_width <= HOST_BITS_PER_WIDE_INT
9713           && exact_log2 (const_op) >= 0
9714           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9715         {
9716           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9717           op1 = const0_rtx, const_op = 0;
9718         }
9719
9720       /* Similarly, if we are comparing a value known to be either -1 or
9721          0 with -1, change it to the opposite comparison against zero.  */
9722
9723       if (const_op == -1
9724           && (code == EQ || code == NE || code == GT || code == LE
9725               || code == GEU || code == LTU)
9726           && num_sign_bit_copies (op0, mode) == mode_width)
9727         {
9728           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9729           op1 = const0_rtx, const_op = 0;
9730         }
9731
9732       /* Do some canonicalizations based on the comparison code.  We prefer
9733          comparisons against zero and then prefer equality comparisons.
9734          If we can reduce the size of a constant, we will do that too.  */
9735
9736       switch (code)
9737         {
9738         case LT:
9739           /* < C is equivalent to <= (C - 1) */
9740           if (const_op > 0)
9741             {
9742               const_op -= 1;
9743               op1 = GEN_INT (const_op);
9744               code = LE;
9745               /* ... fall through to LE case below.  */
9746             }
9747           else
9748             break;
9749
9750         case LE:
9751           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9752           if (const_op < 0)
9753             {
9754               const_op += 1;
9755               op1 = GEN_INT (const_op);
9756               code = LT;
9757             }
9758
9759           /* If we are doing a <= 0 comparison on a value known to have
9760              a zero sign bit, we can replace this with == 0.  */
9761           else if (const_op == 0
9762                    && mode_width <= HOST_BITS_PER_WIDE_INT
9763                    && (nonzero_bits (op0, mode)
9764                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9765             code = EQ;
9766           break;
9767
9768         case GE:
9769           /* >= C is equivalent to > (C - 1).  */
9770           if (const_op > 0)
9771             {
9772               const_op -= 1;
9773               op1 = GEN_INT (const_op);
9774               code = GT;
9775               /* ... fall through to GT below.  */
9776             }
9777           else
9778             break;
9779
9780         case GT:
9781           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9782           if (const_op < 0)
9783             {
9784               const_op += 1;
9785               op1 = GEN_INT (const_op);
9786               code = GE;
9787             }
9788
9789           /* If we are doing a > 0 comparison on a value known to have
9790              a zero sign bit, we can replace this with != 0.  */
9791           else if (const_op == 0
9792                    && mode_width <= HOST_BITS_PER_WIDE_INT
9793                    && (nonzero_bits (op0, mode)
9794                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9795             code = NE;
9796           break;
9797
9798         case LTU:
9799           /* < C is equivalent to <= (C - 1).  */
9800           if (const_op > 0)
9801             {
9802               const_op -= 1;
9803               op1 = GEN_INT (const_op);
9804               code = LEU;
9805               /* ... fall through ...  */
9806             }
9807
9808           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9809           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9810                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9811             {
9812               const_op = 0, op1 = const0_rtx;
9813               code = GE;
9814               break;
9815             }
9816           else
9817             break;
9818
9819         case LEU:
9820           /* unsigned <= 0 is equivalent to == 0 */
9821           if (const_op == 0)
9822             code = EQ;
9823
9824           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9825           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9826                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9827             {
9828               const_op = 0, op1 = const0_rtx;
9829               code = GE;
9830             }
9831           break;
9832
9833         case GEU:
9834           /* >= C is equivalent to > (C - 1).  */
9835           if (const_op > 1)
9836             {
9837               const_op -= 1;
9838               op1 = GEN_INT (const_op);
9839               code = GTU;
9840               /* ... fall through ...  */
9841             }
9842
9843           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9844           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9845                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9846             {
9847               const_op = 0, op1 = const0_rtx;
9848               code = LT;
9849               break;
9850             }
9851           else
9852             break;
9853
9854         case GTU:
9855           /* unsigned > 0 is equivalent to != 0 */
9856           if (const_op == 0)
9857             code = NE;
9858
9859           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9860           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9861                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9862             {
9863               const_op = 0, op1 = const0_rtx;
9864               code = LT;
9865             }
9866           break;
9867
9868         default:
9869           break;
9870         }
9871
9872       /* Compute some predicates to simplify code below.  */
9873
9874       equality_comparison_p = (code == EQ || code == NE);
9875       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9876       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9877                                || code == GEU);
9878
9879       /* If this is a sign bit comparison and we can do arithmetic in
9880          MODE, say that we will only be needing the sign bit of OP0.  */
9881       if (sign_bit_comparison_p
9882           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9883         op0 = force_to_mode (op0, mode,
9884                              ((HOST_WIDE_INT) 1
9885                               << (GET_MODE_BITSIZE (mode) - 1)),
9886                              0);
9887
9888       /* Now try cases based on the opcode of OP0.  If none of the cases
9889          does a "continue", we exit this loop immediately after the
9890          switch.  */
9891
9892       switch (GET_CODE (op0))
9893         {
9894         case ZERO_EXTRACT:
9895           /* If we are extracting a single bit from a variable position in
9896              a constant that has only a single bit set and are comparing it
9897              with zero, we can convert this into an equality comparison
9898              between the position and the location of the single bit.  */
9899           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9900              have already reduced the shift count modulo the word size.  */
9901           if (!SHIFT_COUNT_TRUNCATED
9902               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9903               && XEXP (op0, 1) == const1_rtx
9904               && equality_comparison_p && const_op == 0
9905               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9906             {
9907               if (BITS_BIG_ENDIAN)
9908                 {
9909                   enum machine_mode new_mode
9910                     = mode_for_extraction (EP_extzv, 1);
9911                   if (new_mode == MAX_MACHINE_MODE)
9912                     i = BITS_PER_WORD - 1 - i;
9913                   else
9914                     {
9915                       mode = new_mode;
9916                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9917                     }
9918                 }
9919
9920               op0 = XEXP (op0, 2);
9921               op1 = GEN_INT (i);
9922               const_op = i;
9923
9924               /* Result is nonzero iff shift count is equal to I.  */
9925               code = reverse_condition (code);
9926               continue;
9927             }
9928
9929           /* ... fall through ...  */
9930
9931         case SIGN_EXTRACT:
9932           tem = expand_compound_operation (op0);
9933           if (tem != op0)
9934             {
9935               op0 = tem;
9936               continue;
9937             }
9938           break;
9939
9940         case NOT:
9941           /* If testing for equality, we can take the NOT of the constant.  */
9942           if (equality_comparison_p
9943               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9944             {
9945               op0 = XEXP (op0, 0);
9946               op1 = tem;
9947               continue;
9948             }
9949
9950           /* If just looking at the sign bit, reverse the sense of the
9951              comparison.  */
9952           if (sign_bit_comparison_p)
9953             {
9954               op0 = XEXP (op0, 0);
9955               code = (code == GE ? LT : GE);
9956               continue;
9957             }
9958           break;
9959
9960         case NEG:
9961           /* If testing for equality, we can take the NEG of the constant.  */
9962           if (equality_comparison_p
9963               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9964             {
9965               op0 = XEXP (op0, 0);
9966               op1 = tem;
9967               continue;
9968             }
9969
9970           /* The remaining cases only apply to comparisons with zero.  */
9971           if (const_op != 0)
9972             break;
9973
9974           /* When X is ABS or is known positive,
9975              (neg X) is < 0 if and only if X != 0.  */
9976
9977           if (sign_bit_comparison_p
9978               && (GET_CODE (XEXP (op0, 0)) == ABS
9979                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9980                       && (nonzero_bits (XEXP (op0, 0), mode)
9981                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9982             {
9983               op0 = XEXP (op0, 0);
9984               code = (code == LT ? NE : EQ);
9985               continue;
9986             }
9987
9988           /* If we have NEG of something whose two high-order bits are the
9989              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9990           if (num_sign_bit_copies (op0, mode) >= 2)
9991             {
9992               op0 = XEXP (op0, 0);
9993               code = swap_condition (code);
9994               continue;
9995             }
9996           break;
9997
9998         case ROTATE:
9999           /* If we are testing equality and our count is a constant, we
10000              can perform the inverse operation on our RHS.  */
10001           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10002               && (tem = simplify_binary_operation (ROTATERT, mode,
10003                                                    op1, XEXP (op0, 1))) != 0)
10004             {
10005               op0 = XEXP (op0, 0);
10006               op1 = tem;
10007               continue;
10008             }
10009
10010           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10011              a particular bit.  Convert it to an AND of a constant of that
10012              bit.  This will be converted into a ZERO_EXTRACT.  */
10013           if (const_op == 0 && sign_bit_comparison_p
10014               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10015               && mode_width <= HOST_BITS_PER_WIDE_INT)
10016             {
10017               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10018                                             ((HOST_WIDE_INT) 1
10019                                              << (mode_width - 1
10020                                                  - INTVAL (XEXP (op0, 1)))));
10021               code = (code == LT ? NE : EQ);
10022               continue;
10023             }
10024
10025           /* Fall through.  */
10026
10027         case ABS:
10028           /* ABS is ignorable inside an equality comparison with zero.  */
10029           if (const_op == 0 && equality_comparison_p)
10030             {
10031               op0 = XEXP (op0, 0);
10032               continue;
10033             }
10034           break;
10035
10036         case SIGN_EXTEND:
10037           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10038              (compare FOO CONST) if CONST fits in FOO's mode and we
10039              are either testing inequality or have an unsigned
10040              comparison with ZERO_EXTEND or a signed comparison with
10041              SIGN_EXTEND.  But don't do it if we don't have a compare
10042              insn of the given mode, since we'd have to revert it
10043              later on, and then we wouldn't know whether to sign- or
10044              zero-extend.  */
10045           mode = GET_MODE (XEXP (op0, 0));
10046           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10047               && ! unsigned_comparison_p
10048               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10049               && ((unsigned HOST_WIDE_INT) const_op
10050                   < (((unsigned HOST_WIDE_INT) 1
10051                       << (GET_MODE_BITSIZE (mode) - 1))))
10052               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10053             {
10054               op0 = XEXP (op0, 0);
10055               continue;
10056             }
10057           break;
10058
10059         case SUBREG:
10060           /* Check for the case where we are comparing A - C1 with C2, that is
10061
10062                (subreg:MODE (plus (A) (-C1))) op (C2)
10063
10064              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10065              comparison in the wider mode.  One of the following two conditions
10066              must be true in order for this to be valid:
10067
10068                1. The mode extension results in the same bit pattern being added
10069                   on both sides and the comparison is equality or unsigned.  As
10070                   C2 has been truncated to fit in MODE, the pattern can only be
10071                   all 0s or all 1s.
10072
10073                2. The mode extension results in the sign bit being copied on
10074                   each side.
10075
10076              The difficulty here is that we have predicates for A but not for
10077              (A - C1) so we need to check that C1 is within proper bounds so
10078              as to perturbate A as little as possible.  */
10079
10080           if (mode_width <= HOST_BITS_PER_WIDE_INT
10081               && subreg_lowpart_p (op0)
10082               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10083               && GET_CODE (SUBREG_REG (op0)) == PLUS
10084               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10085             {
10086               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10087               rtx a = XEXP (SUBREG_REG (op0), 0);
10088               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10089
10090               if ((c1 > 0
10091                    && (unsigned HOST_WIDE_INT) c1
10092                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10093                    && (equality_comparison_p || unsigned_comparison_p)
10094                    /* (A - C1) zero-extends if it is positive and sign-extends
10095                       if it is negative, C2 both zero- and sign-extends.  */
10096                    && ((0 == (nonzero_bits (a, inner_mode)
10097                               & ~GET_MODE_MASK (mode))
10098                         && const_op >= 0)
10099                        /* (A - C1) sign-extends if it is positive and 1-extends
10100                           if it is negative, C2 both sign- and 1-extends.  */
10101                        || (num_sign_bit_copies (a, inner_mode)
10102                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10103                                              - mode_width)
10104                            && const_op < 0)))
10105                   || ((unsigned HOST_WIDE_INT) c1
10106                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10107                       /* (A - C1) always sign-extends, like C2.  */
10108                       && num_sign_bit_copies (a, inner_mode)
10109                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10110                                            - (mode_width - 1))))
10111                 {
10112                   op0 = SUBREG_REG (op0);
10113                   continue;
10114                 }
10115             }
10116
10117           /* If the inner mode is narrower and we are extracting the low part,
10118              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10119           if (subreg_lowpart_p (op0)
10120               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10121             /* Fall through */ ;
10122           else
10123             break;
10124
10125           /* ... fall through ...  */
10126
10127         case ZERO_EXTEND:
10128           mode = GET_MODE (XEXP (op0, 0));
10129           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10130               && (unsigned_comparison_p || equality_comparison_p)
10131               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10132               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10133               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10134             {
10135               op0 = XEXP (op0, 0);
10136               continue;
10137             }
10138           break;
10139
10140         case PLUS:
10141           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10142              this for equality comparisons due to pathological cases involving
10143              overflows.  */
10144           if (equality_comparison_p
10145               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10146                                                         op1, XEXP (op0, 1))))
10147             {
10148               op0 = XEXP (op0, 0);
10149               op1 = tem;
10150               continue;
10151             }
10152
10153           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10154           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10155               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10156             {
10157               op0 = XEXP (XEXP (op0, 0), 0);
10158               code = (code == LT ? EQ : NE);
10159               continue;
10160             }
10161           break;
10162
10163         case MINUS:
10164           /* We used to optimize signed comparisons against zero, but that
10165              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10166              arrive here as equality comparisons, or (GEU, LTU) are
10167              optimized away.  No need to special-case them.  */
10168
10169           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10170              (eq B (minus A C)), whichever simplifies.  We can only do
10171              this for equality comparisons due to pathological cases involving
10172              overflows.  */
10173           if (equality_comparison_p
10174               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10175                                                         XEXP (op0, 1), op1)))
10176             {
10177               op0 = XEXP (op0, 0);
10178               op1 = tem;
10179               continue;
10180             }
10181
10182           if (equality_comparison_p
10183               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10184                                                         XEXP (op0, 0), op1)))
10185             {
10186               op0 = XEXP (op0, 1);
10187               op1 = tem;
10188               continue;
10189             }
10190
10191           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10192              of bits in X minus 1, is one iff X > 0.  */
10193           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10194               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10195               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10196                  == mode_width - 1
10197               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10198             {
10199               op0 = XEXP (op0, 1);
10200               code = (code == GE ? LE : GT);
10201               continue;
10202             }
10203           break;
10204
10205         case XOR:
10206           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10207              if C is zero or B is a constant.  */
10208           if (equality_comparison_p
10209               && 0 != (tem = simplify_binary_operation (XOR, mode,
10210                                                         XEXP (op0, 1), op1)))
10211             {
10212               op0 = XEXP (op0, 0);
10213               op1 = tem;
10214               continue;
10215             }
10216           break;
10217
10218         case EQ:  case NE:
10219         case UNEQ:  case LTGT:
10220         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10221         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10222         case UNORDERED: case ORDERED:
10223           /* We can't do anything if OP0 is a condition code value, rather
10224              than an actual data value.  */
10225           if (const_op != 0
10226               || CC0_P (XEXP (op0, 0))
10227               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10228             break;
10229
10230           /* Get the two operands being compared.  */
10231           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10232             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10233           else
10234             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10235
10236           /* Check for the cases where we simply want the result of the
10237              earlier test or the opposite of that result.  */
10238           if (code == NE || code == EQ
10239               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10240                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10241                   && (STORE_FLAG_VALUE
10242                       & (((HOST_WIDE_INT) 1
10243                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10244                   && (code == LT || code == GE)))
10245             {
10246               enum rtx_code new_code;
10247               if (code == LT || code == NE)
10248                 new_code = GET_CODE (op0);
10249               else
10250                 new_code = reversed_comparison_code (op0, NULL);
10251
10252               if (new_code != UNKNOWN)
10253                 {
10254                   code = new_code;
10255                   op0 = tem;
10256                   op1 = tem1;
10257                   continue;
10258                 }
10259             }
10260           break;
10261
10262         case IOR:
10263           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10264              iff X <= 0.  */
10265           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10266               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10267               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10268             {
10269               op0 = XEXP (op0, 1);
10270               code = (code == GE ? GT : LE);
10271               continue;
10272             }
10273           break;
10274
10275         case AND:
10276           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10277              will be converted to a ZERO_EXTRACT later.  */
10278           if (const_op == 0 && equality_comparison_p
10279               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10280               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10281             {
10282               op0 = simplify_and_const_int
10283                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10284                                                    XEXP (op0, 1),
10285                                                    XEXP (XEXP (op0, 0), 1)),
10286                  (HOST_WIDE_INT) 1);
10287               continue;
10288             }
10289
10290           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10291              zero and X is a comparison and C1 and C2 describe only bits set
10292              in STORE_FLAG_VALUE, we can compare with X.  */
10293           if (const_op == 0 && equality_comparison_p
10294               && mode_width <= HOST_BITS_PER_WIDE_INT
10295               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10296               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10297               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10298               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10299               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10300             {
10301               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10302                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10303               if ((~STORE_FLAG_VALUE & mask) == 0
10304                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10305                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10306                           && COMPARISON_P (tem))))
10307                 {
10308                   op0 = XEXP (XEXP (op0, 0), 0);
10309                   continue;
10310                 }
10311             }
10312
10313           /* If we are doing an equality comparison of an AND of a bit equal
10314              to the sign bit, replace this with a LT or GE comparison of
10315              the underlying value.  */
10316           if (equality_comparison_p
10317               && const_op == 0
10318               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10319               && mode_width <= HOST_BITS_PER_WIDE_INT
10320               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10321                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10322             {
10323               op0 = XEXP (op0, 0);
10324               code = (code == EQ ? GE : LT);
10325               continue;
10326             }
10327
10328           /* If this AND operation is really a ZERO_EXTEND from a narrower
10329              mode, the constant fits within that mode, and this is either an
10330              equality or unsigned comparison, try to do this comparison in
10331              the narrower mode.
10332
10333              Note that in:
10334
10335              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10336              -> (ne:DI (reg:SI 4) (const_int 0))
10337
10338              unless TRULY_NOOP_TRUNCATION allows it or the register is
10339              known to hold a value of the required mode the
10340              transformation is invalid.  */
10341           if ((equality_comparison_p || unsigned_comparison_p)
10342               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10343               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10344                                    & GET_MODE_MASK (mode))
10345                                   + 1)) >= 0
10346               && const_op >> i == 0
10347               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10348               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10349                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10350                   || (REG_P (XEXP (op0, 0))
10351                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10352             {
10353               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10354               continue;
10355             }
10356
10357           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10358              fits in both M1 and M2 and the SUBREG is either paradoxical
10359              or represents the low part, permute the SUBREG and the AND
10360              and try again.  */
10361           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10362             {
10363               unsigned HOST_WIDE_INT c1;
10364               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10365               /* Require an integral mode, to avoid creating something like
10366                  (AND:SF ...).  */
10367               if (SCALAR_INT_MODE_P (tmode)
10368                   /* It is unsafe to commute the AND into the SUBREG if the
10369                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10370                      not defined.  As originally written the upper bits
10371                      have a defined value due to the AND operation.
10372                      However, if we commute the AND inside the SUBREG then
10373                      they no longer have defined values and the meaning of
10374                      the code has been changed.  */
10375                   && (0
10376 #ifdef WORD_REGISTER_OPERATIONS
10377                       || (mode_width > GET_MODE_BITSIZE (tmode)
10378                           && mode_width <= BITS_PER_WORD)
10379 #endif
10380                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10381                           && subreg_lowpart_p (XEXP (op0, 0))))
10382                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10383                   && mode_width <= HOST_BITS_PER_WIDE_INT
10384                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10385                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10386                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10387                   && c1 != mask
10388                   && c1 != GET_MODE_MASK (tmode))
10389                 {
10390                   op0 = simplify_gen_binary (AND, tmode,
10391                                              SUBREG_REG (XEXP (op0, 0)),
10392                                              gen_int_mode (c1, tmode));
10393                   op0 = gen_lowpart (mode, op0);
10394                   continue;
10395                 }
10396             }
10397
10398           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10399           if (const_op == 0 && equality_comparison_p
10400               && XEXP (op0, 1) == const1_rtx
10401               && GET_CODE (XEXP (op0, 0)) == NOT)
10402             {
10403               op0 = simplify_and_const_int
10404                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10405               code = (code == NE ? EQ : NE);
10406               continue;
10407             }
10408
10409           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10410              (eq (and (lshiftrt X) 1) 0).
10411              Also handle the case where (not X) is expressed using xor.  */
10412           if (const_op == 0 && equality_comparison_p
10413               && XEXP (op0, 1) == const1_rtx
10414               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10415             {
10416               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10417               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10418
10419               if (GET_CODE (shift_op) == NOT
10420                   || (GET_CODE (shift_op) == XOR
10421                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10422                       && GET_CODE (shift_count) == CONST_INT
10423                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10424                       && (INTVAL (XEXP (shift_op, 1))
10425                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10426                 {
10427                   op0 = simplify_and_const_int
10428                     (NULL_RTX, mode,
10429                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10430                      (HOST_WIDE_INT) 1);
10431                   code = (code == NE ? EQ : NE);
10432                   continue;
10433                 }
10434             }
10435           break;
10436
10437         case ASHIFT:
10438           /* If we have (compare (ashift FOO N) (const_int C)) and
10439              the high order N bits of FOO (N+1 if an inequality comparison)
10440              are known to be zero, we can do this by comparing FOO with C
10441              shifted right N bits so long as the low-order N bits of C are
10442              zero.  */
10443           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10444               && INTVAL (XEXP (op0, 1)) >= 0
10445               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10446                   < HOST_BITS_PER_WIDE_INT)
10447               && ((const_op
10448                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10449               && mode_width <= HOST_BITS_PER_WIDE_INT
10450               && (nonzero_bits (XEXP (op0, 0), mode)
10451                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10452                                + ! equality_comparison_p))) == 0)
10453             {
10454               /* We must perform a logical shift, not an arithmetic one,
10455                  as we want the top N bits of C to be zero.  */
10456               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10457
10458               temp >>= INTVAL (XEXP (op0, 1));
10459               op1 = gen_int_mode (temp, mode);
10460               op0 = XEXP (op0, 0);
10461               continue;
10462             }
10463
10464           /* If we are doing a sign bit comparison, it means we are testing
10465              a particular bit.  Convert it to the appropriate AND.  */
10466           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10467               && mode_width <= HOST_BITS_PER_WIDE_INT)
10468             {
10469               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10470                                             ((HOST_WIDE_INT) 1
10471                                              << (mode_width - 1
10472                                                  - INTVAL (XEXP (op0, 1)))));
10473               code = (code == LT ? NE : EQ);
10474               continue;
10475             }
10476
10477           /* If this an equality comparison with zero and we are shifting
10478              the low bit to the sign bit, we can convert this to an AND of the
10479              low-order bit.  */
10480           if (const_op == 0 && equality_comparison_p
10481               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10482               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10483                  == mode_width - 1)
10484             {
10485               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10486                                             (HOST_WIDE_INT) 1);
10487               continue;
10488             }
10489           break;
10490
10491         case ASHIFTRT:
10492           /* If this is an equality comparison with zero, we can do this
10493              as a logical shift, which might be much simpler.  */
10494           if (equality_comparison_p && const_op == 0
10495               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10496             {
10497               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10498                                           XEXP (op0, 0),
10499                                           INTVAL (XEXP (op0, 1)));
10500               continue;
10501             }
10502
10503           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10504              do the comparison in a narrower mode.  */
10505           if (! unsigned_comparison_p
10506               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10507               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10508               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10509               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10510                                          MODE_INT, 1)) != BLKmode
10511               && (((unsigned HOST_WIDE_INT) const_op
10512                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10513                   <= GET_MODE_MASK (tmode)))
10514             {
10515               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10516               continue;
10517             }
10518
10519           /* Likewise if OP0 is a PLUS of a sign extension with a
10520              constant, which is usually represented with the PLUS
10521              between the shifts.  */
10522           if (! unsigned_comparison_p
10523               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10524               && GET_CODE (XEXP (op0, 0)) == PLUS
10525               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10526               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10527               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10528               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10529                                          MODE_INT, 1)) != BLKmode
10530               && (((unsigned HOST_WIDE_INT) const_op
10531                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10532                   <= GET_MODE_MASK (tmode)))
10533             {
10534               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10535               rtx add_const = XEXP (XEXP (op0, 0), 1);
10536               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10537                                                    add_const, XEXP (op0, 1));
10538
10539               op0 = simplify_gen_binary (PLUS, tmode,
10540                                          gen_lowpart (tmode, inner),
10541                                          new_const);
10542               continue;
10543             }
10544
10545           /* ... fall through ...  */
10546         case LSHIFTRT:
10547           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10548              the low order N bits of FOO are known to be zero, we can do this
10549              by comparing FOO with C shifted left N bits so long as no
10550              overflow occurs.  */
10551           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10552               && INTVAL (XEXP (op0, 1)) >= 0
10553               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10554               && mode_width <= HOST_BITS_PER_WIDE_INT
10555               && (nonzero_bits (XEXP (op0, 0), mode)
10556                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10557               && (((unsigned HOST_WIDE_INT) const_op
10558                    + (GET_CODE (op0) != LSHIFTRT
10559                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10560                          + 1)
10561                       : 0))
10562                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10563             {
10564               /* If the shift was logical, then we must make the condition
10565                  unsigned.  */
10566               if (GET_CODE (op0) == LSHIFTRT)
10567                 code = unsigned_condition (code);
10568
10569               const_op <<= INTVAL (XEXP (op0, 1));
10570               op1 = GEN_INT (const_op);
10571               op0 = XEXP (op0, 0);
10572               continue;
10573             }
10574
10575           /* If we are using this shift to extract just the sign bit, we
10576              can replace this with an LT or GE comparison.  */
10577           if (const_op == 0
10578               && (equality_comparison_p || sign_bit_comparison_p)
10579               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10580               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10581                  == mode_width - 1)
10582             {
10583               op0 = XEXP (op0, 0);
10584               code = (code == NE || code == GT ? LT : GE);
10585               continue;
10586             }
10587           break;
10588
10589         default:
10590           break;
10591         }
10592
10593       break;
10594     }
10595
10596   /* Now make any compound operations involved in this comparison.  Then,
10597      check for an outmost SUBREG on OP0 that is not doing anything or is
10598      paradoxical.  The latter transformation must only be performed when
10599      it is known that the "extra" bits will be the same in op0 and op1 or
10600      that they don't matter.  There are three cases to consider:
10601
10602      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10603      care bits and we can assume they have any convenient value.  So
10604      making the transformation is safe.
10605
10606      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10607      In this case the upper bits of op0 are undefined.  We should not make
10608      the simplification in that case as we do not know the contents of
10609      those bits.
10610
10611      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10612      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10613      also be sure that they are the same as the upper bits of op1.
10614
10615      We can never remove a SUBREG for a non-equality comparison because
10616      the sign bit is in a different place in the underlying object.  */
10617
10618   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10619   op1 = make_compound_operation (op1, SET);
10620
10621   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10622       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10623       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10624       && (code == NE || code == EQ))
10625     {
10626       if (GET_MODE_SIZE (GET_MODE (op0))
10627           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10628         {
10629           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10630              implemented.  */
10631           if (REG_P (SUBREG_REG (op0)))
10632             {
10633               op0 = SUBREG_REG (op0);
10634               op1 = gen_lowpart (GET_MODE (op0), op1);
10635             }
10636         }
10637       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10638                 <= HOST_BITS_PER_WIDE_INT)
10639                && (nonzero_bits (SUBREG_REG (op0),
10640                                  GET_MODE (SUBREG_REG (op0)))
10641                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10642         {
10643           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10644
10645           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10646                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10647             op0 = SUBREG_REG (op0), op1 = tem;
10648         }
10649     }
10650
10651   /* We now do the opposite procedure: Some machines don't have compare
10652      insns in all modes.  If OP0's mode is an integer mode smaller than a
10653      word and we can't do a compare in that mode, see if there is a larger
10654      mode for which we can do the compare.  There are a number of cases in
10655      which we can use the wider mode.  */
10656
10657   mode = GET_MODE (op0);
10658   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10659       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10660       && ! have_insn_for (COMPARE, mode))
10661     for (tmode = GET_MODE_WIDER_MODE (mode);
10662          (tmode != VOIDmode
10663           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10664          tmode = GET_MODE_WIDER_MODE (tmode))
10665       if (have_insn_for (COMPARE, tmode))
10666         {
10667           int zero_extended;
10668
10669           /* If the only nonzero bits in OP0 and OP1 are those in the
10670              narrower mode and this is an equality or unsigned comparison,
10671              we can use the wider mode.  Similarly for sign-extended
10672              values, in which case it is true for all comparisons.  */
10673           zero_extended = ((code == EQ || code == NE
10674                             || code == GEU || code == GTU
10675                             || code == LEU || code == LTU)
10676                            && (nonzero_bits (op0, tmode)
10677                                & ~GET_MODE_MASK (mode)) == 0
10678                            && ((GET_CODE (op1) == CONST_INT
10679                                 || (nonzero_bits (op1, tmode)
10680                                     & ~GET_MODE_MASK (mode)) == 0)));
10681
10682           if (zero_extended
10683               || ((num_sign_bit_copies (op0, tmode)
10684                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10685                                      - GET_MODE_BITSIZE (mode)))
10686                   && (num_sign_bit_copies (op1, tmode)
10687                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10688                                         - GET_MODE_BITSIZE (mode)))))
10689             {
10690               /* If OP0 is an AND and we don't have an AND in MODE either,
10691                  make a new AND in the proper mode.  */
10692               if (GET_CODE (op0) == AND
10693                   && !have_insn_for (AND, mode))
10694                 op0 = simplify_gen_binary (AND, tmode,
10695                                            gen_lowpart (tmode,
10696                                                         XEXP (op0, 0)),
10697                                            gen_lowpart (tmode,
10698                                                         XEXP (op0, 1)));
10699
10700               op0 = gen_lowpart (tmode, op0);
10701               if (zero_extended && GET_CODE (op1) == CONST_INT)
10702                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10703               op1 = gen_lowpart (tmode, op1);
10704               break;
10705             }
10706
10707           /* If this is a test for negative, we can make an explicit
10708              test of the sign bit.  */
10709
10710           if (op1 == const0_rtx && (code == LT || code == GE)
10711               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10712             {
10713               op0 = simplify_gen_binary (AND, tmode,
10714                                          gen_lowpart (tmode, op0),
10715                                          GEN_INT ((HOST_WIDE_INT) 1
10716                                                   << (GET_MODE_BITSIZE (mode)
10717                                                       - 1)));
10718               code = (code == LT) ? NE : EQ;
10719               break;
10720             }
10721         }
10722
10723 #ifdef CANONICALIZE_COMPARISON
10724   /* If this machine only supports a subset of valid comparisons, see if we
10725      can convert an unsupported one into a supported one.  */
10726   CANONICALIZE_COMPARISON (code, op0, op1);
10727 #endif
10728
10729   *pop0 = op0;
10730   *pop1 = op1;
10731
10732   return code;
10733 }
10734 \f
10735 /* Utility function for record_value_for_reg.  Count number of
10736    rtxs in X.  */
10737 static int
10738 count_rtxs (rtx x)
10739 {
10740   enum rtx_code code = GET_CODE (x);
10741   const char *fmt;
10742   int i, ret = 1;
10743
10744   if (GET_RTX_CLASS (code) == '2'
10745       || GET_RTX_CLASS (code) == 'c')
10746     {
10747       rtx x0 = XEXP (x, 0);
10748       rtx x1 = XEXP (x, 1);
10749
10750       if (x0 == x1)
10751         return 1 + 2 * count_rtxs (x0);
10752
10753       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10754            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10755           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10756         return 2 + 2 * count_rtxs (x0)
10757                + count_rtxs (x == XEXP (x1, 0)
10758                              ? XEXP (x1, 1) : XEXP (x1, 0));
10759
10760       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10761            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10762           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10763         return 2 + 2 * count_rtxs (x1)
10764                + count_rtxs (x == XEXP (x0, 0)
10765                              ? XEXP (x0, 1) : XEXP (x0, 0));
10766     }
10767
10768   fmt = GET_RTX_FORMAT (code);
10769   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10770     if (fmt[i] == 'e')
10771       ret += count_rtxs (XEXP (x, i));
10772
10773   return ret;
10774 }
10775 \f
10776 /* Utility function for following routine.  Called when X is part of a value
10777    being stored into last_set_value.  Sets last_set_table_tick
10778    for each register mentioned.  Similar to mention_regs in cse.c  */
10779
10780 static void
10781 update_table_tick (rtx x)
10782 {
10783   enum rtx_code code = GET_CODE (x);
10784   const char *fmt = GET_RTX_FORMAT (code);
10785   int i;
10786
10787   if (code == REG)
10788     {
10789       unsigned int regno = REGNO (x);
10790       unsigned int endregno
10791         = regno + (regno < FIRST_PSEUDO_REGISTER
10792                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10793       unsigned int r;
10794
10795       for (r = regno; r < endregno; r++)
10796         reg_stat[r].last_set_table_tick = label_tick;
10797
10798       return;
10799     }
10800
10801   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10802     /* Note that we can't have an "E" in values stored; see
10803        get_last_value_validate.  */
10804     if (fmt[i] == 'e')
10805       {
10806         /* Check for identical subexpressions.  If x contains
10807            identical subexpression we only have to traverse one of
10808            them.  */
10809         if (i == 0 && ARITHMETIC_P (x))
10810           {
10811             /* Note that at this point x1 has already been
10812                processed.  */
10813             rtx x0 = XEXP (x, 0);
10814             rtx x1 = XEXP (x, 1);
10815
10816             /* If x0 and x1 are identical then there is no need to
10817                process x0.  */
10818             if (x0 == x1)
10819               break;
10820
10821             /* If x0 is identical to a subexpression of x1 then while
10822                processing x1, x0 has already been processed.  Thus we
10823                are done with x.  */
10824             if (ARITHMETIC_P (x1)
10825                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10826               break;
10827
10828             /* If x1 is identical to a subexpression of x0 then we
10829                still have to process the rest of x0.  */
10830             if (ARITHMETIC_P (x0)
10831                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10832               {
10833                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10834                 break;
10835               }
10836           }
10837
10838         update_table_tick (XEXP (x, i));
10839       }
10840 }
10841
10842 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10843    are saying that the register is clobbered and we no longer know its
10844    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10845    only permitted with VALUE also zero and is used to invalidate the
10846    register.  */
10847
10848 static void
10849 record_value_for_reg (rtx reg, rtx insn, rtx value)
10850 {
10851   unsigned int regno = REGNO (reg);
10852   unsigned int endregno
10853     = regno + (regno < FIRST_PSEUDO_REGISTER
10854                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10855   unsigned int i;
10856
10857   /* If VALUE contains REG and we have a previous value for REG, substitute
10858      the previous value.  */
10859   if (value && insn && reg_overlap_mentioned_p (reg, value))
10860     {
10861       rtx tem;
10862
10863       /* Set things up so get_last_value is allowed to see anything set up to
10864          our insn.  */
10865       subst_low_cuid = INSN_CUID (insn);
10866       tem = get_last_value (reg);
10867
10868       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10869          it isn't going to be useful and will take a lot of time to process,
10870          so just use the CLOBBER.  */
10871
10872       if (tem)
10873         {
10874           if (ARITHMETIC_P (tem)
10875               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10876               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10877             tem = XEXP (tem, 0);
10878           else if (count_occurrences (value, reg, 1) >= 2)
10879             {
10880               /* If there are two or more occurrences of REG in VALUE,
10881                  prevent the value from growing too much.  */
10882               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10883                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10884             }
10885
10886           value = replace_rtx (copy_rtx (value), reg, tem);
10887         }
10888     }
10889
10890   /* For each register modified, show we don't know its value, that
10891      we don't know about its bitwise content, that its value has been
10892      updated, and that we don't know the location of the death of the
10893      register.  */
10894   for (i = regno; i < endregno; i++)
10895     {
10896       if (insn)
10897         reg_stat[i].last_set = insn;
10898
10899       reg_stat[i].last_set_value = 0;
10900       reg_stat[i].last_set_mode = 0;
10901       reg_stat[i].last_set_nonzero_bits = 0;
10902       reg_stat[i].last_set_sign_bit_copies = 0;
10903       reg_stat[i].last_death = 0;
10904       reg_stat[i].truncated_to_mode = 0;
10905     }
10906
10907   /* Mark registers that are being referenced in this value.  */
10908   if (value)
10909     update_table_tick (value);
10910
10911   /* Now update the status of each register being set.
10912      If someone is using this register in this block, set this register
10913      to invalid since we will get confused between the two lives in this
10914      basic block.  This makes using this register always invalid.  In cse, we
10915      scan the table to invalidate all entries using this register, but this
10916      is too much work for us.  */
10917
10918   for (i = regno; i < endregno; i++)
10919     {
10920       reg_stat[i].last_set_label = label_tick;
10921       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10922         reg_stat[i].last_set_invalid = 1;
10923       else
10924         reg_stat[i].last_set_invalid = 0;
10925     }
10926
10927   /* The value being assigned might refer to X (like in "x++;").  In that
10928      case, we must replace it with (clobber (const_int 0)) to prevent
10929      infinite loops.  */
10930   if (value && ! get_last_value_validate (&value, insn,
10931                                           reg_stat[regno].last_set_label, 0))
10932     {
10933       value = copy_rtx (value);
10934       if (! get_last_value_validate (&value, insn,
10935                                      reg_stat[regno].last_set_label, 1))
10936         value = 0;
10937     }
10938
10939   /* For the main register being modified, update the value, the mode, the
10940      nonzero bits, and the number of sign bit copies.  */
10941
10942   reg_stat[regno].last_set_value = value;
10943
10944   if (value)
10945     {
10946       enum machine_mode mode = GET_MODE (reg);
10947       subst_low_cuid = INSN_CUID (insn);
10948       reg_stat[regno].last_set_mode = mode;
10949       if (GET_MODE_CLASS (mode) == MODE_INT
10950           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10951         mode = nonzero_bits_mode;
10952       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10953       reg_stat[regno].last_set_sign_bit_copies
10954         = num_sign_bit_copies (value, GET_MODE (reg));
10955     }
10956 }
10957
10958 /* Called via note_stores from record_dead_and_set_regs to handle one
10959    SET or CLOBBER in an insn.  DATA is the instruction in which the
10960    set is occurring.  */
10961
10962 static void
10963 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10964 {
10965   rtx record_dead_insn = (rtx) data;
10966
10967   if (GET_CODE (dest) == SUBREG)
10968     dest = SUBREG_REG (dest);
10969
10970   if (!record_dead_insn)
10971     {
10972       if (REG_P (dest))
10973         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10974       return;
10975     }
10976
10977   if (REG_P (dest))
10978     {
10979       /* If we are setting the whole register, we know its value.  Otherwise
10980          show that we don't know the value.  We can handle SUBREG in
10981          some cases.  */
10982       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10983         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10984       else if (GET_CODE (setter) == SET
10985                && GET_CODE (SET_DEST (setter)) == SUBREG
10986                && SUBREG_REG (SET_DEST (setter)) == dest
10987                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10988                && subreg_lowpart_p (SET_DEST (setter)))
10989         record_value_for_reg (dest, record_dead_insn,
10990                               gen_lowpart (GET_MODE (dest),
10991                                                        SET_SRC (setter)));
10992       else
10993         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10994     }
10995   else if (MEM_P (dest)
10996            /* Ignore pushes, they clobber nothing.  */
10997            && ! push_operand (dest, GET_MODE (dest)))
10998     mem_last_set = INSN_CUID (record_dead_insn);
10999 }
11000
11001 /* Update the records of when each REG was most recently set or killed
11002    for the things done by INSN.  This is the last thing done in processing
11003    INSN in the combiner loop.
11004
11005    We update reg_stat[], in particular fields last_set, last_set_value,
11006    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11007    last_death, and also the similar information mem_last_set (which insn
11008    most recently modified memory) and last_call_cuid (which insn was the
11009    most recent subroutine call).  */
11010
11011 static void
11012 record_dead_and_set_regs (rtx insn)
11013 {
11014   rtx link;
11015   unsigned int i;
11016
11017   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11018     {
11019       if (REG_NOTE_KIND (link) == REG_DEAD
11020           && REG_P (XEXP (link, 0)))
11021         {
11022           unsigned int regno = REGNO (XEXP (link, 0));
11023           unsigned int endregno
11024             = regno + (regno < FIRST_PSEUDO_REGISTER
11025                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11026                        : 1);
11027
11028           for (i = regno; i < endregno; i++)
11029             reg_stat[i].last_death = insn;
11030         }
11031       else if (REG_NOTE_KIND (link) == REG_INC)
11032         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11033     }
11034
11035   if (CALL_P (insn))
11036     {
11037       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11038         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11039           {
11040             reg_stat[i].last_set_value = 0;
11041             reg_stat[i].last_set_mode = 0;
11042             reg_stat[i].last_set_nonzero_bits = 0;
11043             reg_stat[i].last_set_sign_bit_copies = 0;
11044             reg_stat[i].last_death = 0;
11045             reg_stat[i].truncated_to_mode = 0;
11046           }
11047
11048       last_call_cuid = mem_last_set = INSN_CUID (insn);
11049
11050       /* We can't combine into a call pattern.  Remember, though, that
11051          the return value register is set at this CUID.  We could
11052          still replace a register with the return value from the
11053          wrong subroutine call!  */
11054       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11055     }
11056   else
11057     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11058 }
11059
11060 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11061    register present in the SUBREG, so for each such SUBREG go back and
11062    adjust nonzero and sign bit information of the registers that are
11063    known to have some zero/sign bits set.
11064
11065    This is needed because when combine blows the SUBREGs away, the
11066    information on zero/sign bits is lost and further combines can be
11067    missed because of that.  */
11068
11069 static void
11070 record_promoted_value (rtx insn, rtx subreg)
11071 {
11072   rtx links, set;
11073   unsigned int regno = REGNO (SUBREG_REG (subreg));
11074   enum machine_mode mode = GET_MODE (subreg);
11075
11076   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11077     return;
11078
11079   for (links = LOG_LINKS (insn); links;)
11080     {
11081       insn = XEXP (links, 0);
11082       set = single_set (insn);
11083
11084       if (! set || !REG_P (SET_DEST (set))
11085           || REGNO (SET_DEST (set)) != regno
11086           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11087         {
11088           links = XEXP (links, 1);
11089           continue;
11090         }
11091
11092       if (reg_stat[regno].last_set == insn)
11093         {
11094           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11095             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11096         }
11097
11098       if (REG_P (SET_SRC (set)))
11099         {
11100           regno = REGNO (SET_SRC (set));
11101           links = LOG_LINKS (insn);
11102         }
11103       else
11104         break;
11105     }
11106 }
11107
11108 /* Check if X, a register, is known to contain a value already
11109    truncated to MODE.  In this case we can use a subreg to refer to
11110    the truncated value even though in the generic case we would need
11111    an explicit truncation.  */
11112
11113 static bool
11114 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11115 {
11116   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11117
11118   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11119     return false;
11120   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11121     return true;
11122   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11123                              GET_MODE_BITSIZE (truncated)))
11124     return true;
11125   return false;
11126 }
11127
11128 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11129    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11130    a truncate into a subreg using this information.  */
11131
11132 static void
11133 record_truncated_value (rtx x)
11134 {
11135   enum machine_mode truncated_mode;
11136
11137   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11138     {
11139       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11140       truncated_mode = GET_MODE (x);
11141
11142       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11143         return;
11144
11145       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11146                                  GET_MODE_BITSIZE (original_mode)))
11147         return;
11148
11149       x = SUBREG_REG (x);
11150     }
11151   /* ??? For hard-regs we now record everything.  We might be able to
11152      optimize this using last_set_mode.  */
11153   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11154     truncated_mode = GET_MODE (x);
11155   else
11156     return;
11157
11158   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11159       || reg_stat[REGNO (x)].truncation_label < label_tick
11160       || (GET_MODE_SIZE (truncated_mode)
11161           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11162     {
11163       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11164       reg_stat[REGNO (x)].truncation_label = label_tick;
11165     }
11166 }
11167
11168 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11169    found, note what it implies to the registers used in it.  */
11170
11171 static void
11172 check_conversions (rtx insn, rtx x)
11173 {
11174   if (GET_CODE (x) == SUBREG || REG_P (x))
11175     {
11176       if (GET_CODE (x) == SUBREG
11177           && SUBREG_PROMOTED_VAR_P (x)
11178           && REG_P (SUBREG_REG (x)))
11179         record_promoted_value (insn, x);
11180
11181       record_truncated_value (x);
11182     }
11183   else
11184     {
11185       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11186       int i, j;
11187
11188       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11189         switch (format[i])
11190           {
11191           case 'e':
11192             check_conversions (insn, XEXP (x, i));
11193             break;
11194           case 'V':
11195           case 'E':
11196             if (XVEC (x, i) != 0)
11197               for (j = 0; j < XVECLEN (x, i); j++)
11198                 check_conversions (insn, XVECEXP (x, i, j));
11199             break;
11200           }
11201     }
11202 }
11203 \f
11204 /* Utility routine for the following function.  Verify that all the registers
11205    mentioned in *LOC are valid when *LOC was part of a value set when
11206    label_tick == TICK.  Return 0 if some are not.
11207
11208    If REPLACE is nonzero, replace the invalid reference with
11209    (clobber (const_int 0)) and return 1.  This replacement is useful because
11210    we often can get useful information about the form of a value (e.g., if
11211    it was produced by a shift that always produces -1 or 0) even though
11212    we don't know exactly what registers it was produced from.  */
11213
11214 static int
11215 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11216 {
11217   rtx x = *loc;
11218   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11219   int len = GET_RTX_LENGTH (GET_CODE (x));
11220   int i;
11221
11222   if (REG_P (x))
11223     {
11224       unsigned int regno = REGNO (x);
11225       unsigned int endregno
11226         = regno + (regno < FIRST_PSEUDO_REGISTER
11227                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11228       unsigned int j;
11229
11230       for (j = regno; j < endregno; j++)
11231         if (reg_stat[j].last_set_invalid
11232             /* If this is a pseudo-register that was only set once and not
11233                live at the beginning of the function, it is always valid.  */
11234             || (! (regno >= FIRST_PSEUDO_REGISTER
11235                    && REG_N_SETS (regno) == 1
11236                    && (! REGNO_REG_SET_P
11237                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11238                         regno)))
11239                 && reg_stat[j].last_set_label > tick))
11240           {
11241             if (replace)
11242               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11243             return replace;
11244           }
11245
11246       return 1;
11247     }
11248   /* If this is a memory reference, make sure that there were
11249      no stores after it that might have clobbered the value.  We don't
11250      have alias info, so we assume any store invalidates it.  */
11251   else if (MEM_P (x) && !MEM_READONLY_P (x)
11252            && INSN_CUID (insn) <= mem_last_set)
11253     {
11254       if (replace)
11255         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11256       return replace;
11257     }
11258
11259   for (i = 0; i < len; i++)
11260     {
11261       if (fmt[i] == 'e')
11262         {
11263           /* Check for identical subexpressions.  If x contains
11264              identical subexpression we only have to traverse one of
11265              them.  */
11266           if (i == 1 && ARITHMETIC_P (x))
11267             {
11268               /* Note that at this point x0 has already been checked
11269                  and found valid.  */
11270               rtx x0 = XEXP (x, 0);
11271               rtx x1 = XEXP (x, 1);
11272
11273               /* If x0 and x1 are identical then x is also valid.  */
11274               if (x0 == x1)
11275                 return 1;
11276
11277               /* If x1 is identical to a subexpression of x0 then
11278                  while checking x0, x1 has already been checked.  Thus
11279                  it is valid and so as x.  */
11280               if (ARITHMETIC_P (x0)
11281                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11282                 return 1;
11283
11284               /* If x0 is identical to a subexpression of x1 then x is
11285                  valid iff the rest of x1 is valid.  */
11286               if (ARITHMETIC_P (x1)
11287                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11288                 return
11289                   get_last_value_validate (&XEXP (x1,
11290                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11291                                            insn, tick, replace);
11292             }
11293
11294           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11295                                        replace) == 0)
11296             return 0;
11297         }
11298       /* Don't bother with these.  They shouldn't occur anyway.  */
11299       else if (fmt[i] == 'E')
11300         return 0;
11301     }
11302
11303   /* If we haven't found a reason for it to be invalid, it is valid.  */
11304   return 1;
11305 }
11306
11307 /* Get the last value assigned to X, if known.  Some registers
11308    in the value may be replaced with (clobber (const_int 0)) if their value
11309    is known longer known reliably.  */
11310
11311 static rtx
11312 get_last_value (rtx x)
11313 {
11314   unsigned int regno;
11315   rtx value;
11316
11317   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11318      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11319      we cannot predict what values the "extra" bits might have.  */
11320   if (GET_CODE (x) == SUBREG
11321       && subreg_lowpart_p (x)
11322       && (GET_MODE_SIZE (GET_MODE (x))
11323           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11324       && (value = get_last_value (SUBREG_REG (x))) != 0)
11325     return gen_lowpart (GET_MODE (x), value);
11326
11327   if (!REG_P (x))
11328     return 0;
11329
11330   regno = REGNO (x);
11331   value = reg_stat[regno].last_set_value;
11332
11333   /* If we don't have a value, or if it isn't for this basic block and
11334      it's either a hard register, set more than once, or it's a live
11335      at the beginning of the function, return 0.
11336
11337      Because if it's not live at the beginning of the function then the reg
11338      is always set before being used (is never used without being set).
11339      And, if it's set only once, and it's always set before use, then all
11340      uses must have the same last value, even if it's not from this basic
11341      block.  */
11342
11343   if (value == 0
11344       || (reg_stat[regno].last_set_label != label_tick
11345           && (regno < FIRST_PSEUDO_REGISTER
11346               || REG_N_SETS (regno) != 1
11347               || (REGNO_REG_SET_P
11348                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11349                    regno)))))
11350     return 0;
11351
11352   /* If the value was set in a later insn than the ones we are processing,
11353      we can't use it even if the register was only set once.  */
11354   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11355     return 0;
11356
11357   /* If the value has all its registers valid, return it.  */
11358   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11359                                reg_stat[regno].last_set_label, 0))
11360     return value;
11361
11362   /* Otherwise, make a copy and replace any invalid register with
11363      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11364
11365   value = copy_rtx (value);
11366   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11367                                reg_stat[regno].last_set_label, 1))
11368     return value;
11369
11370   return 0;
11371 }
11372 \f
11373 /* Return nonzero if expression X refers to a REG or to memory
11374    that is set in an instruction more recent than FROM_CUID.  */
11375
11376 static int
11377 use_crosses_set_p (rtx x, int from_cuid)
11378 {
11379   const char *fmt;
11380   int i;
11381   enum rtx_code code = GET_CODE (x);
11382
11383   if (code == REG)
11384     {
11385       unsigned int regno = REGNO (x);
11386       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11387                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11388
11389 #ifdef PUSH_ROUNDING
11390       /* Don't allow uses of the stack pointer to be moved,
11391          because we don't know whether the move crosses a push insn.  */
11392       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11393         return 1;
11394 #endif
11395       for (; regno < endreg; regno++)
11396         if (reg_stat[regno].last_set
11397             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11398           return 1;
11399       return 0;
11400     }
11401
11402   if (code == MEM && mem_last_set > from_cuid)
11403     return 1;
11404
11405   fmt = GET_RTX_FORMAT (code);
11406
11407   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11408     {
11409       if (fmt[i] == 'E')
11410         {
11411           int j;
11412           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11413             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11414               return 1;
11415         }
11416       else if (fmt[i] == 'e'
11417                && use_crosses_set_p (XEXP (x, i), from_cuid))
11418         return 1;
11419     }
11420   return 0;
11421 }
11422 \f
11423 /* Define three variables used for communication between the following
11424    routines.  */
11425
11426 static unsigned int reg_dead_regno, reg_dead_endregno;
11427 static int reg_dead_flag;
11428
11429 /* Function called via note_stores from reg_dead_at_p.
11430
11431    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11432    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11433
11434 static void
11435 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11436 {
11437   unsigned int regno, endregno;
11438
11439   if (!REG_P (dest))
11440     return;
11441
11442   regno = REGNO (dest);
11443   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11444                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11445
11446   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11447     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11448 }
11449
11450 /* Return nonzero if REG is known to be dead at INSN.
11451
11452    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11453    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11454    live.  Otherwise, see if it is live or dead at the start of the basic
11455    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11456    must be assumed to be always live.  */
11457
11458 static int
11459 reg_dead_at_p (rtx reg, rtx insn)
11460 {
11461   basic_block block;
11462   unsigned int i;
11463
11464   /* Set variables for reg_dead_at_p_1.  */
11465   reg_dead_regno = REGNO (reg);
11466   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11467                                         ? hard_regno_nregs[reg_dead_regno]
11468                                                           [GET_MODE (reg)]
11469                                         : 1);
11470
11471   reg_dead_flag = 0;
11472
11473   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11474      we allow the machine description to decide whether use-and-clobber
11475      patterns are OK.  */
11476   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11477     {
11478       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11479         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11480           return 0;
11481     }
11482
11483   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11484      beginning of function.  */
11485   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11486        insn = prev_nonnote_insn (insn))
11487     {
11488       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11489       if (reg_dead_flag)
11490         return reg_dead_flag == 1 ? 1 : 0;
11491
11492       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11493         return 1;
11494     }
11495
11496   /* Get the basic block that we were in.  */
11497   if (insn == 0)
11498     block = ENTRY_BLOCK_PTR->next_bb;
11499   else
11500     {
11501       FOR_EACH_BB (block)
11502         if (insn == BB_HEAD (block))
11503           break;
11504
11505       if (block == EXIT_BLOCK_PTR)
11506         return 0;
11507     }
11508
11509   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11510     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11511       return 0;
11512
11513   return 1;
11514 }
11515 \f
11516 /* Note hard registers in X that are used.  This code is similar to
11517    that in flow.c, but much simpler since we don't care about pseudos.  */
11518
11519 static void
11520 mark_used_regs_combine (rtx x)
11521 {
11522   RTX_CODE code = GET_CODE (x);
11523   unsigned int regno;
11524   int i;
11525
11526   switch (code)
11527     {
11528     case LABEL_REF:
11529     case SYMBOL_REF:
11530     case CONST_INT:
11531     case CONST:
11532     case CONST_DOUBLE:
11533     case CONST_VECTOR:
11534     case PC:
11535     case ADDR_VEC:
11536     case ADDR_DIFF_VEC:
11537     case ASM_INPUT:
11538 #ifdef HAVE_cc0
11539     /* CC0 must die in the insn after it is set, so we don't need to take
11540        special note of it here.  */
11541     case CC0:
11542 #endif
11543       return;
11544
11545     case CLOBBER:
11546       /* If we are clobbering a MEM, mark any hard registers inside the
11547          address as used.  */
11548       if (MEM_P (XEXP (x, 0)))
11549         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11550       return;
11551
11552     case REG:
11553       regno = REGNO (x);
11554       /* A hard reg in a wide mode may really be multiple registers.
11555          If so, mark all of them just like the first.  */
11556       if (regno < FIRST_PSEUDO_REGISTER)
11557         {
11558           unsigned int endregno, r;
11559
11560           /* None of this applies to the stack, frame or arg pointers.  */
11561           if (regno == STACK_POINTER_REGNUM
11562 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11563               || regno == HARD_FRAME_POINTER_REGNUM
11564 #endif
11565 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11566               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11567 #endif
11568               || regno == FRAME_POINTER_REGNUM)
11569             return;
11570
11571           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11572           for (r = regno; r < endregno; r++)
11573             SET_HARD_REG_BIT (newpat_used_regs, r);
11574         }
11575       return;
11576
11577     case SET:
11578       {
11579         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11580            the address.  */
11581         rtx testreg = SET_DEST (x);
11582
11583         while (GET_CODE (testreg) == SUBREG
11584                || GET_CODE (testreg) == ZERO_EXTRACT
11585                || GET_CODE (testreg) == STRICT_LOW_PART)
11586           testreg = XEXP (testreg, 0);
11587
11588         if (MEM_P (testreg))
11589           mark_used_regs_combine (XEXP (testreg, 0));
11590
11591         mark_used_regs_combine (SET_SRC (x));
11592       }
11593       return;
11594
11595     default:
11596       break;
11597     }
11598
11599   /* Recursively scan the operands of this expression.  */
11600
11601   {
11602     const char *fmt = GET_RTX_FORMAT (code);
11603
11604     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11605       {
11606         if (fmt[i] == 'e')
11607           mark_used_regs_combine (XEXP (x, i));
11608         else if (fmt[i] == 'E')
11609           {
11610             int j;
11611
11612             for (j = 0; j < XVECLEN (x, i); j++)
11613               mark_used_regs_combine (XVECEXP (x, i, j));
11614           }
11615       }
11616   }
11617 }
11618 \f
11619 /* Remove register number REGNO from the dead registers list of INSN.
11620
11621    Return the note used to record the death, if there was one.  */
11622
11623 rtx
11624 remove_death (unsigned int regno, rtx insn)
11625 {
11626   rtx note = find_regno_note (insn, REG_DEAD, regno);
11627
11628   if (note)
11629     {
11630       REG_N_DEATHS (regno)--;
11631       remove_note (insn, note);
11632     }
11633
11634   return note;
11635 }
11636
11637 /* For each register (hardware or pseudo) used within expression X, if its
11638    death is in an instruction with cuid between FROM_CUID (inclusive) and
11639    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11640    list headed by PNOTES.
11641
11642    That said, don't move registers killed by maybe_kill_insn.
11643
11644    This is done when X is being merged by combination into TO_INSN.  These
11645    notes will then be distributed as needed.  */
11646
11647 static void
11648 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11649              rtx *pnotes)
11650 {
11651   const char *fmt;
11652   int len, i;
11653   enum rtx_code code = GET_CODE (x);
11654
11655   if (code == REG)
11656     {
11657       unsigned int regno = REGNO (x);
11658       rtx where_dead = reg_stat[regno].last_death;
11659       rtx before_dead, after_dead;
11660
11661       /* Don't move the register if it gets killed in between from and to.  */
11662       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11663           && ! reg_referenced_p (x, maybe_kill_insn))
11664         return;
11665
11666       /* WHERE_DEAD could be a USE insn made by combine, so first we
11667          make sure that we have insns with valid INSN_CUID values.  */
11668       before_dead = where_dead;
11669       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11670         before_dead = PREV_INSN (before_dead);
11671
11672       after_dead = where_dead;
11673       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11674         after_dead = NEXT_INSN (after_dead);
11675
11676       if (before_dead && after_dead
11677           && INSN_CUID (before_dead) >= from_cuid
11678           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11679               || (where_dead != after_dead
11680                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11681         {
11682           rtx note = remove_death (regno, where_dead);
11683
11684           /* It is possible for the call above to return 0.  This can occur
11685              when last_death points to I2 or I1 that we combined with.
11686              In that case make a new note.
11687
11688              We must also check for the case where X is a hard register
11689              and NOTE is a death note for a range of hard registers
11690              including X.  In that case, we must put REG_DEAD notes for
11691              the remaining registers in place of NOTE.  */
11692
11693           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11694               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11695                   > GET_MODE_SIZE (GET_MODE (x))))
11696             {
11697               unsigned int deadregno = REGNO (XEXP (note, 0));
11698               unsigned int deadend
11699                 = (deadregno + hard_regno_nregs[deadregno]
11700                                                [GET_MODE (XEXP (note, 0))]);
11701               unsigned int ourend
11702                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11703               unsigned int i;
11704
11705               for (i = deadregno; i < deadend; i++)
11706                 if (i < regno || i >= ourend)
11707                   REG_NOTES (where_dead)
11708                     = gen_rtx_EXPR_LIST (REG_DEAD,
11709                                          regno_reg_rtx[i],
11710                                          REG_NOTES (where_dead));
11711             }
11712
11713           /* If we didn't find any note, or if we found a REG_DEAD note that
11714              covers only part of the given reg, and we have a multi-reg hard
11715              register, then to be safe we must check for REG_DEAD notes
11716              for each register other than the first.  They could have
11717              their own REG_DEAD notes lying around.  */
11718           else if ((note == 0
11719                     || (note != 0
11720                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11721                             < GET_MODE_SIZE (GET_MODE (x)))))
11722                    && regno < FIRST_PSEUDO_REGISTER
11723                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11724             {
11725               unsigned int ourend
11726                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11727               unsigned int i, offset;
11728               rtx oldnotes = 0;
11729
11730               if (note)
11731                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11732               else
11733                 offset = 1;
11734
11735               for (i = regno + offset; i < ourend; i++)
11736                 move_deaths (regno_reg_rtx[i],
11737                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11738             }
11739
11740           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11741             {
11742               XEXP (note, 1) = *pnotes;
11743               *pnotes = note;
11744             }
11745           else
11746             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11747
11748           REG_N_DEATHS (regno)++;
11749         }
11750
11751       return;
11752     }
11753
11754   else if (GET_CODE (x) == SET)
11755     {
11756       rtx dest = SET_DEST (x);
11757
11758       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11759
11760       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11761          that accesses one word of a multi-word item, some
11762          piece of everything register in the expression is used by
11763          this insn, so remove any old death.  */
11764       /* ??? So why do we test for equality of the sizes?  */
11765
11766       if (GET_CODE (dest) == ZERO_EXTRACT
11767           || GET_CODE (dest) == STRICT_LOW_PART
11768           || (GET_CODE (dest) == SUBREG
11769               && (((GET_MODE_SIZE (GET_MODE (dest))
11770                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11771                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11772                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11773         {
11774           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11775           return;
11776         }
11777
11778       /* If this is some other SUBREG, we know it replaces the entire
11779          value, so use that as the destination.  */
11780       if (GET_CODE (dest) == SUBREG)
11781         dest = SUBREG_REG (dest);
11782
11783       /* If this is a MEM, adjust deaths of anything used in the address.
11784          For a REG (the only other possibility), the entire value is
11785          being replaced so the old value is not used in this insn.  */
11786
11787       if (MEM_P (dest))
11788         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11789                      to_insn, pnotes);
11790       return;
11791     }
11792
11793   else if (GET_CODE (x) == CLOBBER)
11794     return;
11795
11796   len = GET_RTX_LENGTH (code);
11797   fmt = GET_RTX_FORMAT (code);
11798
11799   for (i = 0; i < len; i++)
11800     {
11801       if (fmt[i] == 'E')
11802         {
11803           int j;
11804           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11805             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11806                          to_insn, pnotes);
11807         }
11808       else if (fmt[i] == 'e')
11809         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11810     }
11811 }
11812 \f
11813 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11814    pattern of an insn.  X must be a REG.  */
11815
11816 static int
11817 reg_bitfield_target_p (rtx x, rtx body)
11818 {
11819   int i;
11820
11821   if (GET_CODE (body) == SET)
11822     {
11823       rtx dest = SET_DEST (body);
11824       rtx target;
11825       unsigned int regno, tregno, endregno, endtregno;
11826
11827       if (GET_CODE (dest) == ZERO_EXTRACT)
11828         target = XEXP (dest, 0);
11829       else if (GET_CODE (dest) == STRICT_LOW_PART)
11830         target = SUBREG_REG (XEXP (dest, 0));
11831       else
11832         return 0;
11833
11834       if (GET_CODE (target) == SUBREG)
11835         target = SUBREG_REG (target);
11836
11837       if (!REG_P (target))
11838         return 0;
11839
11840       tregno = REGNO (target), regno = REGNO (x);
11841       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11842         return target == x;
11843
11844       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11845       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11846
11847       return endregno > tregno && regno < endtregno;
11848     }
11849
11850   else if (GET_CODE (body) == PARALLEL)
11851     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11852       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11853         return 1;
11854
11855   return 0;
11856 }
11857 \f
11858 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11859    as appropriate.  I3 and I2 are the insns resulting from the combination
11860    insns including FROM (I2 may be zero).
11861
11862    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11863    not need REG_DEAD notes because they are being substituted for.  This
11864    saves searching in the most common cases.
11865
11866    Each note in the list is either ignored or placed on some insns, depending
11867    on the type of note.  */
11868
11869 static void
11870 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11871                   rtx elim_i1)
11872 {
11873   rtx note, next_note;
11874   rtx tem;
11875
11876   for (note = notes; note; note = next_note)
11877     {
11878       rtx place = 0, place2 = 0;
11879
11880       next_note = XEXP (note, 1);
11881       switch (REG_NOTE_KIND (note))
11882         {
11883         case REG_BR_PROB:
11884         case REG_BR_PRED:
11885           /* Doesn't matter much where we put this, as long as it's somewhere.
11886              It is preferable to keep these notes on branches, which is most
11887              likely to be i3.  */
11888           place = i3;
11889           break;
11890
11891         case REG_VALUE_PROFILE:
11892           /* Just get rid of this note, as it is unused later anyway.  */
11893           break;
11894
11895         case REG_NON_LOCAL_GOTO:
11896           if (JUMP_P (i3))
11897             place = i3;
11898           else
11899             {
11900               gcc_assert (i2 && JUMP_P (i2));
11901               place = i2;
11902             }
11903           break;
11904
11905         case REG_EH_REGION:
11906           /* These notes must remain with the call or trapping instruction.  */
11907           if (CALL_P (i3))
11908             place = i3;
11909           else if (i2 && CALL_P (i2))
11910             place = i2;
11911           else
11912             {
11913               gcc_assert (flag_non_call_exceptions);
11914               if (may_trap_p (i3))
11915                 place = i3;
11916               else if (i2 && may_trap_p (i2))
11917                 place = i2;
11918               /* ??? Otherwise assume we've combined things such that we
11919                  can now prove that the instructions can't trap.  Drop the
11920                  note in this case.  */
11921             }
11922           break;
11923
11924         case REG_NORETURN:
11925         case REG_SETJMP:
11926           /* These notes must remain with the call.  It should not be
11927              possible for both I2 and I3 to be a call.  */
11928           if (CALL_P (i3))
11929             place = i3;
11930           else
11931             {
11932               gcc_assert (i2 && CALL_P (i2));
11933               place = i2;
11934             }
11935           break;
11936
11937         case REG_UNUSED:
11938           /* Any clobbers for i3 may still exist, and so we must process
11939              REG_UNUSED notes from that insn.
11940
11941              Any clobbers from i2 or i1 can only exist if they were added by
11942              recog_for_combine.  In that case, recog_for_combine created the
11943              necessary REG_UNUSED notes.  Trying to keep any original
11944              REG_UNUSED notes from these insns can cause incorrect output
11945              if it is for the same register as the original i3 dest.
11946              In that case, we will notice that the register is set in i3,
11947              and then add a REG_UNUSED note for the destination of i3, which
11948              is wrong.  However, it is possible to have REG_UNUSED notes from
11949              i2 or i1 for register which were both used and clobbered, so
11950              we keep notes from i2 or i1 if they will turn into REG_DEAD
11951              notes.  */
11952
11953           /* If this register is set or clobbered in I3, put the note there
11954              unless there is one already.  */
11955           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11956             {
11957               if (from_insn != i3)
11958                 break;
11959
11960               if (! (REG_P (XEXP (note, 0))
11961                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11962                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11963                 place = i3;
11964             }
11965           /* Otherwise, if this register is used by I3, then this register
11966              now dies here, so we must put a REG_DEAD note here unless there
11967              is one already.  */
11968           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11969                    && ! (REG_P (XEXP (note, 0))
11970                          ? find_regno_note (i3, REG_DEAD,
11971                                             REGNO (XEXP (note, 0)))
11972                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11973             {
11974               PUT_REG_NOTE_KIND (note, REG_DEAD);
11975               place = i3;
11976             }
11977           break;
11978
11979         case REG_EQUAL:
11980         case REG_EQUIV:
11981         case REG_NOALIAS:
11982           /* These notes say something about results of an insn.  We can
11983              only support them if they used to be on I3 in which case they
11984              remain on I3.  Otherwise they are ignored.
11985
11986              If the note refers to an expression that is not a constant, we
11987              must also ignore the note since we cannot tell whether the
11988              equivalence is still true.  It might be possible to do
11989              slightly better than this (we only have a problem if I2DEST
11990              or I1DEST is present in the expression), but it doesn't
11991              seem worth the trouble.  */
11992
11993           if (from_insn == i3
11994               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11995             place = i3;
11996           break;
11997
11998         case REG_INC:
11999         case REG_NO_CONFLICT:
12000           /* These notes say something about how a register is used.  They must
12001              be present on any use of the register in I2 or I3.  */
12002           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12003             place = i3;
12004
12005           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12006             {
12007               if (place)
12008                 place2 = i2;
12009               else
12010                 place = i2;
12011             }
12012           break;
12013
12014         case REG_LABEL:
12015           /* This can show up in several ways -- either directly in the
12016              pattern, or hidden off in the constant pool with (or without?)
12017              a REG_EQUAL note.  */
12018           /* ??? Ignore the without-reg_equal-note problem for now.  */
12019           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12020               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12021                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12022                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12023             place = i3;
12024
12025           if (i2
12026               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12027                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12028                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12029                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12030             {
12031               if (place)
12032                 place2 = i2;
12033               else
12034                 place = i2;
12035             }
12036
12037           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12038              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12039           if (place && JUMP_P (place))
12040             {
12041               rtx label = JUMP_LABEL (place);
12042
12043               if (!label)
12044                 JUMP_LABEL (place) = XEXP (note, 0);
12045               else
12046                 {
12047                   gcc_assert (label == XEXP (note, 0));
12048                   if (LABEL_P (label))
12049                     LABEL_NUSES (label)--;
12050                 }
12051               place = 0;
12052             }
12053           if (place2 && JUMP_P (place2))
12054             {
12055               rtx label = JUMP_LABEL (place2);
12056
12057               if (!label)
12058                 JUMP_LABEL (place2) = XEXP (note, 0);
12059               else
12060                 {
12061                   gcc_assert (label == XEXP (note, 0));
12062                   if (LABEL_P (label))
12063                     LABEL_NUSES (label)--;
12064                 }
12065               place2 = 0;
12066             }
12067           break;
12068
12069         case REG_NONNEG:
12070           /* This note says something about the value of a register prior
12071              to the execution of an insn.  It is too much trouble to see
12072              if the note is still correct in all situations.  It is better
12073              to simply delete it.  */
12074           break;
12075
12076         case REG_RETVAL:
12077           /* If the insn previously containing this note still exists,
12078              put it back where it was.  Otherwise move it to the previous
12079              insn.  Adjust the corresponding REG_LIBCALL note.  */
12080           if (!NOTE_P (from_insn))
12081             place = from_insn;
12082           else
12083             {
12084               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12085               place = prev_real_insn (from_insn);
12086               if (tem && place)
12087                 XEXP (tem, 0) = place;
12088               /* If we're deleting the last remaining instruction of a
12089                  libcall sequence, don't add the notes.  */
12090               else if (XEXP (note, 0) == from_insn)
12091                 tem = place = 0;
12092               /* Don't add the dangling REG_RETVAL note.  */
12093               else if (! tem)
12094                 place = 0;
12095             }
12096           break;
12097
12098         case REG_LIBCALL:
12099           /* This is handled similarly to REG_RETVAL.  */
12100           if (!NOTE_P (from_insn))
12101             place = from_insn;
12102           else
12103             {
12104               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12105               place = next_real_insn (from_insn);
12106               if (tem && place)
12107                 XEXP (tem, 0) = place;
12108               /* If we're deleting the last remaining instruction of a
12109                  libcall sequence, don't add the notes.  */
12110               else if (XEXP (note, 0) == from_insn)
12111                 tem = place = 0;
12112               /* Don't add the dangling REG_LIBCALL note.  */
12113               else if (! tem)
12114                 place = 0;
12115             }
12116           break;
12117
12118         case REG_DEAD:
12119           /* If we replaced the right hand side of FROM_INSN with a
12120              REG_EQUAL note, the original use of the dying register
12121              will not have been combined into I3 and I2.  In such cases,
12122              FROM_INSN is guaranteed to be the first of the combined
12123              instructions, so we simply need to search back before
12124              FROM_INSN for the previous use or set of this register,
12125              then alter the notes there appropriately.
12126
12127              If the register is used as an input in I3, it dies there.
12128              Similarly for I2, if it is nonzero and adjacent to I3.
12129
12130              If the register is not used as an input in either I3 or I2
12131              and it is not one of the registers we were supposed to eliminate,
12132              there are two possibilities.  We might have a non-adjacent I2
12133              or we might have somehow eliminated an additional register
12134              from a computation.  For example, we might have had A & B where
12135              we discover that B will always be zero.  In this case we will
12136              eliminate the reference to A.
12137
12138              In both cases, we must search to see if we can find a previous
12139              use of A and put the death note there.  */
12140
12141           if (from_insn
12142               && from_insn == i2mod
12143               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12144             tem = from_insn;
12145           else
12146             {
12147               if (from_insn
12148                   && CALL_P (from_insn)
12149                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12150                 place = from_insn;
12151               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12152                 place = i3;
12153               else if (i2 != 0 && next_nonnote_insn (i2) == i3
12154                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12155                 place = i2;
12156               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12157                         && !(i2mod
12158                              && reg_overlap_mentioned_p (XEXP (note, 0),
12159                                                          i2mod_old_rhs)))
12160                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12161                 break;
12162               tem = i3;
12163             }
12164
12165           if (place == 0)
12166             {
12167               basic_block bb = this_basic_block;
12168
12169               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12170                 {
12171                   if (! INSN_P (tem))
12172                     {
12173                       if (tem == BB_HEAD (bb))
12174                         break;
12175                       continue;
12176                     }
12177
12178                   /* If the register is being set at TEM, see if that is all
12179                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12180                      into a REG_UNUSED note instead. Don't delete sets to
12181                      global register vars.  */
12182                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12183                        || !global_regs[REGNO (XEXP (note, 0))])
12184                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12185                     {
12186                       rtx set = single_set (tem);
12187                       rtx inner_dest = 0;
12188 #ifdef HAVE_cc0
12189                       rtx cc0_setter = NULL_RTX;
12190 #endif
12191
12192                       if (set != 0)
12193                         for (inner_dest = SET_DEST (set);
12194                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12195                               || GET_CODE (inner_dest) == SUBREG
12196                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12197                              inner_dest = XEXP (inner_dest, 0))
12198                           ;
12199
12200                       /* Verify that it was the set, and not a clobber that
12201                          modified the register.
12202
12203                          CC0 targets must be careful to maintain setter/user
12204                          pairs.  If we cannot delete the setter due to side
12205                          effects, mark the user with an UNUSED note instead
12206                          of deleting it.  */
12207
12208                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12209                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12210 #ifdef HAVE_cc0
12211                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12212                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12213                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12214 #endif
12215                           )
12216                         {
12217                           /* Move the notes and links of TEM elsewhere.
12218                              This might delete other dead insns recursively.
12219                              First set the pattern to something that won't use
12220                              any register.  */
12221                           rtx old_notes = REG_NOTES (tem);
12222
12223                           PATTERN (tem) = pc_rtx;
12224                           REG_NOTES (tem) = NULL;
12225
12226                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12227                                             NULL_RTX, NULL_RTX);
12228                           distribute_links (LOG_LINKS (tem));
12229
12230                           SET_INSN_DELETED (tem);
12231
12232 #ifdef HAVE_cc0
12233                           /* Delete the setter too.  */
12234                           if (cc0_setter)
12235                             {
12236                               PATTERN (cc0_setter) = pc_rtx;
12237                               old_notes = REG_NOTES (cc0_setter);
12238                               REG_NOTES (cc0_setter) = NULL;
12239
12240                               distribute_notes (old_notes, cc0_setter,
12241                                                 cc0_setter, NULL_RTX,
12242                                                 NULL_RTX, NULL_RTX);
12243                               distribute_links (LOG_LINKS (cc0_setter));
12244
12245                               SET_INSN_DELETED (cc0_setter);
12246                             }
12247 #endif
12248                         }
12249                       else
12250                         {
12251                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12252
12253                           /*  If there isn't already a REG_UNUSED note, put one
12254                               here.  Do not place a REG_DEAD note, even if
12255                               the register is also used here; that would not
12256                               match the algorithm used in lifetime analysis
12257                               and can cause the consistency check in the
12258                               scheduler to fail.  */
12259                           if (! find_regno_note (tem, REG_UNUSED,
12260                                                  REGNO (XEXP (note, 0))))
12261                             place = tem;
12262                           break;
12263                         }
12264                     }
12265                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12266                            || (CALL_P (tem)
12267                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12268                     {
12269                       place = tem;
12270
12271                       /* If we are doing a 3->2 combination, and we have a
12272                          register which formerly died in i3 and was not used
12273                          by i2, which now no longer dies in i3 and is used in
12274                          i2 but does not die in i2, and place is between i2
12275                          and i3, then we may need to move a link from place to
12276                          i2.  */
12277                       if (i2 && INSN_UID (place) <= max_uid_cuid
12278                           && INSN_CUID (place) > INSN_CUID (i2)
12279                           && from_insn
12280                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12281                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12282                         {
12283                           rtx links = LOG_LINKS (place);
12284                           LOG_LINKS (place) = 0;
12285                           distribute_links (links);
12286                         }
12287                       break;
12288                     }
12289
12290                   if (tem == BB_HEAD (bb))
12291                     break;
12292                 }
12293
12294               /* We haven't found an insn for the death note and it
12295                  is still a REG_DEAD note, but we have hit the beginning
12296                  of the block.  If the existing life info says the reg
12297                  was dead, there's nothing left to do.  Otherwise, we'll
12298                  need to do a global life update after combine.  */
12299               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12300                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12301                                       REGNO (XEXP (note, 0))))
12302                 SET_BIT (refresh_blocks, this_basic_block->index);
12303             }
12304
12305           /* If the register is set or already dead at PLACE, we needn't do
12306              anything with this note if it is still a REG_DEAD note.
12307              We check here if it is set at all, not if is it totally replaced,
12308              which is what `dead_or_set_p' checks, so also check for it being
12309              set partially.  */
12310
12311           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12312             {
12313               unsigned int regno = REGNO (XEXP (note, 0));
12314
12315               /* Similarly, if the instruction on which we want to place
12316                  the note is a noop, we'll need do a global live update
12317                  after we remove them in delete_noop_moves.  */
12318               if (noop_move_p (place))
12319                 SET_BIT (refresh_blocks, this_basic_block->index);
12320
12321               if (dead_or_set_p (place, XEXP (note, 0))
12322                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12323                 {
12324                   /* Unless the register previously died in PLACE, clear
12325                      last_death.  [I no longer understand why this is
12326                      being done.] */
12327                   if (reg_stat[regno].last_death != place)
12328                     reg_stat[regno].last_death = 0;
12329                   place = 0;
12330                 }
12331               else
12332                 reg_stat[regno].last_death = place;
12333
12334               /* If this is a death note for a hard reg that is occupying
12335                  multiple registers, ensure that we are still using all
12336                  parts of the object.  If we find a piece of the object
12337                  that is unused, we must arrange for an appropriate REG_DEAD
12338                  note to be added for it.  However, we can't just emit a USE
12339                  and tag the note to it, since the register might actually
12340                  be dead; so we recourse, and the recursive call then finds
12341                  the previous insn that used this register.  */
12342
12343               if (place && regno < FIRST_PSEUDO_REGISTER
12344                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12345                 {
12346                   unsigned int endregno
12347                     = regno + hard_regno_nregs[regno]
12348                                               [GET_MODE (XEXP (note, 0))];
12349                   int all_used = 1;
12350                   unsigned int i;
12351
12352                   for (i = regno; i < endregno; i++)
12353                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12354                          && ! find_regno_fusage (place, USE, i))
12355                         || dead_or_set_regno_p (place, i))
12356                       all_used = 0;
12357
12358                   if (! all_used)
12359                     {
12360                       /* Put only REG_DEAD notes for pieces that are
12361                          not already dead or set.  */
12362
12363                       for (i = regno; i < endregno;
12364                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12365                         {
12366                           rtx piece = regno_reg_rtx[i];
12367                           basic_block bb = this_basic_block;
12368
12369                           if (! dead_or_set_p (place, piece)
12370                               && ! reg_bitfield_target_p (piece,
12371                                                           PATTERN (place)))
12372                             {
12373                               rtx new_note
12374                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12375
12376                               distribute_notes (new_note, place, place,
12377                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12378                             }
12379                           else if (! refers_to_regno_p (i, i + 1,
12380                                                         PATTERN (place), 0)
12381                                    && ! find_regno_fusage (place, USE, i))
12382                             for (tem = PREV_INSN (place); ;
12383                                  tem = PREV_INSN (tem))
12384                               {
12385                                 if (! INSN_P (tem))
12386                                   {
12387                                     if (tem == BB_HEAD (bb))
12388                                       {
12389                                         SET_BIT (refresh_blocks,
12390                                                  this_basic_block->index);
12391                                         break;
12392                                       }
12393                                     continue;
12394                                   }
12395                                 if (dead_or_set_p (tem, piece)
12396                                     || reg_bitfield_target_p (piece,
12397                                                               PATTERN (tem)))
12398                                   {
12399                                     REG_NOTES (tem)
12400                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12401                                                            REG_NOTES (tem));
12402                                     break;
12403                                   }
12404                               }
12405
12406                         }
12407
12408                       place = 0;
12409                     }
12410                 }
12411             }
12412           break;
12413
12414         default:
12415           /* Any other notes should not be present at this point in the
12416              compilation.  */
12417           gcc_unreachable ();
12418         }
12419
12420       if (place)
12421         {
12422           XEXP (note, 1) = REG_NOTES (place);
12423           REG_NOTES (place) = note;
12424         }
12425       else if ((REG_NOTE_KIND (note) == REG_DEAD
12426                 || REG_NOTE_KIND (note) == REG_UNUSED)
12427                && REG_P (XEXP (note, 0)))
12428         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12429
12430       if (place2)
12431         {
12432           if ((REG_NOTE_KIND (note) == REG_DEAD
12433                || REG_NOTE_KIND (note) == REG_UNUSED)
12434               && REG_P (XEXP (note, 0)))
12435             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12436
12437           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12438                                                REG_NOTE_KIND (note),
12439                                                XEXP (note, 0),
12440                                                REG_NOTES (place2));
12441         }
12442     }
12443 }
12444 \f
12445 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12446    I3, I2, and I1 to new locations.  This is also called to add a link
12447    pointing at I3 when I3's destination is changed.  */
12448
12449 static void
12450 distribute_links (rtx links)
12451 {
12452   rtx link, next_link;
12453
12454   for (link = links; link; link = next_link)
12455     {
12456       rtx place = 0;
12457       rtx insn;
12458       rtx set, reg;
12459
12460       next_link = XEXP (link, 1);
12461
12462       /* If the insn that this link points to is a NOTE or isn't a single
12463          set, ignore it.  In the latter case, it isn't clear what we
12464          can do other than ignore the link, since we can't tell which
12465          register it was for.  Such links wouldn't be used by combine
12466          anyway.
12467
12468          It is not possible for the destination of the target of the link to
12469          have been changed by combine.  The only potential of this is if we
12470          replace I3, I2, and I1 by I3 and I2.  But in that case the
12471          destination of I2 also remains unchanged.  */
12472
12473       if (NOTE_P (XEXP (link, 0))
12474           || (set = single_set (XEXP (link, 0))) == 0)
12475         continue;
12476
12477       reg = SET_DEST (set);
12478       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12479              || GET_CODE (reg) == STRICT_LOW_PART)
12480         reg = XEXP (reg, 0);
12481
12482       /* A LOG_LINK is defined as being placed on the first insn that uses
12483          a register and points to the insn that sets the register.  Start
12484          searching at the next insn after the target of the link and stop
12485          when we reach a set of the register or the end of the basic block.
12486
12487          Note that this correctly handles the link that used to point from
12488          I3 to I2.  Also note that not much searching is typically done here
12489          since most links don't point very far away.  */
12490
12491       for (insn = NEXT_INSN (XEXP (link, 0));
12492            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12493                      || BB_HEAD (this_basic_block->next_bb) != insn));
12494            insn = NEXT_INSN (insn))
12495         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12496           {
12497             if (reg_referenced_p (reg, PATTERN (insn)))
12498               place = insn;
12499             break;
12500           }
12501         else if (CALL_P (insn)
12502                  && find_reg_fusage (insn, USE, reg))
12503           {
12504             place = insn;
12505             break;
12506           }
12507         else if (INSN_P (insn) && reg_set_p (reg, insn))
12508           break;
12509
12510       /* If we found a place to put the link, place it there unless there
12511          is already a link to the same insn as LINK at that point.  */
12512
12513       if (place)
12514         {
12515           rtx link2;
12516
12517           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12518             if (XEXP (link2, 0) == XEXP (link, 0))
12519               break;
12520
12521           if (link2 == 0)
12522             {
12523               XEXP (link, 1) = LOG_LINKS (place);
12524               LOG_LINKS (place) = link;
12525
12526               /* Set added_links_insn to the earliest insn we added a
12527                  link to.  */
12528               if (added_links_insn == 0
12529                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12530                 added_links_insn = place;
12531             }
12532         }
12533     }
12534 }
12535 \f
12536 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12537    Check whether the expression pointer to by LOC is a register or
12538    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12539    Otherwise return zero.  */
12540
12541 static int
12542 unmentioned_reg_p_1 (rtx *loc, void *expr)
12543 {
12544   rtx x = *loc;
12545
12546   if (x != NULL_RTX
12547       && (REG_P (x) || MEM_P (x))
12548       && ! reg_mentioned_p (x, (rtx) expr))
12549     return 1;
12550   return 0;
12551 }
12552
12553 /* Check for any register or memory mentioned in EQUIV that is not
12554    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12555    of EXPR where some registers may have been replaced by constants.  */
12556
12557 static bool
12558 unmentioned_reg_p (rtx equiv, rtx expr)
12559 {
12560   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12561 }
12562 \f
12563 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12564
12565 static int
12566 insn_cuid (rtx insn)
12567 {
12568   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12569          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12570     insn = NEXT_INSN (insn);
12571
12572   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12573
12574   return INSN_CUID (insn);
12575 }
12576 \f
12577 void
12578 dump_combine_stats (FILE *file)
12579 {
12580   fprintf
12581     (file,
12582      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12583      combine_attempts, combine_merges, combine_extras, combine_successes);
12584 }
12585
12586 void
12587 dump_combine_total_stats (FILE *file)
12588 {
12589   fprintf
12590     (file,
12591      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12592      total_attempts, total_merges, total_extras, total_successes);
12593 }
12594 \f
12595
12596 static bool
12597 gate_handle_combine (void)
12598 {
12599   return (optimize > 0);
12600 }
12601
12602 /* Try combining insns through substitution.  */
12603 static unsigned int
12604 rest_of_handle_combine (void)
12605 {
12606   int rebuild_jump_labels_after_combine
12607     = combine_instructions (get_insns (), max_reg_num ());
12608
12609   /* Combining insns may have turned an indirect jump into a
12610      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12611      instructions.  */
12612   if (rebuild_jump_labels_after_combine)
12613     {
12614       timevar_push (TV_JUMP);
12615       rebuild_jump_labels (get_insns ());
12616       timevar_pop (TV_JUMP);
12617
12618       delete_dead_jumptables ();
12619       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12620     }
12621   return 0;
12622 }
12623
12624 struct tree_opt_pass pass_combine =
12625 {
12626   "combine",                            /* name */
12627   gate_handle_combine,                  /* gate */
12628   rest_of_handle_combine,               /* execute */
12629   NULL,                                 /* sub */
12630   NULL,                                 /* next */
12631   0,                                    /* static_pass_number */
12632   TV_COMBINE,                           /* tv_id */
12633   0,                                    /* properties_required */
12634   0,                                    /* properties_provided */
12635   0,                                    /* properties_destroyed */
12636   0,                                    /* todo_flags_start */
12637   TODO_dump_func |
12638   TODO_ggc_collect,                     /* todo_flags_finish */
12639   'c'                                   /* letter */
12640 };
12641