| blob | ca00bbda10767a1216ac8eccaa959999d4177c94 |
1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
38 /* Include insn-config.h before expr.h so that HAVE_conditional_move
39 is properly defined. */
51 machine_mode *);
55 /* Debug facility for use in GDB. */
57 \f
58 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
59 the result of operation CODE applied to OP0 (and OP1 if it is a binary
60 operation). OP0_MODE is OP0's mode.
62 If the last insn does not set TARGET, don't do anything, but return 1.
64 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
65 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
66 try again, ensuring that TARGET is not one of the operands. */
68 static int
71 {
73 rtx set;
74 rtx note;
91 ;
93 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
94 a value changing in the insn, so the note would be invalid for CSE. */
97 {
101 {
102 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
103 over expanding it as temp = MEM op X, MEM = temp. If the target
104 supports MEM = MEM op X instructions, it is sometimes too hard
105 to reconstruct that form later, especially if X is also a memory,
106 and due to multiple occurrences of addresses the address might
107 be forced into register unnecessarily.
108 Note that not emitting the REG_EQUIV note might inhibit
109 CSE in some cases. */
118 }
120 }
127 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
134 {
143 {
149 else
153 }
154 /* FALLTHRU */
158 }
159 else
165 }
166 \f
167 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
168 for a widening operation would be. In most cases this would be OP0, but if
169 that's a constant it'll be VOIDmode, which isn't useful. */
171 static machine_mode
173 {
176 machine_mode result;
182 else
189 }
190 \f
191 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
192 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
193 not actually do a sign-extend or zero-extend, but can leave the
194 higher-order bits of the result rtx undefined, for example, in the case
195 of logical operations, but not right shifts. */
197 static rtx
200 {
201 rtx result;
202 scalar_int_mode int_mode;
204 /* If we don't have to extend and this is a constant, return it. */
208 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
209 extend since it will be more efficient to do so unless the signedness of
210 a promoted object differs from our extension. */
217 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
218 SUBREG. */
222 /* Otherwise, get an object of MODE, clobber it, and set the low-order
223 part to OP. */
229 }
230 \f
231 /* Expand vector widening operations.
233 There are two different classes of operations handled here:
234 1) Operations whose result is wider than all the arguments to the operation.
235 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
236 In this case OP0 and optionally OP1 would be initialized,
237 but WIDE_OP wouldn't (not relevant for this case).
238 2) Operations whose result is of the same size as the last argument to the
239 operation, but wider than all the other arguments to the operation.
240 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
241 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
243 E.g, when called to expand the following operations, this is how
244 the arguments will be initialized:
245 nops OP0 OP1 WIDE_OP
246 widening-sum 2 oprnd0 - oprnd1
247 widening-dot-product 3 oprnd0 oprnd1 oprnd2
248 widening-mult 2 oprnd0 oprnd1 -
249 type-promotion (vec-unpack) 1 oprnd0 - - */
251 rtx
254 {
258 optab widen_pattern_optab;
273 /* The sign is from the result type rather than operand's type
274 for these ops. */
275 widen_pattern_optab
283 {
284 /* For VEC_UNPACK_{LO,HI}_EXPR if the mode of op0 and result is
285 the same scalar mode for VECTOR_BOOLEAN_TYPE_P vectors, use
286 vec_unpacks_sbool_{lo,hi}_optab, so that we can pass in
287 the pattern number of elements in the wider vector. */
288 widen_pattern_optab
292 }
294 {
299 ;
301 {
303 /* Same as optab_vector_mixed_sign but flip the operands. */
305 }
308 else
311 widen_pattern_optab
313 }
314 else
315 widen_pattern_optab
321 tmode0);
322 else
329 {
333 }
335 /* The last operand is of a wider mode than the rest of the operands. */
339 {
343 }
354 }
356 /* Generate code to perform an operation specified by TERNARY_OPTAB
357 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
359 UNSIGNEDP is for the case where we have to widen the operands
360 to perform the operation. It says to use zero-extension.
362 If TARGET is nonzero, the value
363 is generated there, if it is convenient to do so.
364 In all cases an rtx is returned for the locus of the value;
365 this may or may not be TARGET. */
367 rtx
370 {
382 }
385 /* Like expand_binop, but return a constant rtx if the result can be
386 calculated at compile time. The arguments and return value are
387 otherwise the same as for expand_binop. */
389 rtx
393 {
395 {
400 }
403 }
405 /* Like simplify_expand_binop, but always put the result in TARGET.
406 Return true if the expansion succeeded. */
408 bool
412 {
420 }
422 /* Create a new vector value in VMODE with all elements set to OP. The
423 mode of OP must be the element mode of VMODE. If OP is a constant,
424 then the return value will be a constant. */
426 rtx
428 {
430 rtvec vec;
439 {
445 }
450 /* ??? If the target doesn't have a vec_init, then we have no easy way
451 of performing this operation. Most of this sort of generic support
452 is hidden away in the vector lowering support in gimple. */
465 }
467 /* This subroutine of expand_doubleword_shift handles the cases in which
468 the effective shift value is >= BITS_PER_WORD. The arguments and return
469 value are the same as for the parent routine, except that SUPERWORD_OP1
470 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
471 INTO_TARGET may be null if the caller has decided to calculate it. */
473 static bool
477 {
484 {
485 /* For a signed right shift, we must fill OUTOF_TARGET with copies
486 of the sign bit, otherwise we must fill it with zeros. */
489 else
495 }
497 }
499 /* This subroutine of expand_doubleword_shift handles the cases in which
500 the effective shift value is < BITS_PER_WORD. The arguments and return
501 value are the same as for the parent routine. */
503 static bool
509 {
516 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
517 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
518 the opposite direction to BINOPTAB. */
520 {
526 }
527 else
528 {
529 /* We must avoid shifting by BITS_PER_WORD bits since that is either
530 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
531 has unknown behavior. Do a single shift first, then shift by the
532 remainder. It's OK to use ~OP1 as the remainder if shift counts
533 are truncated to the mode size. */
537 {
538 tmp = immed_wide_int_const
542 }
543 else
544 {
549 }
550 }
558 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
559 so the result can go directly into INTO_TARGET if convenient. */
565 /* Now OR in the bits carried over from OUTOF_INPUT. */
570 /* Use a standard word_mode shift for the out-of half. */
577 }
580 /* Try implementing expand_doubleword_shift using conditional moves.
581 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
582 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
583 are the shift counts to use in the former and latter case. All other
584 arguments are the same as the parent routine. */
586 static bool
594 {
597 /* Put the superword version of the output into OUTOF_SUPERWORD and
598 INTO_SUPERWORD. */
601 {
602 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
603 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
608 }
609 else
610 {
616 }
618 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
625 /* Select between them. Do the INTO half first because INTO_SUPERWORD
626 might be the current value of OUTOF_TARGET. */
638 }
640 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
641 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
642 input operand; the shift moves bits in the direction OUTOF_INPUT->
643 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
644 of the target. OP1 is the shift count and OP1_MODE is its mode.
645 If OP1 is constant, it will have been truncated as appropriate
646 and is known to be nonzero.
648 If SHIFT_MASK is zero, the result of word shifts is undefined when the
649 shift count is outside the range [0, BITS_PER_WORD). This routine must
650 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
652 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
653 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
654 fill with zeros or sign bits as appropriate.
656 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
657 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
658 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
659 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
660 are undefined.
662 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
663 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
664 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
665 function wants to calculate it itself.
667 Return true if the shift could be successfully synthesized. */
669 static bool
675 {
679 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
680 fill the result with sign or zero bits as appropriate. If so, the value
681 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
682 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
683 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
685 This isn't worthwhile for constant shifts since the optimizers will
686 cope better with in-range shift counts. */
690 {
700 }
702 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
703 is true when the effective shift value is less than BITS_PER_WORD.
704 Set SUPERWORD_OP1 to the shift count that should be used to shift
705 OUTOF_INPUT into INTO_TARGET when the condition is false. */
708 {
709 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
710 is a subword shift count. */
716 }
717 else
718 {
719 /* Set CMP1 to OP1 - BITS_PER_WORD. */
725 }
729 /* If we can compute the condition at compile time, pick the
730 appropriate subroutine. */
733 {
738 else
743 }
745 /* Try using conditional moves to generate straight-line code. */
747 {
757 }
759 /* As a last resort, use branches to select the correct alternative. */
763 NO_DEFER_POP;
767 OK_DEFER_POP;
786 }
787 \f
788 /* Subroutine of expand_binop. Perform a double word multiplication of
789 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
790 as the target's word_mode. This function return NULL_RTX if anything
791 goes wrong, in which case it may have already emitted instructions
792 which need to be deleted.
794 If we want to multiply two two-word values and have normal and widening
795 multiplies of single-word values, we can do this with three smaller
796 multiplications.
798 The multiplication proceeds as follows:
799 _______________________
800 [__op0_high_|__op0_low__]
801 _______________________
802 * [__op1_high_|__op1_low__]
803 _______________________________________________
804 _______________________
805 (1) [__op0_low__*__op1_low__]
806 _______________________
807 (2a) [__op0_low__*__op1_high_]
808 _______________________
809 (2b) [__op0_high_*__op1_low__]
810 _______________________
811 (3) [__op0_high_*__op1_high_]
814 This gives a 4-word result. Since we are only interested in the
815 lower 2 words, partial result (3) and the upper words of (2a) and
816 (2b) don't need to be calculated. Hence (2a) and (2b) can be
817 calculated using non-widening multiplication.
819 (1), however, needs to be calculated with an unsigned widening
820 multiplication. If this operation is not directly supported we
821 try using a signed widening multiplication and adjust the result.
822 This adjustment works as follows:
824 If both operands are positive then no adjustment is needed.
826 If the operands have different signs, for example op0_low < 0 and
827 op1_low >= 0, the instruction treats the most significant bit of
828 op0_low as a sign bit instead of a bit with significance
829 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
830 with 2**BITS_PER_WORD - op0_low, and two's complements the
831 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
832 the result.
834 Similarly, if both operands are negative, we need to add
835 (op0_low + op1_low) * 2**BITS_PER_WORD.
837 We use a trick to adjust quickly. We logically shift op0_low right
838 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
839 op0_high (op1_high) before it is used to calculate 2b (2a). If no
840 logical shift exists, we do an arithmetic right shift and subtract
841 the 0 or -1. */
843 static rtx
846 {
858 /* If we're using an unsigned multiply to directly compute the product
859 of the low-order words of the operands and perform any required
860 adjustments of the operands, we begin by trying two more multiplications
861 and then computing the appropriate sum.
863 We have checked above that the required addition is provided.
864 Full-word addition will normally always succeed, especially if
865 it is provided at all, so we don't worry about its failure. The
866 multiplication may well fail, however, so we do handle that. */
869 {
870 /* ??? This could be done with emit_store_flag where available. */
876 else
877 {
884 }
888 }
895 /* OP0_HIGH should now be dead. */
898 {
899 /* ??? This could be done with emit_store_flag where available. */
905 else
906 {
913 }
917 }
924 /* OP1_HIGH should now be dead. */
932 /* *_widen_optab needs to determine operand mode, make sure at least
933 one operand has non-VOID mode. */
940 else
952 }
954 /* Subroutine of expand_binop. Optimize unsigned double-word OP0 % OP1 for
955 constant OP1. If for some bit in [BITS_PER_WORD / 2, BITS_PER_WORD] range
956 (prefer higher bits) ((1w << bit) % OP1) == 1, then the modulo can be
957 computed in word-mode as ((OP0 & (bit - 1)) + ((OP0 >> bit) & (bit - 1))
958 + (OP0 >> (2 * bit))) % OP1. Whether we need to sum 2, 3 or 4 values
959 depends on the bit value, if 2, then carry from the addition needs to be
960 added too, i.e. like:
961 sum += __builtin_add_overflow (low, high, &sum)
963 Optimize signed double-word OP0 % OP1 similarly, just apply some correction
964 factor to the sum before doing unsigned remainder, in the form of
965 sum += (((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & const);
966 then perform unsigned
967 remainder = sum % OP1;
968 and finally
969 remainder += ((signed) OP0 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1); */
971 static rtx
973 {
979 {
985 {
986 /* For signed modulo we need to add correction to the sum
987 and that might again overflow. */
1010 OPTAB_DIRECT);
1013 }
1014 else
1015 {
1016 /* Code below uses GEN_INT, so we need the masks to be representable
1017 in HOST_WIDE_INTs. */
1020 /* If op0 is e.g. -1 or -2 unsigned, then the 2 additions might
1021 overflow. Consider 64-bit -1ULL for word size 32, if we add
1022 0x7fffffffU + 0x7fffffffU + 3U, it wraps around to 1. */
1030 {
1031 /* For signed modulo, compute it as unsigned modulo of
1032 sum with a correction added to it if OP0 is negative,
1033 such that the result can be computed as unsigned
1034 remainder + ((OP1 >> (2 * BITS_PER_WORD - 1)) & (1 - OP1). */
1038 /* wmod2 == -wmod1. */
1041 {
1045 /* Now verify if the count sums can't overflow, and punt
1046 if they could. */
1057 mode);
1066 OPTAB_DIRECT);
1069 }
1070 }
1073 {
1087 OPTAB_DIRECT);
1092 else
1097 }
1099 {
1104 }
1105 }
1113 {
1115 {
1117 mode);
1123 }
1126 word_mode),
1134 }
1137 /* Punt if we need any library calls. */
1140 else
1146 }
1148 }
1150 /* Similarly to the above function, but compute both quotient and remainder.
1151 Quotient can be computed from the remainder as:
1152 rem = op0 % op1; // Handled using expand_doubleword_mod
1153 quot = (op0 - rem) * inv; // inv is multiplicative inverse of op1 modulo
1154 // 2 * BITS_PER_WORD
1156 We can also handle cases where op1 is a multiple of power of two constant
1157 and constant handled by expand_doubleword_mod.
1158 op11 = 1 << __builtin_ctz (op1);
1159 op12 = op1 / op11;
1160 rem1 = op0 % op12; // Handled using expand_doubleword_mod
1161 quot1 = (op0 - rem1) * inv; // inv is multiplicative inverse of op12 modulo
1162 // 2 * BITS_PER_WORD
1163 rem = (quot1 % op11) * op12 + rem1;
1164 quot = quot1 / op11; */
1166 rtx
1169 {
1172 /* Negative dividend should have been optimized into positive,
1173 similarly modulo by 1 and modulo by power of two is optimized
1174 differently too. */
1181 {
1185 }
1209 {
1232 }
1234 /* Punt if we need any library calls. */
1237 else
1245 }
1246 \f
1247 /* Wrapper around expand_binop which takes an rtx code to specify
1248 the operation to perform, not an optab pointer. All other
1249 arguments are the same. */
1250 rtx
1254 {
1259 }
1261 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1262 binop. Order them according to commutative_operand_precedence and, if
1263 possible, try to put TARGET or a pseudo first. */
1264 static bool
1266 {
1276 /* With equal precedence, both orders are ok, but it is better if the
1277 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1280 else
1282 }
1284 /* Return true if BINOPTAB implements a shift operation. */
1286 static bool
1288 {
1290 {
1302 }
1303 }
1305 /* Return true if BINOPTAB implements a commutative binary operation. */
1307 static bool
1309 {
1315 }
1317 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1318 optimizing, and if the operand is a constant that costs more than
1319 1 instruction, force the constant into a register and return that
1320 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1322 static rtx
1325 {
1329 && optimize
1333 {
1335 {
1339 }
1340 else
1343 }
1345 }
1347 /* Helper function for expand_binop: handle the case where there
1348 is an insn ICODE that directly implements the indicated operation.
1349 Returns null if this is not possible. */
1350 static rtx
1355 {
1365 /* If it is a commutative operator and the modes would match
1366 if we would swap the operands, we can save the conversions. */
1373 /* If we are optimizing, force expensive constants into a register. */
1377 else
1378 /* Shifts and rotates often use a different mode for op1 from op0;
1379 for VOIDmode constants we don't know the mode, so force it
1380 to be canonicalized using convert_modes. */
1383 /* In case the insn wants input operands in modes different from
1384 those of the actual operands, convert the operands. It would
1385 seem that we don't need to convert CONST_INTs, but we do, so
1386 that they're properly zero-extended, sign-extended or truncated
1387 for their mode. */
1391 {
1394 }
1399 {
1402 }
1404 /* If operation is commutative,
1405 try to make the first operand a register.
1406 Even better, try to make it the same as the target.
1407 Also try to make the last operand a constant. */
1412 /* Now, if insn's predicates don't allow our operands, put them into
1413 pseudo regs. */
1422 {
1423 /* The mode of the result is different then the mode of the
1424 arguments. */
1428 {
1431 }
1432 }
1433 else
1441 {
1442 /* If PAT is composed of more than one insn, try to add an appropriate
1443 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1444 operand, call expand_binop again, this time without a target. */
1449 {
1453 }
1457 }
1460 }
1462 /* Generate code to perform an operation specified by BINOPTAB
1463 on operands OP0 and OP1, with result having machine-mode MODE.
1465 UNSIGNEDP is for the case where we have to widen the operands
1466 to perform the operation. It says to use zero-extension.
1468 If TARGET is nonzero, the value
1469 is generated there, if it is convenient to do so.
1470 In all cases an rtx is returned for the locus of the value;
1471 this may or may not be TARGET. */
1473 rtx
1476 {
1477 enum optab_methods next_methods
1482 machine_mode wider_mode;
1483 scalar_int_mode int_mode;
1484 rtx libfunc;
1485 rtx temp;
1491 /* If subtracting an integer constant, convert this into an addition of
1492 the negated constant. */
1495 {
1498 }
1499 /* For shifts, constant invalid op1 might be expanded from different
1500 mode than MODE. As those are invalid, force them to a register
1501 to avoid further problems during expansion. */
1505 {
1508 }
1510 /* Record where to delete back to if we backtrack. */
1513 /* If we can do it with a three-operand insn, do so. */
1516 {
1518 {
1521 }
1522 else
1525 {
1530 }
1531 }
1533 /* If we were trying to rotate, and that didn't work, try rotating
1534 the other direction before falling back to shifts and bitwise-or. */
1540 {
1542 rtx newop1;
1549 else
1558 }
1560 /* If this is a multiply, see if we can do a widening operation that
1561 takes operands of this mode and makes a wider mode. */
1566 ? umul_widen_optab
1569 {
1570 /* *_widen_optab needs to determine operand mode, make sure at least
1571 one operand has non-VOID mode. */
1579 {
1583 else
1585 }
1586 }
1588 /* If this is a vector shift by a scalar, see if we can do a vector
1589 shift by a vector. If so, broadcast the scalar into a vector. */
1591 {
1607 {
1608 /* The scalar may have been extended to be too wide. Truncate
1609 it back to the proper size to fit in the broadcast vector. */
1619 {
1624 }
1625 }
1626 }
1628 /* Look for a wider mode of the same class for which we think we
1629 can open-code the operation. Check for a widening multiply at the
1630 wider mode as well. */
1635 {
1636 machine_mode next_mode;
1641 ? umul_widen_optab
1645 {
1649 /* For certain integer operations, we need not actually extend
1650 the narrow operands, as long as we will truncate
1651 the results to the same narrowness. */
1658 {
1665 }
1669 /* The second operand of a shift must always be extended. */
1676 {
1679 {
1684 }
1685 else
1687 }
1688 else
1690 }
1691 }
1693 /* If operation is commutative,
1694 try to make the first operand a register.
1695 Even better, try to make it the same as the target.
1696 Also try to make the last operand a constant. */
1701 /* These can be done a word at a time. */
1706 {
1710 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1711 won't be accurate, so use a new target. */
1722 /* Do the actual arithmetic. */
1730 {
1742 }
1748 {
1751 }
1752 }
1754 /* Synthesize double word shifts from single word shifts. */
1764 {
1766 scalar_int_mode op1_mode;
1774 /* Apply the truncation to constant shifts. */
1781 /* Make sure that this is a combination that expand_doubleword_shift
1782 can handle. See the comments there for details. */
1786 {
1792 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1793 won't be accurate, so use a new target. */
1804 /* OUTOF_* is the word we are shifting bits away from, and
1805 INTO_* is the word that we are shifting bits towards, thus
1806 they differ depending on the direction of the shift and
1807 WORDS_BIG_ENDIAN. */
1822 {
1828 }
1830 }
1831 }
1833 /* Synthesize double word rotates from single word shifts. */
1840 {
1844 rtx inter;
1847 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1848 won't be accurate, so use a new target. Do this also if target is not
1849 a REG, first because having a register instead may open optimization
1850 opportunities, and second because if target and op0 happen to be MEMs
1851 designating the same location, we would risk clobbering it too early
1852 in the code sequence we generate below. */
1866 /* OUTOF_* is the word we are shifting bits away from, and
1867 INTO_* is the word that we are shifting bits towards, thus
1868 they differ depending on the direction of the shift and
1869 WORDS_BIG_ENDIAN. */
1881 {
1882 /* This is just a word swap. */
1886 }
1887 else
1888 {
1900 {
1903 }
1904 else
1905 {
1908 }
1909 rtx first_shift_count_rtx
1911 rtx second_shift_count_rtx
1924 else
1944 }
1950 {
1953 }
1954 }
1956 /* These can be done a word at a time by propagating carries. */
1961 {
1968 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1969 value is one of those, use it. Otherwise, use 1 since it is the
1970 one easiest to get. */
1971 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1973 #else
1975 #endif
1977 /* Prepare the operands. */
1986 /* Indicate for flow that the entire target reg is being set. */
1990 /* Do the actual arithmetic. */
1992 {
1997 rtx x;
1999 /* Main add/subtract of the input operands. */
2007 {
2008 /* Store carry from main add/subtract. */
2015 }
2018 {
2019 rtx newx;
2021 /* Add/subtract previous carry to main result. */
2028 {
2029 /* Get out carry from adding/subtracting carry in. */
2037 /* Logical-ior the two poss. carry together. */
2043 }
2045 }
2046 else
2047 {
2050 }
2053 }
2056 {
2059 {
2066 target);
2067 }
2068 else
2072 }
2074 else
2076 }
2078 /* Attempt to synthesize double word multiplies using a sequence of word
2079 mode multiplications. We first attempt to generate a sequence using a
2080 more efficient unsigned widening multiply, and if that fails we then
2081 try using a signed widening multiply. */
2088 {
2092 {
2097 }
2102 {
2107 }
2110 {
2112 {
2114 product);
2116 REG_EQUAL,
2121 }
2123 }
2124 }
2126 /* Attempt to synthetize double word modulo by constant divisor. */
2131 && optimize
2137 int_mode) == CODE_FOR_nothing
2141 {
2147 else
2148 {
2150 binoptab == umod_optab
2156 }
2158 {
2160 {
2162 res);
2167 }
2169 }
2170 else
2172 }
2174 /* It can't be open-coded in this mode.
2175 Use a library call if one is available and caller says that's ok. */
2180 {
2184 rtx value;
2189 {
2191 /* Specify unsigned here,
2192 since negative shift counts are meaningless. */
2194 }
2200 /* Pass 1 for NO_QUEUE so we don't lose any increments
2201 if the libcall is cse'd or moved. */
2212 trapv ? NULL_RTX
2217 }
2221 /* It can't be done in this mode. Can we do it in a wider mode? */
2225 {
2226 /* Caller says, don't even try. */
2229 }
2231 /* Compute the value of METHODS to pass to recursive calls.
2232 Don't allow widening to be tried recursively. */
2236 /* Look for a wider mode of the same class for which it appears we can do
2237 the operation. */
2240 {
2241 /* This code doesn't make sense for conversion optabs, since we
2242 wouldn't then want to extend the operands to be the same size
2243 as the result. */
2246 {
2250 {
2254 /* For certain integer operations, we need not actually extend
2255 the narrow operands, as long as we will truncate
2256 the results to the same narrowness. */
2268 /* The second operand of a shift must always be extended. */
2275 {
2278 {
2283 }
2284 else
2286 }
2287 else
2289 }
2290 }
2291 }
2295 }
2296 \f
2297 /* Expand a binary operator which has both signed and unsigned forms.
2298 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2299 signed operations.
2301 If we widen unsigned operands, we may use a signed wider operation instead
2302 of an unsigned wider operation, since the result would be the same. */
2304 rtx
2308 {
2309 rtx temp;
2313 /* Do it without widening, if possible. */
2319 /* Try widening to a signed int. Disable any direct use of any
2320 signed insn in the current mode. */
2326 /* For unsigned operands, try widening to an unsigned int. */
2333 /* Use the right width libcall if that exists. */
2339 /* Must widen and use a libcall, use either signed or unsigned. */
2346 egress:
2347 /* Undo the fiddling above. */
2351 }
2352 \f
2353 /* Generate code to perform an operation specified by UNOPPTAB
2354 on operand OP0, with two results to TARG0 and TARG1.
2355 We assume that the order of the operands for the instruction
2356 is TARG0, TARG1, OP0.
2358 Either TARG0 or TARG1 may be zero, but what that means is that
2359 the result is not actually wanted. We will generate it into
2360 a dummy pseudo-reg and discard it. They may not both be zero.
2362 Returns 1 if this operation can be performed; 0 if not. */
2364 int
2367 {
2370 machine_mode wider_mode;
2381 /* Record where to go back to if we fail. */
2385 {
2394 }
2396 /* It can't be done in this mode. Can we do it in a wider mode? */
2399 {
2401 {
2403 {
2409 {
2413 }
2414 else
2416 }
2417 }
2418 }
2422 }
2423 \f
2424 /* Generate code to perform an operation specified by BINOPTAB
2425 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2426 We assume that the order of the operands for the instruction
2427 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2428 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2430 Either TARG0 or TARG1 may be zero, but what that means is that
2431 the result is not actually wanted. We will generate it into
2432 a dummy pseudo-reg and discard it. They may not both be zero.
2434 Returns 1 if this operation can be performed; 0 if not. */
2436 int
2439 {
2442 machine_mode wider_mode;
2453 /* Record where to go back to if we fail. */
2457 {
2464 /* If we are optimizing, force expensive constants into a register. */
2475 }
2477 /* It can't be done in this mode. Can we do it in a wider mode? */
2480 {
2482 {
2484 {
2492 {
2496 }
2497 else
2499 }
2500 }
2501 }
2505 }
2507 /* Expand the two-valued library call indicated by BINOPTAB, but
2508 preserve only one of the values. If TARG0 is non-NULL, the first
2509 value is placed into TARG0; otherwise the second value is placed
2510 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2511 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2512 This routine assumes that the value returned by the library call is
2513 as if the return value was of an integral mode twice as wide as the
2514 mode of OP0. Returns 1 if the call was successful. */
2516 bool
2519 {
2520 machine_mode mode;
2521 machine_mode libval_mode;
2522 rtx libval;
2524 rtx libfunc;
2526 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2534 /* The value returned by the library function will have twice as
2535 many bits as the nominal MODE. */
2539 libval_mode,
2542 /* Get the part of VAL containing the value that we want. */
2547 /* Move the into the desired location. */
2552 }
2554 \f
2555 /* Wrapper around expand_unop which takes an rtx code to specify
2556 the operation to perform, not an optab pointer. All other
2557 arguments are the same. */
2558 rtx
2561 {
2566 }
2568 /* Try calculating
2569 (clz:narrow x)
2570 as
2571 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2573 A similar operation can be used for clrsb. UNOPTAB says which operation
2574 we are trying to expand. */
2575 static rtx
2577 {
2578 opt_scalar_int_mode wider_mode_iter;
2580 {
2583 {
2596 temp = expand_binop
2600 wider_mode),
2606 }
2607 }
2609 }
2611 /* Attempt to emit (clrsb:mode op0) as
2612 (plus:mode (clz:mode (xor:mode op0 (ashr:mode op0 (const_int prec-1))))
2613 (const_int -1))
2614 if CLZ_DEFINED_VALUE_AT_ZERO (mode, val) is 2 and val is prec,
2615 or as
2616 (clz:mode (ior:mode (xor:mode (ashl:mode op0 (const_int 1))
2617 (ashr:mode op0 (const_int prec-1)))
2618 (const_int 1)))
2619 otherwise. */
2621 static rtx
2623 {
2633 else
2638 {
2642 {
2643 fail:
2646 }
2647 }
2656 OPTAB_DIRECT);
2661 {
2666 }
2672 {
2677 }
2685 }
2687 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2688 quantities, choosing which based on whether the high word is nonzero. */
2689 static rtx
2691 {
2700 /* If we were not given a target, use a word_mode register, not a
2701 'mode' register. The result will fit, and nobody is expecting
2702 anything bigger (the return type of __builtin_clz* is int). */
2706 /* In any case, write to a word_mode scratch in both branches of the
2707 conditional, so we can ensure there is a single move insn setting
2708 'target' to tag a REG_EQUAL note on. */
2713 /* If the high word is not equal to zero,
2714 then clz of the full value is clz of the high word. */
2728 /* Else clz of the full value is clz of the low word plus the number
2729 of bits in the high word. */
2753 fail:
2756 }
2758 /* Try calculating popcount of a double-word quantity as two popcount's of
2759 word-sized quantities and summing up the results. */
2760 static rtx
2762 {
2775 {
2778 }
2780 /* If we were not given a target, use a word_mode register, not a
2781 'mode' register. The result will fit, and nobody is expecting
2782 anything bigger (the return type of __builtin_popcount* is int). */
2794 }
2796 /* Try calculating
2797 (parity:wide x)
2798 as
2799 (parity:narrow (low (x) ^ high (x))) */
2800 static rtx
2802 {
2808 }
2810 /* Try calculating
2811 (bswap:narrow x)
2812 as
2813 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2814 static rtx
2816 {
2817 rtx x;
2819 opt_scalar_int_mode wider_mode_iter;
2844 {
2848 }
2849 else
2853 }
2855 /* Try calculating bswap as two bswaps of two word-sized operands. */
2857 static rtx
2859 {
2875 }
2877 /* Try calculating (parity x) as (and (popcount x) 1), where
2878 popcount can also be done in a wider mode. */
2879 static rtx
2881 {
2883 opt_scalar_int_mode wider_mode_iter;
2885 {
2888 {
2905 {
2909 else
2911 }
2912 else
2914 }
2915 }
2917 }
2919 /* Try calculating ctz(x) as K - clz(x & -x) ,
2920 where K is GET_MODE_PRECISION(mode) - 1.
2922 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2923 don't have to worry about what the hardware does in that case. (If
2924 the clz instruction produces the usual value at 0, which is K, the
2925 result of this code sequence will be -1; expand_ffs, below, relies
2926 on this. It might be nice to have it be K instead, for consistency
2927 with the (very few) processors that provide a ctz with a defined
2928 value, but that would take one more instruction, and it would be
2929 less convenient for expand_ffs anyway. */
2931 static rtx
2933 {
2935 rtx temp;
2954 {
2957 }
2965 }
2968 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2969 else with the sequence used by expand_clz.
2971 The ffs builtin promises to return zero for a zero value and ctz/clz
2972 may have an undefined value in that case. If they do not give us a
2973 convenient value, we have to generate a test and branch. */
2974 static rtx
2976 {
2979 rtx temp;
2983 {
2991 }
2993 {
3000 {
3003 }
3004 }
3005 else
3010 else
3011 {
3012 /* We don't try to do anything clever with the situation found
3013 on some processors (eg Alpha) where ctz(0:mode) ==
3014 bitsize(mode). If someone can think of a way to send N to -1
3015 and leave alone all values in the range 0..N-1 (where N is a
3016 power of two), cheaper than this test-and-branch, please add it.
3018 The test-and-branch is done after the operation itself, in case
3019 the operation sets condition codes that can be recycled for this.
3020 (This is true on i386, for instance.) */
3028 }
3030 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
3031 to produce a value in the range 0..bitsize. */
3044 fail:
3047 }
3049 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
3050 conditions, VAL may already be a SUBREG against which we cannot generate
3051 a further SUBREG. In this case, we expect forcing the value into a
3052 register will work around the situation. */
3054 static rtx
3056 machine_mode imode)
3057 {
3058 rtx ret;
3061 {
3065 }
3067 }
3069 /* Expand a floating point absolute value or negation operation via a
3070 logical operation on the sign bit. */
3072 static rtx
3075 {
3078 scalar_int_mode imode;
3079 rtx temp;
3082 /* The format has to have a simple sign bit. */
3091 /* Don't create negative zeros if the format doesn't support them. */
3096 {
3101 }
3102 else
3103 {
3108 else
3112 }
3125 {
3129 {
3134 {
3136 op0_piece,
3141 }
3142 else
3144 }
3150 }
3151 else
3152 {
3161 target);
3162 }
3165 }
3167 /* As expand_unop, but will fail rather than attempt the operation in a
3168 different mode or with a libcall. */
3169 static rtx
3172 {
3174 {
3184 {
3189 {
3192 }
3197 }
3198 }
3200 }
3202 /* Generate code to perform an operation specified by UNOPTAB
3203 on operand OP0, with result having machine-mode MODE.
3205 UNSIGNEDP is for the case where we have to widen the operands
3206 to perform the operation. It says to use zero-extension.
3208 If TARGET is nonzero, the value
3209 is generated there, if it is convenient to do so.
3210 In all cases an rtx is returned for the locus of the value;
3211 this may or may not be TARGET. */
3213 rtx
3216 {
3218 machine_mode wider_mode;
3219 scalar_int_mode int_mode;
3220 scalar_float_mode float_mode;
3221 rtx temp;
3222 rtx libfunc;
3228 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3230 /* Widening (or narrowing) clz needs special treatment. */
3232 {
3234 {
3241 {
3245 }
3246 }
3249 }
3252 {
3254 {
3261 }
3263 }
3270 {
3274 }
3282 {
3286 }
3288 /* Widening (or narrowing) bswap needs special treatment. */
3290 {
3291 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3292 or ROTATERT. First try these directly; if this fails, then try the
3293 obvious pair of shifts with allowed widening, as this will probably
3294 be always more efficient than the other fallback methods. */
3296 {
3301 {
3307 }
3310 {
3316 }
3327 {
3332 }
3335 }
3338 {
3343 /* We do not provide a 128-bit bswap in libgcc so force the use of
3344 a double bswap for 64-bit targets. */
3348 {
3352 }
3353 }
3356 }
3360 {
3362 {
3366 /* For certain operations, we need not actually extend
3367 the narrow operand, as long as we will truncate the
3368 results to the same narrowness. */
3376 unsignedp);
3379 {
3382 {
3387 }
3388 else
3390 }
3391 else
3393 }
3394 }
3396 /* These can be done a word at a time. */
3401 {
3413 /* Do the actual arithmetic. */
3415 {
3423 }
3430 }
3432 /* Emit ~op0 as op0 ^ -1. */
3436 {
3441 }
3444 {
3445 /* Try negating floating point values by flipping the sign bit. */
3447 {
3451 }
3453 /* If there is no negation pattern, and we have no negative zero,
3454 try subtracting from zero. */
3456 {
3463 }
3464 }
3466 /* Try calculating parity (x) as popcount (x) % 2. */
3468 {
3472 }
3474 /* Try implementing ffs (x) in terms of clz (x). */
3476 {
3480 }
3482 /* Try implementing ctz (x) in terms of clz (x). */
3484 {
3488 }
3490 try_libcall:
3491 /* Now try a library call in this mode. */
3494 {
3496 rtx value;
3497 rtx eq_value;
3500 /* All of these functions return small values. Thus we choose to
3501 have them return something that isn't a double-word. */
3505 outmode
3511 /* Pass 1 for NO_QUEUE so we don't lose any increments
3512 if the libcall is cse'd or moved. */
3522 else
3523 {
3530 }
3534 }
3536 /* It can't be done in this mode. Can we do it in a wider mode? */
3539 {
3541 {
3544 {
3548 /* For certain operations, we need not actually extend
3549 the narrow operand, as long as we will truncate the
3550 results to the same narrowness. */
3558 unsignedp);
3560 /* If we are generating clz using wider mode, adjust the
3561 result. Similarly for clrsb. */
3564 {
3565 scalar_int_mode wider_int_mode
3568 temp = expand_binop
3572 wider_int_mode),
3574 }
3576 /* Likewise for bswap. */
3578 {
3579 scalar_int_mode wider_int_mode
3591 }
3594 {
3596 {
3601 }
3602 else
3604 }
3605 else
3607 }
3608 }
3609 }
3611 /* One final attempt at implementing negation via subtraction,
3612 this time allowing widening of the operand. */
3614 {
3615 rtx temp;
3622 }
3625 }
3626 \f
3627 /* Emit code to compute the absolute value of OP0, with result to
3628 TARGET if convenient. (TARGET may be 0.) The return value says
3629 where the result actually is to be found.
3631 MODE is the mode of the operand; the mode of the result is
3632 different but can be deduced from MODE.
3634 */
3636 rtx
3639 {
3640 rtx temp;
3646 /* First try to do it with a special abs instruction. */
3652 /* For floating point modes, try clearing the sign bit. */
3653 scalar_float_mode float_mode;
3655 {
3659 }
3661 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3664 {
3671 OPTAB_WIDEN);
3677 }
3679 /* If this machine has expensive jumps, we can do integer absolute
3680 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3681 where W is the width of MODE. */
3683 scalar_int_mode int_mode;
3687 {
3693 OPTAB_LIB_WIDEN);
3701 }
3704 }
3706 rtx
3709 {
3710 rtx temp;
3721 /* If that does not win, use conditional jump and negate. */
3723 /* It is safe to use the target if it is the same
3724 as the source if this is also a pseudo register */
3738 NO_DEFER_POP;
3749 OK_DEFER_POP;
3751 }
3753 /* Emit code to compute the one's complement absolute value of OP0
3754 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3755 (TARGET may be NULL_RTX.) The return value says where the result
3756 actually is to be found.
3758 MODE is the mode of the operand; the mode of the result is
3759 different but can be deduced from MODE. */
3761 rtx
3763 {
3764 rtx temp;
3766 /* Not applicable for floating point modes. */
3770 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3772 {
3778 OPTAB_WIDEN);
3784 }
3786 /* If this machine has expensive jumps, we can do one's complement
3787 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3789 scalar_int_mode int_mode;
3793 {
3799 OPTAB_LIB_WIDEN);
3803 }
3806 }
3808 /* A subroutine of expand_copysign, perform the copysign operation using the
3809 abs and neg primitives advertised to exist on the target. The assumption
3810 is that we have a split register file, and leaving op0 in fp registers,
3811 and not playing with subregs so much, will help the register allocator. */
3813 static rtx
3816 {
3817 scalar_int_mode imode;
3819 rtx sign;
3825 /* Check if the back end provides an insn that handles signbit for the
3826 argument's mode. */
3829 {
3833 }
3834 else
3835 {
3837 {
3841 }
3842 else
3843 {
3849 else
3853 }
3859 }
3862 {
3867 }
3868 else
3869 {
3872 else
3874 }
3881 else
3889 }
3892 /* A subroutine of expand_copysign, perform the entire copysign operation
3893 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3894 is true if op0 is known to have its sign bit clear. */
3896 static rtx
3899 {
3900 scalar_int_mode imode;
3902 rtx temp;
3906 {
3911 }
3912 else
3913 {
3918 else
3922 }
3935 {
3939 {
3944 {
3946 op0_piece
3959 }
3960 else
3962 }
3968 }
3969 else
3970 {
3984 }
3987 }
3989 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3990 scalar floating point mode. Return NULL if we do not know how to
3991 expand the operation inline. */
3993 rtx
3995 {
3996 scalar_float_mode mode;
3999 rtx temp;
4004 /* First try to do it with a special instruction. */
4016 {
4020 }
4026 {
4031 }
4037 }
4038 \f
4039 /* Generate an instruction whose insn-code is INSN_CODE,
4040 with two operands: an output TARGET and an input OP0.
4041 TARGET *must* be nonzero, and the output is always stored there.
4042 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4043 the value that is stored into TARGET.
4045 Return false if expansion failed. */
4047 bool
4050 {
4070 }
4071 /* Generate an instruction whose insn-code is INSN_CODE,
4072 with two operands: an output TARGET and an input OP0.
4073 TARGET *must* be nonzero, and the output is always stored there.
4074 CODE is an rtx code such that (CODE OP0) is an rtx that describes
4075 the value that is stored into TARGET. */
4077 void
4079 {
4082 }
4083 \f
4084 struct no_conflict_data
4085 {
4086 rtx target;
4089 };
4091 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
4092 the currently examined clobber / store has to stay in the list of
4093 insns that constitute the actual libcall block. */
4094 static void
4096 {
4099 /* If this inns directly contributes to setting the target, it must stay. */
4102 /* If we haven't committed to keeping any other insns in the list yet,
4103 there is nothing more to check. */
4106 /* If this insn sets / clobbers a register that feeds one of the insns
4107 already in the list, this insn has to stay too. */
4111 /* Likewise if this insn depends on a register set by a previous
4112 insn in the list, or if it sets a result (presumably a hard
4113 register) that is set or clobbered by a previous insn.
4114 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
4115 SET_DEST perform the former check on the address, and the latter
4116 check on the MEM. */
4123 }
4125 \f
4126 /* Emit code to make a call to a constant function or a library call.
4128 INSNS is a list containing all insns emitted in the call.
4129 These insns leave the result in RESULT. Our block is to copy RESULT
4130 to TARGET, which is logically equivalent to EQUIV.
4132 We first emit any insns that set a pseudo on the assumption that these are
4133 loading constants into registers; doing so allows them to be safely cse'ed
4134 between blocks. Then we emit all the other insns in the block, followed by
4135 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
4136 note with an operand of EQUIV. */
4138 static void
4141 {
4145 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
4146 into a MEM later. Protect the libcall block from this change. */
4150 /* If we're using non-call exceptions, a libcall corresponding to an
4151 operation that may trap may also trap. */
4152 /* ??? See the comment in front of make_reg_eh_region_note. */
4155 {
4158 {
4161 {
4165 }
4166 }
4167 }
4168 else
4169 {
4170 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
4171 reg note to indicate that this call cannot throw or execute a nonlocal
4172 goto (unless there is already a REG_EH_REGION note, in which case
4173 we update it). */
4177 }
4179 /* First emit all insns that set pseudos. Remove them from the list as
4180 we go. Avoid insns that set pseudos which were referenced in previous
4181 insns. These can be generated by move_by_pieces, for example,
4182 to update an address. Similarly, avoid insns that reference things
4183 set in previous insns. */
4186 {
4193 {
4202 {
4205 else
4212 }
4213 }
4215 /* Some ports use a loop to copy large arguments onto the stack.
4216 Don't move anything outside such a loop. */
4219 }
4221 /* Write the remaining insns followed by the final copy. */
4223 {
4227 }
4235 }
4237 void
4239 {
4241 }
4242 \f
4243 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
4244 PURPOSE describes how this comparison will be used. CODE is the rtx
4245 comparison code we will be using.
4247 ??? Actually, CODE is slightly weaker than that. A target is still
4248 required to implement all of the normal bcc operations, but not
4249 required to implement all (or any) of the unordered bcc operations. */
4251 int
4254 {
4255 rtx test;
4257 do
4258 {
4275 }
4279 }
4281 /* Return whether RTL code CODE corresponds to an unsigned optab. */
4283 static bool
4285 {
4287 }
4289 /* Return whether the backend-emitted comparison for code CODE, comparing
4290 operands of mode VALUE_MODE and producing a result with MASK_MODE, matches
4291 operand OPNO of pattern ICODE. */
4293 static bool
4296 machine_mode value_mode)
4297 {
4302 }
4304 /* Return whether the backend can emit a vector comparison (vec_cmp/vec_cmpu)
4305 for code CODE, comparing operands of mode VALUE_MODE and producing a result
4306 with MASK_MODE. */
4308 bool
4310 machine_mode mask_mode)
4311 {
4312 enum insn_code icode
4318 }
4320 /* Return whether the backend can emit a vector comparison (vcond/vcondu) for
4321 code CODE, comparing operands of mode CMP_OP_MODE and producing a result
4322 with VALUE_MODE. */
4324 bool
4326 machine_mode cmp_op_mode)
4327 {
4328 enum insn_code icode
4334 }
4336 /* Return whether the backend can emit vector set instructions for inserting
4337 element into vector at variable index position. */
4339 bool
4341 {
4355 }
4357 /* This function is called when we are going to emit a compare instruction that
4358 compares the values found in X and Y, using the rtl operator COMPARISON.
4360 If they have mode BLKmode, then SIZE specifies the size of both operands.
4362 UNSIGNEDP nonzero says that the operands are unsigned;
4363 this matters if they need to be widened (as given by METHODS).
4365 *PTEST is where the resulting comparison RTX is returned or NULL_RTX
4366 if we failed to produce one.
4368 *PMODE is the mode of the inputs (in case they are const_int).
4370 This function performs all the setup necessary so that the caller only has
4371 to emit a single comparison insn. This setup can involve doing a BLKmode
4372 comparison or emitting a library call to perform the comparison if no insn
4373 is available to handle it.
4374 The values which are passed in through pointers can be modified; the caller
4375 should perform the comparison on the modified values. Constant
4376 comparisons must have already been folded. */
4378 static void
4382 {
4385 machine_mode cmp_mode;
4388 /* The other methods are not needed. */
4395 /* If we are optimizing, force expensive constants into a register. */
4406 /* Don't let both operands fail to indicate the mode. */
4412 /* Handle all BLKmode compares. */
4415 {
4416 machine_mode result_mode;
4418 rtx result;
4419 rtx opalign
4424 /* Try to use a memory block compare insn - either cmpstr
4425 or cmpmem will do. */
4426 opt_scalar_int_mode cmp_mode_iter;
4428 {
4438 /* Must make sure the size fits the insn's mode. */
4453 }
4458 /* Otherwise call a library function. */
4466 }
4468 /* Don't allow operands to the compare to trap, as that can put the
4469 compare and branch in different basic blocks. */
4471 {
4476 }
4479 {
4486 }
4491 {
4496 {
4503 {
4509 }
4511 }
4515 }
4521 {
4522 /* Small trick if UNORDERED isn't implemented by the hardware. */
4524 {
4529 }
4532 }
4533 else
4534 {
4535 rtx result;
4536 machine_mode ret_mode;
4538 /* Handle a libcall just for the mode we are using. */
4542 /* If we want unsigned, and this mode has a distinct unsigned
4543 comparison routine, use that. */
4545 {
4549 }
4555 /* There are two kinds of comparison routines. Biased routines
4556 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4557 of gcc expect that the comparison operation is equivalent
4558 to the modified comparison. For signed comparisons compare the
4559 result against 1 in the biased case, and zero in the unbiased
4560 case. For unsigned comparisons always compare against 1 after
4561 biasing the unbiased result by adding 1. This gives us a way to
4562 represent LTU.
4563 The comparisons in the fixed-point helper library are always
4564 biased. */
4569 {
4572 else
4574 }
4579 }
4583 fail:
4585 }
4587 /* Before emitting an insn with code ICODE, make sure that X, which is going
4588 to be used for operand OPNUM of the insn, is converted from mode MODE to
4589 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4590 that it is accepted by the operand predicate. Return the new value. */
4592 rtx
4595 {
4600 {
4607 }
4610 }
4612 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4613 we can do the branch. */
4615 static void
4617 profile_probability prob)
4618 {
4619 machine_mode optab_mode;
4634 && insn
4639 }
4641 /* Generate code to compare X with Y so that the condition codes are
4642 set and to jump to LABEL if the condition is true. If X is a
4643 constant and Y is not a constant, then the comparison is swapped to
4644 ensure that the comparison RTL has the canonical form.
4646 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4647 need to be widened. UNSIGNEDP is also used to select the proper
4648 branch condition code.
4650 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4652 MODE is the mode of the inputs (in case they are const_int).
4654 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4655 It will be potentially converted into an unsigned variant based on
4656 UNSIGNEDP to select a proper jump instruction.
4658 PROB is the probability of jumping to LABEL. */
4660 void
4663 profile_probability prob)
4664 {
4666 rtx test;
4668 /* Swap operands and condition to ensure canonical RTL. */
4671 {
4674 }
4676 /* If OP0 is still a constant, then both X and Y must be constants
4677 or the opposite comparison is not supported. Force X into a register
4678 to create canonical RTL. */
4688 }
4690 \f
4691 /* Emit a library call comparison between floating point X and Y.
4692 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4694 static void
4697 {
4701 machine_mode mode;
4710 {
4717 {
4721 }
4725 {
4729 }
4730 }
4735 {
4738 }
4740 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4741 the RTL. The allows the RTL optimizers to delete the libcall if the
4742 condition can be determined at compile-time. */
4745 {
4748 }
4749 else
4750 {
4752 {
4785 }
4786 }
4789 {
4794 }
4795 else
4796 {
4801 }
4816 else
4820 }
4821 \f
4822 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4824 void
4826 {
4829 else
4830 {
4835 }
4836 }
4837 \f
4839 /* Emit a conditional move instruction if the machine supports one for that
4840 condition and machine mode.
4842 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4843 the mode to use should they be constants. If it is VOIDmode, they cannot
4844 both be constants.
4846 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4847 should be stored there. MODE is the mode to use should they be constants.
4848 If it is VOIDmode, they cannot both be constants.
4850 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4851 is not supported. */
4853 rtx
4857 {
4858 rtx comparison;
4863 /* If the two source operands are identical, that's just a move. */
4866 {
4872 }
4874 /* If one operand is constant, make it the second one. Only do this
4875 if the other operand is not constant as well. */
4878 {
4881 }
4883 /* get_condition will prefer to generate LT and GT even if the old
4884 comparison was against zero, so undo that canonicalization here since
4885 comparisons against zero are cheaper. */
4899 {
4903 }
4917 {
4921 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4922 punt and let the caller figure out how best to deal with this
4923 situation. */
4925 {
4926 saved_pending_stack_adjust save;
4935 {
4943 {
4947 }
4948 }
4951 }
4956 /* If the preferred op2/op3 order is not usable, retry with other
4957 operand order, perhaps it will expand successfully. */
4961 NULL))
4964 else
4967 }
4968 }
4971 /* Emit a conditional negate or bitwise complement using the
4972 negcc or notcc optabs if available. Return NULL_RTX if such operations
4973 are not available. Otherwise return the RTX holding the result.
4974 TARGET is the desired destination of the result. COMP is the comparison
4975 on which to negate. If COND is true move into TARGET the negation
4976 or bitwise complement of OP1. Otherwise move OP2 into TARGET.
4977 CODE is either NEG or NOT. MODE is the machine mode in which the
4978 operation is performed. */
4980 rtx
4983 rtx op2)
4984 {
4990 else
5010 {
5015 }
5018 }
5020 /* Emit a conditional addition instruction if the machine supports one for that
5021 condition and machine mode.
5023 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
5024 the mode to use should they be constants. If it is VOIDmode, they cannot
5025 both be constants.
5027 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
5028 should be stored there. MODE is the mode to use should they be constants.
5029 If it is VOIDmode, they cannot both be constants.
5031 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
5032 is not supported. */
5034 rtx
5038 {
5039 rtx comparison;
5043 /* If one operand is constant, make it the second one. Only do this
5044 if the other operand is not constant as well. */
5047 {
5050 }
5052 /* get_condition will prefer to generate LT and GT even if the old
5053 comparison was against zero, so undo that canonicalization here since
5054 comparisons against zero are cheaper. */
5077 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
5078 return NULL and let the caller figure out how best to deal with this
5079 situation. */
5089 {
5097 {
5101 }
5102 }
5105 }
5106 \f
5107 /* These functions attempt to generate an insn body, rather than
5108 emitting the insn, but if the gen function already emits them, we
5109 make no attempt to turn them back into naked patterns. */
5111 /* Generate and return an insn body to add Y to X. */
5113 rtx_insn *
5115 {
5123 }
5125 /* Generate and return an insn body to add r1 and c,
5126 storing the result in r0. */
5128 rtx_insn *
5130 {
5140 }
5142 int
5144 {
5160 }
5162 /* Generate and return an insn body to add Y to X. */
5164 rtx_insn *
5166 {
5174 }
5176 /* Return true if the target implements an addptr pattern and X, Y,
5177 and Z are valid for the pattern predicates. */
5179 int
5181 {
5197 }
5199 /* Generate and return an insn body to subtract Y from X. */
5201 rtx_insn *
5203 {
5211 }
5213 /* Generate and return an insn body to subtract r1 and c,
5214 storing the result in r0. */
5216 rtx_insn *
5218 {
5228 }
5230 int
5232 {
5248 }
5249 \f
5250 /* Generate the body of an insn to extend Y (with mode MFROM)
5251 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
5253 rtx_insn *
5256 {
5259 }
5260 \f
5261 /* Generate code to convert FROM to floating point
5262 and store in TO. FROM must be fixed point and not VOIDmode.
5263 UNSIGNEDP nonzero means regard FROM as unsigned.
5264 Normally this is done by correcting the final value
5265 if it is negative. */
5267 void
5269 {
5276 /* Crash now, because we won't be able to decide which mode to use. */
5279 /* Look for an insn to do the conversion. Do it in the specified
5280 modes if possible; otherwise convert either input, output or both to
5281 wider mode. If the integer mode is wider than the mode of FROM,
5282 we can do the conversion signed even if the input is unsigned. */
5286 {
5296 {
5302 }
5305 {
5318 }
5319 }
5321 /* Unsigned integer, and no way to convert directly. Convert as signed,
5322 then unconditionally adjust the result. */
5324 && can_do_signed
5327 {
5328 opt_scalar_mode fmode_iter;
5330 rtx temp;
5331 REAL_VALUE_TYPE offset;
5333 /* Look for a usable floating mode FMODE wider than the source and at
5334 least as wide as the target. Using FMODE will avoid rounding woes
5335 with unsigned values greater than the signed maximum value. */
5338 {
5343 }
5346 {
5347 /* There is no such mode. Pretend the target is wide enough. */
5350 /* Avoid double-rounding when TO is narrower than FROM. */
5353 {
5354 rtx temp1;
5357 /* Don't use TARGET if it isn't a register, is a hard register,
5358 or is the wrong mode. */
5367 /* Test whether the sign bit is set. */
5371 /* The sign bit is not set. Convert as signed. */
5376 /* The sign bit is set.
5377 Convert to a usable (positive signed) value by shifting right
5378 one bit, while remembering if a nonzero bit was shifted
5379 out; i.e., compute (from & 1) | (from >> 1). */
5386 OPTAB_LIB_WIDEN);
5389 /* Multiply by 2 to undo the shift above. */
5398 }
5399 }
5401 /* If we are about to do some arithmetic to correct for an
5402 unsigned operand, do it in a pseudo-register. */
5408 /* Convert as signed integer to floating. */
5411 /* If FROM is negative (and therefore TO is negative),
5412 correct its value by 2**bitwidth. */
5429 }
5431 /* No hardware instruction available; call a library routine. */
5432 {
5433 rtx libfunc;
5435 rtx value;
5454 }
5456 done:
5458 /* Copy result to requested destination
5459 if we have been computing in a temp location. */
5462 {
5465 else
5467 }
5468 }
5469 \f
5470 /* Generate code to convert FROM to fixed point and store in TO. FROM
5471 must be floating point. */
5473 void
5475 {
5479 opt_scalar_mode fmode_iter;
5482 /* We first try to find a pair of modes, one real and one integer, at
5483 least as wide as FROM and TO, respectively, in which we can open-code
5484 this conversion. If the integer mode is wider than the mode of TO,
5485 we can do the conversion either signed or unsigned. */
5489 {
5497 {
5504 {
5508 }
5515 {
5519 }
5521 }
5522 }
5524 /* For an unsigned conversion, there is one more way to do it.
5525 If we have a signed conversion, we generate code that compares
5526 the real value to the largest representable positive number. If if
5527 is smaller, the conversion is done normally. Otherwise, subtract
5528 one plus the highest signed number, convert, and add it back.
5530 We only need to check all real modes, since we know we didn't find
5531 anything with a wider integer mode.
5533 This code used to extend FP value into mode wider than the destination.
5534 This is needed for decimal float modes which cannot accurately
5535 represent one plus the highest signed number of the same size, but
5536 not for binary modes. Consider, for instance conversion from SFmode
5537 into DImode.
5539 The hot path through the code is dealing with inputs smaller than 2^63
5540 and doing just the conversion, so there is no bits to lose.
5542 In the other path we know the value is positive in the range 2^63..2^64-1
5543 inclusive. (as for other input overflow happens and result is undefined)
5544 So we know that the most important bit set in mantissa corresponds to
5545 2^63. The subtraction of 2^63 should not generate any rounding as it
5546 simply clears out that bit. The rest is trivial. */
5548 scalar_int_mode to_mode;
5553 {
5559 {
5561 REAL_VALUE_TYPE offset;
5562 rtx limit;
5575 /* See if we need to do the subtraction. */
5580 /* If not, do the signed "fix" and branch around fixup code. */
5585 /* Otherwise, subtract 2**(N-1), convert to signed number,
5586 then add 2**(N-1). Do the addition using XOR since this
5587 will often generate better code. */
5593 gen_int_mode
5595 to_mode),
5604 {
5605 /* Make a place for a REG_NOTE and add it. */
5610 to);
5611 }
5614 }
5615 }
5617 /* We can't do it with an insn, so use a library call. But first ensure
5618 that the mode of TO is at least as wide as SImode, since those are the
5619 only library calls we know about. */
5622 {
5626 }
5627 else
5628 {
5630 rtx value;
5631 rtx libfunc;
5647 }
5650 {
5653 else
5655 }
5656 }
5659 /* Promote integer arguments for a libcall if necessary.
5660 emit_library_call_value cannot do the promotion because it does not
5661 know if it should do a signed or unsigned promotion. This is because
5662 there are no tree types defined for libcalls. */
5664 static rtx
5666 {
5667 scalar_int_mode mode;
5668 machine_mode arg_mode;
5670 {
5671 /* If we need to promote the integer function argument we need to do
5672 it here instead of inside emit_library_call_value because in
5673 emit_library_call_value we don't know if we should do a signed or
5674 unsigned promotion. */
5681 }
5683 }
5685 /* Generate code to convert FROM or TO a fixed-point.
5686 If UINTP is true, either TO or FROM is an unsigned integer.
5687 If SATP is true, we need to saturate the result. */
5689 void
5691 {
5694 convert_optab tab;
5698 rtx value;
5699 rtx libfunc;
5702 {
5705 }
5708 {
5711 }
5712 else
5713 {
5716 }
5719 {
5722 }
5738 }
5740 /* Generate code to convert FROM to fixed point and store in TO. FROM
5741 must be floating point, TO must be signed. Use the conversion optab
5742 TAB to do the conversion. */
5744 bool
5746 {
5751 /* We first try to find a pair of modes, one real and one integer, at
5752 least as wide as FROM and TO, respectively, in which we can open-code
5753 this conversion. If the integer mode is wider than the mode of TO,
5754 we can do the conversion either signed or unsigned. */
5758 {
5761 {
5770 {
5773 }
5777 }
5778 }
5781 }
5782 \f
5783 /* Report whether we have an instruction to perform the operation
5784 specified by CODE on operands of mode MODE. */
5785 int
5787 {
5791 }
5793 /* Print information about the current contents of the optabs on
5794 STDERR. */
5796 DEBUG_FUNCTION void
5798 {
5801 /* Dump the arithmetic optabs. */
5804 {
5807 {
5813 }
5814 }
5816 /* Dump the conversion optabs. */
5820 {
5824 {
5831 }
5832 }
5833 }
5835 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
5836 CODE. Return 0 on failure. */
5838 rtx_insn *
5840 {
5844 rtx trap_rtx;
5853 /* Some targets only accept a zero trap code. */
5863 else
5865 tcode);
5867 /* If that failed, then give up. */
5869 {
5872 }
5878 }
5880 /* Return rtx code for TCODE or UNKNOWN. Use UNSIGNEDP to select signed
5881 or unsigned operation code. */
5883 enum rtx_code
5885 {
5888 {
5944 }
5946 }
5948 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
5949 or unsigned operation code. */
5951 enum rtx_code
5953 {
5957 }
5959 /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to
5960 select signed or unsigned operators. OPNO holds the index of the
5961 first comparison operand for insn ICODE. Do not generate the
5962 compare instruction itself. */
5964 rtx
5968 {
5976 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
5977 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
5978 cases, use the original mode. */
5980 EXPAND_STACK_PARM);
5986 EXPAND_STACK_PARM);
5996 }
5998 /* Check if vec_perm mask SEL is a constant equivalent to a shift of
5999 the first vec_perm operand, assuming the second operand (for left shift
6000 first operand) is a constant vector of zeros. Return the shift distance
6001 in bits if so, or NULL_RTX if the vec_perm is not a shift. MODE is the
6002 mode of the value being shifted. SHIFT_OPTAB is vec_shr_optab for right
6003 shift or vec_shl_optab for left shift. */
6004 static rtx
6006 optab shift_optab)
6007 {
6014 {
6020 {
6022 {
6026 }
6031 }
6036 }
6038 {
6043 {
6045 /* Indices into the second vector are all equivalent. */
6050 }
6051 }
6054 }
6056 /* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */
6058 static rtx
6061 {
6071 /* Make an effort to preserve v0 == v1. The target expander is able to
6072 rely on this to determine if we're permuting a single input operand. */
6074 {
6082 }
6083 else
6084 {
6087 }
6092 }
6094 /* Implement a permutation of vectors v0 and v1 using the permutation
6095 vector in SEL and return the result. Use TARGET to hold the result
6096 if nonnull and convenient.
6098 MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE
6099 is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known
6100 to have a particular mode. */
6102 rtx
6105 rtx target)
6106 {
6110 /* Set QIMODE to a different vector mode with byte elements.
6111 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6112 machine_mode qimode;
6119 /* Always specify two input vectors here and leave the target to handle
6120 cases in which the inputs are equal. Not all backends can cope with
6121 the single-input representation when testing for a double-input
6122 target instruction. */
6125 /* See if this can be handled with a vec_shr or vec_shl. We only do this
6126 if the second (for vec_shr) or first (for vec_shl) vector is all
6127 zeroes. */
6135 {
6138 }
6140 {
6145 }
6147 {
6150 {
6155 {
6161 }
6163 {
6170 }
6171 }
6172 }
6175 {
6181 }
6183 /* Fall back to a constant byte-based permutation. */
6184 vec_perm_indices qimode_indices;
6187 {
6196 }
6203 /* Otherwise expand as a fully variable permuation. */
6205 /* The optabs are only defined for selectors with the same width
6206 as the values being permuted. */
6207 machine_mode required_sel_mode;
6209 {
6212 }
6214 /* We know that it is semantically valid to treat SEL as having SEL_MODE.
6215 If that isn't the mode we want then we need to prove that using
6216 REQUIRED_SEL_MODE is OK. */
6218 {
6220 {
6223 }
6225 }
6229 {
6234 }
6238 {
6241 {
6246 }
6247 }
6251 }
6253 /* Implement a permutation of vectors v0 and v1 using the permutation
6254 vector in SEL and return the result. Use TARGET to hold the result
6255 if nonnull and convenient.
6257 MODE is the mode of the vectors being permuted (V0 and V1).
6258 SEL must have the integer equivalent of MODE and is known to be
6259 unsuitable for permutes with a constant permutation vector. */
6261 rtx
6263 {
6275 {
6279 }
6281 /* As a special case to aid several targets, lower the element-based
6282 permutation to a byte-based permutation and try again. */
6283 machine_mode qimode;
6291 /* Multiply each element by its byte size. */
6296 else
6302 /* Broadcast the low byte each element into each of its bytes.
6303 The encoding has U interleaved stepped patterns, one for each
6304 byte of an element. */
6314 /* Add the byte offset to each byte element. */
6315 /* Note that the definition of the indicies here is memory ordering,
6316 so there should be no difference between big and little endian. */
6331 }
6333 /* Generate VEC_SERIES_EXPR <OP0, OP1>, returning a value of mode VMODE.
6334 Use TARGET for the result if nonnull and convenient. */
6336 rtx
6338 {
6352 }
6354 /* Generate insns for a vector comparison into a mask. */
6356 rtx
6358 {
6361 rtx comparison;
6363 machine_mode vmode;
6377 {
6382 }
6392 }
6394 /* Expand a highpart multiply. */
6396 rtx
6399 {
6403 machine_mode wmode;
6409 {
6415 OPTAB_LIB_WIDEN);
6428 }
6448 vec_perm_builder sel;
6450 {
6451 /* The encoding has 2 interleaved stepped patterns. */
6456 }
6457 else
6458 {
6459 /* The encoding has a single interleaved stepped pattern. */
6463 }
6466 }
6467 \f
6468 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
6469 pattern. */
6471 static void
6473 {
6476 {
6480 }
6481 }
6483 /* This is a helper function for the other atomic operations. This function
6484 emits a loop that contains SEQ that iterates until a compare-and-swap
6485 operation at the end succeeds. MEM is the memory to be modified. SEQ is
6486 a set of instructions that takes a value from OLD_REG as an input and
6487 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
6488 set to the current contents of MEM. After SEQ, a compare-and-swap will
6489 attempt to update MEM with NEW_REG. The function returns true when the
6490 loop was generated successfully. */
6492 static bool
6494 {
6499 /* The loop we want to generate looks like
6501 cmp_reg = mem;
6502 label:
6503 old_reg = cmp_reg;
6504 seq;
6505 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
6506 if (success)
6507 goto label;
6509 Note that we only do the plain load from memory once. Subsequent
6510 iterations use the value loaded by the compare-and-swap pattern. */
6525 MEMMODEL_RELAXED))
6531 /* Mark this jump predicted not taken. */
6536 }
6539 /* This function tries to emit an atomic_exchange intruction. VAL is written
6540 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
6541 using TARGET if possible. */
6543 static rtx
6545 {
6549 /* If the target supports the exchange directly, great. */
6552 {
6561 }
6564 }
6566 /* This function tries to implement an atomic exchange operation using
6567 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
6568 The previous contents of *MEM are returned, using TARGET if possible.
6569 Since this instructionn is an acquire barrier only, stronger memory
6570 models may require additional barriers to be emitted. */
6572 static rtx
6575 {
6582 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
6583 exists, and the memory model is stronger than acquire, add a release
6584 barrier before the instruction. */
6590 {
6597 }
6599 /* If an external test-and-set libcall is provided, use that instead of
6600 any external compare-and-swap that we might get from the compare-and-
6601 swap-loop expansion later. */
6603 {
6606 {
6607 rtx addr;
6613 }
6614 }
6616 /* If the test_and_set can't be emitted, eliminate any barrier that might
6617 have been emitted. */
6620 }
6622 /* This function tries to implement an atomic exchange operation using a
6623 compare_and_swap loop. VAL is written to *MEM. The previous contents of
6624 *MEM are returned, using TARGET if possible. No memory model is required
6625 since a compare_and_swap loop is seq-cst. */
6627 static rtx
6629 {
6633 {
6638 }
6641 }
6643 /* This function tries to implement an atomic test-and-set operation
6644 using the atomic_test_and_set instruction pattern. A boolean value
6645 is returned from the operation, using TARGET if possible. */
6647 static rtx
6649 {
6650 machine_mode pat_bool_mode;
6656 /* While we always get QImode from __atomic_test_and_set, we get
6657 other memory modes from __sync_lock_test_and_set. Note that we
6658 use no endian adjustment here. This matches the 4.6 behavior
6659 in the Sparc backend. */
6673 }
6675 /* This function expands the legacy _sync_lock test_and_set operation which is
6676 generally an atomic exchange. Some limited targets only allow the
6677 constant 1 to be stored. This is an ACQUIRE operation.
6679 TARGET is an optional place to stick the return value.
6680 MEM is where VAL is stored. */
6682 rtx
6684 {
6685 rtx ret;
6687 /* Try an atomic_exchange first. */
6693 MEMMODEL_SYNC_ACQUIRE);
6701 /* If there are no other options, try atomic_test_and_set if the value
6702 being stored is 1. */
6707 }
6709 /* This function expands the atomic test_and_set operation:
6710 atomically store a boolean TRUE into MEM and return the previous value.
6712 MEMMODEL is the memory model variant to use.
6713 TARGET is an optional place to stick the return value. */
6715 rtx
6717 {
6725 /* Be binary compatible with non-default settings of trueval, and different
6726 cpu revisions. E.g. one revision may have atomic-test-and-set, but
6727 another only has atomic-exchange. */
6729 {
6732 }
6733 else
6734 {
6737 }
6739 /* Try the atomic-exchange optab... */
6742 /* ... then an atomic-compare-and-swap loop ... */
6746 /* ... before trying the vaguely defined legacy lock_test_and_set. */
6750 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
6751 things with the value 1. Thus we try again without trueval. */
6755 /* Failing all else, assume a single threaded environment and simply
6756 perform the operation. */
6758 {
6759 /* If the result is ignored skip the move to target. */
6765 }
6767 /* Recall that have to return a boolean value; rectify if trueval
6768 is not exactly one. */
6773 }
6775 /* This function expands the atomic exchange operation:
6776 atomically store VAL in MEM and return the previous value in MEM.
6778 MEMMODEL is the memory model variant to use.
6779 TARGET is an optional place to stick the return value. */
6781 rtx
6783 {
6785 rtx ret;
6787 /* If loads are not atomic for the required size and we are not called to
6788 provide a __sync builtin, do not do anything so that we stay consistent
6789 with atomic loads of the same size. */
6795 /* Next try a compare-and-swap loop for the exchange. */
6800 }
6802 /* This function expands the atomic compare exchange operation:
6804 *PTARGET_BOOL is an optional place to store the boolean success/failure.
6805 *PTARGET_OVAL is an optional place to store the old value from memory.
6806 Both target parameters may be NULL or const0_rtx to indicate that we do
6807 not care about that return value. Both target parameters are updated on
6808 success to the actual location of the corresponding result.
6810 MEMMODEL is the memory model variant to use.
6812 The return value of the function is true for success. */
6814 bool
6819 {
6824 rtx libfunc;
6826 /* If loads are not atomic for the required size and we are not called to
6827 provide a __sync builtin, do not do anything so that we stay consistent
6828 with atomic loads of the same size. */
6832 /* Load expected into a register for the compare and swap. */
6836 /* Make sure we always have some place to put the return oldval.
6837 Further, make sure that place is distinct from the input expected,
6838 just in case we need that path down below. */
6849 {
6855 /* Make sure we always have a place for the bool operand. */
6861 /* Emit the compare_and_swap. */
6871 {
6872 /* Return success/failure. */
6876 }
6877 }
6879 /* Otherwise fall back to the original __sync_val_compare_and_swap
6880 which is always seq-cst. */
6883 {
6884 rtx cc_reg;
6895 /* If the caller isn't interested in the boolean return value,
6896 skip the computation of it. */
6900 /* Otherwise, work out if the compare-and-swap succeeded. */
6905 {
6909 }
6911 }
6913 /* Also check for library support for __sync_val_compare_and_swap. */
6916 {
6923 /* Compute the boolean return value only if requested. */
6926 else
6928 }
6930 /* Failure. */
6933 success_bool_from_val:
6936 success:
6937 /* Make sure that the oval output winds up where the caller asked. */
6943 }
6945 /* Generate asm volatile("" : : : "memory") as the memory blockage. */
6947 static void
6949 {
6962 }
6964 /* Do not propagate memory accesses across this point. */
6966 static void
6968 {
6971 else
6973 }
6975 /* Generate asm volatile("" : : : "memory") as a memory blockage, at the
6976 same time clobbering the register set specified by REGS. */
6978 void
6980 {
6986 num_of_regs++;
7003 {
7007 {
7009 j++;
7010 }
7012 }
7015 }
7017 /* This routine will either emit the mem_thread_fence pattern or issue a
7018 sync_synchronize to generate a fence for memory model MEMMODEL. */
7020 void
7022 {
7026 {
7029 }
7034 else
7036 }
7038 /* Emit a signal fence with given memory model. */
7040 void
7042 {
7043 /* No machine barrier is required to implement a signal fence, but
7044 a compiler memory barrier must be issued, except for relaxed MM. */
7047 }
7049 /* This function expands the atomic load operation:
7050 return the atomically loaded value in MEM.
7052 MEMMODEL is the memory model variant to use.
7053 TARGET is an option place to stick the return value. */
7055 rtx
7057 {
7061 /* If the target supports the load directly, great. */
7064 {
7074 {
7078 }
7080 }
7082 /* If the size of the object is greater than word size on this target,
7083 then we assume that a load will not be atomic. We could try to
7084 emulate a load with a compare-and-swap operation, but the store that
7085 doing this could result in would be incorrect if this is a volatile
7086 atomic load or targetting read-only-mapped memory. */
7088 /* If there is no atomic load, leave the library call. */
7091 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7095 /* For SEQ_CST, emit a barrier before the load. */
7101 /* Emit the appropriate barrier after the load. */
7105 }
7107 /* This function expands the atomic store operation:
7108 Atomically store VAL in MEM.
7109 MEMMODEL is the memory model variant to use.
7110 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7111 function returns const0_rtx if a pattern was emitted. */
7113 rtx
7115 {
7120 /* If the target supports the store directly, great. */
7123 {
7131 {
7135 }
7137 }
7139 /* If using __sync_lock_release is a viable alternative, try it.
7140 Note that this will not be set to true if we are expanding a generic
7141 __atomic_store_n. */
7143 {
7146 {
7150 {
7151 /* lock_release is only a release barrier. */
7155 }
7156 }
7157 }
7159 /* If the size of the object is greater than word size on this target,
7160 a default store will not be atomic. */
7162 {
7163 /* If loads are atomic or we are called to provide a __sync builtin,
7164 we can try a atomic_exchange and throw away the result. Otherwise,
7165 don't do anything so that we do not create an inconsistency between
7166 loads and stores. */
7168 {
7172 val);
7175 }
7177 }
7179 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7184 /* For SEQ_CST, also emit a barrier after the store. */
7189 }
7192 /* Structure containing the pointers and values required to process the
7193 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7195 struct atomic_op_functions
7196 {
7197 direct_optab mem_fetch_before;
7198 direct_optab mem_fetch_after;
7199 direct_optab mem_no_result;
7200 optab fetch_before;
7201 optab fetch_after;
7202 direct_optab no_result;
7204 };
7207 /* Fill in structure pointed to by OP with the various optab entries for an
7208 operation of type CODE. */
7210 static void
7212 {
7215 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7216 in the source code during compilation, and the optab entries are not
7217 computable until runtime. Fill in the values at runtime. */
7219 {
7276 }
7277 }
7279 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7280 using memory order MODEL. If AFTER is true the operation needs to return
7281 the value of *MEM after the operation, otherwise the previous value.
7282 TARGET is an optional place to place the result. The result is unused if
7283 it is const0_rtx.
7284 Return the result if there is a better sequence, otherwise NULL_RTX. */
7286 static rtx
7289 {
7290 /* If the value is prefetched, or not used, it may be possible to replace
7291 the sequence with a native exchange operation. */
7293 {
7294 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7296 {
7300 }
7302 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7304 {
7308 }
7309 }
7312 }
7314 /* Try to emit an instruction for a specific operation varaition.
7315 OPTAB contains the OP functions.
7316 TARGET is an optional place to return the result. const0_rtx means unused.
7317 MEM is the memory location to operate on.
7318 VAL is the value to use in the operation.
7319 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7320 MODEL is the memory model, if used.
7321 AFTER is true if the returned result is the value after the operation. */
7323 static rtx
7326 {
7333 /* Check to see if there is a result returned. */
7335 {
7337 {
7341 }
7342 else
7343 {
7346 }
7347 }
7348 /* Otherwise, we need to generate a result. */
7349 else
7350 {
7352 {
7357 }
7358 else
7359 {
7363 }
7365 }
7370 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7377 }
7380 /* This function expands an atomic fetch_OP or OP_fetch operation:
7381 TARGET is an option place to stick the return value. const0_rtx indicates
7382 the result is unused.
7383 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7384 CODE is the operation being performed (OP)
7385 MEMMODEL is the memory model variant to use.
7386 AFTER is true to return the result of the operation (OP_fetch).
7387 AFTER is false to return the value before the operation (fetch_OP).
7389 This function will *only* generate instructions if there is a direct
7390 optab. No compare and swap loops or libcalls will be generated. */
7392 static rtx
7396 {
7399 rtx result;
7404 /* Check to see if there are any better instructions. */
7409 /* Check for the case where the result isn't used and try those patterns. */
7411 {
7412 /* Try the memory model variant first. */
7417 /* Next try the old style withuot a memory model. */
7422 /* There is no no-result pattern, so try patterns with a result. */
7424 }
7426 /* Try the __atomic version. */
7431 /* Try the older __sync version. */
7436 /* If the fetch value can be calculated from the other variation of fetch,
7437 try that operation. */
7439 {
7440 /* Try the __atomic version, then the older __sync version. */
7446 {
7447 /* If the result isn't used, no need to do compensation code. */
7451 /* Issue compensation code. Fetch_after == fetch_before OP val.
7452 Fetch_before == after REVERSE_OP val. */
7456 {
7460 }
7461 else
7465 }
7466 }
7468 /* No direct opcode can be generated. */
7470 }
7474 /* This function expands an atomic fetch_OP or OP_fetch operation:
7475 TARGET is an option place to stick the return value. const0_rtx indicates
7476 the result is unused.
7477 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7478 CODE is the operation being performed (OP)
7479 MEMMODEL is the memory model variant to use.
7480 AFTER is true to return the result of the operation (OP_fetch).
7481 AFTER is false to return the value before the operation (fetch_OP). */
7482 rtx
7485 {
7487 rtx result;
7490 /* If loads are not atomic for the required size and we are not called to
7491 provide a __sync builtin, do not do anything so that we stay consistent
7492 with atomic loads of the same size. */
7497 after);
7502 /* Add/sub can be implemented by doing the reverse operation with -(val). */
7504 {
7505 rtx tmp;
7513 {
7514 /* PLUS worked so emit the insns and return. */
7519 }
7521 /* PLUS did not work, so throw away the negation code and continue. */
7523 }
7525 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
7527 {
7528 rtx libfunc;
7538 {
7544 }
7546 {
7555 }
7557 /* We need the original code for any further attempts. */
7559 }
7561 /* If nothing else has succeeded, default to a compare and swap loop. */
7563 {
7569 /* If the result is used, get a register for it. */
7571 {
7574 /* If fetch_before, copy the value now. */
7577 }
7578 else
7583 {
7587 }
7588 else
7590 OPTAB_LIB_WIDEN);
7592 /* For after, copy the value now. */
7600 }
7603 }
7604 \f
7605 /* Return true if OPERAND is suitable for operand number OPNO of
7606 instruction ICODE. */
7608 bool
7610 {
7614 }
7615 \f
7616 /* TARGET is a target of a multiword operation that we are going to
7617 implement as a series of word-mode operations. Return true if
7618 TARGET is suitable for this purpose. */
7620 bool
7622 {
7623 machine_mode mode;
7633 }
7635 /* Make OP describe an input operand that has value INTVAL and that has
7636 no inherent mode. This function should only be used for operands that
7637 are always expand-time constants. The backend may request that INTVAL
7638 be copied into a different kind of rtx, but it must specify the mode
7639 of that rtx if so. */
7641 void
7643 {
7647 }
7649 /* Like maybe_legitimize_operand, but do not change the code of the
7650 current rtx value. */
7652 static bool
7655 {
7656 /* See if the operand matches in its current form. */
7660 /* If the operand is a memory whose address has no side effects,
7661 try forcing the address into a non-virtual pseudo register.
7662 The check for side effects is important because copy_to_mode_reg
7663 cannot handle things like auto-modified addresses. */
7665 {
7672 {
7674 machine_mode mode;
7680 {
7683 }
7685 }
7686 }
7689 }
7691 /* Try to make OP match operand OPNO of instruction ICODE. Return true
7692 on success, storing the new operand value back in OP. */
7694 static bool
7697 {
7702 {
7704 {
7707 }
7722 input:
7740 else
7741 /* The caller must tell us what mode this value has. */
7748 {
7751 }
7753 {
7757 }
7770 {
7773 }
7775 }
7777 }
7779 /* Make OP describe an input operand that should have the same value
7780 as VALUE, after any mode conversion that the target might request.
7781 TYPE is the type of VALUE. */
7783 void
7786 {
7789 }
7791 /* Return true if the requirements on operands OP1 and OP2 of instruction
7792 ICODE are similar enough for the result of legitimizing OP1 to be
7793 reusable for OP2. OPNO1 and OPNO2 are the operand numbers associated
7794 with OP1 and OP2 respectively. */
7801 {
7802 /* Check requirements that are common to all types. */
7809 /* Check the requirements for specific types. */
7811 {
7813 /* Outputs must remain distinct. */
7825 }
7827 }
7829 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
7830 of instruction ICODE. Return true on success, leaving the new operand
7831 values in the OPS themselves. Emit no code on failure. */
7833 bool
7836 {
7840 {
7843 /* First try reusing the result of an earlier legitimization.
7844 This avoids duplicate rtl and ensures that tied operands
7845 remain tied.
7847 This search is linear, but NOPS is bounded at compile time
7848 to a small number (current a single digit). */
7855 {
7858 }
7860 /* Otherwise try legitimizing the operand on its own. */
7862 {
7865 }
7866 }
7868 }
7870 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
7871 as its operands. Return the instruction pattern on success,
7872 and emit any necessary set-up code. Return null and emit no
7873 code on failure. */
7875 rtx_insn *
7878 {
7884 {
7912 }
7914 }
7916 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
7917 as its operands. Return true on success and emit no code on failure. */
7919 bool
7922 {
7925 {
7928 }
7930 }
7932 /* Like maybe_expand_insn, but for jumps. */
7934 bool
7937 {
7940 {
7943 }
7945 }
7947 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
7948 as its operands. */
7950 void
7953 {
7956 }
7958 /* Like expand_insn, but for jumps. */
7960 void
7963 {
7966 }