| blob | 63a651a5035b26e4ee96c8f69a06d93180511aef |
1 ;;- Machine description for Blackfin for GNU compiler
2 ;; Copyright 2005, 2006 Free Software Foundation, Inc.
3 ;; Contributed by Analog Devices.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ; operand punctuation marks:
23 ;
24 ; X -- integer value printed as log2
25 ; Y -- integer value printed as log2(~value) - for bitclear
26 ; h -- print half word register, low part
27 ; d -- print half word register, high part
28 ; D -- print operand as dregs pairs
29 ; w -- print operand as accumulator register word (a0w, a1w)
30 ; H -- high part of double mode operand
31 ; T -- byte register representation Oct. 02 2001
33 ; constant operand classes
34 ;
35 ; J 2**N 5bit imm scaled
36 ; Ks7 -64 .. 63 signed 7bit imm
37 ; Ku5 0..31 unsigned 5bit imm
38 ; Ks4 -8 .. 7 signed 4bit imm
39 ; Ks3 -4 .. 3 signed 3bit imm
40 ; Ku3 0 .. 7 unsigned 3bit imm
41 ; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
42 ;
43 ; register operands
44 ; d (r0..r7)
45 ; a (p0..p5,fp,sp)
46 ; e (a0, a1)
47 ; b (i0..i3)
48 ; f (m0..m3)
49 ; v (b0..b3)
50 ; c (i0..i3,m0..m3) CIRCREGS
51 ; C (CC) CCREGS
52 ; t (lt0,lt1)
53 ; k (lc0,lc1)
54 ; u (lb0,lb1)
55 ;
57 ;; Define constants for hard registers.
59 (define_constants
60 [(REG_R0 0)
61 (REG_R1 1)
62 (REG_R2 2)
63 (REG_R3 3)
64 (REG_R4 4)
65 (REG_R5 5)
66 (REG_R6 6)
67 (REG_R7 7)
69 (REG_P0 8)
70 (REG_P1 9)
71 (REG_P2 10)
72 (REG_P3 11)
73 (REG_P4 12)
74 (REG_P5 13)
75 (REG_P6 14)
76 (REG_P7 15)
78 (REG_SP 14)
79 (REG_FP 15)
81 (REG_I0 16)
82 (REG_I1 17)
83 (REG_I2 18)
84 (REG_I3 19)
86 (REG_B0 20)
87 (REG_B1 21)
88 (REG_B2 22)
89 (REG_B3 23)
91 (REG_L0 24)
92 (REG_L1 25)
93 (REG_L2 26)
94 (REG_L3 27)
96 (REG_M0 28)
97 (REG_M1 29)
98 (REG_M2 30)
99 (REG_M3 31)
101 (REG_A0 32)
102 (REG_A1 33)
104 (REG_CC 34)
105 (REG_RETS 35)
106 (REG_RETI 36)
107 (REG_RETX 37)
108 (REG_RETN 38)
109 (REG_RETE 39)
111 (REG_ASTAT 40)
112 (REG_SEQSTAT 41)
113 (REG_USP 42)
115 (REG_ARGP 43)
117 (REG_LT0 44)
118 (REG_LT1 45)
119 (REG_LC0 46)
120 (REG_LC1 47)
121 (REG_LB0 48)
122 (REG_LB1 49)])
124 ;; Constants used in UNSPECs and UNSPEC_VOLATILEs.
126 (define_constants
127 [(UNSPEC_CBRANCH_TAKEN 0)
128 (UNSPEC_CBRANCH_NOPS 1)
129 (UNSPEC_RETURN 2)
130 (UNSPEC_MOVE_PIC 3)
131 (UNSPEC_LIBRARY_OFFSET 4)
132 (UNSPEC_PUSH_MULTIPLE 5)
133 ;; Multiply or MAC with extra CONST_INT operand specifying the macflag
134 (UNSPEC_MUL_WITH_FLAG 6)
135 (UNSPEC_MAC_WITH_FLAG 7)
136 (UNSPEC_MOVE_FDPIC 8)
137 (UNSPEC_FUNCDESC_GOT17M4 9)
138 (UNSPEC_LSETUP_END 10)
139 ;; Distinguish a 32-bit version of an insn from a 16-bit version.
140 (UNSPEC_32BIT 11)])
142 (define_constants
143 [(UNSPEC_VOLATILE_EH_RETURN 0)
144 (UNSPEC_VOLATILE_CSYNC 1)
145 (UNSPEC_VOLATILE_SSYNC 2)
146 (UNSPEC_VOLATILE_LOAD_FUNCDESC 3)])
148 (define_constants
149 [(MACFLAG_NONE 0)
150 (MACFLAG_T 1)
151 (MACFLAG_FU 2)
152 (MACFLAG_TFU 3)
153 (MACFLAG_IS 4)
154 (MACFLAG_IU 5)
155 (MACFLAG_W32 6)
156 (MACFLAG_M 7)
157 (MACFLAG_S2RND 8)
158 (MACFLAG_ISS2 9)
159 (MACFLAG_IH 10)])
161 (define_attr "type"
162 "move,movcc,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,sync,compare,dummy"
163 (const_string "misc"))
165 (define_attr "addrtype" "32bit,preg,ireg"
166 (cond [(and (eq_attr "type" "mcld")
167 (and (match_operand 0 "d_register_operand" "")
168 (match_operand 1 "mem_p_address_operand" "")))
169 (const_string "preg")
170 (and (eq_attr "type" "mcld")
171 (and (match_operand 0 "d_register_operand" "")
172 (match_operand 1 "mem_i_address_operand" "")))
173 (const_string "ireg")
174 (and (eq_attr "type" "mcst")
175 (and (match_operand 1 "d_register_operand" "")
176 (match_operand 0 "mem_p_address_operand" "")))
177 (const_string "preg")
178 (and (eq_attr "type" "mcst")
179 (and (match_operand 1 "d_register_operand" "")
180 (match_operand 0 "mem_i_address_operand" "")))
181 (const_string "ireg")]
182 (const_string "32bit")))
184 ;; Scheduling definitions
186 (define_automaton "bfin")
188 (define_cpu_unit "slot0" "bfin")
189 (define_cpu_unit "slot1" "bfin")
190 (define_cpu_unit "slot2" "bfin")
192 ;; Three units used to enforce parallel issue restrictions:
193 ;; only one of the 16-bit slots can use a P register in an address,
194 ;; and only one them can be a store.
195 (define_cpu_unit "store" "bfin")
196 (define_cpu_unit "pregs" "bfin")
198 (define_reservation "core" "slot0+slot1+slot2")
200 (define_insn_reservation "alu" 1
201 (eq_attr "type" "move,movcc,mvi,alu0,shft,brcc,br,call,misc,sync,compare")
202 "core")
204 (define_insn_reservation "imul" 3
205 (eq_attr "type" "mult")
206 "core*3")
208 (define_insn_reservation "dsp32" 1
209 (eq_attr "type" "dsp32")
210 "slot0")
212 (define_insn_reservation "load32" 1
213 (and (not (eq_attr "seq_insns" "multi"))
214 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "32bit")))
215 "core")
217 (define_insn_reservation "loadp" 1
218 (and (not (eq_attr "seq_insns" "multi"))
219 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "preg")))
220 "(slot1|slot2)+pregs")
222 (define_insn_reservation "loadi" 1
223 (and (not (eq_attr "seq_insns" "multi"))
224 (and (eq_attr "type" "mcld") (eq_attr "addrtype" "ireg")))
225 "(slot1|slot2)")
227 (define_insn_reservation "store32" 1
228 (and (not (eq_attr "seq_insns" "multi"))
229 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "32bit")))
230 "core")
232 (define_insn_reservation "storep" 1
233 (and (not (eq_attr "seq_insns" "multi"))
234 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "preg")))
235 "(slot1|slot2)+pregs+store")
237 (define_insn_reservation "storei" 1
238 (and (not (eq_attr "seq_insns" "multi"))
239 (and (eq_attr "type" "mcst") (eq_attr "addrtype" "ireg")))
240 "(slot1|slot2)+store")
242 (define_insn_reservation "multi" 2
243 (eq_attr "seq_insns" "multi")
244 "core")
246 (absence_set "slot0" "slot1,slot2")
247 (absence_set "slot1" "slot2")
249 ;; Make sure genautomata knows about the maximum latency that can be produced
250 ;; by the adjust_cost function.
251 (define_insn_reservation "dummy" 5
252 (eq_attr "type" "dummy")
253 "core")
254 \f
255 ;; Operand and operator predicates
257 (include "predicates.md")
259 \f
260 ;;; FRIO branches have been optimized for code density
261 ;;; this comes at a slight cost of complexity when
262 ;;; a compiler needs to generate branches in the general
263 ;;; case. In order to generate the correct branching
264 ;;; mechanisms the compiler needs keep track of instruction
265 ;;; lengths. The follow table describes how to count instructions
266 ;;; for the FRIO architecture.
267 ;;;
268 ;;; unconditional br are 12-bit imm pcrelative branches *2
269 ;;; conditional br are 10-bit imm pcrelative branches *2
270 ;;; brcc 10-bit:
271 ;;; 1024 10-bit imm *2 is 2048 (-1024..1022)
272 ;;; br 12-bit :
273 ;;; 4096 12-bit imm *2 is 8192 (-4096..4094)
274 ;;; NOTE : For brcc we generate instructions such as
275 ;;; if cc jmp; jump.[sl] offset
276 ;;; offset of jump.[sl] is from the jump instruction but
277 ;;; gcc calculates length from the if cc jmp instruction
278 ;;; furthermore gcc takes the end address of the branch instruction
279 ;;; as (pc) for a forward branch
280 ;;; hence our range is (-4094, 4092) instead of (-4096, 4094) for a br
281 ;;;
282 ;;; The way the (pc) rtx works in these calculations is somewhat odd;
283 ;;; for backward branches it's the address of the current instruction,
284 ;;; for forward branches it's the previously known address of the following
285 ;;; instruction - we have to take this into account by reducing the range
286 ;;; for a forward branch.
288 ;; Lengths for type "mvi" insns are always defined by the instructions
289 ;; themselves.
290 (define_attr "length" ""
291 (cond [(eq_attr "type" "mcld")
292 (if_then_else (match_operand 1 "effective_address_32bit_p" "")
293 (const_int 4) (const_int 2))
295 (eq_attr "type" "mcst")
296 (if_then_else (match_operand 0 "effective_address_32bit_p" "")
297 (const_int 4) (const_int 2))
299 (eq_attr "type" "move") (const_int 2)
301 (eq_attr "type" "dsp32") (const_int 4)
302 (eq_attr "type" "call") (const_int 4)
304 (eq_attr "type" "br")
305 (if_then_else (and
306 (le (minus (match_dup 0) (pc)) (const_int 4092))
307 (ge (minus (match_dup 0) (pc)) (const_int -4096)))
308 (const_int 2)
309 (const_int 4))
311 (eq_attr "type" "brcc")
312 (cond [(and
313 (le (minus (match_dup 3) (pc)) (const_int 1020))
314 (ge (minus (match_dup 3) (pc)) (const_int -1024)))
315 (const_int 2)
316 (and
317 (le (minus (match_dup 3) (pc)) (const_int 4092))
318 (ge (minus (match_dup 3) (pc)) (const_int -4094)))
319 (const_int 4)]
320 (const_int 6))
321 ]
323 (const_int 2)))
325 ;; Classify the insns into those that are one instruction and those that
326 ;; are more than one in sequence.
327 (define_attr "seq_insns" "single,multi"
328 (const_string "single"))
330 ;; Conditional moves
332 (define_expand "movsicc"
333 [(set (match_operand:SI 0 "register_operand" "")
334 (if_then_else:SI (match_operand 1 "comparison_operator" "")
335 (match_operand:SI 2 "register_operand" "")
336 (match_operand:SI 3 "register_operand" "")))]
337 ""
338 {
339 operands[1] = bfin_gen_compare (operands[1], SImode);
340 })
342 (define_insn "*movsicc_insn1"
343 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
344 (if_then_else:SI
345 (eq:BI (match_operand:BI 3 "register_operand" "C,C,C")
346 (const_int 0))
347 (match_operand:SI 1 "register_operand" "da,0,da")
348 (match_operand:SI 2 "register_operand" "0,da,da")))]
349 ""
350 "@
351 if !cc %0 =%1; /* movsicc-1a */
352 if cc %0 =%2; /* movsicc-1b */
353 if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */"
354 [(set_attr "length" "2,2,4")
355 (set_attr "type" "movcc")
356 (set_attr "seq_insns" "*,*,multi")])
358 (define_insn "*movsicc_insn2"
359 [(set (match_operand:SI 0 "register_operand" "=da,da,da")
360 (if_then_else:SI
361 (ne:BI (match_operand:BI 3 "register_operand" "C,C,C")
362 (const_int 0))
363 (match_operand:SI 1 "register_operand" "0,da,da")
364 (match_operand:SI 2 "register_operand" "da,0,da")))]
365 ""
366 "@
367 if !cc %0 =%2; /* movsicc-2b */
368 if cc %0 =%1; /* movsicc-2a */
369 if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */"
370 [(set_attr "length" "2,2,4")
371 (set_attr "type" "movcc")
372 (set_attr "seq_insns" "*,*,multi")])
374 ;; Insns to load HIGH and LO_SUM
376 (define_insn "movsi_high"
377 [(set (match_operand:SI 0 "register_operand" "=x")
378 (high:SI (match_operand:SI 1 "immediate_operand" "i")))]
379 "reload_completed"
380 "%d0 = %d1;"
381 [(set_attr "type" "mvi")
382 (set_attr "length" "4")])
384 (define_insn "movstricthi_high"
385 [(set (match_operand:SI 0 "register_operand" "+x")
386 (ior:SI (and:SI (match_dup 0) (const_int 65535))
387 (match_operand:SI 1 "immediate_operand" "i")))]
388 "reload_completed"
389 "%d0 = %d1;"
390 [(set_attr "type" "mvi")
391 (set_attr "length" "4")])
393 (define_insn "movsi_low"
394 [(set (match_operand:SI 0 "register_operand" "=x")
395 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
396 (match_operand:SI 2 "immediate_operand" "i")))]
397 "reload_completed"
398 "%h0 = %h2;"
399 [(set_attr "type" "mvi")
400 (set_attr "length" "4")])
402 (define_insn "movsi_high_pic"
403 [(set (match_operand:SI 0 "register_operand" "=x")
404 (high:SI (unspec:SI [(match_operand:SI 1 "" "")]
405 UNSPEC_MOVE_PIC)))]
406 ""
407 "%d0 = %1@GOT_LOW;"
408 [(set_attr "type" "mvi")
409 (set_attr "length" "4")])
411 (define_insn "movsi_low_pic"
412 [(set (match_operand:SI 0 "register_operand" "=x")
413 (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
414 (unspec:SI [(match_operand:SI 2 "" "")]
415 UNSPEC_MOVE_PIC)))]
416 ""
417 "%h0 = %h2@GOT_HIGH;"
418 [(set_attr "type" "mvi")
419 (set_attr "length" "4")])
421 ;;; Move instructions
423 (define_insn_and_split "movdi_insn"
424 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
425 (match_operand:DI 1 "general_operand" "iFx,r,mx"))]
426 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
427 "#"
428 "reload_completed"
429 [(set (match_dup 2) (match_dup 3))
430 (set (match_dup 4) (match_dup 5))]
431 {
432 rtx lo_half[2], hi_half[2];
433 split_di (operands, 2, lo_half, hi_half);
435 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
436 {
437 operands[2] = hi_half[0];
438 operands[3] = hi_half[1];
439 operands[4] = lo_half[0];
440 operands[5] = lo_half[1];
441 }
442 else
443 {
444 operands[2] = lo_half[0];
445 operands[3] = lo_half[1];
446 operands[4] = hi_half[0];
447 operands[5] = hi_half[1];
448 }
449 })
451 (define_insn "movbi"
452 [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
453 (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
455 ""
456 "@
457 %0 = %1;
458 %0 = %1 (X);
459 %0 = B %1 (Z)%!
460 B %0 = %1;
461 CC = %1;
462 %0 = CC;
463 R0 = R0 | R0; CC = AC0;"
464 [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
465 (set_attr "length" "2,2,*,*,2,2,4")
466 (set_attr "seq_insns" "*,*,*,*,*,*,multi")])
468 (define_insn "movpdi"
469 [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
470 (match_operand:PDI 1 "general_operand" " e,e,>"))]
471 ""
472 "@
473 %0 = %1;
474 %0 = %x1; %0 = %w1;
475 %w0 = %1; %x0 = %1;"
476 [(set_attr "type" "move,mcst,mcld")
477 (set_attr "seq_insns" "*,multi,multi")])
479 (define_insn "load_accumulator"
480 [(set (match_operand:PDI 0 "register_operand" "=e")
481 (sign_extend:PDI (match_operand:SI 1 "register_operand" "d")))]
482 ""
483 "%0 = %1;"
484 [(set_attr "type" "move")])
486 (define_insn_and_split "load_accumulator_pair"
487 [(set (match_operand:V2PDI 0 "register_operand" "=e")
488 (sign_extend:V2PDI (vec_concat:V2SI
489 (match_operand:SI 1 "register_operand" "d")
490 (match_operand:SI 2 "register_operand" "d"))))]
491 ""
492 "#"
493 "reload_completed"
494 [(set (match_dup 3) (sign_extend:PDI (match_dup 1)))
495 (set (match_dup 4) (sign_extend:PDI (match_dup 2)))]
496 {
497 operands[3] = gen_rtx_REG (PDImode, REGNO (operands[0]));
498 operands[4] = gen_rtx_REG (PDImode, REGNO (operands[0]) + 1);
499 })
501 (define_insn "*pushsi_insn"
502 [(set (mem:SI (pre_dec:SI (reg:SI REG_SP)))
503 (match_operand:SI 0 "register_operand" "xy"))]
504 ""
505 "[--SP] = %0;"
506 [(set_attr "type" "mcst")
507 (set_attr "addrtype" "32bit")
508 (set_attr "length" "2")])
510 (define_insn "*popsi_insn"
511 [(set (match_operand:SI 0 "register_operand" "=d,xy")
512 (mem:SI (post_inc:SI (reg:SI REG_SP))))]
513 ""
514 "%0 = [SP++]%!"
515 [(set_attr "type" "mcld")
516 (set_attr "addrtype" "preg,32bit")
517 (set_attr "length" "2")])
519 ;; The first alternative is used to make reload choose a limited register
520 ;; class when faced with a movsi_insn that had its input operand replaced
521 ;; with a PLUS. We generally require fewer secondary reloads this way.
523 (define_insn "*movsi_insn"
524 [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,*k,da,da,x,x,x,da,mr")
525 (match_operand:SI 1 "general_operand" "da,x*y,da,*k,xKs7,xKsh,xKuh,ix,mr,da"))]
526 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
527 "@
528 %0 = %1;
529 %0 = %1;
530 %0 = %1;
531 %0 = %1;
532 %0 = %1 (X);
533 %0 = %1 (X);
534 %0 = %1 (Z);
535 #
536 %0 = %1%!
537 %0 = %1%!"
538 [(set_attr "type" "move,move,move,move,mvi,mvi,mvi,*,mcld,mcst")
539 (set_attr "length" "2,2,2,2,2,4,4,*,*,*")])
541 (define_insn "*movsi_insn32"
542 [(set (match_operand:SI 0 "register_operand" "=d,d")
543 (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "d,P0")] UNSPEC_32BIT))]
544 ""
545 "@
546 %0 = ROT %1 BY 0%!
547 %0 = %0 -|- %0%!"
548 [(set_attr "type" "dsp32")])
550 (define_split
551 [(set (match_operand:SI 0 "d_register_operand" "")
552 (const_int 0))]
553 "splitting_for_sched && !optimize_size"
554 [(set (match_dup 0) (unspec:SI [(const_int 0)] UNSPEC_32BIT))])
556 (define_split
557 [(set (match_operand:SI 0 "d_register_operand" "")
558 (match_operand:SI 1 "d_register_operand" ""))]
559 "splitting_for_sched && !optimize_size"
560 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_32BIT))])
562 (define_insn_and_split "*movv2hi_insn"
563 [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
564 (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
566 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
567 "@
568 #
569 %0 = %1;
570 %0 = %1%!
571 %0 = %1%!"
572 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
573 [(set (match_dup 0) (high:SI (match_dup 2)))
574 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
575 {
576 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
577 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
579 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
580 operands[2] = operands[3] = GEN_INT (trunc_int_for_mode (intval, SImode));
581 }
582 [(set_attr "type" "move,move,mcld,mcst")
583 (set_attr "length" "2,2,*,*")])
585 (define_insn "*movhi_insn"
586 [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
587 (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
588 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
589 {
590 static const char *templates[] = {
591 "%0 = %1;",
592 "%0 = %1 (X);",
593 "%0 = %1 (X);",
594 "%0 = W %1 (X)%!",
595 "W %0 = %1%!",
596 "%h0 = W %1%!",
597 "W %0 = %h1%!"
598 };
599 int alt = which_alternative;
600 rtx mem = (MEM_P (operands[0]) ? operands[0]
601 : MEM_P (operands[1]) ? operands[1] : NULL_RTX);
602 if (mem && bfin_dsp_memref_p (mem))
603 alt += 2;
604 return templates[alt];
605 }
606 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
607 (set_attr "length" "2,2,4,*,*")])
609 (define_insn "*movqi_insn"
610 [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
611 (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
612 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
613 "@
614 %0 = %1;
615 %0 = %1 (X);
616 %0 = %1 (X);
617 %0 = B %1 (X)%!
618 B %0 = %1%!"
619 [(set_attr "type" "move,mvi,mvi,mcld,mcst")
620 (set_attr "length" "2,2,4,*,*")])
622 (define_insn "*movsf_insn"
623 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
624 (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
625 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
626 "@
627 %0 = %1;
628 #
629 %0 = %1%!
630 %0 = %1%!"
631 [(set_attr "type" "move,*,mcld,mcst")])
633 (define_insn_and_split "movdf_insn"
634 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
635 (match_operand:DF 1 "general_operand" "iFx,r,mx"))]
636 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
637 "#"
638 "reload_completed"
639 [(set (match_dup 2) (match_dup 3))
640 (set (match_dup 4) (match_dup 5))]
641 {
642 rtx lo_half[2], hi_half[2];
643 split_di (operands, 2, lo_half, hi_half);
645 if (reg_overlap_mentioned_p (lo_half[0], hi_half[1]))
646 {
647 operands[2] = hi_half[0];
648 operands[3] = hi_half[1];
649 operands[4] = lo_half[0];
650 operands[5] = lo_half[1];
651 }
652 else
653 {
654 operands[2] = lo_half[0];
655 operands[3] = lo_half[1];
656 operands[4] = hi_half[0];
657 operands[5] = hi_half[1];
658 }
659 })
661 ;; Storing halfwords.
662 (define_insn "*movsi_insv"
663 [(set (zero_extract:SI (match_operand 0 "register_operand" "+d,x")
664 (const_int 16)
665 (const_int 16))
666 (match_operand:SI 1 "nonmemory_operand" "d,n"))]
667 ""
668 "@
669 %d0 = %h1 << 0%!
670 %d0 = %1;"
671 [(set_attr "type" "dsp32,mvi")])
673 (define_expand "insv"
674 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
675 (match_operand:SI 1 "immediate_operand" "")
676 (match_operand:SI 2 "immediate_operand" ""))
677 (match_operand:SI 3 "nonmemory_operand" ""))]
678 ""
679 {
680 if (INTVAL (operands[1]) != 16 || INTVAL (operands[2]) != 16)
681 FAIL;
683 /* From mips.md: insert_bit_field doesn't verify that our source
684 matches the predicate, so check it again here. */
685 if (! register_operand (operands[0], VOIDmode))
686 FAIL;
687 })
689 ;; This is the main "hook" for PIC code. When generating
690 ;; PIC, movsi is responsible for determining when the source address
691 ;; needs PIC relocation and appropriately calling legitimize_pic_address
692 ;; to perform the actual relocation.
694 (define_expand "movsi"
695 [(set (match_operand:SI 0 "nonimmediate_operand" "")
696 (match_operand:SI 1 "general_operand" ""))]
697 ""
698 {
699 if (expand_move (operands, SImode))
700 DONE;
701 })
703 (define_expand "movv2hi"
704 [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
705 (match_operand:V2HI 1 "general_operand" ""))]
706 ""
707 "expand_move (operands, V2HImode);")
709 (define_expand "movdi"
710 [(set (match_operand:DI 0 "nonimmediate_operand" "")
711 (match_operand:DI 1 "general_operand" ""))]
712 ""
713 "expand_move (operands, DImode);")
715 (define_expand "movsf"
716 [(set (match_operand:SF 0 "nonimmediate_operand" "")
717 (match_operand:SF 1 "general_operand" ""))]
718 ""
719 "expand_move (operands, SFmode);")
721 (define_expand "movdf"
722 [(set (match_operand:DF 0 "nonimmediate_operand" "")
723 (match_operand:DF 1 "general_operand" ""))]
724 ""
725 "expand_move (operands, DFmode);")
727 (define_expand "movhi"
728 [(set (match_operand:HI 0 "nonimmediate_operand" "")
729 (match_operand:HI 1 "general_operand" ""))]
730 ""
731 "expand_move (operands, HImode);")
733 (define_expand "movqi"
734 [(set (match_operand:QI 0 "nonimmediate_operand" "")
735 (match_operand:QI 1 "general_operand" ""))]
736 ""
737 " expand_move (operands, QImode); ")
739 ;; Some define_splits to break up SI/SFmode loads of immediate constants.
741 (define_split
742 [(set (match_operand:SI 0 "register_operand" "")
743 (match_operand:SI 1 "symbolic_or_const_operand" ""))]
744 "reload_completed
745 /* Always split symbolic operands; split integer constants that are
746 too large for a single instruction. */
747 && (GET_CODE (operands[1]) != CONST_INT
748 || (INTVAL (operands[1]) < -32768
749 || INTVAL (operands[1]) >= 65536
750 || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
751 [(set (match_dup 0) (high:SI (match_dup 1)))
752 (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
753 {
754 if (GET_CODE (operands[1]) == CONST_INT
755 && split_load_immediate (operands))
756 DONE;
757 /* ??? Do something about TARGET_LOW_64K. */
758 })
760 (define_split
761 [(set (match_operand:SF 0 "register_operand" "")
762 (match_operand:SF 1 "immediate_operand" ""))]
763 "reload_completed"
764 [(set (match_dup 2) (high:SI (match_dup 3)))
765 (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
766 {
767 long values;
768 REAL_VALUE_TYPE value;
770 gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
772 REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
773 REAL_VALUE_TO_TARGET_SINGLE (value, values);
775 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
776 operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
777 if (values >= -32768 && values < 65536)
778 {
779 emit_move_insn (operands[2], operands[3]);
780 DONE;
781 }
782 if (split_load_immediate (operands + 2))
783 DONE;
784 })
786 ;; Sadly, this can't be a proper named movstrict pattern, since the compiler
787 ;; expects to be able to use registers for operand 1.
788 ;; Note that the asm instruction is defined by the manual to take an unsigned
789 ;; constant, but it doesn't matter to the assembler, and the compiler only
790 ;; deals with sign-extended constants. Hence "Ksh".
791 (define_insn "movstricthi_1"
792 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x"))
793 (match_operand:HI 1 "immediate_operand" "Ksh"))]
794 ""
795 "%h0 = %1;"
796 [(set_attr "type" "mvi")
797 (set_attr "length" "4")])
799 ;; Sign and zero extensions
801 (define_insn_and_split "extendhisi2"
802 [(set (match_operand:SI 0 "register_operand" "=d, d")
803 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
804 ""
805 "@
806 %0 = %h1 (X);
807 %0 = W %h1 (X)%!"
808 "reload_completed && bfin_dsp_memref_p (operands[1])"
809 [(set (match_dup 2) (match_dup 1))
810 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
811 {
812 operands[2] = gen_lowpart (HImode, operands[0]);
813 }
814 [(set_attr "type" "alu0,mcld")])
816 (define_insn_and_split "zero_extendhisi2"
817 [(set (match_operand:SI 0 "register_operand" "=d, d")
818 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
819 ""
820 "@
821 %0 = %h1 (Z);
822 %0 = W %h1 (Z)%!"
823 "reload_completed && bfin_dsp_memref_p (operands[1])"
824 [(set (match_dup 2) (match_dup 1))
825 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
826 {
827 operands[2] = gen_lowpart (HImode, operands[0]);
828 }
829 [(set_attr "type" "alu0,mcld")])
831 (define_insn "zero_extendbisi2"
832 [(set (match_operand:SI 0 "register_operand" "=d")
833 (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
834 ""
835 "%0 = %1;"
836 [(set_attr "type" "compare")])
838 (define_insn "extendqihi2"
839 [(set (match_operand:HI 0 "register_operand" "=d, d")
840 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
841 ""
842 "@
843 %0 = B %1 (X)%!
844 %0 = %T1 (X);"
845 [(set_attr "type" "mcld,alu0")])
847 (define_insn "extendqisi2"
848 [(set (match_operand:SI 0 "register_operand" "=d, d")
849 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
850 ""
851 "@
852 %0 = B %1 (X)%!
853 %0 = %T1 (X);"
854 [(set_attr "type" "mcld,alu0")])
857 (define_insn "zero_extendqihi2"
858 [(set (match_operand:HI 0 "register_operand" "=d, d")
859 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
860 ""
861 "@
862 %0 = B %1 (Z)%!
863 %0 = %T1 (Z);"
864 [(set_attr "type" "mcld,alu0")])
867 (define_insn "zero_extendqisi2"
868 [(set (match_operand:SI 0 "register_operand" "=d, d")
869 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
870 ""
871 "@
872 %0 = B %1 (Z)%!
873 %0 = %T1 (Z);"
874 [(set_attr "type" "mcld,alu0")])
876 ;; DImode logical operations
878 (define_code_macro any_logical [and ior xor])
879 (define_code_attr optab [(and "and")
880 (ior "ior")
881 (xor "xor")])
882 (define_code_attr op [(and "&")
883 (ior "|")
884 (xor "^")])
885 (define_code_attr high_result [(and "0")
886 (ior "%H1")
887 (xor "%H1")])
889 (define_insn "<optab>di3"
890 [(set (match_operand:DI 0 "register_operand" "=d")
891 (any_logical:DI (match_operand:DI 1 "register_operand" "0")
892 (match_operand:DI 2 "register_operand" "d")))]
893 ""
894 "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;"
895 [(set_attr "length" "4")
896 (set_attr "seq_insns" "multi")])
898 (define_insn "*<optab>di_zesidi_di"
899 [(set (match_operand:DI 0 "register_operand" "=d")
900 (any_logical:DI (zero_extend:DI
901 (match_operand:SI 2 "register_operand" "d"))
902 (match_operand:DI 1 "register_operand" "d")))]
903 ""
904 "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;"
905 [(set_attr "length" "4")
906 (set_attr "seq_insns" "multi")])
908 (define_insn "*<optab>di_sesdi_di"
909 [(set (match_operand:DI 0 "register_operand" "=d")
910 (any_logical:DI (sign_extend:DI
911 (match_operand:SI 2 "register_operand" "d"))
912 (match_operand:DI 1 "register_operand" "0")))
913 (clobber (match_scratch:SI 3 "=&d"))]
914 ""
915 "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;"
916 [(set_attr "length" "8")
917 (set_attr "seq_insns" "multi")])
919 (define_insn "negdi2"
920 [(set (match_operand:DI 0 "register_operand" "=d")
921 (neg:DI (match_operand:DI 1 "register_operand" "d")))
922 (clobber (match_scratch:SI 2 "=&d"))
923 (clobber (reg:CC REG_CC))]
924 ""
925 "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;"
926 [(set_attr "length" "16")
927 (set_attr "seq_insns" "multi")])
929 (define_insn "one_cmpldi2"
930 [(set (match_operand:DI 0 "register_operand" "=d")
931 (not:DI (match_operand:DI 1 "register_operand" "d")))]
932 ""
933 "%0 = ~%1;\\n\\t%H0 = ~%H1;"
934 [(set_attr "length" "4")
935 (set_attr "seq_insns" "multi")])
937 ;; DImode zero and sign extend patterns
939 (define_insn_and_split "zero_extendsidi2"
940 [(set (match_operand:DI 0 "register_operand" "=d")
941 (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
942 ""
943 "#"
944 "reload_completed"
945 [(set (match_dup 3) (const_int 0))]
946 {
947 split_di (operands, 1, operands + 2, operands + 3);
948 if (REGNO (operands[0]) != REGNO (operands[1]))
949 emit_move_insn (operands[2], operands[1]);
950 })
952 (define_insn "zero_extendqidi2"
953 [(set (match_operand:DI 0 "register_operand" "=d")
954 (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
955 ""
956 "%0 = %T1 (Z);\\n\\t%H0 = 0;"
957 [(set_attr "length" "4")
958 (set_attr "seq_insns" "multi")])
960 (define_insn "zero_extendhidi2"
961 [(set (match_operand:DI 0 "register_operand" "=d")
962 (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
963 ""
964 "%0 = %h1 (Z);\\n\\t%H0 = 0;"
965 [(set_attr "length" "4")
966 (set_attr "seq_insns" "multi")])
968 (define_insn_and_split "extendsidi2"
969 [(set (match_operand:DI 0 "register_operand" "=d")
970 (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
971 ""
972 "#"
973 "reload_completed"
974 [(set (match_dup 3) (match_dup 1))
975 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
976 {
977 split_di (operands, 1, operands + 2, operands + 3);
978 if (REGNO (operands[0]) != REGNO (operands[1]))
979 emit_move_insn (operands[2], operands[1]);
980 })
982 (define_insn_and_split "extendqidi2"
983 [(set (match_operand:DI 0 "register_operand" "=d")
984 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
985 ""
986 "#"
987 "reload_completed"
988 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
989 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
990 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
991 {
992 split_di (operands, 1, operands + 2, operands + 3);
993 })
995 (define_insn_and_split "extendhidi2"
996 [(set (match_operand:DI 0 "register_operand" "=d")
997 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
998 ""
999 "#"
1000 "reload_completed"
1001 [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
1002 (set (match_dup 3) (sign_extend:SI (match_dup 1)))
1003 (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
1004 {
1005 split_di (operands, 1, operands + 2, operands + 3);
1006 })
1008 ;; DImode arithmetic operations
1010 (define_insn "adddi3"
1011 [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
1012 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
1013 (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d")))
1014 (clobber (match_scratch:SI 3 "=&d,&d,&d"))
1015 (clobber (reg:CC 34))]
1016 ""
1017 "@
1018 %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3;
1019 %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3;
1020 %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;"
1021 [(set_attr "type" "alu0")
1022 (set_attr "length" "10,8,10")
1023 (set_attr "seq_insns" "multi,multi,multi")])
1025 (define_insn "subdi3"
1026 [(set (match_operand:DI 0 "register_operand" "=&d")
1027 (minus:DI (match_operand:DI 1 "register_operand" "0")
1028 (match_operand:DI 2 "register_operand" "d")))
1029 (clobber (reg:CC 34))]
1030 ""
1031 "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1032 [(set_attr "length" "10")
1033 (set_attr "seq_insns" "multi")])
1035 (define_insn "*subdi_di_zesidi"
1036 [(set (match_operand:DI 0 "register_operand" "=d")
1037 (minus:DI (match_operand:DI 1 "register_operand" "0")
1038 (zero_extend:DI
1039 (match_operand:SI 2 "register_operand" "d"))))
1040 (clobber (match_scratch:SI 3 "=&d"))
1041 (clobber (reg:CC 34))]
1042 ""
1043 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;"
1044 [(set_attr "length" "10")
1045 (set_attr "seq_insns" "multi")])
1047 (define_insn "*subdi_zesidi_di"
1048 [(set (match_operand:DI 0 "register_operand" "=d")
1049 (minus:DI (zero_extend:DI
1050 (match_operand:SI 2 "register_operand" "d"))
1051 (match_operand:DI 1 "register_operand" "0")))
1052 (clobber (match_scratch:SI 3 "=&d"))
1053 (clobber (reg:CC 34))]
1054 ""
1055 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1"
1056 [(set_attr "length" "12")
1057 (set_attr "seq_insns" "multi")])
1059 (define_insn "*subdi_di_sesidi"
1060 [(set (match_operand:DI 0 "register_operand" "=d")
1061 (minus:DI (match_operand:DI 1 "register_operand" "0")
1062 (sign_extend:DI
1063 (match_operand:SI 2 "register_operand" "d"))))
1064 (clobber (match_scratch:SI 3 "=&d"))
1065 (clobber (reg:CC 34))]
1066 ""
1067 "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1068 [(set_attr "length" "14")
1069 (set_attr "seq_insns" "multi")])
1071 (define_insn "*subdi_sesidi_di"
1072 [(set (match_operand:DI 0 "register_operand" "=d")
1073 (minus:DI (sign_extend:DI
1074 (match_operand:SI 2 "register_operand" "d"))
1075 (match_operand:DI 1 "register_operand" "0")))
1076 (clobber (match_scratch:SI 3 "=&d"))
1077 (clobber (reg:CC 34))]
1078 ""
1079 "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
1080 [(set_attr "length" "14")
1081 (set_attr "seq_insns" "multi")])
1083 ;; Combined shift/add instructions
1085 (define_insn ""
1086 [(set (match_operand:SI 0 "register_operand" "=a,d")
1087 (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1088 (match_operand:SI 2 "register_operand" "a,d"))
1089 (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
1090 ""
1091 "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
1092 [(set_attr "type" "alu0")])
1094 (define_insn ""
1095 [(set (match_operand:SI 0 "register_operand" "=a")
1096 (plus:SI (match_operand:SI 1 "register_operand" "a")
1097 (mult:SI (match_operand:SI 2 "register_operand" "a")
1098 (match_operand:SI 3 "scale_by_operand" "i"))))]
1099 ""
1100 "%0 = %1 + (%2 << %X3);"
1101 [(set_attr "type" "alu0")])
1103 (define_insn ""
1104 [(set (match_operand:SI 0 "register_operand" "=a")
1105 (plus:SI (match_operand:SI 1 "register_operand" "a")
1106 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1107 (match_operand:SI 3 "pos_scale_operand" "i"))))]
1108 ""
1109 "%0 = %1 + (%2 << %3);"
1110 [(set_attr "type" "alu0")])
1112 (define_insn ""
1113 [(set (match_operand:SI 0 "register_operand" "=a")
1114 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a")
1115 (match_operand:SI 2 "scale_by_operand" "i"))
1116 (match_operand:SI 3 "register_operand" "a")))]
1117 ""
1118 "%0 = %3 + (%1 << %X2);"
1119 [(set_attr "type" "alu0")])
1121 (define_insn ""
1122 [(set (match_operand:SI 0 "register_operand" "=a")
1123 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a")
1124 (match_operand:SI 2 "pos_scale_operand" "i"))
1125 (match_operand:SI 3 "register_operand" "a")))]
1126 ""
1127 "%0 = %3 + (%1 << %2);"
1128 [(set_attr "type" "alu0")])
1130 (define_insn "mulhisi3"
1131 [(set (match_operand:SI 0 "register_operand" "=d")
1132 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1133 (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1134 ""
1135 "%0 = %h1 * %h2 (IS)%!"
1136 [(set_attr "type" "dsp32")])
1138 (define_insn "umulhisi3"
1139 [(set (match_operand:SI 0 "register_operand" "=d")
1140 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d"))
1141 (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))]
1142 ""
1143 "%0 = %h1 * %h2 (FU)%!"
1144 [(set_attr "type" "dsp32")])
1146 (define_insn "usmulhisi3"
1147 [(set (match_operand:SI 0 "register_operand" "=W")
1148 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
1149 (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
1150 ""
1151 "%0 = %h2 * %h1 (IS,M)%!"
1152 [(set_attr "type" "dsp32")])
1154 ;; The processor also supports ireg += mreg or ireg -= mreg, but these
1155 ;; are unusable if we don't ensure that the corresponding lreg is zero.
1156 ;; The same applies to the add/subtract constant versions involving
1157 ;; iregs
1159 (define_insn "addsi3"
1160 [(set (match_operand:SI 0 "register_operand" "=ad,a,d")
1161 (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d")
1162 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
1163 ""
1164 "@
1165 %0 += %2;
1166 %0 = %1 + %2;
1167 %0 = %1 + %2;"
1168 [(set_attr "type" "alu0")
1169 (set_attr "length" "2,2,2")])
1171 (define_insn "ssaddsi3"
1172 [(set (match_operand:SI 0 "register_operand" "=d")
1173 (ss_plus:SI (match_operand:SI 1 "register_operand" "d")
1174 (match_operand:SI 2 "register_operand" "d")))]
1175 ""
1176 "%0 = %1 + %2 (S)%!"
1177 [(set_attr "type" "dsp32")])
1179 (define_insn "subsi3"
1180 [(set (match_operand:SI 0 "register_operand" "=da,d,a")
1181 (minus:SI (match_operand:SI 1 "register_operand" "0,d,0")
1182 (match_operand:SI 2 "reg_or_neg7bit_operand" "KN7,d,a")))]
1183 ""
1184 {
1185 static const char *const strings_subsi3[] = {
1186 "%0 += -%2;",
1187 "%0 = %1 - %2;",
1188 "%0 -= %2;",
1189 };
1191 if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
1192 rtx tmp_op = operands[2];
1193 operands[2] = GEN_INT (-INTVAL (operands[2]));
1194 output_asm_insn ("%0 += %2;", operands);
1195 operands[2] = tmp_op;
1196 return "";
1197 }
1199 return strings_subsi3[which_alternative];
1200 }
1201 [(set_attr "type" "alu0")])
1203 (define_insn "sssubsi3"
1204 [(set (match_operand:SI 0 "register_operand" "=d")
1205 (ss_minus:SI (match_operand:SI 1 "register_operand" "d")
1206 (match_operand:SI 2 "register_operand" "d")))]
1207 ""
1208 "%0 = %1 - %2 (S)%!"
1209 [(set_attr "type" "dsp32")])
1211 ;; Bit test instructions
1213 (define_insn "*not_bittst"
1214 [(set (match_operand:BI 0 "register_operand" "=C")
1215 (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1216 (const_int 1)
1217 (match_operand:SI 2 "immediate_operand" "Ku5"))
1218 (const_int 0)))]
1219 ""
1220 "cc = !BITTST (%1,%2);"
1221 [(set_attr "type" "alu0")])
1223 (define_insn "*bittst"
1224 [(set (match_operand:BI 0 "register_operand" "=C")
1225 (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1226 (const_int 1)
1227 (match_operand:SI 2 "immediate_operand" "Ku5"))
1228 (const_int 0)))]
1229 ""
1230 "cc = BITTST (%1,%2);"
1231 [(set_attr "type" "alu0")])
1233 (define_insn_and_split "*bit_extract"
1234 [(set (match_operand:SI 0 "register_operand" "=d")
1235 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
1236 (const_int 1)
1237 (match_operand:SI 2 "immediate_operand" "Ku5")))
1238 (clobber (reg:BI REG_CC))]
1239 ""
1240 "#"
1241 ""
1242 [(set (reg:BI REG_CC)
1243 (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1244 (const_int 0)))
1245 (set (match_dup 0)
1246 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1248 (define_insn_and_split "*not_bit_extract"
1249 [(set (match_operand:SI 0 "register_operand" "=d")
1250 (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1251 (const_int 1)
1252 (match_operand:SI 2 "immediate_operand" "Ku5")))
1253 (clobber (reg:BI REG_CC))]
1254 ""
1255 "#"
1256 ""
1257 [(set (reg:BI REG_CC)
1258 (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
1259 (const_int 0)))
1260 (set (match_dup 0)
1261 (ne:SI (reg:BI REG_CC) (const_int 0)))])
1263 (define_insn "*andsi_insn"
1264 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
1265 (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d")
1266 (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
1267 ""
1268 "@
1269 BITCLR (%0,%Y2);
1270 %0 = %T1 (Z);
1271 %0 = %h1 (Z);
1272 %0 = %1 & %2;"
1273 [(set_attr "type" "alu0")])
1275 (define_expand "andsi3"
1276 [(set (match_operand:SI 0 "register_operand" "")
1277 (and:SI (match_operand:SI 1 "register_operand" "")
1278 (match_operand:SI 2 "general_operand" "")))]
1279 ""
1280 {
1281 if (highbits_operand (operands[2], SImode))
1282 {
1283 operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
1284 emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
1285 emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
1286 DONE;
1287 }
1288 if (! rhs_andsi3_operand (operands[2], SImode))
1289 operands[2] = force_reg (SImode, operands[2]);
1290 })
1292 (define_insn "iorsi3"
1293 [(set (match_operand:SI 0 "register_operand" "=d,d")
1294 (ior:SI (match_operand:SI 1 "register_operand" "%0,d")
1295 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1296 ""
1297 "@
1298 BITSET (%0, %X2);
1299 %0 = %1 | %2;"
1300 [(set_attr "type" "alu0")])
1302 (define_insn "xorsi3"
1303 [(set (match_operand:SI 0 "register_operand" "=d,d")
1304 (xor:SI (match_operand:SI 1 "register_operand" "%0,d")
1305 (match_operand:SI 2 "regorlog2_operand" "J,d")))]
1306 ""
1307 "@
1308 BITTGL (%0, %X2);
1309 %0 = %1 ^ %2;"
1310 [(set_attr "type" "alu0")])
1312 (define_insn "smaxsi3"
1313 [(set (match_operand:SI 0 "register_operand" "=d")
1314 (smax:SI (match_operand:SI 1 "register_operand" "d")
1315 (match_operand:SI 2 "register_operand" "d")))]
1316 ""
1317 "%0 = max(%1,%2)%!"
1318 [(set_attr "type" "dsp32")])
1320 (define_insn "sminsi3"
1321 [(set (match_operand:SI 0 "register_operand" "=d")
1322 (smin:SI (match_operand:SI 1 "register_operand" "d")
1323 (match_operand:SI 2 "register_operand" "d")))]
1324 ""
1325 "%0 = min(%1,%2)%!"
1326 [(set_attr "type" "dsp32")])
1328 (define_insn "abssi2"
1329 [(set (match_operand:SI 0 "register_operand" "=d")
1330 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1331 ""
1332 "%0 = abs %1%!"
1333 [(set_attr "type" "dsp32")])
1335 (define_insn "negsi2"
1336 [(set (match_operand:SI 0 "register_operand" "=d")
1337 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1338 ""
1339 "%0 = -%1;"
1340 [(set_attr "type" "alu0")])
1342 (define_insn "ssnegsi2"
1343 [(set (match_operand:SI 0 "register_operand" "=d")
1344 (ss_neg:SI (match_operand:SI 1 "register_operand" "d")))]
1345 ""
1346 "%0 = -%1 (S)%!"
1347 [(set_attr "type" "dsp32")])
1349 (define_insn "one_cmplsi2"
1350 [(set (match_operand:SI 0 "register_operand" "=d")
1351 (not:SI (match_operand:SI 1 "register_operand" "d")))]
1352 ""
1353 "%0 = ~%1;"
1354 [(set_attr "type" "alu0")])
1356 (define_insn "signbitssi2"
1357 [(set (match_operand:HI 0 "register_operand" "=d")
1358 (if_then_else:HI
1359 (lt (match_operand:SI 1 "register_operand" "d") (const_int 0))
1360 (clz:HI (not:SI (match_dup 1)))
1361 (clz:HI (match_dup 1))))]
1362 ""
1363 "%h0 = signbits %1%!"
1364 [(set_attr "type" "dsp32")])
1366 (define_insn "smaxhi3"
1367 [(set (match_operand:HI 0 "register_operand" "=d")
1368 (smax:HI (match_operand:HI 1 "register_operand" "d")
1369 (match_operand:HI 2 "register_operand" "d")))]
1370 ""
1371 "%0 = max(%1,%2) (V)%!"
1372 [(set_attr "type" "dsp32")])
1374 (define_insn "sminhi3"
1375 [(set (match_operand:HI 0 "register_operand" "=d")
1376 (smin:HI (match_operand:HI 1 "register_operand" "d")
1377 (match_operand:HI 2 "register_operand" "d")))]
1378 ""
1379 "%0 = min(%1,%2) (V)%!"
1380 [(set_attr "type" "dsp32")])
1382 (define_insn "abshi2"
1383 [(set (match_operand:HI 0 "register_operand" "=d")
1384 (abs:HI (match_operand:HI 1 "register_operand" "d")))]
1385 ""
1386 "%0 = abs %1 (V)%!"
1387 [(set_attr "type" "dsp32")])
1389 (define_insn "neghi2"
1390 [(set (match_operand:HI 0 "register_operand" "=d")
1391 (neg:HI (match_operand:HI 1 "register_operand" "d")))]
1392 ""
1393 "%0 = -%1;"
1394 [(set_attr "type" "alu0")])
1396 (define_insn "ssneghi2"
1397 [(set (match_operand:HI 0 "register_operand" "=d")
1398 (ss_neg:HI (match_operand:HI 1 "register_operand" "d")))]
1399 ""
1400 "%0 = -%1 (V)%!"
1401 [(set_attr "type" "dsp32")])
1403 (define_insn "signbitshi2"
1404 [(set (match_operand:HI 0 "register_operand" "=d")
1405 (if_then_else:HI
1406 (lt (match_operand:HI 1 "register_operand" "d") (const_int 0))
1407 (clz:HI (not:HI (match_dup 1)))
1408 (clz:HI (match_dup 1))))]
1409 ""
1410 "%h0 = signbits %h1%!"
1411 [(set_attr "type" "dsp32")])
1413 (define_insn "mulsi3"
1414 [(set (match_operand:SI 0 "register_operand" "=d")
1415 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1416 (match_operand:SI 2 "register_operand" "d")))]
1417 ""
1418 "%0 *= %2;"
1419 [(set_attr "type" "mult")])
1421 (define_expand "ashlsi3"
1422 [(set (match_operand:SI 0 "register_operand" "")
1423 (ashift:SI (match_operand:SI 1 "register_operand" "")
1424 (match_operand:SI 2 "nonmemory_operand" "")))]
1425 ""
1426 {
1427 if (GET_CODE (operands[2]) == CONST_INT
1428 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
1429 {
1430 emit_insn (gen_movsi (operands[0], const0_rtx));
1431 DONE;
1432 }
1433 })
1435 (define_insn_and_split "*ashlsi3_insn"
1436 [(set (match_operand:SI 0 "register_operand" "=d,d,a,a,a")
1437 (ashift:SI (match_operand:SI 1 "register_operand" "0,d,a,a,a")
1438 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1,P2,?P3P4")))]
1439 ""
1440 "@
1441 %0 <<= %2;
1442 %0 = %1 << %2%!
1443 %0 = %1 + %1;
1444 %0 = %1 << %2;
1445 #"
1446 "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
1447 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
1448 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
1449 "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
1450 [(set_attr "type" "shft,dsp32,shft,shft,*")])
1452 (define_insn "ashrsi3"
1453 [(set (match_operand:SI 0 "register_operand" "=d,d")
1454 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
1455 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5")))]
1456 ""
1457 "@
1458 %0 >>>= %2;
1459 %0 = %1 >>> %2%!"
1460 [(set_attr "type" "shft,dsp32")])
1462 (define_insn "ror_one"
1463 [(set (match_operand:SI 0 "register_operand" "=d")
1464 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1465 (ashift:SI (zero_extend:SI (reg:BI REG_CC)) (const_int 31))))
1466 (set (reg:BI REG_CC)
1467 (zero_extract:BI (match_dup 1) (const_int 1) (const_int 0)))]
1468 ""
1469 "%0 = ROT %1 BY -1%!"
1470 [(set_attr "type" "dsp32")])
1472 (define_insn "rol_one"
1473 [(set (match_operand:SI 0 "register_operand" "+d")
1474 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1))
1475 (zero_extend:SI (reg:BI REG_CC))))
1476 (set (reg:BI REG_CC)
1477 (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))]
1478 ""
1479 "%0 = ROT %1 BY 1%!"
1480 [(set_attr "type" "dsp32")])
1482 (define_expand "lshrdi3"
1483 [(set (match_operand:DI 0 "register_operand" "")
1484 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
1485 (match_operand:DI 2 "general_operand" "")))]
1486 ""
1487 {
1488 rtx lo_half[2], hi_half[2];
1490 if (operands[2] != const1_rtx)
1491 FAIL;
1492 if (! rtx_equal_p (operands[0], operands[1]))
1493 emit_move_insn (operands[0], operands[1]);
1495 split_di (operands, 2, lo_half, hi_half);
1497 emit_move_insn (bfin_cc_rtx, const0_rtx);
1498 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1499 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1500 DONE;
1501 })
1503 (define_expand "ashrdi3"
1504 [(set (match_operand:DI 0 "register_operand" "")
1505 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
1506 (match_operand:DI 2 "general_operand" "")))]
1507 ""
1508 {
1509 rtx lo_half[2], hi_half[2];
1511 if (operands[2] != const1_rtx)
1512 FAIL;
1513 if (! rtx_equal_p (operands[0], operands[1]))
1514 emit_move_insn (operands[0], operands[1]);
1516 split_di (operands, 2, lo_half, hi_half);
1518 emit_insn (gen_compare_lt (gen_rtx_REG (BImode, REG_CC),
1519 hi_half[1], const0_rtx));
1520 emit_insn (gen_ror_one (hi_half[0], hi_half[0]));
1521 emit_insn (gen_ror_one (lo_half[0], lo_half[0]));
1522 DONE;
1523 })
1525 (define_expand "ashldi3"
1526 [(set (match_operand:DI 0 "register_operand" "")
1527 (ashift:DI (match_operand:DI 1 "register_operand" "")
1528 (match_operand:DI 2 "general_operand" "")))]
1529 ""
1530 {
1531 rtx lo_half[2], hi_half[2];
1533 if (operands[2] != const1_rtx)
1534 FAIL;
1535 if (! rtx_equal_p (operands[0], operands[1]))
1536 emit_move_insn (operands[0], operands[1]);
1538 split_di (operands, 2, lo_half, hi_half);
1540 emit_move_insn (bfin_cc_rtx, const0_rtx);
1541 emit_insn (gen_rol_one (lo_half[0], lo_half[0]));
1542 emit_insn (gen_rol_one (hi_half[0], hi_half[0]));
1543 DONE;
1544 })
1546 (define_insn "lshrsi3"
1547 [(set (match_operand:SI 0 "register_operand" "=d,d,a")
1548 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d,a")
1549 (match_operand:SI 2 "nonmemory_operand" "dKu5,Ku5,P1P2")))]
1550 ""
1551 "@
1552 %0 >>= %2;
1553 %0 = %1 >> %2%!
1554 %0 = %1 >> %2;"
1555 [(set_attr "type" "shft,dsp32,shft")])
1557 ;; A pattern to reload the equivalent of
1558 ;; (set (Dreg) (plus (FP) (large_constant)))
1559 ;; or
1560 ;; (set (dagreg) (plus (FP) (arbitrary_constant)))
1561 ;; using a scratch register
1562 (define_expand "reload_insi"
1563 [(parallel [(set (match_operand:SI 0 "register_operand" "=w")
1564 (match_operand:SI 1 "fp_plus_const_operand" ""))
1565 (clobber (match_operand:SI 2 "register_operand" "=&a"))])]
1566 ""
1567 {
1568 rtx fp_op = XEXP (operands[1], 0);
1569 rtx const_op = XEXP (operands[1], 1);
1570 rtx primary = operands[0];
1571 rtx scratch = operands[2];
1573 emit_move_insn (scratch, const_op);
1574 emit_insn (gen_addsi3 (scratch, scratch, fp_op));
1575 emit_move_insn (primary, scratch);
1576 DONE;
1577 })
1579 ;; Jump instructions
1581 (define_insn "jump"
1582 [(set (pc)
1583 (label_ref (match_operand 0 "" "")))]
1584 ""
1585 {
1586 if (get_attr_length (insn) == 2)
1587 return "jump.s %0;";
1588 else
1589 return "jump.l %0;";
1590 }
1591 [(set_attr "type" "br")])
1593 (define_insn "indirect_jump"
1594 [(set (pc)
1595 (match_operand:SI 0 "register_operand" "a"))]
1596 ""
1597 "jump (%0);"
1598 [(set_attr "type" "misc")])
1600 (define_expand "tablejump"
1601 [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1602 (use (label_ref (match_operand 1 "" "")))])]
1603 ""
1604 {
1605 /* In PIC mode, the table entries are stored PC relative.
1606 Convert the relative address to an absolute address. */
1607 if (flag_pic)
1608 {
1609 rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
1611 operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
1612 op1, NULL_RTX, 0, OPTAB_DIRECT);
1613 }
1614 })
1616 (define_insn "*tablejump_internal"
1617 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1618 (use (label_ref (match_operand 1 "" "")))]
1619 ""
1620 "jump (%0);"
1621 [(set_attr "type" "misc")])
1623 ;; Hardware loop
1625 ; operand 0 is the loop count pseudo register
1626 ; operand 1 is the number of loop iterations or 0 if it is unknown
1627 ; operand 2 is the maximum number of loop iterations
1628 ; operand 3 is the number of levels of enclosed loops
1629 ; operand 4 is the label to jump to at the top of the loop
1630 (define_expand "doloop_end"
1631 [(parallel [(set (pc) (if_then_else
1632 (ne (match_operand:SI 0 "" "")
1633 (const_int 1))
1634 (label_ref (match_operand 4 "" ""))
1635 (pc)))
1636 (set (match_dup 0)
1637 (plus:SI (match_dup 0)
1638 (const_int -1)))
1639 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1640 (clobber (match_scratch:SI 5 ""))])]
1641 ""
1642 {
1643 /* Due to limitations in the hardware (an initial loop count of 0
1644 does not loop 2^32 times) we must avoid to generate a hardware
1645 loops when we cannot rule out this case. */
1647 if (!flag_unsafe_loop_optimizations
1648 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 0xFFFFFFFF)
1649 FAIL;
1650 bfin_hardware_loop ();
1651 })
1653 (define_insn "loop_end"
1654 [(set (pc)
1655 (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+a*d,*b*v*f,m")
1656 (const_int 1))
1657 (label_ref (match_operand 1 "" ""))
1658 (pc)))
1659 (set (match_dup 0)
1660 (plus (match_dup 0)
1661 (const_int -1)))
1662 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1663 (clobber (match_scratch:SI 2 "=X,&r,&r"))]
1664 ""
1665 "@
1666 /* loop end %0 %l1 */
1667 #
1668 #"
1669 [(set_attr "length" "6,10,14")])
1671 (define_split
1672 [(set (pc)
1673 (if_then_else (ne (match_operand:SI 0 "nondp_reg_or_memory_operand" "")
1674 (const_int 1))
1675 (label_ref (match_operand 1 "" ""))
1676 (pc)))
1677 (set (match_dup 0)
1678 (plus (match_dup 0)
1679 (const_int -1)))
1680 (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1681 (clobber (match_scratch:SI 2 "=&r"))]
1682 "reload_completed"
1683 [(set (match_dup 2) (match_dup 0))
1684 (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
1685 (set (match_dup 0) (match_dup 2))
1686 (set (reg:BI REG_CC) (eq:BI (match_dup 2) (const_int 0)))
1687 (set (pc)
1688 (if_then_else (eq (reg:BI REG_CC)
1689 (const_int 0))
1690 (label_ref (match_dup 1))
1691 (pc)))]
1692 "")
1694 (define_insn "lsetup_with_autoinit"
1695 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1696 (label_ref (match_operand 1 "" "")))
1697 (set (match_operand:SI 2 "lb_register_operand" "=u")
1698 (label_ref (match_operand 3 "" "")))
1699 (set (match_operand:SI 4 "lc_register_operand" "=k")
1700 (match_operand:SI 5 "register_operand" "a"))]
1701 ""
1702 "LSETUP (%1, %3) %4 = %5;"
1703 [(set_attr "length" "4")])
1705 (define_insn "lsetup_without_autoinit"
1706 [(set (match_operand:SI 0 "lt_register_operand" "=t")
1707 (label_ref (match_operand 1 "" "")))
1708 (set (match_operand:SI 2 "lb_register_operand" "=u")
1709 (label_ref (match_operand 3 "" "")))
1710 (use (match_operand:SI 4 "lc_register_operand" "k"))]
1711 ""
1712 "LSETUP (%1, %3) %4;"
1713 [(set_attr "length" "4")])
1715 ;; Call instructions..
1717 ;; The explicit MEM inside the UNSPEC prevents the compiler from moving
1718 ;; the load before a branch after a NULL test, or before a store that
1719 ;; initializes a function descriptor.
1721 (define_insn_and_split "load_funcdescsi"
1722 [(set (match_operand:SI 0 "register_operand" "=a")
1723 (unspec_volatile:SI [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
1724 UNSPEC_VOLATILE_LOAD_FUNCDESC))]
1725 ""
1726 "#"
1727 "reload_completed"
1728 [(set (match_dup 0) (mem:SI (match_dup 1)))])
1730 (define_expand "call"
1731 [(parallel [(call (match_operand:SI 0 "" "")
1732 (match_operand 1 "" ""))
1733 (use (match_operand 2 "" ""))])]
1734 ""
1735 {
1736 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 0);
1737 DONE;
1738 })
1740 (define_expand "sibcall"
1741 [(parallel [(call (match_operand:SI 0 "" "")
1742 (match_operand 1 "" ""))
1743 (use (match_operand 2 "" ""))
1744 (return)])]
1745 ""
1746 {
1747 bfin_expand_call (NULL_RTX, operands[0], operands[1], operands[2], 1);
1748 DONE;
1749 })
1751 (define_expand "call_value"
1752 [(parallel [(set (match_operand 0 "register_operand" "")
1753 (call (match_operand:SI 1 "" "")
1754 (match_operand 2 "" "")))
1755 (use (match_operand 3 "" ""))])]
1756 ""
1757 {
1758 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 0);
1759 DONE;
1760 })
1762 (define_expand "sibcall_value"
1763 [(parallel [(set (match_operand 0 "register_operand" "")
1764 (call (match_operand:SI 1 "" "")
1765 (match_operand 2 "" "")))
1766 (use (match_operand 3 "" ""))
1767 (return)])]
1768 ""
1769 {
1770 bfin_expand_call (operands[0], operands[1], operands[2], operands[3], 1);
1771 DONE;
1772 })
1774 (define_insn "*call_symbol_fdpic"
1775 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1776 (match_operand 1 "general_operand" "g"))
1777 (use (match_operand:SI 2 "register_operand" "Z"))
1778 (use (match_operand 3 "" ""))]
1779 "! SIBLING_CALL_P (insn)
1780 && GET_CODE (operands[0]) == SYMBOL_REF
1781 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1782 "call %0;"
1783 [(set_attr "type" "call")
1784 (set_attr "length" "4")])
1786 (define_insn "*sibcall_symbol_fdpic"
1787 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1788 (match_operand 1 "general_operand" "g"))
1789 (use (match_operand:SI 2 "register_operand" "Z"))
1790 (use (match_operand 3 "" ""))
1791 (return)]
1792 "SIBLING_CALL_P (insn)
1793 && GET_CODE (operands[0]) == SYMBOL_REF
1794 && !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
1795 "jump.l %0;"
1796 [(set_attr "type" "br")
1797 (set_attr "length" "4")])
1799 (define_insn "*call_value_symbol_fdpic"
1800 [(set (match_operand 0 "register_operand" "=d")
1801 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1802 (match_operand 2 "general_operand" "g")))
1803 (use (match_operand:SI 3 "register_operand" "Z"))
1804 (use (match_operand 4 "" ""))]
1805 "! SIBLING_CALL_P (insn)
1806 && GET_CODE (operands[1]) == SYMBOL_REF
1807 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1808 "call %1;"
1809 [(set_attr "type" "call")
1810 (set_attr "length" "4")])
1812 (define_insn "*sibcall_value_symbol_fdpic"
1813 [(set (match_operand 0 "register_operand" "=d")
1814 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1815 (match_operand 2 "general_operand" "g")))
1816 (use (match_operand:SI 3 "register_operand" "Z"))
1817 (use (match_operand 4 "" ""))
1818 (return)]
1819 "SIBLING_CALL_P (insn)
1820 && GET_CODE (operands[1]) == SYMBOL_REF
1821 && !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
1822 "jump.l %1;"
1823 [(set_attr "type" "br")
1824 (set_attr "length" "4")])
1826 (define_insn "*call_insn_fdpic"
1827 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1828 (match_operand 1 "general_operand" "g"))
1829 (use (match_operand:SI 2 "register_operand" "Z"))
1830 (use (match_operand 3 "" ""))]
1831 "! SIBLING_CALL_P (insn)"
1832 "call (%0);"
1833 [(set_attr "type" "call")
1834 (set_attr "length" "2")])
1836 (define_insn "*sibcall_insn_fdpic"
1837 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "Y"))
1838 (match_operand 1 "general_operand" "g"))
1839 (use (match_operand:SI 2 "register_operand" "Z"))
1840 (use (match_operand 3 "" ""))
1841 (return)]
1842 "SIBLING_CALL_P (insn)"
1843 "jump (%0);"
1844 [(set_attr "type" "br")
1845 (set_attr "length" "2")])
1847 (define_insn "*call_value_insn_fdpic"
1848 [(set (match_operand 0 "register_operand" "=d")
1849 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1850 (match_operand 2 "general_operand" "g")))
1851 (use (match_operand:SI 3 "register_operand" "Z"))
1852 (use (match_operand 4 "" ""))]
1853 "! SIBLING_CALL_P (insn)"
1854 "call (%1);"
1855 [(set_attr "type" "call")
1856 (set_attr "length" "2")])
1858 (define_insn "*sibcall_value_insn_fdpic"
1859 [(set (match_operand 0 "register_operand" "=d")
1860 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "Y"))
1861 (match_operand 2 "general_operand" "g")))
1862 (use (match_operand:SI 3 "register_operand" "Z"))
1863 (use (match_operand 4 "" ""))
1864 (return)]
1865 "SIBLING_CALL_P (insn)"
1866 "jump (%1);"
1867 [(set_attr "type" "br")
1868 (set_attr "length" "2")])
1870 (define_insn "*call_symbol"
1871 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1872 (match_operand 1 "general_operand" "g"))
1873 (use (match_operand 2 "" ""))]
1874 "! SIBLING_CALL_P (insn)
1875 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1876 && GET_CODE (operands[0]) == SYMBOL_REF
1877 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1878 "call %0;"
1879 [(set_attr "type" "call")
1880 (set_attr "length" "4")])
1882 (define_insn "*sibcall_symbol"
1883 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "Q"))
1884 (match_operand 1 "general_operand" "g"))
1885 (use (match_operand 2 "" ""))
1886 (return)]
1887 "SIBLING_CALL_P (insn)
1888 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1889 && GET_CODE (operands[0]) == SYMBOL_REF
1890 && !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
1891 "jump.l %0;"
1892 [(set_attr "type" "br")
1893 (set_attr "length" "4")])
1895 (define_insn "*call_value_symbol"
1896 [(set (match_operand 0 "register_operand" "=d")
1897 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1898 (match_operand 2 "general_operand" "g")))
1899 (use (match_operand 3 "" ""))]
1900 "! SIBLING_CALL_P (insn)
1901 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1902 && GET_CODE (operands[1]) == SYMBOL_REF
1903 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
1904 "call %1;"
1905 [(set_attr "type" "call")
1906 (set_attr "length" "4")])
1908 (define_insn "*sibcall_value_symbol"
1909 [(set (match_operand 0 "register_operand" "=d")
1910 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "Q"))
1911 (match_operand 2 "general_operand" "g")))
1912 (use (match_operand 3 "" ""))
1913 (return)]
1914 "SIBLING_CALL_P (insn)
1915 && (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
1916 && GET_CODE (operands[1]) == SYMBOL_REF
1917 && !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
1918 "jump.l %1;"
1919 [(set_attr "type" "br")
1920 (set_attr "length" "4")])
1922 (define_insn "*call_insn"
1923 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "a"))
1924 (match_operand 1 "general_operand" "g"))
1925 (use (match_operand 2 "" ""))]
1926 "! SIBLING_CALL_P (insn)"
1927 "call (%0);"
1928 [(set_attr "type" "call")
1929 (set_attr "length" "2")])
1931 (define_insn "*sibcall_insn"
1932 [(call (mem:SI (match_operand:SI 0 "register_no_elim_operand" "z"))
1933 (match_operand 1 "general_operand" "g"))
1934 (use (match_operand 2 "" ""))
1935 (return)]
1936 "SIBLING_CALL_P (insn)"
1937 "jump (%0);"
1938 [(set_attr "type" "br")
1939 (set_attr "length" "2")])
1941 (define_insn "*call_value_insn"
1942 [(set (match_operand 0 "register_operand" "=d")
1943 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "a"))
1944 (match_operand 2 "general_operand" "g")))
1945 (use (match_operand 3 "" ""))]
1946 "! SIBLING_CALL_P (insn)"
1947 "call (%1);"
1948 [(set_attr "type" "call")
1949 (set_attr "length" "2")])
1951 (define_insn "*sibcall_value_insn"
1952 [(set (match_operand 0 "register_operand" "=d")
1953 (call (mem:SI (match_operand:SI 1 "register_no_elim_operand" "z"))
1954 (match_operand 2 "general_operand" "g")))
1955 (use (match_operand 3 "" ""))
1956 (return)]
1957 "SIBLING_CALL_P (insn)"
1958 "jump (%1);"
1959 [(set_attr "type" "br")
1960 (set_attr "length" "2")])
1962 ;; Block move patterns
1964 ;; We cheat. This copies one more word than operand 2 indicates.
1966 (define_insn "rep_movsi"
1967 [(set (match_operand:SI 0 "register_operand" "=&a")
1968 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
1969 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1970 (const_int 2)))
1971 (const_int 4)))
1972 (set (match_operand:SI 1 "register_operand" "=&b")
1973 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
1974 (ashift:SI (match_dup 2) (const_int 2)))
1975 (const_int 4)))
1976 (set (mem:BLK (match_dup 3))
1977 (mem:BLK (match_dup 4)))
1978 (use (match_dup 2))
1979 (clobber (match_scratch:HI 5 "=&d"))
1980 (clobber (reg:SI REG_LT1))
1981 (clobber (reg:SI REG_LC1))
1982 (clobber (reg:SI REG_LB1))]
1983 ""
1984 "%5 = [%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
1985 [(set_attr "type" "misc")
1986 (set_attr "length" "16")
1987 (set_attr "seq_insns" "multi")])
1989 (define_insn "rep_movhi"
1990 [(set (match_operand:SI 0 "register_operand" "=&a")
1991 (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0")
1992 (ashift:SI (match_operand:SI 2 "register_operand" "a")
1993 (const_int 1)))
1994 (const_int 2)))
1995 (set (match_operand:SI 1 "register_operand" "=&b")
1996 (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1")
1997 (ashift:SI (match_dup 2) (const_int 1)))
1998 (const_int 2)))
1999 (set (mem:BLK (match_dup 3))
2000 (mem:BLK (match_dup 4)))
2001 (use (match_dup 2))
2002 (clobber (match_scratch:HI 5 "=&d"))
2003 (clobber (reg:SI REG_LT1))
2004 (clobber (reg:SI REG_LC1))
2005 (clobber (reg:SI REG_LB1))]
2006 ""
2007 "%h5 = W[%4++]; lsetup (1f, 1f) LC1 = %2; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
2008 [(set_attr "type" "misc")
2009 (set_attr "length" "16")
2010 (set_attr "seq_insns" "multi")])
2012 (define_expand "movmemsi"
2013 [(match_operand:BLK 0 "general_operand" "")
2014 (match_operand:BLK 1 "general_operand" "")
2015 (match_operand:SI 2 "const_int_operand" "")
2016 (match_operand:SI 3 "const_int_operand" "")]
2017 ""
2018 {
2019 if (bfin_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
2020 DONE;
2021 FAIL;
2022 })
2024 ;; Conditional branch patterns
2025 ;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu
2027 ;; The only outcome of this pattern is that global variables
2028 ;; bfin_compare_op[01] are set for use in bcond patterns.
2030 (define_expand "cmpbi"
2031 [(set (cc0) (compare (match_operand:BI 0 "register_operand" "")
2032 (match_operand:BI 1 "immediate_operand" "")))]
2033 ""
2034 {
2035 bfin_compare_op0 = operands[0];
2036 bfin_compare_op1 = operands[1];
2037 DONE;
2038 })
2040 (define_expand "cmpsi"
2041 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2042 (match_operand:SI 1 "reg_or_const_int_operand" "")))]
2043 ""
2044 {
2045 bfin_compare_op0 = operands[0];
2046 bfin_compare_op1 = operands[1];
2047 DONE;
2048 })
2050 (define_insn "compare_eq"
2051 [(set (match_operand:BI 0 "register_operand" "=C,C")
2052 (eq:BI (match_operand:SI 1 "register_operand" "d,a")
2053 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2054 ""
2055 "cc =%1==%2;"
2056 [(set_attr "type" "compare")])
2058 (define_insn "compare_ne"
2059 [(set (match_operand:BI 0 "register_operand" "=C,C")
2060 (ne:BI (match_operand:SI 1 "register_operand" "d,a")
2061 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2062 "0"
2063 "cc =%1!=%2;"
2064 [(set_attr "type" "compare")])
2066 (define_insn "compare_lt"
2067 [(set (match_operand:BI 0 "register_operand" "=C,C")
2068 (lt:BI (match_operand:SI 1 "register_operand" "d,a")
2069 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2070 ""
2071 "cc =%1<%2;"
2072 [(set_attr "type" "compare")])
2074 (define_insn "compare_le"
2075 [(set (match_operand:BI 0 "register_operand" "=C,C")
2076 (le:BI (match_operand:SI 1 "register_operand" "d,a")
2077 (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))]
2078 ""
2079 "cc =%1<=%2;"
2080 [(set_attr "type" "compare")])
2082 (define_insn "compare_leu"
2083 [(set (match_operand:BI 0 "register_operand" "=C,C")
2084 (leu:BI (match_operand:SI 1 "register_operand" "d,a")
2085 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2086 ""
2087 "cc =%1<=%2 (iu);"
2088 [(set_attr "type" "compare")])
2090 (define_insn "compare_ltu"
2091 [(set (match_operand:BI 0 "register_operand" "=C,C")
2092 (ltu:BI (match_operand:SI 1 "register_operand" "d,a")
2093 (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))]
2094 ""
2095 "cc =%1<%2 (iu);"
2096 [(set_attr "type" "compare")])
2098 (define_expand "beq"
2099 [(set (match_dup 1) (match_dup 2))
2100 (set (pc)
2101 (if_then_else (match_dup 3)
2102 (label_ref (match_operand 0 "" ""))
2103 (pc)))]
2104 ""
2105 {
2106 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2107 operands[1] = bfin_cc_rtx; /* hard register: CC */
2108 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2109 /* If we have a BImode input, then we already have a compare result, and
2110 do not need to emit another comparison. */
2111 if (GET_MODE (bfin_compare_op0) == BImode)
2112 {
2113 gcc_assert (bfin_compare_op1 == const0_rtx);
2114 emit_insn (gen_cbranchbi4 (operands[2], op0, op1, operands[0]));
2115 DONE;
2116 }
2118 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2119 })
2121 (define_expand "bne"
2122 [(set (match_dup 1) (match_dup 2))
2123 (set (pc)
2124 (if_then_else (match_dup 3)
2125 (label_ref (match_operand 0 "" ""))
2126 (pc)))]
2127 ""
2128 {
2129 rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
2130 /* If we have a BImode input, then we already have a compare result, and
2131 do not need to emit another comparison. */
2132 if (GET_MODE (bfin_compare_op0) == BImode)
2133 {
2134 rtx cmp = gen_rtx_NE (BImode, op0, op1);
2136 gcc_assert (bfin_compare_op1 == const0_rtx);
2137 emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
2138 DONE;
2139 }
2141 operands[1] = bfin_cc_rtx; /* hard register: CC */
2142 operands[2] = gen_rtx_EQ (BImode, op0, op1);
2143 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2144 })
2146 (define_expand "bgt"
2147 [(set (match_dup 1) (match_dup 2))
2148 (set (pc)
2149 (if_then_else (match_dup 3)
2150 (label_ref (match_operand 0 "" ""))
2151 (pc)))]
2152 ""
2153 {
2154 operands[1] = bfin_cc_rtx;
2155 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2156 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2157 })
2159 (define_expand "bgtu"
2160 [(set (match_dup 1) (match_dup 2))
2161 (set (pc)
2162 (if_then_else (match_dup 3)
2163 (label_ref (match_operand 0 "" ""))
2164 (pc)))]
2165 ""
2166 {
2167 operands[1] = bfin_cc_rtx;
2168 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2169 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2170 })
2172 (define_expand "blt"
2173 [(set (match_dup 1) (match_dup 2))
2174 (set (pc)
2175 (if_then_else (match_dup 3)
2176 (label_ref (match_operand 0 "" ""))
2177 (pc)))]
2178 ""
2179 {
2180 operands[1] = bfin_cc_rtx;
2181 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2182 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2183 })
2185 (define_expand "bltu"
2186 [(set (match_dup 1) (match_dup 2))
2187 (set (pc)
2188 (if_then_else (match_dup 3)
2189 (label_ref (match_operand 0 "" ""))
2190 (pc)))]
2191 ""
2192 {
2193 operands[1] = bfin_cc_rtx;
2194 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2195 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2196 })
2199 (define_expand "bge"
2200 [(set (match_dup 1) (match_dup 2))
2201 (set (pc)
2202 (if_then_else (match_dup 3)
2203 (label_ref (match_operand 0 "" ""))
2204 (pc)))]
2205 ""
2206 {
2207 operands[1] = bfin_cc_rtx;
2208 operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
2209 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2210 })
2212 (define_expand "bgeu"
2213 [(set (match_dup 1) (match_dup 2))
2214 (set (pc)
2215 (if_then_else (match_dup 3)
2216 (label_ref (match_operand 0 "" ""))
2217 (pc)))]
2218 ""
2219 {
2220 operands[1] = bfin_cc_rtx;
2221 operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
2222 operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
2223 })
2225 (define_expand "ble"
2226 [(set (match_dup 1) (match_dup 2))
2227 (set (pc)
2228 (if_then_else (match_dup 3)
2229 (label_ref (match_operand 0 "" ""))
2230 (pc)))]
2231 ""
2232 {
2233 operands[1] = bfin_cc_rtx;
2234 operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
2235 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2236 })
2238 (define_expand "bleu"
2239 [(set (match_dup 1) (match_dup 2))
2240 (set (pc)
2241 (if_then_else (match_dup 3)
2242 (label_ref (match_operand 0 "" ""))
2243 (pc)))
2244 ]
2245 ""
2246 {
2247 operands[1] = bfin_cc_rtx;
2248 operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
2249 operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
2250 })
2252 (define_insn "cbranchbi4"
2253 [(set (pc)
2254 (if_then_else
2255 (match_operator 0 "bfin_cbranch_operator"
2256 [(match_operand:BI 1 "register_operand" "C")
2257 (match_operand:BI 2 "immediate_operand" "P0")])
2258 (label_ref (match_operand 3 "" ""))
2259 (pc)))]
2260 ""
2261 {
2262 asm_conditional_branch (insn, operands, 0, 0);
2263 return "";
2264 }
2265 [(set_attr "type" "brcc")])
2267 ;; Special cbranch patterns to deal with the speculative load problem - see
2268 ;; bfin_reorg for details.
2270 (define_insn "cbranch_predicted_taken"
2271 [(set (pc)
2272 (if_then_else
2273 (match_operator 0 "bfin_cbranch_operator"
2274 [(match_operand:BI 1 "register_operand" "C")
2275 (match_operand:BI 2 "immediate_operand" "P0")])
2276 (label_ref (match_operand 3 "" ""))
2277 (pc)))
2278 (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
2279 ""
2280 {
2281 asm_conditional_branch (insn, operands, 0, 1);
2282 return "";
2283 }
2284 [(set_attr "type" "brcc")])
2286 (define_insn "cbranch_with_nops"
2287 [(set (pc)
2288 (if_then_else
2289 (match_operator 0 "bfin_cbranch_operator"
2290 [(match_operand:BI 1 "register_operand" "C")
2291 (match_operand:BI 2 "immediate_operand" "P0")])
2292 (label_ref (match_operand 3 "" ""))
2293 (pc)))
2294 (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
2295 "reload_completed"
2296 {
2297 asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
2298 return "";
2299 }
2300 [(set_attr "type" "brcc")
2301 (set_attr "length" "6")])
2303 ;; setcc insns. */
2304 (define_expand "seq"
2305 [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3)))
2306 (set (match_operand:SI 0 "register_operand" "")
2307 (ne:SI (match_dup 1) (const_int 0)))]
2308 ""
2309 {
2310 operands[2] = bfin_compare_op0;
2311 operands[3] = bfin_compare_op1;
2312 operands[1] = bfin_cc_rtx;
2313 })
2315 (define_expand "slt"
2316 [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3)))
2317 (set (match_operand:SI 0 "register_operand" "")
2318 (ne:SI (match_dup 1) (const_int 0)))]
2319 ""
2320 {
2321 operands[2] = bfin_compare_op0;
2322 operands[3] = bfin_compare_op1;
2323 operands[1] = bfin_cc_rtx;
2324 })
2326 (define_expand "sle"
2327 [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3)))
2328 (set (match_operand:SI 0 "register_operand" "")
2329 (ne:SI (match_dup 1) (const_int 0)))]
2330 ""
2331 {
2332 operands[2] = bfin_compare_op0;
2333 operands[3] = bfin_compare_op1;
2334 operands[1] = bfin_cc_rtx;
2335 })
2337 (define_expand "sltu"
2338 [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3)))
2339 (set (match_operand:SI 0 "register_operand" "")
2340 (ne:SI (match_dup 1) (const_int 0)))]
2341 ""
2342 {
2343 operands[2] = bfin_compare_op0;
2344 operands[3] = bfin_compare_op1;
2345 operands[1] = bfin_cc_rtx;
2346 })
2348 (define_expand "sleu"
2349 [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
2350 (set (match_operand:SI 0 "register_operand" "")
2351 (ne:SI (match_dup 1) (const_int 0)))]
2352 ""
2353 {
2354 operands[2] = bfin_compare_op0;
2355 operands[3] = bfin_compare_op1;
2356 operands[1] = bfin_cc_rtx;
2357 })
2359 (define_insn "nop"
2360 [(const_int 0)]
2361 ""
2362 "nop;")
2364 (define_insn "mnop"
2365 [(unspec [(const_int 0)] UNSPEC_32BIT)]
2366 ""
2367 "mnop%!"
2368 [(set_attr "type" "dsp32")])
2370 ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;;
2371 (define_insn "movsibi"
2372 [(set (match_operand:BI 0 "register_operand" "=C")
2373 (ne:BI (match_operand:SI 1 "register_operand" "d")
2374 (const_int 0)))]
2375 ""
2376 "CC = %1;"
2377 [(set_attr "length" "2")])
2379 (define_insn "movbisi"
2380 [(set (match_operand:SI 0 "register_operand" "=d")
2381 (ne:SI (match_operand:BI 1 "register_operand" "C")
2382 (const_int 0)))]
2383 ""
2384 "%0 = CC;"
2385 [(set_attr "length" "2")])
2387 (define_insn ""
2388 [(set (match_operand:BI 0 "register_operand" "=C")
2389 (eq:BI (match_operand:BI 1 "register_operand" " 0")
2390 (const_int 0)))]
2391 ""
2392 "%0 = ! %0;" /* NOT CC;" */
2393 [(set_attr "type" "compare")])
2395 ;; Vector and DSP insns
2397 (define_insn ""
2398 [(set (match_operand:SI 0 "register_operand" "=d")
2399 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2400 (const_int 24))
2401 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2402 (const_int 8))))]
2403 ""
2404 "%0 = ALIGN8(%1, %2)%!"
2405 [(set_attr "type" "dsp32")])
2407 (define_insn ""
2408 [(set (match_operand:SI 0 "register_operand" "=d")
2409 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2410 (const_int 16))
2411 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2412 (const_int 16))))]
2413 ""
2414 "%0 = ALIGN16(%1, %2)%!"
2415 [(set_attr "type" "dsp32")])
2417 (define_insn ""
2418 [(set (match_operand:SI 0 "register_operand" "=d")
2419 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d")
2420 (const_int 8))
2421 (lshiftrt:SI (match_operand:SI 2 "register_operand" "d")
2422 (const_int 24))))]
2423 ""
2424 "%0 = ALIGN24(%1, %2)%!"
2425 [(set_attr "type" "dsp32")])
2427 ;; Prologue and epilogue.
2429 (define_expand "prologue"
2430 [(const_int 1)]
2431 ""
2432 "bfin_expand_prologue (); DONE;")
2434 (define_expand "epilogue"
2435 [(const_int 1)]
2436 ""
2437 "bfin_expand_epilogue (1, 0); DONE;")
2439 (define_expand "sibcall_epilogue"
2440 [(const_int 1)]
2441 ""
2442 "bfin_expand_epilogue (0, 0); DONE;")
2444 (define_expand "eh_return"
2445 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")]
2446 UNSPEC_VOLATILE_EH_RETURN)]
2447 ""
2448 {
2449 emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]);
2450 emit_jump_insn (gen_eh_return_internal ());
2451 emit_barrier ();
2452 DONE;
2453 })
2455 (define_insn_and_split "eh_return_internal"
2456 [(set (pc)
2457 (unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN))]
2458 ""
2459 "#"
2460 "reload_completed"
2461 [(const_int 1)]
2462 "bfin_expand_epilogue (1, 1); DONE;")
2464 (define_insn "link"
2465 [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
2466 (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
2467 (set (reg:SI REG_FP)
2468 (plus:SI (reg:SI REG_SP) (const_int -8)))
2469 (set (reg:SI REG_SP)
2470 (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
2471 ""
2472 "LINK %Z0;"
2473 [(set_attr "length" "4")])
2475 (define_insn "unlink"
2476 [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
2477 (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
2478 (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
2479 ""
2480 "UNLINK;"
2481 [(set_attr "length" "4")])
2483 ;; This pattern is slightly clumsy. The stack adjust must be the final SET in
2484 ;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
2485 ;; where on the stack, since it goes through all elements of the parallel in
2486 ;; sequence.
2487 (define_insn "push_multiple"
2488 [(match_parallel 0 "push_multiple_operation"
2489 [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
2490 ""
2491 {
2492 output_push_multiple (insn, operands);
2493 return "";
2494 })
2496 (define_insn "pop_multiple"
2497 [(match_parallel 0 "pop_multiple_operation"
2498 [(set (reg:SI REG_SP)
2499 (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
2500 ""
2501 {
2502 output_pop_multiple (insn, operands);
2503 return "";
2504 })
2506 (define_insn "return_internal"
2507 [(return)
2508 (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)]
2509 "reload_completed"
2510 {
2511 switch (INTVAL (operands[0]))
2512 {
2513 case EXCPT_HANDLER:
2514 return "rtx;";
2515 case NMI_HANDLER:
2516 return "rtn;";
2517 case INTERRUPT_HANDLER:
2518 return "rti;";
2519 case SUBROUTINE:
2520 return "rts;";
2521 }
2522 gcc_unreachable ();
2523 })
2525 (define_insn "csync"
2526 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
2527 ""
2528 "csync;"
2529 [(set_attr "type" "sync")])
2531 (define_insn "ssync"
2532 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_SSYNC)]
2533 ""
2534 "ssync;"
2535 [(set_attr "type" "sync")])
2537 (define_insn "trap"
2538 [(trap_if (const_int 1) (const_int 3))]
2539 ""
2540 "excpt 3;"
2541 [(set_attr "type" "misc")
2542 (set_attr "length" "2")])
2544 (define_insn "trapifcc"
2545 [(trap_if (reg:BI REG_CC) (const_int 3))]
2546 ""
2547 "if !cc jump 4 (bp); excpt 3;"
2548 [(set_attr "type" "misc")
2549 (set_attr "length" "4")
2550 (set_attr "seq_insns" "multi")])
2552 ;;; Vector instructions
2554 ;; First, all sorts of move variants
2556 (define_insn "movhi_low2high"
2557 [(set (match_operand:V2HI 0 "register_operand" "=d")
2558 (vec_concat:V2HI
2559 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2560 (parallel [(const_int 0)]))
2561 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2562 (parallel [(const_int 0)]))))]
2563 ""
2564 "%d0 = %h2 << 0%!"
2565 [(set_attr "type" "dsp32")])
2567 (define_insn "movhi_high2high"
2568 [(set (match_operand:V2HI 0 "register_operand" "=d")
2569 (vec_concat:V2HI
2570 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2571 (parallel [(const_int 0)]))
2572 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2573 (parallel [(const_int 1)]))))]
2574 ""
2575 "%d0 = %d2 << 0%!"
2576 [(set_attr "type" "dsp32")])
2578 (define_insn "movhi_low2low"
2579 [(set (match_operand:V2HI 0 "register_operand" "=d")
2580 (vec_concat:V2HI
2581 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2582 (parallel [(const_int 0)]))
2583 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2584 (parallel [(const_int 1)]))))]
2585 ""
2586 "%h0 = %h2 << 0%!"
2587 [(set_attr "type" "dsp32")])
2589 (define_insn "movhi_high2low"
2590 [(set (match_operand:V2HI 0 "register_operand" "=d")
2591 (vec_concat:V2HI
2592 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2593 (parallel [(const_int 1)]))
2594 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2595 (parallel [(const_int 1)]))))]
2596 ""
2597 "%h0 = %d2 << 0%!"
2598 [(set_attr "type" "dsp32")])
2600 (define_insn "movhiv2hi_low"
2601 [(set (match_operand:V2HI 0 "register_operand" "=d")
2602 (vec_concat:V2HI
2603 (match_operand:HI 2 "register_operand" "d")
2604 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2605 (parallel [(const_int 1)]))))]
2606 ""
2607 "%h0 = %h2 << 0%!"
2608 [(set_attr "type" "dsp32")])
2610 (define_insn "movhiv2hi_high"
2611 [(set (match_operand:V2HI 0 "register_operand" "=d")
2612 (vec_concat:V2HI
2613 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
2614 (parallel [(const_int 0)]))
2615 (match_operand:HI 2 "register_operand" "d")))]
2616 ""
2617 "%d0 = %h2 << 0%!"
2618 [(set_attr "type" "dsp32")])
2620 ;; No earlyclobber on alternative two since our sequence ought to be safe.
2621 ;; The order of operands is intentional to match the VDSP builtin (high word
2622 ;; is passed first).
2623 (define_insn_and_split "composev2hi"
2624 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
2625 (vec_concat:V2HI (match_operand:HI 2 "register_operand" "0,d")
2626 (match_operand:HI 1 "register_operand" "d,d")))]
2627 ""
2628 "@
2629 %d0 = %h2 << 0%!
2630 #"
2631 "reload_completed"
2632 [(set (match_dup 0)
2633 (vec_concat:V2HI
2634 (vec_select:HI (match_dup 0) (parallel [(const_int 0)]))
2635 (match_dup 2)))
2636 (set (match_dup 0)
2637 (vec_concat:V2HI
2638 (match_dup 1)
2639 (vec_select:HI (match_dup 0) (parallel [(const_int 1)]))))]
2640 ""
2641 [(set_attr "type" "dsp32")])
2643 ; Like composev2hi, but operating on elements of V2HI vectors.
2644 ; Useful on its own, and as a combiner bridge for the multiply and
2645 ; mac patterns.
2646 (define_insn "packv2hi"
2647 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d,d")
2648 (vec_concat:V2HI (vec_select:HI
2649 (match_operand:V2HI 1 "register_operand" "d,d,d,d")
2650 (parallel [(match_operand 3 "const01_operand" "P0,P1,P0,P1")]))
2651 (vec_select:HI
2652 (match_operand:V2HI 2 "register_operand" "d,d,d,d")
2653 (parallel [(match_operand 4 "const01_operand" "P0,P0,P1,P1")]))))]
2654 ""
2655 "@
2656 %0 = PACK (%h2,%h1)%!
2657 %0 = PACK (%h2,%d1)%!
2658 %0 = PACK (%d2,%h1)%!
2659 %0 = PACK (%d2,%d1)%!"
2660 [(set_attr "type" "dsp32")])
2662 (define_insn "movv2hi_hi"
2663 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2664 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,d,d")
2665 (parallel [(match_operand 2 "const01_operand" "P0,P0,P1")])))]
2666 ""
2667 "@
2668 /* optimized out */
2669 %h0 = %h1 << 0%!
2670 %h0 = %d1 << 0%!"
2671 [(set_attr "type" "dsp32")])
2673 (define_expand "movv2hi_hi_low"
2674 [(set (match_operand:HI 0 "register_operand" "")
2675 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2676 (parallel [(const_int 0)])))]
2677 ""
2678 "")
2680 (define_expand "movv2hi_hi_high"
2681 [(set (match_operand:HI 0 "register_operand" "")
2682 (vec_select:HI (match_operand:V2HI 1 "register_operand" "")
2683 (parallel [(const_int 1)])))]
2684 ""
2685 "")
2687 ;; Unusual arithmetic operations on 16-bit registers.
2689 (define_insn "ssaddhi3"
2690 [(set (match_operand:HI 0 "register_operand" "=d")
2691 (ss_plus:HI (match_operand:HI 1 "register_operand" "d")
2692 (match_operand:HI 2 "register_operand" "d")))]
2693 ""
2694 "%h0 = %h1 + %h2 (S)%!"
2695 [(set_attr "type" "dsp32")])
2697 (define_insn "sssubhi3"
2698 [(set (match_operand:HI 0 "register_operand" "=d")
2699 (ss_minus:HI (match_operand:HI 1 "register_operand" "d")
2700 (match_operand:HI 2 "register_operand" "d")))]
2701 ""
2702 "%h0 = %h1 - %h2 (S)%!"
2703 [(set_attr "type" "dsp32")])
2705 ;; V2HI vector insns
2707 (define_insn "addv2hi3"
2708 [(set (match_operand:V2HI 0 "register_operand" "=d")
2709 (plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2710 (match_operand:V2HI 2 "register_operand" "d")))]
2711 ""
2712 "%0 = %1 +|+ %2%!"
2713 [(set_attr "type" "dsp32")])
2715 (define_insn "ssaddv2hi3"
2716 [(set (match_operand:V2HI 0 "register_operand" "=d")
2717 (ss_plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2718 (match_operand:V2HI 2 "register_operand" "d")))]
2719 ""
2720 "%0 = %1 +|+ %2 (S)%!"
2721 [(set_attr "type" "dsp32")])
2723 (define_insn "subv2hi3"
2724 [(set (match_operand:V2HI 0 "register_operand" "=d")
2725 (minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2726 (match_operand:V2HI 2 "register_operand" "d")))]
2727 ""
2728 "%0 = %1 -|- %2%!"
2729 [(set_attr "type" "dsp32")])
2731 (define_insn "sssubv2hi3"
2732 [(set (match_operand:V2HI 0 "register_operand" "=d")
2733 (ss_minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
2734 (match_operand:V2HI 2 "register_operand" "d")))]
2735 ""
2736 "%0 = %1 -|- %2 (S)%!"
2737 [(set_attr "type" "dsp32")])
2739 (define_insn "addsubv2hi3"
2740 [(set (match_operand:V2HI 0 "register_operand" "=d")
2741 (vec_concat:V2HI
2742 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2743 (parallel [(const_int 0)]))
2744 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2745 (parallel [(const_int 0)])))
2746 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2747 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2748 ""
2749 "%0 = %1 +|- %2%!"
2750 [(set_attr "type" "dsp32")])
2752 (define_insn "subaddv2hi3"
2753 [(set (match_operand:V2HI 0 "register_operand" "=d")
2754 (vec_concat:V2HI
2755 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2756 (parallel [(const_int 0)]))
2757 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2758 (parallel [(const_int 0)])))
2759 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2760 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2761 ""
2762 "%0 = %1 -|+ %2%!"
2763 [(set_attr "type" "dsp32")])
2765 (define_insn "ssaddsubv2hi3"
2766 [(set (match_operand:V2HI 0 "register_operand" "=d")
2767 (vec_concat:V2HI
2768 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2769 (parallel [(const_int 0)]))
2770 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2771 (parallel [(const_int 0)])))
2772 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2773 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2774 ""
2775 "%0 = %1 +|- %2 (S)%!"
2776 [(set_attr "type" "dsp32")])
2778 (define_insn "sssubaddv2hi3"
2779 [(set (match_operand:V2HI 0 "register_operand" "=d")
2780 (vec_concat:V2HI
2781 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2782 (parallel [(const_int 0)]))
2783 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2784 (parallel [(const_int 0)])))
2785 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
2786 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
2787 ""
2788 "%0 = %1 -|+ %2 (S)%!"
2789 [(set_attr "type" "dsp32")])
2791 (define_insn "sublohiv2hi3"
2792 [(set (match_operand:HI 0 "register_operand" "=d")
2793 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2794 (parallel [(const_int 1)]))
2795 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2796 (parallel [(const_int 0)]))))]
2797 ""
2798 "%h0 = %d1 - %h2%!"
2799 [(set_attr "type" "dsp32")])
2801 (define_insn "subhilov2hi3"
2802 [(set (match_operand:HI 0 "register_operand" "=d")
2803 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2804 (parallel [(const_int 0)]))
2805 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2806 (parallel [(const_int 1)]))))]
2807 ""
2808 "%h0 = %h1 - %d2%!"
2809 [(set_attr "type" "dsp32")])
2811 (define_insn "sssublohiv2hi3"
2812 [(set (match_operand:HI 0 "register_operand" "=d")
2813 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2814 (parallel [(const_int 1)]))
2815 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2816 (parallel [(const_int 0)]))))]
2817 ""
2818 "%h0 = %d1 - %h2 (S)%!"
2819 [(set_attr "type" "dsp32")])
2821 (define_insn "sssubhilov2hi3"
2822 [(set (match_operand:HI 0 "register_operand" "=d")
2823 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2824 (parallel [(const_int 0)]))
2825 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2826 (parallel [(const_int 1)]))))]
2827 ""
2828 "%h0 = %h1 - %d2 (S)%!"
2829 [(set_attr "type" "dsp32")])
2831 (define_insn "addlohiv2hi3"
2832 [(set (match_operand:HI 0 "register_operand" "=d")
2833 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2834 (parallel [(const_int 1)]))
2835 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2836 (parallel [(const_int 0)]))))]
2837 ""
2838 "%h0 = %d1 + %h2%!"
2839 [(set_attr "type" "dsp32")])
2841 (define_insn "addhilov2hi3"
2842 [(set (match_operand:HI 0 "register_operand" "=d")
2843 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2844 (parallel [(const_int 0)]))
2845 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2846 (parallel [(const_int 1)]))))]
2847 ""
2848 "%h0 = %h1 + %d2%!"
2849 [(set_attr "type" "dsp32")])
2851 (define_insn "ssaddlohiv2hi3"
2852 [(set (match_operand:HI 0 "register_operand" "=d")
2853 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2854 (parallel [(const_int 1)]))
2855 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2856 (parallel [(const_int 0)]))))]
2857 ""
2858 "%h0 = %d1 + %h2 (S)%!"
2859 [(set_attr "type" "dsp32")])
2861 (define_insn "ssaddhilov2hi3"
2862 [(set (match_operand:HI 0 "register_operand" "=d")
2863 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
2864 (parallel [(const_int 0)]))
2865 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
2866 (parallel [(const_int 1)]))))]
2867 ""
2868 "%h0 = %h1 + %d2 (S)%!"
2869 [(set_attr "type" "dsp32")])
2871 (define_insn "sminv2hi3"
2872 [(set (match_operand:V2HI 0 "register_operand" "=d")
2873 (smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
2874 (match_operand:V2HI 2 "register_operand" "d")))]
2875 ""
2876 "%0 = MIN (%1, %2) (V)%!"
2877 [(set_attr "type" "dsp32")])
2879 (define_insn "smaxv2hi3"
2880 [(set (match_operand:V2HI 0 "register_operand" "=d")
2881 (smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
2882 (match_operand:V2HI 2 "register_operand" "d")))]
2883 ""
2884 "%0 = MAX (%1, %2) (V)%!"
2885 [(set_attr "type" "dsp32")])
2887 ;; Multiplications.
2889 ;; The Blackfin allows a lot of different options, and we need many patterns to
2890 ;; cover most of the hardware's abilities.
2891 ;; There are a few simple patterns using MULT rtx codes, but most of them use
2892 ;; an unspec with a const_int operand that determines which flag to use in the
2893 ;; instruction.
2894 ;; There are variants for single and parallel multiplications.
2895 ;; There are variants which just use 16-bit lowparts as inputs, and variants
2896 ;; which allow the user to choose just which halves to use as input values.
2897 ;; There are variants which set D registers, variants which set accumulators,
2898 ;; variants which set both, some of them optionally using the accumulators as
2899 ;; inputs for multiply-accumulate operations.
2901 (define_insn "flag_mulhi"
2902 [(set (match_operand:HI 0 "register_operand" "=d")
2903 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2904 (match_operand:HI 2 "register_operand" "d")
2905 (match_operand 3 "const_int_operand" "n")]
2906 UNSPEC_MUL_WITH_FLAG))]
2907 ""
2908 "%h0 = %h1 * %h2 %M3%!"
2909 [(set_attr "type" "dsp32")])
2911 (define_insn "flag_mulhisi"
2912 [(set (match_operand:SI 0 "register_operand" "=d")
2913 (unspec:SI [(match_operand:HI 1 "register_operand" "d")
2914 (match_operand:HI 2 "register_operand" "d")
2915 (match_operand 3 "const_int_operand" "n")]
2916 UNSPEC_MUL_WITH_FLAG))]
2917 ""
2918 "%0 = %h1 * %h2 %M3%!"
2919 [(set_attr "type" "dsp32")])
2921 (define_insn "flag_mulhisi_parts"
2922 [(set (match_operand:SI 0 "register_operand" "=d")
2923 (unspec:SI [(vec_select:HI
2924 (match_operand:V2HI 1 "register_operand" "d")
2925 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
2926 (vec_select:HI
2927 (match_operand:V2HI 2 "register_operand" "d")
2928 (parallel [(match_operand 4 "const01_operand" "P0P1")]))
2929 (match_operand 5 "const_int_operand" "n")]
2930 UNSPEC_MUL_WITH_FLAG))]
2931 ""
2932 {
2933 const char *templates[] = {
2934 "%0 = %h1 * %h2 %M5%!",
2935 "%0 = %d1 * %h2 %M5%!",
2936 "%0 = %h1 * %d2 %M5%!",
2937 "%0 = %d1 * %d2 %M5%!" };
2938 int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
2939 return templates[alt];
2940 }
2941 [(set_attr "type" "dsp32")])
2943 (define_insn "flag_machi"
2944 [(set (match_operand:HI 0 "register_operand" "=d")
2945 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2946 (match_operand:HI 2 "register_operand" "d")
2947 (match_operand 3 "register_operand" "A")
2948 (match_operand 4 "const01_operand" "P0P1")
2949 (match_operand 5 "const_int_operand" "n")]
2950 UNSPEC_MAC_WITH_FLAG))
2951 (set (match_operand:PDI 6 "register_operand" "=A")
2952 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)
2953 (match_dup 4) (match_dup 5)]
2954 UNSPEC_MAC_WITH_FLAG))]
2955 ""
2956 "%h0 = (A0 %b4 %h1 * %h2) %M6%!"
2957 [(set_attr "type" "dsp32")])
2959 (define_insn "flag_machi_acconly"
2960 [(set (match_operand:PDI 0 "register_operand" "=e")
2961 (unspec:PDI [(match_operand:HI 1 "register_operand" "d")
2962 (match_operand:HI 2 "register_operand" "d")
2963 (match_operand 3 "register_operand" "A")
2964 (match_operand 4 "const01_operand" "P0P1")
2965 (match_operand 5 "const_int_operand" "n")]
2966 UNSPEC_MAC_WITH_FLAG))]
2967 ""
2968 "%0 %b4 %h1 * %h2 %M6%!"
2969 [(set_attr "type" "dsp32")])
2971 (define_insn "flag_macinithi"
2972 [(set (match_operand:HI 0 "register_operand" "=d")
2973 (unspec:HI [(match_operand:HI 1 "register_operand" "d")
2974 (match_operand:HI 2 "register_operand" "d")
2975 (match_operand 3 "const_int_operand" "n")]
2976 UNSPEC_MAC_WITH_FLAG))
2977 (set (match_operand:PDI 4 "register_operand" "=A")
2978 (unspec:PDI [(match_dup 1) (match_dup 2) (match_dup 3)]
2979 UNSPEC_MAC_WITH_FLAG))]
2980 ""
2981 "%h0 = (A0 = %h1 * %h2) %M3%!"
2982 [(set_attr "type" "dsp32")])
2984 (define_insn "flag_macinit1hi"
2985 [(set (match_operand:PDI 0 "register_operand" "=e")
2986 (unspec:PDI [(match_operand:HI 1 "register_operand" "d")
2987 (match_operand:HI 2 "register_operand" "d")
2988 (match_operand 3 "const_int_operand" "n")]
2989 UNSPEC_MAC_WITH_FLAG))]
2990 ""
2991 "%0 = %h1 * %h2 %M3%!"
2992 [(set_attr "type" "dsp32")])
2994 (define_insn "mulv2hi3"
2995 [(set (match_operand:V2HI 0 "register_operand" "=d")
2996 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
2997 (match_operand:V2HI 2 "register_operand" "d")))]
2998 ""
2999 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS)%!"
3000 [(set_attr "type" "dsp32")])
3002 (define_insn "flag_mulv2hi"
3003 [(set (match_operand:V2HI 0 "register_operand" "=d")
3004 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
3005 (match_operand:V2HI 2 "register_operand" "d")
3006 (match_operand 3 "const_int_operand" "n")]
3007 UNSPEC_MUL_WITH_FLAG))]
3008 ""
3009 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M3%!"
3010 [(set_attr "type" "dsp32")])
3012 (define_insn "flag_mulv2hi_parts"
3013 [(set (match_operand:V2HI 0 "register_operand" "=d")
3014 (unspec:V2HI [(vec_concat:V2HI
3015 (vec_select:HI
3016 (match_operand:V2HI 1 "register_operand" "d")
3017 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3018 (vec_select:HI
3019 (match_dup 1)
3020 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3021 (vec_concat:V2HI
3022 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3023 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3024 (vec_select:HI (match_dup 2)
3025 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3026 (match_operand 7 "const_int_operand" "n")]
3027 UNSPEC_MUL_WITH_FLAG))]
3028 ""
3029 {
3030 const char *templates[] = {
3031 "%h0 = %h1 * %h2, %d0 = %h1 * %h2 %M7%!",
3032 "%h0 = %d1 * %h2, %d0 = %h1 * %h2 %M7%!",
3033 "%h0 = %h1 * %h2, %d0 = %d1 * %h2 %M7%!",
3034 "%h0 = %d1 * %h2, %d0 = %d1 * %h2 %M7%!",
3035 "%h0 = %h1 * %d2, %d0 = %h1 * %h2 %M7%!",
3036 "%h0 = %d1 * %d2, %d0 = %h1 * %h2 %M7%!",
3037 "%h0 = %h1 * %d2, %d0 = %d1 * %h2 %M7%!",
3038 "%h0 = %d1 * %d2, %d0 = %d1 * %h2 %M7%!",
3039 "%h0 = %h1 * %h2, %d0 = %h1 * %d2 %M7%!",
3040 "%h0 = %d1 * %h2, %d0 = %h1 * %d2 %M7%!",
3041 "%h0 = %h1 * %h2, %d0 = %d1 * %d2 %M7%!",
3042 "%h0 = %d1 * %h2, %d0 = %d1 * %d2 %M7%!",
3043 "%h0 = %h1 * %d2, %d0 = %h1 * %d2 %M7%!",
3044 "%h0 = %d1 * %d2, %d0 = %h1 * %d2 %M7%!",
3045 "%h0 = %h1 * %d2, %d0 = %d1 * %d2 %M7%!",
3046 "%h0 = %d1 * %d2, %d0 = %d1 * %d2 %M7%!" };
3047 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3048 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3049 return templates[alt];
3050 }
3051 [(set_attr "type" "dsp32")])
3053 ;; A slightly complicated pattern.
3054 ;; Operand 0 is the halfword output; operand 11 is the accumulator output
3055 ;; Halfword inputs are operands 1 and 2; operands 3, 4, 5 and 6 specify which
3056 ;; parts of these 2x16 bit registers to use.
3057 ;; Operand 7 is the accumulator input.
3058 ;; Operands 8/9 specify whether low/high parts are mac (0) or msu (1)
3059 ;; Operand 10 is the macflag to be used.
3060 (define_insn "flag_macv2hi_parts"
3061 [(set (match_operand:V2HI 0 "register_operand" "=d")
3062 (unspec:V2HI [(vec_concat:V2HI
3063 (vec_select:HI
3064 (match_operand:V2HI 1 "register_operand" "d")
3065 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3066 (vec_select:HI
3067 (match_dup 1)
3068 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3069 (vec_concat:V2HI
3070 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3071 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3072 (vec_select:HI (match_dup 2)
3073 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3074 (match_operand:V2PDI 7 "register_operand" "e")
3075 (match_operand 8 "const01_operand" "P0P1")
3076 (match_operand 9 "const01_operand" "P0P1")
3077 (match_operand 10 "const_int_operand" "n")]
3078 UNSPEC_MAC_WITH_FLAG))
3079 (set (match_operand:V2PDI 11 "register_operand" "=e")
3080 (unspec:V2PDI [(vec_concat:V2HI
3081 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3082 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3083 (vec_concat:V2HI
3084 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3085 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3086 (match_dup 7) (match_dup 8) (match_dup 9) (match_dup 10)]
3087 UNSPEC_MAC_WITH_FLAG))]
3088 ""
3089 {
3090 const char *templates[] = {
3091 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3092 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3093 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3094 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3095 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3096 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %h2) %M10%!",
3097 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3098 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %h2) %M10%!",
3099 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3100 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3101 "%h0 = (A0 %b8 %h1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3102 "%h0 = (A0 %b8 %d1 * %h2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3103 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3104 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %h1 * %d2) %M10%!",
3105 "%h0 = (A0 %b8 %h1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!",
3106 "%h0 = (A0 %b8 %d1 * %d2), %d0 = (A1 %b9 %d1 * %d2) %M10%!" };
3107 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3108 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3109 return templates[alt];
3110 }
3111 [(set_attr "type" "dsp32")])
3113 (define_insn "flag_macv2hi_parts_acconly"
3114 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3115 (unspec:V2PDI [(vec_concat:V2HI
3116 (vec_select:HI
3117 (match_operand:V2HI 1 "register_operand" "d")
3118 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3119 (vec_select:HI
3120 (match_dup 1)
3121 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3122 (vec_concat:V2HI
3123 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3124 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3125 (vec_select:HI (match_dup 2)
3126 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3127 (match_operand:V2PDI 7 "register_operand" "e")
3128 (match_operand 8 "const01_operand" "P0P1")
3129 (match_operand 9 "const01_operand" "P0P1")
3130 (match_operand 10 "const_int_operand" "n")]
3131 UNSPEC_MAC_WITH_FLAG))]
3132 ""
3133 {
3134 const char *templates[] = {
3135 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3136 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %h2 %M10%!",
3137 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3138 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %h2 %M10%!",
3139 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3140 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %h2 %M10%!",
3141 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3142 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %h2 %M10%!",
3143 "A0 %b8 %h1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3144 "A0 %b8 %d1 * %h2, A1 %b9 %h1 * %d2 %M10%!",
3145 "A0 %b8 %h1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3146 "A0 %b8 %d1 * %h2, A1 %b9 %d1 * %d2 %M10%!",
3147 "A0 %b8 %h1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3148 "A0 %b8 %d1 * %d2, A1 %b9 %h1 * %d2 %M10%!",
3149 "A0 %b8 %h1 * %d2, A1 %b9 %d1 * %d2 %M10%!",
3150 "A0 %b8 %d1 * %d2, A1 %b9 %d1 * %d2 %M10%!" };
3151 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3152 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3153 return templates[alt];
3154 }
3155 [(set_attr "type" "dsp32")])
3157 ;; Same as above, but initializing the accumulators and therefore a couple fewer
3158 ;; necessary operands.
3159 (define_insn "flag_macinitv2hi_parts"
3160 [(set (match_operand:V2HI 0 "register_operand" "=d")
3161 (unspec:V2HI [(vec_concat:V2HI
3162 (vec_select:HI
3163 (match_operand:V2HI 1 "register_operand" "d")
3164 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3165 (vec_select:HI
3166 (match_dup 1)
3167 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3168 (vec_concat:V2HI
3169 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3170 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3171 (vec_select:HI (match_dup 2)
3172 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3173 (match_operand 7 "const_int_operand" "n")]
3174 UNSPEC_MAC_WITH_FLAG))
3175 (set (match_operand:V2PDI 8 "register_operand" "=e")
3176 (unspec:V2PDI [(vec_concat:V2HI
3177 (vec_select:HI (match_dup 1) (parallel [(match_dup 3)]))
3178 (vec_select:HI (match_dup 1) (parallel [(match_dup 4)])))
3179 (vec_concat:V2HI
3180 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)]))
3181 (vec_select:HI (match_dup 2) (parallel [(match_dup 5)])))
3182 (match_dup 7)]
3183 UNSPEC_MAC_WITH_FLAG))]
3184 ""
3185 {
3186 const char *templates[] = {
3187 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3188 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %h2) %M7%!",
3189 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3190 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %h2) %M7%!",
3191 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3192 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %h2) %M7%!",
3193 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3194 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %h2) %M7%!",
3195 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3196 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %h1 * %d2) %M7%!",
3197 "%h0 = (A0 = %h1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3198 "%h0 = (A0 = %d1 * %h2), %d0 = (A1 = %d1 * %d2) %M7%!",
3199 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3200 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %h1 * %d2) %M7%!",
3201 "%h0 = (A0 = %h1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!",
3202 "%h0 = (A0 = %d1 * %d2), %d0 = (A1 = %d1 * %d2) %M7%!" };
3203 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3204 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3205 return templates[alt];
3206 }
3207 [(set_attr "type" "dsp32")])
3209 (define_insn "flag_macinit1v2hi_parts"
3210 [(set (match_operand:V2PDI 0 "register_operand" "=e")
3211 (unspec:V2PDI [(vec_concat:V2HI
3212 (vec_select:HI
3213 (match_operand:V2HI 1 "register_operand" "d")
3214 (parallel [(match_operand 3 "const01_operand" "P0P1")]))
3215 (vec_select:HI
3216 (match_dup 1)
3217 (parallel [(match_operand 4 "const01_operand" "P0P1")])))
3218 (vec_concat:V2HI
3219 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3220 (parallel [(match_operand 5 "const01_operand" "P0P1")]))
3221 (vec_select:HI (match_dup 2)
3222 (parallel [(match_operand 6 "const01_operand" "P0P1")])))
3223 (match_operand 7 "const_int_operand" "n")]
3224 UNSPEC_MAC_WITH_FLAG))]
3225 ""
3226 {
3227 const char *templates[] = {
3228 "A0 = %h1 * %h2, A1 = %h1 * %h2 %M7%!",
3229 "A0 = %d1 * %h2, A1 = %h1 * %h2 %M7%!",
3230 "A0 = %h1 * %h2, A1 = %d1 * %h2 %M7%!",
3231 "A0 = %d1 * %h2, A1 = %d1 * %h2 %M7%!",
3232 "A0 = %h1 * %d2, A1 = %h1 * %h2 %M7%!",
3233 "A0 = %d1 * %d2, A1 = %h1 * %h2 %M7%!",
3234 "A0 = %h1 * %d2, A1 = %d1 * %h2 %M7%!",
3235 "A0 = %d1 * %d2, A1 = %d1 * %h2 %M7%!",
3236 "A0 = %h1 * %h2, A1 = %h1 * %d2 %M7%!",
3237 "A0 = %d1 * %h2, A1 = %h1 * %d2 %M7%!",
3238 "A0 = %h1 * %h2, A1 = %d1 * %d2 %M7%!",
3239 "A0 = %d1 * %h2, A1 = %d1 * %d2 %M7%!",
3240 "A0 = %h1 * %d2, A1 = %h1 * %d2 %M7%!",
3241 "A0 = %d1 * %d2, A1 = %h1 * %d2 %M7%!",
3242 "A0 = %h1 * %d2, A1 = %d1 * %d2 %M7%!",
3243 "A0 = %d1 * %d2, A1 = %d1 * %d2 %M7%!" };
3244 int alt = (INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
3245 + (INTVAL (operands[5]) << 2) + (INTVAL (operands[6]) << 3));
3246 return templates[alt];
3247 }
3248 [(set_attr "type" "dsp32")])
3250 (define_insn "mulhisi_ll"
3251 [(set (match_operand:SI 0 "register_operand" "=d")
3252 (mult:SI (sign_extend:SI
3253 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3254 (parallel [(const_int 0)])))
3255 (sign_extend:SI
3256 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3257 (parallel [(const_int 0)])))))]
3258 ""
3259 "%0 = %h1 * %h2 (IS)%!"
3260 [(set_attr "type" "dsp32")])
3262 (define_insn "mulhisi_lh"
3263 [(set (match_operand:SI 0 "register_operand" "=d")
3264 (mult:SI (sign_extend:SI
3265 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3266 (parallel [(const_int 0)])))
3267 (sign_extend:SI
3268 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3269 (parallel [(const_int 1)])))))]
3270 ""
3271 "%0 = %h1 * %d2 (IS)%!"
3272 [(set_attr "type" "dsp32")])
3274 (define_insn "mulhisi_hl"
3275 [(set (match_operand:SI 0 "register_operand" "=d")
3276 (mult:SI (sign_extend:SI
3277 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3278 (parallel [(const_int 1)])))
3279 (sign_extend:SI
3280 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3281 (parallel [(const_int 0)])))))]
3282 ""
3283 "%0 = %d1 * %h2 (IS)%!"
3284 [(set_attr "type" "dsp32")])
3286 (define_insn "mulhisi_hh"
3287 [(set (match_operand:SI 0 "register_operand" "=d")
3288 (mult:SI (sign_extend:SI
3289 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
3290 (parallel [(const_int 1)])))
3291 (sign_extend:SI
3292 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
3293 (parallel [(const_int 1)])))))]
3294 ""
3295 "%0 = %d1 * %d2 (IS)%!"
3296 [(set_attr "type" "dsp32")])
3298 (define_insn "ssnegv2hi2"
3299 [(set (match_operand:V2HI 0 "register_operand" "=d")
3300 (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3301 ""
3302 "%0 = - %1 (V)%!"
3303 [(set_attr "type" "dsp32")])
3305 (define_insn "absv2hi2"
3306 [(set (match_operand:V2HI 0 "register_operand" "=d")
3307 (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
3308 ""
3309 "%0 = ABS %1 (V)%!"
3310 [(set_attr "type" "dsp32")])
3312 ;; Shifts.
3314 (define_insn "ssashiftv2hi3"
3315 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3316 (if_then_else:V2HI
3317 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3318 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3319 (match_dup 2))
3320 (ss_ashift:V2HI (match_dup 1) (match_dup 2))))]
3321 ""
3322 "@
3323 %0 = ASHIFT %1 BY %2 (V, S)%!
3324 %0 = %1 << %2 (V,S)%!
3325 %0 = %1 >>> %N2 (V,S)%!"
3326 [(set_attr "type" "dsp32")])
3328 (define_insn "ssashifthi3"
3329 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3330 (if_then_else:HI
3331 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3332 (ashiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3333 (match_dup 2))
3334 (ss_ashift:HI (match_dup 1) (match_dup 2))))]
3335 ""
3336 "@
3337 %0 = ASHIFT %1 BY %2 (V, S)%!
3338 %0 = %1 << %2 (V,S)%!
3339 %0 = %1 >>> %N2 (V,S)%!"
3340 [(set_attr "type" "dsp32")])
3342 (define_insn "lshiftv2hi3"
3343 [(set (match_operand:V2HI 0 "register_operand" "=d,d,d")
3344 (if_then_else:V2HI
3345 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3346 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" "d,d,d")
3347 (match_dup 2))
3348 (ashift:V2HI (match_dup 1) (match_dup 2))))]
3349 ""
3350 "@
3351 %0 = LSHIFT %1 BY %2 (V)%!
3352 %0 = %1 << %2 (V)%!
3353 %0 = %1 >> %N2 (V)%!"
3354 [(set_attr "type" "dsp32")])
3356 (define_insn "lshifthi3"
3357 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3358 (if_then_else:HI
3359 (lt (match_operand:SI 2 "vec_shift_operand" "d,Ku4,Ks4") (const_int 0))
3360 (lshiftrt:HI (match_operand:HI 1 "register_operand" "d,d,d")
3361 (match_dup 2))
3362 (ashift:HI (match_dup 1) (match_dup 2))))]
3363 ""
3364 "@
3365 %0 = LSHIFT %1 BY %2 (V)%!
3366 %0 = %1 << %2 (V)%!
3367 %0 = %1 >> %N2 (V)%!"
3368 [(set_attr "type" "dsp32")])