1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
32 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1
PARAMS ((void));
50 static void init_reg_modes
PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set
;
75 /* Data for initializing the above. */
77 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set
;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set
;
94 /* Data for initializing the above. */
96 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
98 /* Indexed by hard register number, contains 1 for registers that are
99 fixed use or call used registers that cannot hold quantities across
100 calls even if we are willing to save and restore them. call fixed
101 registers are a subset of call used registers. */
103 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
105 /* The same info as a HARD_REG_SET. */
107 HARD_REG_SET call_fixed_reg_set
;
109 /* Number of non-fixed registers. */
111 int n_non_fixed_regs
;
113 /* Indexed by hard register number, contains 1 for registers
114 that are being used for global register decls.
115 These must be exempt from ordinary flow analysis
116 and are also considered fixed. */
118 char global_regs
[FIRST_PSEUDO_REGISTER
];
120 /* Table of register numbers in the order in which to try to use them. */
121 #ifdef REG_ALLOC_ORDER
122 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
124 /* The inverse of reg_alloc_order. */
125 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
128 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
130 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
132 /* The same information, but as an array of unsigned ints. We copy from
133 these unsigned ints to the table above. We do this so the tm.h files
134 do not have to be aware of the wordsize for machines with <= 64 regs. */
137 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
139 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
140 = REG_CLASS_CONTENTS
;
142 /* For each reg class, number of regs it contains. */
144 unsigned int reg_class_size
[N_REG_CLASSES
];
146 /* For each reg class, table listing all the containing classes. */
148 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
150 /* For each reg class, table listing all the classes contained in it. */
152 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
154 /* For each pair of reg classes,
155 a largest reg class contained in their union. */
157 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
159 /* For each pair of reg classes,
160 the smallest reg class containing their union. */
162 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
164 /* Array containing all of the register names. Unless
165 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
167 #ifdef DEBUG_REGISTER_NAMES
168 const char * reg_names
[] = REGISTER_NAMES
;
171 /* For each hard register, the widest mode object that it can contain.
172 This will be a MODE_INT mode if the register can hold integers. Otherwise
173 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
176 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
178 /* 1 if class does contain register of given mode. */
180 static char contains_reg_of_mode
[N_REG_CLASSES
] [MAX_MACHINE_MODE
];
182 /* Maximum cost of moving from a register in one class to a register in
183 another class. Based on REGISTER_MOVE_COST. */
185 static int move_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
187 /* Similar, but here we don't have to move if the first index is a subset
188 of the second so in that case the cost is zero. */
190 static int may_move_in_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
192 /* Similar, but here we don't have to move if the first index is a superset
193 of the second so in that case the cost is zero. */
195 static int may_move_out_cost
[MAX_MACHINE_MODE
][N_REG_CLASSES
][N_REG_CLASSES
];
197 #ifdef FORBIDDEN_INC_DEC_CLASSES
199 /* These are the classes that regs which are auto-incremented or decremented
202 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
204 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
207 static char *in_inc_dec
;
209 #endif /* FORBIDDEN_INC_DEC_CLASSES */
211 #ifdef CLASS_CANNOT_CHANGE_MODE
213 /* These are the classes containing only registers that can be used in
214 a SUBREG expression that changes the mode of the register in some
215 way that is illegal. */
217 static int class_can_change_mode
[N_REG_CLASSES
];
219 /* Registers, including pseudos, which change modes in some way that
222 static regset reg_changes_mode
;
224 #endif /* CLASS_CANNOT_CHANGE_MODE */
226 #ifdef HAVE_SECONDARY_RELOADS
228 /* Sample MEM values for use by memory_move_secondary_cost. */
230 static rtx top_of_stack
[MAX_MACHINE_MODE
];
232 #endif /* HAVE_SECONDARY_RELOADS */
234 /* Linked list of reg_info structures allocated for reg_n_info array.
235 Grouping all of the allocated structures together in one lump
236 means only one call to bzero to clear them, rather than n smaller
238 struct reg_info_data
{
239 struct reg_info_data
*next
; /* next set of reg_info structures */
240 size_t min_index
; /* minimum index # */
241 size_t max_index
; /* maximum index # */
242 char used_p
; /* non-zero if this has been used previously */
243 reg_info data
[1]; /* beginning of the reg_info data */
246 static struct reg_info_data
*reg_info_head
;
248 /* No more global register variables may be declared; true once
249 regclass has been initialized. */
251 static int no_global_reg_vars
= 0;
254 /* Function called only once to initialize the above data on reg usage.
255 Once this is done, various switches may override. */
262 /* First copy the register information from the initial int form into
265 for (i
= 0; i
< N_REG_CLASSES
; i
++)
267 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
269 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
270 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
271 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
272 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
275 memcpy (fixed_regs
, initial_fixed_regs
, sizeof fixed_regs
);
276 memcpy (call_used_regs
, initial_call_used_regs
, sizeof call_used_regs
);
277 memset (global_regs
, 0, sizeof global_regs
);
279 /* Do any additional initialization regsets may need */
280 INIT_ONCE_REG_SET ();
282 #ifdef REG_ALLOC_ORDER
283 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
284 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
288 /* After switches have been processed, which perhaps alter
289 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
294 register unsigned int i
, j
;
295 register unsigned int /* enum machine_mode */ m
;
296 char allocatable_regs_of_mode
[MAX_MACHINE_MODE
];
298 /* This macro allows the fixed or call-used registers
299 and the register classes to depend on target flags. */
301 #ifdef CONDITIONAL_REGISTER_USAGE
302 CONDITIONAL_REGISTER_USAGE
;
305 /* Compute number of hard regs in each class. */
307 memset ((char *) reg_class_size
, 0, sizeof reg_class_size
);
308 for (i
= 0; i
< N_REG_CLASSES
; i
++)
309 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
310 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
313 /* Initialize the table of subunions.
314 reg_class_subunion[I][J] gets the largest-numbered reg-class
315 that is contained in the union of classes I and J. */
317 for (i
= 0; i
< N_REG_CLASSES
; i
++)
319 for (j
= 0; j
< N_REG_CLASSES
; j
++)
322 register /* Declare it register if it's a scalar. */
327 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
328 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
329 for (k
= 0; k
< N_REG_CLASSES
; k
++)
331 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
336 /* keep the largest subclass */ /* SPEE 900308 */
337 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
338 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
340 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
347 /* Initialize the table of superunions.
348 reg_class_superunion[I][J] gets the smallest-numbered reg-class
349 containing the union of classes I and J. */
351 for (i
= 0; i
< N_REG_CLASSES
; i
++)
353 for (j
= 0; j
< N_REG_CLASSES
; j
++)
356 register /* Declare it register if it's a scalar. */
361 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
362 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
363 for (k
= 0; k
< N_REG_CLASSES
; k
++)
364 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
367 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
371 /* Initialize the tables of subclasses and superclasses of each reg class.
372 First clear the whole table, then add the elements as they are found. */
374 for (i
= 0; i
< N_REG_CLASSES
; i
++)
376 for (j
= 0; j
< N_REG_CLASSES
; j
++)
378 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
379 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
383 for (i
= 0; i
< N_REG_CLASSES
; i
++)
385 if (i
== (int) NO_REGS
)
388 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
392 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
396 /* Reg class I is a subclass of J.
397 Add J to the table of superclasses of I. */
398 p
= ®_class_superclasses
[i
][0];
399 while (*p
!= LIM_REG_CLASSES
) p
++;
400 *p
= (enum reg_class
) j
;
401 /* Add I to the table of superclasses of J. */
402 p
= ®_class_subclasses
[j
][0];
403 while (*p
!= LIM_REG_CLASSES
) p
++;
404 *p
= (enum reg_class
) i
;
408 /* Initialize "constant" tables. */
410 CLEAR_HARD_REG_SET (fixed_reg_set
);
411 CLEAR_HARD_REG_SET (call_used_reg_set
);
412 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
414 memcpy (call_fixed_regs
, fixed_regs
, sizeof call_fixed_regs
);
416 n_non_fixed_regs
= 0;
418 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
421 SET_HARD_REG_BIT (fixed_reg_set
, i
);
425 if (call_used_regs
[i
])
426 SET_HARD_REG_BIT (call_used_reg_set
, i
);
427 if (call_fixed_regs
[i
])
428 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
429 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
430 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
432 memset (contains_reg_of_mode
, 0, sizeof (contains_reg_of_mode
));
433 memset (allocatable_regs_of_mode
, 0, sizeof (allocatable_regs_of_mode
));
434 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
435 for (i
= 0; i
< N_REG_CLASSES
; i
++)
436 if (CLASS_MAX_NREGS (i
, m
) <= reg_class_size
[i
])
437 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
438 if (!fixed_regs
[j
] && TEST_HARD_REG_BIT (reg_class_contents
[i
], j
)
439 && HARD_REGNO_MODE_OK (j
, m
))
441 contains_reg_of_mode
[i
][m
] = 1;
442 allocatable_regs_of_mode
[m
] = 1;
446 /* Initialize the move cost table. Find every subset of each class
447 and take the maximum cost of moving any subset to any other. */
449 for (m
= 0; m
< (unsigned int) MAX_MACHINE_MODE
; m
++)
450 if (allocatable_regs_of_mode
[m
])
452 for (i
= 0; i
< N_REG_CLASSES
; i
++)
453 if (contains_reg_of_mode
[i
][m
])
454 for (j
= 0; j
< N_REG_CLASSES
; j
++)
457 enum reg_class
*p1
, *p2
;
459 if (!contains_reg_of_mode
[j
][m
])
461 move_cost
[m
][i
][j
] = 65536;
462 may_move_in_cost
[m
][i
][j
] = 65536;
463 may_move_out_cost
[m
][i
][j
] = 65536;
467 cost
= i
== j
? 2 : REGISTER_MOVE_COST (m
, i
, j
);
469 for (p2
= ®_class_subclasses
[j
][0];
470 *p2
!= LIM_REG_CLASSES
;
472 if (*p2
!= i
&& contains_reg_of_mode
[*p2
][m
])
473 cost
= MAX (cost
, move_cost
[m
][i
][*p2
]);
475 for (p1
= ®_class_subclasses
[i
][0];
476 *p1
!= LIM_REG_CLASSES
;
478 if (*p1
!= j
&& contains_reg_of_mode
[*p1
][m
])
479 cost
= MAX (cost
, move_cost
[m
][*p1
][j
]);
481 move_cost
[m
][i
][j
] = cost
;
483 if (reg_class_subset_p (i
, j
))
484 may_move_in_cost
[m
][i
][j
] = 0;
486 may_move_in_cost
[m
][i
][j
] = cost
;
488 if (reg_class_subset_p (j
, i
))
489 may_move_out_cost
[m
][i
][j
] = 0;
491 may_move_out_cost
[m
][i
][j
] = cost
;
495 for (j
= 0; j
< N_REG_CLASSES
; j
++)
497 move_cost
[m
][i
][j
] = 65536;
498 may_move_in_cost
[m
][i
][j
] = 65536;
499 may_move_out_cost
[m
][i
][j
] = 65536;
503 #ifdef CLASS_CANNOT_CHANGE_MODE
506 COMPL_HARD_REG_SET (c
, reg_class_contents
[CLASS_CANNOT_CHANGE_MODE
]);
508 for (i
= 0; i
< N_REG_CLASSES
; i
++)
510 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], c
, ok_class
);
511 class_can_change_mode
[i
] = 0;
514 class_can_change_mode
[i
] = 1;
517 #endif /* CLASS_CANNOT_CHANGE_MODE */
520 /* Compute the table of register modes.
521 These values are used to record death information for individual registers
522 (as opposed to a multi-register mode). */
529 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
531 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
533 /* If we couldn't find a valid mode, just use the previous mode.
534 ??? One situation in which we need to do this is on the mips where
535 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
536 to use DF mode for the even registers and VOIDmode for the odd
537 (for the cpu models where the odd ones are inaccessible). */
538 if (reg_raw_mode
[i
] == VOIDmode
)
539 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
543 /* Finish initializing the register sets and
544 initialize the register modes. */
549 /* This finishes what was started by init_reg_sets, but couldn't be done
550 until after register usage was specified. */
555 #ifdef HAVE_SECONDARY_RELOADS
557 /* Make some fake stack-frame MEM references for use in
558 memory_move_secondary_cost. */
561 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
562 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
563 ggc_add_rtx_root (top_of_stack
, MAX_MACHINE_MODE
);
568 #ifdef HAVE_SECONDARY_RELOADS
570 /* Compute extra cost of moving registers to/from memory due to reloads.
571 Only needed if secondary reloads are required for memory moves. */
574 memory_move_secondary_cost (mode
, class, in
)
575 enum machine_mode mode
;
576 enum reg_class
class;
579 enum reg_class altclass
;
580 int partial_cost
= 0;
581 /* We need a memory reference to feed to SECONDARY... macros. */
582 /* mem may be unused even if the SECONDARY_ macros are defined. */
583 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
588 #ifdef SECONDARY_INPUT_RELOAD_CLASS
589 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
596 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
597 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
603 if (altclass
== NO_REGS
)
607 partial_cost
= REGISTER_MOVE_COST (mode
, altclass
, class);
609 partial_cost
= REGISTER_MOVE_COST (mode
, class, altclass
);
611 if (class == altclass
)
612 /* This isn't simply a copy-to-temporary situation. Can't guess
613 what it is, so MEMORY_MOVE_COST really ought not to be calling
616 I'm tempted to put in an abort here, but returning this will
617 probably only give poor estimates, which is what we would've
618 had before this code anyways. */
621 /* Check if the secondary reload register will also need a
623 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
627 /* Return a machine mode that is legitimate for hard reg REGNO and large
628 enough to save nregs. If we can't find one, return VOIDmode. */
631 choose_hard_reg_mode (regno
, nregs
)
632 unsigned int regno ATTRIBUTE_UNUSED
;
635 unsigned int /* enum machine_mode */ m
;
636 enum machine_mode found_mode
= VOIDmode
, mode
;
638 /* We first look for the largest integer mode that can be validly
639 held in REGNO. If none, we look for the largest floating-point mode.
640 If we still didn't find a valid mode, try CCmode. */
642 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
644 mode
= GET_MODE_WIDER_MODE (mode
))
645 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
646 && HARD_REGNO_MODE_OK (regno
, mode
))
649 if (found_mode
!= VOIDmode
)
652 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
654 mode
= GET_MODE_WIDER_MODE (mode
))
655 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
656 && HARD_REGNO_MODE_OK (regno
, mode
))
659 if (found_mode
!= VOIDmode
)
662 /* Iterate over all of the CCmodes. */
663 for (m
= (unsigned int) CCmode
; m
< (unsigned int) NUM_MACHINE_MODES
; ++m
)
665 mode
= (enum machine_mode
) m
;
666 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
667 && HARD_REGNO_MODE_OK (regno
, mode
))
671 /* We can't find a mode valid for this register. */
675 /* Specify the usage characteristics of the register named NAME.
676 It should be a fixed register if FIXED and a
677 call-used register if CALL_USED. */
680 fix_register (name
, fixed
, call_used
)
682 int fixed
, call_used
;
686 /* Decode the name and update the primary form of
687 the register info. */
689 if ((i
= decode_reg_name (name
)) >= 0)
691 if ((i
== STACK_POINTER_REGNUM
692 #ifdef HARD_FRAME_POINTER_REGNUM
693 || i
== HARD_FRAME_POINTER_REGNUM
695 || i
== FRAME_POINTER_REGNUM
698 && (fixed
== 0 || call_used
== 0))
700 static const char * const what_option
[2][2] = {
701 { "call-saved", "call-used" },
702 { "no-such-option", "fixed" }};
704 error ("can't use '%s' as a %s register", name
,
705 what_option
[fixed
][call_used
]);
709 fixed_regs
[i
] = fixed
;
710 call_used_regs
[i
] = call_used
;
715 warning ("unknown register name: %s", name
);
719 /* Mark register number I as global. */
725 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
726 error ("global register variable follows a function definition");
730 warning ("register used for two global register variables");
734 if (call_used_regs
[i
] && ! fixed_regs
[i
])
735 warning ("call-clobbered register used for global register variable");
739 /* If already fixed, nothing else to do. */
743 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
746 SET_HARD_REG_BIT (fixed_reg_set
, i
);
747 SET_HARD_REG_BIT (call_used_reg_set
, i
);
748 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
751 /* Now the data and code for the `regclass' pass, which happens
752 just before local-alloc. */
754 /* The `costs' struct records the cost of using a hard register of each class
755 and of using memory for each pseudo. We use this data to set up
756 register class preferences. */
760 int cost
[N_REG_CLASSES
];
764 /* Structure used to record preferrences of given pseudo. */
767 /* (enum reg_class) prefclass is the preferred class. */
770 /* altclass is a register class that we should use for allocating
771 pseudo if no register in the preferred class is available.
772 If no register in this class is available, memory is preferred.
774 It might appear to be more general to have a bitmask of classes here,
775 but since it is recommended that there be a class corresponding to the
776 union of most major pair of classes, that generality is not required. */
780 /* Record the cost of each class for each pseudo. */
782 static struct costs
*costs
;
784 /* Initialized once, and used to initialize cost values for each insn. */
786 static struct costs init_cost
;
788 /* Record preferrences of each pseudo.
789 This is available after `regclass' is run. */
791 static struct reg_pref
*reg_pref
;
793 /* Allocated buffers for reg_pref. */
795 static struct reg_pref
*reg_pref_buffer
;
797 /* Account for the fact that insns within a loop are executed very commonly,
798 but don't keep doing this as loops go too deep. */
800 static int loop_cost
;
802 static rtx scan_one_insn
PARAMS ((rtx
, int));
803 static void record_operand_costs
PARAMS ((rtx
, struct costs
*, struct reg_pref
*));
804 static void dump_regclass
PARAMS ((FILE *));
805 static void record_reg_classes
PARAMS ((int, int, rtx
*, enum machine_mode
*,
807 struct costs
*, struct reg_pref
*));
808 static int copy_cost
PARAMS ((rtx
, enum machine_mode
,
809 enum reg_class
, int));
810 static void record_address_regs
PARAMS ((rtx
, enum reg_class
, int));
811 #ifdef FORBIDDEN_INC_DEC_CLASSES
812 static int auto_inc_dec_reg_p
PARAMS ((rtx
, enum machine_mode
));
814 static void reg_scan_mark_refs
PARAMS ((rtx
, rtx
, int, unsigned int));
816 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
817 This function is sometimes called before the info has been computed.
818 When that happens, just return GENERAL_REGS, which is innocuous. */
821 reg_preferred_class (regno
)
826 return (enum reg_class
) reg_pref
[regno
].prefclass
;
830 reg_alternate_class (regno
)
836 return (enum reg_class
) reg_pref
[regno
].altclass
;
839 /* Initialize some global data for this pass. */
846 init_cost
.mem_cost
= 10000;
847 for (i
= 0; i
< N_REG_CLASSES
; i
++)
848 init_cost
.cost
[i
] = 10000;
850 /* This prevents dump_flow_info from losing if called
851 before regclass is run. */
854 /* No more global register variables may be declared. */
855 no_global_reg_vars
= 1;
858 /* Dump register costs. */
863 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
865 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
867 int /* enum reg_class */ class;
870 fprintf (dump
, " Register %i costs:", i
);
871 for (class = 0; class < (int) N_REG_CLASSES
; class++)
872 if (contains_reg_of_mode
[(enum reg_class
) class][PSEUDO_REGNO_MODE (i
)]
873 #ifdef FORBIDDEN_INC_DEC_CLASSES
875 || !forbidden_inc_dec_class
[(enum reg_class
) class])
877 #ifdef CLASS_CANNOT_CHANGE_MODE
878 && (!REGNO_REG_SET_P (reg_changes_mode
, i
)
879 || class_can_change_mode
[(enum reg_class
) class])
882 fprintf (dump
, " %s:%i", reg_class_names
[class],
883 costs
[i
].cost
[(enum reg_class
) class]);
884 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
890 /* Calculate the costs of insn operands. */
893 record_operand_costs (insn
, op_costs
, reg_pref
)
895 struct costs
*op_costs
;
896 struct reg_pref
*reg_pref
;
898 const char *constraints
[MAX_RECOG_OPERANDS
];
899 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
902 for (i
= 0; i
< recog_data
.n_operands
; i
++)
904 constraints
[i
] = recog_data
.constraints
[i
];
905 modes
[i
] = recog_data
.operand_mode
[i
];
908 /* If we get here, we are set up to record the costs of all the
909 operands for this insn. Start by initializing the costs.
910 Then handle any address registers. Finally record the desired
911 classes for any pseudos, doing it twice if some pair of
912 operands are commutative. */
914 for (i
= 0; i
< recog_data
.n_operands
; i
++)
916 op_costs
[i
] = init_cost
;
918 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
920 rtx inner
= SUBREG_REG (recog_data
.operand
[i
]);
921 #ifdef CLASS_CANNOT_CHANGE_MODE
922 if (GET_CODE (inner
) == REG
923 && CLASS_CANNOT_CHANGE_MODE_P (modes
[i
], GET_MODE (inner
)))
924 SET_REGNO_REG_SET (reg_changes_mode
, REGNO (inner
));
926 recog_data
.operand
[i
] = inner
;
929 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
930 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
931 BASE_REG_CLASS
, loop_cost
* 2);
932 else if (constraints
[i
][0] == 'p')
933 record_address_regs (recog_data
.operand
[i
],
934 BASE_REG_CLASS
, loop_cost
* 2);
937 /* Check for commutative in a separate loop so everything will
938 have been initialized. We must do this even if one operand
939 is a constant--see addsi3 in m68k.md. */
941 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
942 if (constraints
[i
][0] == '%')
944 const char *xconstraints
[MAX_RECOG_OPERANDS
];
947 /* Handle commutative operands by swapping the constraints.
948 We assume the modes are the same. */
950 for (j
= 0; j
< recog_data
.n_operands
; j
++)
951 xconstraints
[j
] = constraints
[j
];
953 xconstraints
[i
] = constraints
[i
+1];
954 xconstraints
[i
+1] = constraints
[i
];
955 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
956 recog_data
.operand
, modes
,
957 xconstraints
, insn
, op_costs
, reg_pref
);
960 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
961 recog_data
.operand
, modes
,
962 constraints
, insn
, op_costs
, reg_pref
);
965 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
966 time it would save code to put a certain register in a certain class.
967 PASS, when nonzero, inhibits some optimizations which need only be done
969 Return the last insn processed, so that the scan can be continued from
973 scan_one_insn (insn
, pass
)
977 enum rtx_code code
= GET_CODE (insn
);
978 enum rtx_code pat_code
;
981 struct costs op_costs
[MAX_RECOG_OPERANDS
];
983 if (GET_RTX_CLASS (code
) != 'i')
986 pat_code
= GET_CODE (PATTERN (insn
));
988 || pat_code
== CLOBBER
989 || pat_code
== ASM_INPUT
990 || pat_code
== ADDR_VEC
991 || pat_code
== ADDR_DIFF_VEC
)
994 set
= single_set (insn
);
997 /* If this insn loads a parameter from its stack slot, then
998 it represents a savings, rather than a cost, if the
999 parameter is stored in memory. Record this fact. */
1001 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
1002 && GET_CODE (SET_SRC (set
)) == MEM
1003 && (note
= find_reg_note (insn
, REG_EQUIV
,
1005 && GET_CODE (XEXP (note
, 0)) == MEM
)
1007 costs
[REGNO (SET_DEST (set
))].mem_cost
1008 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
1011 record_address_regs (XEXP (SET_SRC (set
), 0),
1012 BASE_REG_CLASS
, loop_cost
* 2);
1016 /* Improve handling of two-address insns such as
1017 (set X (ashift CONST Y)) where CONST must be made to
1018 match X. Change it into two insns: (set X CONST)
1019 (set X (ashift X Y)). If we left this for reloading, it
1020 would probably get three insns because X and Y might go
1021 in the same place. This prevents X and Y from receiving
1024 We can only do this if the modes of operands 0 and 1
1025 (which might not be the same) are tieable and we only need
1026 do this during our first pass. */
1028 if (pass
== 0 && optimize
1029 && recog_data
.n_operands
>= 3
1030 && recog_data
.constraints
[1][0] == '0'
1031 && recog_data
.constraints
[1][1] == 0
1032 && CONSTANT_P (recog_data
.operand
[1])
1033 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
1034 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
1035 && GET_CODE (recog_data
.operand
[0]) == REG
1036 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
1037 recog_data
.operand_mode
[1]))
1039 rtx previnsn
= prev_real_insn (insn
);
1041 = gen_lowpart (recog_data
.operand_mode
[1],
1042 recog_data
.operand
[0]);
1044 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
1046 /* If this insn was the start of a basic block,
1047 include the new insn in that block.
1048 We need not check for code_label here;
1049 while a basic block can start with a code_label,
1050 INSN could not be at the beginning of that block. */
1051 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
1054 for (b
= 0; b
< n_basic_blocks
; b
++)
1055 if (insn
== BLOCK_HEAD (b
))
1056 BLOCK_HEAD (b
) = newinsn
;
1059 /* This makes one more setting of new insns's dest. */
1060 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
1062 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
1063 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
1064 if (recog_data
.dup_num
[i
] == 1)
1065 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
1067 return PREV_INSN (newinsn
);
1070 record_operand_costs (insn
, op_costs
, reg_pref
);
1072 /* Now add the cost for each operand to the total costs for
1075 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1076 if (GET_CODE (recog_data
.operand
[i
]) == REG
1077 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1079 int regno
= REGNO (recog_data
.operand
[i
]);
1080 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
1082 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
1083 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1084 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
1090 /* This is a pass of the compiler that scans all instructions
1091 and calculates the preferred class for each pseudo-register.
1092 This information can be accessed later by calling `reg_preferred_class'.
1093 This pass comes just before local register allocation. */
1096 regclass (f
, nregs
, dump
)
1107 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
1109 #ifdef CLASS_CANNOT_CHANGE_MODE
1110 reg_changes_mode
= BITMAP_XMALLOC();
1113 #ifdef FORBIDDEN_INC_DEC_CLASSES
1115 in_inc_dec
= (char *) xmalloc (nregs
);
1117 /* Initialize information about which register classes can be used for
1118 pseudos that are auto-incremented or auto-decremented. It would
1119 seem better to put this in init_reg_sets, but we need to be able
1120 to allocate rtx, which we can't do that early. */
1122 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1124 rtx r
= gen_rtx_REG (VOIDmode
, 0);
1125 enum machine_mode m
;
1128 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1129 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1133 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1134 m
= (enum machine_mode
) ((int) m
+ 1))
1135 if (HARD_REGNO_MODE_OK (j
, m
))
1139 /* If a register is not directly suitable for an
1140 auto-increment or decrement addressing mode and
1141 requires secondary reloads, disallow its class from
1142 being used in such addresses. */
1145 #ifdef SECONDARY_RELOAD_CLASS
1146 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1149 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1150 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1153 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1154 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1159 && ! auto_inc_dec_reg_p (r
, m
))
1160 forbidden_inc_dec_class
[i
] = 1;
1164 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1166 /* Normally we scan the insns once and determine the best class to use for
1167 each register. However, if -fexpensive_optimizations are on, we do so
1168 twice, the second time using the tentative best classes to guide the
1171 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1176 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1177 /* Zero out our accumulation of the cost of each class for each reg. */
1179 memset ((char *) costs
, 0, nregs
* sizeof (struct costs
));
1181 #ifdef FORBIDDEN_INC_DEC_CLASSES
1182 memset (in_inc_dec
, 0, nregs
);
1185 /* Scan the instructions and record each time it would
1186 save code to put a certain register in a certain class. */
1191 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1192 insn
= scan_one_insn (insn
, pass
);
1195 for (index
= 0; index
< n_basic_blocks
; index
++)
1197 basic_block bb
= BASIC_BLOCK (index
);
1199 /* Show that an insn inside a loop is likely to be executed three
1200 times more than insns outside a loop. This is much more
1201 aggressive than the assumptions made elsewhere and is being
1202 tried as an experiment. */
1206 loop_cost
= 1 << (2 * MIN (bb
->loop_depth
, 5));
1207 for (insn
= bb
->head
; ; insn
= NEXT_INSN (insn
))
1209 insn
= scan_one_insn (insn
, pass
);
1210 if (insn
== bb
->end
)
1215 /* Now for each register look at how desirable each class is
1216 and find which class is preferred. Store that in
1217 `prefclass'. Record in `altclass' the largest register
1218 class any of whose registers is better than memory. */
1221 reg_pref
= reg_pref_buffer
;
1225 dump_regclass (dump
);
1226 fprintf (dump
,"\n");
1228 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1230 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1231 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1232 /* This is an enum reg_class, but we call it an int
1233 to save lots of casts. */
1235 register struct costs
*p
= &costs
[i
];
1237 /* In non-optimizing compilation REG_N_REFS is not initialized
1239 if (optimize
&& !REG_N_REFS (i
))
1242 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1244 /* Ignore classes that are too small for this operand or
1245 invalid for a operand that was auto-incremented. */
1246 if (!contains_reg_of_mode
[class][PSEUDO_REGNO_MODE (i
)]
1247 #ifdef FORBIDDEN_INC_DEC_CLASSES
1248 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1250 #ifdef CLASS_CANNOT_CHANGE_MODE
1251 || (REGNO_REG_SET_P (reg_changes_mode
, i
)
1252 && ! class_can_change_mode
[class])
1256 else if (p
->cost
[class] < best_cost
)
1258 best_cost
= p
->cost
[class];
1259 best
= (enum reg_class
) class;
1261 else if (p
->cost
[class] == best_cost
)
1262 best
= reg_class_subunion
[(int)best
][class];
1265 /* Record the alternate register class; i.e., a class for which
1266 every register in it is better than using memory. If adding a
1267 class would make a smaller class (i.e., no union of just those
1268 classes exists), skip that class. The major unions of classes
1269 should be provided as a register class. Don't do this if we
1270 will be doing it again later. */
1272 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1273 for (class = 0; class < N_REG_CLASSES
; class++)
1274 if (p
->cost
[class] < p
->mem_cost
1275 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1276 > reg_class_size
[(int) alt
])
1277 #ifdef FORBIDDEN_INC_DEC_CLASSES
1278 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1280 #ifdef CLASS_CANNOT_CHANGE_MODE
1281 && ! (REGNO_REG_SET_P (reg_changes_mode
, i
)
1282 && ! class_can_change_mode
[class])
1285 alt
= reg_class_subunion
[(int) alt
][class];
1287 /* If we don't add any classes, nothing to try. */
1292 && (reg_pref
[i
].prefclass
!= (int) best
1293 || reg_pref
[i
].altclass
!= (int) alt
))
1295 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1296 fprintf (dump
, " Register %i", i
);
1297 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1298 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1299 else if (alt
== NO_REGS
)
1300 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1302 fprintf (dump
, " pref %s, else %s\n",
1303 reg_class_names
[(int) best
],
1304 reg_class_names
[(int) alt
]);
1307 /* We cast to (int) because (char) hits bugs in some compilers. */
1308 reg_pref
[i
].prefclass
= (int) best
;
1309 reg_pref
[i
].altclass
= (int) alt
;
1313 #ifdef FORBIDDEN_INC_DEC_CLASSES
1316 #ifdef CLASS_CANNOT_CHANGE_MODE
1317 BITMAP_XFREE (reg_changes_mode
);
1322 /* Record the cost of using memory or registers of various classes for
1323 the operands in INSN.
1325 N_ALTS is the number of alternatives.
1327 N_OPS is the number of operands.
1329 OPS is an array of the operands.
1331 MODES are the modes of the operands, in case any are VOIDmode.
1333 CONSTRAINTS are the constraints to use for the operands. This array
1334 is modified by this procedure.
1336 This procedure works alternative by alternative. For each alternative
1337 we assume that we will be able to allocate all pseudos to their ideal
1338 register class and calculate the cost of using that alternative. Then
1339 we compute for each operand that is a pseudo-register, the cost of
1340 having the pseudo allocated to each register class and using it in that
1341 alternative. To this cost is added the cost of the alternative.
1343 The cost of each class for this insn is its lowest cost among all the
1347 record_reg_classes (n_alts
, n_ops
, ops
, modes
,
1348 constraints
, insn
, op_costs
, reg_pref
)
1352 enum machine_mode
*modes
;
1353 const char **constraints
;
1355 struct costs
*op_costs
;
1356 struct reg_pref
*reg_pref
;
1362 /* Process each alternative, each time minimizing an operand's cost with
1363 the cost for each operand in that alternative. */
1365 for (alt
= 0; alt
< n_alts
; alt
++)
1367 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1370 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1371 int allows_mem
[MAX_RECOG_OPERANDS
];
1374 for (i
= 0; i
< n_ops
; i
++)
1376 const char *p
= constraints
[i
];
1378 enum machine_mode mode
= modes
[i
];
1379 int allows_addr
= 0;
1383 /* Initially show we know nothing about the register class. */
1384 classes
[i
] = NO_REGS
;
1387 /* If this operand has no constraints at all, we can conclude
1388 nothing about it since anything is valid. */
1392 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1393 memset ((char *) &this_op_costs
[i
], 0, sizeof this_op_costs
[i
]);
1398 /* If this alternative is only relevant when this operand
1399 matches a previous operand, we do different things depending
1400 on whether this operand is a pseudo-reg or not. We must process
1401 any modifiers for the operand before we can make this test. */
1403 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1406 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1408 /* Copy class and whether memory is allowed from the matching
1409 alternative. Then perform any needed cost computations
1410 and/or adjustments. */
1412 classes
[i
] = classes
[j
];
1413 allows_mem
[i
] = allows_mem
[j
];
1415 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1417 /* If this matches the other operand, we have no added
1419 if (rtx_equal_p (ops
[j
], op
))
1422 /* If we can put the other operand into a register, add to
1423 the cost of this alternative the cost to copy this
1424 operand to the register used for the other operand. */
1426 else if (classes
[j
] != NO_REGS
)
1427 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1429 else if (GET_CODE (ops
[j
]) != REG
1430 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1432 /* This op is a pseudo but the one it matches is not. */
1434 /* If we can't put the other operand into a register, this
1435 alternative can't be used. */
1437 if (classes
[j
] == NO_REGS
)
1440 /* Otherwise, add to the cost of this alternative the cost
1441 to copy the other operand to the register used for this
1445 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1449 /* The costs of this operand are not the same as the other
1450 operand since move costs are not symmetric. Moreover,
1451 if we cannot tie them, this alternative needs to do a
1452 copy, which is one instruction. */
1454 struct costs
*pp
= &this_op_costs
[i
];
1456 for (class = 0; class < N_REG_CLASSES
; class++)
1458 = ((recog_data
.operand_type
[i
] != OP_OUT
1459 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1461 + (recog_data
.operand_type
[i
] != OP_IN
1462 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1465 /* If the alternative actually allows memory, make things
1466 a bit cheaper since we won't need an extra insn to
1470 = ((recog_data
.operand_type
[i
] != OP_IN
1471 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1473 + (recog_data
.operand_type
[i
] != OP_OUT
1474 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1475 : 0) - allows_mem
[i
]);
1477 /* If we have assigned a class to this register in our
1478 first pass, add a cost to this alternative corresponding
1479 to what we would add if this register were not in the
1480 appropriate class. */
1484 += (may_move_in_cost
[mode
]
1485 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1486 [(int) classes
[i
]]);
1488 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1489 && ! find_reg_note (insn
, REG_DEAD
, op
))
1492 /* This is in place of ordinary cost computation
1493 for this operand, so skip to the end of the
1494 alternative (should be just one character). */
1495 while (*p
&& *p
++ != ',')
1503 /* Scan all the constraint letters. See if the operand matches
1504 any of the constraints. Collect the valid register classes
1505 and see if this operand accepts memory. */
1507 while (*p
&& (c
= *p
++) != ',')
1511 /* Ignore the next letter for this pass. */
1517 case '!': case '#': case '&':
1518 case '0': case '1': case '2': case '3': case '4':
1519 case '5': case '6': case '7': case '8': case '9':
1524 win
= address_operand (op
, GET_MODE (op
));
1525 /* We know this operand is an address, so we want it to be
1526 allocated to a register that can be the base of an
1527 address, ie BASE_REG_CLASS. */
1529 = reg_class_subunion
[(int) classes
[i
]]
1530 [(int) BASE_REG_CLASS
];
1533 case 'm': case 'o': case 'V':
1534 /* It doesn't seem worth distinguishing between offsettable
1535 and non-offsettable addresses here. */
1537 if (GET_CODE (op
) == MEM
)
1542 if (GET_CODE (op
) == MEM
1543 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1544 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1549 if (GET_CODE (op
) == MEM
1550 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1551 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1556 #ifndef REAL_ARITHMETIC
1557 /* Match any floating double constant, but only if
1558 we can examine the bits of it reliably. */
1559 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1560 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1561 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1564 if (GET_CODE (op
) == CONST_DOUBLE
)
1569 if (GET_CODE (op
) == CONST_DOUBLE
)
1575 if (GET_CODE (op
) == CONST_DOUBLE
1576 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1581 if (GET_CODE (op
) == CONST_INT
1582 || (GET_CODE (op
) == CONST_DOUBLE
1583 && GET_MODE (op
) == VOIDmode
))
1587 #ifdef LEGITIMATE_PIC_OPERAND_P
1588 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1595 if (GET_CODE (op
) == CONST_INT
1596 || (GET_CODE (op
) == CONST_DOUBLE
1597 && GET_MODE (op
) == VOIDmode
))
1609 if (GET_CODE (op
) == CONST_INT
1610 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1619 if (GET_CODE (op
) == MEM
1621 #ifdef LEGITIMATE_PIC_OPERAND_P
1622 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1629 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1633 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1635 = reg_class_subunion
[(int) classes
[i
]]
1636 [(int) REG_CLASS_FROM_LETTER (c
)];
1637 #ifdef EXTRA_CONSTRAINT
1638 else if (EXTRA_CONSTRAINT (op
, c
))
1646 /* How we account for this operand now depends on whether it is a
1647 pseudo register or not. If it is, we first check if any
1648 register classes are valid. If not, we ignore this alternative,
1649 since we want to assume that all pseudos get allocated for
1650 register preferencing. If some register class is valid, compute
1651 the costs of moving the pseudo into that class. */
1653 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1655 if (classes
[i
] == NO_REGS
)
1657 /* We must always fail if the operand is a REG, but
1658 we did not find a suitable class.
1660 Otherwise we may perform an uninitialized read
1661 from this_op_costs after the `continue' statement
1667 struct costs
*pp
= &this_op_costs
[i
];
1669 for (class = 0; class < N_REG_CLASSES
; class++)
1671 = ((recog_data
.operand_type
[i
] != OP_OUT
1672 ? may_move_in_cost
[mode
][class][(int) classes
[i
]]
1674 + (recog_data
.operand_type
[i
] != OP_IN
1675 ? may_move_out_cost
[mode
][(int) classes
[i
]][class]
1678 /* If the alternative actually allows memory, make things
1679 a bit cheaper since we won't need an extra insn to
1683 = ((recog_data
.operand_type
[i
] != OP_IN
1684 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1686 + (recog_data
.operand_type
[i
] != OP_OUT
1687 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1688 : 0) - allows_mem
[i
]);
1690 /* If we have assigned a class to this register in our
1691 first pass, add a cost to this alternative corresponding
1692 to what we would add if this register were not in the
1693 appropriate class. */
1697 += (may_move_in_cost
[mode
]
1698 [(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1699 [(int) classes
[i
]]);
1703 /* Otherwise, if this alternative wins, either because we
1704 have already determined that or if we have a hard register of
1705 the proper class, there is no cost for this alternative. */
1708 || (GET_CODE (op
) == REG
1709 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1712 /* If registers are valid, the cost of this alternative includes
1713 copying the object to and/or from a register. */
1715 else if (classes
[i
] != NO_REGS
)
1717 if (recog_data
.operand_type
[i
] != OP_OUT
)
1718 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1720 if (recog_data
.operand_type
[i
] != OP_IN
)
1721 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1724 /* The only other way this alternative can be used is if this is a
1725 constant that could be placed into memory. */
1727 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1728 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1736 /* Finally, update the costs with the information we've calculated
1737 about this alternative. */
1739 for (i
= 0; i
< n_ops
; i
++)
1740 if (GET_CODE (ops
[i
]) == REG
1741 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1743 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1744 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1746 pp
->mem_cost
= MIN (pp
->mem_cost
,
1747 (qq
->mem_cost
+ alt_cost
) * scale
);
1749 for (class = 0; class < N_REG_CLASSES
; class++)
1750 pp
->cost
[class] = MIN (pp
->cost
[class],
1751 (qq
->cost
[class] + alt_cost
) * scale
);
1755 /* If this insn is a single set copying operand 1 to operand 0
1756 and one operand is a pseudo with the other a hard reg or a pseudo
1757 that prefers a register that is in its own register class then
1758 we may want to adjust the cost of that register class to -1.
1760 Avoid the adjustment if the source does not die to avoid stressing of
1761 register allocator by preferrencing two coliding registers into single
1764 Also avoid the adjustment if a copy between registers of the class
1765 is expensive (ten times the cost of a default copy is considered
1766 arbitrarily expensive). This avoids losing when the preferred class
1767 is very expensive as the source of a copy instruction. */
1769 if ((set
= single_set (insn
)) != 0
1770 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1771 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1772 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1773 for (i
= 0; i
<= 1; i
++)
1774 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1776 unsigned int regno
= REGNO (ops
[!i
]);
1777 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1781 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1783 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1785 if ((reg_class_size
[(unsigned char) pref
]
1786 == CLASS_MAX_NREGS (pref
, mode
))
1787 && REGISTER_MOVE_COST (mode
, pref
, pref
) < 10 * 2)
1788 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1790 else if (regno
< FIRST_PSEUDO_REGISTER
)
1791 for (class = 0; class < N_REG_CLASSES
; class++)
1792 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1793 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1795 if (reg_class_size
[class] == 1)
1796 op_costs
[i
].cost
[class] = -1;
1799 for (nr
= 0; nr
< HARD_REGNO_NREGS (regno
, mode
); nr
++)
1801 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1806 if (nr
== HARD_REGNO_NREGS (regno
,mode
))
1807 op_costs
[i
].cost
[class] = -1;
1813 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1814 TO_P is zero) a register of class CLASS in mode MODE.
1816 X must not be a pseudo. */
1819 copy_cost (x
, mode
, class, to_p
)
1821 enum machine_mode mode ATTRIBUTE_UNUSED
;
1822 enum reg_class
class;
1823 int to_p ATTRIBUTE_UNUSED
;
1825 #ifdef HAVE_SECONDARY_RELOADS
1826 enum reg_class secondary_class
= NO_REGS
;
1829 /* If X is a SCRATCH, there is actually nothing to move since we are
1830 assuming optimal allocation. */
1832 if (GET_CODE (x
) == SCRATCH
)
1835 /* Get the class we will actually use for a reload. */
1836 class = PREFERRED_RELOAD_CLASS (x
, class);
1838 #ifdef HAVE_SECONDARY_RELOADS
1839 /* If we need a secondary reload (we assume here that we are using
1840 the secondary reload as an intermediate, not a scratch register), the
1841 cost is that to load the input into the intermediate register, then
1842 to copy them. We use a special value of TO_P to avoid recursion. */
1844 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1846 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1849 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1851 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1854 if (secondary_class
!= NO_REGS
)
1855 return (move_cost
[mode
][(int) secondary_class
][(int) class]
1856 + copy_cost (x
, mode
, secondary_class
, 2));
1857 #endif /* HAVE_SECONDARY_RELOADS */
1859 /* For memory, use the memory move cost, for (hard) registers, use the
1860 cost to move between the register classes, and use 2 for everything
1861 else (constants). */
1863 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1864 return MEMORY_MOVE_COST (mode
, class, to_p
);
1866 else if (GET_CODE (x
) == REG
)
1867 return move_cost
[mode
][(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1870 /* If this is a constant, we may eventually want to call rtx_cost here. */
1871 return COSTS_N_INSNS (1);
1874 /* Record the pseudo registers we must reload into hard registers
1875 in a subexpression of a memory address, X.
1877 CLASS is the class that the register needs to be in and is either
1878 BASE_REG_CLASS or INDEX_REG_CLASS.
1880 SCALE is twice the amount to multiply the cost by (it is twice so we
1881 can represent half-cost adjustments). */
1884 record_address_regs (x
, class, scale
)
1886 enum reg_class
class;
1889 register enum rtx_code code
= GET_CODE (x
);
1902 /* When we have an address that is a sum,
1903 we must determine whether registers are "base" or "index" regs.
1904 If there is a sum of two registers, we must choose one to be
1905 the "base". Luckily, we can use the REG_POINTER to make a good
1906 choice most of the time. We only need to do this on machines
1907 that can have two registers in an address and where the base
1908 and index register classes are different.
1910 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1911 that seems bogus since it should only be set when we are sure
1912 the register is being used as a pointer. */
1915 rtx arg0
= XEXP (x
, 0);
1916 rtx arg1
= XEXP (x
, 1);
1917 register enum rtx_code code0
= GET_CODE (arg0
);
1918 register enum rtx_code code1
= GET_CODE (arg1
);
1920 /* Look inside subregs. */
1921 if (code0
== SUBREG
)
1922 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1923 if (code1
== SUBREG
)
1924 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1926 /* If this machine only allows one register per address, it must
1927 be in the first operand. */
1929 if (MAX_REGS_PER_ADDRESS
== 1)
1930 record_address_regs (arg0
, class, scale
);
1932 /* If index and base registers are the same on this machine, just
1933 record registers in any non-constant operands. We assume here,
1934 as well as in the tests below, that all addresses are in
1937 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1939 record_address_regs (arg0
, class, scale
);
1940 if (! CONSTANT_P (arg1
))
1941 record_address_regs (arg1
, class, scale
);
1944 /* If the second operand is a constant integer, it doesn't change
1945 what class the first operand must be. */
1947 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1948 record_address_regs (arg0
, class, scale
);
1950 /* If the second operand is a symbolic constant, the first operand
1951 must be an index register. */
1953 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1954 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1956 /* If both operands are registers but one is already a hard register
1957 of index or base class, give the other the class that the hard
1960 #ifdef REG_OK_FOR_BASE_P
1961 else if (code0
== REG
&& code1
== REG
1962 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1963 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1964 record_address_regs (arg1
,
1965 REG_OK_FOR_BASE_P (arg0
)
1966 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1968 else if (code0
== REG
&& code1
== REG
1969 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1970 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1971 record_address_regs (arg0
,
1972 REG_OK_FOR_BASE_P (arg1
)
1973 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1977 /* If one operand is known to be a pointer, it must be the base
1978 with the other operand the index. Likewise if the other operand
1981 else if ((code0
== REG
&& REG_POINTER (arg0
))
1984 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1985 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1987 else if ((code1
== REG
&& REG_POINTER (arg1
))
1990 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1991 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1994 /* Otherwise, count equal chances that each might be a base
1995 or index register. This case should be rare. */
1999 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
2000 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
2001 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
2002 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
2007 /* Double the importance of a pseudo register that is incremented
2008 or decremented, since it would take two extra insns
2009 if it ends up in the wrong place. */
2012 record_address_regs (XEXP (x
, 0), BASE_REG_CLASS
, 2 * scale
);
2013 if (REG_P (XEXP (XEXP (x
, 1), 1)))
2014 record_address_regs (XEXP (XEXP (x
, 1), 1),
2015 INDEX_REG_CLASS
, 2 * scale
);
2022 /* Double the importance of a pseudo register that is incremented
2023 or decremented, since it would take two extra insns
2024 if it ends up in the wrong place. If the operand is a pseudo,
2025 show it is being used in an INC_DEC context. */
2027 #ifdef FORBIDDEN_INC_DEC_CLASSES
2028 if (GET_CODE (XEXP (x
, 0)) == REG
2029 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
2030 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
2033 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
2038 register struct costs
*pp
= &costs
[REGNO (x
)];
2041 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
2043 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2044 pp
->cost
[i
] += (may_move_in_cost
[Pmode
][i
][(int) class] * scale
) / 2;
2050 register const char *fmt
= GET_RTX_FORMAT (code
);
2052 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2054 record_address_regs (XEXP (x
, i
), class, scale
);
2059 #ifdef FORBIDDEN_INC_DEC_CLASSES
2061 /* Return 1 if REG is valid as an auto-increment memory reference
2062 to an object of MODE. */
2065 auto_inc_dec_reg_p (reg
, mode
)
2067 enum machine_mode mode
;
2069 if (HAVE_POST_INCREMENT
2070 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
2073 if (HAVE_POST_DECREMENT
2074 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
2077 if (HAVE_PRE_INCREMENT
2078 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
2081 if (HAVE_PRE_DECREMENT
2082 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
2089 static short *renumber
;
2090 static size_t regno_allocated
;
2091 static unsigned int reg_n_max
;
2093 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2094 reg_scan and flow_analysis that are indexed by the register number. If
2095 NEW_P is non zero, initialize all of the registers, otherwise only
2096 initialize the new registers allocated. The same table is kept from
2097 function to function, only reallocating it when we need more room. If
2098 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2101 allocate_reg_info (num_regs
, new_p
, renumber_p
)
2107 size_t size_renumber
;
2108 size_t min
= (new_p
) ? 0 : reg_n_max
;
2109 struct reg_info_data
*reg_data
;
2111 if (num_regs
> regno_allocated
)
2113 size_t old_allocated
= regno_allocated
;
2115 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
2116 size_renumber
= regno_allocated
* sizeof (short);
2120 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2121 renumber
= (short *) xmalloc (size_renumber
);
2122 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2123 * sizeof (struct reg_pref
));
2128 VARRAY_GROW (reg_n_info
, regno_allocated
);
2130 if (new_p
) /* if we're zapping everything, no need to realloc */
2132 free ((char *)renumber
);
2133 free ((char *)reg_pref
);
2134 renumber
= (short *) xmalloc (size_renumber
);
2135 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2136 * sizeof (struct reg_pref
));
2141 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
2142 reg_pref_buffer
= (struct reg_pref
*) xrealloc ((char *)reg_pref_buffer
,
2144 * sizeof (struct reg_pref
));
2148 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2149 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2150 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
2151 reg_data
->min_index
= old_allocated
;
2152 reg_data
->max_index
= regno_allocated
- 1;
2153 reg_data
->next
= reg_info_head
;
2154 reg_info_head
= reg_data
;
2157 reg_n_max
= num_regs
;
2160 /* Loop through each of the segments allocated for the actual
2161 reg_info pages, and set up the pointers, zero the pages, etc. */
2162 for (reg_data
= reg_info_head
;
2163 reg_data
&& reg_data
->max_index
>= min
;
2164 reg_data
= reg_data
->next
)
2166 size_t min_index
= reg_data
->min_index
;
2167 size_t max_index
= reg_data
->max_index
;
2168 size_t max
= MIN (max_index
, num_regs
);
2169 size_t local_min
= min
- min_index
;
2172 if (reg_data
->min_index
> num_regs
)
2175 if (min
< min_index
)
2177 if (!reg_data
->used_p
) /* page just allocated with calloc */
2178 reg_data
->used_p
= 1; /* no need to zero */
2180 memset ((char *) ®_data
->data
[local_min
], 0,
2181 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2183 for (i
= min_index
+local_min
; i
<= max
; i
++)
2185 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2186 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2188 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2189 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2194 /* If {pref,alt}class have already been allocated, update the pointers to
2195 the newly realloced ones. */
2197 reg_pref
= reg_pref_buffer
;
2200 reg_renumber
= renumber
;
2202 /* Tell the regset code about the new number of registers */
2203 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2206 /* Free up the space allocated by allocate_reg_info. */
2212 struct reg_info_data
*reg_data
;
2213 struct reg_info_data
*reg_next
;
2215 VARRAY_FREE (reg_n_info
);
2216 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2218 reg_next
= reg_data
->next
;
2219 free ((char *)reg_data
);
2222 free (reg_pref_buffer
);
2223 reg_pref_buffer
= (struct reg_pref
*)0;
2224 reg_info_head
= (struct reg_info_data
*)0;
2225 renumber
= (short *)0;
2227 regno_allocated
= 0;
2231 /* This is the `regscan' pass of the compiler, run just before cse
2232 and again just before loop.
2234 It finds the first and last use of each pseudo-register
2235 and records them in the vectors regno_first_uid, regno_last_uid
2236 and counts the number of sets in the vector reg_n_sets.
2238 REPEAT is nonzero the second time this is called. */
2240 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2241 Always at least 3, since the combiner could put that many together
2242 and we want this to remain correct for all the remaining passes.
2243 This corresponds to the maximum number of times note_stores will call
2244 a function for any insn. */
2248 /* Used as a temporary to record the largest number of registers in
2249 PARALLEL in a SET_DEST. This is added to max_parallel. */
2251 static int max_set_parallel
;
2254 reg_scan (f
, nregs
, repeat
)
2257 int repeat ATTRIBUTE_UNUSED
;
2261 allocate_reg_info (nregs
, TRUE
, FALSE
);
2263 max_set_parallel
= 0;
2265 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2266 if (GET_CODE (insn
) == INSN
2267 || GET_CODE (insn
) == CALL_INSN
2268 || GET_CODE (insn
) == JUMP_INSN
)
2270 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2271 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2272 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2273 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
2275 if (REG_NOTES (insn
))
2276 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2279 max_parallel
+= max_set_parallel
;
2282 /* Update 'regscan' information by looking at the insns
2283 from FIRST to LAST. Some new REGs have been created,
2284 and any REG with number greater than OLD_MAX_REGNO is
2285 such a REG. We only update information for those. */
2288 reg_scan_update (first
, last
, old_max_regno
)
2291 unsigned int old_max_regno
;
2295 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2297 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2298 if (GET_CODE (insn
) == INSN
2299 || GET_CODE (insn
) == CALL_INSN
2300 || GET_CODE (insn
) == JUMP_INSN
)
2302 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2303 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2304 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2305 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
2307 if (REG_NOTES (insn
))
2308 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2312 /* X is the expression to scan. INSN is the insn it appears in.
2313 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2314 We should only record information for REGs with numbers
2315 greater than or equal to MIN_REGNO. */
2318 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2322 unsigned int min_regno
;
2324 register enum rtx_code code
;
2328 code
= GET_CODE (x
);
2344 unsigned int regno
= REGNO (x
);
2346 if (regno
>= min_regno
)
2348 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2350 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2351 if (REGNO_FIRST_UID (regno
) == 0)
2352 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2359 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2361 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2366 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2370 /* Count a set of the destination if it is a register. */
2371 for (dest
= SET_DEST (x
);
2372 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2373 || GET_CODE (dest
) == ZERO_EXTEND
;
2374 dest
= XEXP (dest
, 0))
2377 /* For a PARALLEL, record the number of things (less the usual one for a
2378 SET) that are set. */
2379 if (GET_CODE (dest
) == PARALLEL
)
2380 max_set_parallel
= MAX (max_set_parallel
, XVECLEN (dest
, 0) - 1);
2382 if (GET_CODE (dest
) == REG
2383 && REGNO (dest
) >= min_regno
)
2384 REG_N_SETS (REGNO (dest
))++;
2386 /* If this is setting a pseudo from another pseudo or the sum of a
2387 pseudo and a constant integer and the other pseudo is known to be
2388 a pointer, set the destination to be a pointer as well.
2390 Likewise if it is setting the destination from an address or from a
2391 value equivalent to an address or to the sum of an address and
2394 But don't do any of this if the pseudo corresponds to a user
2395 variable since it should have already been set as a pointer based
2398 if (GET_CODE (SET_DEST (x
)) == REG
2399 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2400 && REGNO (SET_DEST (x
)) >= min_regno
2401 /* If the destination pseudo is set more than once, then other
2402 sets might not be to a pointer value (consider access to a
2403 union in two threads of control in the presense of global
2404 optimizations). So only set REG_POINTER on the destination
2405 pseudo if this is the only set of that pseudo. */
2406 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2407 && ! REG_USERVAR_P (SET_DEST (x
))
2408 && ! REG_POINTER (SET_DEST (x
))
2409 && ((GET_CODE (SET_SRC (x
)) == REG
2410 && REG_POINTER (SET_SRC (x
)))
2411 || ((GET_CODE (SET_SRC (x
)) == PLUS
2412 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2413 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2414 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2415 && REG_POINTER (XEXP (SET_SRC (x
), 0)))
2416 || GET_CODE (SET_SRC (x
)) == CONST
2417 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2418 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2419 || (GET_CODE (SET_SRC (x
)) == HIGH
2420 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2421 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2422 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2423 || ((GET_CODE (SET_SRC (x
)) == PLUS
2424 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2425 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2426 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2427 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2428 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2429 && (GET_CODE (XEXP (note
, 0)) == CONST
2430 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2431 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2432 REG_POINTER (SET_DEST (x
)) = 1;
2434 /* ... fall through ... */
2438 register const char *fmt
= GET_RTX_FORMAT (code
);
2440 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2443 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2444 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2447 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2448 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2455 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2459 reg_class_subset_p (c1
, c2
)
2460 register enum reg_class c1
;
2461 register enum reg_class c2
;
2463 if (c1
== c2
) return 1;
2468 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2469 reg_class_contents
[(int)c2
],
2474 /* Return nonzero if there is a register that is in both C1 and C2. */
2477 reg_classes_intersect_p (c1
, c2
)
2478 register enum reg_class c1
;
2479 register enum reg_class c2
;
2486 if (c1
== c2
) return 1;
2488 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2491 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2492 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2494 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2501 /* Release any memory allocated by register sets. */
2504 regset_release_memory ()
2506 bitmap_release_memory ();